Farnell PDF TEXAS INSTRUMENTS - LM3S6110 Microcontroller - Farnell Element 14

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Branding Farnell element14 (France)

 

Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Recherche intégrée

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

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Voltage Level Translation

Puce électronique / Microchip :

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Raspberry Pi board B product overview

Logiciels :

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Introduction to Cadsoft EAGLE PCB Design Software in Chinese

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Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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Ben's Autodesk 123D Tutorial Trailer

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Ben's CadSoft EAGLE Tutorial Trailer

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Ben Heck's Soldering Tutorial Trailer

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Ben Heck's AVR Dev Board tutorial

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Ben Heck's Pinball Tutorial Trailer

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Ben Heck's Interface Tutorial Trailer

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First Stage with Python and PiFace Digital

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Cypress - Getting Started with PSoC® 3 - Part 2

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

Autres documentations :

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LM3S6110 Microcontroller DATA SHEET DS-LM3S6110-1972 Copyright © 2007 Luminary Micro, Inc. PRELIMINARY Legal Disclaimers and Trademark Information INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS. Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office or your distributor to obtain the latest specifications before placing your product order. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Copyright © 2007 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Luminary Micro, Inc. 108 Wild Basin, Suite 350 Austin, TX 78746 Main: +1-512-279-8800 Fax: +1-512-279-8879 http://www.luminarymicro.com 2 November 30, 2007 Preliminary Table of Contents About This Document .................................................................................................................... 17 Audience .............................................................................................................................................. 17 About This Manual ................................................................................................................................ 17 Related Documents ............................................................................................................................... 17 Documentation Conventions .................................................................................................................. 17 1 Architectural Overview ...................................................................................................... 19 1.1 Product Features ...................................................................................................................... 19 1.2 Target Applications .................................................................................................................... 24 1.3 High-Level Block Diagram ......................................................................................................... 24 1.4 Functional Overview .................................................................................................................. 25 1.4.1 ARM Cortex™-M3 ..................................................................................................................... 26 1.4.2 Motor Control Peripherals .......................................................................................................... 26 1.4.3 Analog Peripherals .................................................................................................................... 27 1.4.4 Serial Communications Peripherals ............................................................................................ 27 1.4.5 System Peripherals ................................................................................................................... 28 1.4.6 Memory Peripherals .................................................................................................................. 29 1.4.7 Additional Features ................................................................................................................... 30 1.4.8 Hardware Details ...................................................................................................................... 30 2 ARM Cortex-M3 Processor Core ...................................................................................... 31 2.1 Block Diagram .......................................................................................................................... 32 2.2 Functional Description ............................................................................................................... 32 2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 32 2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 33 2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 33 2.2.4 ROM Table ............................................................................................................................... 33 2.2.5 Memory Protection Unit (MPU) ................................................................................................... 33 2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 33 3 Memory Map ....................................................................................................................... 37 4 Interrupts ............................................................................................................................ 39 5 JTAG Interface .................................................................................................................... 41 5.1 Block Diagram .......................................................................................................................... 42 5.2 Functional Description ............................................................................................................... 42 5.2.1 JTAG Interface Pins .................................................................................................................. 43 5.2.2 JTAG TAP Controller ................................................................................................................. 44 5.2.3 Shift Registers .......................................................................................................................... 45 5.2.4 Operational Considerations ........................................................................................................ 45 5.3 Initialization and Configuration ................................................................................................... 48 5.4 Register Descriptions ................................................................................................................ 48 5.4.1 Instruction Register (IR) ............................................................................................................. 48 5.4.2 Data Registers .......................................................................................................................... 50 6 System Control ................................................................................................................... 52 6.1 Functional Description ............................................................................................................... 52 6.1.1 Device Identification .................................................................................................................. 52 6.1.2 Reset Control ............................................................................................................................ 52 November 30, 2007 3 Preliminary LM3S6110 Microcontroller 6.1.3 Power Control ........................................................................................................................... 55 6.1.4 Clock Control ............................................................................................................................ 55 6.1.5 System Control ......................................................................................................................... 57 6.2 Initialization and Configuration ................................................................................................... 57 6.3 Register Map ............................................................................................................................ 58 6.4 Register Descriptions ................................................................................................................ 59 7 Internal Memory ............................................................................................................... 107 7.1 Block Diagram ........................................................................................................................ 107 7.2 Functional Description ............................................................................................................. 107 7.2.1 SRAM Memory ........................................................................................................................ 107 7.2.2 Flash Memory ......................................................................................................................... 108 7.3 Flash Memory Initialization and Configuration ........................................................................... 109 7.3.1 Flash Programming ................................................................................................................. 109 7.3.2 Nonvolatile Register Programming ........................................................................................... 110 7.4 Register Map .......................................................................................................................... 110 7.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 111 7.6 Flash Register Descriptions (System Control Offset) .................................................................. 118 8 General-Purpose Input/Outputs (GPIOs) ....................................................................... 131 8.1 Functional Description ............................................................................................................. 131 8.1.1 Data Control ........................................................................................................................... 132 8.1.2 Interrupt Control ...................................................................................................................... 133 8.1.3 Mode Control .......................................................................................................................... 134 8.1.4 Commit Control ....................................................................................................................... 134 8.1.5 Pad Control ............................................................................................................................. 134 8.1.6 Identification ........................................................................................................................... 134 8.2 Initialization and Configuration ................................................................................................. 134 8.3 Register Map .......................................................................................................................... 135 8.4 Register Descriptions .............................................................................................................. 137 9 General-Purpose Timers ................................................................................................. 172 9.1 Block Diagram ........................................................................................................................ 172 9.2 Functional Description ............................................................................................................. 173 9.2.1 GPTM Reset Conditions .......................................................................................................... 173 9.2.2 32-Bit Timer Operating Modes .................................................................................................. 174 9.2.3 16-Bit Timer Operating Modes .................................................................................................. 175 9.3 Initialization and Configuration ................................................................................................. 179 9.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 179 9.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 180 9.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 180 9.3.4 16-Bit Input Edge Count Mode ................................................................................................. 181 9.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 181 9.3.6 16-Bit PWM Mode ................................................................................................................... 182 9.4 Register Map .......................................................................................................................... 182 9.5 Register Descriptions .............................................................................................................. 183 10 Watchdog Timer ............................................................................................................... 208 10.1 Block Diagram ........................................................................................................................ 208 10.2 Functional Description ............................................................................................................. 208 10.3 Initialization and Configuration ................................................................................................. 209 4 November 30, 2007 Preliminary Table of Contents 10.4 Register Map .......................................................................................................................... 209 10.5 Register Descriptions .............................................................................................................. 210 11 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 231 11.1 Block Diagram ........................................................................................................................ 232 11.2 Functional Description ............................................................................................................. 232 11.2.1 Transmit/Receive Logic ........................................................................................................... 232 11.2.2 Baud-Rate Generation ............................................................................................................. 233 11.2.3 Data Transmission .................................................................................................................. 234 11.2.4 Serial IR (SIR) ......................................................................................................................... 234 11.2.5 FIFO Operation ....................................................................................................................... 235 11.2.6 Interrupts ................................................................................................................................ 235 11.2.7 Loopback Operation ................................................................................................................ 236 11.2.8 IrDA SIR block ........................................................................................................................ 236 11.3 Initialization and Configuration ................................................................................................. 236 11.4 Register Map .......................................................................................................................... 237 11.5 Register Descriptions .............................................................................................................. 238 12 Synchronous Serial Interface (SSI) ................................................................................ 272 12.1 Block Diagram ........................................................................................................................ 272 12.2 Functional Description ............................................................................................................. 272 12.2.1 Bit Rate Generation ................................................................................................................. 273 12.2.2 FIFO Operation ....................................................................................................................... 273 12.2.3 Interrupts ................................................................................................................................ 273 12.2.4 Frame Formats ....................................................................................................................... 274 12.3 Initialization and Configuration ................................................................................................. 281 12.4 Register Map .......................................................................................................................... 282 12.5 Register Descriptions .............................................................................................................. 283 13 Ethernet Controller .......................................................................................................... 309 13.1 Block Diagram ........................................................................................................................ 310 13.2 Functional Description ............................................................................................................. 310 13.2.1 Internal MII Operation .............................................................................................................. 310 13.2.2 PHY Configuration/Operation ................................................................................................... 311 13.2.3 MAC Configuration/Operation .................................................................................................. 312 13.2.4 Interrupts ................................................................................................................................ 314 13.3 Initialization and Configuration ................................................................................................. 315 13.4 Ethernet Register Map ............................................................................................................. 315 13.5 Ethernet MAC Register Descriptions ......................................................................................... 317 13.6 MII Management Register Descriptions ..................................................................................... 334 14 Analog Comparators ....................................................................................................... 353 14.1 Block Diagram ........................................................................................................................ 354 14.2 Functional Description ............................................................................................................. 354 14.2.1 Internal Reference Programming .............................................................................................. 356 14.3 Initialization and Configuration ................................................................................................. 357 14.4 Register Map .......................................................................................................................... 357 14.5 Register Descriptions .............................................................................................................. 358 15 Pulse Width Modulator (PWM) ........................................................................................ 366 15.1 Block Diagram ........................................................................................................................ 366 15.2 Functional Description ............................................................................................................. 366 November 30, 2007 5 Preliminary LM3S6110 Microcontroller 15.2.1 PWM Timer ............................................................................................................................. 366 15.2.2 PWM Comparators .................................................................................................................. 367 15.2.3 PWM Signal Generator ............................................................................................................ 368 15.2.4 Dead-Band Generator ............................................................................................................. 369 15.2.5 Interrupt Selector ..................................................................................................................... 369 15.2.6 Synchronization Methods ......................................................................................................... 369 15.2.7 Fault Conditions ...................................................................................................................... 369 15.2.8 Output Control Block ............................................................................................................... 370 15.3 Initialization and Configuration ................................................................................................. 370 15.4 Register Map .......................................................................................................................... 371 15.5 Register Descriptions .............................................................................................................. 372 16 Pin Diagram ...................................................................................................................... 401 17 Signal Tables .................................................................................................................... 402 18 Operating Characteristics ............................................................................................... 414 19 Electrical Characteristics ................................................................................................ 415 19.1 DC Characteristics .................................................................................................................. 415 19.1.1 Maximum Ratings ................................................................................................................... 415 19.1.2 Recommended DC Operating Conditions .................................................................................. 415 19.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 416 19.1.4 Power Specifications ............................................................................................................... 416 19.1.5 Flash Memory Characteristics .................................................................................................. 417 19.2 AC Characteristics ................................................................................................................... 418 19.2.1 Load Conditions ...................................................................................................................... 418 19.2.2 Clocks .................................................................................................................................... 418 19.2.3 Analog Comparator ................................................................................................................. 419 19.2.4 Ethernet Controller .................................................................................................................. 419 19.2.5 Synchronous Serial Interface (SSI) ........................................................................................... 422 19.2.6 JTAG and Boundary Scan ........................................................................................................ 424 19.2.7 General-Purpose I/O ............................................................................................................... 425 19.2.8 Reset ..................................................................................................................................... 426 20 Package Information ........................................................................................................ 428 A Serial Flash Loader .......................................................................................................... 430 A.1 Serial Flash Loader ................................................................................................................. 430 A.2 Interfaces ............................................................................................................................... 430 A.2.1 UART ..................................................................................................................................... 430 A.2.2 SSI ......................................................................................................................................... 430 A.3 Packet Handling ...................................................................................................................... 431 A.3.1 Packet Format ........................................................................................................................ 431 A.3.2 Sending Packets ..................................................................................................................... 431 A.3.3 Receiving Packets ................................................................................................................... 431 A.4 Commands ............................................................................................................................. 432 A.4.1 COMMAND_PING (0X20) ........................................................................................................ 432 A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 432 A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 432 A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 433 A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 433 A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 433 6 November 30, 2007 Preliminary Table of Contents B Register Quick Reference ............................................................................................... 435 C Ordering and Contact Information ................................................................................. 449 C.1 Ordering Information ................................................................................................................ 449 C.2 Kits ......................................................................................................................................... 449 C.3 Company Information .............................................................................................................. 449 C.4 Support Information ................................................................................................................. 450 November 30, 2007 7 Preliminary LM3S6110 Microcontroller List of Figures Figure 1-1. Stellaris® 6000 Series High-Level Block Diagram ............................................................... 25 Figure 2-1. CPU Block Diagram ......................................................................................................... 32 Figure 2-2. TPIU Block Diagram ........................................................................................................ 33 Figure 5-1. JTAG Module Block Diagram ............................................................................................ 42 Figure 5-2. Test Access Port State Machine ....................................................................................... 45 Figure 5-3. IDCODE Register Format ................................................................................................. 50 Figure 5-4. BYPASS Register Format ................................................................................................ 51 Figure 5-5. Boundary Scan Register Format ....................................................................................... 51 Figure 6-1. External Circuitry to Extend Reset .................................................................................... 53 Figure 7-1. Flash Block Diagram ...................................................................................................... 107 Figure 8-1. GPIO Port Block Diagram ............................................................................................... 132 Figure 8-2. GPIODATA Write Example ............................................................................................. 133 Figure 8-3. GPIODATA Read Example ............................................................................................. 133 Figure 9-1. GPTM Module Block Diagram ........................................................................................ 173 Figure 9-2. 16-Bit Input Edge Count Mode Example .......................................................................... 177 Figure 9-3. 16-Bit Input Edge Time Mode Example ........................................................................... 178 Figure 9-4. 16-Bit PWM Mode Example ............................................................................................ 179 Figure 10-1. WDT Module Block Diagram .......................................................................................... 208 Figure 11-1. UART Module Block Diagram ......................................................................................... 232 Figure 11-2. UART Character Frame ................................................................................................. 233 Figure 11-3. IrDA Data Modulation ..................................................................................................... 235 Figure 12-1. SSI Module Block Diagram ............................................................................................. 272 Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 275 Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 275 Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 276 Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 276 Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 277 Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 278 Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 278 Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 279 Figure 12-10. MICROWIRE Frame Format (Single Frame) .................................................................... 280 Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 281 Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 281 Figure 13-1. Ethernet Controller Block Diagram .................................................................................. 310 Figure 13-2. Ethernet Controller ......................................................................................................... 310 Figure 13-3. Ethernet Frame ............................................................................................................. 312 Figure 14-1. Analog Comparator Module Block Diagram ..................................................................... 354 Figure 14-2. Structure of Comparator Unit .......................................................................................... 355 Figure 14-3. Comparator Internal Reference Structure ........................................................................ 356 Figure 15-1. PWM Module Block Diagram .......................................................................................... 366 Figure 15-2. PWM Count-Down Mode ................................................................................................ 367 Figure 15-3. PWM Count-Up/Down Mode .......................................................................................... 368 Figure 15-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 368 Figure 15-5. PWM Dead-Band Generator ........................................................................................... 369 Figure 16-1. Pin Connection Diagram ................................................................................................ 401 Figure 19-1. Load Conditions ............................................................................................................ 418 8 November 30, 2007 Preliminary Table of Contents Figure 19-2. External XTLP Oscillator Characteristics ......................................................................... 422 Figure 19-3. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 423 Figure 19-4. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 423 Figure 19-5. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 424 Figure 19-6. JTAG Test Clock Input Timing ......................................................................................... 425 Figure 19-7. JTAG Test Access Port (TAP) Timing .............................................................................. 425 Figure 19-8. JTAG TRST Timing ........................................................................................................ 425 Figure 19-9. External Reset Timing (RST) .......................................................................................... 426 Figure 19-10. Power-On Reset Timing ................................................................................................. 427 Figure 19-11. Brown-Out Reset Timing ................................................................................................ 427 Figure 19-12. Software Reset Timing ................................................................................................... 427 Figure 19-13. Watchdog Reset Timing ................................................................................................. 427 Figure 20-1. 100-Pin LQFP Package .................................................................................................. 428 November 30, 2007 9 Preliminary LM3S6110 Microcontroller List of Tables Table 1. Documentation Conventions ............................................................................................ 17 Table 3-1. Memory Map ................................................................................................................... 37 Table 4-1. Exception Types .............................................................................................................. 39 Table 4-2. Interrupts ........................................................................................................................ 40 Table 5-1. JTAG Port Pins Reset State ............................................................................................. 43 Table 5-2. JTAG Instruction Register Commands ............................................................................... 48 Table 6-1. System Control Register Map ........................................................................................... 58 Table 7-1. Flash Protection Policy Combinations ............................................................................. 109 Table 7-2. Flash Resident Registers ............................................................................................... 110 Table 7-3. Flash Register Map ........................................................................................................ 110 Table 8-1. GPIO Pad Configuration Examples ................................................................................. 134 Table 8-2. GPIO Interrupt Configuration Example ............................................................................ 135 Table 8-3. GPIO Register Map ....................................................................................................... 136 Table 9-1. Available CCP Pins ........................................................................................................ 173 Table 9-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 176 Table 9-3. Timers Register Map ...................................................................................................... 182 Table 10-1. Watchdog Timer Register Map ........................................................................................ 209 Table 11-1. UART Register Map ....................................................................................................... 237 Table 12-1. SSI Register Map .......................................................................................................... 282 Table 13-1. TX & RX FIFO Organization ........................................................................................... 313 Table 13-2. Ethernet Register Map ................................................................................................... 316 Table 14-1. Comparator 0 Operating Modes ...................................................................................... 355 Table 14-2. Comparator 1 Operating Modes ..................................................................................... 355 Table 14-3. Comparator 2 Operating Modes ...................................................................................... 356 Table 14-4. Internal Reference Voltage and ACREFCTL Field Values ................................................. 356 Table 14-5. Analog Comparators Register Map ................................................................................. 358 Table 15-1. PWM Register Map ........................................................................................................ 371 Table 17-1. Signals by Pin Number ................................................................................................... 402 Table 17-2. Signals by Signal Name ................................................................................................. 406 Table 17-3. Signals by Function, Except for GPIO ............................................................................. 409 Table 17-4. GPIO Pins and Alternate Functions ................................................................................. 412 Table 18-1. Temperature Characteristics ........................................................................................... 414 Table 18-2. Thermal Characteristics ................................................................................................. 414 Table 19-1. Maximum Ratings .......................................................................................................... 415 Table 19-2. Recommended DC Operating Conditions ........................................................................ 415 Table 19-3. LDO Regulator Characteristics ....................................................................................... 416 Table 19-4. Detailed Power Specifications ........................................................................................ 417 Table 19-5. Flash Memory Characteristics ........................................................................................ 417 Table 19-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 418 Table 19-7. Clock Characteristics ..................................................................................................... 418 Table 19-8. Crystal Characteristics ................................................................................................... 418 Table 19-9. Analog Comparator Characteristics ................................................................................. 419 Table 19-10. Analog Comparator Voltage Reference Characteristics .................................................... 419 Table 19-11. 100BASE-TX Transmitter Characteristics ........................................................................ 419 Table 19-12. 100BASE-TX Transmitter Characteristics (informative) ..................................................... 419 Table 19-13. 100BASE-TX Receiver Characteristics ............................................................................ 420 10 November 30, 2007 Preliminary Table of Contents Table 19-14. 10BASE-T Transmitter Characteristics ............................................................................ 420 Table 19-15. 10BASE-T Transmitter Characteristics (informative) ......................................................... 420 Table 19-16. 10BASE-T Receiver Characteristics ................................................................................ 420 Table 19-17. Isolation Transformers ................................................................................................... 420 Table 19-18. Ethernet Reference Crystal ............................................................................................ 421 Table 19-19. External XTLP Oscillator Characteristics ......................................................................... 422 Table 19-20. SSI Characteristics ........................................................................................................ 422 Table 19-21. JTAG Characteristics ..................................................................................................... 424 Table 19-22. GPIO Characteristics ..................................................................................................... 426 Table 19-23. Reset Characteristics ..................................................................................................... 426 Table C-1. Part Ordering Information ............................................................................................... 449 November 30, 2007 11 Preliminary LM3S6110 Microcontroller List of Registers System Control .............................................................................................................................. 52 Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 60 Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 62 Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 63 Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 64 Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 65 Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 66 Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 67 Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 68 Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 72 Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 73 Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 75 Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 76 Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 78 Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 79 Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 81 Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 83 Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 85 Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 87 Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 88 Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 89 Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 90 Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 92 Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ......................... 94 Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 .................................... 96 Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 .................................. 98 Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 100 Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 102 Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 103 Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 105 Internal Memory ........................................................................................................................... 107 Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 112 Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 113 Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 114 Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 116 Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 117 Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 118 Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 119 Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 120 Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 121 Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 122 Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 123 Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 124 Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 125 Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 126 12 November 30, 2007 Preliminary Table of Contents Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 127 Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 128 Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 129 Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 130 General-Purpose Input/Outputs (GPIOs) ................................................................................... 131 Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 138 Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 139 Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 140 Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 141 Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 142 Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 143 Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 144 Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 145 Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 146 Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 147 Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 149 Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 150 Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 151 Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 152 Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 153 Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 154 Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 155 Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 156 Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 157 Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 158 Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 160 Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 161 Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 162 Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 163 Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 164 Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 165 Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 166 Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 167 Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 168 Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 169 Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 170 Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 171 General-Purpose Timers ............................................................................................................. 172 Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 184 Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 185 Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 187 Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 189 Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 192 Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 194 Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 195 Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 196 Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 198 Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 199 November 30, 2007 13 Preliminary LM3S6110 Microcontroller Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 200 Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 201 Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 202 Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 203 Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 204 Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 205 Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 206 Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 207 Watchdog Timer ........................................................................................................................... 208 Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 211 Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 212 Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 213 Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 214 Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 215 Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 216 Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 217 Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 218 Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 219 Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 220 Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 221 Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 222 Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 223 Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 224 Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 225 Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 226 Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 227 Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 228 Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 229 Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 230 Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 231 Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 239 Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 241 Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 243 Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 245 Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 246 Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 247 Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 248 Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 250 Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 252 Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 254 Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 256 Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 257 Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 258 Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 260 Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 261 Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 262 Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 263 Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 264 14 November 30, 2007 Preliminary Table of Contents Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 265 Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 266 Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 267 Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 268 Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 269 Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 270 Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 271 Synchronous Serial Interface (SSI) ............................................................................................ 272 Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 284 Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 286 Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 288 Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 289 Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 291 Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 292 Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 294 Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 295 Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 296 Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 297 Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 298 Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 299 Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 300 Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 301 Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 302 Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 303 Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 304 Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 305 Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 306 Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 307 Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 308 Ethernet Controller ...................................................................................................................... 309 Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 318 Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 320 Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 321 Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 322 Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 323 Register 6: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 324 Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 326 Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 327 Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 328 Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 329 Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 330 Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 331 Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 332 Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 333 Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 334 Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 335 Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 337 Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 339 November 30, 2007 15 Preliminary LM3S6110 Microcontroller Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 340 Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address 0x04 ............................................................................................................................. 341 Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5), address 0x05 ..................................................................................................... 343 Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address 0x06 ............................................................................................................................. 344 Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 345 Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address 0x11 .............................................................................................................................. 347 Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 349 Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 350 Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 351 Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 352 Analog Comparators ................................................................................................................... 353 Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 359 Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 360 Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 361 Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 362 Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 363 Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 363 Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60 ....................................................... 363 Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 364 Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 364 Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64 ...................................................... 364 Pulse Width Modulator (PWM) .................................................................................................... 366 Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 373 Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 374 Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 375 Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 376 Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 377 Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 378 Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 379 Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 380 Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 381 Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 382 Register 11: PWM0 Interrupt Enable (PWM0INTEN), offset 0x044 ...................................................... 384 Register 12: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 386 Register 13: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 387 Register 14: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 388 Register 15: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 389 Register 16: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 390 Register 17: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 391 Register 18: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 392 Register 19: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 395 Register 20: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 398 Register 21: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 399 Register 22: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 400 16 November 30, 2007 Preliminary Table of Contents About This Document This data sheet provides reference information for the LM3S6110 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature. Related Documents The following documents are referenced by the data sheet, and available on the documentation CD or from the Luminary Micro web site at www.luminarymicro.com: ■ ARM® Cortex™-M3 Technical Reference Manual ■ ARM® CoreSight Technical Reference Manual ■ ARM® v7-M Architecture Application Level Reference Manual The following related documents are also referenced: ■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the Luminary Micro web site for additional documentation, including application notes and white papers. Documentation Conventions This document uses the conventions shown in Table 1 on page 17. Table 1. Documentation Conventions Notation Meaning General Register Notation APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1 , and SRCR2. REGISTER bit A single bit in a register. bit field Two or more consecutive and related bits. A hexadecimal increment to a register's address, relative to that module's base address as specified in “Memory Map” on page 37. offset 0xnnn Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. Register N November 30, 2007 17 Preliminary LM3S6110 Microcontroller Notation Meaning Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. reserved The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. yy:xx This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. Register Bit/Field Types RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field. RO Software can read this field. Always write the chip reset value. R/W Software can read or write this field. Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. R/W1C Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. W1C WO Only a write by software is valid; a read of the register returns no meaningful data. Register Bit/Field This value in the register bit diagram shows the bit/field value after any reset, unless noted. Reset Value 0 Bit cleared to 0 on chip reset. 1 Bit set to 1 on chip reset. - Nondeterministic. Pin/Signal Notation [ ] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). assert a signal deassert a signal Change the value of the signal from the logically True state to the logically False state. Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. SIGNAL Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low. SIGNAL Numbers An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. X Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. 0x 18 November 30, 2007 Preliminary About This Document 1 Architectural Overview The Luminary Micro Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The Stellaris® family offers efficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity capabilities. The Stellaris® LM3S1000 series extends the Stellaris® family with larger on-chip memories, enhanced power management, and expanded I/O and control capabilities. The Stellaris® LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris family with Bosch CAN networking technology, the golden standard in short-haul industrial networks. The Stellaris® LM3S2000 series also marks the first integration of CAN capabilities with the revolutionary Cortex-M3 core. The Stellaris® LM3S6000 series combines both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC and PHY available in an ARM architecture MCU. The Stellaris® LM3S8000 series combines Bosch Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer. The LM3S6110 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security. In addition, the LM3S6110 microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S6110 microcontroller is code-compatible to all members of the extensive Stellaris® family; providing flexibility to fit our customers' precise needs. Luminary Micro offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. 1.1 Product Features The LM3S6110 microcontroller includes the following product features: ■ 32-Bit RISC Performance – 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications – System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism – Thumb®-compatible Thumb-2-only instruction set processor core for high code density – 25-MHz operation – Hardware-division and single-cycle-multiplication November 30, 2007 19 Preliminary LM3S6110 Microcontroller – Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling – 24 interrupts with eight priority levels – Memory protection unit (MPU), providing a privileged mode for protected operating system functionality – Unaligned data access, enabling data to be efficiently packed into memory – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control ■ Internal Memory – 64 KB single-cycle flash • User-managed flash block protection on a 2-KB block basis • User-managed flash data programming • User-defined and managed flash-protection block – 16 KB single-cycle SRAM ■ General-Purpose Timers – Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers. Each GPTM can be configured to operate independently: • As a single 32-bit timer • As one 32-bit Real-Time Clock (RTC) to event capture • For Pulse Width Modulation (PWM) – 32-bit Timer modes • Programmable one-shot timer • Programmable periodic timer • Real-Time Clock when using an external 32.768-KHz clock as the input • User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug – 16-bit Timer modes • General-purpose timer function with an 8-bit prescaler • Programmable one-shot timer • Programmable periodic timer • User-enabled stalling when the controller asserts CPU Halt flag during debug 20 November 30, 2007 Preliminary Architectural Overview – 16-bit Input Capture modes • Input edge count capture • Input edge time capture – 16-bit PWM mode • Simple PWM mode with software-programmable output inversion of the PWM signal ■ ARM FiRM-compliant Watchdog Timer – 32-bit down counter with a programmable load register – Separate watchdog clock with an enable – Programmable interrupt generation logic with interrupt masking – Lock register protection from runaway software – Reset generation logic with an enable/disable – User-enabled stalling when the controller asserts the CPU Halt flag during debug ■ 10/100 Ethernet Controller – Conforms to the IEEE 802.3-2002 Specification – Full- and half-duplex for both 100 Mbps and 10 Mbps operation – Integrated 10/100 Mbps Transceiver (PHY) – Automatic MDI/MDI-X cross-over correction – Programmable MAC address – Power-saving and power-down modes ■ Synchronous Serial Interface (SSI) – Master or slave operation – Programmable clock bit rate and prescale – Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep – Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces – Programmable data frame size from 4 to 16 bits – Internal loopback test mode for diagnostic/debug testing ■ UART – Fully programmable 16C550-type UART with IrDA support November 30, 2007 21 Preliminary LM3S6110 Microcontroller – Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading – Programmable baud-rate generator with fractional divider – Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface – FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 – Standard asynchronous communication bits for start, stop, and parity – False-start-bit detection – Line-break generation and detection ■ Analog Comparators – Three independent integrated analog comparators – Configurable for output to: drive an output pin or generate an interrupt – Compare external pin input to external pin input or to internal programmable voltage reference ■ PWM – One PWM generator blocks, each with one 16-bit counter, two comparators, a PWM generator, and a dead-band generator – One 16-bit counter • Runs in Down or Up/Down mode • Output frequency controlled by a 16-bit load value • Load value updates can be synchronized • Produces output signals at zero and load value – Two PWM comparators • Comparator value updates can be synchronized • Produces output signals on match – PWM generator • Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals • Produces two independent PWM signals – Dead-band generator • Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge 22 November 30, 2007 Preliminary Architectural Overview • Can be bypassed, leaving input PWM signals unmodified – Flexible output control block with PWM output enable of each PWM signal • PWM output enable of each PWM signal • Optional output inversion of each PWM signal (polarity control) • Optional fault handling for each PWM signal • Synchronization of timers in the PWM generator blocks • Synchronization of timer/comparator updates across the PWM generator blocks • Interrupt status summary of the PWM generator blocks ■ GPIOs – 8-35 GPIOs, depending on configuration – 5-V-tolerant input/outputs – Programmable interrupt generation as either edge-triggered or level-sensitive – Bit masking in both read and write operations through address lines – Programmable control for GPIO pad configuration: • Weak pull-up or pull-down resistors • 2-mA, 4-mA, and 8-mA pad drive • Slew rate control for the 8-mA drive • Open drain enables • Digital input enables ■ Power – On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V – Low-power options on controller: Sleep and Deep-sleep modes – Low-power options for peripherals: software controls shutdown of individual peripherals – User-enabled LDO unregulated voltage detection and automatic reset – 3.3-V supply brown-out detection and reporting via interrupt or reset ■ Flexible Reset Sources – Power-on reset (POR) – Reset pin assertion November 30, 2007 23 Preliminary LM3S6110 Microcontroller – Brown-out (BOR) detector alerts to system power drops – Software reset – Watchdog timer reset – Internal low drop-out (LDO) regulator output goes unregulated ■ Additional Features – Six reset sources – Programmable clock source control – Clock gating to individual peripherals for power savings – IEEE 1149.1-1990 compliant Test Access Port (TAP) controller – Debug access via JTAG and Serial Wire interfaces – Full JTAG boundary scan ■ Industrial-range 100-pin RoHS-compliant LQFP package 1.2 Target Applications ■ Remote monitoring ■ Electronic point-of-sale (POS) machines ■ Test and measurement equipment ■ Network appliances and switches ■ Factory automation ■ HVAC and building control ■ Gaming equipment ■ Motion control ■ Medical instrumentation ■ Fire and security ■ Power and energy ■ Transportation 1.3 High-Level Block Diagram Figure 1-1 on page 25 represents the full set of features in the Stellaris® 6000 series of devices; not all features may be available on the LM3S6110 microcontroller. 24 November 30, 2007 Preliminary Architectural Overview Figure 1-1. Stellaris® 6000 Series High-Level Block Diagram 1.4 Functional Overview The following sections provide an overview of the features of the LM3S6110 microcontroller. The page number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 449. November 30, 2007 25 Preliminary LM3S6110 Microcontroller 1.4.1 ARM Cortex™-M3 1.4.1.1 Processor Core (see page 31) All members of the Stellaris® product family, including the LM3S6110 microcontroller, are designed around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. “ARM Cortex-M3 Processor Core” on page 31 provides an overview of the ARM core; the core is detailed in the ARM® Cortex™-M3 Technical Reference Manual. 1.4.1.2 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter. Software can use this to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. 1.4.1.3 Nested Vectored Interrupt Controller (NVIC) The LM3S6110 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 24 interrupts. “Interrupts” on page 39 provides an overview of the NVIC controller and the interrupt map. Exceptions and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual. 1.4.2 Motor Control Peripherals To enhance motor control, the LM3S6110 controller features Pulse Width Modulation (PWM) outputs. 1.4.2.1 PWM Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. 26 November 30, 2007 Preliminary Architectural Overview On the LM3S6110, PWM motion control functionality can be achieved through: ■ Dedicated, flexible motion control hardware using the PWM pins ■ The motion control features of the general-purpose timers using the CCP pins PWM Pins (see page 366) The LM3S6110 PWM module consists of one PWM generator blocks and a control block. Each PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM signal generator, a dead-band generator, and an interrupt. The control block determines the polarity of the PWM signals, and which signals are passed through to the pins. Each PWM generator block produces two PWM signals that can either be independent signals or a single pair of complementary signals with dead-band delays inserted. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins. CCP Pins (see page 178) The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal. 1.4.3 Analog Peripherals For support of analog signals, the LM3S6110 microcontroller offers three analog comparators. 1.4.3.1 Analog Comparators (see page 353) An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. The LM3S6110 microcontroller provides three independent integrated analog comparators that can be configured to drive an output or generate an interrupt . A comparator can compare a test voltage against any one of these voltages: ■ An individual external reference voltage ■ A shared single external reference voltage ■ A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence. 1.4.4 Serial Communications Peripherals The LM3S6110 controller supports both asynchronous and synchronous serial communications with: ■ One fully programmable 16C550-type UART ■ One SSI module ■ Ethernet controller November 30, 2007 27 Preliminary LM3S6110 Microcontroller 1.4.4.1 UART (see page 231) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The LM3S6110 controller includes one fully programmable 16C550-type UARTthat supports data transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not register-compatible.) In addition, each UART is capable of supporting IrDA. Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading. The UART can generate individually masked interrupts from the RX, TX, modem status, and error conditions. The module provides a single combined interrupt when any of the interrupts are asserted and are unmasked. 1.4.4.2 SSI (see page 272) Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface. The LM3S6110 controller includes one SSI module that provides the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive. The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently. The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. 1.4.4.3 Ethernet Controller (see page 309) Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet has been standardized as IEEE 802.3. It defines a number of wiring and signaling standards for the physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer, and a common addressing format. The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. In addition, the Ethernet Controller supports automatic MDI/MDI-X cross-over correction. 1.4.5 System Peripherals 1.4.5.1 Programmable GPIOs (see page 131) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris® GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 8-35 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 402 for the signals available to each GPIO pin). 28 November 30, 2007 Preliminary Architectural Overview The GPIO module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in both read and write operations through address lines. 1.4.5.2 Three Programmable Timers (see page 172) Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris® General-Purpose Timer Module (GPTM) contains three GPTM blocks. Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event capture or Pulse Width Modulation (PWM) generation. 1.4.5.3 Watchdog Timer (see page 208) A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The Stellaris® Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 1.4.6 Memory Peripherals The LM3S6110 controller offers both single-cycle SRAM and single-cycle Flash memory. 1.4.6.1 SRAM (see page 107) The LM3S6110 static random access memory (SRAM) controller supports 16 KB SRAM. The internal SRAM of the Stellaris® devices is located at offset 0x0000.0000 of the device memory map. To reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. 1.4.6.2 Flash (see page 108) The LM3S6110 Flash controller supports 64 KB of flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. November 30, 2007 29 Preliminary LM3S6110 Microcontroller 1.4.7 Additional Features 1.4.7.1 Memory Map (see page 37) A memory map lists the location of instructions and data in memory. The memory map for the LM3S6110 controller can be found in “Memory Map” on page 37. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory map. 1.4.7.2 JTAG TAP Controller (see page 41) The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG data registers can be used to test the interconnects of assembled printed circuit boards, obtain manufacturing information on the components, and observe and/or control the inputs and outputs of the controller during normal operation. The JTAG port provides a high degree of testability and chip-level access at a low cost. The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions. 1.4.7.3 System Control and Clocks (see page 52) System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. 1.4.8 Hardware Details Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 401 ■ “Signal Tables” on page 402 ■ “Operating Characteristics” on page 414 ■ “Electrical Characteristics” on page 415 ■ “Package Information” on page 428 30 November 30, 2007 Preliminary Architectural Overview 2 ARM Cortex-M3 Processor Core The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: ■ Compact core. ■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. ■ Rapid application execution through Harvard architecture characterized by separate buses for instruction and data. ■ Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. ■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications. ■ Migration from the ARM7™ processor family for better performance and power efficiency. ■ Full-featured debug solution with a: – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer The Stellaris® family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motors. For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference Manual. November 30, 2007 31 Preliminary LM3S6110 Microcontroller 2.1 Block Diagram Figure 2-1. CPU Block Diagram Private Peripheral Bus (internal) Data Watchpoint and Trace Interrupts Debug Sleep Instrumentation Trace Macrocell Trace Port Interface Unit CM3 Core Instructions Data Flash Patch and Breakpoint Memory Protection Unit Adv. High- Perf. Bus Access Port Nested Vectored Interrupt Controller Serial Wire JTAG Debug Port Bus Matrix Adv. Peripheral Bus I-code bus D-code bus System bus ROM Table Private Peripheral Bus (external) Serial Wire Output Trace Port (SWO) ARM Cortex-M3 2.2 Functional Description Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an ARM Cortex-M3 in detail. However, these features differ based on the implementation. This section describes the Stellaris® implementation. Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 32. As noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow. 2.2.1 Serial Wire and JTAG Debug Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris® devices. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP. 32 November 30, 2007 Preliminary ARM Cortex-M3 Processor Core 2.2.2 Embedded Trace Macrocell (ETM) ETM was not implemented in the Stellaris® devices. This means Chapters 15 and 16 of the ARM® Cortex™-M3 Technical Reference Manual can be ignored. 2.2.3 Trace Port Interface Unit (TPIU) The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace Port Analyzer. The Stellaris® devices have implemented TPIU as shown in Figure 2-2 on page 33. This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference Manual, however, SWJ-DP only provides SWV output for the TPIU. Figure 2-2. TPIU Block Diagram ATB Interface Asynchronous FIFO APB Interface Trace Out (serializer) Debug ATB Slave Port APB Slave Port Serial Wire Trace Port (SWO) 2.2.4 ROM Table The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical Reference Manual. 2.2.5 Memory Protection Unit (MPU) The Memory Protection Unit (MPU) is included on the LM3S6110 controller and supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 2.2.6 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC): ■ Facilitates low-latency exception and interrupt handling ■ Controls power management ■ Implements system control registers November 30, 2007 33 Preliminary LM3S6110 Microcontroller The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of priority. The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the stacked (nested) interrupts to enable tail-chaining of interrupts. You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference Manual). Any other user-mode access causes a bus fault. All NVIC registers are accessible using byte, halfword, and word unless otherwise stated. All NVIC registers and system debug registers are little endian regardless of the endianness state of the processor. 2.2.6.1 Interrupts The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts and interrupt priorities. The LM3S6110 microcontroller supports 24 interrupts with eight priority levels. 2.2.6.2 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter. Software can use this to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. Functional Description The timer consists of three registers: ■ A control and status counter to configure its clock, enable the counter, enable the SysTick interrupt, and determine counter status. ■ The reload value for the counter, used to provide the counter's wrap value. ■ The current value of the counter. A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris® devices. When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks. Writing a value of zero to the Reload Value register disables the counter on the next wrap. When the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. 34 November 30, 2007 Preliminary ARM Cortex-M3 Processor Core Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed. If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect to a reference clock. The reference clock can be the core clock or an external clock source. SysTick Control and Status Register Use the SysTick Control and Status Register to enable the SysTick features. The reset is 0x0000.0000. Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:17 reserved RO 0 Returns 1 if timer counted to 0 since last time this was read. Clears on read by application. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read. 16 COUNTFLAG R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:3 reserved RO 0 0 = external reference clock. (Not implemented for Stellaris microcontrollers.) 1 = core clock. If no reference clock is provided, it is held at 1 and so gives the same time as the core clock. The core clock must be at least 2.5 times faster than the reference clock. If it is not, the count values are unpredictable. 2 CLKSOURCE R/W 0 1 = counting down to 0 pends the SysTick handler. 0 = counting down to 0 does not pend the SysTick handler. Software can use the COUNTFLAG to determine if ever counted to 0. 1 TICKINT R/W 0 1 = counter operates in a multi-shot way. That is, counter loads with the Reload value and then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads the Reload value again, and begins counting. 0 = counter disabled. 0 ENABLE R/W 0 SysTick Reload Value Register Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 1 and 0x00FF.FFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. Therefore, as a multi-shot timer, repeated over and over, it fires every N+1 clock pulse, where N is any value from 1 to 0x00FF.FFFF. So, if the tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD. If a new value is written on each tick interrupt, so treated as single shot, then the actual count down must be written. For example, if a tick is next required after 400 clock pulses, 400 must be written into the RELOAD. Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:24 reserved RO 0 November 30, 2007 35 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description 23:0 RELOAD W1C - Value to load into the SysTick Current Value Register when the counter reaches 0. SysTick Current Value Register Use the SysTick Current Value Register to find the current value in the register. Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:24 reserved RO 0 Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. 23:0 CURRENT W1C - SysTick Calibration Value Register The SysTick Calibration Value register is not implemented. 36 November 30, 2007 Preliminary ARM Cortex-M3 Processor Core 3 Memory Map The memory map for the LM3S6110 controller is provided in Table 3-1 on page 37. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM® Cortex™-M3 Technical Reference Manual. Important: In Table 3-1 on page 37, addresses not listed are reserved. Table 3-1. Memory Mapa For details on registers, see page ... Start End Description Memory 0x0000.0000 0x0000.FFFF On-chip flash b 111 0x2000.0000 0x2000.3FFF Bit-banded on-chip SRAMc 111 0x2010.0000 0x21FF.FFFF Reserved non-bit-banded SRAM space - 0x2200.0000 0x23FF.FFFF Bit-band alias of 0x2000.0000 through 0x200F.FFFF 107 0x2400.0000 0x3FFF.FFFF Reserved non-bit-banded SRAM space - FiRM Peripherals 0x4000.0000 0x4000.0FFF Watchdog timer 210 0x4000.4000 0x4000.4FFF GPIO Port A 137 0x4000.5000 0x4000.5FFF GPIO Port B 137 0x4000.6000 0x4000.6FFF GPIO Port C 137 0x4000.7000 0x4000.7FFF GPIO Port D 137 0x4000.8000 0x4000.8FFF SSI0 283 0x4000.C000 0x4000.CFFF UART0 238 Peripherals 0x4002.4000 0x4002.4FFF GPIO Port E 137 0x4002.5000 0x4002.5FFF GPIO Port F 137 0x4002.6000 0x4002.6FFF GPIO Port G 137 0x4002.8000 0x4002.8FFF PWM 372 0x4003.0000 0x4003.0FFF Timer0 183 0x4003.1000 0x4003.1FFF Timer1 183 0x4003.2000 0x4003.2FFF Timer2 183 0x4003.C000 0x4003.CFFF Analog Comparators 353 0x4004.8000 0x4004.8FFF Ethernet Controller 317 0x400F.D000 0x400F.DFFF Flash control 111 0x400F.E000 0x400F.EFFF System control 59 0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF - Private Peripheral Bus November 30, 2007 37 Preliminary LM3S6110 Microcontroller For details on registers, see page ... Start End Description ARM® Cortex™-M3 Technical Reference Manual 0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM) 0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT) 0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB) 0xE000.3000 0xE000.DFFF Reserved 0xE000.E000 0xE000.EFFF Nested Vectored Interrupt Controller (NVIC) 0xE000.F000 0xE003.FFFF Reserved 0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU) 0xE004.1000 0xE004.1FFF Reserved - 0xE004.2000 0xE00F.FFFF Reserved - 0xE010.0000 0xFFFF.FFFF Reserved for vendor peripherals - a. All reserved space returns a bus fault when read or written. b. The unavailable flash will bus fault throughout this range. c. The unavailable SRAM will bus fault throughout this range. 38 November 30, 2007 Preliminary Memory Map 4 Interrupts The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 4-1 on page 39 lists all the exceptions. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 24 interrupts (listed in Table 4-2 on page 40). Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt Priority registers. You can also group priorities by splitting priority levels into pre-emption priorities and subpriorities. All the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt Controller” in the ARM® Cortex™-M3 Technical Reference Manual. Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and a Hard Fault. Note that 0 is the default priority for all the settable priorities. If you assign the same priority level to two or more interrupts, their hardware priority (the lower the position number) determines the order in which the processor activates them. For example, if both GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority. See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM® Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts. Note: In Table 4-2 on page 40 interrupts not listed are reserved. Table 4-1. Exception Types Exception Type Position Prioritya Description - 0 - Stack top is loaded from first entry of vector table on reset. Invoked on power up and warm reset. On first instruction, drops to lowest priority (and then is called the base level of activation). This is asynchronous. Reset 1 -3 (highest) Cannot be stopped or preempted by any exception but reset. This is asynchronous. An NMI is only producible by software, using the NVIC Interrupt Control State register. Non-Maskable 2 -2 Interrupt (NMI) All classes of Fault, when the fault cannot activate due to priority or the configurable fault handler has been disabled. This is synchronous. Hard Fault 3 -1 MPU mismatch, including access violation and no match. This is synchronous. The priority of this exception can be changed. Memory Management 4 settable Pre-fetch fault, memory access fault, and other address/memory related faults. This is synchronous when precise and asynchronous when imprecise. You can enable or disable this fault. Bus Fault 5 settable Usage fault, such as undefined instruction executed or illegal state transition attempt. This is synchronous. Usage Fault 6 settable - 7-10 - Reserved. SVCall 11 settable System service call with SVC instruction. This is synchronous. November 30, 2007 39 Preliminary LM3S6110 Microcontroller Exception Type Position Prioritya Description Debug monitor (when not halting). This is synchronous, but only active when enabled. It does not activate if lower priority than the current activation. Debug Monitor 12 settable - 13 - Reserved. Pendable request for system service. This is asynchronous and only pended by software. PendSV 14 settable SysTick 15 settable System tick timer has fired. This is asynchronous. Asserted from outside the ARM Cortex-M3 core and fed through the NVIC (prioritized). These are all asynchronous. Table 4-2 on page 40 lists the interrupts on the LM3S6110 controller. 16 and settable above Interrupts a. 0 is the default priority for all the settable priorities. Table 4-2. Interrupts Interrupt (Bit in Interrupt Registers) Description 0 GPIO Port A 1 GPIO Port B 2 GPIO Port C 3 GPIO Port D 4 GPIO Port E 5 UART0 7 SSI0 9 PWM Fault 10 PWM Generator 0 18 Watchdog timer 19 Timer0 A 20 Timer0 B 21 Timer1 A 22 Timer1 B 23 Timer2 A 24 Timer2 B 25 Analog Comparator 0 26 Analog Comparator 1 27 Analog Comparator 2 28 System Control 29 Flash Control 30 GPIO Port F 31 GPIO Port G 42 Ethernet Controller 40 November 30, 2007 Preliminary Interrupts 5 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions. The JTAG module has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: – BYPASS instruction – IDCODE instruction – SAMPLE/PRELOAD instruction – EXTEST instruction – INTEST instruction ■ ARM additional instructions: – APACC instruction – DPACC instruction – ABORT instruction ■ Integrated ARM Serial Wire Debug (SWD) See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG controller. November 30, 2007 41 Preliminary LM3S6110 Microcontroller 5.1 Block Diagram Figure 5-1. JTAG Module Block Diagram Instruction Register (IR) TAP Controller BYPASS Data Register Boundary Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register TRST TCK TMS TDI TDO Cortex-M3 Debug Port 5.2 Functional Description A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 42. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and TMS inputs. The current state of the TAP controller depends on the current value of TRST and the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 5-2 on page 48 for a list of implemented instructions). See “JTAG and Boundary Scan” on page 424 for JTAG timing diagrams. 42 November 30, 2007 Preliminary JTAG Interface 5.2.1 JTAG Interface Pins The JTAG interface consists of five standard pins: TRST, TCK, TMS, TDI, and TDO. These pins and their associated reset state are given in Table 5-1 on page 43. Detailed information on each pin follows. Table 5-1. JTAG Port Pins Reset State Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value TRST Input Enabled Disabled N/A N/A TCK Input Enabled Disabled N/A N/A TMS Input Enabled Disabled N/A N/A TDI Input Enabled Disabled N/A N/A TDO Output Enabled Disabled 2-mA driver High-Z 5.2.1.1 Test Reset Input (TRST) The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled on PB7/TRST; otherwise JTAG communication could be lost. 5.2.1.2 Test Clock Input (TCK) The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost. By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as the TCK pin is constantly being driven by an external source. 5.2.1.3 Test Mode Select (TMS) The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK. Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine can be seen in its entirety in Figure 5-2 on page 45. November 30, 2007 43 Preliminary LM3S6110 Microcontroller By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost. 5.2.1.4 Test Data Input (TDI) The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is sampled on the rising edge of TCK and, depending on the current TAP state and the current instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost. 5.2.1.5 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states. 5.2.2 JTAG TAP Controller The JTAG TAP controller state machine is shown in Figure 5-2 on page 45. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR) or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. 44 November 30, 2007 Preliminary JTAG Interface Figure 5-2. Test Access Port State Machine Test Logic Reset Run Test Idle Select DR Scan Select IR Scan Capture DR Capture IR Shift DR Shift IR Exit 1 DR Exit 1 IR Exit 2 DR Exit 2 IR Pause DR Pause IR Update DR Update IR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5.2.3 Shift Registers The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller’s CAPTURE states and allows this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 48. 5.2.4 Operational Considerations There are certain operational considerations when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below. November 30, 2007 45 Preliminary LM3S6110 Microcontroller 5.2.4.1 GPIO Functionality When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins. It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides five more GPIOs for use in the design. Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down resistors connected to both of them at the same time. If both pins are pulled Low during reset, the controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors, and apply RST or power-cycle the part. In addition, it is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 147) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 157) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 158) have been set to 1. Recovering a "Locked" Device If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate with the debugger, there is a debug sequence that can be used to recover the device. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset mass erases the flash memory. The sequence to recover the device is: 1. Assert and hold the RST signal. 2. Perform the JTAG-to-SWD switch sequence. 3. Perform the SWD-to-JTAG switch sequence. 4. Perform the JTAG-to-SWD switch sequence. 5. Perform the SWD-to-JTAG switch sequence. 6. Perform the JTAG-to-SWD switch sequence. 7. Perform the SWD-to-JTAG switch sequence. 8. Perform the JTAG-to-SWD switch sequence. 9. Perform the SWD-to-JTAG switch sequence. 10. Perform the JTAG-to-SWD switch sequence. 11. Perform the SWD-to-JTAG switch sequence. 46 November 30, 2007 Preliminary JTAG Interface 12. Release the RST signal. The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug (SWD)” on page 47. When performing switch sequences for the purpose of recovering the debug capabilities of the device, only steps 1 and 2 of the switch sequence need to be performed. 5.2.4.2 ARM Serial Wire Debug (SWD) In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M3 core without having to perform, or have any knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the SWD session begins. The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. Stepping through this sequences of the TAP state machine enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see the ARM® Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual. Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occurring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface. JTAG-to-SWD Switching To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the external debug hardware must send a switch sequence to the device. The 16-bit switch sequence for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in SWD mode, before sending the switch sequence, the SWD goes into the line reset state. SWD-to-JTAG Switching To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the external debug hardware must send a switch sequence to the device. The 16-bit switch sequence for switching to JTAG mode is defined as b1110011110011110, transmitted LSB first. This can also be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. November 30, 2007 47 Preliminary LM3S6110 Microcontroller 2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C. 3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic Reset state. 5.3 Initialization and Configuration After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. This is done by enabling the five JTAG pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. 5.4 Register Descriptions There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The registers within the JTAG controller are all accessed serially through the TAP Controller. The registers can be broken down into two main categories: Instruction Registers and Data Registers. 5.4.1 Instruction Register (IR) The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the Instruction Register bits is shown in Table 5-2 on page 48. A detailed explanation of each instruction, along with its associated Data Register, follows. Table 5-2. JTAG Instruction Register Commands IR[3:0] Instruction Description Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. 0000 EXTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. 0001 INTEST Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. 0010 SAMPLE / PRELOAD 1000 ABORT Shifts data into the ARM Debug Port Abort Register. 1010 DPACC Shifts data into and out of the ARM DP Access Register. 1011 APACC Shifts data into and out of the ARM AC Access Register. Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. 1110 IDCODE 1111 BYPASS Connects TDI to TDO through a single Shift Register chain. All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. 5.4.1.1 EXTEST Instruction The EXTEST instruction does not have an associated Data Register chain. The EXTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. This allows 48 November 30, 2007 Preliminary JTAG Interface tests to be developed that drive known values out of the controller, which can be used to verify connectivity. 5.4.1.2 INTEST Instruction The INTEST instruction does not have an associated Data Register chain. The INTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the GPIO pads. This allows tests to be developed that drive known values into the controller, which can be used for testing. It is important to note that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable. 5.4.1.3 SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with each input, output, and output enable. This preloaded data can be used with the EXTEST and INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data Register” on page 51 for more information. 5.4.1.4 ABORT Instruction The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. Please see the “ABORT Data Register” on page 51 for more information. 5.4.1.5 DPACC Instruction The DPACC instruction connects the associated DPACC Data Register chain between TDI and TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. Please see “DPACC Data Register” on page 51 for more information. 5.4.1.6 APACC Instruction The APACC instruction connects the associated APACC Data Register chain between TDI and TDO. This instruction provides read and write access to the APACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. Please see “APACC Data Register” on page 51 for more information. November 30, 2007 49 Preliminary LM3S6110 Microcontroller 5.4.1.7 IDCODE Instruction The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and TDO. This instruction provides information on the manufacturer, part number, and version of the ARM core. This information can be used by testing equipment and debuggers to automatically configure their input and output data streams. IDCODE is the default instruction that is loaded into the JTAG Instruction Register when a power-on-reset (POR) is asserted, TRST is asserted, or the Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 50 for more information. 5.4.1.8 BYPASS Instruction The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports. The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 50 for more information. 5.4.2 Data Registers The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed in the following sections. 5.4.2.1 IDCODE Data Register The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in Figure 5-3 on page 50. The standard requires that every JTAG-compliant device implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This allows auto configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly, and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x3BA00477. This value indicates an ARM Cortex-M3, Version 1 processor. This allows the debuggers to automatically configure themselves to work correctly with the Cortex-M3 during debug. Figure 5-3. IDCODE Register Format 5.4.2.2 BYPASS Data Register The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in Figure 5-4 on page 51. The standard requires that every JTAG-compliant device implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This allows auto configuration test tools to determine which instruction is the default instruction. 50 November 30, 2007 Preliminary JTAG Interface Figure 5-4. BYPASS Register Format 5.4.2.3 Boundary Scan Data Register The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 51. Each GPIO pin, in a counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data Register. Each GPIO pin has three associated digital signals that are included in the chain. These signals are input, output, and output enable, and are arranged in that order as can be seen in the figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because the reset pin is always an input, only the input signal is included in the Data Register chain. When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST and INTEST instructions. These instructions either force data out of the controller, with the EXTEST instruction, or into the controller, with the INTEST instruction. Figure 5-5. Boundary Scan Register Format O TDO TDI O IN E UT O O IN U E T O O IN E UT O O IN U E T I N ... ... GPIO PB6 GPIO m RST GPIO m+1 GPIO n For detailed information on the order of the input, output, and output enable bits for each of the GPIO ports, please refer to the Stellaris® Family Boundary Scan Description Language (BSDL) files, downloadable from www.luminarymicro.com. 5.4.2.4 APACC Data Register The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 5.4.2.5 DPACC Data Register The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 5.4.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. November 30, 2007 51 Preliminary LM3S6110 Microcontroller 6 System Control System control determines the overall operation of the device. It provides information about the device, controls the clocking to the core and individual peripherals, and handles reset detection and reporting. 6.1 Functional Description The System Control module provides the following capabilities: ■ Device identification, see “Device Identification” on page 52 ■ Local control, such as reset (see “Reset Control” on page 52), power (see “Power Control” on page 55) and clock control (see “Clock Control” on page 55) ■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 57 6.1.1 Device Identification Seven read-only registers provide software with information on the microcontroller, such as version, part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers. 6.1.2 Reset Control This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 6.1.2.1 CMOD0 and CMOD1 Test-Mode Control Pins Two pins, CMOD0 and CMOD1, are defined for use by Luminary Micro for testing the devices during manufacture. They have no end-user function and should not be used. The CMOD pins should be connected to ground. 6.1.2.2 Reset Sources The controller has five sources of reset: 1. External reset input pin (RST) assertion, see “RST Pin Assertion” on page 52. 2. Power-on reset (POR), see “Power-On Reset (POR)” on page 53. 3. Internal brown-out (BOR) detector, see “Brown-Out Reset (BOR)” on page 53. 4. Software-initiated reset (with the software reset registers), see “Software Reset” on page 54. 5. A watchdog timer reset condition violation, see “Watchdog Timer Reset” on page 54. After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal POR is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator. 6.1.2.3 RST Pin Assertion The external reset pin (RST) resets the controller. This resets the core and all the peripherals except the JTAG TAP controller (see “JTAG Interface” on page 41). The external reset sequence is as follows: 52 November 30, 2007 Preliminary System Control 1. The external reset pin (RST) is asserted and then de-asserted. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. A few clocks cycles from RST de-assertion to the start of the reset sequence is necessary for synchronization. The external reset timing is shown in Figure 19-9 on page 426. 6.1.2.4 Power-On Reset (POR) The Power-On Reset (POR) circuit monitors the power supply voltage (VDD). The POR circuit generates a reset signal to the internal logic when the power supply ramp reaches a threshold value (VTH). If the application only uses the POR circuit, the RST input needs to be connected to the power supply (VDD) through a pull-up resistor (1K to 10K Ω). The device must be operating within the specified operating parameters at the point when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the device must reach 3.0 V within 10 msec of it crossing 2.0 V to guarantee proper operation. For applications that require the use of an external reset to hold the device in reset longer than the internal POR, the RST input may be used with the circuit as shown in Figure 6-1 on page 53. Figure 6-1. External Circuitry to Extend Reset R1 C1 R2 RST Stellaris D1 The R1 and C1 components define the power-on delay. The R2 resistor mitigates any leakage from the RST input. The diode (D1) discharges C1 rapidly when the power supply is turned off. The Power-On Reset sequence is as follows: 1. The controller waits for the later of external reset (RST) or internal POR to go inactive. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing is shown in Figure 19-10 on page 427. Note: The power-on reset also resets the JTAG controller. An external reset does not. 6.1.2.5 Brown-Out Reset (BOR) A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller. This is initially disabled and may be enabled by software. The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may generate a controller interrupt or a system reset. November 30, 2007 53 Preliminary LM3S6110 Microcontroller Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL) register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger a reset. The brown-out reset is equivelent to an assertion of the external RST input and the reset is held active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. The internal Brown-Out Reset timing is shown in Figure 19-11 on page 427. 6.1.2.6 Software Reset Software can reset a specific peripheral or generate a reset to the entire system . Peripherals can be individually reset by software via three registers that control reset signals to each peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see “System Control” on page 57). Note that all reset signals for all clocks of the specified unit are asserted as a result of a software-initiated reset. The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3 Application Interrupt and Reset Control register resets the entire system including the core. The software-initiated system reset sequence is as follows: 1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register. 2. An internal reset is asserted. 3. The internal reset is deasserted and the controller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 19-12 on page 427. 6.1.2.7 Watchdog Timer Reset The watchdog timer module's function is to prevent system hangs. The watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted. 3. The internal reset is released and the controller loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. 54 November 30, 2007 Preliminary System Control The watchdog reset timing is shown in Figure 19-13 on page 427. 6.1.3 Power Control The Stellaris® microcontroller provides an integrated LDO regulator that may be used to provide power to the majority of the controller's internal logic. The LDO regulator provides software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ field in the LDO Power Control (LDOPCTL) register. Note: The use of the LDO is optional. The internal logic may be supplied by the on-chip LDO or by an external regulator. If the LDO is used, the LDO output pin is connected to the VDD25 pins on the printed circuit board. The LDO requires decoupling capacitors on the printed circuit board. If an external regulator is used, it is strongly recommended that the external regulator supply the controller only and not be shared with other devices on the printed circuit board. 6.1.4 Clock Control System control determines the control of clocks in this part. 6.1.4.1 Fundamental Clock Sources There are four clock sources for use in the device: ■ Internal Oscillator (IOSC): The internal oscillator is an on-chip clock source. It does not require the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%. Applications that do not depend on accurate clock sources may use this clock source to reduce system cost. The internal oscillator is the clock source the device uses during and following POR. If the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. ■ Main Oscillator: The main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins. The crystal value allowed depends on whether the main oscillator is used as the clock reference source to the PLL. If so, the crystal must be one of the supported frequencies between 3.579545 MHz through 8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC through the specified speed of the device. The supported crystals are listed in the XTAL bit in the RCC register (see page 68). ■ Internal 30-kHz Oscillator: The internal 30-kHz oscillator is similar to the internal oscillator, except that it provides an operational frequency of 30 kHz ± 30%. It is intended for use during Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal switching and also allows the main oscillator to be powered down. The internal system clock (sysclk), is derived from any of the four sources plus two others: the output of the internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive). The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2) registers provide control for the system clock. The RCC2 register is provided to extend fields that offer additional encodings over the RCC register. When used, the RCC2 register field values are November 30, 2007 55 Preliminary LM3S6110 Microcontroller used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for a larger assortment of clock configuration options. 6.1.4.2 Crystal Configuration for the Main Oscillator (MOSC) The main oscillator supports the use of a select number of crystals. If the main oscillator is used by the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise, the range of supported crystals is 1 to 8.192 MHz. The XTAL bit in the RCC register (see page 68) describes the available crystal choices and default programming values. Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the design, the XTAL field value is internally translated to the PLL settings. 6.1.4.3 PLL Frequency Configuration The PLL is disabled by default during power-on reset and is enabled later by software if required. Software configures the PLL input reference clock source, specifies the output divisor to set the system clock frequency, and enables the PLL to drive the output. If the main oscillator provides the clock reference to the PLL, the translation provided by hardware and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG) register (see page 72). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency. The Crystal Value field (XTAL) on page 68 describes the available crystal choices and default programming of the PLLCFG register. The crystal number is written into the XTAL field of the Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings are translated and the internal PLL settings are updated. 6.1.4.4 PLL Modes The PLL has two modes of operation: Normal and Power-Down ■ Normal: The PLL multiplies the input clock reference and drives the output. ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the RCC/RCC2 register fields (see page 68 and page 73). 6.1.4.5 PLL Operation If the PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 19-6 on page 418). During this time, the PLL is not usable as a clock reference. The PLL is changed by one of the following: ■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock. ■ Change in the PLL from Power-Down to Normal mode. A counter is defined to measure the TREADY requirement. The counter is clocked by the main oscillator. The range of the main oscillator has been taken into account and the down counter is set to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). . Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the 56 November 30, 2007 Preliminary System Control two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched to use the PLL. 6.1.5 System Control For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep mode, respectively. In Run mode, the processor executes code. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor is not clocked and therefore no longer executes code. In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns the device to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. Each mode is described in more detail below. There are four levels of operation for the device defined as: ■ Run Mode. Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the RCGCn registers. The system clock can be any of the available clock sources including the PLL. ■ Sleep Mode. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for Interrupt) instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual for more details. In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system clock has the same source and frequency as that during Run mode. ■ Deep-Sleep Mode. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual for more details. The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when auto-clock gating is disabled. The system clock source is the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up, if necessary, and the main oscillator is powered down. If the PLL is running at the time of the WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active RCC/RCC2 register to be /16 or /64, respectively. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration. 6.2 Initialization and Configuration The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps required to successfully change the PLL-based system clock are: November 30, 2007 57 Preliminary LM3S6110 Microcontroller 1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register. This configures the system to run off a “raw” clock source (using the main oscillator or internal oscillator) and allows for the new PLL configuration to be validated before switching the system clock to the PLL. 2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output. 3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The SYSDIV field determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. 6.3 Register Map Table 6-1 on page 58 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register’s address, relative to the System Control base address of 0x400F.E000. Note: Spaces in the System Control register space that are not used are reserved for future or internal use by Luminary Micro, Inc. Software should not modify any reserved memory address. Table 6-1. System Control Register Map See Offset Name Type Reset Description page 0x000 DID0 RO - Device Identification 0 60 0x004 DID1 RO - Device Identification 1 76 0x008 DC0 RO 0x003F.001F Device Capabilities 0 78 0x010 DC1 RO 0x0010.709F Device Capabilities 1 79 0x014 DC2 RO 0x0707.0011 Device Capabilities 2 81 0x018 DC3 RO 0x0F00.B7C3 Device Capabilities 3 83 0x01C DC4 RO 0x5000.007F Device Capabilities 4 85 0x030 PBORCTL R/W 0x0000.7FFD Brown-Out Reset Control 62 0x034 LDOPCTL R/W 0x0000.0000 LDO Power Control 63 0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 102 0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 103 0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 105 0x050 RIS RO 0x0000.0000 Raw Interrupt Status 64 0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 65 0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 66 0x05C RESC R/W - Reset Cause 67 58 November 30, 2007 Preliminary System Control See Offset Name Type Reset Description page 0x060 RCC R/W 0x07AE.3AD1 Run-Mode Clock Configuration 68 0x064 PLLCFG RO - XTAL to PLL Translation 72 0x070 RCC2 R/W 0x0780.2800 Run-Mode Clock Configuration 2 73 0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 87 0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 90 0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 96 0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 88 0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 92 0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 98 0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 89 0x124 DCGC1 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 94 0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 100 0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 75 6.4 Register Descriptions All addresses given are relative to the System Control base address of 0x400F.E000. November 30, 2007 59 Preliminary LM3S6110 Microcontroller Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the device. Device Identification 0 (DID0) Base 0x400F.E000 Offset 0x000 Type RO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved VER reserved CLASS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAJOR MINOR Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 DID0 Version This field defines the DID0 register format version. The version number is numeric. The value of the VER field is encoded as follows: Value Description First revision of the DID0 register format, for Stellaris® Fury-class devices . 0x1 30:28 VER RO 0x1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:24 reserved RO 0x0 Device Class The CLASS field value identifies the internal design from which all mask sets are generated for all devices in a particular product line. The CLASS field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the MAJOR or MINOR fields require differentiation from prior devices. The value of the CLASS field is encoded as follows (all other encodings are reserved): Value Description 0x0 Stellaris® Sandstorm-class devices. 0x1 Stellaris® Fury-class devices. 23:16 CLASS RO 0x1 60 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description Major Revision This field specifies the major revision number of the device. The major revision reflects changes to base layers of the design. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on). This field is encoded as follows: Value Description 0x0 Revision A (initial device) 0x1 Revision B (first base layer revision) 0x2 Revision C (second base layer revision) and so on. 15:8 MAJOR RO - Minor Revision This field specifies the minor revision number of the device. The minor revision reflects changes to the metal layers of the design. The MINOR field value is reset when the MAJOR field is changed. This field is numeric and is encoded as follows: Value Description 0x0 Initial device, or a major revision update. 0x1 First metal layer change. 0x2 Second metal layer change. and so on. 7:0 MINOR RO - November 30, 2007 61 Preliminary LM3S6110 Microcontroller Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 This register is responsible for controlling reset conditions after initial power-on reset. Brown-Out Reset Control (PBORCTL) Base 0x400F.E000 Offset 0x030 Type R/W, reset 0x0000.7FFD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved BORIOR reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x0 BOR Interrupt or Reset This bit controls how a BOR event is signaled to the controller. If set, a reset is signaled. Otherwise, an interrupt is signaled. 1 BORIOR R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 62 November 30, 2007 Preliminary System Control Register 3: LDO Power Control (LDOPCTL), offset 0x034 The VADJ field in this register adjusts the on-chip output voltage (VOUT). LDO Power Control (LDOPCTL) Base 0x400F.E000 Offset 0x034 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved VADJ Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0 LDO Output Voltage This field sets the on-chip output voltage. The programming values for the VADJ field are provided below. Value VOUT (V) 0x00 2.50 0x01 2.45 0x02 2.40 0x03 2.35 0x04 2.30 0x05 2.25 0x06-0x3F Reserved 0x1B 2.75 0x1C 2.70 0x1D 2.65 0x1E 2.60 0x1F 2.55 5:0 VADJ R/W 0x0 November 30, 2007 63 Preliminary LM3S6110 Microcontroller Register 4: Raw Interrupt Status (RIS), offset 0x050 Central location for system control raw interrupts. These are set and cleared by hardware. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PLLLRIS reserved BORRIS reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0 PLL Lock Raw Interrupt Status This bit is set when the PLL TREADY Timer asserts. 6 PLLLRIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:2 reserved RO 0 Brown-Out Reset Raw Interrupt Status This bit is the raw interrupt status for any brown-out conditions. If set, a brown-out condition is currently active. This is an unregistered signal from the brown-out detection circuit. An interrupt is reported if the BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL register is cleared. 1 BORRIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 64 November 30, 2007 Preliminary System Control Register 5: Interrupt Mask Control (IMC), offset 0x054 Central location for system control interrupt masks. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PLLLIM reserved BORIM reserved Type RO RO RO RO RO RO RO RO RO R/W RO RO RO RO R/W RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0 PLL Lock Interrupt Mask This bit specifies whether a current limit detection is promoted to a controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set; otherwise, an interrupt is not generated. 6 PLLLIM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:2 reserved RO 0 Brown-Out Reset Interrupt Mask This bit specifies whether a brown-out condition is promoted to a controller interrupt. If set, an interrupt is generated if BORRIS is set; otherwise, an interrupt is not generated. 1 BORIM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 November 30, 2007 65 Preliminary LM3S6110 Microcontroller Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 Central location for system control result of RIS AND IMC to generate an interrupt to the controller. All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register (see page 64). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PLLLMIS reserved BORMIS reserved Type RO RO RO RO RO RO RO RO RO R/W1C RO RO RO RO R/W1C RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0 PLL Lock Masked Interrupt Status This bit is set when the PLL TREADY timer asserts. The interrupt is cleared by writing a 1 to this bit. 6 PLLLMIS R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:2 reserved RO 0 BOR Masked Interrupt Status The BORMIS is simply the BORRIS ANDed with the mask value, BORIM. 1 BORMIS R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 66 November 30, 2007 Preliminary System Control Register 7: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an external reset is the cause, and then all the other bits in the RESC register are cleared. Reset Cause (RESC) Base 0x400F.E000 Offset 0x05C Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved LDO SW WDT BOR POR EXT Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0 LDO Reset When set, indicates the LDO circuit has lost regulation and has generated a reset event. 5 LDO R/W - Software Reset When set, indicates a software reset is the cause of the reset event. 4 SW R/W - Watchdog Timer Reset When set, indicates a watchdog reset is the cause of the reset event. 3 WDT R/W - Brown-Out Reset When set, indicates a brown-out reset is the cause of the reset event. 2 BOR R/W - Power-On Reset When set, indicates a power-on reset is the cause of the reset event. 1 POR R/W - External Reset When set, indicates an external reset (RST assertion) is the cause of the reset event. 0 EXT R/W - November 30, 2007 67 Preliminary LM3S6110 Microcontroller Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 This register is defined to provide source control and frequency speed. Run-Mode Clock Configuration (RCC) Base 0x400F.E000 Offset 0x060 Type R/W, reset 0x07AE.3AD1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved ACG SYSDIV USESYSDIV reserved USEPWMDIV PWMDIV reserved Type RO RO RO RO R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W RO Reset 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PWRDN reserved BYPASS reserved XTAL OSCSRC reserved IOSCDIS MOSCDIS Type RO RO R/W RO R/W RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W Reset 0 0 1 1 1 0 1 0 1 1 0 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:28 reserved RO 0x0 Auto Clock Gating This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers if the controller enters a Sleep or Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating Control (RCGCn) registers are used when the controller enters a sleep mode. The RCGCn registers are always used to control the clocks in Run mode. This allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused. 27 ACG R/W 0 68 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output. The PLL VCO frequency is 400 MHz. Value Divisor (BYPASS=1) Frequency (BYPASS=0) 0x0 reserved reserved 0x1 /2 reserved 0x2 /3 reserved 0x3 /4 reserved 0x4 /5 reserved 0x5 /6 reserved 0x6 /7 reserved 0x7 /8 25 MHz 0x8 /9 22.22 MHz 0x9 /10 20 MHz 0xA /11 18.18 MHz 0xB /12 16.67 MHz 0xC /13 15.38 MHz 0xD /14 14.29 MHz 0xE /15 13.33 MHz 0xF /16 12.5 MHz (default) When reading the Run-Mode Clock Configuration (RCC) register (see page 68), the SYSDIV value is MINSYSDIV if a lower divider was requested and the PLL is being used. This lower value is allowed to divide a non-PLL source. 26:23 SYSDIV R/W 0xF Enable System Clock Divider Use the system clock divider as the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. 22 USESYSDIV R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 21 reserved RO 0 Enable PWM Clock Divisor Use the PWM clock divider as the source for the PWM clock. 20 USEPWMDIV R/W 0 November 30, 2007 69 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description PWM Unit Clock Divisor This field specifies the binary divisor used to predivide the system clock down for use as the timing reference for the PWM module. This clock is only power 2 divide and rising edge is synchronous without phase shift from the system clock. Value Divisor 0x0 /2 0x1 /4 0x2 /8 0x3 /16 0x4 /32 0x5 /64 0x6 /64 0x7 /64 (default) 19:17 PWMDIV R/W 0x7 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16:14 reserved RO 0 PLL Power Down This bit connects to the PLL PWRDN input. The reset value of 1 powers down the PLL. 13 PWRDN R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 reserved RO 1 PLL Bypass Chooses whether the system clock is derived from the PLL output or the OSC source. If set, the clock that drives the system is the OSC source. Otherwise, the clock that drives the system is the PLL output clock divided by the system divider. 11 BYPASS R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 reserved RO 0 70 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description Crystal Value This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided below. Crystal Frequency (MHz) Using the PLL Crystal Frequency (MHz) Not Using the PLL Value 0x0 1.000 reserved 0x1 1.8432 reserved 0x2 2.000 reserved 0x3 2.4576 reserved 0x4 3.579545 MHz 0x5 3.6864 MHz 0x6 4 MHz 0x7 4.096 MHz 0x8 4.9152 MHz 0x9 5 MHz 0xA 5.12 MHz 0xB 6 MHz (reset value) 0xC 6.144 MHz 0xD 7.3728 MHz 0xE 8 MHz 0xF 8.192 MHz 9:6 XTAL R/W 0xB Oscillator Source Picks among the four input sources for the OSC. The values are: Value Input Source 0x0 Main oscillator (default) 0x1 Internal oscillator (default) 0x2 Internal oscillator / 4 (this is necessary if used as input to PLL) 0x3 reserved 5:4 OSCSRC R/W 0x1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0x0 Internal Oscillator Disable 0: Internal oscillator (IOSC) is enabled. 1: Internal oscillator is disabled. 1 IOSCDIS R/W 0 Main Oscillator Disable 0: Main oscillator is enabled. 1: Main oscillator is disabled (default). 0 MOSCDIS R/W 1 November 30, 2007 71 Preliminary LM3S6110 Microcontroller Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 68). The PLL frequency is calculated using the PLLCFG field values, as follows: PLLFreq = OSCFreq * F / (R + 1) XTAL to PLL Translation (PLLCFG) Base 0x400F.E000 Offset 0x064 Type RO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved F R Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 - - - - - - - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:14 reserved RO 0x0 PLL F Value This field specifies the value supplied to the PLL’s F input. 13:5 F RO - PLL R Value This field specifies the value supplied to the PLL’s R input. 4:0 R RO - 72 November 30, 2007 Preliminary System Control Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 This register overrides the RCC equivalent register fields when the USERCC2 bit is set. This allows RCC2 to be used to extend the capabilities, while also providing a means to be backward-compatible to previous parts. The fields within the RCC2 register occupy the same bit positions as they do within the RCC register as LSB-justified. The SYSDIV2 field is wider so that additional larger divisors are possible. This allows a lower system clock frequency for improved Deep Sleep power consumption. Run-Mode Clock Configuration 2 (RCC2) Base 0x400F.E000 Offset 0x070 Type R/W, reset 0x0780.2800 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 USERCC2 reserved SYSDIV2 reserved Type R/W RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PWRDN2 reserved BYPASS2 reserved OSCSRC2 reserved Type RO RO R/W RO R/W RO RO RO RO R/W R/W R/W RO RO RO RO Reset 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Use RCC2 When set, overrides the RCC register fields. 31 USERCC2 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30:29 reserved RO 0x0 System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output. The PLL VCO frequency is 400 MHz. This field is wider than the RCC register SYSDIV field in order to provide additional divisor values. This permits the system clock to be run at much lower frequencies during Deep Sleep mode. For example, where the RCC register SYSDIV encoding of 1111 provides /16, the RCC2 register SYSDIV2 encoding of 111111 provides /64. 28:23 SYSDIV2 R/W 0x0F Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:14 reserved RO 0x0 Power-Down PLL When set, powers down the PLL. 13 PWRDN2 R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 reserved RO 0 Bypass PLL When set, bypasses the PLL for the clock source. 11 BYPASS2 R/W 1 November 30, 2007 73 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10:7 reserved RO 0x0 System Clock Source Value Description 0x0 Main oscillator (MOSC) 0x1 Internal oscillator (IOSC) 0x2 Internal oscillator / 4 0x3 30 kHz internal oscillator 0x7 32 kHz external oscillator 6:4 OSCSRC2 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0 74 November 30, 2007 Preliminary System Control Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F.E000 Offset 0x144 Type R/W, reset 0x0780.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved DSDIVORIDE reserved Type RO RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DSOSCSRC reserved Type RO RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:29 reserved RO 0x0 Divider Field Override 6-bit system divider field to override when Deep-Sleep occurs with PLL running. 28:23 DSDIVORIDE R/W 0x0F Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:7 reserved RO 0x0 Clock Source When set, forces IOSC to be clock source during Deep Sleep mode. Value Name Description 0x0 NOORIDE No override to the oscillator clock source is done 0x1 IOSC Use internal 12 MHz oscillator as source 0x3 30kHz Use 30 kHz internal oscillator 0x7 32kHz Use 32 kHz external oscillator 6:4 DSOSCSRC R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0x0 November 30, 2007 75 Preliminary LM3S6110 Microcontroller Register 12: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, pin count, and package type. Device Identification 1 (DID1) Base 0x400F.E000 Offset 0x004 Type RO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VER FAM PARTNO Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 1 0 0 0 0 0 1 1 1 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PINCOUNT reserved TEMP PKG ROHS QUAL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 0 0 0 0 0 0 0 0 1 0 1 1 - - Bit/Field Name Type Reset Description DID1 Version This field defines the DID1 register format version. The version number is numeric. The value of the VER field is encoded as follows (all other encodings are reserved): Value Description First revision of the DID1 register format, indicating a Stellaris Fury-class device. 0x1 31:28 VER RO 0x1 Family This field provides the family identification of the device within the Luminary Micro product portfolio. The value is encoded as follows (all other encodings are reserved): Value Description Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S. 0x0 27:24 FAM RO 0x0 Part Number This field provides the part number of the device within the family. The value is encoded as follows (all other encodings are reserved): Value Description 0x74 LM3S6110 23:16 PARTNO RO 0x74 Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): Value Description 0x2 100-pin package 15:13 PINCOUNT RO 0x2 76 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12:8 reserved RO 0 Temperature Range This field specifies the temperature rating of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x1 Industrial temperature range (-40°C to 85°C) 7:5 TEMP RO 0x1 Package Type This field specifies the package type. The value is encoded as follows (all other encodings are reserved): Value Description 0x1 LQFP package 4:3 PKG RO 0x1 RoHS-Compliance This bit specifies whether the device is RoHS-compliant. A 1 indicates the part is RoHS-compliant. 2 ROHS RO 1 Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Engineering Sample (unqualified) 0x1 Pilot Production (unqualified) 0x2 Fully Qualified 1:0 QUAL RO - November 30, 2007 77 Preliminary LM3S6110 Microcontroller Register 13: Device Capabilities 0 (DC0), offset 0x008 This register is predefined by the part and can be used to verify features. Device Capabilities 0 (DC0) Base 0x400F.E000 Offset 0x008 Type RO, reset 0x003F.001F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRAMSZ Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLASHSZ Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 Bit/Field Name Type Reset Description SRAM Size Indicates the size of the on-chip SRAM memory. Value Description 0x003F 16 KB of SRAM 31:16 SRAMSZ RO 0x003F Flash Size Indicates the size of the on-chip flash memory. Value Description 0x001F 64 KB of Flash 15:0 FLASHSZ RO 0x001F 78 November 30, 2007 Preliminary System Control Register 14: Device Capabilities 1 (DC1), offset 0x010 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: CANs, PWM, ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the maximum clock frequency and maximum ADC sample rate. The format of this register is consistent with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control register. Device Capabilities 1 (DC1) Base 0x400F.E000 Offset 0x010 Type RO, reset 0x0010.709F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved PWM reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MINSYSDIV reserved MPU reserved PLL WDT SWO SWD JTAG Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 1 1 0 0 0 0 1 0 0 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:21 reserved RO 0 PWM Module Present When set, indicates that the PWM module is present. 20 PWM RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:16 reserved RO 0 System Clock Divider Minimum 4-bit divider value for system clock. The reset value is hardware-dependent. See the RCC register for how to change the system clock divisor using the SYSDIV bit. Value Description 0x7 Specifies a 25-MHz clock with a PLL divider of 8. 15:12 MINSYSDIV RO 0x7 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:8 reserved RO 0 MPU Present When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the ARM Cortex-M3 Technical Reference Manual for details on the MPU. 7 MPU RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:5 reserved RO 0 November 30, 2007 79 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description PLL Present When set, indicates that the on-chip Phase Locked Loop (PLL) is present. 4 PLL RO 1 Watchdog Timer Present When set, indicates that a watchdog timer is present. 3 WDT RO 1 SWO Trace Port Present When set, indicates that the Serial Wire Output (SWO) trace port is present. 2 SWO RO 1 SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present. 1 SWD RO 1 JTAG Present When set, indicates that the JTAG debugger interface is present. 0 JTAG RO 1 80 November 30, 2007 Preliminary System Control Register 15: Device Capabilities 2 (DC2), offset 0x014 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software reset control register. Device Capabilities 2 (DC2) Base 0x400F.E000 Offset 0x014 Type RO, reset 0x0707.0011 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SSI0 reserved UART0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Present When set, indicates that analog comparator 2 is present. 26 COMP2 RO 1 Analog Comparator 1 Present When set, indicates that analog comparator 1 is present. 25 COMP1 RO 1 Analog Comparator 0 Present When set, indicates that analog comparator 0 is present. 24 COMP0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:19 reserved RO 0 Timer 2 Present When set, indicates that General-Purpose Timer module 2 is present. 18 TIMER2 RO 1 Timer 1 Present When set, indicates that General-Purpose Timer module 1 is present. 17 TIMER1 RO 1 Timer 0 Present When set, indicates that General-Purpose Timer module 0 is present. 16 TIMER0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:5 reserved RO 0 SSI0 Present When set, indicates that SSI module 0 is present. 4 SSI0 RO 1 November 30, 2007 81 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:1 reserved RO 0 UART0 Present When set, indicates that UART module 0 is present. 0 UART0 RO 1 82 November 30, 2007 Preliminary System Control Register 16: Device Capabilities 3 (DC3), offset 0x018 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os. Device Capabilities 3 (DC3) Base 0x400F.E000 Offset 0x018 Type RO, reset 0x0F00.B7C3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved CCP3 CCP2 CCP1 CCP0 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWMFAULT reserved C2PLUS C2MINUS reserved C1PLUS C1MINUS C0O C0PLUS C0MINUS reserved PWM1 PWM0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 0 1 1 0 1 1 1 1 1 0 0 0 0 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:28 reserved RO 0 CCP3 Pin Present When set, indicates that Capture/Compare/PWM pin 3 is present. 27 CCP3 RO 1 CCP2 Pin Present When set, indicates that Capture/Compare/PWM pin 2 is present. 26 CCP2 RO 1 CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin 1 is present. 25 CCP1 RO 1 CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin 0 is present. 24 CCP0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:16 reserved RO 0 PWM Fault Pin Present When set, indicates that the PWM Fault pin is present. 15 PWMFAULT RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 reserved RO 0 C2+ Pin Present When set, indicates that the analog comparator 2 (+) input pin is present. 13 C2PLUS RO 1 C2- Pin Present When set, indicates that the analog comparator 2 (-) input pin is present. 12 C2MINUS RO 1 November 30, 2007 83 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 reserved RO 0 C1+ Pin Present When set, indicates that the analog comparator 1 (+) input pin is present. 10 C1PLUS RO 1 C1- Pin Present When set, indicates that the analog comparator 1 (-) input pin is present. 9 C1MINUS RO 1 C0o Pin Present When set, indicates that the analog comparator 0 output pin is present. 8 C0O RO 1 C0+ Pin Present When set, indicates that the analog comparator 0 (+) input pin is present. 7 C0PLUS RO 1 C0- Pin Present When set, indicates that the analog comparator 0 (-) input pin is present. 6 C0MINUS RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:2 reserved RO 0 PWM1 Pin Present When set, indicates that the PWM pin 1 is present. 1 PWM1 RO 1 PWM0 Pin Present When set, indicates that the PWM pin 0 is present. 0 PWM0 RO 1 84 November 30, 2007 Preliminary System Control Register 17: Device Capabilities 4 (DC4), offset 0x01C This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Ethernet MAC and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2, and DCGC2 clock control registers and the SRCR2 software reset control register. Device Capabilities 4 (DC4) Base 0x400F.E000 Offset 0x01C Type RO, reset 0x5000.007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved EPHY0 reserved EMAC0 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 Ethernet PHY0 Present When set, indicates that Ethernet PHY module 0 is present. 30 EPHY0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 reserved RO 0 Ethernet MAC0 Present When set, indicates that Ethernet MAC module 0 is present. 28 EMAC0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:7 reserved RO 0 GPIO Port G Present When set, indicates that GPIO Port G is present. 6 GPIOG RO 1 GPIO Port F Present When set, indicates that GPIO Port F is present. 5 GPIOF RO 1 GPIO Port E Present When set, indicates that GPIO Port E is present. 4 GPIOE RO 1 GPIO Port D Present When set, indicates that GPIO Port D is present. 3 GPIOD RO 1 GPIO Port C Present When set, indicates that GPIO Port C is present. 2 GPIOC RO 1 November 30, 2007 85 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description GPIO Port B Present When set, indicates that GPIO Port B is present. 1 GPIOB RO 1 GPIO Port A Present When set, indicates that GPIO Port A is present. 0 GPIOA RO 1 86 November 30, 2007 Preliminary System Control Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 0 (RCGC0) Base 0x400F.E000 Offset 0x100 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved PWM reserved Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WDT reserved Type RO RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:21 reserved RO 0 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 20 PWM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:4 reserved RO 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 November 30, 2007 87 Preliminary LM3S6110 Microcontroller Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 0 (SCGC0) Base 0x400F.E000 Offset 0x110 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved PWM reserved Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WDT reserved Type RO RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:21 reserved RO 0 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 20 PWM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:4 reserved RO 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 88 November 30, 2007 Preliminary System Control Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 0 (DCGC0) Base 0x400F.E000 Offset 0x120 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved PWM reserved Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WDT reserved Type RO RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:21 reserved RO 0 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 20 PWM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:4 reserved RO 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 November 30, 2007 89 Preliminary LM3S6110 Microcontroller Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 1 (RCGC1) Base 0x400F.E000 Offset 0x104 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SSI0 reserved UART0 Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 26 COMP2 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:19 reserved RO 0 90 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 18 TIMER2 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:5 reserved RO 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:1 reserved RO 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 November 30, 2007 91 Preliminary LM3S6110 Microcontroller Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 1 (SCGC1) Base 0x400F.E000 Offset 0x114 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SSI0 reserved UART0 Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 26 COMP2 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:19 reserved RO 0 92 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 18 TIMER2 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:5 reserved RO 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:1 reserved RO 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 November 30, 2007 93 Preliminary LM3S6110 Microcontroller Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 1 (DCGC1) Base 0x400F.E000 Offset 0x124 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SSI0 reserved UART0 Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 26 COMP2 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:19 reserved RO 0 94 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 18 TIMER2 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:5 reserved RO 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:1 reserved RO 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 November 30, 2007 95 Preliminary LM3S6110 Microcontroller Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 2 (RCGC2) Base 0x400F.E000 Offset 0x108 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved EPHY0 reserved EMAC0 reserved Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 30 EPHY0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 reserved RO 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 28 EMAC0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:7 reserved RO 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 6 GPIOG R/W 0 96 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 November 30, 2007 97 Preliminary LM3S6110 Microcontroller Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 2 (SCGC2) Base 0x400F.E000 Offset 0x118 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved EPHY0 reserved EMAC0 reserved Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 30 EPHY0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 reserved RO 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 28 EMAC0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:7 reserved RO 0 98 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 6 GPIOG R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 November 30, 2007 99 Preliminary LM3S6110 Microcontroller Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Base 0x400F.E000 Offset 0x128 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved EPHY0 reserved EMAC0 reserved Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 30 EPHY0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 reserved RO 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 28 EMAC0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:7 reserved RO 0 100 November 30, 2007 Preliminary System Control Bit/Field Name Type Reset Description Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 6 GPIOG R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 November 30, 2007 101 Preliminary LM3S6110 Microcontroller Register 27: Software Reset Control 0 (SRCR0), offset 0x040 Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register. Software Reset Control 0 (SRCR0) Base 0x400F.E000 Offset 0x040 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved PWM reserved Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WDT reserved Type RO RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:21 reserved RO 0 PWM Reset Control Reset control for PWM module. 20 PWM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:4 reserved RO 0 WDT Reset Control Reset control for Watchdog unit. 3 WDT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 102 November 30, 2007 Preliminary System Control Register 28: Software Reset Control 1 (SRCR1), offset 0x044 Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register. Software Reset Control 1 (SRCR1) Base 0x400F.E000 Offset 0x044 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SSI0 reserved UART0 Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comp 2 Reset Control Reset control for analog comparator 2. 26 COMP2 R/W 0 Analog Comp 1 Reset Control Reset control for analog comparator 1. 25 COMP1 R/W 0 Analog Comp 0 Reset Control Reset control for analog comparator 0. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:19 reserved RO 0 Timer 2 Reset Control Reset control for General-Purpose Timer module 2. 18 TIMER2 R/W 0 Timer 1 Reset Control Reset control for General-Purpose Timer module 1. 17 TIMER1 R/W 0 Timer 0 Reset Control Reset control for General-Purpose Timer module 0. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:5 reserved RO 0 SSI0 Reset Control Reset control for SSI unit 0. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:1 reserved RO 0 November 30, 2007 103 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description UART0 Reset Control Reset control for UART unit 0. 0 UART0 R/W 0 104 November 30, 2007 Preliminary System Control Register 29: Software Reset Control 2 (SRCR2), offset 0x048 Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register. Software Reset Control 2 (SRCR2) Base 0x400F.E000 Offset 0x048 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved EPHY0 reserved EMAC0 reserved Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 PHY0 Reset Control Reset control for Ethernet PHY unit 0. 30 EPHY0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 reserved RO 0 MAC0 Reset Control Reset control for Ethernet MAC unit 0. 28 EMAC0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:7 reserved RO 0 Port G Reset Control Reset control for GPIO Port G. 6 GPIOG R/W 0 Port F Reset Control Reset control for GPIO Port F. 5 GPIOF R/W 0 Port E Reset Control Reset control for GPIO Port E. 4 GPIOE R/W 0 Port D Reset Control Reset control for GPIO Port D. 3 GPIOD R/W 0 Port C Reset Control Reset control for GPIO Port C. 2 GPIOC R/W 0 Port B Reset Control Reset control for GPIO Port B. 1 GPIOB R/W 0 November 30, 2007 105 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description Port A Reset Control Reset control for GPIO Port A. 0 GPIOA R/W 0 106 November 30, 2007 Preliminary System Control 7 Internal Memory The LM3S6110 microcontroller comes with 16 KB of bit-banded SRAM and 64 KB of flash memory. The flash controller provides a user-friendly interface, making flash programming a simple task. Flash protection can be applied to the flash memory on a 2-KB block basis. 7.1 Block Diagram Figure 7-1. Flash Block Diagram Flash Control FMA FCMISC FCIM FCRIS FMC FMD Flash Timing USECRL Flash Protection FMPREn FMPPEn Flash Array SRAM Array Bridge Cortex-M3 ICode DCode System Bus APB User Registers USER_REG0 USER_REG1 USER_DBG 7.2 Functional Description This section describes the functionality of both the flash and SRAM memories. 7.2.1 SRAM Memory The internal SRAM of the Stellaris® devices is located at address 0x2000.0000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. The bit-band alias is calculated by using the formula: November 30, 2007 107 Preliminary LM3S6110 Microcontroller bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows direct access to only bit 3 of the byte at address 0x2000.1000. For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3 Technical Reference Manual. 7.2.2 Flash Memory The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB blocks that can be individually protected. The protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. See also “Serial Flash Loader” on page 430 for a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. 7.2.2.1 Flash Memory Timing The timing for the flash is automatically handled by the flash controller. However, in order to do so, it must know the clock rate of the system in order to time its internal signals properly. The number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. It is software's responsibility to keep the flash controller updated with this information via the USec Reload (USECRL) register. On reset, the USECRL register is loaded with a value that configures the flash timing so that it works with the maximum clock rate of the part. If software changes the system operating frequency, the new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value of 0x13 (20-1) must be written to the USECRL register. 7.2.2.2 Flash Memory Protection The user is provided two forms of flash protection per 2-KB flash blocks in one pair of 32-bit wide registers. The protection policy for each form is controlled by individual bits (per policy per block) in the FMPPEn and FMPREn registers. ■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed (written) or erased. If cleared, the block may not be changed. ■ Flash Memory Protection Read Enable (FMPREn): If set, the block may be executed or read by software or debuggers. If cleared, the block may only be executed. The contents of the memory block are prohibited from being accessed as data and traversing the DCode bus. The policies may be combined as shown in Table 7-1 on page 109. 108 November 30, 2007 Preliminary Internal Memory Table 7-1. Flash Protection Policy Combinations FMPPEn FMPREn Protection Execute-only protection. The block may only be executed and may not be written or erased. This mode is used to protect code. 0 0 1 0 The block may be written, erased or executed, but not read. This combination is unlikely to be used. Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. 0 1 1 1 No protection. The block may be written, erased, executed or read. An access that attempts to program or erase a PE-protected block is prohibited. A controller interrupt may be optionally generated (by setting the AMASK bit in the FIM register) to alert software developers of poorly behaving software during the development and debug phases. An access that attempts to read an RE-protected block is prohibited. Such accesses return data filled with all 0s. A controller interrupt may be optionally generated to alert software developers of poorly behaving software during the development and debug phases. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This implements a policy of open access and programmability. The register bits may be changed by writing the specific register bit. The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. Details on programming these bits are discussed in “Nonvolatile Register Programming” on page 110. 7.3 Flash Memory Initialization and Configuration 7.3.1 Flash Programming The Stellaris® devices provide a user-friendly interface for flash programming. All erase/program operations are handled via three registers: FMA, FMD, and FMC. 7.3.1.1 To program a 32-bit word 1. Write source data to the FMD register. 2. Write the target address to the FMA register. 3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register. 4. Poll the FMC register until the WRITE bit is cleared. 7.3.1.2 To perform an erase of a 1-KB page 1. Write the page address to the FMA register. 2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register. 3. Poll the FMC register until the ERASE bit is cleared. 7.3.1.3 To perform a mass erase of the flash 1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register. 2. Poll the FMC register until the MERASE bit is cleared. November 30, 2007 109 Preliminary LM3S6110 Microcontroller 7.3.2 Nonvolatile Register Programming This section discusses how to update registers that are resident within the flash memory itself. These registers exist in a separate space from the main flash array and are not affected by an ERASE or MASS ERASE operation. These nonvolatile registers are updated by using the COMT bit in the FMC register to activate a write operation. For the USER_DBG register, the data to be written must be loaded into the FMD register before it is "committed". All other registers are R/W and can have their operation tried before committing them to nonvolatile memory. Important: These registers can only have bits changed from 1 to 0 by the user and there is no mechanism for the user to erase them back to a 1 value. In addition, the USER_REG0, USER_REG1, and USER_DBG use bit 31 (NW) of their respective registers to indicate that they are available for user write. These three registers can only be written once whereas the flash protection registers may be written multiple times. Table 7-2 on page 110 provides the FMA address required for commitment of each of the registers and the source of the data to be written when the COMT bit of the FMC register is written with a value of 0xA442.0008. After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to complete. Table 7-2. Flash Resident Registersa Register to be Committed FMA Value Data Source FMPRE0 0x0000.0000 FMPRE0 FMPRE1 0x0000.0002 FMPRE1 FMPRE2 0x0000.0004 FMPRE2 FMPRE3 0x0000.0008 FMPRE3 FMPPE0 0x0000.0001 FMPPE0 FMPPE1 0x0000.0003 FMPPE1 FMPPE2 0x0000.0005 FMPPE2 FMPPE3 0x0000.0007 FMPPE3 USER_REG0 0x8000.0000 USER_REG0 USER_REG1 0x8000.0001 USER_REG1 USER_DBG 0x7510.0000 FMD a. Which FMPREn and FMPPEn registers are available depend on the flash size of your particular Stellaris® device. 7.4 Register Map Table 7-3 on page 110 lists the Flash memory and control registers. The offset listed is a hexadecimal increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash control base address of 0x400F.D000. The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the System Control base address of 0x400F.E000. Table 7-3. Flash Register Map See Offset Name Type Reset Description page Flash Control Offset 0x000 FMA R/W 0x0000.0000 Flash Memory Address 112 110 November 30, 2007 Preliminary Internal Memory See Offset Name Type Reset Description page 0x004 FMD R/W 0x0000.0000 Flash Memory Data 113 0x008 FMC R/W 0x0000.0000 Flash Memory Control 114 0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 116 0x010 FCIM R/W 0x0000.0000 Flash Controller Interrupt Mask 117 0x014 FCMISC R/W1C 0x0000.0000 Flash Controller Masked Interrupt Status and Clear 118 System Control Offset 0x130 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 120 0x200 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 120 0x134 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 121 0x400 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 121 0x140 USECRL R/W 0x16 USec Reload 119 0x1D0 USER_DBG R/W 0xFFFF.FFFE User Debug 122 0x1E0 USER_REG0 R/W 0xFFFF.FFFF User Register 0 123 0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 124 0x204 FMPRE1 R/W 0x0000.0000 Flash Memory Protection Read Enable 1 125 0x208 FMPRE2 R/W 0x0000.0000 Flash Memory Protection Read Enable 2 126 0x20C FMPRE3 R/W 0x0000.0000 Flash Memory Protection Read Enable 3 127 0x404 FMPPE1 R/W 0x0000.0000 Flash Memory Protection Program Enable 1 128 0x408 FMPPE2 R/W 0x0000.0000 Flash Memory Protection Program Enable 2 129 0x40C FMPPE3 R/W 0x0000.0000 Flash Memory Protection Program Enable 3 130 7.5 Flash Register Descriptions (Flash Control Offset) The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000. November 30, 2007 111 Preliminary LM3S6110 Microcontroller Register 1: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned address and specifies which page is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable. Flash Memory Address (FMA) Base 0x400F.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0 Address Offset Address offset in flash where operation is performed, except for nonvolatile registers (see “Nonvolatile Register Programming” on page 110 for details on values for this field). 15:0 OFFSET R/W 0x0 112 November 30, 2007 Preliminary Internal Memory Register 2: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during the erase cycles. Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Data Value Data value for write operation. 31:0 DATA R/W 0x0 November 30, 2007 113 Preliminary LM3S6110 Microcontroller Register 3: Flash Memory Control (FMC), offset 0x008 When this register is written, the flash controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 112). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 113) is written. This is the final register written and initiates the memory operation. There are four control bits in the lower byte of this register that, when set, initiate the memory operation. The most used of these register bits are the ERASE and WRITE bits. It is a programming error to write multiple control bits and the results of such an operation are unpredictable. Flash Memory Control (FMC) Base 0x400F.D000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WRKEY Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved COMT MERASE ERASE WRITE Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Flash Write Key This field contains a write key, which is used to minimize the incidence of accidental flash writes. The value 0xA442 must be written into this field for a write to occur. Writes to the FMC register without this WRKEY value are ignored. A read of this field returns the value 0. 31:16 WRKEY WO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:4 reserved RO 0x0 Commit Register Value Commit (write) of register value to nonvolatile storage. A write of 0 has no effect on the state of this bit. If read, the state of the previous commit access is provided. If the previous commit access is complete, a 0 is returned; otherwise, if the commit access is not complete, a 1 is returned. This can take up to 50 μs. 3 COMT R/W 0 Mass Erase Flash Memory If this bit is set, the flash main memory of the device is all erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous mass erase access is provided. If the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned. This can take up to 250 ms. 2 MERASE R/W 0 114 November 30, 2007 Preliminary Internal Memory Bit/Field Name Type Reset Description Erase a Page of Flash Memory If this bit is set, the page of flash main memory as specified by the contents of FMA is erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous erase access is provided. If the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned. This can take up to 25 ms. 1 ERASE R/W 0 Write a Word into Flash Memory If this bit is set, the data stored in FMD is written into the location as specified by the contents of FMA. A write of 0 has no effect on the state of this bit. If read, the state of the previous write update is provided. If the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. This can take up to 50 μs. 0 WRITE R/W 0 November 30, 2007 115 Preliminary LM3S6110 Microcontroller Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled if the corresponding FCIM register bit is set. Flash Controller Raw Interrupt Status (FCRIS) Base 0x400F.D000 Offset 0x00C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PRIS ARIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 Programming Raw Interrupt Status This bit indicates the current state of the programming cycle. If set, the programming cycle completed; if cleared, the programming cycle has not completed. Programming cycles are either write or erase actions generated through the Flash Memory Control (FMC) register bits (see page 114). 1 PRIS RO 0 Access Raw Interrupt Status This bit indicates if the flash was improperly accessed. If set, the program tried to access the flash counter to the policy as set in the Flash Memory Protection Read Enable (FMPREn) and Flash Memory Protection Program Enable (FMPPEn) registers. Otherwise, no access has tried to improperly access the flash. 0 ARIS RO 0 116 November 30, 2007 Preliminary Internal Memory Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the flash controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PMASK AMASK Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the controller. If set, a programming-generated interrupt is promoted to the controller. Otherwise, interrupts are recorded but suppressed from the controller. 1 PMASK R/W 0 Access Interrupt Mask This bit controls the reporting of the access raw interrupt status to the controller. If set, an access-generated interrupt is promoted to the controller. Otherwise, interrupts are recorded but suppressed from the controller. 0 AMASK R/W 0 November 30, 2007 117 Preliminary LM3S6110 Microcontroller Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Base 0x400F.D000 Offset 0x014 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PMISC AMISC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 Programming Masked Interrupt Status and Clear This bit indicates whether an interrupt was signaled because a programming cycle completed and was not masked. This bit is cleared by writing a 1. The PRIS bit in the FCRIS register (see page 116) is also cleared when the PMISC bit is cleared. 1 PMISC R/W1C 0 Access Masked Interrupt Status and Clear This bit indicates whether an interrupt was signaled because an improper access was attempted and was not masked. This bit is cleared by writing a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC bit is cleared. 0 AMISC R/W1C 0 7.6 Flash Register Descriptions (System Control Offset) The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000. 118 November 30, 2007 Preliminary Internal Memory Register 7: USec Reload (USECRL), offset 0x140 Note: Offset is relative to System Control base address of 0x400F.E000 This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller. The internal flash has specific minimum and maximum requirements on the length of time the high voltage write pulse can be applied. It is required that this register contain the operating frequency (in MHz -1) whenever the flash is being erased or programmed. The user is required to change this value if the clocking conditions are changed for a flash erase/program operation. USec Reload (USECRL) Base 0x400F.E000 Offset 0x140 Type R/W, reset 0x16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved USEC Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Microsecond Reload Value MHz -1 of the controller clock when the flash is being erased or programmed. USEC should be set to 0x18 (24 MHz) whenever the flash is being erased or programmed. 7:0 USEC R/W 0x18 November 30, 2007 119 Preliminary LM3S6110 Microcontroller Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 0 (FMPRE0) Base 0x400F.D000 Offset 0x130 and 0x200 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 64 KB of flash. 31:0 READ_ENABLE R/W 0xFFFFFFFF 120 November 30, 2007 Preliminary Internal Memory Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 0 (FMPPE0) Base 0x400F.D000 Offset 0x134 and 0x400 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 64 KB of flash. 31:0 PROG_ENABLE R/W 0xFFFFFFFF November 30, 2007 121 Preliminary LM3S6110 Microcontroller Register 10: User Debug (USER_DBG), offset 0x1D0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides a write-once mechanism to disable external debugger access to the device in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0 disables any external debugger access to the device permanently, starting with the next power-up cycle of the device. The NOTWRITTEN bit (bit 31) indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. User Debug (USER_DBG) Base 0x400F.E000 Offset 0x1D0 Type R/W, reset 0xFFFF.FFFE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NW DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA DBG1 DBG0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Bit/Field Name Type Reset Description User Debug Not Written Specifies that this 32-bit dword has not been written. 31 NW R/W 1 User Data Contains the user data value. This field is initialized to all 1s and can only be written once. 30:2 DATA R/W 0x1FFFFFFF Debug Control 1 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 1 DBG1 R/W 1 Debug Control 0 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 0 DBG0 R/W 0 122 November 30, 2007 Preliminary Internal Memory Register 11: User Register 0 (USER_REG0), offset 0x1E0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 0 (USER_REG0) Base 0x400F.E000 Offset 0x1E0 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NW DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Not Written Specifies that this 32-bit dword has not been written. 31 NW R/W 1 User Data Contains the user data value. This field is initialized to all 1s and can only be written once. 30:0 DATA R/W 0x7FFFFFFF November 30, 2007 123 Preliminary LM3S6110 Microcontroller Register 12: User Register 1 (USER_REG1), offset 0x1E4 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 1 (USER_REG1) Base 0x400F.E000 Offset 0x1E4 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NW DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Not Written Specifies that this 32-bit dword has not been written. 31 NW R/W 1 User Data Contains the user data value. This field is initialized to all 1s and can only be written once. 30:0 DATA R/W 0x7FFFFFFF 124 November 30, 2007 Preliminary Internal Memory Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 1 (FMPRE1) Base 0x400F.E000 Offset 0x204 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 64 KB of flash. 31:0 READ_ENABLE R/W 0x00000000 November 30, 2007 125 Preliminary LM3S6110 Microcontroller Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 2 (FMPRE2) Base 0x400F.E000 Offset 0x208 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 64 KB of flash. 31:0 READ_ENABLE R/W 0x00000000 126 November 30, 2007 Preliminary Internal Memory Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 3 (FMPRE3) Base 0x400F.E000 Offset 0x20C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 64 KB of flash. 31:0 READ_ENABLE R/W 0x00000000 November 30, 2007 127 Preliminary LM3S6110 Microcontroller Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 1 (FMPPE1) Base 0x400F.E000 Offset 0x404 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 64 KB of flash. 31:0 PROG_ENABLE R/W 0x00000000 128 November 30, 2007 Preliminary Internal Memory Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 2 (FMPPE2) Base 0x400F.E000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 64 KB of flash. 31:0 PROG_ENABLE R/W 0x00000000 November 30, 2007 129 Preliminary LM3S6110 Microcontroller Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 3 (FMPPE3) Base 0x400F.E000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 64 KB of flash. 31:0 PROG_ENABLE R/W 0x00000000 130 November 30, 2007 Preliminary Internal Memory 8 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, and Port G, ). The GPIO module is FiRM-compliant and supports 8-35 programmable input/output pins, depending on the peripherals being used. The GPIO module has the following features: ■ Programmable control for GPIO interrupts – Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ 5-V-tolerant input/outputs ■ Bit masking in both read and write operations through address lines ■ Programmable control for GPIO pad configuration – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive – Slew rate control for the 8-mA drive – Open drain enables – Digital input enables 8.1 Functional Description Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 8-1 on page 132). The LM3S6110 microcontroller contains seven ports and thus seven of these physical GPIO blocks. November 30, 2007 131 Preliminary LM3S6110 Microcontroller Figure 8-1. GPIO Port Block Diagram Alternate Input Alternate Output Alternate Output Enable Interrupt GPIO Input GPIO Output GPIO Output Enable Pad Output Pad Output Enable Package I/O Pin GPIODATA GPIODIR Data Control GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR Interrupt Control GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN Pad Control GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 Identification Registers GPIOAFSEL Mode Control DEMUX MUX MUX Digital I/O Pad Pad Input GPIOLOCK Commit Control GPIOCR 8.1.1 Data Control The data control registers allow software to configure the operational modes of the GPIOs. The data direction register configures the GPIO as an input or an output while the data register either captures incoming data or drives it out to the pads. 8.1.1.1 Data Direction Operation The GPIO Direction (GPIODIR) register (see page 139) is used to configure each individual pin as an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and the corresponding data register bit will capture and store the value on the GPIO port. When the data direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit will be driven out on the GPIO port. 8.1.1.2 Data Register Operation To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register (see page 138) by using bits [9:2] of the address bus as a mask. This allows software drivers to modify individual GPIO pins in a single instruction, without affecting the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA register covers 256 locations in the memory map. During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA register is altered. If it is cleared to 0, it is left unchanged. 132 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in Figure 8-2 on page 133, where u is data unchanged by the write. Figure 8-2. GPIODATA Write Example 0 0 1 0 0 1 1 0 1 0 u u 1 u u 0 1 u 9 8 7 6 5 4 3 2 1 0 1 1 1 0 1 0 1 1 7 6 5 4 3 2 1 0 GPIODATA 0xEB 0x098 ADDR[9:2] During a read, if the address bit associated with the data bit is set to 1, the value is read. If the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-3 on page 133. Figure 8-3. GPIODATA Read Example 0 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 9 8 7 6 5 4 3 2 1 0 1 0 1 1 1 1 1 0 7 6 5 4 3 2 1 0 Returned Value GPIODATA 0x0C4 ADDR[9:2] 8.1.2 Interrupt Control The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these registers, it is possible to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source holds the level constant for the interrupt to be recognized by the controller. Three registers are required to define the edge or sense that causes interrupts: ■ GPIO Interrupt Sense (GPIOIS) register (see page 140) ■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 141) ■ GPIO Interrupt Event (GPIOIEV) register (see page 142) Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 143). When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers (see page 144 and page 145). As the name implies, the GPIOMIS register only shows interrupt conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller. Interrupts are cleared by writing a 1 to the GPIO Interrupt Clear (GPIOICR) register (see page 146). November 30, 2007 133 Preliminary LM3S6110 Microcontroller When programming the following interrupt control registers, the interrupts should be masked (GPIOIM set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can generate a spurious interrupt if the corresponding bits are enabled. 8.1.3 Mode Control The GPIO pins can be controlled by either hardware or software. When hardware control is enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 147), the pin state is controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO mode, where the GPIODATA register is used to read/write the corresponding pins. 8.1.4 Commit Control The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 147) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 157) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 158) have been set to 1. 8.1.5 Pad Control The pad control registers allow for GPIO pad configuration by software based on the application requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. 8.1.6 Identification The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. 8.2 Initialization and Configuration To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn) in the RCGC2 register. On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 8-1 on page 134 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 8-2 on page 135 shows how a rising edge interrupt would be configured for pin 2 of a GPIO port. Table 8-1. GPIO Pad Configuration Examples Configuration GPIO Register Bit Valuea AFSEL DIR ODR DEN PUR PDR DR2R DR4R DR8R SLR Digital Input (GPIO) 0 0 0 1 ? ? X X X X Digital Output (GPIO) 0 1 0 1 ? ? ? ? ? ? Open Drain Input 0 0 1 1 X X X X X X (GPIO) Open Drain Output 0 1 1 1 X X ? ? ? ? (GPIO) Digital Input (Timer 1 X 0 1 ? ? X X X X CCP) Digital Output (PWM) 1 X 0 1 ? ? ? ? ? ? 134 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Configuration GPIO Register Bit Valuea AFSEL DIR ODR DEN PUR PDR DR2R DR4R DR8R SLR Digital Output (Timer 1 X 0 1 ? ? ? ? ? ? PWM) Digital Input/Output 1 X 0 1 ? ? ? ? ? ? (SSI) Digital Input/Output 1 X 0 1 ? ? ? ? ? ? (UART) Analog Input 0 0 0 0 0 0 X X X X (Comparator) Digital Output 1 X 0 1 ? ? ? ? ? ? (Comparator) a. X=Ignored (don’t care bit) ?=Can be either 0 or 1, depending on the configuration Table 8-2. GPIO Interrupt Configuration Example Desired Pin 2 Bit Valuea Interrupt Event Trigger Register 7 6 5 4 3 2 1 0 0=edge X X X X X 0 X X 1=level GPIOIS 0=single X X X X X 0 X X edge 1=both edges GPIOIBE 0=Low level, X X X X X 1 X X or negative edge 1=High level, or positive edge GPIOIEV 0=masked 0 0 0 0 0 1 0 0 1=not masked GPIOIM a. X=Ignored (don’t care bit) 8.3 Register Map Table 8-3 on page 136 lists the GPIO registers. The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s base address: ■ GPIO Port A: 0x4000.4000 ■ GPIO Port B: 0x4000.5000 ■ GPIO Port C: 0x4000.6000 ■ GPIO Port D: 0x4000.7000 ■ GPIO Port E: 0x4002.4000 November 30, 2007 135 Preliminary LM3S6110 Microcontroller ■ GPIO Port F: 0x4002.5000 ■ GPIO Port G: 0x4002.6000 Important: The GPIO registers in this chapter are duplicated in each GPIO block, however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to those unconnected bits has no effect and reading those unconnected bits returns no meaningful data. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. The default register type for the GPIOCR register is RO for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-commitable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. Table 8-3. GPIO Register Map See Offset Name Type Reset Description page 0x000 GPIODATA R/W 0x0000.0000 GPIO Data 138 0x400 GPIODIR R/W 0x0000.0000 GPIO Direction 139 0x404 GPIOIS R/W 0x0000.0000 GPIO Interrupt Sense 140 0x408 GPIOIBE R/W 0x0000.0000 GPIO Interrupt Both Edges 141 0x40C GPIOIEV R/W 0x0000.0000 GPIO Interrupt Event 142 0x410 GPIOIM R/W 0x0000.0000 GPIO Interrupt Mask 143 0x414 GPIORIS RO 0x0000.0000 GPIO Raw Interrupt Status 144 0x418 GPIOMIS RO 0x0000.0000 GPIO Masked Interrupt Status 145 0x41C GPIOICR W1C 0x0000.0000 GPIO Interrupt Clear 146 0x420 GPIOAFSEL R/W - GPIO Alternate Function Select 147 0x500 GPIODR2R R/W 0x0000.00FF GPIO 2-mA Drive Select 149 0x504 GPIODR4R R/W 0x0000.0000 GPIO 4-mA Drive Select 150 0x508 GPIODR8R R/W 0x0000.0000 GPIO 8-mA Drive Select 151 0x50C GPIOODR R/W 0x0000.0000 GPIO Open Drain Select 152 0x510 GPIOPUR R/W - GPIO Pull-Up Select 153 0x514 GPIOPDR R/W 0x0000.0000 GPIO Pull-Down Select 154 136 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) See Offset Name Type Reset Description page 0x518 GPIOSLR R/W 0x0000.0000 GPIO Slew Rate Control Select 155 0x51C GPIODEN R/W - GPIO Digital Enable 156 0x520 GPIOLOCK R/W 0x0000.0001 GPIO Lock 157 0x524 GPIOCR - - GPIO Commit 158 0xFD0 GPIOPeriphID4 RO 0x0000.0000 GPIO Peripheral Identification 4 160 0xFD4 GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 161 0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 162 0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 163 0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 164 0xFE4 GPIOPeriphID1 RO 0x0000.0000 GPIO Peripheral Identification 1 165 0xFE8 GPIOPeriphID2 RO 0x0000.0018 GPIO Peripheral Identification 2 166 0xFEC GPIOPeriphID3 RO 0x0000.0001 GPIO Peripheral Identification 3 167 0xFF0 GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 168 0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 169 0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 170 0xFFC GPIOPCellID3 RO 0x0000.00B1 GPIO PrimeCell Identification 3 171 8.4 Register Descriptions The remainder of this section lists and describes the GPIO registers, in numerical order by address offset. November 30, 2007 137 Preliminary LM3S6110 Microcontroller Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 139). In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write. Similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the corresponding bits in GPIODATA to be read as 0, regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. GPIO Data (GPIODATA) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DATA Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Data This register is virtually mapped to 256 locations in the address space. To facilitate the reading and writing of data to these registers by independent drivers, the data read from and the data written to the registers are masked by the eight address lines ipaddr[9:2]. Reads from this register return its current state. Writes to this register only affect bits that are not masked by ipaddr[9:2] and are configured as outputs. See “Data Register Operation” on page 132 for examples of reads and writes. 7:0 DATA R/W 0x00 138 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. GPIO Direction (GPIODIR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DIR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Data Direction The DIR values are defined as follows: Value Description 0 Pins are inputs. 1 Pins are outputs. 7:0 DIR R/W 0x00 November 30, 2007 139 Preliminary LM3S6110 Microcontroller Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits are cleared by a reset. GPIO Interrupt Sense (GPIOIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x404 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IS Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Sense The IS values are defined as follows: Value Description 0 Edge on corresponding pin is detected (edge-sensitive). 1 Level on corresponding pin is detected (level-sensitive). 7:0 IS R/W 0x00 140 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 140) is set to detect edges, bits set to High in GPIOIBE configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 142). Clearing a bit configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset. GPIO Interrupt Both Edges (GPIOIBE) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IBE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Both Edges The IBE values are defined as follows: Value Description Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register (see page 142). 0 1 Both edges on the corresponding pin trigger an interrupt. Note: Single edge is determined by the corresponding bit in GPIOIEV. 7:0 IBE R/W 0x00 November 30, 2007 141 Preliminary LM3S6110 Microcontroller Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 140). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are cleared by a reset. GPIO Interrupt Event (GPIOIEV) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IEV Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Event The IEV values are defined as follows: Value Description Falling edge or Low levels on corresponding pins trigger interrupts. 0 Rising edge or High levels on corresponding pins trigger interrupts. 1 7:0 IEV R/W 0x00 142 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin. All bits are cleared by a reset. GPIO Interrupt Mask (GPIOIM) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x410 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IME Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Mask Enable The IME values are defined as follows: Value Description 0 Corresponding pin interrupt is masked. 1 Corresponding pin interrupt is not masked. 7:0 IME R/W 0x00 November 30, 2007 143 Preliminary LM3S6110 Microcontroller Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask (GPIOIM) register (see page 143). Bits read as zero indicate that corresponding input pins have not initiated an interrupt. All bits are cleared by a reset. GPIO Raw Interrupt Status (GPIORIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x414 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Raw Status Reflects the status of interrupt trigger condition detection on pins (raw, prior to masking). The RIS values are defined as follows: Value Description 0 Corresponding pin interrupt requirements not met. 1 Corresponding pin interrupt has met requirements. 7:0 RIS RO 0x00 144 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has been generated, or the interrupt is masked. GPIOMIS is the state of the interrupt after masking. GPIO Masked Interrupt Status (GPIOMIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x418 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Masked Interrupt Status Masked value of interrupt due to corresponding pin. The MIS values are defined as follows: Value Description 0 Corresponding GPIO line interrupt not active. 1 Corresponding GPIO line asserting interrupt. 7:0 MIS RO 0x00 November 30, 2007 145 Preliminary LM3S6110 Microcontroller Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt edge detection logic register. Writing a 0 has no effect. GPIO Interrupt Clear (GPIOICR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x41C Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IC Type RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Clear The IC values are defined as follows: Value Description 0 Corresponding interrupt is unaffected. 1 Corresponding interrupt is cleared. 7:0 IC W1C 0x00 146 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore no GPIO line is set to hardware control by default. The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 147) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 157) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 158) have been set to 1. Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down resistors connected to both of them at the same time. If both pins are pulled Low during reset, the controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors, and apply RST or power-cycle the part. In addition, it is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. GPIO Alternate Function Select (GPIOAFSEL) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x420 Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved AFSEL Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 November 30, 2007 147 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description GPIO Alternate Function Select The AFSEL values are defined as follows: Value Description 0 Software control of corresponding GPIO line (GPIO mode). Hardware control of corresponding GPIO line (alternate hardware function). 1 Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 AFSEL R/W - 148 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 2-mA Drive Select (GPIODR2R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x500 Type R/W, reset 0x0000.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DRV2 Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad 2-mA Drive Enable A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the corresponding 2-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV2 R/W 0xFF November 30, 2007 149 Preliminary LM3S6110 Microcontroller Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 4-mA Drive Select (GPIODR4R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x504 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DRV4 Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad 4-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the corresponding 4-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV4 R/W 0x00 150 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R register are automatically cleared by hardware. GPIO 8-mA Drive Select (GPIODR8R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x508 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DRV8 Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad 8-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the corresponding 8-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV8 R/W 0x00 November 30, 2007 151 Preliminary LM3S6110 Microcontroller Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see page 156). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R, and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open drain output when set to 1. GPIO Open Drain Select (GPIOODR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x50C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ODE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad Open Drain Enable The ODE values are defined as follows: Value Description 0 Open drain configuration is disabled. 1 Open drain configuration is enabled. 7:0 ODE R/W 0x00 152 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 154). GPIO Pull-Up Select (GPIOPUR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x510 Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PUE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Pad Weak Pull-Up Enable A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n] enables. The change is effective on the second clock cycle after the write. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 PUE R/W - November 30, 2007 153 Preliminary LM3S6110 Microcontroller Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 153). GPIO Pull-Down Select (GPIOPDR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x514 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PDE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Pad Weak Pull-Down Enable A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n] enables. The change is effective on the second clock cycle after the write. 7:0 PDE R/W 0x00 154 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see page 151). GPIO Slew Rate Control Select (GPIOSLR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x518 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SRL Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Slew Rate Limit Enable (8-mA drive only) The SRL values are defined as follows: Value Description 0 Slew rate control disabled. 1 Slew rate control enabled. 7:0 SRL R/W 0x00 November 30, 2007 155 Preliminary LM3S6110 Microcontroller Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C The GPIODEN register is the digital enable register. By default, with the exception of the GPIO signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or alternate function), the corresponding GPIODEN bit must be set. GPIO Digital Enable (GPIODEN) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x51C Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DEN Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Digital Enable The DEN values are defined as follows: Value Description 0 Digital functions disabled. 1 Digital functions enabled. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 DEN R/W - 156 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 19: GPIO Lock (GPIOLOCK), offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register (see page 158). Writing 0x1ACCE551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000. GPIO Lock (GPIOLOCK) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x520 Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LOCK Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOCK Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description GPIO Lock A write of the value 0x1ACCE551 unlocks the GPIO Commit (GPIOCR) register for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 locked 0x0000.0000 unlocked 31:0 LOCK R/W 0x0000.0001 November 30, 2007 157 Preliminary LM3S6110 Microcontroller Register 20: GPIO Commit (GPIOCR), offset 0x524 The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the GPIOAFSEL register will be committed when a write to the GPIOAFSEL register is performed. If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit in the GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the GPIOCR register is a one, the data being written to the corresponding bit of the GPIOAFSEL register will be committed to the register and will reflect the new value. The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked. Writes to the GPIOCR register will be ignored if the GPIOLOCK register is locked. Important: This register is designed to prevent accidental programming of the GPIOAFSEL registers that control connectivity to the JTAG/SWD debug hardware. By initializing the bits of the GPIOCR register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and GPIOAFSEL registers. Because this protection is currently only implemented on the JTAG/SWD pins on PB7 and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the GPIOAFSEL register bits of these other pins. GPIO Commit (GPIOCR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x524 Type -, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CR Type RO RO RO RO RO RO RO RO - - - - - - - - Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 158 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset Description GPIO Commit On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL bit to be set to its alternate function. Note: The default register type for the GPIOCR register is RO for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-commitable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. 7:0 CR - - November 30, 2007 159 Preliminary LM3S6110 Microcontroller Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 4 (GPIOPeriphID4) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID4 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID4 RO 0x00 GPIO Peripheral ID Register[7:0] 160 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 5 (GPIOPeriphID5) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID5 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID5 RO 0x00 GPIO Peripheral ID Register[15:8] November 30, 2007 161 Preliminary LM3S6110 Microcontroller Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 6 (GPIOPeriphID6) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID6 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID6 RO 0x00 GPIO Peripheral ID Register[23:16] 162 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 7 (GPIOPeriphID7) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID7 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID7 RO 0x00 GPIO Peripheral ID Register[31:24] November 30, 2007 163 Preliminary LM3S6110 Microcontroller Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 0 (GPIOPeriphID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE0 Type RO, reset 0x0000.0061 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID0 RO 0x61 164 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 1 (GPIOPeriphID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID1 RO 0x00 November 30, 2007 165 Preliminary LM3S6110 Microcontroller Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 2 (GPIOPeriphID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID2 RO 0x18 166 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 3 (GPIOPeriphID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID3 RO 0x01 November 30, 2007 167 Preliminary LM3S6110 Microcontroller Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 0 (GPIOPCellID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. 7:0 CID0 RO 0x0D 168 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 1 (GPIOPCellID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 7:0 CID1 RO 0xF0 November 30, 2007 169 Preliminary LM3S6110 Microcontroller Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 2 (GPIOPCellID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. 7:0 CID2 RO 0x05 170 November 30, 2007 Preliminary General-Purpose Input/Outputs (GPIOs) Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 3 (GPIOPCellID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 7:0 CID3 RO 0xB1 November 30, 2007 171 Preliminary LM3S6110 Microcontroller 9 General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris® General-Purpose Timer Module (GPTM) contains three GPTM blocks (Timer0, Timer1, and Timer 2). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA and TimerB) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Note: Timer2 is an internal timer and can only be used to generate internal interrupts. The General-Purpose Timer Module is one timing resource available on the Stellaris® microcontrollers. Other timer resources include the System Timer (SysTick) (see “System Timer (SysTick)” on page 34) and the PWM timer in the PWM module (see “PWM Timer” on page 366). The following modes are supported: ■ 32-bit Timer modes – Programmable one-shot timer – Programmable periodic timer – Real-Time Clock using 32.768-KHz input clock – Software-controlled event stalling (excluding RTC mode) ■ 16-bit Timer modes – General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) – Programmable one-shot timer – Programmable periodic timer – Software-controlled event stalling ■ 16-bit Input Capture modes – Input edge count capture – Input edge time capture ■ 16-bit PWM mode – Simple PWM mode with software-programmable output inversion of the PWM signal 9.1 Block Diagram Note: In Figure 9-1 on page 173, the specific CCP pins available depend on the Stellaris® device. See Table 9-1 on page 173 for the available CCPs. 172 November 30, 2007 Preliminary General-Purpose Timers Figure 9-1. GPTM Module Block Diagram TA Comparator TB Comparator GPTMTBR GPTMAR Clock / Edge Detect RTC Divider Clock / Edge Detect TimerA Interrupt TimerB Interrupt System Clock 0x0000 (Down Counter Modes) 0x0000 (Down Counter Modes) 32 KHz or Even CCP Pin Odd CCP Pin En En TimerA Control GPTMTAPMR GPTMTAILR GPTMTAMATCHR GPTMTAPR GPTMTAMR TimerB Control GPTMTBPMR GPTMTBILR GPTMTBMATCHR GPTMTBPR GPTMTBMR Interrupt / Config GPTMCFG GPTMRIS GPTMICR GPTMMIS GPTMIMR GPTMCTL Table 9-1. Available CCP Pins Timer 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin Timer 0 TimerA CCP0 - TimerB - CCP1 Timer 1 TimerA CCP2 - TimerB - CCP3 Timer 2 TimerA - - TimerB - - 9.2 Functional Description The main components of each GPTM block are two free-running 16-bit up/down counters (referred to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface. Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 184), the GPTM TimerA Mode (GPTMTAMR) register (see page 185), and the GPTM TimerB Mode (GPTMTBMR) register (see page 187). When in one of the 32-bit modes, the timer can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers configured in any combination of the 16-bit modes. 9.2.1 GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters TimerA and TimerB are initialized to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load November 30, 2007 173 Preliminary LM3S6110 Microcontroller (GPTMTAILR) register (see page 198) and the GPTM TimerB Interval Load (GPTMTBILR) register (see page 199). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale (GPTMTAPR) register (see page 202) and the GPTM TimerB Prescale (GPTMTBPR) register (see page 203). 9.2.2 32-Bit Timer Operating Modes This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their configuration. The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1 (RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM registers are concatenated to form pseudo 32-bit registers. These registers include: ■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 198 ■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 199 ■ GPTM TimerA (GPTMTAR) register [15:0], see page 206 ■ GPTM TimerB (GPTMTBR) register [15:0], see page 207 In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0] 9.2.2.1 32-Bit One-Shot/Periodic Timer Mode In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register (see page 185), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register. When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 189), the timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the GPTM generates interrupts and output triggers when it reaches the 0x0000000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register (see page 194), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register (see page 196). If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTIMR) register (see page 192), the GPTM also sets the TATOMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register (see page 195). The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000.0000 state, and deasserted on the following clock cycle. It is enabled by setting the TAOTE bit in GPTMCTL. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. 174 November 30, 2007 Preliminary General-Purpose Timers If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal is deasserted. 9.2.2.2 32-Bit Real-Time Clock Timer Mode In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA Match (GPTMTAMATCHR) register (see page 200) by the controller. The input clock on the CCP0, CCP2, or CCP4 pins is required to be 32.768 KHz in RTC mode. The clock signal is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter. When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs, the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR. If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL. 9.2.3 16-Bit Timer Operating Modes The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 184). This section describes each of the GPTM 16-bit modes of operation. TimerA and TimerB have identical modes, so a single description is given using an n to reference both. 9.2.3.1 16-Bit One-Shot/Periodic Timer Mode In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR) register. When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the timer generates interrupts and output triggers when it reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR, the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000 state, and deasserted on the following clock cycle. It is enabled by setting the TnOTE bit in the GPTMCTL register, and can trigger SoC-level events. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. November 30, 2007 175 Preliminary LM3S6110 Microcontroller If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal is deasserted. The following example shows a variety of configurations for a 16-bit free running timer while using the prescaler. All values assume a 25-MHz clock with Tc=20 ns (clock period). Table 9-2. 16-Bit Timer With Prescaler Configurations Prescale #Clock (T c)a Max Time Units 00000000 1 2.6214 mS 00000001 2 5.2428 mS 00000010 3 7.8642 mS ------------ -- -- -- 11111100 254 665.8458 mS 11111110 255 668.4672 mS 11111111 256 671.0886 mS a. Tc is the clock period. 9.2.3.2 16-Bit Input Edge Count Mode In Edge Count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match (GPTMTnMATCHR) register is configured so that the difference between the value in the GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that must be counted. When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are ignored until TnEN is re-enabled by software. Figure 9-2 on page 177 shows how input edge count mode works. In this case, the timer start value is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted since the timer automatically clears the TnEN bit after the current count matches the value in the GPTMnMR register. 176 November 30, 2007 Preliminary General-Purpose Timers Figure 9-2. 16-Bit Input Edge Count Mode Example 0x000A 0x0006 0x0007 0x0008 0x0009 Input Signal Timer stops, flags asserted Timer reload Count on next cycle Ignored Ignored 9.2.3.3 16-Bit Input Edge Time Mode Note: The prescaler is not available in 16-Bit Input Edge Time mode. In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of both rising and falling edges. The timer is placed into Edge Time mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCnTL register. When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and the CnEMIS bit, if the interrupt is not masked). After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the GPTMnILR register. Figure 9-3 on page 178 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events. Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into GPTMTnR). November 30, 2007 177 Preliminary LM3S6110 Microcontroller Figure 9-3. 16-Bit Input Edge Time Mode Example GPTMTnR=Y Input Signal Time Count GPTMTnR=X GPTMTnR=Z Z X Y 0xFFFF 9.2.3.4 16-Bit PWM Mode The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from GPTMTnILR (and GPTMTnPR if using a prescaler) and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM mode. The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its start state), and is deasserted when the counter value equals the value in the GPTM Timern Match Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register. Figure 9-4 on page 179 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is GPTMnMR=0x411A. 178 November 30, 2007 Preliminary General-Purpose Timers Figure 9-4. 16-Bit PWM Mode Example Output Signal Time Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0xC350 0x411A TnPWML = 0 TnPWML = 1 TnEN set 9.3 Initialization and Configuration To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0, TIMER1, and TIMER2 bits in the RCGC1 register. This section shows module initialization and configuration examples for each of the supported timer modes. 9.3.1 32-Bit One-Shot/Periodic Timer Mode The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0. 3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR): a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR). 5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. November 30, 2007 179 Preliminary LM3S6110 Microcontroller 7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). In One-Shot mode, the timer stops counting after step 7 on page 180. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 9.3.2 32-Bit Real-Time Clock (RTC) Mode To use the RTC mode, the timer must have a 32.768-KHz input signal on its CCP0, CCP2, or CCP4 pins. To enable the RTC feature, follow these steps: 1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1. 3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR). 4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired. 5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared. 9.3.3 16-Bit One-Shot/Periodic Timer Mode A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4. 3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register: a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register (GPTMTnPR). 5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR). 6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start counting. 8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). 180 November 30, 2007 Preliminary General-Purpose Timers In One-Shot mode, the timer stops counting after step 8 on page 180. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 9.3.4 16-Bit Input Edge Count Mode A timer is configured to Input Edge Count mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3. 4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register. 7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register. In Input Edge Count Mode, the timer stops after the desired number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 181 through step 9 on page 181. 9.3.5 16-Bit Input Edge Timing Mode A timer is configured to Input Edge Timing mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3. 4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting. 8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM November 30, 2007 181 Preliminary LM3S6110 Microcontroller Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timern (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the GPTMTnILR register. The change takes effect at the next cycle after the write. 9.3.6 16-Bit PWM Mode A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. 4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value. 7. If a prescaler is going to be used, configure the GPTM Timern Prescale (GPTMTnPR) register and the GPTM Timern Prescale Match (GPTMTnPMR) register. 8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes effect at the next cycle after the write. 9.4 Register Map Table 9-3 on page 182 lists the GPTM registers. The offset listed is a hexadecimal increment to the register’s address, relative to that timer’s base address: ■ Timer0: 0x4003.0000 ■ Timer1: 0x4003.1000 ■ Timer2: 0x4003.2000 Table 9-3. Timers Register Map See Offset Name Type Reset Description page 0x000 GPTMCFG R/W 0x0000.0000 GPTM Configuration 184 0x004 GPTMTAMR R/W 0x0000.0000 GPTM TimerA Mode 185 0x008 GPTMTBMR R/W 0x0000.0000 GPTM TimerB Mode 187 182 November 30, 2007 Preliminary General-Purpose Timers See Offset Name Type Reset Description page 0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 189 0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 192 0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 194 0x020 GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 195 0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 196 GPTM TimerA Interval Load 198 0x0000.FFFF (16-bit mode) 0xFFFF.FFFF (32-bit mode) 0x028 GPTMTAILR R/W 0x02C GPTMTBILR R/W 0x0000.FFFF GPTM TimerB Interval Load 199 GPTM TimerA Match 200 0x0000.FFFF (16-bit mode) 0xFFFF.FFFF (32-bit mode) 0x030 GPTMTAMATCHR R/W 0x034 GPTMTBMATCHR R/W 0x0000.FFFF GPTM TimerB Match 201 0x038 GPTMTAPR R/W 0x0000.0000 GPTM TimerA Prescale 202 0x03C GPTMTBPR R/W 0x0000.0000 GPTM TimerB Prescale 203 0x040 GPTMTAPMR R/W 0x0000.0000 GPTM TimerA Prescale Match 204 0x044 GPTMTBPMR R/W 0x0000.0000 GPTM TimerB Prescale Match 205 GPTM TimerA 206 0x0000.FFFF (16-bit mode) 0xFFFF.FFFF (32-bit mode) 0x048 GPTMTAR RO 0x04C GPTMTBR RO 0x0000.FFFF GPTM TimerB 207 9.5 Register Descriptions The remainder of this section lists and describes the GPTM registers, in numerical order by address offset. November 30, 2007 183 Preliminary LM3S6110 Microcontroller Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. GPTM Configuration (GPTMCFG) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPTMCFG Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:3 reserved RO 0x00 GPTM Configuration The GPTMCFG values are defined as follows: Value Description 0x0 32-bit timer configuration. 0x1 32-bit real-time clock (RTC) counter configuration. 0x2 Reserved. 0x3 Reserved. 16-bit timer configuration, function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. 0x4-0x7 2:0 GPTMCFG R/W 0x0 184 November 30, 2007 Preliminary General-Purpose Timers Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to 0x2. GPTM TimerA Mode (GPTMTAMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TAAMS TACMR TAMR Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 GPTM TimerA Alternate Mode Select The TAAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: To enable PWM mode, you must also clear the TACMR bit and set the TAMR field to 0x2. 3 TAAMS R/W 0 GPTM TimerA Capture Mode The TACMR values are defined as follows: Value Description 0 Edge-Count mode. 1 Edge-Time mode. 2 TACMR R/W 0 November 30, 2007 185 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description GPTM TimerA Mode The TAMR values are defined as follows: Value Description 0x0 Reserved. 0x1 One-Shot Timer mode. 0x2 Periodic Timer mode. 0x3 Capture mode. The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register (16-or 32-bit). In 16-bit timer configuration, TAMR controls the 16-bit timer modes for TimerA. In 32-bit timer configuration, this register controls the mode and the contents of GPTMTBMR are ignored. 1:0 TAMR R/W 0x0 186 November 30, 2007 Preliminary General-Purpose Timers Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to 0x2. GPTM TimerB Mode (GPTMTBMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBAMS TBCMR TBMR Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 GPTM TimerB Alternate Mode Select The TBAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: To enable PWM mode, you must also clear the TBCMR bit and set the TBMR field to 0x2. 3 TBAMS R/W 0 GPTM TimerB Capture Mode The TBCMR values are defined as follows: Value Description 0 Edge-Count mode. 1 Edge-Time mode. 2 TBCMR R/W 0 November 30, 2007 187 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description GPTM TimerB Mode The TBMR values are defined as follows: Value Description 0x0 Reserved. 0x1 One-Shot Timer mode. 0x2 Periodic Timer mode. 0x3 Capture mode. The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerB. In 32-bit timer configuration, this register’s contents are ignored and GPTMTAMR is used. 1:0 TBMR R/W 0x0 188 November 30, 2007 Preliminary General-Purpose Timers Register 4: GPTM Control (GPTMCTL), offset 0x00C This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall. GPTM Control (GPTMCTL) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBPWML TBOTE reserved TBEVENT TBSTALL TBEN reserved TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN Type RO R/W R/W RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:15 reserved RO 0x00 GPTM TimerB PWM Output Level The TBPWML values are defined as follows: Value Description 0 Output is unaffected. 1 Output is inverted. 14 TBPWML R/W 0 GPTM TimerB Output Trigger Enable The TBOTE values are defined as follows: Value Description 0 The output TimerB trigger is disabled. 1 The output TimerB trigger is enabled. 13 TBOTE R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 reserved RO 0 GPTM TimerB Event Mode The TBEVENT values are defined as follows: Value Description 0x0 Positive edge. 0x1 Negative edge. 0x2 Reserved 0x3 Both edges. 11:10 TBEVENT R/W 0x0 November 30, 2007 189 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description GPTM TimerB Stall Enable The TBSTALL values are defined as follows: Value Description 0 TimerB stalling is disabled. 1 TimerB stalling is enabled. 9 TBSTALL R/W 0 GPTM TimerB Enable The TBEN values are defined as follows: Value Description 0 TimerB is disabled. TimerB is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 1 8 TBEN R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 reserved RO 0 GPTM TimerA PWM Output Level The TAPWML values are defined as follows: Value Description 0 Output is unaffected. 1 Output is inverted. 6 TAPWML R/W 0 GPTM TimerA Output Trigger Enable The TAOTE values are defined as follows: Value Description 0 The output TimerA trigger is disabled. 1 The output TimerA trigger is enabled. 5 TAOTE R/W 0 GPTM RTC Enable The RTCEN values are defined as follows: Value Description 0 RTC counting is disabled. 1 RTC counting is enabled. 4 RTCEN R/W 0 190 November 30, 2007 Preliminary General-Purpose Timers Bit/Field Name Type Reset Description GPTM TimerA Event Mode The TAEVENT values are defined as follows: Value Description 0x0 Positive edge. 0x1 Negative edge. 0x2 Reserved 0x3 Both edges. 3:2 TAEVENT R/W 0x0 GPTM TimerA Stall Enable The TASTALL values are defined as follows: Value Description 0 TimerA stalling is disabled. 1 TimerA stalling is enabled. 1 TASTALL R/W 0 GPTM TimerA Enable The TAEN values are defined as follows: Value Description 0 TimerA is disabled. TimerA is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 1 0 TAEN R/W 0 November 30, 2007 191 Preliminary LM3S6110 Microcontroller Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables the interrupt, while writing a 0 disables it. GPTM Interrupt Mask (GPTMIMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBEIM CBMIM TBTOIM reserved RTCIM CAEIM CAMIM TATOIM Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Interrupt Mask The CBEIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 10 CBEIM R/W 0 GPTM CaptureB Match Interrupt Mask The CBMIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 9 CBMIM R/W 0 GPTM TimerB Time-Out Interrupt Mask The TBTOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 8 TBTOIM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0 192 November 30, 2007 Preliminary General-Purpose Timers Bit/Field Name Type Reset Description GPTM RTC Interrupt Mask The RTCIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 3 RTCIM R/W 0 GPTM CaptureA Event Interrupt Mask The CAEIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 2 CAEIM R/W 0 GPTM CaptureA Match Interrupt Mask The CAMIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 1 CAMIM R/W 0 GPTM TimerA Time-Out Interrupt Mask The TATOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 0 TATOIM R/W 0 November 30, 2007 193 Preliminary LM3S6110 Microcontroller Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR. GPTM Raw Interrupt Status (GPTMRIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBERIS CBMRIS TBTORIS reserved RTCRIS CAERIS CAMRIS TATORIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Raw Interrupt This is the CaptureB Event interrupt status prior to masking. 10 CBERIS RO 0 GPTM CaptureB Match Raw Interrupt This is the CaptureB Match interrupt status prior to masking. 9 CBMRIS RO 0 GPTM TimerB Time-Out Raw Interrupt This is the TimerB time-out interrupt status prior to masking. 8 TBTORIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0x0 GPTM RTC Raw Interrupt This is the RTC Event interrupt status prior to masking. 3 RTCRIS RO 0 GPTM CaptureA Event Raw Interrupt This is the CaptureA Event interrupt status prior to masking. 2 CAERIS RO 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA Match interrupt status prior to masking. 1 CAMRIS RO 0 GPTM TimerA Time-Out Raw Interrupt This the TimerA time-out interrupt status prior to masking. 0 TATORIS RO 0 194 November 30, 2007 Preliminary General-Purpose Timers Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR. GPTM Masked Interrupt Status (GPTMMIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBEMIS CBMMIS TBTOMIS reserved RTCMIS CAEMIS CAMMIS TATOMIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Masked Interrupt This is the CaptureB event interrupt status after masking. 10 CBEMIS RO 0 GPTM CaptureB Match Masked Interrupt This is the CaptureB match interrupt status after masking. 9 CBMMIS RO 0 GPTM TimerB Time-Out Masked Interrupt This is the TimerB time-out interrupt status after masking. 8 TBTOMIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0x0 GPTM RTC Masked Interrupt This is the RTC event interrupt status after masking. 3 RTCMIS RO 0 GPTM CaptureA Event Masked Interrupt This is the CaptureA event interrupt status after masking. 2 CAEMIS RO 0 GPTM CaptureA Match Masked Interrupt This is the CaptureA match interrupt status after masking. 1 CAMMIS RO 0 GPTM TimerA Time-Out Masked Interrupt This is the TimerA time-out interrupt status after masking. 0 TATOMIS RO 0 November 30, 2007 195 Preliminary LM3S6110 Microcontroller Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. GPTM Interrupt Clear (GPTMICR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x024 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBECINT CBMCINT TBTOCINT reserved RTCCINT CAECINT CAMCINT TATOCINT Type RO RO RO RO RO W1C W1C W1C RO RO RO RO W1C W1C W1C W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Interrupt Clear The CBECINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 10 CBECINT W1C 0 GPTM CaptureB Match Interrupt Clear The CBMCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 9 CBMCINT W1C 0 GPTM TimerB Time-Out Interrupt Clear The TBTOCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 8 TBTOCINT W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0x0 196 November 30, 2007 Preliminary General-Purpose Timers Bit/Field Name Type Reset Description GPTM RTC Interrupt Clear The RTCCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 3 RTCCINT W1C 0 GPTM CaptureA Event Interrupt Clear The CAECINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 2 CAECINT W1C 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA match interrupt status after masking. 1 CAMCINT W1C 0 GPTM TimerA Time-Out Raw Interrupt The TATOCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 0 TATOCINT W1C 0 November 30, 2007 197 Preliminary LM3S6110 Microcontroller Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 This register is used to load the starting count value into the timer. When GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR. GPTM TimerA Interval Load (GPTMTAILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x028 Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TAILRH Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAILRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description GPTM TimerA Interval Load Register High When configured for 32-bit mode via the GPTMCFG register, the GPTM TimerB Interval Load (GPTMTBILR) register loads this value on a write. A read returns the current value of GPTMTBILR. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBILR. 0xFFFF (32-bit mode) 0x0000 (16-bit mode) 31:16 TAILRH R/W GPTM TimerA Interval Load Register Low For both 16- and 32-bit modes, writing this field loads the counter for TimerA. A read returns the current value of GPTMTAILR. 15:0 TAILRL R/W 0xFFFF 198 November 30, 2007 Preliminary General-Purpose Timers Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C This register is used to load the starting count value into TimerB. When the GPTM is configured to a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes. GPTM TimerB Interval Load (GPTMTBILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x02C Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBILRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 GPTM TimerB Interval Load Register When the GPTM is not configured as a 32-bit timer, a write to this field updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. 15:0 TBILRL R/W 0xFFFF November 30, 2007 199 Preliminary LM3S6110 Microcontroller Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerA Match (GPTMTAMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x030 Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TAMRH Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAMRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description GPTM TimerA Match Register High When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the upper half of GPTMTAR, to determine match events. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBMATCHR. 0xFFFF (32-bit mode) 0x0000 (16-bit mode) 31:16 TAMRH R/W GPTM TimerA Match Register Low When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the lower half of GPTMTAR, to determine match events. When configured for PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value. 15:0 TAMRL R/W 0xFFFF 200 November 30, 2007 Preliminary General-Purpose Timers Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerB Match (GPTMTBMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x034 Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBMRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 GPTM TimerB Match Register Low When configured for PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTBILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value. 15:0 TBMRL R/W 0xFFFF November 30, 2007 201 Preliminary LM3S6110 Microcontroller Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerA Prescale (GPTMTAPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TAPSR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerA Prescale The register loads this value on a write. A read returns the current value of the register. Refer to Table 9-2 on page 176 for more details and an example. 7:0 TAPSR R/W 0x00 202 November 30, 2007 Preliminary General-Purpose Timers Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerB Prescale (GPTMTBPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x03C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBPSR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerB Prescale The register loads this value on a write. A read returns the current value of this register. Refer to Table 9-2 on page 176 for more details and an example. 7:0 TBPSR R/W 0x00 November 30, 2007 203 Preliminary LM3S6110 Microcontroller Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerA Prescale Match (GPTMTAPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TAPSMR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerA Prescale Match This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler. 7:0 TAPSMR R/W 0x00 204 November 30, 2007 Preliminary General-Purpose Timers Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerB Prescale Match (GPTMTBPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBPSMR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerB Prescale Match This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler. 7:0 TBPSMR R/W 0x00 November 30, 2007 205 Preliminary LM3S6110 Microcontroller Register 17: GPTM TimerA (GPTMTAR), offset 0x048 This register shows the current value of the TimerA counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place. GPTM TimerA (GPTMTAR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x048 Type RO, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TARH Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TARL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description GPTM TimerA Register High If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the GPTMCFG is in a 16-bit mode, this is read as zero. 0xFFFF (32-bit mode) 0x0000 (16-bit mode) 31:16 TARH RO GPTM TimerA Register Low A read returns the current value of the GPTM TimerA Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. 15:0 TARL RO 0xFFFF 206 November 30, 2007 Preliminary General-Purpose Timers Register 18: GPTM TimerB (GPTMTBR), offset 0x04C This register shows the current value of the TimerB counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place. GPTM TimerB (GPTMTBR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x04C Type RO, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBRL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 GPTM TimerB A read returns the current value of the GPTM TimerB Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. 15:0 TBRL RO 0xFFFF November 30, 2007 207 Preliminary LM3S6110 Microcontroller 10 Watchdog Timer A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. The Stellaris® Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, a locking register, and user-enabled stalling. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 10.1 Block Diagram Figure 10-1. WDT Module Block Diagram Control / Clock / Interrupt Generation WDTCTL WDTICR WDTRIS WDTMIS WDTLOCK WDTTEST WDTLOAD WDTVALUE Comparator 32-Bit Down Counter 0x00000000 Interrupt System Clock Identification Registers WDTPCellID0 WDTPeriphID0 WDTPeriphID4 WDTPCellID1 WDTPeriphID1 WDTPeriphID5 WDTPCellID2 WDTPeriphID2 WDTPeriphID6 WDTPCellID3 WDTPeriphID3 WDTPeriphID7 10.2 Functional Description The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the 208 November 30, 2007 Preliminary Watchdog Timer Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting resumes from that value. If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting. Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 10.3 Initialization and Configuration To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register. The Watchdog Timer is configured using the following sequence: 1. Load the WDTLOAD register with the desired timer load value. 2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register. 3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register. If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write a value of 0x1ACC.E551. 10.4 Register Map Table 10-1 on page 209 lists the Watchdog registers. The offset listed is a hexadecimal increment to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000. Table 10-1. Watchdog Timer Register Map See Offset Name Type Reset Description page 0x000 WDTLOAD R/W 0xFFFF.FFFF Watchdog Load 211 0x004 WDTVALUE RO 0xFFFF.FFFF Watchdog Value 212 0x008 WDTCTL R/W 0x0000.0000 Watchdog Control 213 0x00C WDTICR WO - Watchdog Interrupt Clear 214 0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 215 0x014 WDTMIS RO 0x0000.0000 Watchdog Masked Interrupt Status 216 0x418 WDTTEST R/W 0x0000.0000 Watchdog Test 217 0xC00 WDTLOCK R/W 0x0000.0000 Watchdog Lock 218 November 30, 2007 209 Preliminary LM3S6110 Microcontroller See Offset Name Type Reset Description page 0xFD0 WDTPeriphID4 RO 0x0000.0000 Watchdog Peripheral Identification 4 219 0xFD4 WDTPeriphID5 RO 0x0000.0000 Watchdog Peripheral Identification 5 220 0xFD8 WDTPeriphID6 RO 0x0000.0000 Watchdog Peripheral Identification 6 221 0xFDC WDTPeriphID7 RO 0x0000.0000 Watchdog Peripheral Identification 7 222 0xFE0 WDTPeriphID0 RO 0x0000.0005 Watchdog Peripheral Identification 0 223 0xFE4 WDTPeriphID1 RO 0x0000.0018 Watchdog Peripheral Identification 1 224 0xFE8 WDTPeriphID2 RO 0x0000.0018 Watchdog Peripheral Identification 2 225 0xFEC WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 226 0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 227 0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 228 0xFF8 WDTPCellID2 RO 0x0000.0005 Watchdog PrimeCell Identification 2 229 0xFFC WDTPCellID3 RO 0x0000.00B1 Watchdog PrimeCell Identification 3 230 10.5 Register Descriptions The remainder of this section lists and describes the WDT registers, in numerical order by address offset. 210 November 30, 2007 Preliminary Watchdog Timer Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated. Watchdog Load (WDTLOAD) Base 0x4000.0000 Offset 0x000 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTLoad Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTLoad Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description 31:0 WDTLoad R/W 0xFFFF.FFFF Watchdog Load Value November 30, 2007 211 Preliminary LM3S6110 Microcontroller Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) Base 0x4000.0000 Offset 0x004 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTValue Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTValue Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Watchdog Value Current value of the 32-bit down counter. 31:0 WDTValue RO 0xFFFF.FFFF 212 November 30, 2007 Preliminary Watchdog Timer Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. When the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. The only mechanism that can re-enable writes is a hardware reset. Watchdog Control (WDTCTL) Base 0x4000.0000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RESEN INTEN Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 Watchdog Reset Enable The RESEN values are defined as follows: Value Description 0 Disabled. 1 Enable the Watchdog module reset output. 1 RESEN R/W 0 Watchdog Interrupt Enable The INTEN values are defined as follows: Value Description Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). 0 1 Interrupt event enabled. Once enabled, all writes are ignored. 0 INTEN R/W 0 November 30, 2007 213 Preliminary LM3S6110 Microcontroller Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is indeterminate. Watchdog Interrupt Clear (WDTICR) Base 0x4000.0000 Offset 0x00C Type WO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTIntClr Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTIntClr Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description 31:0 WDTIntClr WO - Watchdog Interrupt Clear 214 November 30, 2007 Preliminary Watchdog Timer Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Watchdog Raw Interrupt Status (WDTRIS) Base 0x4000.0000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WDTRIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Watchdog Raw Interrupt Status Gives the raw interrupt state (prior to masking) of WDTINTR. 0 WDTRIS RO 0 November 30, 2007 215 Preliminary LM3S6110 Microcontroller Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit. Watchdog Masked Interrupt Status (WDTMIS) Base 0x4000.0000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WDTMIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Watchdog Masked Interrupt Status Gives the masked interrupt state (after masking) of the WDTINTR interrupt. 0 WDTMIS RO 0 216 November 30, 2007 Preliminary Watchdog Timer Register 7: Watchdog Test (WDTTEST), offset 0x418 This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug. Watchdog Test (WDTTEST) Base 0x4000.0000 Offset 0x418 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved STALL reserved Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:9 reserved RO 0x00 Watchdog Stall Enable When set to 1, if the Stellaris® microcontroller is stopped with a debugger, the watchdog timer stops counting. Once the microcontroller is restarted, the watchdog timer resumes counting. 8 STALL R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 reserved RO 0x00 November 30, 2007 217 Preliminary LM3S6110 Microcontroller Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). Watchdog Lock (WDTLOCK) Base 0x4000.0000 Offset 0xC00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTLock Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTLock Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Watchdog Lock A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 Locked 0x0000.0000 Unlocked 31:0 WDTLock R/W 0x0000 218 November 30, 2007 Preliminary Watchdog Timer Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 4 (WDTPeriphID4) Base 0x4000.0000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID4 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID4 RO 0x00 WDT Peripheral ID Register[7:0] November 30, 2007 219 Preliminary LM3S6110 Microcontroller Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) Base 0x4000.0000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID5 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID5 RO 0x00 WDT Peripheral ID Register[15:8] 220 November 30, 2007 Preliminary Watchdog Timer Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 6 (WDTPeriphID6) Base 0x4000.0000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID6 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID6 RO 0x00 WDT Peripheral ID Register[23:16] November 30, 2007 221 Preliminary LM3S6110 Microcontroller Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) Base 0x4000.0000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID7 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID7 RO 0x00 WDT Peripheral ID Register[31:24] 222 November 30, 2007 Preliminary Watchdog Timer Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 0 (WDTPeriphID0) Base 0x4000.0000 Offset 0xFE0 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID0 RO 0x05 Watchdog Peripheral ID Register[7:0] November 30, 2007 223 Preliminary LM3S6110 Microcontroller Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) Base 0x4000.0000 Offset 0xFE4 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID1 RO 0x18 Watchdog Peripheral ID Register[15:8] 224 November 30, 2007 Preliminary Watchdog Timer Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 2 (WDTPeriphID2) Base 0x4000.0000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID2 RO 0x18 Watchdog Peripheral ID Register[23:16] November 30, 2007 225 Preliminary LM3S6110 Microcontroller Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) Base 0x4000.0000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID3 RO 0x01 Watchdog Peripheral ID Register[31:24] 226 November 30, 2007 Preliminary Watchdog Timer Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 0 (WDTPCellID0) Base 0x4000.0000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID0 RO 0x0D Watchdog PrimeCell ID Register[7:0] November 30, 2007 227 Preliminary LM3S6110 Microcontroller Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 1 (WDTPCellID1) Base 0x4000.0000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID1 RO 0xF0 Watchdog PrimeCell ID Register[15:8] 228 November 30, 2007 Preliminary Watchdog Timer Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 2 (WDTPCellID2) Base 0x4000.0000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID2 RO 0x05 Watchdog PrimeCell ID Register[23:16] November 30, 2007 229 Preliminary LM3S6110 Microcontroller Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 3 (WDTPCellID3) Base 0x4000.0000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID3 RO 0xB1 Watchdog PrimeCell ID Register[31:24] 230 November 30, 2007 Preliminary Watchdog Timer 11 Universal Asynchronous Receivers/Transmitters (UARTs) The Stellaris® Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable, 16C550-type serial interface characteristics. The LM3S6110 controller is equipped with one UART module. The UART has the following features: ■ Separate transmit and receive FIFOs ■ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface ■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ■ Programmable baud-rate generator allowing rates up to 1.5625 Mbps ■ Standard asynchronous communication bits for start, stop, and parity ■ False start bit detection ■ Line-break generation and detection ■ Fully programmable serial interface characteristics: – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation ■ IrDA serial-IR (SIR) encoder/decoder providing: – Programmable use of IrDA Serial InfraRed (SIR) or UART input/output – Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex – Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations – Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration November 30, 2007 231 Preliminary LM3S6110 Microcontroller 11.1 Block Diagram Figure 11-1. UART Module Block Diagram Receiver Transmitter System Clock Control / Status UARTRSR/ECR UARTFR UARTLCRH UARTCTL UARTILPR Interrupt Control UARTIFLS UARTIM UARTMIS UARTRIS UARTICR Baud Rate Generator UARTIBRD UARTFBRD Identification Registers UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UART PeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7 UARTDR TXFIFO 16x8 ... RXFIFO 16x8 ... Interrupt UnTx UnRx 11.2 Functional Description Each Stellaris® UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in functionality to a 16C550 UART, but is not register compatible. The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control (UARTCTL) register (see page 250). Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL register. 11.2.1 Transmit/Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit, and followed by the data 232 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 11-2 on page 233 for details. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. Figure 11-2. UART Character Frame 1 0 5-8 data bits LSB MSB Parity bit if enabled 1-2 stop bits UnTX n Start 11.2.2 Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register (see page 246) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register (see page 247). The baud-rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal place.): BRD = BRDI + BRDF = SysClk / (16 * Baud Rate) The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error detection during receive operations. Along with the UART Line Control, High Byte (UARTLCRH) register (see page 248), the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. To update the baud-rate registers, there are four possible sequences: ■ UARTIBRD write, UARTFBRD write, and UARTLCRH write ■ UARTFBRD write, UARTIBRD write, and UARTLCRH write ■ UARTIBRD write and UARTLCRH write ■ UARTFBRD write and UARTLCRH write November 30, 2007 233 Preliminary LM3S6110 Microcontroller 11.2.3 Data Transmission Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 243) is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 (described in “Transmit/Receive Logic” on page 232). The start bit is valid if UnRx is still low on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR) register (see page 241). If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word. 11.2.4 Serial IR (SIR) The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block provides functionality that converts between an asynchronous UART data stream, and half-duplex serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to provide a digital encoded output, and decoded input to the UART. The UART signal pins can be connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block has two modes of operation: ■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the selected baud rate bit period on the output pin, while logic one levels are transmitted as a static LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light for each zero. On the reception side, the incoming light pulses energize the photo transistor base of the receiver, pulling its output LOW. This drives the UART input pin LOW. ■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the period of the internally generated IrLPBaud16 signal (1.63 μs, assuming a nominal 1.8432 MHz frequency) by changing the appropriate bit in the UARTCR register. Figure 11-3 on page 235 shows the UART transmit and receive signals, with and without IrDA modulation. 234 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Figure 11-3. IrDA Data Modulation 0 1 0 1 0 0 1 1 0 1 Data bits 0 1 0 1 0 0 1 1 0 1 Start Data bits bit Start Stop Bit period Bit period 3 16 UnTx UnTx with IrDA UnRx with IrDA UnRx Stop bit In both normal and low-power IrDA modes: ■ During transmission, the UART data bit is used as the base for encoding ■ During reception, the decoded bits are transferred to the UART receive logic The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay between transmission and reception. This delay must be generated by software because it is not automatically supported by the UART. The delay is required because the infrared receiver electronics might become biased, or even saturated from the optical power coupled from the adjacent transmitter LED. This delay is known as latency, or receiver setup time. 11.2.5 FIFO Operation The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the UART Data (UARTDR) register (see page 239). Read operations of the UARTDR register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit FIFO. Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH (page 248). FIFO status can be monitored via the UART Flag (UARTFR) register (see page 243) and the UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the UARTRSR register shows overrun status via the OE bit. The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register (see page 252). Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the ½ mark. 11.2.6 Interrupts The UART can generate interrupts when the following conditions are observed: ■ Overrun Error ■ Break Error November 30, 2007 235 Preliminary LM3S6110 Microcontroller ■ Parity Error ■ Framing Error ■ Receive Timeout ■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met) ■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met) All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register (see page 257). The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM ) register (see page 254) by setting the corresponding IM bit to 1. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register (see page 256). Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 258). The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the UARTICR register. 11.2.7 Loopback Operation The UART can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LBE bit in the UARTCTL register (see page 250). In loopback mode, data transmitted on UnTx is received on the UnRx input. 11.2.8 IrDA SIR block The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR transceiver. The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before data can be received. The IrDA SIR physical layer specifies a minimum 10-ms delay between transmission and reception. 11.3 Initialization and Configuration To use the UART, the peripheral clock must be enabled by setting the UART0 bit in the RCGC1 register. This section discusses the steps that are required for using a UART module. For this example, the system clock is assumed to be 20 MHz and the desired UART configuration is: ■ 115200 baud rate ■ Data length of 8 bits ■ One stop bit 236 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) ■ No parity ■ FIFOs disabled ■ No interrupts The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the equation described in “Baud-Rate Generation” on page 233, the BRD can be calculated: BRD = 20,000,000 / (16 * 115,200) = 10.8507 which means that the DIVINT field of the UARTIBRD register (see page 246) should be set to 10. The value to be loaded into the UARTFBRD register (see page 247) is calculated by the equation: UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54 With the BRD values in hand, the UART configuration is written to the module in the following order: 1. Disable the UART by clearing the UARTEN bit in the UARTCTL register. 2. Write the integer portion of the BRD to the UARTIBRD register. 3. Write the fractional portion of the BRD to the UARTFBRD register. 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x0000.0060). 5. Enable the UART by setting the UARTEN bit in the UARTCTL register. 11.4 Register Map Table 11-1 on page 237 lists the UART registers. The offset listed is a hexadecimal increment to the register’s address, relative to that UART’s base address: ■ UART0: 0x4000.C000 Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 250) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. Table 11-1. UART Register Map See Offset Name Type Reset Description page 0x000 UARTDR R/W 0x0000.0000 UART Data 239 0x004 UARTRSR/UARTECR R/W 0x0000.0000 UART Receive Status/Error Clear 241 0x018 UARTFR RO 0x0000.0090 UART Flag 243 0x020 UARTILPR R/W 0x0000.0000 UART IrDA Low-Power Register 245 0x024 UARTIBRD R/W 0x0000.0000 UART Integer Baud-Rate Divisor 246 0x028 UARTFBRD R/W 0x0000.0000 UART Fractional Baud-Rate Divisor 247 November 30, 2007 237 Preliminary LM3S6110 Microcontroller See Offset Name Type Reset Description page 0x02C UARTLCRH R/W 0x0000.0000 UART Line Control 248 0x030 UARTCTL R/W 0x0000.0300 UART Control 250 0x034 UARTIFLS R/W 0x0000.0012 UART Interrupt FIFO Level Select 252 0x038 UARTIM R/W 0x0000.0000 UART Interrupt Mask 254 0x03C UARTRIS RO 0x0000.000F UART Raw Interrupt Status 256 0x040 UARTMIS RO 0x0000.0000 UART Masked Interrupt Status 257 0x044 UARTICR W1C 0x0000.0000 UART Interrupt Clear 258 0xFD0 UARTPeriphID4 RO 0x0000.0000 UART Peripheral Identification 4 260 0xFD4 UARTPeriphID5 RO 0x0000.0000 UART Peripheral Identification 5 261 0xFD8 UARTPeriphID6 RO 0x0000.0000 UART Peripheral Identification 6 262 0xFDC UARTPeriphID7 RO 0x0000.0000 UART Peripheral Identification 7 263 0xFE0 UARTPeriphID0 RO 0x0000.0011 UART Peripheral Identification 0 264 0xFE4 UARTPeriphID1 RO 0x0000.0000 UART Peripheral Identification 1 265 0xFE8 UARTPeriphID2 RO 0x0000.0018 UART Peripheral Identification 2 266 0xFEC UARTPeriphID3 RO 0x0000.0001 UART Peripheral Identification 3 267 0xFF0 UARTPCellID0 RO 0x0000.000D UART PrimeCell Identification 0 268 0xFF4 UARTPCellID1 RO 0x0000.00F0 UART PrimeCell Identification 1 269 0xFF8 UARTPCellID2 RO 0x0000.0005 UART PrimeCell Identification 2 270 0xFFC UARTPCellID3 RO 0x0000.00B1 UART PrimeCell Identification 3 271 11.5 Register Descriptions The remainder of this section lists and describes the UART registers, in numerical order by address offset. 238 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 1: UART Data (UARTDR), offset 0x000 This register is the data register (the interface to the FIFOs). When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART. For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register. UART Data (UARTDR) UART0 base: 0x4000.C000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OE BE PE FE DATA Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:12 reserved RO 0 UART Overrun Error The OE values are defined as follows: Value Description 0 There has been no data loss due to a FIFO overrun. New data was received when the FIFO was full, resulting in data loss. 1 11 OE RO 0 UART Break Error This bit is set to 1 when a break condition is detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the received data input goes to a 1 (marking state) and the next valid start bit is received. 10 BE RO 0 UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. In FIFO mode, this error is associated with the character at the top of the FIFO. 9 PE RO 0 November 30, 2007 239 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). 8 FE RO 0 Data Transmitted or Received When written, the data that is to be transmitted via the UART. When read, the data that was received by the UART. 7:0 DATA R/W 0 240 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs. The UARTRSR register cannot be written. A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared to 0 on reset. Read-Only Receive Status (UARTRSR) Register UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OE BE PE FE Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0 UART Overrun Error When this bit is set to 1, data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid since no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data in order to empty the FIFO. 3 OE RO 0 UART Break Error This bit is set to 1 when a break condition is detected, indicating that the received data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 2 BE RO 0 November 30, 2007 241 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. This bit is cleared to 0 by a write to UARTECR. 1 PE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. 0 FE RO 0 Write-Only Error Clear (UARTECR) Register UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DATA Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved WO 0 Error Clear A write to this register of any data clears the framing, parity, break, and overrun flags. 7:0 DATA WO 0 242 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 3: UART Flag (UARTFR), offset 0x018 The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. UART Flag (UARTFR) UART0 base: 0x4000.C000 Offset 0x018 Type RO, reset 0x0000.0090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TXFE RXFF TXFF RXFE BUSY reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding register is empty. If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO is empty. 7 TXFE RO 1 UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, this bit is set when the receive FIFO is full. 6 RXFF RO 0 UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, this bit is set when the transmit FIFO is full. 5 TXFF RO 0 UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, this bit is set when the receive FIFO is empty. 4 RXFE RO 1 November 30, 2007 243 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description UART Busy When this bit is 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled). 3 BUSY RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 244 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor value used to generate the IrLPBaud16 signal by dividing down the system clock (SysClk). All the bits are cleared to 0 when reset. The IrLPBaud16 internal signal is generated by dividing down the UARTCLK signal according to the low-power divisor value written to UARTILPR. The low-power divisor value is calculated as follows: ILPDVSR = SysClk / FIrLPBaud16 where FIrLPBaud16 is nominally 1.8432 MHz. IrLPBaud16 is an internal signal used for SIR pulse generation when low-power mode is used. You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that pulses greater than 1.4 μs are accepted as valid pulses. Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being generated. UART IrDA Low-Power Register (UARTILPR) UART0 base: 0x4000.C000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ILPDVSR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 IrDA Low-Power Divisor This is an 8-bit low-power divisor value. 7:0 ILPDVSR R/W 0x00 November 30, 2007 245 Preliminary LM3S6110 Microcontroller Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 233 for configuration details. UART Integer Baud-Rate Divisor (UARTIBRD) UART0 base: 0x4000.C000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIVINT Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0 15:0 DIVINT R/W 0x0000 Integer Baud-Rate Divisor 246 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 233 for configuration details. UART Fractional Baud-Rate Divisor (UARTFBRD) UART0 base: 0x4000.C000 Offset 0x028 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DIVFRAC Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0x00 5:0 DIVFRAC R/W 0x000 Fractional Baud-Rate Divisor November 30, 2007 247 Preliminary LM3S6110 Microcontroller Register 7: UART Line Control (UARTLCRH), offset 0x02C The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register. UART Line Control (UARTLCRH) UART0 base: 0x4000.C000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SPS WLEN FEN STP2 EPS PEN BRK Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 UART Stick Parity Select When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. When this bit is cleared, stick parity is disabled. 7 SPS R/W 0 UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: Value Description 0x3 8 bits 0x2 7 bits 0x1 6 bits 0x0 5 bits (default) 6:5 WLEN R/W 0 UART Enable FIFOs If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 4 FEN R/W 0 UART Two Stop Bits Select If this bit is set to 1, two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received. 3 STP2 R/W 0 248 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description UART Even Parity Select If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed, which checks for an odd number of 1s. This bit has no effect when parity is disabled by the PEN bit. 2 EPS R/W 0 UART Parity Enable If this bit is set to 1, parity checking and generation is enabled; otherwise, parity is disabled and no parity bit is added to the data frame. 1 PEN R/W 0 UART Send Break If this bit is set to 1, a Low level is continually output on the UnTX output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two frames (character periods). For normal use, this bit must be cleared to 0. 0 BRK R/W 0 November 30, 2007 249 Preliminary LM3S6110 Microcontroller Register 8: UART Control (UARTCTL), offset 0x030 The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1. To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping. UART Control (UARTCTL) UART0 base: 0x4000.C000 Offset 0x030 Type R/W, reset 0x0000.0300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RXE TXE LBE reserved SIRLP SIREN UARTEN Type RO RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:10 reserved RO 0 UART Receive Enable If this bit is set to 1, the receive section of the UART is enabled. When the UART is disabled in the middle of a receive, it completes the current character before stopping. Note: To enable reception, the UARTEN bit must also be set. 9 RXE R/W 1 UART Transmit Enable If this bit is set to 1, the transmit section of the UART is enabled. When the UART is disabled in the middle of a transmission, it completes the current character before stopping. Note: To enable transmission, the UARTEN bit must also be set. 8 TXE R/W 1 UART Loop Back Enable If this bit is set to 1, the UnTX path is fed through the UnRX path. 7 LBE R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:3 reserved RO 0 250 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description UART SIR Low Power Mode This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active High pulse with a width of 3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width which is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. See page 245 for more information. 2 SIRLP R/W 0 UART SIR Enable If this bit is set to 1, the IrDA SIR block is enabled, and the UART will transmit and receive data using SIR protocol. 1 SIREN R/W 0 UART Enable If this bit is set to 1, the UART is enabled. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 0 UARTEN R/W 0 November 30, 2007 251 Preliminary LM3S6110 Microcontroller Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark. UART Interrupt FIFO Level Select (UARTIFLS) UART0 base: 0x4000.C000 Offset 0x034 Type R/W, reset 0x0000.0012 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RXIFLSEL TXIFLSEL Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0x00 UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Value Description 0x0 RX FIFO ≥ 1/8 full 0x1 RX FIFO ≥ ¼ full 0x2 RX FIFO ≥ ½ full (default) 0x3 RX FIFO ≥ ¾ full 0x4 RX FIFO ≥ 7/8 full 0x5-0x7 Reserved 5:3 RXIFLSEL R/W 0x2 252 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Value Description 0x0 TX FIFO ≤ 1/8 full 0x1 TX FIFO ≤ ¼ full 0x2 TX FIFO ≤ ½ full (default) 0x3 TX FIFO ≤ ¾ full 0x4 TX FIFO ≤ 7/8 full 0x5-0x7 Reserved 2:0 TXIFLSEL R/W 0x2 November 30, 2007 253 Preliminary LM3S6110 Microcontroller Register 10: UART Interrupt Mask (UARTIM), offset 0x038 The UARTIM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a 0 prevents the raw interrupt signal from being sent to the interrupt controller. UART Interrupt Mask (UARTIM) UART0 base: 0x4000.C000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OEIM BEIM PEIM FEIM RTIM TXIM RXIM reserved Type RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 UART Overrun Error Interrupt Mask On a read, the current mask for the OEIM interrupt is returned. Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller. 10 OEIM R/W 0 UART Break Error Interrupt Mask On a read, the current mask for the BEIM interrupt is returned. Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller. 9 BEIM R/W 0 UART Parity Error Interrupt Mask On a read, the current mask for the PEIM interrupt is returned. Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller. 8 PEIM R/W 0 UART Framing Error Interrupt Mask On a read, the current mask for the FEIM interrupt is returned. Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller. 7 FEIM R/W 0 UART Receive Time-Out Interrupt Mask On a read, the current mask for the RTIM interrupt is returned. Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller. 6 RTIM R/W 0 UART Transmit Interrupt Mask On a read, the current mask for the TXIM interrupt is returned. Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller. 5 TXIM R/W 0 254 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description UART Receive Interrupt Mask On a read, the current mask for the RXIM interrupt is returned. Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller. 4 RXIM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0x00 November 30, 2007 255 Preliminary LM3S6110 Microcontroller Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect. UART Raw Interrupt Status (UARTRIS) UART0 base: 0x4000.C000 Offset 0x03C Type RO, reset 0x0000.000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 UART Overrun Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 10 OERIS RO 0 UART Break Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 9 BERIS RO 0 UART Parity Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 8 PERIS RO 0 UART Framing Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 7 FERIS RO 0 UART Receive Time-Out Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 6 RTRIS RO 0 UART Transmit Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 5 TXRIS RO 0 UART Receive Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 4 RXRIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0xF 256 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 The UARTMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. UART Masked Interrupt Status (UARTMIS) UART0 base: 0x4000.C000 Offset 0x040 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 UART Overrun Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 10 OEMIS RO 0 UART Break Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 9 BEMIS RO 0 UART Parity Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 8 PEMIS RO 0 UART Framing Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 7 FEMIS RO 0 UART Receive Time-Out Masked Interrupt Status Gives the masked interrupt state of this interrupt. 6 RTMIS RO 0 UART Transmit Masked Interrupt Status Gives the masked interrupt state of this interrupt. 5 TXMIS RO 0 UART Receive Masked Interrupt Status Gives the masked interrupt state of this interrupt. 4 RXMIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0 November 30, 2007 257 Preliminary LM3S6110 Microcontroller Register 13: UART Interrupt Clear (UARTICR), offset 0x044 The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect. UART Interrupt Clear (UARTICR) UART0 base: 0x4000.C000 Offset 0x044 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OEIC BEIC PEIC FEIC RTIC TXIC RXIC reserved Type RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 Overrun Error Interrupt Clear The OEIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. 10 OEIC W1C 0 Break Error Interrupt Clear The BEIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. 9 BEIC W1C 0 Parity Error Interrupt Clear The PEIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. 8 PEIC W1C 0 Framing Error Interrupt Clear The FEIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. 7 FEIC W1C 0 258 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description Receive Time-Out Interrupt Clear The RTIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. 6 RTIC W1C 0 Transmit Interrupt Clear The TXIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. 5 TXIC W1C 0 Receive Interrupt Clear The RXIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. 4 RXIC W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0x00 November 30, 2007 259 Preliminary LM3S6110 Microcontroller Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 4 (UARTPeriphID4) UART0 base: 0x4000.C000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID4 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID4 RO 0x0000 260 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 5 (UARTPeriphID5) UART0 base: 0x4000.C000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID5 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID5 RO 0x0000 November 30, 2007 261 Preliminary LM3S6110 Microcontroller Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 6 (UARTPeriphID6) UART0 base: 0x4000.C000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID6 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID6 RO 0x0000 262 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 7 (UARTPeriphID7) UART0 base: 0x4000.C000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID7 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID7 RO 0x0000 November 30, 2007 263 Preliminary LM3S6110 Microcontroller Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 0 (UARTPeriphID0) UART0 base: 0x4000.C000 Offset 0xFE0 Type RO, reset 0x0000.0011 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID0 RO 0x11 264 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 1 (UARTPeriphID1) UART0 base: 0x4000.C000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID1 RO 0x00 November 30, 2007 265 Preliminary LM3S6110 Microcontroller Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 2 (UARTPeriphID2) UART0 base: 0x4000.C000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID2 RO 0x18 266 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 3 (UARTPeriphID3) UART0 base: 0x4000.C000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID3 RO 0x01 November 30, 2007 267 Preliminary LM3S6110 Microcontroller Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 0 (UARTPCellID0) UART0 base: 0x4000.C000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. 7:0 CID0 RO 0x0D 268 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 1 (UARTPCellID1) UART0 base: 0x4000.C000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 7:0 CID1 RO 0xF0 November 30, 2007 269 Preliminary LM3S6110 Microcontroller Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 2 (UARTPCellID2) UART0 base: 0x4000.C000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. 7:0 CID2 RO 0x05 270 November 30, 2007 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 3 (UARTPCellID3) UART0 base: 0x4000.C000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 UART PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 7:0 CID3 RO 0xB1 November 30, 2007 271 Preliminary LM3S6110 Microcontroller 12 Synchronous Serial Interface (SSI) The Stellaris® Synchronous Serial Interface (SSI) is a master or slave interface for synchronous serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces. The Stellaris® SSI module has the following features: ■ Master or slave operation ■ Programmable clock bit rate and prescale ■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ Programmable data frame size from 4 to 16 bits ■ Internal loopback test mode for diagnostic/debug testing 12.1 Block Diagram Figure 12-1. SSI Module Block Diagram Transmit/ Receive Logic Clock Prescaler SSICPSR Control / Status SSICR0 SSICR1 SSISR Interrupt Control SSIIM SSIMIS SSIRIS SSIICR SSIDR TxFIFO 8 x 16 ... RxFIFO 8 x 16 ... System Clock SSITx SSIRx SSIClk SSIFss Interrupt Identification Registers SSIPCellID0 SSIPeriphID0 SSIPeriphID4 SSIPCellID1 SSIPeriphID1 SSIPeriphID5 SSIPCellID2 SSIPeriphID2 SSIPeriphID6 SSIPCellID3 SSIPeriphID3 SSIPeriphID7 12.2 Functional Description The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with 272 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. 12.2.1 Bit Rate Generation The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral devices. The serial bit rate is derived by dividing down the 25-MHz input clock. The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale (SSICPSR) register (see page 291). The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 284). The frequency of the output clock SSIClk is defined by: FSSIClk = FSysClk / (CPSDVSR * (1 + SCR)) Note that although the SSIClk transmit clock can theoretically be 12.5 MHz, the module may not be able to operate at that speed. For master mode, the system clock must be at least two times faster than the SSIClk. For slave mode, the system clock must be at least 12 times faster than the SSIClk. See “Synchronous Serial Interface (SSI)” on page 422 to view SSI timing parameters. 12.2.2 FIFO Operation 12.2.2.1 Transmit FIFO The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 288), and data is stored in the FIFO until it is read out by the transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin. 12.2.2.2 Receive FIFO The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is registered prior to parallel loading into the attached slave or master receive FIFO, respectively. 12.2.3 Interrupts The SSI can generate interrupts when the following conditions are observed: ■ Transmit FIFO service ■ Receive FIFO service ■ Receive FIFO time-out ■ Receive FIFO overrun November 30, 2007 273 Preliminary LM3S6110 Microcontroller All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI can only generate a single interrupt request to the controller at any given time. You can mask each of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask (SSIIM) register (see page 292). Setting the appropriate mask bit to 1 enables the interrupt. Provision of the individual outputs, as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts. The transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers (see page 294 and page 295, respectively). 12.2.4 Frame Formats Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. There are three basic frame types that can be selected: ■ Texas Instruments synchronous serial ■ Freescale SPI ■ MICROWIRE For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period. For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low, and is asserted (pulled down) during the entire transmission of the frame. For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. For this frame format, both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and latch data from the other device on the falling edge. Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a special master-slave messaging technique, which operates at half-duplex. In this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 12.2.4.1 Texas Instruments Synchronous Serial Frame Format Figure 12-2 on page 275 shows the Texas Instruments synchronous serial frame format for a single transmitted frame. 274 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) SSIClk 4 to 16 bits SSIFss SSITx/SSIRx MSB LSB In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data is shifted onto the SSIRx pin by the off-chip serial slave device. Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SSIClk after the LSB has been latched. Figure 12-3 on page 275 shows the Texas Instruments synchronous serial frame format when back-to-back frames are transmitted. Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) MSB LSB 4 to 16 bits SSIClk SSIFss SSITx/SSIRx 12.2.4.2 Freescale SPI Frame Format The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave select. The main feature of the Freescale SPI format is that the inactive state and phase of the SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register. SPO Clock Polarity Bit When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not being transferred. SPH Phase Control Bit The SPH phase control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH phase control bit is Low, data is captured on the first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition. November 30, 2007 275 Preliminary LM3S6110 Microcontroller 12.2.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and SPH=0 are shown in Figure 12-4 on page 276 and Figure 12-5 on page 276. Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 4 to 16 bits SSIClk SSIFss SSIRx Q SSITx MSB MSB LSB LSB Note: Q is undefined. Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx LSB SSITx MSB LSB 4 to 16 bits LSB MSB MSB MSB LSB In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto the SSIRx input line of the master. The master SSITx output pad is enabled. One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the master and slave data have been set, the SSIClk master clock pin goes High after one further half SSIClk period. The data is now captured on the rising and propagated on the falling edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its 276 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 12.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure 12-6 on page 277, which covers both single and continuous transfers. Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 4 to 16 bits SSIClk SSIFss SSIRx SSITx Q MSB Q MSB LSB LSB Note: Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After a further one half SSIClk period, both master and slave valid data is enabled onto their respective transmission lines. At the same time, the SSIClk is enabled with a rising edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 12.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and SPH=0 are shown in Figure 12-7 on page 278 and Figure 12-8 on page 278. November 30, 2007 277 Preliminary LM3S6110 Microcontroller Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 4 to 16 bits SSIClk SSIFss SSIRx SSITx MSB Q MSB LSB LSB Note: Q is undefined. Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSITx/SSIRx MSB LSB 4 to 16 bits LSB MSB In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low, which causes slave data to be immediately transferred onto the SSIRx line of the master. The master SSITx output pad is enabled. One half period later, valid master data is transferred to the SSITx line. Now that both the master and slave data have been set, the SSIClk master clock pin becomes Low after one further half SSIClk period. This means that data is captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 278 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) 12.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure 12-9 on page 279, which covers both single and continuous transfers. Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 4 to 16 bits SSIClk SSIFss SSIRx SSITx Q Q MSB MSB LSB LSB Note: Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled. After a further one-half SSIClk period, both master and slave data are enabled onto their respective transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SSIClk signal. After all bits have been transferred, in the case of a single word transmission, the SSIFss line is returned to its idle high state one SSIClk period after the last bit has been captured. For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 12.2.4.7 MICROWIRE Frame Format Figure 12-10 on page 280 shows the MICROWIRE frame format, again for a single frame. Figure 12-11 on page 281 shows the same format when back-to-back frames are transmitted. November 30, 2007 279 Preliminary LM3S6110 Microcontroller Figure 12-10. MICROWIRE Frame Format (Single Frame) SSIClk SSIFss SSIRx MSB LSB 4 to 16 bits output data 0 SSITx MSB LSB 8-bit control MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains tristated during this transmission. The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one clock period after the last bit has been latched in the receive serial shifter, which causes the data to be transferred to the receive FIFO. Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High. For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs back-to-back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge of SSIClk, after the LSB of the frame has been latched into the SSI. 280 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) 8-bit control SSIClk SSIFss SSIRx MSB LSB 4 to 16 bits output data 0 SSITx LSB MSB LSB MSB In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk. Figure 12-12 on page 281 illustrates these setup and hold time requirements. With respect to the SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss must have a setup of at least two times the period of SSIClk on which the SSI operates. With respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one SSIClk period. Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements SSIClk SSIFss SSIRx First RX data to be sampled by SSI slave tSetup=(2*tSSIClk) tHold=tSSIClk 12.3 Initialization and Configuration To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register. For each of the frame formats, the SSI is configured using the following steps: 1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration changes. 2. Select whether the SSI is a master or slave: a. For master operations, set the SSICR1 register to 0x0000.0000. b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004. c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C. 3. Configure the clock prescale divisor by writing the SSICPSR register. November 30, 2007 281 Preliminary LM3S6110 Microcontroller 4. Write the SSICR0 register with the following configuration: ■ Serial clock rate (SCR) ■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO) ■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF) ■ The data size (DSS) 5. Enable the SSI by setting the SSE bit in the SSICR1 register. As an example, assume the SSI must be configured to operate with the following parameters: ■ Master operation ■ Freescale SPI mode (SPO=1, SPH=1) ■ 1 Mbps bit rate ■ 8 data bits Assuming the system clock is 20 MHz, the bit rate calculation would be: FSSIClk = FSysClk / (CPSDVSR * (1 + SCR)) 1x106 = 20x106 / (CPSDVSR * (1 + SCR)) In this case, if CPSDVSR=2, SCR must be 9. The configuration sequence would be as follows: 1. Ensure that the SSE bit in the SSICR1 register is disabled. 2. Write the SSICR1 register with a value of 0x0000.0000. 3. Write the SSICPSR register with a value of 0x0000.0002. 4. Write the SSICR0 register with a value of 0x0000.09C7. 5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1. 12.4 Register Map Table 12-1 on page 282 lists the SSI registers. The offset listed is a hexadecimal increment to the register’s address, relative to that SSI module’s base address: ■ SSI0: 0x4000.8000 Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control registers are reprogrammed. Table 12-1. SSI Register Map See Offset Name Type Reset Description page 0x000 SSICR0 R/W 0x0000.0000 SSI Control 0 284 282 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) See Offset Name Type Reset Description page 0x004 SSICR1 R/W 0x0000.0000 SSI Control 1 286 0x008 SSIDR R/W 0x0000.0000 SSI Data 288 0x00C SSISR RO 0x0000.0003 SSI Status 289 0x010 SSICPSR R/W 0x0000.0000 SSI Clock Prescale 291 0x014 SSIIM R/W 0x0000.0000 SSI Interrupt Mask 292 0x018 SSIRIS RO 0x0000.0008 SSI Raw Interrupt Status 294 0x01C SSIMIS RO 0x0000.0000 SSI Masked Interrupt Status 295 0x020 SSIICR W1C 0x0000.0000 SSI Interrupt Clear 296 0xFD0 SSIPeriphID4 RO 0x0000.0000 SSI Peripheral Identification 4 297 0xFD4 SSIPeriphID5 RO 0x0000.0000 SSI Peripheral Identification 5 298 0xFD8 SSIPeriphID6 RO 0x0000.0000 SSI Peripheral Identification 6 299 0xFDC SSIPeriphID7 RO 0x0000.0000 SSI Peripheral Identification 7 300 0xFE0 SSIPeriphID0 RO 0x0000.0022 SSI Peripheral Identification 0 301 0xFE4 SSIPeriphID1 RO 0x0000.0000 SSI Peripheral Identification 1 302 0xFE8 SSIPeriphID2 RO 0x0000.0018 SSI Peripheral Identification 2 303 0xFEC SSIPeriphID3 RO 0x0000.0001 SSI Peripheral Identification 3 304 0xFF0 SSIPCellID0 RO 0x0000.000D SSI PrimeCell Identification 0 305 0xFF4 SSIPCellID1 RO 0x0000.00F0 SSI PrimeCell Identification 1 306 0xFF8 SSIPCellID2 RO 0x0000.0005 SSI PrimeCell Identification 2 307 0xFFC SSIPCellID3 RO 0x0000.00B1 SSI PrimeCell Identification 3 308 12.5 Register Descriptions The remainder of this section lists and describes the SSI registers, in numerical order by address offset. November 30, 2007 283 Preliminary LM3S6110 Microcontroller Register 1: SSI Control 0 (SSICR0), offset 0x000 SSICR0 is control register 0 and contains bit fields that control various functions within the SSI module. Functionality such as protocol mode, clock rate, and data size are configured in this register. SSI Control 0 (SSICR0) SSI0 base: 0x4000.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCR SPH SPO FRF DSS Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x00 SSI Serial Clock Rate The value SCR is used to generate the transmit and receive bit rate of the SSI. The bit rate is: BR=FSSIClk/(CPSDVSR * (1 + SCR)) where CPSDVSR is an even value from 2-254 programmed in the SSICPSR register, and SCR is a value from 0-255. 15:8 SCR R/W 0x0000 SSI Serial Clock Phase This bit is only applicable to the Freescale SPI Format. The SPH control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH bit is 0, data is captured on the first clock edge transition. If SPH is 1, data is captured on the second clock edge transition. 7 SPH R/W 0 SSI Serial Clock Polarity This bit is only applicable to the Freescale SPI Format. When the SPO bit is 0, it produces a steady state Low value on the SSIClk pin. If SPO is 1, a steady state High value is placed on the SSIClk pin when data is not being transferred. 6 SPO R/W 0 284 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Bit/Field Name Type Reset Description SSI Frame Format Select The FRF values are defined as follows: Value Frame Format 0x0 Freescale SPI Frame Format 0x1 Texas Intruments Synchronous Serial Frame Format 0x2 MICROWIRE Frame Format 0x3 Reserved 5:4 FRF R/W 0x0 SSI Data Size Select The DSS values are defined as follows: Value Data Size 0x0-0x2 Reserved 0x3 4-bit data 0x4 5-bit data 0x5 6-bit data 0x6 7-bit data 0x7 8-bit data 0x8 9-bit data 0x9 10-bit data 0xA 11-bit data 0xB 12-bit data 0xC 13-bit data 0xD 14-bit data 0xE 15-bit data 0xF 16-bit data 3:0 DSS R/W 0x00 November 30, 2007 285 Preliminary LM3S6110 Microcontroller Register 2: SSI Control 1 (SSICR1), offset 0x004 SSICR1 is control register 1 and contains bit fields that control various functions within the SSI module. Master and slave mode functionality is controlled by this register. SSI Control 1 (SSICR1) SSI0 base: 0x4000.8000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SOD MS SSE LBM Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SSI Slave Mode Output Disable This bit is relevant only in the Slave mode (MS=1). In multiple-slave systems, it is possible for the SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. In such systems, the TXD lines from multiple slaves could be tied together. To operate in such a system, the SOD bit can be configured so that the SSI slave does not drive the SSITx pin. The SOD values are defined as follows: Value Description 0 SSI can drive SSITx output in Slave Output mode. 1 SSI must not drive the SSITx output in Slave mode. 3 SOD R/W 0 SSI Master/Slave Select This bit selects Master or Slave mode and can be modified only when SSI is disabled (SSE=0). The MS values are defined as follows: Value Description 0 Device configured as a master. 1 Device configured as a slave. 2 MS R/W 0 286 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Bit/Field Name Type Reset Description SSI Synchronous Serial Port Enable Setting this bit enables SSI operation. The SSE values are defined as follows: Value Description 0 SSI operation disabled. 1 SSI operation enabled. Note: This bit must be set to 0 before any control registers are reprogrammed. 1 SSE R/W 0 SSI Loopback Mode Setting this bit enables Loopback Test mode. The LBM values are defined as follows: Value Description 0 Normal serial port operation enabled. Output of the transmit serial shift register is connected internally to the input of the receive serial shift register. 1 0 LBM R/W 0 November 30, 2007 287 Preliminary LM3S6110 Microcontroller Register 3: SSI Data (SSIDR), offset 0x008 SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO (pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed to by the current FIFO write pointer). When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer. The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1 register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI. SSI Data (SSIDR) SSI0 base: 0x4000.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 SSI Receive/Transmit Data A read operation reads the receive FIFO. A write operation writes the transmit FIFO. Software must right-justify data when the SSI is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by the transmit logic. The receive logic automatically right-justifies the data. 15:0 DATA R/W 0x0000 288 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 4: SSI Status (SSISR), offset 0x00C SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status. SSI Status (SSISR) SSI0 base: 0x4000.8000 Offset 0x00C Type RO, reset 0x0000.0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved BSY RFF RNE TNF TFE Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:5 reserved RO 0x00 SSI Busy Bit The BSY values are defined as follows: Value Description 0 SSI is idle. SSI is currently transmitting and/or receiving a frame, or the transmit FIFO is not empty. 1 4 BSY RO 0 SSI Receive FIFO Full The RFF values are defined as follows: Value Description 0 Receive FIFO is not full. 1 Receive FIFO is full. 3 RFF RO 0 SSI Receive FIFO Not Empty The RNE values are defined as follows: Value Description 0 Receive FIFO is empty. 1 Receive FIFO is not empty. 2 RNE RO 0 SSI Transmit FIFO Not Full The TNF values are defined as follows: Value Description 0 Transmit FIFO is full. 1 Transmit FIFO is not full. 1 TNF RO 1 November 30, 2007 289 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description SSI Transmit FIFO Empty The TFE values are defined as follows: Value Description 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. 0 TFE R0 1 290 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 SSICPSR is the clock prescale register and specifies the division factor by which the system clock must be internally divided before further use. The value programmed into this register must be an even number between 2 and 254. The least-significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least-significant bit as zero. SSI Clock Prescale (SSICPSR) SSI0 base: 0x4000.8000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CPSDVSR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Clock Prescale Divisor This value must be an even number from 2 to 254, depending on the frequency of SSIClk. The LSB always returns 0 on reads. 7:0 CPSDVSR R/W 0x00 November 30, 2007 291 Preliminary LM3S6110 Microcontroller Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits are cleared to 0 on reset. On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. SSI Interrupt Mask (SSIIM) SSI0 base: 0x4000.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TXIM RXIM RTIM RORIM Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SSI Transmit FIFO Interrupt Mask The TXIM values are defined as follows: Value Description 0 TX FIFO half-full or less condition interrupt is masked. 1 TX FIFO half-full or less condition interrupt is not masked. 3 TXIM R/W 0 SSI Receive FIFO Interrupt Mask The RXIM values are defined as follows: Value Description 0 RX FIFO half-full or more condition interrupt is masked. 1 RX FIFO half-full or more condition interrupt is not masked. 2 RXIM R/W 0 SSI Receive Time-Out Interrupt Mask The RTIM values are defined as follows: Value Description 0 RX FIFO time-out interrupt is masked. 1 RX FIFO time-out interrupt is not masked. 1 RTIM R/W 0 292 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Bit/Field Name Type Reset Description SSI Receive Overrun Interrupt Mask The RORIM values are defined as follows: Value Description 0 RX FIFO overrun interrupt is masked. 1 RX FIFO overrun interrupt is not masked. 0 RORIM R/W 0 November 30, 2007 293 Preliminary LM3S6110 Microcontroller Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 The SSIRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. SSI Raw Interrupt Status (SSIRIS) SSI0 base: 0x4000.8000 Offset 0x018 Type RO, reset 0x0000.0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TXRIS RXRIS RTRIS RORRIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SSI Transmit FIFO Raw Interrupt Status Indicates that the transmit FIFO is half full or less, when set. 3 TXRIS RO 1 SSI Receive FIFO Raw Interrupt Status Indicates that the receive FIFO is half full or more, when set. 2 RXRIS RO 0 SSI Receive Time-Out Raw Interrupt Status Indicates that the receive time-out has occurred, when set. 1 RTRIS RO 0 SSI Receive Overrun Raw Interrupt Status Indicates that the receive FIFO has overflowed, when set. 0 RORRIS RO 0 294 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C The SSIMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. SSI Masked Interrupt Status (SSIMIS) SSI0 base: 0x4000.8000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TXMIS RXMIS RTMIS RORMIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0 SSI Transmit FIFO Masked Interrupt Status Indicates that the transmit FIFO is half full or less, when set. 3 TXMIS RO 0 SSI Receive FIFO Masked Interrupt Status Indicates that the receive FIFO is half full or more, when set. 2 RXMIS RO 0 SSI Receive Time-Out Masked Interrupt Status Indicates that the receive time-out has occurred, when set. 1 RTMIS RO 0 SSI Receive Overrun Masked Interrupt Status Indicates that the receive FIFO has overflowed, when set. 0 RORMIS RO 0 November 30, 2007 295 Preliminary LM3S6110 Microcontroller Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. SSI Interrupt Clear (SSIICR) SSI0 base: 0x4000.8000 Offset 0x020 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RTIC RORIC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO W1C W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 SSI Receive Time-Out Interrupt Clear The RTIC values are defined as follows: Value Description 0 No effect on interrupt. 1 Clears interrupt. 1 RTIC W1C 0 SSI Receive Overrun Interrupt Clear The RORIC values are defined as follows: Value Description 0 No effect on interrupt. 1 Clears interrupt. 0 RORIC W1C 0 296 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 4 (SSIPeriphID4) SSI0 base: 0x4000.8000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID4 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID4 RO 0x00 November 30, 2007 297 Preliminary LM3S6110 Microcontroller Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 5 (SSIPeriphID5) SSI0 base: 0x4000.8000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID5 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID5 RO 0x00 298 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 6 (SSIPeriphID6) SSI0 base: 0x4000.8000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID6 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID6 RO 0x00 November 30, 2007 299 Preliminary LM3S6110 Microcontroller Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 7 (SSIPeriphID7) SSI0 base: 0x4000.8000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID7 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID7 RO 0x00 300 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 0 (SSIPeriphID0) SSI0 base: 0x4000.8000 Offset 0xFE0 Type RO, reset 0x0000.0022 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID0 RO 0x22 November 30, 2007 301 Preliminary LM3S6110 Microcontroller Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 1 (SSIPeriphID1) SSI0 base: 0x4000.8000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID1 RO 0x00 302 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 2 (SSIPeriphID2) SSI0 base: 0x4000.8000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID2 RO 0x18 November 30, 2007 303 Preliminary LM3S6110 Microcontroller Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 3 (SSIPeriphID3) SSI0 base: 0x4000.8000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID3 RO 0x01 304 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 0 (SSIPCellID0) SSI0 base: 0x4000.8000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 7:0 CID0 RO 0x0D November 30, 2007 305 Preliminary LM3S6110 Microcontroller Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 1 (SSIPCellID1) SSI0 base: 0x4000.8000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. 7:0 CID1 RO 0xF0 306 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 2 (SSIPCellID2) SSI0 base: 0x4000.8000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 7:0 CID2 RO 0x05 November 30, 2007 307 Preliminary LM3S6110 Microcontroller Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 3 (SSIPCellID3) SSI0 base: 0x4000.8000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 SSI PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. 7:0 CID3 RO 0xB1 308 November 30, 2007 Preliminary Synchronous Serial Interface (SSI) 13 Ethernet Controller The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. The Ethernet Controller module has the following features: ■ Conforms to the IEEE 802.3-2002 specification – 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer interface to the line – 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler – Full-featured auto-negotiation ■ Multiple operational modes – Full- and half-duplex 100 Mbps – Full- and half-duplex 10 Mbps – Power-saving and power-down modes ■ Highly configurable – Programmable MAC address – LED activity selection – Promiscuous mode support – CRC error-rejection control – User-configurable interrupts ■ Physical media manipulation – Automatic MDI/MDI-X cross-over correction – Register-programmable transmit amplitude – Automatic polarity correction and 10BASE-T signal reception November 30, 2007 309 Preliminary LM3S6110 Microcontroller 13.1 Block Diagram Figure 13-1. Ethernet Controller Block Diagram MACISR MACIACK MACIMR Interrupt Control MACRCR MACNPR Receive Control MACTCR MACITHR MACTRR Transmit Control Transmit FIFO Receive FIFO MACIAR0 MACIAR1 Individual Address MACMDTX MACMCR MACMDVR MACMAR MACMDRX MII Control MACDR Data Access TXOP TXON RXIP RXIN XTLP XTLN MDIX Clock Reference Transmit Encoding Pulse Shaping Receive Decoding Clock Recovery Auto Negotiation Carrier Sense MR3 MR0 MR1 MR2 MR4 Media Independent Interface Management Register Set MR5 MR18 MR6 MR16 MR17 MR19 MR23 MR24 Collision Detect System Clock Interrupt 13.2 Functional Description As shown in Figure 13-2 on page 310, the Ethernet Controller is functionally divided into two layers or modules: the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These correspond to the OSI model layers 2 and 1. The primary interface to the Ethernet Controller is a simple bus interface to the MAC layer. The MAC layer provides transmit and receive processing for Ethernet frames. The MAC layer also provides the interface to the PHY module via an internal Media Independent Interface (MII). Figure 13-2. Ethernet Controller Cortex M3 Media Access Controller MAC (Layer 2) Physical Layer Entity PHY (Layer 1) Magnetics RJ45 Ethernet Controller 13.2.1 Internal MII Operation For the MII management interface to function properly, the MDIO signal must be connected through a 10k Ω pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor will prevent management transactions on this internal MII to function. Note that it is possible for data transmission across the MII to still function since the PHY layer will auto-negotiate the link parameters by default. 310 November 30, 2007 Preliminary Ethernet Controller For the MII management interface to function properly, the internal clock must be divided down from the system clock to a frequency no greater than 2.5 MHz. The MACMDV register contains the divider used for scaling down the system clock. See page 330 for more details about the use of this register. 13.2.2 PHY Configuration/Operation The Physical Layer (PHY) in the Ethernet Controller includes integrated ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions. The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery. The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external filter is required. 13.2.2.1 Clock Selection The PHY has an on-chip crystal oscillator which can also be driven by an external oscillator. In this mode of operation, a 25-MHz crystal should be connected between the XTALPPHY and XTALNPHY pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY pin. In this mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground. 13.2.2.2 Auto-Negotiation The PHY supports the auto-negotiation functions of Clause 28 of the IEEE 802.3 standard for 10/100 Mbps operation over copper wiring. This function can be enabled via register settings. The auto-negotiation function defaults to On and the ANEGEN bit in the MR0 register is High after reset. Software can disable the auto-negotiation function by writing to the ANEGEN bit. The contents of the MR4 register are sent to the PHY’s link partner during auto-negotiation via fast-link pulse coding. Once auto-negotiation is complete, the DPLX and RATE bits in the MR18 register reflect the actual speed and duplex that was chosen. If auto-negotiation fails to establish a link for any reason, the ANEGF bit in the MR18 register reflects this and auto-negotiation restarts from the beginning. Writing a 1 to the RANEG bit in the MR0 register also causes auto-negotiation to restart. 13.2.2.3 Polarity Correction The PHY is capable of either automatic or manual polarity reversal for 10BASE-T and auto-negotiation functions. Bits 4 and 5 (RVSPOL and APOL) in the MR16 register control this feature. The default is automatic mode, where APOL is Low and RVSPOL indicates if the detection circuitry has inverted the input signal. To enter manual mode, APOL should be set High and RVSPOL then controls the signal polarity. 13.2.2.4 MDI/MDI-X Configuration The PHY supports the automatic MDI/MDI-X configuration as defined in IEEE 802.3-2002 specification. This eliminates the need for cross-over cables when connecting to another device, such as a hub. The algorithm is controlled via settings in the MR24 register. Refer to page 352 for additional details about these settings. 13.2.2.5 LED Indicators The PHY supports two LED signals that can be used to indicate various states of operation of the Ethernet Controller. These signals are mapped to the LED0 and LED1 pins. By default, these pins are configured as GPIO signals (PF3 and PF2). For the PHY layer to drive these signals, they must be reconfigured to their hardware function. See “General-Purpose Input/Outputs (GPIOs)” on page November 30, 2007 311 Preliminary LM3S6110 Microcontroller 131 for additional details. The function of these pins is programmable via the PHY layer MR23 register. Refer to page 351 for additonal details on how to program these LED functions. 13.2.3 MAC Configuration/Operation 13.2.3.1 Ethernet Frame Format Ethernet data is carried by Ethernet frames. The basic frame format is shown in Figure 13-3 on page 312. Figure 13-3. Ethernet Frame Preamble SFD Destination Address Source Address Length/ Type Data FCS 7 Bytes 6 Bytes 6 Bytes 2 Bytes 1 Byte 4 Bytes 46 - 1500 Bytes The seven fields of the frame are transmitted from left to right. The bits within the frame are transmitted from least to most significant bit. ■ Preamble The Preamble field is used by the physical layer signaling circuitry to synchronize with the received frame’s timing. The preamble is 7 octets long. ■ Start Frame Delimiter (SFD) The SFD field follows the preamble pattern and indicates the start of the frame. Its value is 1010.1011. ■ Destination Address (DA) This field specifies destination addresses for which the frame is intended. The LSB of the DA determines whether the address is an individual (0), or group/multicast (1) address. ■ Source Address (SA) The source address field identifies the station from which the frame was initiated. ■ Length/Type Field The meaning of this field depends on its numeric value. The first of two octets is most significant. This field can be interpreted as length or type code. The maximum length of the data field is 1500 octets. If the value of the Length/Type field is less than or equal to 1500 decimal, it indicates the number of MAC client data octets. If the value of this field is greater than or equal to 1536 decimal, then it is type interpretation. The meaning of the Length/Type field when the value is between 1500 and 1536 decimal is unspecified by the standard. The MAC module assumes type interpretation if the value of the Length/Type field is greater than 1500 decimal. ■ Data The data field is a sequence of 0 to 1500 octets. Full data transparency is provided so any values can appear in this field. A minimum frame size is required to properly meet the IEEE standard. If necessary, the data field is extended by appending extra bits (a pad). The pad field can have a size of 0 to 46 octets. The sum of the data and pad lengths must be a minimum of 46 octets. The MAC module automatically inserts pads if required, though it can be disabled by a register 312 November 30, 2007 Preliminary Ethernet Controller write. For the MAC module core, data sent/received can be larger than 1500 bytes, and no Frame Too Long error is reported. Instead, a FIFO Overrun error is reported when the frame received is too large to fit into the Ethernet Controller’s RAM. ■ Frame Check Sequence (FCS) The frame check sequence carries the cyclic redundancy check (CRC) value. The value of this field is computed over destination address, source address, length/type, data, and pad fields using the CRC-32 algorithm. The MAC module computes the FCS value one nibble at a time. For transmitted frames, this field is automatically inserted by the MAC layer, unless disabled by the CRC bit in the MACTCTL register. For received frames, this field is automatically checked. If the FCS does not pass, the frame will not be placed in the RX FIFO, unless the FCS check is disabled by the BADCRC bit in the MACRCTL register. 13.2.3.2 MAC Layer FIFOs For Ethernet frame transmission, a 2 KB TX FIFO is provided that can be used to store a single frame. While the IEEE 802.3 specification limits the size of an Ethernet frame's payload section to 1500 Bytes, the Ethernet Controller places no such limit. The full buffer can be used, for a payload of up to 2032 bytes. For Ethernet frame reception, a 2-KB RX FIFO is provided that can be used to store multiple frames, up to a maximum of 31 frames. If a frame is received and there is insufficient space in the RX FIFO, an overflow error will be indicated. For details regarding the TX and RX FIFO layout, refer to Table 13-1 on page 313. Please note the following difference between TX and RX FIFO layout. For the TX FIFO, the Data Length field in the first FIFO word refers to the Ethernet frame data payload, as shown in the 5th to nth FIFO positions. For the RX FIFO, the Frame Length field is the total length of the received Ethernet frame, including the FCS and Frame Length bytes. Also note that if FCS generation is disabled with the CRC bit in the MACTCTL register, the last word in the FIFO must be the FCS bytes for the frame that has been written to the FIFO. Also note that if the length of the data payload section is not a multiple of 4, the FCS field will overlap words in the FIFO. However, for the RX FIFO, the beginning of the next frame will always be on a word boundary. Table 13-1. TX & RX FIFO Organization FIFO Word Read/Write Word Bit Fields TX FIFO (Write) RX FIFO (Read) Sequence 1st 7:0 Data Length LSB Frame Length LSB 15:8 Data Length MSB Frame Length MSB 23:16 DA oct 1 31:24 DA oct 2 2nd 7:0 DA oct 3 15:8 DA oct 4 23:16 DA oct 5 31:24 DA oct 6 3rd 7:0 SA oct 1 15:8 SA oct 2 23:16 SA oct 3 31:24 SA oct 4 November 30, 2007 313 Preliminary LM3S6110 Microcontroller FIFO Word Read/Write Word Bit Fields TX FIFO (Write) RX FIFO (Read) Sequence 4th 7:0 SA oct 5 15:8 SA oct 6 23:16 Len/Type MSB 31:24 Len/Type LSB 5th to nth 7:0 data oct n 15:8 data oct n+1 23:16 data oct n+2 31:24 data oct n+3 FCS 1 (if the CRC bit in FCS 1 MACCTL is 0) last 7:0 FCS 2 (if the CRC bit in FCS 2 MACCTL is 0) 15:8 FCS 3 (if the CRC bit in FCS 3 MACCTL is 0) 23:16 FCS 4 (if the CRC bit in FCS 4 MACCTL is 0) 31:24 13.2.3.3 Ethernet Transmission Options The Ethernet Controller can automatically generate and insert the Frame Check Sequence (FCS) at the end of the transmit frame. This is controlled by the CRC bit in the MACTCTL register. For test purposes, in order to generate a frame with an invalid CRC, this feature can be disabled. The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46 bytes. The Ethernet Controller can be configured to automatically pad the data section if the payload data section loaded into the FIFO is less than the minimum 46 bytes. This feature is controlled by the PADEN bit in the MACTCTL register. At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation by using the DUPLEX bit in the MACTCTL register. 13.2.3.4 Ethernet Reception Options Using the BADCRC bit in the MACRCTL register, the Ethernet Controller can be configured to reject incoming Ethernet frames with an invalid FCS field. The Ethernet receiver can also be configured for Promiscuous and Multicast modes using the PRMS and AMUL fields in the MACRCTL register. If these modes are not enabled, only Ethernet frames with a broadcast address, or frames matching the MAC address programmed into the MACIA0 and MACIA1 register will be placed into the RX FIFO. 13.2.4 Interrupts The Ethernet Controller can generate an interrupt for one or more of the following conditions: ■ A frame has been received into an empty RX FIFO ■ A frame transmission error has occurred ■ A frame has been transmitted successfully ■ A frame has been received with no room in the RX FIFO (overrun) 314 November 30, 2007 Preliminary Ethernet Controller ■ A frame has been received with one or more error conditions (for example, FCS failed) ■ An MII management transaction between the MAC and PHY layers has completed ■ One or more of the following PHY layer conditions occurs: – Auto-Negotiate Complete – Remote Fault – Link Status Change – Link Partner Acknowledge – Parallel Detect Fault – Page Received – Receive Error – Jabber Event Detected 13.3 Initialization and Configuration To use the Ethernet Controller, the peripheral must be enabled by setting the EPHY0 and EMAC0 bits in the RCGC2 register. The following steps can then be used to configure the Ethernet Controller for basic operation. 1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming a 20-MHz system clock, the MACDIV value would be 4. 2. Program the MACIA0 and MACIA1 register for address filtering. 3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation using a value of 0x16. 4. Program the MACRCTL register to reject frames with bad FCS using a value of 0x08. 5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and MACRCTL registers. 6. To transmit a frame, write the frame into the TX FIFO using the MACDATA register. Then set the NEWTX bit in the MACTR register to initiate the transmit process. When the NEWTX bit has been cleared, the TX FIFO will be available for the next transmit frame. 7. To receive a frame, wait for the NPR field in the MACNP register to be non-zero. Then begin reading the frame from the RX FIFO by using the MACDATA register. When the frame (including the FCS field) has been read, the NPR field should decrement by one. When there are no more frames in the RX FIFO, the NPR field will read 0. 13.4 Ethernet Register Map Table 13-2 on page 316 lists the Ethernet MAC registers. All addresses given are relative to the Ethernet MAC base address of 0x4004.8000. November 30, 2007 315 Preliminary LM3S6110 Microcontroller The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY. The registers are collectively known as the MII Management registers and are detailed in Section 22.2.4 of the IEEE 802.3 specification. Table 13-2 on page 316 also lists these MII Management registers. All addresses given are absolute and are written directly to the REGADR field of the MACMCTL register. The format of registers 0 to 15 are defined by the IEEE specification and are common to all PHY implementations. The only variance allowed is for features that may or may not be supported by a specific PHY. Registers 16 to 31 are vendor-specific registers, used to support features that are specific to a vendors PHY implementation. Vendor-specific registers not listed are reserved. Table 13-2. Ethernet Register Map See Offset Name Type Reset Description page Ethernet MAC 0x000 MACRIS RO 0x0000.0000 Ethernet MAC Raw Interrupt Status 318 0x000 MACIACK W1C 0x0000.0000 Ethernet MAC Interrupt Acknowledge 320 0x004 MACIM R/W 0x0000.007F Ethernet MAC Interrupt Mask 321 0x008 MACRCTL R/W 0x0000.0008 Ethernet MAC Receive Control 322 0x00C MACTCTL R/W 0x0000.0000 Ethernet MAC Transmit Control 323 0x010 MACDATA R/W 0x0000.0000 Ethernet MAC Data 324 0x014 MACIA0 R/W 0x0000.0000 Ethernet MAC Individual Address 0 326 0x018 MACIA1 R/W 0x0000.0000 Ethernet MAC Individual Address 1 327 0x01C MACTHR R/W 0x0000.003F Ethernet MAC Threshold 328 0x020 MACMCTL R/W 0x0000.0000 Ethernet MAC Management Control 329 0x024 MACMDV R/W 0x0000.0080 Ethernet MAC Management Divider 330 0x02C MACMTXD R/W 0x0000.0000 Ethernet MAC Management Transmit Data 331 0x030 MACMRXD R/W 0x0000.0000 Ethernet MAC Management Receive Data 332 0x034 MACNP RO 0x0000.0000 Ethernet MAC Number of Packets 333 0x038 MACTR R/W 0x0000.0000 Ethernet MAC Transmission Request 334 MII Management - MR0 R/W 0x3100 Ethernet PHY Management Register 0 – Control 335 - MR1 RO 0x7849 Ethernet PHY Management Register 1 – Status 337 Ethernet PHY Management Register 2 – PHY Identifier 339 - MR2 RO 0x000E 1 Ethernet PHY Management Register 3 – PHY Identifier 340 - MR3 RO 0x7237 2 Ethernet PHYManagement Register 4 – Auto-Negotiation 341 - MR4 R/W 0x01E1 Advertisement Ethernet PHYManagement Register 5 – Auto-Negotiation 343 - MR5 RO 0x0000 Link Partner Base Page Ability 316 November 30, 2007 Preliminary Ethernet Controller See Offset Name Type Reset Description page Ethernet PHYManagement Register 6 – Auto-Negotiation 344 - MR6 RO 0x0000 Expansion Ethernet PHY Management Register 16 – 345 - MR16 R/W 0x0140 Vendor-Specific Ethernet PHY Management Register 17 – Interrupt 347 - MR17 R/W 0x0000 Control/Status - MR18 RO 0x0000 Ethernet PHY Management Register 18 – Diagnostic 349 Ethernet PHY Management Register 19 – Transceiver 350 - MR19 R/W 0x4000 Control Ethernet PHY Management Register 23 – LED 351 - MR23 R/W 0x0010 Configuration Ethernet PHY Management Register 24 –MDI/MDIX 352 - MR24 R/W 0x00C0 Control 13.5 Ethernet MAC Register Descriptions The remainder of this section lists and describes the Ethernet MAC registers, in numerical order by address offset. Also see “MII Management Register Descriptions” on page 334. November 30, 2007 317 Preliminary LM3S6110 Microcontroller Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 The MACRIS register is the interrupt status register. On a read, this register gives the current status value of the corresponding interrupt prior to masking. Ethernet MAC Raw Interrupt Status (MACRIS) Base 0x4004.8000 Offset 0x000 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PHYINT MDINT RXER FOV TXEMP TXER RXINT Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0x0 PHY Interrupt When set, indicates that an enabled interrupt in the PHY layer has occured. MR17 in the PHY must be read to determine the specific PHY event that triggered this interrupt. 6 PHYINT RO 0x0 MII Transaction Complete When set, indicates that a transaction (read or write) on the MII interface has completed successfully. 5 MDINT RO 0x0 Receive Error This bit indicates that an error was encountered on the receiver. The possible errors that can cause this interrupt bit to be set are: ■ A receive error occurs during the reception of a frame (100 Mb/s only). ■ The frame is not an integer number of bytes (dribble bits) due to an alignment error. ■ The CRC of the frame does not pass the FCS check. ■ The length/type field is inconsistent with the frame data size when interpreted as a length field. 4 RXER RO 0x0 FIFO Overrrun When set, indicates that an overrun was encountered on the receive FIFO. 3 FOV RO 0x0 Transmit FIFO Empty When set, indicates that the packet was transmitted and that the TX FIFO is empty. 2 TXEMP RO 0x0 318 November 30, 2007 Preliminary Ethernet Controller Bit/Field Name Type Reset Description Transmit Error When set, indicates that an error was encountered on the transmitter. The possible errors that can cause this interrupt bit to be set are: ■ The data length field stored in the TX FIFO exceeds 2032. The frame is not sent when this error occurs. ■ The retransmission attempts during the backoff process have exceeded the maximum limit of 16. 1 TXER RO 0x0 Packet Received When set, indicates that at least one packet has been received and is stored in the receiver FIFO. 0 RXINT RO 0x0 November 30, 2007 319 Preliminary LM3S6110 Microcontroller Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 A write of a 1 to any bit position of this register clears the corresponding interrupt bit in the Ethernet MAC Raw Interrupt Status (MACRIS) register. Ethernet MAC Interrupt Acknowledge (MACIACK) Base 0x4004.8000 Offset 0x000 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PHYINT MDINT RXER FOV TXEMP TXER RXINT Type RO RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0x0 Clear PHY Interrupt A write of a 1 clears the PHYINT interrupt read from the MACRIS register. 6 PHYINT W1C 0x0 Clear MII Transaction Complete A write of a 1 clears the MDINT interrupt read from the MACRIS register. 5 MDINT W1C 0x0 Clear Receive Error A write of a 1 clears the RXER interrupt read from the MACRIS register. 4 RXER W1C 0x0 Clear FIFO Overrun A write of a 1 clears the FOV interrupt read from the MACRIS register. 3 FOV W1C 0x0 Clear Transmit FIFO Empty A write of a 1 clears the TXEMP interrupt read from the MACRIS register. 2 TXEMP W1C 0x0 Clear Transmit Error A write of a 1 clears the TXER interrupt read from the MACRIS register and resets the TX FIFO write pointer. 1 TXER W1C 0x0 Clear Packet Received A write of a 1 clears the RXINT interrupt read from the MACRIS register. 0 RXINT W1C 0x0 320 November 30, 2007 Preliminary Ethernet Controller Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 This register allows software to enable/disable Ethernet MAC interrupts. Writing a 0 disables the interrupt, while writing a 1 enables it. Ethernet MAC Interrupt Mask (MACIM) Base 0x4004.8000 Offset 0x004 Type R/W, reset 0x0000.007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PHYINTM MDINTM RXERM FOVM TXEMPM TXERM RXINTM Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0x0 Mask PHY Interrupt This bit masks the PHYINT bit in the MACRIS register from being asserted. 6 PHYINTM R/W 1 Mask MII Transaction Complete This bit masks the MDINT bit in the MACRIS register from being asserted. 5 MDINTM R/W 1 Mask Receive Error This bit masks the RXER bit in the MACRIS register from being asserted. 4 RXERM R/W 1 Mask FIFO Overrrun This bit masks the FOV bit in the MACRIS register from being asserted. 3 FOVM R/W 1 Mask Transmit FIFO Empty This bit masks the TXEMP bit in the MACRIS register from being asserted. 2 TXEMPM R/W 1 Mask Transmit Error This bit masks the TXER bit in the MACRIS register from being asserted. 1 TXERM R/W 1 Mask Packet Received This bit masks the RXINT bit in the MACRIS register from being asserted. 0 RXINTM R/W 1 November 30, 2007 321 Preliminary LM3S6110 Microcontroller Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 This register enables software to configure the receive module and control the types of frames that are received from the physical medium. It is important to note that when the receive module is enabled, all valid frames with a broadcast address of FF-FF-FF-FF-FF-FF in the Destination Address field will be received and stored in the RX FIFO, even if the AMUL bit is not set. Ethernet MAC Receive Control (MACRCTL) Base 0x4004.8000 Offset 0x008 Type R/W, reset 0x0000.0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RSTFIFO BADCRC PRMS AMUL RXEN Type RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:5 reserved RO 0x0 Clear Receive FIFO When set, clears the receive FIFO. This should be done when software initialization is performed. It is recommended that the receiver be disabled (RXEN = 0), and then the reset initiated (RSTFIFO = 1). This sequence will flush and reset the RX FIFO. 4 RSTFIFO R/W 0x0 Enable Reject Bad CRC The BADCRC bit enables the rejection of frames with an incorrectly calculated CRC. 3 BADCRC R/W 0x1 Enable Promiscuous Mode The PRMS bit enables Promiscuous mode, which accepts all valid frames, regardless of the Destination Address. 2 PRMS R/W 0x0 Enable Multicast Frames The AMUL bit enables the reception of multicast frames from the physical medium. 1 AMUL R/W 0x0 Enable Receiver The RXEN bit enables the Ethernet receiver. When this bit is Low, the receiver is disabled and all frames on the physical medium are ignored. 0 RXEN R/W 0x0 322 November 30, 2007 Preliminary Ethernet Controller Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C This register enables software to configure the transmit module, and control frames are placed onto the physical medium. Ethernet MAC Transmit Control (MACTCTL) Base 0x4004.8000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DUPLEX reserved CRC PADEN TXEN Type RO RO RO RO RO RO RO RO RO RO RO R/W RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:5 reserved RO 0x0 Enable Duplex Mode When set, enables Duplex mode, allowing simultaneous transmission and reception. 4 DUPLEX R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 reserved RO 0x0 Enable CRC Generation When set, enables the automatic generation of the CRC and the placement at the end of the packet. If this bit is not set, the frames placed in the TX FIFO will be sent exactly as they are written into the FIFO. 2 CRC R/W 0x0 Enable Packet Padding When set, enables the automatic padding of packets that do not meet the minimum frame size. 1 PADEN R/W 0x0 Enable Transmitter When set, enables the transmitter. When this bit is 0, the transmitter is disabled. 0 TXEN R/W 0x0 November 30, 2007 323 Preliminary LM3S6110 Microcontroller Register 6: Ethernet MAC Data (MACDATA), offset 0x010 This register enables software to access the TX and RX FIFOs. Reads from this register return the data stored in the RX FIFO from the location indicated by the read pointer. Writes to this register store the data in the TX FIFO at the location indicated by the write pointer. The write pointer is then auto-incremented to the next TX FIFO location. There is no mechanism for randomly accessing bytes in either the RX or TX FIFOs. Data must be read from the RX FIFO sequentially and stored in a buffer for further processing. Once a read has been performed, the data in the FIFO cannot be re-read. Data must be written to the TX FIFO sequentially. If an error is made in placing the frame into the TX FIFO, the write pointer can be reset to the start of the TX FIFO by writing the TXER bit of the MACIACK register and then the data re-written. Read-Only Register Ethernet MAC Data (MACDATA) Base 0x4004.8000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXDATA Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXDATA Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Receive FIFO Data The RXDATA bits represent the next four bytes of data stored in the RX FIFO. 31:0 RXDATA RO 0x0 Write-Only Register Ethernet MAC Data (MACDATA) Base 0x4004.8000 Offset 0x010 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TXDATA Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXDATA Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 324 November 30, 2007 Preliminary Ethernet Controller Bit/Field Name Type Reset Description Transmit FIFO Data The TXDATA bits represent the next four bytes of data to place in the TX FIFO for transmission. 31:0 TXDATA WO 0x0 November 30, 2007 325 Preliminary LM3S6110 Microcontroller Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 This register enables software to program the first four bytes of the hardware MAC address of the Network Interface Card (NIC). (The last two bytes are in MACIA1). The 6-byte IAR is compared against the incoming Destination Address fields to determine whether the frame should be received. Ethernet MAC Individual Address 0 (MACIA0) Base 0x4004.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MACOCT4 MACOCT3 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MACOCT2 MACOCT1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description MAC Address Octet 4 The MACOCT4 bits represent the fourth octet of the MAC address used to uniquely identify each Ethernet Controller. 31:24 MACOCT4 R/W 0x0 MAC Address Octet 3 The MACOCT3 bits represent the third octet of the MAC address used to uniquely identify each Ethernet Controller. 23:16 MACOCT3 R/W 0x0 MAC Address Octet 2 The MACOCT2 bits represent the second octet of the MAC address used to uniquely identify each Ethernet Controller. 15:8 MACOCT2 R/W 0x0 MAC Address Octet 1 The MACOCT1 bits represent the first octet of the MAC address used to uniquely identify each Ethernet Controller. 7:0 MACOCT1 R/W 0x0 326 November 30, 2007 Preliminary Ethernet Controller Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 This register enables software to program the last two bytes of the hardware MAC address of the Network Interface Card (NIC). (The first four bytes are in MACIA0). The 6-byte IAR is compared against the incoming Destination Address fields to determine whether the frame should be received. Ethernet MAC Individual Address 1 (MACIA1) Base 0x4004.8000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MACOCT6 MACOCT5 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0 MAC Address Octet 6 The MACOCT6 bits represent the sixth octet of the MAC address used to uniquely identify each Ethernet Controller. 15:8 MACOCT6 R/W 0x0 MAC Address Octet 5 The MACOCT5 bits represent the fifth octet of the MAC address used to uniquely identify each Ethernet Controller. 7:0 MACOCT5 R/W 0x0 November 30, 2007 327 Preliminary LM3S6110 Microcontroller Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C This register enables software to set the threshold level at which the transmission of the frame begins. If the THRESH bits are set to 0x3F, which is the reset value, transmission does not start until the NEWTX bit is set in the MACTR register. This effectively disables the early transmission feature. Writing the THRESH bits to any value besides all 1s enables the early transmission feature. Once the byte count of data in the TX FIFO reaches this level, transmission of the frame begins. When THRESH is set to all 0s, transmission of the frame begins after 4 bytes (a single write) are stored in the TX FIFO. Each increment of the THRESH bit field waits for an additional 32 bytes of data (eight writes) to be stored in the TX FIFO. Therefore, a value of 0x01 would wait for 36 bytes of data to be written while a value of 0x02 would wait for 68 bytes to be written. In general, early transmission starts when: Number of Bytes >= 4 (THRESH x 8 + 1) Reaching the threshold level has the same effect as setting the NEWTX bit in the MACTR register. Transmission of the frame begins and then the number of bytes indicated by the Data Length field is sent out on the physical medium. Because under-run checking is not performed, it is possible that the tail pointer may reach and pass the write pointer in the TX FIFO. This causes indeterminate values to be written to the physical medium rather than the end of the frame. Therefore, sufficient bus bandwidth for writing to the TX FIFO must be guaranteed by the software. If a frame smaller than the threshold level needs to be sent, the NEWTX bit in the MACTR register must be set with an explicit write. This initiates the transmission of the frame even though the threshold limit has not been reached. If the threshold level is set too small, it is possible for the transmitter to underrun. If this occurs, the transmit frame is aborted, and a transmit error occurs. Ethernet MAC Threshold (MACTHR) Base 0x4004.8000 Offset 0x01C Type R/W, reset 0x0000.003F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved THRESH Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0x0 Threshold Value The THRESH bits represent the early transmit threshold. Once the amount of data in the TX FIFO exceeds this value, transmission of the packet begins. 5:0 THRESH R/W 0x3F 328 November 30, 2007 Preliminary Ethernet Controller Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 This register enables software to control the transfer of data to and from the MII Management registers in the Ethernet PHY. The address, name, type, reset configuration, and functional description of each of these registers can be found in Table 13-2 on page 316 and in “MII Management Register Descriptions” on page 334. In order to initiate a read transaction from the MII Management registers, the WRITE bit must be written with a 0 during the same cycle that the START bit is written with a 1. In order to initiate a write transaction to the MII Management registers, the WRITE bit must be written with a 1 during the same cycle that the START bit is written with a 1. Ethernet MAC Management Control (MACMCTL) Base 0x4004.8000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved REGADR reserved WRITE START Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x0 MII Register Address The REGADR bit field represents the MII Management register address for the next MII management interface transaction. 7:3 REGADR R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 reserved RO 0x0 MII Register Transaction Type The WRITE bit represents the operation of the next MII management interface transaction. If WRITE is set, the next operation will be a write; otherwise, it will be a read. 1 WRITE R/W 0x0 MII Register Transaction Enable The START bit represents the initiation of the next MII management interface transaction. When a 1 is written to this bit, the MII register located at REGADR will be read (WRITE=0) or written (WRITE=1). 0 START R/W 0x0 November 30, 2007 329 Preliminary LM3S6110 Microcontroller Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 This register enables software to set the clock divider for the Management Data Clock (MDC). This clock is used to synchronize read and write transactions between the system and the MII Management registers. The frequency of the MDC clock can be calculated from the following formula: Fmdc = Fipclk / (2 * (MACMDVR + 1 )) The clock divider must be written with a value that ensures that the MDC clock will not exceed a frequency of 2.5 MHz. Ethernet MAC Management Divider (MACMDV) Base 0x4004.8000 Offset 0x024 Type R/W, reset 0x0000.0080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DIV Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x0 Clock Divider The DIV bits are used to set the clock divider for the MDC clock used to transmit data between the MAC and PHY over the serial MII interface. 7:0 DIV R/W 0x80 330 November 30, 2007 Preliminary Ethernet Controller Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C This register holds the next value to be written to the MII Management registers. Ethernet MAC Management Transmit Data (MACMTXD) Base 0x4004.8000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDTX Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0 MII Register Transmit Data The MDTX bits represent the data that will be written in the next MII management transaction. 15:0 MDTX R/W 0x0 November 30, 2007 331 Preliminary LM3S6110 Microcontroller Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 This register holds the last value read from the MII Management registers. Ethernet MAC Management Receive Data (MACMRXD) Base 0x4004.8000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDRX Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0 MII Register Receive Data The MDRX bits represent the data that was read in the previous MII management transaction. 15:0 MDRX R/W 0x0 332 November 30, 2007 Preliminary Ethernet Controller Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 This register holds the number of frames that are currently in the RX FIFO. When NPR is 0, there are no frames in the RX FIFO and the RXINT bit is not set. When NPR is any other value, there is at least one frame in the RX FIFO and the RXINT bit in the MACRIS register is set. Ethernet MAC Number of Packets (MACNP) Base 0x4004.8000 Offset 0x034 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved NPR Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0x0 Number of Packets in Receive FIFO The NPR bits represent the number of packets stored in the RX FIFO. While the NPR field is greater than 0, the RXINT interrupt in the MACRIS register will be asserted. 5:0 NPR RO 0x0 November 30, 2007 333 Preliminary LM3S6110 Microcontroller Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 This register enables software to initiate the transmission of the frame currently located in the TX FIFO to the physical medium. Once the frame has been transmitted to the medium from the TX FIFO or a transmission error has been encountered, the NEWTX bit is auto-cleared by the hardware. Ethernet MAC Transmission Request (MACTR) Base 0x4004.8000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved NEWTX Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x0 New Transmission When set, the NEWTX bit initiates an Ethernet transmission once the packet has been placed in the TX FIFO. This bit is cleared once the transmission has been completed. If early transmission is being used (see the MACTHR register), this bit does not need to be set. 0 NEWTX R/W 0x0 13.6 MII Management Register Descriptions The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY. The registers are collectively known as the MII Management registers. All addresses given are absolute. Addresses not listed are reserved. Also see “Ethernet MAC Register Descriptions” on page 317. 334 November 30, 2007 Preliminary Ethernet Controller Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 This register enables software to configure the operation of the PHY. The default settings of these registers are designed to initialize the PHY to a normal operational mode without configuration. Ethernet PHY Management Register 0 – Control (MR0) Base 0x4004.8000 Address 0x00 Type R/W, reset 0x3100 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT reserved Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Reset Registers When set, resets the registers to their default state and reinitializes internal state machines. Once the reset operation has completed, this bit is cleared by hardware. 15 RESET R/W 0 Loopback Mode When set, enables the Loopback mode of operation. The receive circuitry is isolated from the physical medium and transmissions are sent back through the receive circuitry instead of the medium. 14 LOOPBK R/W 0 Speed Select 1: Enables the 100 Mb/s mode of operation (100BASE-TX). 0: Enables the 10 Mb/s mode of operation (10BASE-T). 13 SPEEDSL R/W 1 Auto-Negotiation Enable When set, enables the Auto-Negotiation process. 12 ANEGEN R/W 1 Power Down When set, places the PHY into a low-power consuming state. 11 PWRDN R/W 0 Isolate When set, isolates transmit and receive data paths and ignores all signaling on these buses. 10 ISO R/W 0 Restart Auto-Negotiation When set, restarts the Auto-Negotiation process. Once the restart has initiated, this bit is cleared by hardware. 9 RANEG R/W 0 Set Duplex Mode 1: Enables the Full-Duplex mode of operation. This bit can be set by software in a manual configuration process or by the Auto-Negotiation process. 0: Enables the Half-Duplex mode of operation. 8 DUPLEX R/W 1 November 30, 2007 335 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description Collision Test When set, enables the Collision Test mode of operation. The COLT bit asserts after the initiation of a transmission and de-asserts once the transmission is halted. 7 COLT R/W 0 6:0 reserved R/W 0x00 Write as 0, ignore on read. 336 November 30, 2007 Preliminary Ethernet Controller Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 This register enables software to determine the capabilities of the PHY and perform its initialization and operation appropriately. Ethernet PHY Management Register 1 – Status (MR1) Base 0x4004.8000 Address 0x01 Type RO, reset 0x7849 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved 100X_F 100X_H 10T_F 10T_H reserved MFPS ANEGC RFAULT ANEGA LINK JAB EXTD Type RO RO RO RO RO RO RO RO RO RO RO RC RO RO RC RO Reset 0 1 1 1 1 0 0 0 0 1 0 0 1 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 reserved RO 0 100BASE-TX Full-Duplex Mode When set, indicates that the PHY is capable of supporting 100BASE-TX Full-Duplex mode. 14 100X_F RO 1 100BASE-TX Half-Duplex Mode When set, indicates that the PHY is capable of supporting 100BASE-TX Half-Duplex mode. 13 100X_H RO 1 10BASE-T Full-Duplex Mode When set, indicates that the PHY is capable of 10BASE-T Full-Duplex mode. 12 10T_F RO 1 10BASE-T Half-Duplex Mode When set, indicates that the PHY is capable of supporting 10BASE-T Half-Duplex mode. 11 10T_H RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10:7 reserved RO 0 Management Frames with Preamble Suppressed When set, indicates that the Management Interface is capable of receiving management frames with the preamble suppressed. 6 MFPS RO 1 Auto-Negotiation Complete When set, indicates that the Auto-Negotiation process has been completed and that the extended registers defined by the Auto-Negotiation protocol are valid. 5 ANEGC RO 0 Remote Fault When set, indicates that a remote fault condition has been detected. This bit remains set until it is read, even if the condition no longer exists. 4 RFAULT RC 0 November 30, 2007 337 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description Auto-Negotiation When set, indicates that the PHY has the ability to perform Auto-Negotiation. 3 ANEGA RO 1 Link Made When set, indicates that a valid link has been established by the PHY. 2 LINK RO 0 Jabber Condition When set, indicates that a jabber condition has been detected by the PHY. This bit remains set until it is read, even if the jabber condition no longer exists. 1 JAB RC 0 Extended Capabilities When set, indicates that the PHY provides an extended set of capabilities that can be accessed through the extended register set. 0 EXTD RO 1 338 November 30, 2007 Preliminary Ethernet Controller Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 This register, along with MR3, provides a 32-bit value indicating the manufacturer, model, and revision information. Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2) Base 0x4004.8000 Address 0x02 Type RO, reset 0x000E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OUI[21:6] Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 Bit/Field Name Type Reset Description Organizationally Unique Identifier[21:6] This field, along with the OUI[5:0] field in MR3, makes up the Organizationally Unique Identifier indicating the PHY manufacturer. 15:0 OUI[21:6] RO 0x000E November 30, 2007 339 Preliminary LM3S6110 Microcontroller Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 This register, along with MR2, provides a 32-bit value indicating the manufacturer, model, and revision information. Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3) Base 0x4004.8000 Address 0x03 Type RO, reset 0x7237 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OUI[5:0] MN RN Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 Bit/Field Name Type Reset Description Organizationally Unique Identifier[5:0] This field, along with the OUI[21:6] field in MR2, makes up the Organizationally Unique Identifier indicating the PHY manufacturer. 15:10 OUI[5:0] RO 0x1C Model Number The MN field represents the Model Number of the PHY. 9:4 MN RO 0x23 Revision Number The RN field represents the Revision Number of the PHY. 3:0 RN RO 0x7 340 November 30, 2007 Preliminary Ethernet Controller Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address 0x04 This register provides the advertised abilities of the PHY used during Auto-Negotiation. Bits 8:5 represent the Technology Ability Field bits. This field can be overwritten by software to Auto-Negotiate to an alternate common technology. Writing to this register has no effect until Auto-Negotiation is re-initiated. Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4) Base 0x4004.8000 Address 0x04 Type R/W, reset 0x01E1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NP reserved RF reserved A3 A2 A1 A0 S[4:0] Type RO RO R/W RO RO RO RO R/W R/W R/W R/W RO RO RO RO RO Reset 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 Bit/Field Name Type Reset Description Next Page When set, indicates the PHY is capable of Next Page exchanges to provide more detailed information on the PHY’s capabilities. 15 NP RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 reserved RO 0 Remote Fault When set, indicates to the link partner that a Remote Fault condition has been encountered. 13 RF R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12:9 reserved RO 0 Technology Ability Field[3] When set, indicates that the PHY supports the 100Base-TX full-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be written to 0 and Auto-Negotiation re-initiated with the RANEG bit in the MR0 register. 8 A3 R/W 1 Technology Ability Field[2] When set, indicates that the PHY supports the 100Base-T half-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be written to 0 and Auto-Negotiation re-initiated. 7 A2 R/W 1 Technology Ability Field[1] When set, indicates that the PHY supports the 10Base-T full-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be written to 0 and Auto-Negotiation re-initiated. 6 A1 R/W 1 Technology Ability Field[0] When set, indicates that the PHY supports the 10Base-T half-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be written to 0 and Auto-Negotiation re-initiated. 5 A0 R/W 1 November 30, 2007 341 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description Selector Field The S[4:0] field encodes 32 possible messages for communicating between PHYs. This field is hard-coded to 0x01, indicating that the Stellaris® PHY is IEEE 802.3 compliant. 4:0 S[4:0] RO 0x01 342 November 30, 2007 Preliminary Ethernet Controller Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5), address 0x05 This register provides the advertised abilities of the link partner’s PHY that are received and stored during Auto-Negotiation. Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5) Base 0x4004.8000 Address 0x05 Type RO, reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NP ACK RF A[7:0] S[4:0] Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Next Page When set, indicates that the link partner’s PHY is capable of Next page exchanges to provide more detailed information on the PHY’s capabilities. 15 NP RO 0 Acknowledge When set, indicates that the device has successfully received the link partner’s advertised abilities during Auto-Negotiation. 14 ACK RO 0 Remote Fault Used as a standard transport mechanism for transmitting simple fault information. 13 RF RO 0 Technology Ability Field The A[7:0] field encodes individual technologies that are supported by the PHY. See the MR4 register. 12:5 A[7:0] RO 0x00 Selector Field The S[4:0] field encodes possible messages for communicating between PHYs. Value Description 0x00 Reserved 0x01 IEEE Std 802.3 0x02 IEEE Std 802.9 ISLAN-16T 0x03 IEEE Std 802.5 0x04 IEEE Std 1394 0x05–0x1F Reserved 4:0 S[4:0] RO 0x00 November 30, 2007 343 Preliminary LM3S6110 Microcontroller Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address 0x06 This register enables software to determine the Auto-Negotiation and Next Page capabilities of the PHY and the link partner after Auto-Negotiation. Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6) Base 0x4004.8000 Address 0x06 Type RO, reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PDF LPNPA reserved PRX LPANEGA Type RO RO RO RO RO RO RO RO RO RO RO RC RO RO RC RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:5 reserved RO 0x000 Parallel Detection Fault When set, indicates that more than one technology has been detected at link up. This bit is cleared when read. 4 PDF RC 0 Link Partner is Next Page Able When set, indicates that the link partner is Next Page Able. 3 LPNPA RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 reserved RO 0x000 New Page Received When set, indicates that a New Page has been received from the link partner and stored in the appropriate location. This bit remains set until the register is read. 1 PRX RC 0 Link Partner is Auto-Negotiation Able When set, indicates that the Link partner is Auto-Negotiation Able. 0 LPANEGA RO 0 344 November 30, 2007 Preliminary Ethernet Controller Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 This register enables software to configure the operation of vendor-specific modes of the PHY. Ethernet PHY Management Register 16 – Vendor-Specific (MR16) Base 0x4004.8000 Address 0x10 Type R/W, reset 0x0140 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RPTR INPOL reserved TXHIM SQEI NL10 reserved APOL RVSPOL reserved PCSBP RXCC Type R/W R/W RO R/W R/W R/W RO RO RO RO R/W R/W RO RO R/W R/W Reset 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 Bit/Field Name Type Reset Description Repeater Mode When set, enables the repeater mode of operation. In this mode, full-duplex is not allowed and the Carrier Sense signal only responds to receive activity. If the PHY is configured to 10Base-T mode, the SQE test function is disabled. 15 RPTR R/W 0 Interrupt Polarity 1: Sets the polarity of the PHY interrupt to be active High. 0: Sets the polarity of the PHY interrupt to active Low. Important: Because the Media Access Controller expects active Low interrupts from the PHY, this bit must always be written with a 0 to ensure proper operation. 14 INPOL R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 reserved RO 0 Transmit High Impedance Mode When set, enables the transmitter High Impedance mode. In this mode, the TXOP and TXON transmitter pins are put into a high impedance state. The RXIP and RXIN pins remain fully functional. 12 TXHIM R/W 0 SQE Inhibit Testing When set, prohibits 10Base-T SQE testing. When 0, the SQE testing is performed by generating a Collision pulse following the completion of the transmission of a frame. 11 SQEI R/W 0 Natural Loopback Mode When set, enables the 10Base-T Natural Loopback mode. This causes the transmission data received by the PHY to be looped back onto the receive data path when 10Base-T mode is enabled. 10 NL10 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9:6 reserved RO 0x05 November 30, 2007 345 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description Auto-Polarity Disable When set, disables the PHY’s auto-polarity function. If this bit is 0, the PHY automatically inverts the received signal due to a wrong polarity connection during Auto-Negotiation if the PHY is in 10Base-T mode. 5 APOL R/W 0 Receive Data Polarity This bit indicates whether the receive data pulses are being inverted. If the APOL bit is 0, then the RVSPOL bit is read-only and indicates whether the auto-polarity circuitry is reversing the polarity. In this case, a 1 in the RVSPOL bit indicates that the receive data is inverted while a 0 indicates that the receive data is not inverted. If the APOL bit is 1, then the RVSPOL bit is writable and software can force the receive data to be inverted. Setting RVSPOL to 1 forces the receive data to be inverted while a 0 does not invert the receive data. 4 RVSPOL R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0 PCS Bypass When set, enables the bypass of the PCS and scrambling/descrambling functions in 100Base-TX mode. This mode is only valid when Auto-Negotiation is disabled and 100Base-T mode is enabled. 1 PCSBP R/W 0 Receive Clock Control When set, enables the Receive Clock Control power saving mode if the PHY is configured in 100Base-TX mode. This mode shuts down the receive clock when no data is being received from the physical medium to save power. This mode should not be used when PCSBP is enabled and is automatically disabled when the LOOPBK bit in the MR0 register is set. 0 RXCC R/W 0 346 November 30, 2007 Preliminary Ethernet Controller Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address 0x11 This register provides the means for controlling and observing the events, which trigger a PHY interrupt in the MACRIS register. This register can also be used in a polling mode via the MII Serial Interface as a means to observe key events within the PHY via one register address. Bits 0 through 7 are status bits, which are each set to logic 1 based on an event. These bits are cleared after the register is read. Bits 8 through 15 of this register, when set to logic 1, enable their corresponding bit in the lower byte to signal a PHY interrupt in the MACRIS register. Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17) Base 0x4004.8000 Address 0x11 Type R/W, reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JABBER_IE RXER_IE PRX_IE PDF_IE LPACK_IELSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INTRXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT ANEGCOMP_INT Type R/W R/W R/W R/W R/W R/W R/W R/W RC RC RC RC RC RC RC RC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Jabber Interrupt Enable When set, enables system interrupts when a Jabber condition is detected by the PHY. 15 JABBER_IE R/W 0 Receive Error Interrupt Enable When set, enables system interrupts when a receive error is detected by the PHY. 14 RXER_IE R/W 0 Page Received Interrupt Enable When set, enables system interrupts when a new page is received by the PHY. 13 PRX_IE R/W 0 Parallel Detection Fault Interrupt Enable When set, enables system interrupts when a Parallel Detection Fault is detected by the PHY. 12 PDF_IE R/W 0 LP Acknowledge Interrupt Enable When set, enables system interrupts when FLP bursts are received with the Acknowledge bit during Auto-Negotiation. 11 LPACK_IE R/W 0 Link Status Change Interrupt Enable When set, enables system interrupts when the Link Status changes from OK to FAIL. 10 LSCHG_IE R/W 0 Remote Fault Interrupt Enable When set, enables system interrupts when a Remote Fault condition is signaled by the link partner. 9 RFAULT_IE R/W 0 Auto-Negotiation Complete Interrupt Enable When set, enables system interrupts when the Auto-Negotiation sequence has completed successfully. 8 ANEGCOMP_IE R/W 0 November 30, 2007 347 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description Jabber Event Interrupt When set, indicates that a Jabber event has been detected by the 10Base-T circuitry. 7 JABBER_INT RC 0 Receive Error Interrupt When set, indicates that a receive error has been detected by the PHY. 6 RXER_INT RC 0 Page Receive Interrupt When set, indicates that a new page has been received from the link partner during Auto-Negotiation. 5 PRX_INT RC 0 Parallel Detection Fault Interrupt When set, indicates that a Parallel Detection Fault has been detected by the PHY during the Auto-Negotiation process. 4 PDF_INT RC 0 LP Acknowledge Interrupt When set, indicates that an FLP burst has been received with the Acknowledge bit set during Auto-Negotiation. 3 LPACK_INT RC 0 Link Status Change Interrupt When set, indicates that the link status has changed from OK to FAIL. 2 LSCHG_INT RC 0 Remote Fault Interrupt When set, indicates that a Remote Fault condition has been signaled by the link partner. 1 RFAULT_INT RC 0 Auto-Negotiation Complete Interrupt When set, indicates that the Auto-Negotiation sequence has completed successfully. 0 ANEGCOMP_INT RC 0 348 November 30, 2007 Preliminary Ethernet Controller Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 This register enables software to diagnose the results of the previous Auto-Negotiation. Ethernet PHY Management Register 18 – Diagnostic (MR18) Base 0x4004.8000 Address 0x12 Type RO, reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ANEGF DPLX RATE RXSD RX_LOCK reserved Type RO RO RO RC RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 reserved RO 0 Auto-Negotiation Failure When set, indicates that no common technology was found during Auto-Negotiation and has failed. This bit remains set until read. 12 ANEGF RC 0 Duplex Mode When set, indicates that Full-Duplex was the highest common denominator found during the Auto-Negotiation process. Otherwise, Half-Duplex was the highest common denominator found. 11 DPLX RO 0 Rate When set, indicates that 100Base-TX was the highest common denominator found during the Auto-Negotiation process. Otherwise, 10Base-TX was the highest common denominator found. 10 RATE RO 0 Receive Detection When set, indicates that receive signal detection has occurred (in 100Base-TX mode) or that Manchester-encoded data has been detected (in 10Base-T mode). 9 RXSD RO 0 Receive PLL Lock When set, indicates that the Receive PLL has locked onto the receive signal for the selected speed of operation (10Base-T or 100Base-TX). 8 RX_LOCK RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 reserved RO 00 November 30, 2007 349 Preliminary LM3S6110 Microcontroller Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 This register enables software to set the gain of the transmit output to compensate for transformer loss. Ethernet PHY Management Register 19 – Transceiver Control (MR19) Base 0x4004.8000 Address 0x13 Type R/W, reset 0x4000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXO[1:0] reserved Type R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Transmit Amplitude Selection The TXO[1:0] field sets the transmit output amplitude to account for transmit transformer insertion loss. Value Description 0x0 Gain set for 0.0dB of insertion loss 0x1 Gain set for 0.4dB of insertion loss 0x2 Gain set for 0.8dB of insertion loss 0x3 Gain set for 1.2dB of insertion loss 15:14 TXO[1:0] R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13:0 reserved RO 0x0 350 November 30, 2007 Preliminary Ethernet Controller Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 This register enables software to select the source that will cause the LEDs to toggle. Ethernet PHY Management Register 23 – LED Configuration (MR23) Base 0x4004.8000 Address 0x17 Type R/W, reset 0x0010 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved LED1[3:0] LED0[3:0] Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:8 reserved RO 0x0 LED1 Source The LED1 field selects the source that will toggle the LED1 signal. Value Description 0x0 Link OK 0x1 RX or TX Activity (Default LED1) 0x2 TX Activity 0x3 RX Activity 0x4 Collision 0x5 100BASE-TX mode 0x6 10BASE-T mode 0x7 Full-Duplex 0x8 Link OK & Blink=RX or TX Activity 7:4 LED1[3:0] R/W 1 LED0 Source The LED0 field selects the source that will toggle the LED0 signal. Value Description 0x0 Link OK (Default LED0) 0x1 RX or TX Activity 0x2 TX Activity 0x3 RX Activity 0x4 Collision 0x5 100BASE-TX mode 0x6 10BASE-T mode 0x7 Full-Duplex 0x8 Link OK & Blink=RX or TX Activity 3:0 LED0[3:0] R/W 0 November 30, 2007 351 Preliminary LM3S6110 Microcontroller Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 This register enables software to control the behavior of the MDI/MDIX mux and its switching capabilities. Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24) Base 0x4004.8000 Address 0x18 Type R/W, reset 0x00C0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PD_MODEAUTO_SW MDIX MDIX_CM MDIX_SD Type RO RO RO RO RO RO RO RO R/W R/W R/W RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:8 reserved RO 0x0 Parallel Detection Mode When set, enables the Parallel Detection mode and allows auto-switching to work when Auto-Negotiation is not enabled. 7 PD_MODE R/W 0 Auto-Switching Enable When set, enables Auto-Switching of the MDI/MDIX mux. 6 AUTO_SW R/W 0 Auto-Switching Configuration When set, indicates that the MDI/MDIX mux is in the crossover (MDIX) configuration. When 0, it indicates that the mux is in the pass-through (MDI) configuration. When the AUTO_SW bit is 1, the MDIX bit is read-only. When the AUTO_SW bit is 0, the MDIX bit is read/write and can be configured manually. 5 MDIX R/W 0 Auto-Switching Complete When set, indicates that the auto-switching sequence has completed. If 0, it indicates that the sequence has not completed or that auto-switching is disabled. 4 MDIX_CM RO 0 Auto-Switching Seed This field provides the initial seed for the switching algorithm. This seed directly affects the number of attempts [5,4] respectively to write bits [3:0]. A 0 sets the seed to 0x5. 3:0 MDIX_SD R/W 0 352 November 30, 2007 Preliminary Ethernet Controller 14 Analog Comparators An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. The LM3S6110 controller provides three independent integrated analog comparators that can be configured to drive an output or generate an interrupt. Note: Not all comparators have the option to drive an output pin. See the Comparator Operating Mode tables for more information. A comparator can compare a test voltage against any one of these voltages: ■ An individual external reference voltage ■ A shared single external reference voltage ■ A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence. November 30, 2007 353 Preliminary LM3S6110 Microcontroller 14.1 Block Diagram Figure 14-1. Analog Comparator Module Block Diagram interrupt C2+ C2- output +ve input (alternate) +ve input interrupt -ve input reference input Comparator 2 ACSTAT2 ACCTL2 interrupt C1- C1+ output +ve input (alternate) +ve input interrupt -ve input reference input Comparator 1 ACSTAT1 ACCTL1 Voltage Ref ACREFCTL output +ve input (alternate) +ve input interrupt -ve input reference input Comparator 0 ACSTAT0 ACCTL0 C0+ internal bus interrupt C0- C0o 14.2 Functional Description Important: It is recommended that the Digital-Input enable (the GPIODEN bit in the GPIO module) for the analog input pin be disabled to prevent excessive current draw from the I/O pads. The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT. VIN- < VIN+, VOUT = 1 VIN- > VIN+, VOUT = 0 As shown in Figure 14-2 on page 355, the input source for VIN- is an external input. In addition to an external input, input sources for VIN+ can be the +ve input of comparator 0 or an internal reference. 354 November 30, 2007 Preliminary Analog Comparators Figure 14-2. Structure of Comparator Unit output -ve input +ve input interrupt internal bus +ve input (alternate) reference input ACCTL ACSTAT IntGen 2 1 0 CINV A comparator is configured through two status/control registers (ACCTL and ACSTAT ). The internal reference is configured through one control register (ACREFCTL). Interrupt status and control is configured through three registers (ACMIS, ACRIS, and ACINTEN). The operating modes of the comparators are shown in the Comparator Operating Mode tables. Typically, the comparator output is used internally to generate controller interrupts. It may also be used to drive an external pin. Important: Certain register bit values must be set before using the analog comparators. The proper pad configuration for the comparator input and output pins are described in the Comparator Operating Mode tables. Table 14-1. Comparator 0 Operating Modes ACCNTL0 Comparator 0 ASRCP VIN- VIN+ Output Interrupt 00 C0- C0+ C0o/C1+ yes 01 C0- C0+ C0o/C1+ yes 10 C0- Vref C0o/C1+ yes 11 C0- reserved C0o/C1+ yes Table 14-2. Comparator 1 Operating Modes ACCNTL1 Comparator 1 ASRCP VIN- VIN+ Output Interrupt 00 C1- C0o/C1+a n/a yes 01 C1- C0+ n/a yes 10 C1- Vref n/a yes 11 C1- reserved n/a yes a. C0o and C1+ signals share a single pin and may only be used as one or the other. November 30, 2007 355 Preliminary LM3S6110 Microcontroller Table 14-3. Comparator 2 Operating Modes ACCNTL2 Comparator 2 ASRCP VIN- VIN+ Output Interrupt 00 C2- C2+ n/a yes 01 C2- C0+ n/a yes 10 C2- Vref n/a yes 11 C2- reserved n/a yes 14.2.1 Internal Reference Programming The structure of the internal reference is shown in Figure 14-3 on page 356. This is controlled by a single configuration register (ACREFCTL). Table 14-4 on page 356 shows the programming options to develop specific internal reference values, to compare an external voltage against a particular voltage generated internally. Figure 14-3. Comparator Internal Reference Structure 8R R R 8R R R ••• ••• 0 Decoder 15 14 1 AVDD EN internal reference VREF RNG Table 14-4. Internal Reference Voltage and ACREFCTL Field Values ACREFCTL Register Output Reference Voltage Based on VREF Field Value EN Bit Value RNG Bit Value 0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and VREF=0 for the least noisy ground reference. EN=0 RNG=X 356 November 30, 2007 Preliminary Analog Comparators ACREFCTL Register Output Reference Voltage Based on VREF Field Value EN Bit Value RNG Bit Value Total resistance in ladder is 32 R. VREF AVDD R V REF RT = × ---------------- VREF AVDD (VREF + 8) 32 = × ------------------------------ VR EF = 0.825 + 0.103 VREF The range of internal reference in this mode is 0.825-2.37 V. EN=1 RNG=0 Total resistance in ladder is 24 R. VREF AVDD R V REF RT = × ---------------- VREF AVDD (VREF) 24 = × -------------------- VREF = 0.1375 x VREF The range of internal reference for this mode is 0.0-2.0625 V. RNG=1 14.3 Initialization and Configuration The following example shows how to configure an analog comparator to read back its output value from an internal register. 1. Enable the analog comparator 0 clock by writing a value of 0x0010.0000 to the RCGC1 register in the System Control module. 2. In the GPIO module, enable the GPIO port/pin associated with C0- as a GPIO input. 3. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the value 0x0000.030C. 4. Configure comparator 0 to use the internal voltage reference and to not invert the output on the C0o pin by writing the ACCTL0 register with the value of 0x0000.040C. 5. Delay for some time. 6. Read the comparator output value by reading the ACSTAT0 register’s OVAL value. Change the level of the signal input on C0- to see the OVAL value change. 14.4 Register Map Table 14-5 on page 358 lists the comparator registers. The offset listed is a hexadecimal increment to the register’s address, relative to the Analog Comparator base address of 0x4003.C000. November 30, 2007 357 Preliminary LM3S6110 Microcontroller Table 14-5. Analog Comparators Register Map See Offset Name Type Reset Description page 0x00 ACMIS R/W1C 0x0000.0000 Analog Comparator Masked Interrupt Status 359 0x04 ACRIS RO 0x0000.0000 Analog Comparator Raw Interrupt Status 360 0x08 ACINTEN R/W 0x0000.0000 Analog Comparator Interrupt Enable 361 0x10 ACREFCTL R/W 0x0000.0000 Analog Comparator Reference Voltage Control 362 0x20 ACSTAT0 RO 0x0000.0000 Analog Comparator Status 0 363 0x24 ACCTL0 R/W 0x0000.0000 Analog Comparator Control 0 364 0x40 ACSTAT1 RO 0x0000.0000 Analog Comparator Status 1 363 0x44 ACCTL1 R/W 0x0000.0000 Analog Comparator Control 1 364 0x60 ACSTAT2 RO 0x0000.0000 Analog Comparator Status 2 363 0x64 ACCTL2 R/W 0x0000.0000 Analog Comparator Control 2 364 14.5 Register Descriptions The remainder of this section lists and describes the Analog Comparator registers, in numerical order by address offset. 358 November 30, 2007 Preliminary Analog Comparators Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 This register provides a summary of the interrupt status (masked) of the comparator. Analog Comparator Masked Interrupt Status (ACMIS) Base 0x4003.C000 Offset 0x00 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IN2 IN1 IN0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:3 reserved RO 0x00 Comparator 2 Masked Interrupt Status Gives the masked interrupt state of this interrupt. Write 1 to this bit to clear the pending interrupt. 2 IN2 R/W1C 0 Comparator 1 Masked Interrupt Status Gives the masked interrupt state of this interrupt. Write 1 to this bit to clear the pending interrupt. 1 IN1 R/W1C 0 Comparator 0 Masked Interrupt Status Gives the masked interrupt state of this interrupt. Write 1 to this bit to clear the pending interrupt. 0 IN0 R/W1C 0 November 30, 2007 359 Preliminary LM3S6110 Microcontroller Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 This register provides a summary of the interrupt status (raw) of the comparator. Analog Comparator Raw Interrupt Status (ACRIS) Base 0x4003.C000 Offset 0x04 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IN2 IN1 IN0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:3 reserved RO 0x00 Comparator 2 Interrupt Status When set, indicates that an interrupt has been generated by comparator 2. 2 IN2 RO 0 Comparator 1 Interrupt Status When set, indicates that an interrupt has been generated by comparator 1. 1 IN1 RO 0 Comparator 0 Interrupt Status When set, indicates that an interrupt has been generated by comparator 0. 0 IN0 RO 0 360 November 30, 2007 Preliminary Analog Comparators Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 This register provides the interrupt enable for the comparator. Analog Comparator Interrupt Enable (ACINTEN) Base 0x4003.C000 Offset 0x08 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IN2 IN1 IN0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:3 reserved RO 0x00 Comparator 2 Interrupt Enable When set, enables the controller interrupt from the comparator 2 output 2 IN2 R/W 0 Comparator 1 Interrupt Enable When set, enables the controller interrupt from the comparator 1 output. 1 IN1 R/W 0 Comparator 0 Interrupt Enable When set, enables the controller interrupt from the comparator 0 output. 0 IN0 R/W 0 November 30, 2007 361 Preliminary LM3S6110 Microcontroller Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 This register specifies whether the resistor ladder is powered on as well as the range and tap. Analog Comparator Reference Voltage Control (ACREFCTL) Base 0x4003.C000 Offset 0x10 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved EN RNG reserved VREF Type RO RO RO RO RO RO R/W R/W RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:10 reserved RO 0x00 Resistor Ladder Enable The EN bit specifies whether the resistor ladder is powered on. If 0, the resistor ladder is unpowered. If 1, the resistor ladder is connected to the analog VDD. This bit is reset to 0 so that the internal reference consumes the least amount of power if not used and programmed. 9 EN R/W 0 Resistor Ladder Range The RNG bit specifies the range of the resistor ladder. If 0, the resistor ladder has a total resistance of 32 R. If 1, the resistor ladder has a total resistance of 24 R. 8 RNG R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0x00 Resistor Ladder Voltage Ref The VREF bit field specifies the resistor ladder tap that is passed through an analog multiplexer. The voltage corresponding to the tap position is the internal reference voltage available for comparison. See Table 14-4 on page 356 for some output reference voltage examples. 3:0 VREF R/W 0x00 362 November 30, 2007 Preliminary Analog Comparators Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60 These registers specify the current output value of the comparator. Analog Comparator Status 0 (ACSTAT0) Base 0x4003.C000 Offset 0x20 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OVAL reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 Comparator Output Value The OVAL bit specifies the current output value of the comparator. 1 OVAL RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 November 30, 2007 363 Preliminary LM3S6110 Microcontroller Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24 Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44 Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64 These registers configure the comparator’s input and output. Analog Comparator Control 0 (ACCTL0) Base 0x4003.C000 Offset 0x24 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ASRCP reserved ISLVAL ISEN CINV reserved Type RO RO RO RO RO R/W R/W RO RO RO RO R/W R/W R/W R/W RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 Analog Source Positive The ASRCP field specifies the source of input voltage to the VIN+ terminal of the comparator. The encodings for this field are as follows: Value Function 0x0 Pin value 0x1 Pin value of C0+ 0x2 Internal voltage reference 0x3 Reserved 10:9 ASRCP R/W 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8:5 reserved RO 0 Interrupt Sense Level Value The ISLVAL bit specifies the sense value of the input that generates an interrupt if in Level Sense mode. If 0, an interrupt is generated if the comparator output is Low. Otherwise, an interrupt is generated if the comparator output is High. 4 ISLVAL R/W 0 364 November 30, 2007 Preliminary Analog Comparators Bit/Field Name Type Reset Description Interrupt Sense The ISEN field specifies the sense of the comparator output that generates an interrupt. The sense conditioning is as follows: Value Function 0x0 Level sense, see ISLVAL 0x1 Falling edge 0x2 Rising edge 0x3 Either edge 3:2 ISEN R/W 0x0 Comparator Output Invert The CINV bit conditionally inverts the output of the comparator. If 0, the output of the comparator is unchanged. If 1, the output of the comparator is inverted prior to being processed by hardware. 1 CINV R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 November 30, 2007 365 Preliminary LM3S6110 Microcontroller 15 Pulse Width Modulator (PWM) Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. The Stellaris® PWM module consists of one PWM generator block and a control block. The PWM generator block contains one timer (16-bit down or up/down counter), two PWM comparators, a PWM signal generator, a dead-band generator, and an interrupt selector. The control block determines the polarity of the PWM signals, and which signals are passed through to the pins. The PWM generator block produces two PWM signals that can either be independent signals (other than being based on the same timer and therefore having the same frequency) or a single pair of complementary signals with dead-band delays inserted. The output of the PWM generation block is managed by the output control block before being passed to the device pins. The Stellaris® PWM module provides a great deal of flexibility. It can generate simple PWM signals, such as those required by a simple charge pump. It can also generate paired PWM signals with dead-band delays, such as those required by a half-H bridge driver. 15.1 Block Diagram Figure 15-1 on page 366 provides a block diagram of a Stellaris® PWM module. The LM3S6110 controller contains one generator block (PWM0) and generates two independent PWM signals or one paired PWM signal with dead-band delays inserted. Figure 15-1. PWM Module Block Diagram Interrupt and Trigger Generate PWMnINTEN PWMnRIS PWMnISC PWM Clock Interrupt Dead-Band Generator PWMnDBCTL PWMnDBRISE PWMnDBFALL PWM Output Control PWMENABLE PWMINVERT PWMFAULT PWM Generator PWMnGENA PWMnGENB pwma pwmb Timer PWMnLOAD PWMnCOUNT Comparator A PWMnCMPA Comparator B PWMnCMPB zero load dir 16 cmpA cmpB Fault PWM Generator Block 15.2 Functional Description 15.2.1 PWM Timer The timer runs in one of two modes: Count-Down mode or Count-Up/Down mode. In Count-Down mode, the timer counts from the load value to zero, goes back to the load value, and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the load value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode is used for 366 November 30, 2007 Preliminary Pulse Width Modulator (PWM) generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used for generating center-aligned PWM signals. The timers output three signals that are used in the PWM generation process: the direction signal (this is always Low in Count-Down mode, but alternates between Low and High in Count-Up/Down mode), a single-clock-cycle-width High pulse when the counter is zero, and a single-clock-cycle-width High pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero pulse is immediately followed by the load pulse. 15.2.2 PWM Comparators There are two comparators in the PWM generator that monitor the value of the counter; when either match the counter, they output a single-clock-cycle-width High pulse. When in Count-Up/Down mode, these comparators match both when counting up and when counting down; they are therefore qualified by the counter direction signal. These qualified pulses are used in the PWM generation process. If either comparator match value is greater than the counter load value, then that comparator never outputs a High pulse. Figure 15-2 on page 367 shows the behavior of the counter and the relationship of these pulses when the counter is in Count-Down mode. Figure 15-3 on page 368 shows the behavior of the counter and the relationship of these pulses when the counter is in Count-Up/Down mode. Figure 15-2. PWM Count-Down Mode Load Zero CompB CompA Load Zero B A Dir ADown BDown November 30, 2007 367 Preliminary LM3S6110 Microcontroller Figure 15-3. PWM Count-Up/Down Mode Load Zero CompB CompA Load Zero B A Dir BUp AUp ADown BDown 15.2.3 PWM Signal Generator The PWM generator takes these pulses (qualified by the direction signal), and generates two PWM signals. In Count-Down mode, there are four events that can affect the PWM signal: zero, load, match A down, and match B down. In Count-Up/Down mode, there are six events that can affect the PWM signal: zero, load, match A down, match A up, match B down, and match B up. The match A or match B events are ignored when they coincide with the zero or load events. If the match A and match B events coincide, the first signal, PWMA, is generated based only on the match A event, and the second signal, PWMB, is generated based only on the match B event. For each event, the effect on each output PWM signal is programmable: it can be left alone (ignoring the event), it can be toggled, it can be driven Low, or it can be driven High. These actions can be used to generate a pair of PWM signals of various positions and duty cycles, which do or do not overlap. Figure 15-4 on page 368 shows the use of Count-Up/Down mode to generate a pair of center-aligned, overlapped PWM signals that have different duty cycles. Figure 15-4. PWM Generation Example In Count-Up/Down Mode Load Zero CompB CompA PWMB PWMA In this example, the first generator is set to drive High on match A up, drive Low on match A down, and ignore the other four events. The second generator is set to drive High on match B up, drive Low on match B down, and ignore the other four events. Changing the value of comparator A 368 November 30, 2007 Preliminary Pulse Width Modulator (PWM) changes the duty cycle of the PWMA signal, and changing the value of comparator B changes the duty cycle of the PWMB signal. 15.2.4 Dead-Band Generator The two PWM signals produced by the PWM generator are passed to the dead-band generator. If disabled, the PWM signals simply pass through unmodified. If enabled, the second PWM signal is lost and two PWM signals are generated based on the first PWM signal. The first output PWM signal is the input signal with the rising edge delayed by a programmable amount. The second output PWM signal is the inversion of the input signal with a programmable delay added between the falling edge of the input signal and the rising edge of this new signal. This is therefore a pair of active High signals where one is always High, except for a programmable amount of time at transitions where both are Low. These signals are therefore suitable for driving a half-H bridge, with the dead-band delays preventing shoot-through current from damaging the power electronics. Figure 15-5 on page 369 shows the effect of the dead-band generator on an input PWM signal. Figure 15-5. PWM Dead-Band Generator Input PWMA PWMB Rising Edge Delay Falling Edge Delay 15.2.5 Interrupt Selector The PWM generator also takes the same four (or six) counter events and uses them to generate an interrupt. Any of these events or a set of these events can be selected as a source for an interrupt; when any of the selected events occur, an interrupt is generated. The selection of events allows the interrupt to occur at a specific position within the PWM signal. Note that interrupts are based on the raw events; delays in the PWM signal edges caused by the dead-band generator are not taken into account. 15.2.6 Synchronization Methods There is a global reset capability that can reset the counter of the PWM generator. The counter load values and comparator match values of the PWM generator can be updated in two ways. The first is immediate update mode, where a new value is used as soon as the counter reaches zero. By waiting for the counter to reach zero, a guaranteed behavior is defined, and overly short or overly long output PWM pulses are prevented. The other update method is synchronous, where the new value is not used until a global synchronized update signal is asserted, at which point the new value is used as soon as the counter reaches zero. This second mode allows multiple items to be updated simultaneously without odd effects during the update; everything runs from the old values until a point at which they all run from the new values. 15.2.7 Fault Conditions There are two external conditions that affect the PWM block; the signal input on the Fault pin and the stalling of the controller by a debugger. There are two mechanisms available to handle such November 30, 2007 369 Preliminary LM3S6110 Microcontroller conditions: the output signals can be forced into an inactive state and/or the PWM timers can be stopped. Each output signal has a fault bit. If set, a fault input signal causes the corresponding output signal to go into the inactive state. If the inactive state is a safe condition for the signal to be in for an extended period of time, this keeps the output signal from driving the outside world in a dangerous manner during the fault condition. A fault condition can also generate a controller interrupt. Each PWM generator can also be configured to stop counting during a stall condition. The user can select for the counters to run until they reach zero then stop, or to continue counting and reloading. A stall condition does not generate a controller interrupt. 15.2.8 Output Control Block With the PWM generator block producing two raw PWM signals, the output control block takes care of the final conditioning of the PWM signals before they go to the pins. Via a single register, the set of PWM signals that are actually enabled to the pins can be modified; this can be used, for example, to perform commutation of a brushless DC motor with a single register write (and without modifying the individual PWM generators, which are modified by the feedback control loop). Similarly, fault control can disable any of the PWM signals as well. A final inversion can be applied to any of the PWM signals, making them active Low instead of the default active High. 15.3 Initialization and Configuration The following example shows how to initialize the PWM Generator 0 with a 25-KHz frequency, and with a 25% duty cycle on the PWM0 pin and a 75% duty cycle on the PWM1 pin. This example assumes the system clock is 20 MHz. 1. Enable the PWM clock by writing a value of 0x0010.0000 to the RCGC0 register in the System Control module. 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module. 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register. 4. Configure the Run-Mode Clock Configuration (RCC) register in the System Control module to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000). 5. Configure the PWM generator for countdown mode with immediate updates to the parameters. ■ Write the PWM0CTL register with a value of 0x0000.0000. ■ Write the PWM0GENA register with a value of 0x0000.008C. ■ Write the PWM0GENB register with a value of 0x0000.080C. 6. Set the period. For a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM clock source is 10 MHz; the system clock divided by 2. This translates to 400 clock ticks per period. Use this value to set the PWM0LOAD register. In Count-Down mode, set the Load field in the PWM0LOAD register to the requested period minus one. ■ Write the PWM0LOAD register with a value of 0x0000.018F. 7. Set the pulse width of the PWM0 pin for a 25% duty cycle. 370 November 30, 2007 Preliminary Pulse Width Modulator (PWM) ■ Write the PWM0CMPA register with a value of 0x0000.012B. 8. Set the pulse width of the PWM1 pin for a 75% duty cycle. ■ Write the PWM0CMPB register with a value of 0x0000.0063. 9. Start the timers in PWM generator 0. ■ Write the PWM0CTL register with a value of 0x0000.0001. 10. Enable PWM outputs. ■ Write the PWMENABLE register with a value of 0x0000.0003. 15.4 Register Map Table 15-1 on page 371 lists the PWM registers. The offset listed is a hexadecimal increment to the register’s address, relative to the PWM base address of 0x4002.8000. Table 15-1. PWM Register Map See Offset Name Type Reset Description page 0x000 PWMCTL R/W 0x0000.0000 PWM Master Control 373 0x004 PWMSYNC R/W 0x0000.0000 PWM Time Base Sync 374 0x008 PWMENABLE R/W 0x0000.0000 PWM Output Enable 375 0x00C PWMINVERT R/W 0x0000.0000 PWM Output Inversion 376 0x010 PWMFAULT R/W 0x0000.0000 PWM Output Fault 377 0x014 PWMINTEN R/W 0x0000.0000 PWM Interrupt Enable 378 0x018 PWMRIS RO 0x0000.0000 PWM Raw Interrupt Status 379 0x01C PWMISC R/W1C 0x0000.0000 PWM Interrupt Status and Clear 380 0x020 PWMSTATUS RO 0x0000.0000 PWM Status 381 0x040 PWM0CTL R/W 0x0000.0000 PWM0 Control 382 0x044 PWM0INTEN R/W 0x0000.0000 PWM0 Interrupt Enable 384 0x048 PWM0RIS RO 0x0000.0000 PWM0 Raw Interrupt Status 386 0x04C PWM0ISC R/W1C 0x0000.0000 PWM0 Interrupt Status and Clear 387 0x050 PWM0LOAD R/W 0x0000.0000 PWM0 Load 388 0x054 PWM0COUNT RO 0x0000.0000 PWM0 Counter 389 0x058 PWM0CMPA R/W 0x0000.0000 PWM0 Compare A 390 0x05C PWM0CMPB R/W 0x0000.0000 PWM0 Compare B 391 0x060 PWM0GENA R/W 0x0000.0000 PWM0 Generator A Control 392 0x064 PWM0GENB R/W 0x0000.0000 PWM0 Generator B Control 395 0x068 PWM0DBCTL R/W 0x0000.0000 PWM0 Dead-Band Control 398 November 30, 2007 371 Preliminary LM3S6110 Microcontroller See Offset Name Type Reset Description page 0x06C PWM0DBRISE R/W 0x0000.0000 PWM0 Dead-Band Rising-Edge Delay 399 0x070 PWM0DBFALL R/W 0x0000.0000 PWM0 Dead-Band Falling-Edge-Delay 400 15.5 Register Descriptions The remainder of this section lists and describes the PWM registers, in numerical order by address offset. 372 November 30, 2007 Preliminary Pulse Width Modulator (PWM) Register 1: PWM Master Control (PWMCTL), offset 0x000 This register provides master control over the PWM generation block. PWM Master Control (PWMCTL) Base 0x4002.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GlobalSync0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Update PWM Generator 0 Setting this bit causes any queued update to a load or comparator register in PWM generator 0 to be applied the next time the corresponding counter becomes zero. This bit automatically clears when the updates have completed; it cannot be cleared by software. 0 GlobalSync0 R/W 0 November 30, 2007 373 Preliminary LM3S6110 Microcontroller Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 This register provides a method to perform synchronization of the counters in the PWM generation blocks. Writing a bit in this register to 1 causes the specified counter to reset back to 0; writing multiple bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred; reading them back as zero indicates that the synchronization has completed. PWM Time Base Sync (PWMSYNC) Base 0x4002.8000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Sync0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Reset Generator 0 Counter Performs a reset of the PWM generator 0 counter. 0 Sync0 R/W 0 374 November 30, 2007 Preliminary Pulse Width Modulator (PWM) Register 3: PWM Output Enable (PWMENABLE), offset 0x008 This register provides a master control of which generated PWM signals are output to device pins. By disabling a PWM output, the generation process can continue (for example, when the time bases are synchronized) without driving PWM signals to the pins. When bits in this register are set, the corresponding PWM signal is passed through to the output stage, which is controlled by the PWMINVERT register. When bits are not set, the PWM signal is replaced by a zero value which is also passed to the output stage. PWM Output Enable (PWMENABLE) Base 0x4002.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PWM1En PWM0En Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 PWM1 Output Enable When set, allows the generated PWM1 signal to be passed to the device pin. 1 PWM1En R/W 0 PWM0 Output Enable When set, allows the generated PWM0 signal to be passed to the device pin. 0 PWM0En R/W 0 November 30, 2007 375 Preliminary LM3S6110 Microcontroller Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C This register provides a master control of the polarity of the PWM signals on the device pins. The PWM signals generated by the PWM generator are active High; they can optionally be made active Low via this register. Disabled PWM channels are also passed through the output inverter (if so configured) so that inactive channels maintain the correct polarity. PWM Output Inversion (PWMINVERT) Base 0x4002.8000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PWM1Inv PWM0Inv Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 Invert PWM1 Signal When set, the generated PWM1 signal is inverted. 1 PWM1Inv R/W 0 Invert PWM0 Signal When set, the generated PWM0 signal is inverted. 0 PWM0Inv R/W 0 376 November 30, 2007 Preliminary Pulse Width Modulator (PWM) Register 5: PWM Output Fault (PWMFAULT), offset 0x010 This register controls the behavior of the PWM outputs in the presence of fault conditions. Both the fault input and debug events are considered fault conditions. On a fault condition, each PWM signal can either be passed through unmodified or driven Low. For outputs that are configured for pass-through, the debug event handling on the corresponding PWM generator also determines if the PWM signal continues to be generated. Fault condition control happens before the output inverter, so PWM signals driven Low on fault are inverted if the channel is configured for inversion (therefore, the pin is driven High on a fault condition). PWM Output Fault (PWMFAULT) Base 0x4002.8000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Fault1 Fault0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 PWM1 Driven Low on Fault When set, the PWM1 output signal is driven Low on a fault condition. 1 Fault1 R/W 0 PWM0 Driven Low on Fault When set, the PWM0 output signal is driven Low on a fault condition. 0 Fault0 R/W 0 November 30, 2007 377 Preliminary LM3S6110 Microcontroller Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 This register controls the global interrupt generation capabilities of the PWM module. The events that can cause an interrupt are the fault input and the individual interrupts from the PWM generator. PWM Interrupt Enable (PWMINTEN) Base 0x4002.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved IntFault Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IntPWM0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:17 reserved RO 0x00 Fault Interrupt Enable When 1, an interrupt occurs when the fault input is asserted. 16 IntFault R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:1 reserved RO 0x00 PWM0 Interrupt Enable When 1, an interrupt occurs when the PWM generator 0 block asserts an interrupt. 0 IntPWM0 R/W 0 378 November 30, 2007 Preliminary Pulse Width Modulator (PWM) Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 This register provides the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller. The fault interrupt is latched on detection; it must be cleared through the PWM Interrupt Status and Clear (PWMISC) register (see page 380). The PWM generator interrupts simply reflect the status of the PWM generator; they are cleared via the interrupt status register in the PWM generator block. Bits set to 1 indicate the events that are active; a zero bit indicates that the event in question is not active. PWM Raw Interrupt Status (PWMRIS) Base 0x4002.8000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved IntFault Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IntPWM0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:17 reserved RO 0x00 Fault Interrupt Asserted Indicates that the fault input has been asserted. 16 IntFault RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:1 reserved RO 0x00 PWM0 Interrupt Asserted Indicates that the PWM generator 0 block is asserting its interrupt. 0 IntPWM0 RO 0 November 30, 2007 379 Preliminary LM3S6110 Microcontroller Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C This register provides a summary of the interrupt status of the PWM generator block. A bit set to 1 indicates that the generator block is asserting an interrupt. The individual interrupt status registers must be consulted to determine the reason for the interrupt, and used to clear the interrupt. For the fault interrupt, a write of 1 to that bit position clears the latched interrupt status. PWM Interrupt Status and Clear (PWMISC) Base 0x4002.8000 Offset 0x01C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved IntFault Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IntPWM0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:17 reserved RO 0x00 Fault Interrupt Asserted Indicates if the fault input is asserting an interrupt. 16 IntFault R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:1 reserved RO 0x00 PWM0 Interrupt Status Indicates if the PWM generator 0 block is asserting an interrupt. 0 IntPWM0 RO 0 380 November 30, 2007 Preliminary Pulse Width Modulator (PWM) Register 9: PWM Status (PWMSTATUS), offset 0x020 This register provides the status of the Fault input signal. PWM Status (PWMSTATUS) Base 0x4002.8000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Fault Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Fault Interrupt Status When set to 1, indicates the fault input is asserted. 0 Fault RO 0 November 30, 2007 381 Preliminary LM3S6110 Microcontroller Register 10: PWM0 Control (PWM0CTL), offset 0x040 This register configures the PWM signal generation block. The Register Update mode, Debug mode, Counting mode, and Block Enable mode are all controlled via this register. The block produces the PWM signals, which can be either two independent PWM signals (from the same counter), or a paired set of PWM signals with dead-band delays added. These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator 0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable mode are all controlled via these registers. The blocks produce the PWM signals, which can be either two independent PWM signals (from the same counter), or a paired set of PWM signals with dead-band delays added. The PWM0 block produces the PWM0 and PWM1 outputs. PWM0 Control (PWM0CTL) Base 0x4002.8000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CmpBUpdCmpAUpd LoadUpd Debug Mode Enable Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0x00 Comparator B Update Mode Same as CmpAUpd but for the comparator B register. 5 CmpBUpd R/W 0 Comparator A Update Mode The Update mode for the comparator A register. If 0, updates to the register are reflected to the comparator the next time the counter is 0. If 1, updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 373). 4 CmpAUpd R/W 0 Load Register Update Mode The Update mode for the load register. If 0, updates to the register are reflected to the counter the next time the counter is 0. If 1, updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWM Master Control (PWMCTL) register. 3 LoadUpd R/W 0 Debug Mode The behavior of the counter in Debug mode. If 0, the counter stops running when it next reaches 0, and continues running again when no longer in Debug mode. If 1, the counter always runs. 2 Debug R/W 0 382 November 30, 2007 Preliminary Pulse Width Modulator (PWM) Bit/Field Name Type Reset Description Counter Mode The mode for the counter. If 0, the counter counts down from the load value to 0 and then wraps back to the load value (Count-Down mode). If 1, the counter counts up from 0 to the load value, back down to 0, and then repeats (Count-Up/Down mode). 1 Mode R/W 0 PWM Block Enable Master enable for the PWM generation block. If 0, the entire block is disabled and not clocked. If 1, the block is enabled and produces PWM signals. 0 Enable R/W 0 November 30, 2007 383 Preliminary LM3S6110 Microcontroller Register 11: PWM0 Interrupt Enable (PWM0INTEN), offset 0x044 This register controls the interrupt generation capabilities of the PWM generator. The events that can cause an interrupt are: ■ The counter being equal to the load register ■ The counter being equal to zero ■ The counter being equal to the comparator A register while counting up ■ The counter being equal to the comparator A register while counting down ■ The counter being equal to the comparator B register while counting up ■ The counter being equal to the comparator B register while counting down Any combination of these events can generate either an interrupt. PWM0 Interrupt Enable (PWM0INTEN) Base 0x4002.8000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IntCmpBDIntCmpBUIntCmpADIntCmpAU IntCntLoad IntCntZero Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0x00 Interrupt for Counter=Comparator B Down When 1, an interrupt occurs when the counter matches the comparator B value and the counter is counting down. 5 IntCmpBD R/W 0 Interrupt for Counter=Comparator B Up When 1, an interrupt occurs when the counter matches the comparator B value and the counter is counting up. 4 IntCmpBU R/W 0 Interrupt for Counter=Comparator A Down When 1, an interrupt occurs when the counter matches the comparator A value and the counter is counting down. 3 IntCmpAD R/W 0 Interrupt for Counter=Comparator A Up When 1, an interrupt occurs when the counter matches the comparator A value and the counter is counting up. 2 IntCmpAU R/W 0 384 November 30, 2007 Preliminary Pulse Width Modulator (PWM) Bit/Field Name Type Reset Description Interrupt for Counter=Load When 1, an interrupt occurs when the counter matches the PWMnLOAD register. 1 IntCntLoad R/W 0 Interrupt for Counter=0 When 1, an interrupt occurs when the counter is 0. 0 IntCntZero R/W 0 November 30, 2007 385 Preliminary LM3S6110 Microcontroller Register 12: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 This register provides the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller. Bits set to 1 indicate the latched events that have occurred; a 0 bit indicates that the event in question has not occurred. PWM0 Raw Interrupt Status (PWM0RIS) Base 0x4002.8000 Offset 0x048 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IntCmpBDIntCmpBUIntCmpADIntCmpAU IntCntLoad IntCntZero Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0x00 Comparator B Down Interrupt Status Indicates that the counter has matched the comparator B value while counting down. 5 IntCmpBD RO 0 Comparator B Up Interrupt Status Indicates that the counter has matched the comparator B value while counting up. 4 IntCmpBU RO 0 Comparator A Down Interrupt Status Indicates that the counter has matched the comparator A value while counting down. 3 IntCmpAD RO 0 Comparator A Up Interrupt Status Indicates that the counter has matched the comparator A value while counting up. 2 IntCmpAU RO 0 Counter=Load Interrupt Status Indicates that the counter has matched the PWMnLOAD register. 1 IntCntLoad RO 0 Counter=0 Interrupt Status Indicates that the counter has matched 0. 0 IntCntZero RO 0 386 November 30, 2007 Preliminary Pulse Width Modulator (PWM) Register 13: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C This register provides the current set of interrupt sources that are asserted to the controller. Bits set to 1 indicate the latched events that have occurred; a 0 bit indicates that the event in question has not occurred. These are R/W1C registers; writing a 1 to a bit position clears the corresponding interrupt reason. PWM0 Interrupt Status and Clear (PWM0ISC) Base 0x4002.8000 Offset 0x04C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IntCmpBDIntCmpBUIntCmpADIntCmpAU IntCntLoad IntCntZero Type RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0x00 Comparator B Down Interrupt Indicates that the counter has matched the comparator B value while counting down. 5 IntCmpBD R/W1C 0 Comparator B Up Interrupt Indicates that the counter has matched the comparator B value while counting up. 4 IntCmpBU R/W1C 0 Comparator A Down Interrupt Indicates that the counter has matched the comparator A value while counting down. 3 IntCmpAD R/W1C 0 Comparator A Up Interrupt Indicates that the counter has matched the comparator A value while counting up. 2 IntCmpAU R/W1C 0 Counter=Load Interrupt Indicates that the counter has matched the PWMnLOAD register. 1 IntCntLoad R/W1C 0 Counter=0 Interrupt Indicates that the counter has matched 0. 0 IntCntZero R/W1C 0 November 30, 2007 387 Preliminary LM3S6110 Microcontroller Register 14: PWM0 Load (PWM0LOAD), offset 0x050 This register contains the load value for the PWM counter. Based on the counter mode, either this value is loaded into the counter after it reaches zero, or it is the limit of up-counting after which the counter decrements back to zero. If the Load Value Update mode is immediate, this value is used the next time the counter reaches zero; if the mode is synchronous, it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 373). If this register is re-written before the actual update occurs, the previous value is never used and is lost. PWM0 Load (PWM0LOAD) Base 0x4002.8000 Offset 0x050 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Load Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x00 Counter Load Value The counter load value. 15:0 Load R/W 0 388 November 30, 2007 Preliminary Pulse Width Modulator (PWM) Register 15: PWM0 Counter (PWM0COUNT), offset 0x054 This register contains the current value of the PWM counter. When this value matches the load register, a pulse is output; this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers, see page 392 and page 395) or drive an interrupt (via the PWMnINTEN register, see page 384). A pulse with the same capabilities is generated when this value is zero. PWM0 Counter (PWM0COUNT) Base 0x4002.8000 Offset 0x054 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Count Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x00 Counter Value The current value of the counter. 15:0 Count RO 0x00 November 30, 2007 389 Preliminary LM3S6110 Microcontroller Register 16: PWM0 Compare A (PWM0CMPA), offset 0x058 This register contains a value to be compared against the counter . When this value matches the counter, a pulse is output; this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an interrupt (via the PWMnINTEN register). If the value of this register is greater than the PWMnLOAD register (see page 388), then no pulse is ever output. If the comparator A update mode is immediate (based on the CmpAUpd bit in the PWMnCTL register), then this 16-bit CompA value is used the next time the counter reaches zero. If the update mode is synchronous, it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 373). If this register is rewritten before the actual update occurs, the previous value is never used and is lost. PWM0 Compare A (PWM0CMPA) Base 0x4002.8000 Offset 0x058 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CompA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x00 Comparator A Value The value to be compared against the counter. 15:0 CompA R/W 0x00 390 November 30, 2007 Preliminary Pulse Width Modulator (PWM) Register 17: PWM0 Compare B (PWM0CMPB), offset 0x05C This register contains a value to be compared against the counter. When this value matches the counter, a pulse is output; this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an interrupt (via the PWMnINTEN register). If the value of this register is greater than the PWMnLOAD register, then no pulse is ever output. IF the comparator B update mode is immediate (based on the CmpBUpd bit in the PWMnCTL register), then this 16-bit CompB value is used the next time the counter reaches zero. If the update mode is synchronous, it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 373). If this register is rewritten before the actual update occurs, the previous value is never used and is lost. PWM0 Compare B (PWM0CMPB) Base 0x4002.8000 Offset 0x05C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CompB Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x00 Comparator B Value The value to be compared against the counter. 15:0 CompB R/W 0x00 November 30, 2007 391 Preliminary LM3S6110 Microcontroller Register 18: PWM0 Generator A Control (PWM0GENA), offset 0x060 This register controls the generation of the PWMnA signal based on the load and zero output pulses from the counter, as well as the compare A and compare B pulses from the comparators. When the counter is running in Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six occur. These events provide great flexibility in the positioning and duty cycle of the PWM signal that is produced. The PWM0GENA register controls generation of the PWM0A signal. If a zero or load event coincides with a compare A or compare B event, the zero or load action is taken and the compare A or compare B action is ignored. If a compare A event coincides with a compare B event, the compare A action is taken and the compare B action is ignored. PWM0 Generator A Control (PWM0GENA) Base 0x4002.8000 Offset 0x060 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:12 reserved RO 0x00 Action for Comparator B Down The action to be taken when the counter matches comparator B while counting down. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 11:10 ActCmpBD R/W 0x0 392 November 30, 2007 Preliminary Pulse Width Modulator (PWM) Bit/Field Name Type Reset Description Action for Comparator B Up The action to be taken when the counter matches comparator B while counting up. Occurs only when the Mode bit in the PWMnCTL register (see page 382) is set to 1. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 9:8 ActCmpBU R/W 0x0 Action for Comparator A Down The action to be taken when the counter matches comparator A while counting down. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 7:6 ActCmpAD R/W 0x0 Action for Comparator A Up The action to be taken when the counter matches comparator A while counting up. Occurs only when the Mode bit in the PWMnCTL register is set to 1. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 5:4 ActCmpAU R/W 0x0 Action for Counter=Load The action to be taken when the counter matches the load value. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 3:2 ActLoad R/W 0x0 November 30, 2007 393 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description Action for Counter=0 The action to be taken when the counter is zero. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 1:0 ActZero R/W 0x0 394 November 30, 2007 Preliminary Pulse Width Modulator (PWM) Register 19: PWM0 Generator B Control (PWM0GENB), offset 0x064 This register controls the generation of the PWMnB signal based on the load and zero output pulses from the counter, as well as the compare A and compare B pulses from the comparators. When the counter is running in Down mode, only four of these events occur; when running in Up/Down mode, all six occur. These events provide great flexibility in the positioning and duty cycle of the PWM signal that is produced. The PWM0GENB register controls generation of the PWM0B signal. If a zero or load event coincides with a compare A or compare B event, the zero or load action is taken and the compare A or compare B action is ignored. If a compare A event coincides with a compare B event, the compare B action is taken and the compare A action is ignored. PWM0 Generator B Control (PWM0GENB) Base 0x4002.8000 Offset 0x064 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:12 reserved RO 0x00 Action for Comparator B Down The action to be taken when the counter matches comparator B while counting down. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 11:10 ActCmpBD R/W 0x0 November 30, 2007 395 Preliminary LM3S6110 Microcontroller Bit/Field Name Type Reset Description Action for Comparator B Up The action to be taken when the counter matches comparator B while counting up. Occurs only when the Mode bit in the PWMnCTL register is set to 1. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 9:8 ActCmpBU R/W 0x0 Action for Comparator A Down The action to be taken when the counter matches comparator A while counting down. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 7:6 ActCmpAD R/W 0x0 Action for Comparator A Up The action to be taken when the counter matches comparator A while counting up. Occurs only when the Mode bit in the PWMnCTL register is set to 1. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 5:4 ActCmpAU R/W 0x0 Action for Counter=Load The action to be taken when the counter matches the load value. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 3:2 ActLoad R/W 0x0 396 November 30, 2007 Preliminary Pulse Width Modulator (PWM) Bit/Field Name Type Reset Description Action for Counter=0 The action to be taken when the counter is 0. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 1:0 ActZero R/W 0x0 November 30, 2007 397 Preliminary LM3S6110 Microcontroller Register 20: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 The PWM0DBCTL register controls the dead-band generator, which produces the PWM0 and PWM1 signals based on the PWM0A and PWM0B signals. When disabled, the PWM0A signal passes through to the PWM0 signal and the PWM0B signal passes through to the PWM1 signal. When enabled and inverting the resulting waveform, the PWM0B signal is ignored; the PWM0 signal is generated by delaying the rising edge(s) of the PWM0A signal by the value in the PWM0DBRISE register (see page 399), and the PWM1 signal is generated by delaying the falling edge(s) of the PWM0A signal by the value in the PWM0DBFALL register (see page 400). PWM0 Dead-Band Control (PWM0DBCTL) Base 0x4002.8000 Offset 0x068 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Enable Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Dead-Band Generator Enable When set, the dead-band generator inserts dead bands into the output signals; when clear, it simply passes the PWM signals through. 0 Enable R/W 0 398 November 30, 2007 Preliminary Pulse Width Modulator (PWM) Register 21: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C The PWM0DBRISE register contains the number of clock ticks to delay the rising edge of the PWM0A signal when generating the PWM0 signal. If the dead-band generator is disabled through the PWMnDBCTL register, the PWM0DBRISE register is ignored. If the value of this register is larger than the width of a High pulse on the input PWM signal, the rising-edge delay consumes the entire High time of the signal, resulting in no High time on the output. Care must be taken to ensure that the input High time always exceeds the rising-edge delay. PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE) Base 0x4002.8000 Offset 0x06C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RiseDelay Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:12 reserved RO 0x00 Dead-Band Rise Delay The number of clock ticks to delay the rising edge. 11:0 RiseDelay R/W 0 November 30, 2007 399 Preliminary LM3S6110 Microcontroller Register 22: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 The PWM0DBFALL register contains the number of clock ticks to delay the falling edge of the PWM0A signal when generating the PWM1 signal. If the dead-band generator is disabled, this register is ignored. If the value of this register is larger than the width of a Low pulse on the input PWM signal, the falling-edge delay consumes the entire Low time of the signal, resulting in no Low time on the output. Care must be taken to ensure that the input Low time always exceeds the falling-edge delay. PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL) Base 0x4002.8000 Offset 0x070 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FallDelay Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:12 reserved RO 0x00 Dead-Band Fall Delay The number of clock ticks to delay the falling edge. 11:0 FallDelay R/W 0x00 400 November 30, 2007 Preliminary Pulse Width Modulator (PWM) 16 Pin Diagram Figure 16-1 on page 401 shows the pin diagram and pin-to-signal-name mapping. Figure 16-1. Pin Connection Diagram LM3S6110 38 39 40 41 42 43 44 45 46 47 48 49 50 1 75 26 100 2 27 5 6 3 4 7 8 11 9 10 99 28 98 29 97 30 96 31 95 32 94 33 93 34 92 35 91 36 90 73 72 74 71 69 68 70 67 65 66 12 13 14 17 18 15 16 19 20 23 21 22 24 25 64 37 89 88 87 86 85 84 83 82 81 80 79 78 77 76 63 61 60 62 59 57 56 58 55 53 54 52 51 NC NC VDDA GNDA NC NC LDO VDD GND PD0/PWM0 PD1/PWM1 PD2 PD3 VDD25 GND XTALPPHY XTALNPHY NC NC VDD GND PC7/C2- PC6/C2+ PC5/C1+ PC4 PA0/U0Rx PA1/U0Tx PA2/SSI0Clk PA3/SSI0Fss PA4/SSI0Rx PA5/SSI0Tx VDD GND PA6/CCP1 NC VCCPHY RXIN VDD25 GND RXIP GNDPHY GNDPHY TXOP VDD GND TXON PF0 OSC0 OSC1 NC NC NC NC GND VDD VDD GND MDIO PF3/LED0 PF2/LED1 PF1 VDD25 GND RST CMOD0 PB0/CCP0 PB1/CCP2 VDD GND PB2 PB3/Fault NC NC NC NC CMOD1 PC3/TDO/SWO PC2/TDI PC1/TMS/SWDIO PC0/TCK/SWCLK VDD GND VCCPHY VCCPHY GNDPHY GNDPHY GND VDD25 PB7/TRST PB6/C0+ PB5/C1- PB4/C0- VDD GND PD4/CCP3 PD5 GNDA VDDA PD6 PD7/C0o November 30, 2007 401 Preliminary LM3S6110 Microcontroller 17 Signal Tables The following tables list the signals available for each pin. Functionality is enabled by software with the GPIOAFSEL register. Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7 and PC[3:0]) which default to the JTAG functionality. Table 17-1 on page 402 shows the pin-to-signal-name mapping, including functional characteristics of the signals. Table 17-2 on page 406 lists the signals in alphabetical order by signal name. Table 17-3 on page 409 groups the signals by functionality, except for GPIOs. Table 17-4 on page 412 lists the GPIO pins and their alternate functionality. Table 17-1. Signals by Pin Number Pin Number Pin Name Pin Type Buffer Type Description 1 NC - - No connect 2 NC - - No connect The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. 3 VDDA - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. 4 GNDA - Power 5 NC - - No connect 6 NC - - No connect Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 μF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). 7 LDO - Power 8 VDD - Power Positive supply for I/O and some logic. 9 GND - Power Ground reference for logic and I/O pins. 10 PD0 I/O TTL GPIO port D bit 0 PWM0 O TTL PWM 0 11 PD1 I/O TTL GPIO port D bit 1 PWM1 O TTL PWM 1 12 PD2 I/O TTL GPIO port D bit 2 13 PD3 I/O TTL GPIO port D bit 3 Positive supply for most of the logic function, including the processor core and most peripherals. 14 VDD25 - Power 15 GND - Power Ground reference for logic and I/O pins. 16 XTALPPHY O TTL XTALP of the Ethernet PHY 17 XTALNPHY I TTL XTALN of the Ethernet PHY 402 November 30, 2007 Preliminary Signal Tables Pin Number Pin Name Pin Type Buffer Type Description 18 NC - - No connect 19 NC - - No connect 20 VDD - Power Positive supply for I/O and some logic. 21 GND - Power Ground reference for logic and I/O pins. 22 PC7 I/O TTL GPIO port C bit 7 C2- I Analog Analog comparator 2 negative input 23 PC6 I/O TTL GPIO port C bit 6 C2+ I Analog Analog comparator positive input 24 PC5 I/O TTL GPIO port C bit 5 C1+ I Analog Analog comparator positive input 25 PC4 I/O TTL GPIO port C bit 4 26 PA0 I/O TTL GPIO port A bit 0 UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Rx I TTL 27 PA1 I/O TTL GPIO port A bit 1 UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U0Tx O TTL 28 PA2 I/O TTL GPIO port A bit 2 SSI0Clk I/O TTL SSI module 0 clock 29 PA3 I/O TTL GPIO port A bit 3 SSI0Fss I/O TTL SSI module 0 frame 30 PA4 I/O TTL GPIO port A bit 4 SSI0Rx I TTL SSI module 0 receive 31 PA5 I/O TTL GPIO port A bit 5 SSI0Tx O TTL SSI module 0 transmit 32 VDD - Power Positive supply for I/O and some logic. 33 GND - Power Ground reference for logic and I/O pins. 34 PA6 I/O TTL GPIO port A bit 6 CCP1 I/O TTL Capture/Compare/PWM 1 35 NC - - No connect 36 VCCPHY I TTL VCC of the Ethernet PHY 37 RXIN I Analog RXIN of the Ethernet PHY Positive supply for most of the logic function, including the processor core and most peripherals. 38 VDD25 - Power 39 GND - Power Ground reference for logic and I/O pins. 40 RXIP I Analog RXIP of the Ethernet PHY 41 GNDPHY I TTL GND of the Ethernet PHY 42 GNDPHY I TTL GND of the Ethernet PHY 43 TXOP O Analog TXOP of the Ethernet PHY 44 VDD - Power Positive supply for I/O and some logic. 45 GND - Power Ground reference for logic and I/O pins. 46 TXON O Analog TXON of the Ethernet PHY 47 PF0 I/O TTL GPIO port F bit 0 November 30, 2007 403 Preliminary LM3S6110 Microcontroller Pin Number Pin Name Pin Type Buffer Type Description Main oscillator crystal input or an external clock reference input. 48 OSC0 I Analog 49 OSC1 I Analog Main oscillator crystal output. 50 NC - - No connect 51 NC - - No connect 52 NC - - No connect 53 NC - - No connect 54 GND - Power Ground reference for logic and I/O pins. 55 VDD - Power Positive supply for I/O and some logic. 56 VDD - Power Positive supply for I/O and some logic. 57 GND - Power Ground reference for logic and I/O pins. 58 MDIO I/O TTL MDIO of the Ethernet PHY 59 PF3 I/O TTL GPIO port F bit 3 LED0 O TTL MII LED 0 60 PF2 I/O TTL GPIO port F bit 2 LED1 O TTL MII LED 1 61 PF1 I/O TTL GPIO port F bit 1 Positive supply for most of the logic function, including the processor core and most peripherals. 62 VDD25 - Power 63 GND - Power Ground reference for logic and I/O pins. 64 RST I TTL System reset input. CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. 65 CMOD0 I/O TTL 66 PB0 I/O TTL GPIO port B bit 0 CCP0 I/O TTL Capture/Compare/PWM 0 67 PB1 I/O TTL GPIO port B bit 1 CCP2 I/O TTL Capture/Compare/PWM 2 68 VDD - Power Positive supply for I/O and some logic. 69 GND - Power Ground reference for logic and I/O pins. 70 PB2 I/O TTL GPIO port B bit 2 71 PB3 I/O TTL GPIO port B bit 3 Fault I TTL PWM Fault 72 NC - - No connect 73 NC - - No connect 74 NC - - No connect 75 NC - - No connect CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. 76 CMOD1 I/O TTL 77 PC3 I/O TTL GPIO port C bit 3 TDO O TTL JTAG TDO and SWO SWO O TTL JTAG TDO and SWO 78 PC2 I/O TTL GPIO port C bit 2 TDI I TTL JTAG TDI 404 November 30, 2007 Preliminary Signal Tables Pin Number Pin Name Pin Type Buffer Type Description 79 PC1 I/O TTL GPIO port C bit 1 TMS I/O TTL JTAG TMS and SWDIO SWDIO I/O TTL JTAG TMS and SWDIO 80 PC0 I/O TTL GPIO port C bit 0 TCK I TTL JTAG/SWD CLK SWCLK I TTL JTAG/SWD CLK 81 VDD - Power Positive supply for I/O and some logic. 82 GND - Power Ground reference for logic and I/O pins. 83 VCCPHY I TTL VCC of the Ethernet PHY 84 VCCPHY I TTL VCC of the Ethernet PHY 85 GNDPHY I TTL GND of the Ethernet PHY 86 GNDPHY I TTL GND of the Ethernet PHY 87 GND - Power Ground reference for logic and I/O pins. Positive supply for most of the logic function, including the processor core and most peripherals. 88 VDD25 - Power 89 PB7 I/O TTL GPIO port B bit 7 TRST I TTL JTAG TRSTn 90 PB6 I/O TTL GPIO port B bit 6 C0+ I Analog Analog comparator 0 positive input 91 PB5 I/O TTL GPIO port B bit 5 C1- I Analog Analog comparator 1 negative input 92 PB4 I/O TTL GPIO port B bit 4 C0- I Analog Analog comparator 0 negative input 93 VDD - Power Positive supply for I/O and some logic. 94 GND - Power Ground reference for logic and I/O pins. 95 PD4 I/O TTL GPIO port D bit 4 CCP3 I/O TTL Capture/Compare/PWM 3 96 PD5 I/O TTL GPIO port D bit 5 The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. 97 GNDA - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. 98 VDDA - Power 99 PD6 I/O TTL GPIO port D bit 6 100 PD7 I/O TTL GPIO port D bit 7 C0o O TTL Analog comparator 0 output November 30, 2007 405 Preliminary LM3S6110 Microcontroller Table 17-2. Signals by Signal Name Pin Name Pin Number Pin Type Buffer Type Description C0+ 90 I Analog Analog comparator 0 positive input C0- 92 I Analog Analog comparator 0 negative input C0o 100 O TTL Analog comparator 0 output C1+ 24 I Analog Analog comparator positive input C1- 91 I Analog Analog comparator 1 negative input C2+ 23 I Analog Analog comparator positive input C2- 22 I Analog Analog comparator 2 negative input CCP0 66 I/O TTL Capture/Compare/PWM 0 CCP1 34 I/O TTL Capture/Compare/PWM 1 CCP2 67 I/O TTL Capture/Compare/PWM 2 CCP3 95 I/O TTL Capture/Compare/PWM 3 CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. CMOD0 65 I/O TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. CMOD1 76 I/O TTL Fault 71 I TTL PWM Fault GND 9 - Power Ground reference for logic and I/O pins. GND 15 - Power Ground reference for logic and I/O pins. GND 21 - Power Ground reference for logic and I/O pins. GND 33 - Power Ground reference for logic and I/O pins. GND 39 - Power Ground reference for logic and I/O pins. GND 45 - Power Ground reference for logic and I/O pins. GND 54 - Power Ground reference for logic and I/O pins. GND 57 - Power Ground reference for logic and I/O pins. GND 63 - Power Ground reference for logic and I/O pins. GND 69 - Power Ground reference for logic and I/O pins. GND 82 - Power Ground reference for logic and I/O pins. GND 87 - Power Ground reference for logic and I/O pins. GND 94 - Power Ground reference for logic and I/O pins. The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. GNDA 4 - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. GNDA 97 - Power GNDPHY 41 I TTL GND of the Ethernet PHY GNDPHY 42 I TTL GND of the Ethernet PHY GNDPHY 85 I TTL GND of the Ethernet PHY GNDPHY 86 I TTL GND of the Ethernet PHY 406 November 30, 2007 Preliminary Signal Tables Pin Name Pin Number Pin Type Buffer Type Description Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 μF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). LDO 7 - Power LED0 59 O TTL MII LED 0 LED1 60 O TTL MII LED 1 MDIO 58 I/O TTL MDIO of the Ethernet PHY NC 1 - - No connect NC 2 - - No connect NC 5 - - No connect NC 6 - - No connect NC 18 - - No connect NC 19 - - No connect NC 35 - - No connect NC 50 - - No connect NC 51 - - No connect NC 52 - - No connect NC 53 - - No connect NC 72 - - No connect NC 73 - - No connect NC 74 - - No connect NC 75 - - No connect Main oscillator crystal input or an external clock reference input. OSC0 48 I Analog OSC1 49 I Analog Main oscillator crystal output. PA0 26 I/O TTL GPIO port A bit 0 PA1 27 I/O TTL GPIO port A bit 1 PA2 28 I/O TTL GPIO port A bit 2 PA3 29 I/O TTL GPIO port A bit 3 PA4 30 I/O TTL GPIO port A bit 4 PA5 31 I/O TTL GPIO port A bit 5 PA6 34 I/O TTL GPIO port A bit 6 PB0 66 I/O TTL GPIO port B bit 0 PB1 67 I/O TTL GPIO port B bit 1 PB2 70 I/O TTL GPIO port B bit 2 PB3 71 I/O TTL GPIO port B bit 3 PB4 92 I/O TTL GPIO port B bit 4 PB5 91 I/O TTL GPIO port B bit 5 PB6 90 I/O TTL GPIO port B bit 6 PB7 89 I/O TTL GPIO port B bit 7 PC0 80 I/O TTL GPIO port C bit 0 PC1 79 I/O TTL GPIO port C bit 1 November 30, 2007 407 Preliminary LM3S6110 Microcontroller Pin Name Pin Number Pin Type Buffer Type Description PC2 78 I/O TTL GPIO port C bit 2 PC3 77 I/O TTL GPIO port C bit 3 PC4 25 I/O TTL GPIO port C bit 4 PC5 24 I/O TTL GPIO port C bit 5 PC6 23 I/O TTL GPIO port C bit 6 PC7 22 I/O TTL GPIO port C bit 7 PD0 10 I/O TTL GPIO port D bit 0 PD1 11 I/O TTL GPIO port D bit 1 PD2 12 I/O TTL GPIO port D bit 2 PD3 13 I/O TTL GPIO port D bit 3 PD4 95 I/O TTL GPIO port D bit 4 PD5 96 I/O TTL GPIO port D bit 5 PD6 99 I/O TTL GPIO port D bit 6 PD7 100 I/O TTL GPIO port D bit 7 PF0 47 I/O TTL GPIO port F bit 0 PF1 61 I/O TTL GPIO port F bit 1 PF2 60 I/O TTL GPIO port F bit 2 PF3 59 I/O TTL GPIO port F bit 3 PWM0 10 O TTL PWM 0 PWM1 11 O TTL PWM 1 RST 64 I TTL System reset input. RXIN 37 I Analog RXIN of the Ethernet PHY RXIP 40 I Analog RXIP of the Ethernet PHY SSI0Clk 28 I/O TTL SSI module 0 clock SSI0Fss 29 I/O TTL SSI module 0 frame SSI0Rx 30 I TTL SSI module 0 receive SSI0Tx 31 O TTL SSI module 0 transmit SWCLK 80 I TTL JTAG/SWD CLK SWDIO 79 I/O TTL JTAG TMS and SWDIO SWO 77 O TTL JTAG TDO and SWO TCK 80 I TTL JTAG/SWD CLK TDI 78 I TTL JTAG TDI TDO 77 O TTL JTAG TDO and SWO TMS 79 I/O TTL JTAG TMS and SWDIO TRST 89 I TTL JTAG TRSTn TXON 46 O Analog TXON of the Ethernet PHY TXOP 43 O Analog TXOP of the Ethernet PHY UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Rx 26 I TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U0Tx 27 O TTL VCCPHY 36 I TTL VCC of the Ethernet PHY VCCPHY 83 I TTL VCC of the Ethernet PHY 408 November 30, 2007 Preliminary Signal Tables Pin Name Pin Number Pin Type Buffer Type Description VCCPHY 84 I TTL VCC of the Ethernet PHY VDD 8 - Power Positive supply for I/O and some logic. VDD 20 - Power Positive supply for I/O and some logic. VDD 32 - Power Positive supply for I/O and some logic. VDD 44 - Power Positive supply for I/O and some logic. VDD 55 - Power Positive supply for I/O and some logic. VDD 56 - Power Positive supply for I/O and some logic. VDD 68 - Power Positive supply for I/O and some logic. VDD 81 - Power Positive supply for I/O and some logic. VDD 93 - Power Positive supply for I/O and some logic. Positive supply for most of the logic function, including the processor core and most peripherals. VDD25 14 - Power Positive supply for most of the logic function, including the processor core and most peripherals. VDD25 38 - Power Positive supply for most of the logic function, including the processor core and most peripherals. VDD25 62 - Power Positive supply for most of the logic function, including the processor core and most peripherals. VDD25 88 - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA 3 - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA 98 - Power XTALNPHY 17 I TTL XTALN of the Ethernet PHY XTALPPHY 16 O TTL XTALP of the Ethernet PHY Table 17-3. Signals by Function, Except for GPIO Buffer Description Type Pin Pin Type Number Function Pin Name Analog C0+ 90 I Analog Analog comparator 0 positive input Comparators C0- 92 I Analog Analog comparator 0 negative input C0o 100 O TTL Analog comparator 0 output C1+ 24 I Analog Analog comparator positive input C1- 91 I Analog Analog comparator 1 negative input C2+ 23 I Analog Analog comparator positive input C2- 22 I Analog Analog comparator 2 negative input November 30, 2007 409 Preliminary LM3S6110 Microcontroller Buffer Description Type Pin Pin Type Number Function Pin Name Ethernet PHY GNDPHY 41 I TTL GND of the Ethernet PHY GNDPHY 42 I TTL GND of the Ethernet PHY GNDPHY 85 I TTL GND of the Ethernet PHY GNDPHY 86 I TTL GND of the Ethernet PHY LED0 59 O TTL MII LED 0 LED1 60 O TTL MII LED 1 MDIO 58 I/O TTL MDIO of the Ethernet PHY RXIN 37 I Analog RXIN of the Ethernet PHY RXIP 40 I Analog RXIP of the Ethernet PHY TXON 46 O Analog TXON of the Ethernet PHY TXOP 43 O Analog TXOP of the Ethernet PHY VCCPHY 36 I TTL VCC of the Ethernet PHY VCCPHY 83 I TTL VCC of the Ethernet PHY VCCPHY 84 I TTL VCC of the Ethernet PHY XTALNPHY 17 I TTL XTALN of the Ethernet PHY XTALPPHY 16 O TTL XTALP of the Ethernet PHY General-Purpose CCP0 66 I/O TTL Capture/Compare/PWM 0 Timers CCP1 34 I/O TTL Capture/Compare/PWM 1 CCP2 67 I/O TTL Capture/Compare/PWM 2 CCP3 95 I/O TTL Capture/Compare/PWM 3 JTAG/SWD/SWO SWCLK 80 I TTL JTAG/SWD CLK SWDIO 79 I/O TTL JTAG TMS and SWDIO SWO 77 O TTL JTAG TDO and SWO TCK 80 I TTL JTAG/SWD CLK TDI 78 I TTL JTAG TDI TDO 77 O TTL JTAG TDO and SWO TMS 79 I/O TTL JTAG TMS and SWDIO PWM Fault 71 I TTL PWM Fault PWM0 10 O TTL PWM 0 PWM1 11 O TTL PWM 1 410 November 30, 2007 Preliminary Signal Tables Buffer Description Type Pin Pin Type Number Function Pin Name Power GND 9 - Power Ground reference for logic and I/O pins. GND 15 - Power Ground reference for logic and I/O pins. GND 21 - Power Ground reference for logic and I/O pins. GND 33 - Power Ground reference for logic and I/O pins. GND 39 - Power Ground reference for logic and I/O pins. GND 45 - Power Ground reference for logic and I/O pins. GND 54 - Power Ground reference for logic and I/O pins. GND 57 - Power Ground reference for logic and I/O pins. GND 63 - Power Ground reference for logic and I/O pins. GND 69 - Power Ground reference for logic and I/O pins. GND 82 - Power Ground reference for logic and I/O pins. GND 87 - Power Ground reference for logic and I/O pins. GND 94 - Power Ground reference for logic and I/O pins. The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. GNDA 4 - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. GNDA 97 - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 μF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). LDO 7 - Power VDD 8 - Power Positive supply for I/O and some logic. VDD 20 - Power Positive supply for I/O and some logic. VDD 32 - Power Positive supply for I/O and some logic. VDD 44 - Power Positive supply for I/O and some logic. VDD 55 - Power Positive supply for I/O and some logic. VDD 56 - Power Positive supply for I/O and some logic. VDD 68 - Power Positive supply for I/O and some logic. VDD 81 - Power Positive supply for I/O and some logic. VDD 93 - Power Positive supply for I/O and some logic. Positive supply for most of the logic function, including the processor core and most peripherals. VDD25 14 - Power Positive supply for most of the logic function, including the processor core and most peripherals. VDD25 38 - Power Positive supply for most of the logic function, including the processor core and most peripherals. VDD25 62 - Power Positive supply for most of the logic function, including the processor core and most peripherals. VDD25 88 - Power VDDA 3 - Power November 30, 2007 411 Preliminary LM3S6110 Microcontroller Buffer Description Type Pin Pin Type Number Function Pin Name The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA 98 - Power SSI SSI0Clk 28 I/O TTL SSI module 0 clock SSI0Fss 29 I/O TTL SSI module 0 frame SSI0Rx 30 I TTL SSI module 0 receive SSI0Tx 31 O TTL SSI module 0 transmit CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. System Control & CMOD0 65 I/O TTL Clocks CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. CMOD1 76 I/O TTL Main oscillator crystal input or an external clock reference input. OSC0 48 I Analog OSC1 49 I Analog Main oscillator crystal output. RST 64 I TTL System reset input. TRST 89 I TTL JTAG TRSTn UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. UART U0Rx 26 I TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U0Tx 27 O TTL Table 17-4. GPIO Pins and Alternate Functions GPIO Pin Pin Number Multiplexed Function Multiplexed Function PA0 26 U0Rx PA1 27 U0Tx PA2 28 SSI0Clk PA3 29 SSI0Fss PA4 30 SSI0Rx PA5 31 SSI0Tx PA6 34 CCP1 PB0 66 CCP0 PB1 67 CCP2 PB2 70 PB3 71 Fault PB4 92 C0- PB5 91 C1- PB6 90 C0+ PB7 89 TRST PC0 80 TCK SWCLK 412 November 30, 2007 Preliminary Signal Tables GPIO Pin Pin Number Multiplexed Function Multiplexed Function PC1 79 TMS SWDIO PC2 78 TDI PC3 77 TDO SWO PC4 25 PC5 24 C1+ PC6 23 C2+ PC7 22 C2- PD0 10 PWM0 PD1 11 PWM1 PD2 12 PD3 13 PD4 95 CCP3 PD5 96 PD6 99 PD7 100 C0o PF0 47 PF1 61 PF2 60 LED1 PF3 59 LED0 November 30, 2007 413 Preliminary LM3S6110 Microcontroller 18 Operating Characteristics Table 18-1. Temperature Characteristics Characteristic Symbol Value Unit Operating temperature rangea TA -40 to +85 °C a. Maximum storage temperature is 150°C. Table 18-2. Thermal Characteristics Characteristic Symbol Value Unit Thermal resistance (junction to ambient)a ΘJA 55.3 °C/W Average junction temperatureb TJ TA + (PAVG • ΘJA) °C a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator. b. Power dissipation is a function of temperature. 414 November 30, 2007 Preliminary Operating Characteristics 19 Electrical Characteristics 19.1 DC Characteristics 19.1.1 Maximum Ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note: The device is not guaranteed to operate properly at the maximum ratings. Table 19-1. Maximum Ratings Characteristic Symbol Value Unit a Min Max I/O supply voltage (VDD) VDD 0 4 V Core supply voltage (VDD25) VDD25 0 4 V Analog supply voltage (VDDA) VDDA 0 4 V Ethernet PHY supply voltage (VCCPHY) VCCPHY 0 4 V Input voltage VIN -0.3 5.5 V Maximum current per output pins I - 25 mA a. Voltages are measured with respect to GND. Important: This device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either GND or VDD). 19.1.2 Recommended DC Operating Conditions Table 19-2. Recommended DC Operating Conditions Parameter Parameter Name Min Nom Max Unit VDD I/O supply voltage 3.0 3.3 3.6 V VDD25 Core supply voltage 2.25 2.5 2.75 V VDDA Analog supply voltage 3.0 3.3 3.6 V VCCPHY Ethernet PHY supply voltage 3.0 3.3 3.6 V VIH High-level input voltage 2.0 - 5.0 V VIL Low-level input voltage -0.3 - 1.3 V VSIH High-level input voltage for Schmitt trigger inputs 0.8 * VDD - VDD V VSIL Low-level input voltage for Schmitt trigger inputs 0 - 0.2 * VDD V VOH High-level output voltage 2.4 - - V VOL Low-level output voltage - - 0.4 V IOH High-level source current, VOH=2.4 V 2-mA Drive 2.0 - - mA 4-mA Drive 4.0 - - mA 8-mA Drive 8.0 - - mA November 30, 2007 415 Preliminary LM3S6110 Microcontroller Parameter Parameter Name Min Nom Max Unit IOL Low-level sink current, VOL=0.4 V 2-mA Drive 2.0 - - mA 4-mA Drive 4.0 - - mA 8-mA Drive 8.0 - - mA 19.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics Table 19-3. LDO Regulator Characteristics Parameter Parameter Name Min Nom Max Unit VLDOOUT Programmable internal (logic) power supply output value 2.25 2.5 2.75 V Output voltage accuracy - 2% - % tPON Power-on time - - 100 μs tON Time on - - 200 μs tOFF Time off - - 100 μs VSTEP Step programming incremental voltage - 50 - mV CLDO External filter capacitor size for internal power supply 1.0 - 3.0 μF 19.1.4 Power Specifications The power measurements specified in the tables that follow are run on the core processor using SRAM with the following specifications (except as noted): ■ VDD = 3.3 V ■ VDD25 = 2.50 V ■ VDDA = 3.3 V ■ VDDPHY = 3.3 V ■ Temperature = 25°C ■ Clock Source (MOSC) =3.579545 MHz Crystal Oscillator ■ Main oscillator (MOSC) = enabled ■ Internal oscillator (IOSC) = disabled 416 November 30, 2007 Preliminary Electrical Characteristics Table 19-4. Detailed Power Specifications 3.3 V VDD, VDDA, 2.5 V VDD25 Unit VDDPHY Parameter Parameter Name Conditions Nom Max Nom Max VDD25 = 2.50 V 48 pendinga 64 pendinga mA Code= while(1){} executed in Flash Peripherals = All ON System Clock = 25 MHz (with PLL) Run mode 1 (Flash loop) IDD_RUN VDD25 = 2.50 V 5 pendinga 33 pendinga mA Code= while(1){} executed in Flash Peripherals = All OFF System Clock = 25 MHz (with PLL) Run mode 2 (Flash loop) VDD25 = 2.50 V 48 pendinga 56 pendinga mA Code= while(1){} executed in SRAM Peripherals = All ON System Clock = 25 MHz (with PLL) Run mode 1 (SRAM loop) VDD25 = 2.50 V 5 pendinga 26 pendinga mA Code= while(1){} executed in SRAM Peripherals = All OFF System Clock = 25 MHz (with PLL) Run mode 2 (SRAM loop) VDD25 = 2.50 V 5 pendinga 12 pendinga mA Peripherals = All OFF System Clock = 25 MHz (with PLL) IDD_SLEEP Sleep mode LDO = 2.25 V 4.6 pendinga 0.21 pendinga mA Peripherals = All OFF System Clock = IOSC30KHZ/64 IDD_DEEPSLEEP Deep-Sleep mode a. Pending characterization completion. 19.1.5 Flash Memory Characteristics Table 19-5. Flash Memory Characteristics Parameter Parameter Name Min Nom Max Unit PECYC Number of guaranteed program/erase cycles before failurea 10,000 100,000 - cycles TRET Data retention at average operating temperature of 85˚C 10 - - years TPROG Word program time 20 - - μs TERASE Page erase time 20 - - ms TME Mass erase time 200 - - ms a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1. November 30, 2007 417 Preliminary LM3S6110 Microcontroller 19.2 AC Characteristics 19.2.1 Load Conditions Unless otherwise specified, the following conditions are true for all timing measurements. Timing measurements are for 4-mA drive strength. Figure 19-1. Load Conditions CL = 50 pF GND pin 19.2.2 Clocks Table 19-6. Phase Locked Loop (PLL) Characteristics Parameter Parameter Name Min Nom Max Unit fref_crystal Crystal referencea 3.579545 - 8.192 MHz fref_ext External clock referencea 3.579545 - 8.192 MHz fpll PLL frequencyb - 400 - MHz TREADY PLL lock time - - 0.5 ms a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration (RCC) register. b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register. Table 19-7. Clock Characteristics Parameter Parameter Name Min Nom Max Unit fIOSC Internal 12 MHz oscillator frequency 8.4 12 15.6 MHz fIOSC30KHZ Internal 30 KHz oscillator frequency 21 30 39 KHz fMOSC Main oscillator frequency 1 - 8 MHz tMOSC_per Main oscillator period 125 - 1000 ns fref_crystal_bypass Crystal reference using the main oscillator (PLL in BYPASS mode) 1 - 8 MHz fref_ext_bypass External clock reference (PLL in BYPASS mode) 0 - 25 MHz fsystem_clock System clock 0 - 25 MHz Table 19-8. Crystal Characteristics Parameter Name Value Units Frequency 8 6 4 3.5 MHz Frequency tolerance ±50 ±50 ±50 ±50 ppm Aging ±5 ±5 ±5 ±5 ppm/yr Oscillation mode Parallel Parallel Parallel Parallel Temperature stability (0 - 85 °C) ±25 ±25 ±25 ±25 ppm Motional capacitance (typ) 27.8 37.0 55.6 63.5 pF 418 November 30, 2007 Preliminary Electrical Characteristics Parameter Name Value Units Motional inductance (typ) 14.3 19.1 28.6 32.7 mH Equivalent series resistance (max) 120 160 200 220 Ω Shunt capacitance (max) 10 10 10 10 pF Load capacitance (typ) 16 16 16 16 pF Drive level (typ) 100 100 100 100 μW 19.2.3 Analog Comparator Table 19-9. Analog Comparator Characteristics Parameter Parameter Name Min Nom Max Unit VOS Input offset voltage - ±10 ±25 mV VCM Input common mode voltage range 0 - VDD-1.5 V CMRR Common mode rejection ratio 50 - - dB TRT Response time - - 1 μs TMC Comparator mode change to Output Valid - - 10 μs Table 19-10. Analog Comparator Voltage Reference Characteristics Parameter Parameter Name Min Nom Max Unit RHR Resolution high range - VDD/32 - LSB RLR Resolution low range - VDD/24 - LSB AHR Absolute accuracy high range - - ±1/2 LSB ALR Absolute accuracy low range - - ±1/4 LSB 19.2.4 Ethernet Controller Table 19-11. 100BASE-TX Transmitter Characteristicsa Parameter Name Min Nom Max Unit Peak output amplitude 950 - 1050 mVpk Output amplitude symmetry 0.98 - 1.02 mVpk Output overshoot - - 5 % Rise/Fall time 3 - 5 ns Rise/Fall time imbalance - - 500 ps Duty cycle distortion - - - ps Jitter - - 1.4 ns a. Measured at the line side of the transformer. Table 19-12. 100BASE-TX Transmitter Characteristics (informative)a Parameter Name Min Nom Max Unit Return loss 16 - - dB Open-circuit inductance 350 - - μs a. The specifications in this table are included for information only. They are mainly a function of the external transformer and termination resistors used for measurements. November 30, 2007 419 Preliminary LM3S6110 Microcontroller Table 19-13. 100BASE-TX Receiver Characteristics Parameter Name Min Nom Max Unit Signal detect assertion threshold 600 700 mVppd Signal detect de-assertion threshold 350 425 - mVppd Differential input resistance 20 - - kΩ Jitter tolerance (pk-pk) 4 - - ns Baseline wander tracking -75 - +75 % Signal detect assertion time - - 1000 μs Signal detect de-assertion time - - 4 μs Table 19-14. 10BASE-T Transmitter Characteristicsa Parameter Name Min Nom Max Unit Peak differential output signal 2.2 - 2.8 V Harmonic content 27 - - dB Link pulse width - 100 - ns 300 - ns 350 Start-of-idle pulse width - a. The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using the procedures found in Clause 14 of IEEE 802.3. Table 19-15. 10BASE-T Transmitter Characteristics (informative)a Parameter Name Min Nom Max Unit Output return loss 15 - - dB Output impedance balance 29-17log(f/10) - - dB Peak common-mode output voltage - - 50 mV Common-mode rejection - - 100 mV Common-mode rejection jitter - - 1 ns a. The specifications in this table are included for information only. They are mainly a function of the external transformer and termination resistors used for measurements. Table 19-16. 10BASE-T Receiver Characteristics Parameter Name Min Nom Max Unit DLL phase acquisition time - 10 - BT Jitter tolerance (pk-pk) 30 - - ns Input squelched threshold 500 600 700 mVppd Input unsquelched threshold 275 350 425 mVppd Differential input resistance - 20 - kΩ Bit error ratio - 10-10 - - Common-mode rejection 25 - - V Table 19-17. Isolation Transformersa Name Value Condition Turns ratio 1 CT : 1 CT +/- 5% Open-circuit inductance 350 uH (min) @ 10 mV, 10 kHz 420 November 30, 2007 Preliminary Electrical Characteristics Name Value Condition Leakage inductance 0.40 uH (max) @ 1 MHz (min) Inter-winding capacitance 25 pF (max) DC resistance 0.9 Ohm (max) Insertion loss 0.4 dB (typ) 0-65 MHz HIPOT 1500 Vrms a. Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common-mode chokes are recommended for exceeding FCC requirements. This table gives the recommended line transformer characteristics. Note: The 100Base-TX amplitude specifications assume a transformer loss of 0.4 dB. For the transmit line transformer with higher insertion losses, up to 1.2 dB of insertion loss can be compensated by selecting the appropriate setting in the Transmit Amplitude Selection (TXO) bits in the MR19 register. Table 19-18. Ethernet Reference Crystala Name Value Condition Frequency 25.00000 MHz Load capacitanceb 4c pF Frequency tolerance ±50 PPM Aging ±2 PPM/yr Temperature stability (0° to 70°) ±5 PPM Oscillation mode Parallel resonance, fundamental mode Parameters at 25° C ±2° C; Drive level = 0.5 mW Drive level (typ) 50-100 μW Shunt capacitance (max) 10 pF Motional capacitance (min) 10 fF Serious resistance (max) 60 Ω Spurious response (max) > 5 dB below main within 500 kHz a. If the internal crystal oscillator is used, select a crystal with the following characteristics. b. Equivalent differential capacitance across XTLP/XTLN. c. If crystal with a larger load is used, external shunt capacitors to ground should be added to make up the equivalent capacitance difference. November 30, 2007 421 Preliminary LM3S6110 Microcontroller Figure 19-2. External XTLP Oscillator Characteristics Tclkper Tr Tclkhi Tclklo Tf Table 19-19. External XTLP Oscillator Characteristics Parameter Name Symbol Min Nom Max Unit XTLN Input Low Voltage XTLNILV - - 0.8 - XTLP Frequencya XTLPf - 25.0 - - XTLP Periodb Tclkper - 40 - - 60 % 60 40 - 40 XTLPDC XTLP Duty Cycle Rise/Fall Time Tr , Tf - - 4.0 ns Absolute Jitter - - 0.1 ns a. IEEE 802.3 frequency tolerance ±50 ppm. b. IEEE 802.3 frequency tolerance ±50 ppm. 19.2.5 Synchronous Serial Interface (SSI) Table 19-20. SSI Characteristics Parameter No. Parameter Parameter Name Min Nom Max Unit S1 tclk_per SSIClk cycle time 2 - 65024 system clocks S2 tclk_high SSIClk high time - 1/2 - t clk_per S3 tclk_low SSIClk low time - 1/2 - t clk_per S4 tclkrf SSIClk rise/fall time - 7.4 26 ns S5 tDMd Data from master valid delay time 0 - 20 ns S6 tDMs Data from master setup time 20 - - ns S7 tDMh Data from master hold time 40 - - ns S8 tDSs Data from slave setup time 20 - - ns S9 tDSh Data from slave hold time 40 - - ns 422 November 30, 2007 Preliminary Electrical Characteristics Figure 19-3. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement SSIClk SSIFss SSITx SSIRx MSB LSB S2 S3 S1 S4 4 to 16 bits Figure 19-4. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer 0 SSIClk SSIFss SSITx SSIRx MSB LSB MSB LSB S2 S3 S1 8-bit control 4 to 16 bits output data November 30, 2007 423 Preliminary LM3S6110 Microcontroller Figure 19-5. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 SSIClk (SPO=1) SSITx (master) SSIRx (slave) LSB SSIClk (SPO=0) S2 S1 S4 SSIFss LSB S3 MSB S5 S6 S7 S8 S9 MSB 19.2.6 JTAG and Boundary Scan Table 19-21. JTAG Characteristics Parameter No. Parameter Parameter Name Min Nom Max Unit J1 fTCK TCK operational clock frequency 0 - 10 MHz J2 tTCK TCK operational clock period 100 - - ns J3 tTCK_LOW TCK clock Low time - tTCK - ns J4 tTCK_HIGH TCK clock High time - tTCK - ns J5 tTCK_R TCK rise time 0 - 10 ns J6 tTCK_F TCK fall time 0 - 10 ns J7 tTMS_SU TMS setup time to TCK rise 20 - - ns J8 tTMS_HLD TMS hold time from TCK rise 20 - - ns J9 tTDI_SU TDI setup time to TCK rise 25 - - ns J10 tTDI_HLD TDI hold time from TCK rise 25 - - ns J11 TCK fall to Data Valid from High-Z 2-mA drive - 23 35 ns t TDO_ZDV 4-mA drive 15 26 ns 8-mA drive 14 25 ns 8-mA drive with slew rate control 18 29 ns J12 TCK fall to Data Valid from Data Valid 2-mA drive - 21 35 ns t TDO_DV 4-mA drive 14 25 ns 8-mA drive 13 24 ns 8-mA drive with slew rate control 18 28 ns 424 November 30, 2007 Preliminary Electrical Characteristics Parameter No. Parameter Parameter Name Min Nom Max Unit J13 TCK fall to High-Z from Data Valid 2-mA drive - 9 11 ns t TDO_DVZ 4-mA drive 7 9 ns 8-mA drive 6 8 ns 8-mA drive with slew rate control 7 9 ns J14 tTRST TRST assertion time 100 - - ns J15 tTRST_SU TRST setup time to TCK rise 10 - - ns Figure 19-6. JTAG Test Clock Input Timing TCK J6 J5 J3 J4 J2 Figure 19-7. JTAG Test Access Port (TAP) Timing TDO Output Valid TCK TDO Output Valid J12 TDO TDI TMS TDI Input Valid TDI Input Valid J13 J9 J10 TMS Input Valid J9 J10 TMS Input Valid J11 J7 J8 J7 J8 Figure 19-8. JTAG TRST Timing TCK J14 J15 TRST 19.2.7 General-Purpose I/O Note: All GPIOs are 5 V-tolerant. November 30, 2007 425 Preliminary LM3S6110 Microcontroller Table 19-22. GPIO Characteristics Parameter Parameter Name Condition Min Nom Max Unit tGPIOR GPIO Rise Time (from 20% to 80% of VDD) 2-mA drive - 17 26 ns 4-mA drive 9 13 ns 8-mA drive 6 9 ns 8-mA drive with slew rate control 10 12 ns tGPIOF GPIO Fall Time (from 80% to 20% of VDD) 2-mA drive - 17 25 ns 4-mA drive 8 12 ns 8-mA drive 6 10 ns 8-mA drive with slew rate control 11 13 ns 19.2.8 Reset Table 19-23. Reset Characteristics Parameter No. Parameter Parameter Name Min Nom Max Unit R1 VTH Reset threshold - 2.0 - V R2 VBTH Brown-Out threshold 2.85 2.9 2.95 V R3 TPOR Power-On Reset timeout - 10 - ms R4 TBOR Brown-Out timeout - 500 - μs R5 TIRPOR Internal reset timeout after POR 6 - 11 ms R6 TIRBOR Internal reset timeout after BORa 0 - 1 μs R7 TIRHWR Internal reset timeout after hardware reset (RST pin) 0 - 1 ms R8 TIRSWR Internal reset timeout after software-initiated system reset a 2.5 - 20 μs R9 TIRWDR Internal reset timeout after watchdog reseta 2.5 - 20 μs R10 TVDDRISE Supply voltage (VDD) rise time (0V-3.3V) - - 100 ms R11 TMIN Minimum RST pulse width 2 - - μs a. 20 * t MOSC_per Figure 19-9. External Reset Timing (RST) RST /Reset (Internal) R11 R7 426 November 30, 2007 Preliminary Electrical Characteristics Figure 19-10. Power-On Reset Timing VDD /POR (Internal) /Reset (Internal) R3 R1 R5 Figure 19-11. Brown-Out Reset Timing VDD /BOR (Internal) /Reset (Internal) R2 R4 R6 Figure 19-12. Software Reset Timing R8 SW Reset /Reset (Internal) Figure 19-13. Watchdog Reset Timing WDOG Reset (Internal) /Reset (Internal) R9 November 30, 2007 427 Preliminary LM3S6110 Microcontroller 20 Package Information Figure 20-1. 100-Pin LQFP Package Note: The following notes apply to the package drawing. 1. All dimensions shown in mm. 2. Dimensions shown are nominal with tolerances indicated. 3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane. 428 November 30, 2007 Preliminary Package Information Body +2.00 mm Footprint, 1.4 mm package thickness Symbols Leads 100L A Max. 1.60 A1 0.05 Min./0.15 Max. A2 ±0.05 1.40 D ±0.20 16.00 D1 ±0.05 14.00 E ±0.20 16.00 E1 ±0.05 14.00 L ±0.15/-0.10 0.60 e BASIC 0.50 b ±0.05 0.22 θ === 0˚~7˚ ddd Max. 0.08 ccc Max. 0.08 JEDEC Reference Drawing MS-026 Variation Designator BED November 30, 2007 429 Preliminary LM3S6110 Microcontroller A Serial Flash Loader A.1 Serial Flash Loader The Stellaris® serial flash loader is a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. The serial flash loader uses a simple packet interface to provide synchronous communication with the device. The flash loader runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used. The two serial interfaces that can be used are the UART0 and SSI0 interfaces. For simplicity, both the data format and communication protocol are identical for both serial interfaces. A.2 Interfaces Once communication with the flash loader is established via one of the serial interfaces, that interface is used until the flash loader is reset or new code takes over. For example, once you start communicating using the SSI port, communications with the flash loader via the UART are disabled until the device is reset. A.2.1 UART The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is automatically detected by the flash loader and can be any valid baud rate supported by the host and the device. The auto detection sequence requires that the baud rate should be no more than 1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the same as the hardware limitation for the maximum baud rate for any UART on a Stellaris® device which is calculated as follows: Max Baud Rate = System Clock Frequency / 16 In order to determine the baud rate, the serial flash loader needs to determine the relationship between its own crystal frequency and the baud rate. This is enough information for the flash loader to configure its UART to the same baud rate as the host. This automatic baud-rate detection allows the host to use any valid baud rate that it wants to communicate with the device. The method used to perform this automatic synchronization relies on the host sending the flash loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can use to calculate the ratios needed to program the UART to match the host’s baud rate. After the host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received after at least twice the time required to transfer the two bytes, the host can resend another pattern of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader acknowledges that it has received a synchronization pattern correctly. For example, the time to wait for data back from the flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate of 115200, this time is 2*(20/115200) or 0.35 ms. A.2.2 SSI The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications, with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See “Frame Formats” on page 274 in the SSI chapter for more information on formats for this transfer protocol. Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI clock can run. This allows the SSI clock to be at most 1/12 the crystal frequency of the board running 430 November 30, 2007 Preliminary Serial Flash Loader the flash loader. Since the host device is the master, the SSI on the flash loader device does not need to determine the clock as it is provided directly by the host. A.3 Packet Handling All communications, with the exception of the UART auto-baud, are done via defined packets that are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same format for receiving and sending packets, including the method used to acknowledge successful or unsuccessful reception of a packet. A.3.1 Packet Format All packets sent and received from the device use the following byte-packed format. struct { unsigned char ucSize; unsigned char ucCheckSum; unsigned char Data[]; }; ucSize The first byte received holds the total size of the transfer including the size and checksum bytes. ucChecksum This holds a simple checksum of the bytes in the data buffer only. The algorithm is Data[0]+Data[1]+…+ Data[ucSize-3]. Data This is the raw data intended for the device, which is formatted in some form of command interface. There should be ucSize–2 bytes of data provided in this buffer to or from the device. A.3.2 Sending Packets The actual bytes of the packet can be sent individually or all at once; the only limitation is that commands that cause flash memory access should limit the download sizes to prevent losing bytes during flash programming. This limitation is discussed further in the section that describes the serial flash loader command, COMMAND_SEND_DATA (see “COMMAND_SEND_DATA (0x24)” on page 433). Once the packet has been formatted correctly by the host, it should be sent out over the UART or SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This does not indicate that the actual contents of the command issued in the data portion of the packet were valid, just that the packet was received correctly. A.3.3 Receiving Packets The flash loader sends a packet of data in the same format that it receives a packet. The flash loader may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte is the size of the packet followed by a checksum byte, and finally followed by the data itself. There is no break in the data after the first non-zero byte is sent from the flash loader. Once the device communicating with the flash loader receives all the bytes, it must either ACK or NAK the packet to indicate that the transmission was successful. The appropriate response after sending a NAK to the flash loader is to resend the command that failed and request the data again. If needed, the host may send leading zeros before sending down the ACK/NAK signal to the flash loader, as the November 30, 2007 431 Preliminary LM3S6110 Microcontroller flash loader only accepts the first non-zero data as a valid response. This zero padding is needed by the SSI interface in order to receive data to or from the flash loader. A.4 Commands The next section defines the list of commands that can be sent to the flash loader. The first byte of the data should always be one of the defined commands, followed by data or parameters as determined by the command that is sent. A.4.1 COMMAND_PING (0X20) This command simply accepts the command and sets the global status to success. The format of the packet is as follows: Byte[0] = 0x03; Byte[1] = checksum(Byte[2]); Byte[2] = COMMAND_PING; The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status, the receipt of an ACK can be interpreted as a successful ping to the flash loader. A.4.2 COMMAND_GET_STATUS (0x23) This command returns the status of the last command that was issued. Typically, this command should be sent after every command to ensure that the previous command was successful or to properly respond to a failure. The command requires one byte in the data of the packet and should be followed by reading a packet with one byte of data that contains a status code. The last step is to ACK or NAK the received data so the flash loader knows that the data has been read. Byte[0] = 0x03 Byte[1] = checksum(Byte[2]) Byte[2] = COMMAND_GET_STATUS A.4.3 COMMAND_DOWNLOAD (0x21) This command is sent to the flash loader to indicate where to store data and how many bytes will be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit values that are both transferred MSB first. The first 32-bit value is the address to start programming data into, while the second is the 32-bit size of the data that will be sent. This command also triggers an erase of the full area to be programmed so this command takes longer than other commands. This results in a longer time to receive the ACK/NAK back from the board. This command should be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size are valid for the device running the flash loader. The format of the packet to send this command is a follows: Byte[0] = 11 Byte[1] = checksum(Bytes[2:10]) Byte[2] = COMMAND_DOWNLOAD Byte[3] = Program Address [31:24] Byte[4] = Program Address [23:16] Byte[5] = Program Address [15:8] Byte[6] = Program Address [7:0] Byte[7] = Program Size [31:24] 432 November 30, 2007 Preliminary Serial Flash Loader Byte[8] = Program Size [23:16] Byte[9] = Program Size [15:8] Byte[10] = Program Size [7:0] A.4.4 COMMAND_SEND_DATA (0x24) This command should only follow a COMMAND_DOWNLOAD command or another COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands automatically increment address and continue programming from the previous location. The caller should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program successfully and not overflow input buffers of the serial interfaces. The command terminates programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to ensure that the data was successfully programmed into the flash. If the flash loader sends a NAK to this command, the flash loader does not increment the current address to allow retransmission of the previous data. Byte[0] = 11 Byte[1] = checksum(Bytes[2:10]) Byte[2] = COMMAND_SEND_DATA Byte[3] = Data[0] Byte[4] = Data[1] Byte[5] = Data[2] Byte[6] = Data[3] Byte[7] = Data[4] Byte[8] = Data[5] Byte[9] = Data[6] Byte[10] = Data[7] A.4.5 COMMAND_RUN (0x22) This command is used to tell the flash loader to execute from the address passed as the parameter in this command. This command consists of a single 32-bit value that is interpreted as the address to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK signal back to the host device before actually executing the code at the given address. This allows the host to know that the command was received successfully and the code is now running. Byte[0] = 7 Byte[1] = checksum(Bytes[2:6]) Byte[2] = COMMAND_RUN Byte[3] = Execute Address[31:24] Byte[4] = Execute Address[23:16] Byte[5] = Execute Address[15:8] Byte[6] = Execute Address[7:0] A.4.6 COMMAND_RESET (0x25) This command is used to tell the flash loader device to reset. This is useful when downloading a new image that overwrote the flash loader and wants to start from a full reset. Unlike the COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set up for the new code. It can also be used to reset the flash loader if a critical error occurs and the host device wants to restart communication with the flash loader. November 30, 2007 433 Preliminary LM3S6110 Microcontroller Byte[0] = 3 Byte[1] = checksum(Byte[2]) Byte[2] = COMMAND_RESET The flash loader responds with an ACK signal back to the host device before actually executing the software reset to the device running the flash loader. This allows the host to know that the command was received successfully and the part will be reset. 434 November 30, 2007 Preliminary Serial Flash Loader B Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 System Control Base 0x400F.E000 DID0, type RO, offset 0x000, reset - VER CLASS MAJOR MINOR PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD BORIOR LDOPCTL, type R/W, offset 0x034, reset 0x0000.0000 VADJ RIS, type RO, offset 0x050, reset 0x0000.0000 PLLLRIS BORRIS IMC, type R/W, offset 0x054, reset 0x0000.0000 PLLLIM BORIM MISC, type R/W1C, offset 0x058, reset 0x0000.0000 PLLLMIS BORMIS RESC, type R/W, offset 0x05C, reset - LDO SW WDT BOR POR EXT RCC, type R/W, offset 0x060, reset 0x07AE.3AD1 ACG SYSDIV USESYSDIV USEPWMDIV PWMDIV PWRDN BYPASS XTAL OSCSRC IOSCDIS MOSCDIS PLLCFG, type RO, offset 0x064, reset - F R RCC2, type R/W, offset 0x070, reset 0x0780.2800 USERCC2 SYSDIV2 PWRDN2 BYPASS2 OSCSRC2 DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000 DSDIVORIDE DSOSCSRC DID1, type RO, offset 0x004, reset - VER FAM PARTNO PINCOUNT TEMP PKG ROHS QUAL DC0, type RO, offset 0x008, reset 0x003F.001F SRAMSZ FLASHSZ DC1, type RO, offset 0x010, reset 0x0010.709F PWM MINSYSDIV MPU PLL WDT SWO SWD JTAG DC2, type RO, offset 0x014, reset 0x0707.0011 COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0 SSI0 UART0 DC3, type RO, offset 0x018, reset 0x0F00.B7C3 CCP3 CCP2 CCP1 CCP0 PWMFAULT C2PLUS C2MINUS C1PLUS C1MINUS C0O C0PLUS C0MINUS PWM1 PWM0 November 30, 2007 435 Preliminary LM3S6110 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DC4, type RO, offset 0x01C, reset 0x5000.007F EPHY0 EMAC0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA RCGC0, type R/W, offset 0x100, reset 0x00000040 PWM WDT SCGC0, type R/W, offset 0x110, reset 0x00000040 PWM WDT DCGC0, type R/W, offset 0x120, reset 0x00000040 PWM WDT RCGC1, type R/W, offset 0x104, reset 0x00000000 COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0 SSI0 UART0 SCGC1, type R/W, offset 0x114, reset 0x00000000 COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0 SSI0 UART0 DCGC1, type R/W, offset 0x124, reset 0x00000000 COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0 SSI0 UART0 RCGC2, type R/W, offset 0x108, reset 0x00000000 EPHY0 EMAC0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SCGC2, type R/W, offset 0x118, reset 0x00000000 EPHY0 EMAC0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA DCGC2, type R/W, offset 0x128, reset 0x00000000 EPHY0 EMAC0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SRCR0, type R/W, offset 0x040, reset 0x00000000 PWM WDT SRCR1, type R/W, offset 0x044, reset 0x00000000 COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0 SSI0 UART0 SRCR2, type R/W, offset 0x048, reset 0x00000000 EPHY0 EMAC0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Internal Memory Flash Control Offset Base 0x400F.D000 FMA, type R/W, offset 0x000, reset 0x0000.0000 OFFSET FMD, type R/W, offset 0x004, reset 0x0000.0000 DATA DATA FMC, type R/W, offset 0x008, reset 0x0000.0000 WRKEY COMT MERASE ERASE WRITE 436 November 30, 2007 Preliminary Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FCRIS, type RO, offset 0x00C, reset 0x0000.0000 PRIS ARIS FCIM, type R/W, offset 0x010, reset 0x0000.0000 PMASK AMASK FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000 PMISC AMISC Internal Memory System Control Offset Base 0x400F.E000 USECRL, type R/W, offset 0x140, reset 0x16 USEC FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE USER_DBG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE NW DATA DATA DBG1 DBG0 USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF NW DATA DATA USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF NW DATA DATA FMPRE1, type R/W, offset 0x204, reset 0x0000.0000 READ_ENABLE READ_ENABLE FMPRE2, type R/W, offset 0x208, reset 0x0000.0000 READ_ENABLE READ_ENABLE FMPRE3, type R/W, offset 0x20C, reset 0x0000.0000 READ_ENABLE READ_ENABLE FMPPE1, type R/W, offset 0x404, reset 0x0000.0000 PROG_ENABLE PROG_ENABLE FMPPE2, type R/W, offset 0x408, reset 0x0000.0000 PROG_ENABLE PROG_ENABLE FMPPE3, type R/W, offset 0x40C, reset 0x0000.0000 PROG_ENABLE PROG_ENABLE General-Purpose Input/Outputs (GPIOs) November 30, 2007 437 Preliminary LM3S6110 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIODATA, type R/W, offset 0x000, reset 0x0000.0000 DATA GPIODIR, type R/W, offset 0x400, reset 0x0000.0000 DIR GPIOIS, type R/W, offset 0x404, reset 0x0000.0000 IS GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000 IBE GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000 IEV GPIOIM, type R/W, offset 0x410, reset 0x0000.0000 IME GPIORIS, type RO, offset 0x414, reset 0x0000.0000 RIS GPIOMIS, type RO, offset 0x418, reset 0x0000.0000 MIS GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000 IC GPIOAFSEL, type R/W, offset 0x420, reset - AFSEL GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF DRV2 GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000 DRV4 GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000 DRV8 GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000 ODE GPIOPUR, type R/W, offset 0x510, reset - PUE GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000 PDE 438 November 30, 2007 Preliminary Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000 SRL GPIODEN, type R/W, offset 0x51C, reset - DEN GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001 LOCK LOCK GPIOCR, type -, offset 0x524, reset - CR GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 PID4 GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 PID5 GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 PID6 GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 PID7 GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061 PID0 GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 PID1 GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 PID2 GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 PID3 GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D CID0 GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 CID1 GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 CID2 GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 CID3 General-Purpose Timers November 30, 2007 439 Preliminary LM3S6110 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000 GPTMCFG GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000 TAAMS TACMR TAMR GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000 TBAMS TBCMR TBMR GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000 TBPWML TBOTE TBEVENT TBSTALL TBEN TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000 CBEIM CBMIM TBTOIM RTCIM CAEIM CAMIM TATOIM GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000 CBERIS CBMRIS TBTORIS RTCRIS CAERIS CAMRIS TATORIS GPTMMIS, type RO, offset 0x020, reset 0x0000.0000 CBEMIS CBMMIS TBTOMIS RTCMIS CAEMIS CAMMIS TATOMIS GPTMICR, type W1C, offset 0x024, reset 0x0000.0000 CBECINT CBMCINT TBTOCINT RTCCINT CAECINT CAMCINT TATOCINT GPTMTAILR, type R/W, offset 0x028, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) TAILRH TAILRL GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF TBILRL GPTMTAMATCHR, type R/W, offset 0x030, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) TAMRH TAMRL GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF TBMRL GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000 TAPSR GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000 TBPSR GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000 TAPSMR GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000 TBPSMR 440 November 30, 2007 Preliminary Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPTMTAR, type RO, offset 0x048, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) TARH TARL GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF TBRL Watchdog Timer Base 0x4000.0000 WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF WDTLoad WDTLoad WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF WDTValue WDTValue WDTCTL, type R/W, offset 0x008, reset 0x0000.0000 RESEN INTEN WDTICR, type WO, offset 0x00C, reset - WDTIntClr WDTIntClr WDTRIS, type RO, offset 0x010, reset 0x0000.0000 WDTRIS WDTMIS, type RO, offset 0x014, reset 0x0000.0000 WDTMIS WDTTEST, type R/W, offset 0x418, reset 0x0000.0000 STALL WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000 WDTLock WDTLock WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 PID4 WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 PID5 WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 PID6 WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 PID7 WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005 PID0 WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018 PID1 WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 PID2 November 30, 2007 441 Preliminary LM3S6110 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 PID3 WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D CID0 WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 CID1 WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 CID2 WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 CID3 Universal Asynchronous Receivers/Transmitters (UARTs) UART0 base: 0x4000.C000 UARTDR, type R/W, offset 0x000, reset 0x0000.0000 OE BE PE FE DATA UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000 OE BE PE FE UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000 DATA UARTFR, type RO, offset 0x018, reset 0x0000.0090 TXFE RXFF TXFF RXFE BUSY UARTILPR, type R/W, offset 0x020, reset 0x0000.0000 ILPDVSR UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000 DIVINT UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000 DIVFRAC UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000 SPS WLEN FEN STP2 EPS PEN BRK UARTCTL, type R/W, offset 0x030, reset 0x0000.0300 RXE TXE LBE SIRLP SIREN UARTEN UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012 RXIFLSEL TXIFLSEL UARTIM, type R/W, offset 0x038, reset 0x0000.0000 OEIM BEIM PEIM FEIM RTIM TXIM RXIM UARTRIS, type RO, offset 0x03C, reset 0x0000.000F OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS 442 November 30, 2007 Preliminary Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UARTMIS, type RO, offset 0x040, reset 0x0000.0000 OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS UARTICR, type W1C, offset 0x044, reset 0x0000.0000 OEIC BEIC PEIC FEIC RTIC TXIC RXIC UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 PID4 UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 PID5 UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 PID6 UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 PID7 UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011 PID0 UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 PID1 UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 PID2 UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 PID3 UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D CID0 UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 CID1 UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 CID2 UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 CID3 Synchronous Serial Interface (SSI) SSI0 base: 0x4000.8000 SSICR0, type R/W, offset 0x000, reset 0x0000.0000 SCR SPH SPO FRF DSS SSICR1, type R/W, offset 0x004, reset 0x0000.0000 SOD MS SSE LBM SSIDR, type R/W, offset 0x008, reset 0x0000.0000 DATA November 30, 2007 443 Preliminary LM3S6110 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSISR, type RO, offset 0x00C, reset 0x0000.0003 BSY RFF RNE TNF TFE SSICPSR, type R/W, offset 0x010, reset 0x0000.0000 CPSDVSR SSIIM, type R/W, offset 0x014, reset 0x0000.0000 TXIM RXIM RTIM RORIM SSIRIS, type RO, offset 0x018, reset 0x0000.0008 TXRIS RXRIS RTRIS RORRIS SSIMIS, type RO, offset 0x01C, reset 0x0000.0000 TXMIS RXMIS RTMIS RORMIS SSIICR, type W1C, offset 0x020, reset 0x0000.0000 RTIC RORIC SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 PID4 SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 PID5 SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 PID6 SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 PID7 SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022 PID0 SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 PID1 SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 PID2 SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 PID3 SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D CID0 SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 CID1 SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 CID2 444 November 30, 2007 Preliminary Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 CID3 Ethernet Controller Ethernet MAC Base 0x4004.8000 MACRIS, type RO, offset 0x000, reset 0x0000.0000 PHYINT MDINT RXER FOV TXEMP TXER RXINT MACIACK, type W1C, offset 0x000, reset 0x0000.0000 PHYINT MDINT RXER FOV TXEMP TXER RXINT MACIM, type R/W, offset 0x004, reset 0x0000.007F PHYINTM MDINTM RXERM FOVM TXEMPM TXERM RXINTM MACRCTL, type R/W, offset 0x008, reset 0x0000.0008 RSTFIFO BADCRC PRMS AMUL RXEN MACTCTL, type R/W, offset 0x00C, reset 0x0000.0000 DUPLEX CRC PADEN TXEN MACDATA, type RO, offset 0x010, reset 0x0000.0000 RXDATA RXDATA MACDATA, type WO, offset 0x010, reset 0x0000.0000 TXDATA TXDATA MACIA0, type R/W, offset 0x014, reset 0x0000.0000 MACOCT4 MACOCT3 MACOCT2 MACOCT1 MACIA1, type R/W, offset 0x018, reset 0x0000.0000 MACOCT6 MACOCT5 MACTHR, type R/W, offset 0x01C, reset 0x0000.003F THRESH MACMCTL, type R/W, offset 0x020, reset 0x0000.0000 REGADR WRITE START MACMDV, type R/W, offset 0x024, reset 0x0000.0080 DIV MACMTXD, type R/W, offset 0x02C, reset 0x0000.0000 MDTX MACMRXD, type R/W, offset 0x030, reset 0x0000.0000 MDRX MACNP, type RO, offset 0x034, reset 0x0000.0000 NPR November 30, 2007 445 Preliminary LM3S6110 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MACTR, type R/W, offset 0x038, reset 0x0000.0000 NEWTX Ethernet Controller MII Management Base 0x4004.8000 MR0, type R/W, address 0x00, reset 0x3100 RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT MR1, type RO, address 0x01, reset 0x7849 100X_F 100X_H 10T_F 10T_H MFPS ANEGC RFAULT ANEGA LINK JAB EXTD MR2, type RO, address 0x02, reset 0x000E OUI[21:6] MR3, type RO, address 0x03, reset 0x7237 OUI[5:0] MN RN MR4, type R/W, address 0x04, reset 0x01E1 NP RF A3 A2 A1 A0 S[4:0] MR5, type RO, address 0x05, reset 0x0000 NP ACK RF A[7:0] S[4:0] MR6, type RO, address 0x06, reset 0x0000 PDF LPNPA PRX LPANEGA MR16, type R/W, address 0x10, reset 0x0140 RPTR INPOL TXHIM SQEI NL10 APOL RVSPOL PCSBP RXCC MR17, type R/W, address 0x11, reset 0x0000 JABBER_IE RXER_IE PRX_IE PDF_IE LPACK_IE LSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INT RXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT ANEGCOMP_INT MR18, type RO, address 0x12, reset 0x0000 ANEGF DPLX RATE RXSD RX_LOCK MR19, type R/W, address 0x13, reset 0x4000 TXO[1:0] MR23, type R/W, address 0x17, reset 0x0010 LED1[3:0] LED0[3:0] MR24, type R/W, address 0x18, reset 0x00C0 PD_MODE AUTO_SW MDIX MDIX_CM MDIX_SD Analog Comparators Base 0x4003.C000 ACMIS, type R/W1C, offset 0x00, reset 0x0000.0000 IN2 IN1 IN0 ACRIS, type RO, offset 0x04, reset 0x0000.0000 IN2 IN1 IN0 ACINTEN, type R/W, offset 0x08, reset 0x0000.0000 IN2 IN1 IN0 ACREFCTL, type R/W, offset 0x10, reset 0x0000.0000 EN RNG VREF ACSTAT0, type RO, offset 0x20, reset 0x0000.0000 OVAL ACSTAT1, type RO, offset 0x40, reset 0x0000.0000 OVAL 446 November 30, 2007 Preliminary Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACSTAT2, type RO, offset 0x60, reset 0x0000.0000 OVAL ACCTL0, type R/W, offset 0x24, reset 0x0000.0000 ASRCP ISLVAL ISEN CINV ACCTL1, type R/W, offset 0x44, reset 0x0000.0000 ASRCP ISLVAL ISEN CINV ACCTL2, type R/W, offset 0x64, reset 0x0000.0000 ASRCP ISLVAL ISEN CINV Pulse Width Modulator (PWM) Base 0x4002.8000 PWMCTL, type R/W, offset 0x000, reset 0x0000.0000 GlobalSync0 PWMSYNC, type R/W, offset 0x004, reset 0x0000.0000 Sync0 PWMENABLE, type R/W, offset 0x008, reset 0x0000.0000 PWM1En PWM0En PWMINVERT, type R/W, offset 0x00C, reset 0x0000.0000 PWM1Inv PWM0Inv PWMFAULT, type R/W, offset 0x010, reset 0x0000.0000 Fault1 Fault0 PWMINTEN, type R/W, offset 0x014, reset 0x0000.0000 IntFault IntPWM0 PWMRIS, type RO, offset 0x018, reset 0x0000.0000 IntFault IntPWM0 PWMISC, type R/W1C, offset 0x01C, reset 0x0000.0000 IntFault IntPWM0 PWMSTATUS, type RO, offset 0x020, reset 0x0000.0000 Fault PWM0CTL, type R/W, offset 0x040, reset 0x0000.0000 CmpBUpd CmpAUpd LoadUpd Debug Mode Enable PWM0INTEN, type R/W, offset 0x044, reset 0x0000.0000 IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero PWM0RIS, type RO, offset 0x048, reset 0x0000.0000 IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero PWM0ISC, type R/W1C, offset 0x04C, reset 0x0000.0000 IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero November 30, 2007 447 Preliminary LM3S6110 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM0LOAD, type R/W, offset 0x050, reset 0x0000.0000 Load PWM0COUNT, type RO, offset 0x054, reset 0x0000.0000 Count PWM0CMPA, type R/W, offset 0x058, reset 0x0000.0000 CompA PWM0CMPB, type R/W, offset 0x05C, reset 0x0000.0000 CompB PWM0GENA, type R/W, offset 0x060, reset 0x0000.0000 ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero PWM0GENB, type R/W, offset 0x064, reset 0x0000.0000 ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero PWM0DBCTL, type R/W, offset 0x068, reset 0x0000.0000 Enable PWM0DBRISE, type R/W, offset 0x06C, reset 0x0000.0000 RiseDelay PWM0DBFALL, type R/W, offset 0x070, reset 0x0000.0000 FallDelay 448 November 30, 2007 Preliminary Register Quick Reference C Ordering and Contact Information C.1 Ordering Information L M 3 S n n n n – g p p s s – r r m Part Number Temperature Package Speed Revision Shipping Medium I = -40 C to 85 C T = Tape-and-reel Omitted = Default shipping (tray or tube) Omitted = Default to current shipping revision A0 = First all-layer mask A1 = Metal layers update to A0 A2 = Metal layers update to A1 B0 = Second all-layer mask revision RN = 28-pin SOIC QN = 48-pin LQFP QC = 100-pin LQFP 20 = 20 MHz 25 = 25 MHz 50 = 50 MHz Table C-1. Part Ordering Information Orderable Part Number Description Stellaris® LM3S6110-IQC25 LM3S6110 Microcontroller Stellaris® LM3S6110-IQC25(T) LM3S6110 Microcontroller C.2 Kits The Luminary Micro Stellaris® Family provides the hardware and software tools that engineers need to begin development quickly. ■ Reference Design Kits accelerate product development by providing ready-to-run hardware, and comprehensive documentation including hardware design files: http://www.luminarymicro.com/products/reference_design_kits/ ■ Evaluation Kits provide a low-cost and effective means of evaluating Stellaris® microcontrollers before purchase: http://www.luminarymicro.com/products/evaluation_kits/ ■ Development Kits provide you with all the tools you need to develop and prototype embedded applications right out of the box: http://www.luminarymicro.com/products/boards.html See the Luminary Micro website for the latest tools available or ask your Luminary Micro distributor. C.3 Company Information Luminary Micro, Inc. designs, markets, and sells ARM Cortex-M3-based microcontrollers (MCUs). Austin, Texas-based Luminary Micro is the lead partner for the Cortex-M3 processor, delivering the world's first silicon implementation of the Cortex-M3 processor. Luminary Micro's introduction of the November 30, 2007 449 Preliminary LM3S6110 Microcontroller Stellaris® family of products provides 32-bit performance for the same price as current 8- and 16-bit microcontroller designs. With entry-level pricing at $1.00 for an ARM technology-based MCU, Luminary Micro's Stellaris product line allows for standardization that eliminates future architectural upgrades or software tool changes. Luminary Micro, Inc. 108 Wild Basin, Suite 350 Austin, TX 78746 Main: +1-512-279-8800 Fax: +1-512-279-8879 http://www.luminarymicro.com sales@luminarymicro.com C.4 Support Information For support on Luminary Micro products, contact: support@luminarymicro.com +1-512-279-8800, ext. 3 450 November 30, 2007 Preliminary Ordering and Contact Information 1 EIT Series FCC-B U Put Any Serial Device On the IP Network in Minutes U Bridge RS232/RS485 to TCP/IP U Auto-negotiating 10/100 Ethernet Half/ Full Duplex U Built-in Web Server U TCP, UDP, SNMP, SMTP, TFTP, ICMP, Telnet, DHCP, DNS, HTTP, and ARP U MODBUS® RTU to MODBUS TCP/IP Bridging U Email Notifications and SNMP Traps U 1 to 6 Programmable I/Os U Firmware Upgrade Over Ethernet U Custom Firmware/Private Labeling for OEMs U TCP Socket with Command Line Interface U Serial Speed Up to 460 Kb/s U Authentication and Access Restrictions U Small Enough to Fit Almost Anywhere U Free COM Port Redirector U Free Configuration Software iServer MicroServerTM for Serial-to-Ethernet Applications The 3rd Generation NEWPORT® connects any Serial Device (RS232, RS485) to an Ethernet network or the Internet in minutes, including Serial Modbus to ModbusTCP/IP over Ethernet. The iServer3G can send notifications by email, and has SNMP for remote management. Newport offers custom firmware and private-labeling for OEMs. EIT-D DIN rail for industrial applications, shown smaller than actual size. EIT-W Wall mount or benchtop for commercial applications, shown smaller than actual size. EIT-PCB Embedded PC board assembly for OEMs, shown smaller than actual size. Connect any serial device to Ethernet LAN and the Internet Quickly configured through a web browser 2 To Order Visit newportUS.com/eit for Pricing and Details Model No. Description EIT-W iServer MicroServer™ for Serial-to-Ethernet applications in commercial wall-mount case with universal AC power adaptor (100 to 240 Vac input, 5 Vdc output); full RS232 serial interface with 1 input pin EIT-W-485 Commercial wall-mount case; RS485 (full and half duplex) serial interface with 3 I/Os EIT-D Industrial DIN rail case with screw terminal serial ports; full RS232 serial interface without I/Os EIT-D-485 Industrial DIN rail case; RS485 (full and half duplex) serial interface with 3 I/Os EIT-PCB Printed circuit board for embedded applications; full RS232 serial interface with 3 I/Os EIT-PCB-485 Printed circuit board; RS485 (full and half duplex) serial interface with 6 I/Os Ordering Example: EIT-W, one full RS232 serial interface commercial wall-mount iServer MicroServer. * Volume discounts are available. Sensor Specifications Serial Interface Interface: RS232 or RS485 (2- and 4-wire) Connector: DB9 male DTE for RS232; 8 position terminal block plug for RS485 Serial Data Rates: 300 to 460.8 Kbps Characters: 5, 6, 7, or 8 data bits Parity: odd, even, or none Stop Bits: 1 or 2 Flow Control: Hardware (RTS/CTS) and Software (Xon/Xoff) Digital I/Os: 1 to 6 programmable input/output lines, depending on model. Network Interface Interface: Fixed or auto-negotiating 10/100BASE-T half/full duplex Ethernet with auto MDI/MDIX Connector: RJ45 Protocols: TCP, UDP, SNMP, SMTP, TFTP, ICMP, DHCP, DNS, HTTP, ARP, Modbus TCP/IP and Telnet Compliant to Standard: IEEE 802.3 Indicators (LEDs): 100BASE-T, Network Link/Activity, and Serial Transmit/Receive 32-Bit Microprocessor: CPU: ARM7, 72 MHz Memory: 512 Kbyte Flash, 32 Kbyte SRAM Embedded Web Server: Serves dynamic Web pages and Java applets Management: Web server, Telnet login, Serial login, iConnect General Power (for EIT-PCB): Input: 5 Vdc @ 200 mA max. Consumption: 1 W max. Power (for EIT-W): Input: 5 Vdc @ 200 mA max Consumption: 1 W max. Safety Qualified AC Power Adapter (included): Nominal Output: 5 Vdc @ 600 mA; Input: 100 to 240 Vac, 50/60Hz Operating Temperature: 0 to 40°C (32 to 104°F) Power (for EIT-D): Input: 10 to 32 Vdc Consumption: 2 W max. DC Power supply sold separately: iDRN-PS-1000 Packaging (for EIT-W): Material: ABS (ChiMei PA-757) with wall mount bracket Dimensions: 27.4H x 66.0W x 93.1D mm (1.08 x 2.60 x 3.67 in) Weight: 77g (0.17 lbs.) Packaging (for EIT-D): Material: Polycarbonate case with DIN Rail mount Dimensions: 90.2H x 25.1W x 115.0D mm (3.54 x .99 x 4.53 in) Weight: 113g (0.25 lbs.) Packaging (for EIT-PCB): Material: FR4 Board Surface area dimensions: Approximately 80 sq. mm (3 sq") Weight: 14g (0.03 lbs.) Environmental Operating Temperature: -40 to 85°C (-40 to 185°F) Storage Temperature: -40 to 100°C (-40 to 212°F) Software Firmware upgrade from Ethernet COM Port redirector (iPort); Configuration Software utility (iConnect) Compatible with Windows 9x/ME/NT/2000/XP software and related utilities 2.60 [66.0] 1.08 [ 27.4] 3.67 [93.1] 100BASE-T LINK/ACT TRANSMIT RECEIVE RS232 RS485 0.88 [ 22.4] COMMUNICATIONS ETHERNET DC POWER IN RECEIVE TRANSMIT LINK/ACT 100BASE-T RESET N/C 4.53 [115] 0.99 [25.1] 3.54 [90.2] EIT-D Material: Polycarbonate case with DIN rail mount Weight: 113 g (0.25 lbs) EIT-W Material: ABS (ChiMei PA-757) with wall mount Weight: 77 g (0.17 lbs) EIT-PCB Board Surface area: approximately 3 sq. inches [80 sq. mm] Weight: 14 g (0.03 lbs) EIT-W READINGS http://192.168.1.200 Overview Network Serial I/O Pins Management Security Device Query Device Setup Readings Terminal System Diagnostics READINGS 000 Auto Update 1 Boiler 1 92.4 Deg. C No De vice Name Reading Unit 92.4 Deg. C Dimensions: in (mm) ø = diameter Mechanical SB520-SB5100 2001 Fairchild Semiconductor Corporation SB520 - SB5100, Rev. C Features •Metal to silicon rectifier, majoritycarrier conduction. •For use in low voltage, highfrequency inverters freewheeling, and polarityprotection applications. • Low power loss, high efficiency. • High current capability, low VF. • High surge capacity. SB520 - SB5100 Schottky Rectifiers Absolute Maximum Ratings* TA = 25°C unless otherwise noted *These ratings are limiting values above which the serviceability of any semiconductor device may be impaired. Electrical Characteristics TA = 25°C unless otherwise noted Symbol Parameter Value Units PD Power Dissipation 5.0 W RθJA Thermal Resistance, Junction to Ambient 25 °C/W Symbol Parameter Device Units 520 530 540 550 560 580 5100 VF Forward Voltage @ 5.0 A 0.55 0.67 0.85 V IR Reverse Current @ rated VR TA = 25°C 0.5 mA TA = 100°C 50 25 mA CT Total Capacitance VR = 4.0 V, f = 1.0 MHz 500 380 pF DO-201AD COLOR BAND DENOTES CATHODE Thermal Characteristics Symbol Parameter Value Units 520 530 540 550 560 580 5100 VRRM Maximum Repetitive Reverse Voltage 20 30 40 50 60 80 100 V IF(AV) Average Rectified Forward Current .375 " lead length @ TA = 75°C 5.0 A IFSM Non-repetitive Peak Forward Surge Current 8.3 ms Single Half-Sine-Wave 150 A Tstg Storage Temperature Range -50 to +150 °C TJ Operating Junction Temperature -50 to +150 °C • Glass passivated SB520-SB5100 2001 Fairchild Semiconductor Corporation SB520 - SB5100, Rev. C Schottky Rectifiers (continued) Typical Characteristics 1 2 5 102050100 0 30 60 90 120 150 Number of Cycles at 60Hz Peak Forward Surge Current, IFSM [A] 0.1110100 100 200 500 1000 2000 5000 Reverse Voltage, VR [V] Total Capacitance, CT [pF] SB520-SB540 SB550-SB5100 0.40.50.60.70.80.911.1 0.1 1 10 40 Forward Voltage, VF [V] Forward Current, IF [A] Pulse Width = 300μS 2% Duty Cycle T = 25 C A º SB520-SB540 SB550-SB560 SB580-SB5100 0 255075100125150175 0 1 2 3 4 5 Ambient Temperature [ºC] Average Rectified Forward Current, IF [A] SINGLE PHASE HALF WAVE 60HZ RESISTIVE OR INDUCTIVE LOAD .375" (9.00mm) LOAD LENGTHS SB520-SB540 SB550-SB5100 0 20406080100120140 0.001 0.01 0.1 1 10 20 Percent of Rated Peak Reverse Voltage [%] Reverse Current, IR [mA] T = 25 C A º T = 75 C A º T = 100 C A º SB520-SB540 SB550-SB5100 SB520-SB540 SB550-SB5100 Figure 1. Forward Current Derating Curve Figure 2. Non-Repetitive Surge Current Figure 3. Forward Voltage Characteristics Figure 4. Reverse Current vs Reverse Voltage Figure 5. Total Capacitance DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOTASSUME ANY LIABILITYARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEYANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Preliminary No Identification Needed Obsolete This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Formative or In Design First Production Full Production Not In Production OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER FAST FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ Rev. H4 â ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ â UltraFET â â STAR*POWER is used under license VCX™ RaspiCam Documentation July 2013 This document describes the use of the three Raspberry Pi camera applications as of July 2013. There are three applications provided: raspistill, raspivid and raspistillyuv. Both raspistill and raspistillyuv are very similar and are intended for capturing images, while raspivid is for capturing video. All the applications are command-line driven, written to take advantage of the mmal API which runs over OpenMAX. The mmal API provides an easier to use system than that presented by OpenMAX. Note that mmal is a Broadcom specific API used only on Videocore 4 systems. The applications use up to four OpenMAX(mmal) components - camera, preview, encoder and null_sink. All applications use the camera component: raspistill uses the Image Encode component, raspivid uses the Video Encode component, and raspistillyuv does not use an encoder, and sends its YUV or RGB output direct from camera component to file. The preview display is optional, but can be used full screen or directed to a specific rectangular area on the display. If preview is disabled, the null_sink component is used to 'absorb' the preview frames. It is necessary for the camera to produce preview frames even if not required for display, as they are used for calculating exposure and white balance settings. In addition it is possible to omit the filename option, in which case the preview is displayed but no file is written, or to redirect all output to stdout. Command line help is available by typing just the application name in on the command line. Setting up the camera hardware Please note that camera modules are static-sensitive. Earth yourself prior to handling the PCB: a sink tap/faucet or similar should suffice if you don’t have an earthing strap. The camera board attaches to the Raspberry Pi via a 15-way ribbon cable. There are only two connections to make: the ribbon cable need to be attached to the camera PCB and the Raspberry Pi itself. You need to get it the right way round, or the camera will not work. On the camera PCB, the blue backing on the cable should be facing away from the PCB, and on the Raspberry Pi it should be facing towards the Ethernet connection (or where the Ethernet connector would be if you are using a model A). Although the connectors on the PCB and the Pi are different, they work in a similar way. On the Raspberry Pi, pull up the tabs on each end of the connector. It should slide up easily, and be able to pivot around slightly. Fully insert the ribbon cable into the slot, ensuring it is straight, then gently press down the tabs to clip it into place. The camera PCB itself also requires you to pull the tabs away from the board, gently insert the cable, then push the tabs back. The PCB connector is a little more awkward than the one on the Pi itself. You can watch a video showing you how to attach the connectors at www.raspberrypi.org/archives/3890 (scroll down for the video). Setting up the Camera software Execute the following instructions on the command line to download and install the latest kernel, GPU firmware and applications. You will need an internet connection for this to work correctly. sudo apt-get update sudo apt-get upgrade Now you need to enable camera support, using the raspiconfig program you will have used when you first set up your Raspberry Pi. sudo raspi-config Use the cursor keys to move to the camera option and select enable. On exiting raspi-config it will ask to reboot. The enable option will ensure that on reboot the correct GPU firmware will be running (with the camera driver and tuning), and the GPU memory split is sufficient to allow the camera to acquire enough memory to run correctly. To test that the system is installed and working, try the following command: raspistill -v -o test.jpg The display should show a 5-second preview from the camera and then take a picture, saved to the file test.jpg, while displaying various informational messages. Troubleshooting If the camera is not working correctly, there are number of things to try. • Are the ribbon connectors all firmly seated and the right way round? They must be straight in their sockets. • Is the camera module connector firmly attached to the camera PCB? This is the connection from the smaller black camera module itself to the camera PCB. Sometimes this connection can come loose. Using a fingernail, flip up the connector on the PCB, then reseat it with gentle pressure, it engages with a very slight click. • Have sudo apt-get update and sudo apt-get upgrade been run? • Has raspi-config been run and the camera enabled? If things are still not working, try the following: Error : raspistill/raspivid not found. This probably means your update/upgrade failed in some way. Try it again. Error : ENOMEM displayed. Camera is not starting up. Check all connections again. Error : ENOSPC displayed. Camera is probably running out of GPU memory. Check config.txt in the /boot/ folder. The gpu_mem option should be at least 128. If, after all the above, the camera is still not working, it may have a defect (most likely because it has suffered static shock). Try posting on the Raspberry Pi forum in the camera board section to see if there is any more help available there. Common Command line Options Preview Window --preview, -p Preview window settings <'x,y,w,h'> Allows the user to define the size and location on the screen that the preview window will be placed. Note this will be superimposed over the top of any other windows/graphics. --fullscreen, -f Fullscreen preview mode Forces the preview window to use the whole screen. Note that the aspect ratio of the incoming image will be retained, so there may be bars on some edges. --nopreview, -n, Do not display a preview window Disables the preview window completely. Note that even though the preview is disabled, the camera will still be producing frames, so will be using power. --opacity, -op Set preview window opacity Sets the opacity of the preview windows. 0 = invisible, 255 = fully opaque. Camera Control Options --sharpness, -sh Set image sharpness (-100 to 100) Set the sharpness of the image, 0 is the default. --contrast, -co Set image contrast (-100 to 100) Set the contrast of the image, 0 is the default --brightness, -br Set image brightness (0 to 100) Set the brightness of the image, 50 is the default. 0 is black, 100 is white. --saturation, -sa Set image saturation (-100 to 100) Set the colour saturation of the image. 0 is the default. --ISO, -ISO Set capture ISO Sets the ISO to be used for captures. Range is 100 to 800. --vstab, -vs Turn on video stabilization In video mode only, turn on video stabilization. --ev, -ev Set EV compensation Set the EV compensation of the image. Range is -10 to +10, default is 0. --exposure, -ex Set exposure mode Possible options are: off auto Use automatic exposure mode night Select setting for night shooting nightpreview backlight Select setting for back-lit subject spotlight sports Select setting for sports (fast shutter etc.) snow Select setting optimized for snowy scenery beach Select setting optimized for beach verylong Select setting for long exposures fixedfps Constrain fps to a fixed value antishake Antishake mode fireworks Select setting optimized for fireworks Note that not all of these settings may be implemented, depending on camera tuning. --awb, -awb Set automatic white balance (AWB) off Turn off white balance calculation auto Automatic mode (default) sun Sunny mode cloud shade Cloudy mode tungsten Tungsten lighting mode fluorescent Fluorescent lighting mode incandescent Incandescent lighting mode flash Flash mode horizon Horizon mode --imxfx, -ifx Set image effect none No effect negative Produces a negative image solarise Solarise the image whiteboard Whiteboard effect blackboard Blackboard effect sketch Sketch-style effect denoise Denoise the image emboss Embossed effect oilpaint Oil paint-style effect hatch Cross-hatch sketch style gpen Graphite sketch style pastel Pastel effect watercolour Watercolour effect film Grainy film effect blur Blur the image saturation Colour-saturate the image colourswap Not fully implemented washedout Not fully implemented posterise Not fully implemented colourpoint Not fully implemented colourbalance Not fully implemented cartoon Not fully implemented --colfx, -cfx Set colour effect The supplied U and V parameters (range 0 to 255) are applied to the U and Y channels of the image. For example, --colfx 128:128 should result in a monochrome image. --metering, -mm Set metering mode Specify the metering mode used for the preview and capture. average Average the whole frame for metering spot Spot metering backlit Assume a backlit image matrix Matrix metering --rotation, -rot Set image rotation (0-359) Sets the rotation of the image in viewfinder and resulting image. This can take any value from 0 upwards, but due to hardware constraints only 0, 90, 180 and 270-degree rotations are supported. --hflip, -hf Set horizontal flip Flips the preview and saved image horizontally. --vflip, -vf Set vertical flip Flips the preview and saved image vertically. --roi, -roi Set sensor region of interest Allows the specification of the area of the sensor to be used as the source for the preview and capture. This is defined as x,y for the top left corner, and a width and height, all values in normalised coordinates (0.0-1.0). So to set a ROI at half way across and down the sensor, and an width and height of a quarter of the sensor use : -roi 0.5,0.5,0.25,0.25 Application-­‐specific settings raspistill --width, -w Set image width --height, -h Set image height --quality, -q Set jpeg quality <0 to 100> Quality 100 is almost completely uncompressed. 75 is a good allround value. --raw, -r Add raw Bayer data to jpeg metadata This option inserts the raw Bayer data from the camera in to the JPEG metadata. --output -o Output filename Specify the output filename. If not specified, no file is saved. If the filename is '-', then all output is sent to stdout. --verbose, -v Output verbose information during run Outputs debugging/information messages during the program run. --timeout, -t Time before capture and shut down The program will run for this length of time, then take the capture (if output is specified). If not specified, this is set to 5 seconds. --timelapse, -tl Timelapse mode. The specific value is the time between shots in milliseconds. Note you should specify %04d at the point in the filename where you want a frame count number to appear. For example: -t 30000 -tl 2000 -o image%04d.jpg will produce a capture every 2 seconds over a total period of 30s, named image1.jpg, image0002.jpg...image0015.jpg. Note that the %04d indicates a four-digit number with leading zeros added to pad to the required number of digits. So, for example, %08d would result in an eight-digit number. --thumb, -th Set thumbnail parameters (x:y:quality) Allows specification of the thumbnail image inserted in to the JPEG file. If not specified, defaults are a size of 64x48 at quality 35. --demo, -d Run a demo mode This options cycles through range of camera options, and no capture is done. The demo will end at the end of the timeout period, irrespective of whether all the options have been cycled. The time between cycles should be specified as a millisecond value. --encoding, -e Encoding to use as output file Valid options are jpg, bmp, gif and png. Note that unaccelerated image types (gif, png, bmp) will take much longer to save than jpg, which is hardware accelerated. Also note that the filename suffix is completely ignored when encoding a file. --exif, -x EXIF tag to apply to captures (format as 'key=value') Allows the insertion of specific EXIF tags into the JPEG image. You can have up to 32 EXIF tge entries. This is useful for things like adding GPS metadata. For example, to set the longitude: --exif GPS.GPSLongitude=5/1,10/1,15/100 would set the longitude to 5degs, 10 minutes, 15 seconds. See EXIF documentation for more details on the range of tags available; the supported tags are as follows: IFD0.< or IFD1.< ImageWidth, ImageLength, BitsPerSample, Compression, PhotometricInterpretation, ImageDescription, Make, Model, StripOffsets, Orientation, SamplesPerPixel, RowsPerString, StripByteCounts, Xresolution, Yresolution, PlanarConfiguration, ResolutionUnit, TransferFunction, Software, DateTime, Artist, WhitePoint, PrimaryChromaticities, JPEGInterchangeFormat, JPEGInterchangeFormatLength, YcbCrCoefficients, YcbCrSubSampling, YcbCrPositioning, ReferenceBlackWhite, Copyright> EXIF.< ExposureTime, FNumber, ExposureProgram, SpectralSensitivity, a ISOSpeedRatings, OECF, ExifVersion, DateTimeOriginal, DateTimeDigitized, ComponentsConfiguration, CompressedBitsPerPixel, ShutterSpeedValue, ApertureValue, BrightnessValue, ExposureBiasValue, MaxApertureValue, SubjectDistance, MeteringMode, LightSource, Flash, FocalLength, SubjectArea, MakerNote, UserComment, SubSecTime, SubSecTimeOriginal, SubSecTimeDigitized, FlashpixVersion, ColorSpace, PixelXDimension, PixelYDimension, RelatedSoundFile, FlashEnergy, SpacialFrequencyResponse, FocalPlaneXResolution, FocalPlaneYResolution, FocalPlaneResolutionUnit, SubjectLocation, ExposureIndex, SensingMethod, FileSource, SceneType, CFAPattern, CustomRendered, ExposureMode, WhiteBalance, DigitalZoomRatio, FocalLengthIn35mmFilm, SceneCaptureType, GainControl, Contrast, Saturation, Sharpness, DeviceSettingDescription, SubjectDistanceRange, ImageUniqueID> GPS.< GPSVersionID, GPSLatitudeRef, GPSLatitude, GPSLongitudeRef, GPSLongitude, GPSAltitudeRef, GPSAltitude, GPSTimeStamp, GPSSatellites, GPSStatus, GPSMeasureMode, GPSDOP, GPSSpeedRef, GPSSpeed, GPSTrackRef, GPSTrack, GPSImgDirectionRef, GPSImgDirection, GPSMapDatum, GPSDestLatitudeRef, GPSDestLatitude, GPSDestLongitudeRef, GPSDestLongitude, GPSDestBearingRef, GPSDestBearing, GPSDestDistanceRef, GPSDestDistance, GPSProcessingMethod, GPSAreaInformation, GPSDateStamp, GPSDifferential> EINT.< InteroperabilityIndex, InteroperabilityVersion, RelatedImageFileFormat, RelatedImageWidth, RelatedImageLength> Note that a small subset of these tags will be set automatically by the camera system, but will be overridden by any exif options on the command line. --fullpreview, -fp Full Preview mode This runs the preview windows using the full resolution capture mode. Maximum frames per second in this mode is 15fps and the preview will have the same field of view as the capture. Captures should happen more quickly as no mode change should be required. This feature is currently under development. raspistillyuv Many of the options for raspistillyuv are the same as those for raspistill. This section shows the differences. Unsupported Options: --exif, --encoding, --thumb, --raw, --quality Extra Options: --rgb, -rgb Save uncompressed data as RGB888 This option forces the image to be saved as RGB data with 8 bits per channel, rather than YUV420. Note that the image buffers saved in raspistillyuv are padded to a horizontal size divisible by 16 (so there may be unused bytes at the end of each line to made the width divisible by 16). Buffers are also padded vertically to be divisible by 16, and in the YUV mode, each plane of Y,U,V is padded in this way. raspivid --width, -w Set image width Width of resulting video. This should be between 64 and 1920. --height, -h Set image height Height of resulting video. This should be between 64 and 1080. --bitrate, -b Set bitrate Use bits per second, so 10MBits/s would be -b 10000000. For H264, 1080p a high quality bitrate would be 15Mbits/s or more. --output, -o Output filename . Specify the output filename. If not specified, no file is saved. If the filename is '-', then all output is sent to stdout. --verbose, -v Output verbose information during run Outputs debugging/information messages during the program run. --timeout, -t Time before capture and shut down The program will run for this length of time, then take the capture (if output is specified). If not specified, this is set to five seconds. Setting 0 will mean the application will run continuously until stopped with Ctrl-C. --demo, -d Run a demo mode This option cycles through range of camera options, no capture is done, the demo will end at the end of the timeout period, irrespective of whether all the options have been cycled. The time between cycles should be specified as a millisecond value. --framerate, -fps Specify the frames per second to record At present, the minimum frame rate allowed is 2fps, the maximum is 30fps. This is likely to change in the future. --penc, -e Display preview image after encoding Switch on an option to display the preview after compression. This will show any compression artefacts in the preview window. In normal operation, the preview will show the camera output prior to being compressed. This option is not guaranteed to work in future releases. --intra, -g Specify the intra refresh period (key frame rate/GoP) Sets the intra refresh period (GoP) rate for the recorded video. H.264 video uses a complete frame (I-frame) every intra refresh period from which subsequent frames are based. This options specifies the numbers of frames between each I-frame. Larger numbers here will reduce the size of the resulting video, smaller numbers make the stream more robust to error. Examples Still captures By default, captures are done at the highest resolution supported by the sensor. This can be changed using the -w and -h command line options. Taking a default capture after two seconds (note times are specified in milliseconds) on viewfinder, saving in image.jpg raspistill -t 2000 -o image.jpg Take a capture at a different resolution raspistill -t 2000 -o image.jpg -w 640 -h 480 Now reduce the quality considerably to reduce file size raspistill -t 2000 -o image.jpg -q 5 Force the preview to appear at coordinate 100,100, with width 300 and height 200 pixels. raspistill -t 2000 -o image.jpg -p 100,100,300,200 Disable preview entirely. raspistill -t 2000 -o image.jpg -n Save the image as a png file (lossless compression, but slower than JPEG). Note that the filename suffix is ignored when choosing the image encoding. raspistill -t 2000 -o image.png –e png Add some EXIF information to the JPEG. This sets the Artist tag name to Mooncake, and the GPS altitude to 123.5m. Note that if setting GPS tags you should set as a minimum GPSLatitude, GPSLatitudeRef, GPSLongitude, GPSLongitudeRef, GPSAltitude and GPSAltitudeRef. raspistill -t 2000 -o image.jpg -x IFDO.Artist=Mooncake -x GPS.GPSAltitude=1235/10 Set an emboss style image effect. raspistill -t 2000 -o image.jpg -ifx emboss Set the U and V channels of the YUV image to specific values (128:128 produces a greyscale image) raspistill -t 2000 -o image.jpg -cfx 128:128 Run preview ONLY for two seconds, no saved image. raspistill -t 2000 Take timelapse picture, one every 10 seconds for 10 minutes (10 minutes = 600000ms), named image_number_1_today.jpg, image_number_2_today.jpg onwards. raspistill -t 600000 -tl 10000 -o image_num_%d_today.jpg Take a picture and send image data to stdout raspistill -t 2000 -o - Take a picture and send image data to file raspistill -t 2000 -o - > my_file.jpg Video Captures Image size and preview settings are the same as for stills capture. Default size for video recording is 1080p (1920x1080) Record a 5s clip with default settings (1080p30) raspivid -t 5000 -o video.h264 Record a 5s clip at a specified bitrate (3.5MBits/s) raspivid -t 5000 -o video.h264 -b 3500000 Record a 5s clip at a specified framerate (5fps) raspivid -t 5000 -o video.h264 -f 5 Encode a 5s camera stream and send image data to stdout raspivid -t 5000 -o - Encode a 5s camera stream and send image data to file raspivid -t 5000 -o - > my_file.h264 L78S 2 A positive voltage regulator IC Datasheet - production data Features • Output current up to 2 A • Output voltages of 5; 7.5; 9; 10; 12; 15; 18; 24 V • Thermal protection • Short circuit protection • Output transition SOA protection Description The L78S series of three-terminal positive regulators is available in TO-220 package and several fixed output voltages, making it useful in a wide range of applications. These regulators can provide local on-card regulation, eliminating the distribution problems associated with single point regulation. Each type embeds internal current limiting, thermal shut-down and safe area protection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 2 A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltages and currents. TO-220 Table 1. Device summary Part numbers TO-220 packages Output voltage Dual gauge Single gauge L78S05C L78S05CV-DG L78S05CV 5 V L78S75C L78S75CV-DG L78S75CV 7.5 V L78S09C L78S09CV-DG L78S09CV 9 V L78S10C L78S10CV-DG L78S10CV 10 V L78S12C L78S12CV-DG L78S12CV 12 V L78S15C L78S15CV-DG L78S15CV 15 V L78S18C L78S18CV 18 V L78S24C L78S24CV 24 V www.st.com Contents L78S 2/35 DocID2148 Rev 8 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DocID2148 Rev 8 3/35 L78S List of tables 35 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Electrical characteristics of L78S05C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. Electrical characteristics of L78S75C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. Electrical characteristics of L78S09C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Electrical characteristics of L78S10C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Electrical characteristics of L78S12C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 9. Electrical characteristics of L78S15C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 10. Electrical characteristics of L78S18C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 11. Electrical characteristics of L78S24C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 12. TO-220 (dual gauge) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 13. TO-220 SG (single gauge) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 List of figures L78S 4/35 DocID2148 Rev 8 List of figures Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. DC parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Ripple rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Dropout voltage vs. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9. Peak output current vs. input/output differential voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10. Output impedance vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11. Output voltage vs. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 12. Supply voltage rejection vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 13. Quiescent current vs. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 14. Load transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 15. Line transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 16. Quiescent current vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 17. Fixed output regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 18. Constant current regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 19. Circuit for increasing output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 20. Adjustable output regulator (7 to 30 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 21. 0.5 to 10 V regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 22. High current voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 23. High output current with short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 24. Tracking voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 25. Positive and negative regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 26. Negative output voltage circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 27. Switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 28. High input voltage circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 29. High input voltage circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 30. High output voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 31. High input and output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 32. Reducing power dissipation with dropping resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 33. Remote shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 34. Power AM modulator (unity voltage gain, IO £ 1 A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 35. Adjustable output voltage with temperature compensation . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 36. Light controllers (VOmin = VXX + VBE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 37. Protection against input short-circuit with high capacitance loads . . . . . . . . . . . . . . . . . . . 27 Figure 38. TO-220 (dual gauge) drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 39. TO-220 SG (single gauge) drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 40. Tube for TO-220 (dual gauge) (mm.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 41. Tube for TO-220 (single gauge) (mm.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DocID2148 Rev 8 5/35 L78S Diagram 35 1 Diagram Figure 1. Block diagram Pin configuration L78S 6/35 DocID2148 Rev 8 2 Pin configuration Figure 2. Pin connections (top view) 􀀷􀀲􀀐􀀕􀀕􀀓 􀀪􀀪􀀵􀀵􀀲􀀲􀀸􀀸􀀱􀀱􀀧􀀧 Figure 3. Schematic diagram DocID2148 Rev 8 7/35 L78S Maximum ratings 35 3 Maximum ratings Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Table 2. Absolute maximum ratings Symbol Parameter Value Unit VI DC input voltage for VO= 5 to 18V 35 V for VO= 24V 40 IO Output current Internally limited PD Power dissipation Internally limited TSTG Storage temperature range -65 to 150 °C TOP Operating junction temperature range 0 to 150 °C Table 3. Thermal data Symbol Parameter TO-220 Unit RthJC Thermal resistance junction-case 5 °C/W RthJA Thermal resistance junction-ambient 50 °C/W Figure 4. Application circuits 􀀴 Test circuits L78S 8/35 DocID2148 Rev 8 4 Test circuits Figure 5. DC parameter 􀀴 Figure 6. Load regulation 􀀴 Figure 7. Ripple rejection 􀀴 DocID2148 Rev 8 9/35 L78S Electrical characteristics 35 5 Electrical characteristics Refer to the test circuits, TJ = 25 °C, VI = 10 V, IO = 500 mA, unless otherwise specified. Table 4. Electrical characteristics of L78S05C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage 4.8 5 5.2 V VO Output voltage IO = 1 A, VI = 7 V 4.75 5 5.25 V ΔVO Line regulation VI = 7 to 25 V 100 mV VI = 8 to 25 V 50 ΔVO Load regulation IO = 20 mA to 1.5 A 100 mV IO = 2 A 80 IQ Quiescent current 8 mA ΔIQ Quiescent current change IO = 20 mA to 1 A 0.5 mA VI = 7 to 25 V, IO = 20 mA 1.3 ΔVO/ΔT Output voltage drift IO = 5 mA, TJ = 0 °C to 70 °C -1.1 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz 40 μV SVR Supply voltage rejection f = 120 Hz 54(1) dB VI Operating input voltage IO ≤ 1 A 8 V RO Output resistance f = 1 kHz 17 mΩ Isc Short circuit current VI = 27 V 500 mA Iscp Short circuit peak current 3 A 1. Guaranteed by design. Electrical characteristics L78S 10/35 DocID2148 Rev 8 Refer to the test circuits, TJ = 25 °C, VI = 12.5 V, IO = 500 mA, unless otherwise specified. Table 5. Electrical characteristics of L78S75C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage 7.15 7.5 7.9 V VO Output voltage IO = 1 A, VI = 9.5 V 7.1 7.5 7.95 V ΔVO Line regulation VI = 9.5 to 25 V 120 mV VI = 10.5 to 20 V 60 ΔVO Load regulation IO = 20 mA to 1.5 A 140 mV IO = 2 A 100 IQ Quiescent current 8 mA ΔIQ Quiescent current change IO = 20 mA to 1 A 0.5 mA VI = 9.5 to 25 V, IO = 20 mA 1.3 ΔVO/ΔT Output voltage drift IO = 5 mA, TJ = 0 °C to 70 °C -0.8 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz 52 μV SVR Supply voltage rejection f = 120 Hz 48(1) dB VI Operating input voltage IO ≤ 1 A 10.5 V RO Output resistance f = 1 kHz 16 mΩ Isc Short circuit current VI = 27 V 500 mA Iscp Short circuit peak current 3 A 1. Guaranteed by design. DocID2148 Rev 8 11/35 L78S Electrical characteristics 35 Refer to the test circuits, TJ = 25 °C, VI = 14 V, IO = 500 mA, unless otherwise specified. Table 6. Electrical characteristics of L78S09C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage 8.65 9 9.35 V VO Output voltage IO = 1 A, VI = 11 V 8.6 9 9.4 V ΔVO Line regulation VI = 11 to 25 V 130 mV VI = 11 to 20 V 65 ΔVO Load regulation IO = 20 mA to 1.5 A 170 mV IO = 2 A 100 IQ Quiescent current 8 mA ΔIQ Quiescent current change IO = 20 mA to 1 A 0.5 mA VI = 11 to 25 V, IO = 20 mA 1.3 ΔVO/ΔT Output voltage drift IO = 5 mA, TJ = 0 °C to 70 °C -1 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz 60 μV SVR Supply voltage rejection f = 120 Hz 47(1) dB VI Operating input voltage IO ≤ 1 A 12 V RO Output resistance f = 1 kHz 17 mΩ Isc Short circuit current VI = 27 V 500 mA Iscp Short circuit peak current 3 A 1. Guaranteed by design. Electrical characteristics L78S 12/35 DocID2148 Rev 8 Refer to the test circuits, TJ = 25 °C, VI = 15 V, IO = 500 mA, unless otherwise specified. Table 7. Electrical characteristics of L78S10C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage 9.5 10 10.5 V VO Output voltage IO = 1 A, VI = 12.5 V 9.4 10 10.6 V ΔVO Line regulation VI = 12.5 to 30 V 200 mV VI = 14 to 22 V 100 ΔVO Load regulation IO = 20 mA to 1.5 A 240 mV IO = 2 A 150 IQ Quiescent current 8 mA ΔIQ Quiescent current change IO = 20 mA to 1 A 0.5 mA VI = 12.5 to 30 V, IO = 20 mA 1 ΔVO/ΔT Output voltage drift IO = 5 mA, TJ = 0 °C to 70 °C -1 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz 65 μV SVR Supply voltage rejection f = 120 Hz 47(1) dB VI Operating input voltage IO ≤ 1 A 13 V RO Output resistance f = 1 kHz 17 mΩ Isc Short circuit current VI = 27 V 500 mA Iscp Short circuit peak current 3 A 1. Guaranteed by design. DocID2148 Rev 8 13/35 L78S Electrical characteristics 35 Refer to the test circuits, TJ = 25 °C, VI = 19 V, IO = 500 mA, unless otherwise specified. Table 8. Electrical characteristics of L78S12C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage 11.5 12 12.5 V VO Output voltage IO = 1 A, VI = 14.5 V 11.4 12 12.6 V ΔVO Line regulation VI = 14.5 to 30 V 240 mV VI = 16 to 22 V 120 ΔVO Load regulation IO = 20 mA to 1.5 A 240 mV IO = 2 A 150 IQ Quiescent current 8 mA ΔIQ Quiescent current change IO = 20 mA to 1 A 0.5 mA VI = 14.5 to 30 V, IO = 20 mA 1 ΔVO/ΔT Output voltage drift IO = 5 mA, TJ = 0 °C to 70 °C -1 mV/°C eN Output noise voltage B =10 Hz to 100 kHz 75 μV SVR Supply voltage rejection f = 120 Hz 47(1) dB VI Operating input voltage IO ≤ 1 A 15 V RO Output resistance f = 1 kHz 18 mΩ Isc Short circuit current VI = 27 V 500 mA Iscp Short circuit peak current 3 A 1. Guaranteed by design. Electrical characteristics L78S 14/35 DocID2148 Rev 8 Refer to the test circuits, TJ = 25 °C, VI = 23 V, IO = 500 mA, unless otherwise specified. Table 9. Electrical characteristics of L78S15C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage 14.4 15 15.6 V VO Output voltage IO = 1 A, VI = 17.5 V 14.25 15 15.75 V ΔVO Line regulation VI = 17.5 to 30 V 300 mV VI = 20 to 26 V 150 ΔVO Load regulation IO = 20 mA to 1.5 A 300 mV IO = 2 A 150 IQ Quiescent current 8 mA ΔIQ Quiescent current change IO = 20 mA to 1 A 0.5 mA VI = 17.5 to 30 V, IO = 20 mA 1 ΔVO/ΔT Output voltage drift IO = 5 mA, TJ = 0 °C to 70 °C -1 mV/°C eN Output noise voltage B =10 Hz to 100 kHz 90 μV SVR Supply voltage rejection f = 120 Hz 46(1) dB VI Operating input voltage IO ≤ 1 A 18 V RO Output resistance f = 1 kHz 19 mΩ Isc Short circuit current VI = 27 V 500 mA Iscp Short circuit peak current 3 A 1. Guaranteed by design. DocID2148 Rev 8 15/35 L78S Electrical characteristics 35 Refer to the test circuits, TJ = 25 °C, VI = 26 V, IO = 500 mA, unless otherwise specified. Table 10. Electrical characteristics of L78S18C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage 17.1 18 18.9 V VO Output voltage IO = 1 A, VI = 20.5 V 17 18 19 V ΔVO Line regulation VI = 20.5 to 30 V 360 mV VI = 22 to 28 V 180 ΔVO Load regulation IO = 20 mA to 1.5 A 360 mV IO = 2 A 200 IQ Quiescent current 8 mA ΔIQ Quiescent current change IO = 20 mA to 1 A 0.5 mA VI = 20.5 to 30 V, IO = 20 mA 1 ΔVO/ΔT Output voltage drift IO = 5 mA, TJ = 0 °C to 70 °C -1 mV/°C eN Output noise voltage B =10 Hz to 100 kHz 110 μV SVR Supply voltage rejection f = 120 Hz 43(1) dB VI Operating input voltage IO ≤ 1 A 21 V RO Output resistance f = 1 kHz 22 mΩ Isc Short circuit current VI = 27 V 500 mA Iscp Short circuit peak current 3 A 1. Guaranteed by design. Electrical characteristics L78S 16/35 DocID2148 Rev 8 Refer to the test circuits, TJ = 25 °C, VI = 33 V, IO = 500 mA, unless otherwise specified. Table 11. Electrical characteristics of L78S24C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage 23 24 25 V VO Output voltage IO = 1 A, VI = 27 V 22.8 24 25.2 V ΔVO Line regulation VI = 27 to 38 V 480 mV VI = 30 to 36 V 240 ΔVO Load regulation IO = 20 mA to 1.5 A 480 mV IO = 2 A 300 IQ Quiescent current 8 mA ΔIQ Quiescent current change IO = 20 mA to 1 A 0.5 mA VI = 27 to 38 V, IO = 20 mA 1 ΔVO/ΔT Output voltage drift IO = 5 mA, TJ = 0 °C to 70 °C -1.5 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz 170 μV SVR Supply voltage rejection f = 120 Hz 42(1) dB VI Operating input voltage IO ≤ 1 A 27 V RO Output resistance f = 1 kHz 28 mΩ Isc Short circuit current VI = 27 V 500 mA Iscp Short circuit peak current 3 A 1. Guaranteed by design. DocID2148 Rev 8 17/35 L78S Typical performance 35 6 Typical performance Figure 8. Dropout voltage vs. junction temperature Figure 9. Peak output current vs. input/output differential voltage Figure 10. Output impedance vs. frequency Figure 11. Output voltage vs. junction temperature Typical performance L78S 18/35 DocID2148 Rev 8 Figure 12. Supply voltage rejection vs. frequency Figure 13. Quiescent current vs. junction temperature Figure 14. Load transient response Figure 15. Line transient response Figure 16. Quiescent current vs. input voltage DocID2148 Rev 8 19/35 L78S Typical performance 35 1. Although no output capacitor is need for stability, it does improve transient response. 2. Required if regulator is located an appreciable distance from power supply filter. Figure 17. Fixed output regulator 􀀕 􀀔 Figure 18. Constant current regulator 􀀬􀀲 􀀠􀀠􀀃􀀃􀀹􀀻􀀻􀀻􀀻􀀒􀀵􀀔􀀎􀀬􀁇 􀀴 Figure 19. Circuit for increasing output voltage 􀀬􀀵􀀔 􀀃􀀘􀀃􀀬􀁇 􀀹􀀲􀀃􀀃􀀠􀀠􀀃􀀹􀀻􀀻􀀻􀀻􀀋􀀋􀀔􀀔􀀎􀀎􀀵􀀵􀀕􀀒􀀵􀀔􀀌􀀌􀀎􀀎􀀬􀁇􀀵􀀕 􀅻 􀀴 Typical performance L78S 20/35 DocID2148 Rev 8 Figure 20. Adjustable output regulator (7 to 30 V) Figure 21. 0.5 to 10 V regulator VO=VXXR4/R1 DocID2148 Rev 8 21/35 L78S Typical performance 35 Figure 22. High current voltage regulator 􀀵􀀔 􀀬􀀲􀀃􀀠􀀃􀀬􀀵􀀨􀀪􀀃􀀎􀀃􀀴􀀔􀀃􀀋􀀬􀀵􀀨􀀪􀀃􀁂􀀹􀁂􀀥􀁂􀀨􀁂􀀴􀁂􀀔􀁂􀀌 􀀹􀀥􀀨􀀴􀀔 􀀵􀀔􀀃􀀠􀀃􀁂􀁂􀁂􀁂􀁂􀁂􀁂􀁂􀁂􀁂􀁂􀁂􀁂􀁂 􀀬􀀵􀀨􀀴􀀐􀀋􀀬􀀴􀀔􀀒􀁅􀀴􀀔􀀌 􀀴 Figure 23. High output current with short circuit protection 􀀵􀀶􀀶􀀦􀀦􀀠􀀹􀀥􀀥􀀨􀀨􀀴􀀴􀀕􀀕􀀒􀀬􀀶􀀶􀀦􀀦 􀀴 Typical performance L78S 22/35 DocID2148 Rev 8 Figure 24. Tracking voltage regulator 􀀴 Figure 25. Positive and negative regulator DocID2148 Rev 8 23/35 L78S Typical performance 35 Figure 26. Negative output voltage circuit Figure 27. Switching regulator Figure 28. High input voltage circuit 􀀹􀀬􀀱􀀃􀀠􀀃􀀹􀀬􀀃􀀐􀀃􀀋􀀋􀀹􀀹􀀽􀀃􀀎􀀃􀀹􀀥􀀥􀀨􀀨􀀌 􀀴 Typical performance L78S 24/35 DocID2148 Rev 8 Figure 29. High input voltage circuit 􀀴 Figure 30. High output voltage regulator 􀀴 Figure 31. High input and output voltage 􀀹􀀲􀀃􀀠􀀃􀀹􀀻􀀻􀀻􀀻􀀃􀀎􀀃􀀹􀀽􀀔 􀀴 DocID2148 Rev 8 25/35 L78S Typical performance 35 Figure 32. Reducing power dissipation with dropping resistor 􀀹􀀹 􀀐􀀐􀀹􀀹 􀀐􀀹 􀀵􀀃􀀠􀀃􀁂􀁂􀀬􀀬􀁂􀁂􀀋􀀋􀁐􀁐􀁂􀁂􀁂􀁌􀁌􀁑􀁑􀁂􀁂􀀌􀀌 􀁂􀁂􀁂􀁂􀀻􀀻􀁂􀀻􀀻􀁂􀁂􀁂􀁂􀁂􀀧􀁂􀁂􀀵􀁂􀁂􀀲􀁂􀁂􀀳􀁂􀀋􀀋􀁐􀁐􀁂􀁂􀁄􀁄􀁂􀁂􀁛􀁛􀁂􀀌􀁂 􀀬􀀲􀀋􀁐􀁄􀁛􀁛􀀌􀀌􀀎􀀬􀁇􀀋􀀋􀁐􀁐􀁄􀁄􀁛􀁛􀀌􀀌 􀀴 Figure 33. Remote shutdown 􀀴 Typical performance L78S 26/35 DocID2148 Rev 8 Note: The circuit performs well up to 100 kHz. Note: Q2 is connected as a diode in order to compensate the variation of the Q1 VBE with the temperature. C allows a slow rise time of the VO. Figure 34. Power AM modulator (unity voltage gain, IO ≤ 1 A) 􀀴 Figure 35. Adjustable output voltage with temperature compensation 􀀹􀀲􀀃􀀠􀀃􀀹􀀻􀀻􀀃􀀋􀀔􀀎􀀵􀀕􀀒􀀵􀀔􀀌􀀃􀀎􀀃􀀹􀀥􀀨 􀀴 DocID2148 Rev 8 27/35 L78S Typical performance 35 1. Application with high capacitance loads and an output voltage greater than 6 volts need an external diode (see Figure 30 on page 24) to protect the device against input short circuit. In this case the input voltage falls rapidly while the output voltage decrease slowly. The capacitance discharges by means of the Base- Emitter junction of the series pass transistor in the regulator. If the energy is sufficiently high, the transistor may be destroyed. The external diode by-passes the current from the IC to ground. Figure 36. Light controllers (VOmin = VXX + VBE) 􀀹􀀲􀀃􀁕􀁌􀁖􀁈􀁖􀀃􀁚􀁋􀁈􀁑􀀃􀁗􀁋􀁈􀀃􀁏􀁌􀁊􀁋􀁗􀀃􀁊􀁒􀁈􀁖􀀃􀁘􀁓 􀀹􀀲􀀃􀁉􀁄􀁏􀁏􀁖􀀃􀁚􀁋􀁈􀁑􀀃􀁗􀁋􀁈􀀃􀁏􀁌􀁊􀁋􀁗􀀃􀁊􀁒􀁈􀁖􀀃􀁘􀁓 Figure 37. Protection against input short-circuit with high capacitance loads 􀀴 Package mechanical data L78S 28/35 DocID2148 Rev 8 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID2148 Rev 8 29/35 L78S Package mechanical data 35 Figure 38. TO-220 (dual gauge) drawing 􀀓􀀓􀀔􀀘􀀜􀀛􀀛􀁂􀁗􀁜􀁓􀁈􀀤􀁂􀀵􀁈􀁙􀁂􀀷 Package mechanical data L78S 30/35 DocID2148 Rev 8 Table 12. TO-220 (dual gauge) mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.70 c 0.48 0.70 D 15.25 15.75 D1 1.27 E 10 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13 14 L1 3.50 3.93 L20 16.40 L30 28.90 ∅P 3.75 3.85 Q 2.65 2.95 DocID2148 Rev 8 31/35 L78S Package mechanical data 35 Figure 39. TO-220 SG (single gauge) drawing 􀀛􀀔􀀚􀀗􀀙􀀕􀀚􀁂􀁕􀁈􀁙􀀧 Package mechanical data L78S 32/35 DocID2148 Rev 8 Table 13. TO-220 SG (single gauge) mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.70 c 0.48 0.70 D 15.25 15.75 E 10 10.40 e 2.40 2.70 e1 4.95 5.15 F 0.51 0.60 H1 6.20 6.60 J1 2.40 2.72 L 13 14 L1 3.50 3.93 L20 16.40 L30 28.90 ∅P 3.75 3.85 Q 2.65 2.95 DocID2148 Rev 8 33/35 L78S Packaging mechanical data 35 8 Packaging mechanical data Figure 40. Tube for TO-220 (dual gauge) (mm.) Figure 41. Tube for TO-220 (single gauge) (mm.) Revision history L78S 34/35 DocID2148 Rev 8 9 Revision history Table 14. Document revision history Date Revision Changes 07-Sep-2006 2 Order codes updated. 20-Mar-2008 3 Added: Table 1 on page 1. 22-Mar-2010 4 Added: Table 20 on page 32, Figure 38 on page 33, Figure 39 on page 34, Figure 40 and Figure 41 on page 33. 08-Feb-2012 5 Added: order codes L78S05CV-DG, L78S12CV-DG and L78S15CV-DG Table 13 on page 35. 09-Mar-2012 6 Added: order codes L78S09CV-DG Table 13 on page 35. 15-May-2012 7 Added: order codes L78S75CV-DG and L78S10CV-DG Table 13 on page 35. 10-Mar-2014 8 Part numbers L78Sxx and L78SxxC changed to L78S. Modified the title, the features and the description in cover page. Removed TO-3 package. Updated Table 1: Device summary, Section 2: Pin configuration, Section 3: Maximum ratings, Section 4: Test circuits, Section 5: Electrical characteristics,Section 6: Typical performance, Section 7: Package mechanical data, Section 9: Order codes. Added Section 8: Packaging mechanical data. Minor text changes. DocID2148 Rev 8 35/35 L78S 35 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2014 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com BD6xxx Complementary power Darlington transistors Features ■ Good hFE linearity ■ High fT frequency ■ Monolithic Darlington configuration with integrated antiparallel collector-emitter diode Applications ■ Linear and switching industrial equipment Description The devices are manufactured in planar base island technology with monolithic Darlington configuration. . Figure 1. Internal schematic diagram SOT-32 3 2 1 R1 typ.= 15 KΩ R2 typ.= 100 Ω Table 1. Device summary Order codes Marking Package Packaging BD677 BD677 SOT-32 Tube BD677A BD677A BD678 BD678 BD678A BD678A BD679 BD679 BD679A BD679A BD680 BD680 BD680A BD680A BD681 BD681 BD682 BD682 www.st.com Contents BD6xxx 2/12 Contents 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Typical characteristic (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 BD6xxx Absolute maximum ratings 3/12 1 Absolute maximum ratings Note: For PNP types voltage and current values are negative Table 2. Absolute maximum ratings Symbol Parameter Value Unit NPN BD677 BD677A BD679 BD679A BD681 PNP BD678 BD678A BD680 BD680A BD682 VCBO Collector-base voltage (IE = 0) 60 80 100 V VCEO Collector-emitter voltage (IB = 0) VEBO Emitte-base voltage (IC = 0) 5 V IC Collector current 4 A ICM Collector peak current 6 A IB Base current 0.1 A PTOT Total dissipation at Tcase = 25°C 40 W Tstg Storage temperature -65 to 150 °C TJ Max. operating junction temperature 150 °C Electrical characteristics BD6xxx 4/12 2 Electrical characteristics (Tcase = 25°C; unless otherwise specified) Table 3. Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit ICEO Collector cut-off current (IB = 0) VCE = half rated VCEO 0.5 mA ICBO Collector cut-off current (IE = 0) VCE = rated VCBO VCE = rated VCBO Tc = 100 °C 0.2 2 mA IEBO Emitter cut-off current (IC = 0) VEB = 5 V 2 mA VCEO(sus) (1) Collector-emitter sustaining voltage (IB = 0) for BD677, BD677A, BD678, BD678A IC = 50 mA 60 V for BD679, BD679A, BD680, BD680A IC = 50 mA 80 for BD681, BD682 IC = 50 mA 100 VCE(sat) (1) Collector-emitter saturation voltage for BD677, BD678, BD679, BD680, BD681, BD682 IC = 1.5 A IB = 30 mA 2.5 V for BD677A, BD678A, BD679A, BD680A IC = 2 A IB = 40 mA 2.8 VBE (1) Base-emitter voltage for BD677, BD678, BD679, BD680, BD681, BD682 IC = 1.5 A ___ VCE = 3 V 2.5 V for BD677A, BD678A, BD679A, BD680A IC = 2 A VCE = 3 V BD6xxx Electrical characteristics 5/12 Note: For PNP types voltage e current values are negative. hFE (1) DC current gain for BD677, BD678, BD679, BD680, BD681, BD682 IC = 1.5 A_ _ VCE = 3 V 750 for BD677A, BD678A, BD679A, BD680A IC = 2 A_ _ VCE = 3 V 1. Pulsed duration = 300 ms, duty cycle ≥1.5%. Table 3. Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit Electrical characteristics BD6xxx 6/12 2.1 Typical characteristic (curves) Figure 2. DC current gain (NPN) Figure 3. DC current gain (PNP) Figure 4. DC current gain (NPN) Figure 5. DC current gain (PNP) Figure 6. Collector-emitter saturation voltage (NPN) Figure 7. Collector-emitter saturation voltage (PNP) BD6xxx Electrical characteristics 7/12 Figure 8. Base-emitter saturation voltage (NPN) Figure 9. Base-emitter saturation voltage (PNP) Figure 10. Base-emitter voltage (NPN) Figure 11. Base-emitter voltage (PNP) Figure 12. Resistive load switching time (NPN, on) Figure 13. Resistive load switching time (PNP, on) Electrical characteristics BD6xxx 8/12 2.2 Test circuit Note: For PNP types voltage e current values are negative. Figure 14. Resistive load switching time (NPN, off) Figure 15. Resistive load switching time (PNP, off) Figure 16. Resistive load switching test circuit 1) Fast electronic switch 2) Non-inductive resistor BD6xxx Package mechanical data 9/12 3 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com Package mechanical data BD6xxx 10/12 BD6xxx Revision history 11/12 4 Revision history Table 4. Document revision history Date Revision Changes 21-Jun-2004 4 14-Jan-2008 5 1. Technology change from epybase to planar. 2. Updated Section 2.1: Typical characteristic (curves) on page 6 3. Content reworked to improve readability. BD6xxx 12/12 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com This is information on a product in full production. August 2013 DocID13587 Rev 16 1/105 STM32F103x8 STM32F103xB Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces Datasheet - production data Features  ARM 32-bit Cortex™-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM  Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage detector (PVD) – 4-to-16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC – PLL for CPU clock – 32 kHz oscillator for RTC with calibration  Low power – Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers  2 x 12-bit, 1 μs A/D converters (up to 16 channels) – Conversion range: 0 to 3.6 V – Dual-sample and hold capability – Temperature sensor  DMA – 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs  Up to 80 fast I/O ports – 26/37/51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant  Debug mode – Serial wire debug (SWD) & JTAG interfaces  7 timers – Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input – 16-bit, motor control PWM timer with deadtime generation and emergency stop – 2 watchdog timers (Independent and Window) – SysTick timer 24-bit downcounter  Up to 9 communication interfaces – Up to 2 x I2C interfaces (SMBus/PMBus) – Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to 2 SPIs (18 Mbit/s) – CAN interface (2.0B Active) – USB 2.0 full-speed interface  CRC calculation unit, 96-bit unique ID  Packages are ECOPACK® Table 1. Device summary Reference Part number STM32F103x8 STM32F103C8, STM32F103R8 STM32F103V8, STM32F103T8 STM32F103xB STM32F103RB STM32F103VB, STM32F103CB, STM32F103TB BGA100 10 × 10 mm UFBGA100 7 x 7 mm BGA64 5 × 5 mm VFQFPN36 6 × 6 mm LQFP100 14 × 14 mm LQFP64 10 × 10 mm LQFP48 7 × 7 mm UFQFPN48 7 × 7 mm www.st.com 2012-2013 Dremel Experts: US: 1 (800) 437-3635 Canada: 1 (888) 285-3476 www.dremel.com The M akers o f Scan this code with your phone for product information, videos, and more. Do you like to: REA D Visit Dremel.com and get tips and tricks on projects and products. Plus visit our message board or sign up for our monthly eblast for news on new product introductions. TALK Join the conversation on Facebook at facebook.com/Dremel. BE INSPIRE D Sign up for weekly project inspiration at DremelWeekends.com. SHARE Pin Dremel projects and ideas on Pinterest. STAY UP-TO-DATE Get the latest news from Dremel. Follow us on Twitter, username @Dremel. ROTARY TOOLS Corded.. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Cordless.. . . . . . . . . . . . . . . . . . . . . . . 13-20 At tachments.. . . . . . . . . . . . . . . . . 21-26 Accessories.. . . . . . . . . . . . . . . . . . 27-42 OSCILLATING TOOLS Mul t i-Max™ Corded.. . . . . . 43-48 Mul t i-Max™ Cordless.. . . . 49-50 Accessories.. . . . . . . . . . . . . . . . . . 51-54 At tachments.. . . . . . . . . . . . . . . . . . . . . 54 SPECIALTY TOOLS Saw-Max™ System. . . . . . . . 55-60 Trio™ System.. . . . . . . . . . . . . . . . 61-66 VersaTip™ and Accessories.. . . . . . . . . . . . . . . . . . . . . . 67 Engraver and Accessories.. . . . . . . . . . . . . . . . . . . . . . 67 V ersatile Tool Systems™ INDEX Customer Support A well-prepared staff of Dremel Experts is available to answer questions about our tools. With over 650 total years of combined work experience, the Dremel Experts are ready to serve you. Call: 1-800-4-DREMEL (1-800-437-3635) USA. 1-888-285-3476 CANADA. Cal l for Your Free Dremel DVD 1(800) 437-3635 1 The Makers of Versatile Tool Systems™ ROTARY TOOLS 2 What Is a Rotary Tool ? Rotary tools are hand held power tools that use high-speed and low torque to undertake a variety of useful tasks with control and precision. Since AJ Dremel invented the first rotary tool over 80 years ago, no other brand has worked harder to bring users a more complete and innovative system of rotary tools, accessories and attachments. Over the years Dremel rotary tools have become the gold standard in versatility, performance, and quality by which all other rotary tools are judged. 3 4200, 4000, 8220 3000, 8100 ROTARY TOOL OVERVIEW CORDED VERSATILITY METER Model 4200 4000 3000 200 SERIES 100 SERIES Amps 1.6 1.6 1.2 1.15 1.15 Speed Range [RPM] 5,000— 35,000 5,000— 35,000 5,000— 32,000 15,000 and 35,000 35,000 Versatility Level High High Intermediate Basic + Basic Electronic Feedback Control Yes Yes No No No Number of Speeds Variable Variable Variable 2 1 Soft Grip Yes Yes Yes No No Separate On/Off Speed Control Yes Yes No No No Accessory Change System EZ Change™ EZ Twist™ Nose Cap EZ Twist™ Nose Cap Wrench Wrench Weight [oz.] 25 22.5 20.0 18.0 18.0 Warranty 2 year 2 year 2 year 2 year 2 year High Intermediate Models: Models: Premium Rotary Tools, able t o perform the wide st range o f applications. High Performance Rotary Tools, able to tackle a wider r ange of applications. 4 200 SERIES, STYLUS, 7700 100 SERIES, 7300 ROTARY TOOL OVERVIEW CORDLESS Model 8220 8100 STYLUS™ 7700 7300 Voltage 12Vmax 8Vmax 7.2 7.2 4.8 Battery Type Lithium Ion Lithium Ion Lithium Ion Ni-Cd Ni-Cd Speed Range [RPM] 5,000— 30,000 5,000— 30,000 5,000— 25,000 10,000 and 20,000 6,500 and 13,000 Versatility Level High Intermediate Basic + Basic + Basic Electronic Feedback Control No No No No No Number of Speeds Variable Variable Variable 2 2 Soft Grip Yes Yes Yes No No Separate On/Off Speed Control Yes Yes Yes No No Accessory Change System EZ Twist™ Nose Cap EZ Twist™ Nose Cap Wrench Wrench Wrench Weight [oz.] 22.0 14.0 9.0 12.0 9.0 Warranty 2 year 2 year 2 year 2 year 2 year Basic + Basic Models: Models: Enhanced Level Rotary Tools, with improved control across multiple applications. Entry Level Rotary Tools, ideal for precision applications. 5 1 2 3 NEW! PULL INSERT SECURE Integrated EZ Change™ For the fastest and easiest accessory change. Patented pull lever system Means you'll never need to look for the wrench again. Variable Speed For maximum accessory versatility and precise tool control. Electronic Feedback Auto adjusts power and speed as needed. Can be used with all Dremel accessories and attachments except MS400 and PL400 attachments.* High-Performance Motor For maximum performance at all speeds. Separate On/Off Switch Retains speed setting for ease of use. Increased power and air flow For cooler operation. Limited Warranty CORDED ROTARY TOOLS Versatility * Attachment models 225, 575 and 670 are compatible with the 4200 when used with the 4200 Attachment Adapter found in your Dremel 4200 kit. 6 EZC480 EZC481 EZC482 EZC483 • 4200 High Performance Rotary Tool, Circle Cutter, Safety Shield, Cutting Guide, Lawn Mower Sharpener, Lawn Mower and Garden Tool Sharpener, Sanding/Grinding Guide, Detailers Grip • Storage Case, Accessory Case, Product Reference Sheet, Adapter/Drive Coupling 40 ASSORTED ACCESSORIES Carving/Engraving - 107, 191 Grinding/Sharpening - 932, 8193, 84922 Cutting - EZ409, EZ456, 561 Cleaning/Polishing - 403, 428 Sanding - EZ407, 408 (x6), EZ411 (x3) EZ412 (x3), EZ413 (x3), 432 (x6), 445 (x6) Miscellaneous - 150, EZ402 4200 KIT 4200 - 6/40 The following 4200-specific collets are available for purchase. Call 1-800-4-DREMEL for more information. 2615001034 – EZC480 2615001035 – EZC481 2615001036 – EZC482 2615001037 – EZC483 1/8" 3/32" 1/16" 1/32" 3,2 mm 2,4 mm 1,6 mm 0,8 mm 4200 COLLETS 7 Electronic Feedback Auto adjusts power and speed as needed. EZ Twist™ Nose Cap Wrench for fast accessory changes. Variable Speed For maximum accessory versatility and precise tool control. Can be used with all Dremel accessories and attachments. Does it All, Better.™ Limited Warranty Versatility CORDED ROTARY TOOLS High-Performance Motor For maximum performance at all speeds. Separate On/Off Switch Retains speed setting for ease of use.