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Farnell PDF
Schroff-A1086CHSCFG - Farnell Element 14
Schroff-A1086CHSCFG - Farnell Element 14
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Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
![[TXT]](http://www.audentia-gestion.fr/icons/text.gif)
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Electronics Packaging www.schroff.biz UK 04/2006 9.3
Power supplies– 19" compatible – AC/DC switched-mode power supply
11396002
DIJM0084
Connector pin-out
19" compatible – AC/DC switched-mode power supply
Wide range mains/line input voltage (from 90 – 264 VAC and
130 – 340 VDC)
Single output voltage
Redundancy operation with integrated decoupling diode
Active Current Share Bus (CSB)
Signalling: Output voltage OK
Efficiency up to 80%
Delivery comprises
Order Information
Note
Please order front panel separately
Output data at Ta= 0 ... 50 °C
Further accessories, see page 9.21
Single, 50 W ecopower
Pin Connection
4 Output + V1
6 Output + V1
8 Sense line + V1
10 Sense line 0 V1
12 Output 0 V1
14 Output 0 V1
16 -
18 -
20 -
22 CSB
24 Output OK
26 -
28 L
30 N
32 PE
Qty Description
1 19" compatible power supply
height 3 U
width A: 6 HP
depth 171.93 mm (160 mm deep boards)
connector H15M (assembled)
keying/coding peg (assembled)
Voltage Current Power Description Order no.
V A W
5 9 45 SEK 105 13100-043
12 4.2 51 SEK 112 13100-044
15 3.4 51 SEK 115 13100-041
24 2.1 51 SEK 124 13100-045
48 1.1 53 SEK 148 13100-046
Front panel 6 HP, Al, front anodised, rear colourless
chromated, with vertical slots for EMC contact strips,
incl. assembly kit, 1 piece
21006-943
EMC contact strips Stainless steel, 2 pieces per front
panel necessary, PU 10 pieces
21101-705
Connector H 15 F FASTON connection, 1 piece 69001-733
Coding PU (keying/coding peg, 1 piece, keying/coding pin
2 pieces)
60800-123
For further information www.schroff.biz/oneclick
oneClick code = Order no.
6
1
2
3
4
5
7
TE = HP = F
Aufbau / Exploded diagram / Montage
ELA44928
Maßbilder / Dimensions / Dimensions
DIJM0001
Fühlerleitungbetrieb (Last)
Die Fühlerleitungen werden polrichtig
direkt an der Last angeschlossen. Die
Leitungen müssen verdrillt oder abgeschirmt
sein (Schirm mit PE verbinden).
Für optimale Störspannungsunterdrückung
sollte negative Ausgangsleitung
mit Schutzleiter (PE, Pin
32) verbunden werden.
Fühlerleitungbetrieb (lokal)
Die Senseanschlüsse werden polrichtig
direkt am Power Supply gebrückt.
Betrieb ohne Fühlerleitung
Fühlerleitungsanschlüsse sind intern
mit einem Widerstand verbunden;
ohne Fühlerleitungsanschluß wird die
Ausgangsspannung ca. auf Nennspannung
geregelt.
Operation with sense lines
(load)
The sense lines are connected directly
to the load with the correct polarity.
The lines must be twisted or screened
(connect screen with PE). For optimum
interference suppression, the negative
output should be connected to the protective
GND/earth (PE, pin 32).
Operation with sense lines
(local)
The sense connections are bridged
directly to the power supply with the
correct polarity.
Operation without sense lines
Sense connections are connected
internally with a resistor; without sense
connection the output voltage is
approx. the same as the nominal
voltage.
Utilisation avec lignes de
compensation (charge)
Les lignes de compensation doivent être
raccordées directement à la charge en
respectant la correspondance des
polarités. Elles doivent être torsadées ou
blindées (raccorder le blindage au
conducteur de protection PE). Pour
obtenir une neutralisation optimale des
tensions parasites , la ligne négative
devrait être reliée au conducteur de
protection (PE, broche 32).
Utilisation avec lignes de
compensation (local)
Les lignes de compensation doivent être
pontées directement en sortie
d´alimentation en respectant la
correspondance des polarités.
Utilisation sans lignes de
compensation
Les raccordements des lignes de
compensation sont pontées dans
l´alimentation à l´aide d´une résistance.
Lorsque les lignes de compensation ne
sont pas raccordées en externe, la
tension de sortie est régulée
approximativement à la valeur nominale.
Pos.
Item
Repère
Benennung
Description
Désignation
Bestell-Nr.
Order No.
Référence
1
Netzgerät, Teileinsatz 3 HE nach DIN 41494, Teil 5
Power Supply, Plug-in unit 3 U to DIN 41494, part 5
Alimentation, Module enfichable 3 U, selon DIN 41494 partie 5
2
Steckverbinder Messerleiste
Male connector
Connecteur mâle
H 15 M, DIN 41612
3
Codierleiste, Kammleiste
Coding strip, Female strip
Détrompeur, Peigne
4
Steckverbinder-Gegenstück
Female connector
Connecteur femelle
69001-733
5
Codierleisten-Gegenstück
Coding strip
Réceptacle détrompeur
60800-123
6
HF Frontplatte (seitlich geschlitzt) mit Befestigungsmaterial
Front panel with slots incl. assembly parts
Face avant HF (avec fentes latérales) et pièces de fixation
21006-943
7
Sicherung
Fuse
Fusible secteur
Power
LED grün, versorgt durch die Ausgangsspannung
LED green, supplied by the ouput voltage
LED verte, alimentée par tension de sortie
D V
Einstellung der Ausgangsspannung V
Adjustment of the output voltages V
Réglage tensions de sortie V
Prinzipschaltbild, Steckerbelegung / Circuit diagram, Connector pin-out / Schéma de principe, Brochage
DIJM0002
PSU
+ Sense
- Sense
- V
+ V
12,14
4,6
8
10
R
C
+
PSU
+ Sense
- Sense
- V
+ V
12,14
4,6
8
10
R
DIJM0057
Uup Udown Hyst. typ.
SEK 105 4,6 ±0,2 V 4,5 ±0,2 V 60 mV
SEK 112 11,0 ±0,2 V 10,9 ±0,2 V 200 mV
SEK 115 13,9 ±0,2 V 13,7 ±0,2 V 200 mV
SEK 124 23 ±0,3 V 22,8 ±0,3 V 300 mV
SEK 148 46,9 ±0,4 V 45,5 ±0,4 V 600 mV
Rpullup
SEK 105 470 h
SEK 112 1k6 h
SEK 115 1k6 h
SEK 124 4k7 h
SEK 148 20k h
+
-
+
-
PSU 2
PSU 1
+
-
RL
V1
V1
Leistungsbegrenzung
Zum Schutz des Gerätes müssen die
maximalen Ausgangsströme mit steigender
Temperatur reduziert werden.
Das Derating setzt bei 50 °C ein.
Strombegrenzung
Die Geräte sind für Dauerkurzschluß
ausgelegt. Der Ausgangsstrom wird
gemäß einer I/U-Kennlinie begrenzt.
Wird die Ausgangsspannung vom
Anwender erhöht, muß er sicherstellen,
daß der maximale Ausgangstrom um
den gleichen Faktor verringert wird.
Das Netzgerät kann sonst zerstört werden.
Beispiel: UDC + 10 % => IDC - 10 %.
Überspannungsschutz
Der OVP ist werkseitig eingestellt
(siehe technische Daten). Beim
Ansprechen des Überspannungschutzes
wird der Regler abgeschaltet.
Wenn die Überspannung nicht mehr
ansteht schaltet sich das Netzgerät
wieder ein.
Serienschaltung
Sehen Sie am Ausgang externe Inversdioden
vor. Summenspannung von
200 V nicht überschreiten. Spricht bei
einem Gerät die Strombegrenzung an,
muß die Last kurz abgetrennt werden.
Bei Serienschaltung können am Ausgang
berührungsgefährliche Spannungen
auftreten:
SELV-Spannung nur bis 60 VDC.
Parallelschaltung
Zur Leistungserhöhung oder Redundanzbetrieb
werden die Ausgänge der
Netzgeräte parallel verbunden. Es
erfolgt eine geregelte Lastaufteilung
wenn der Current Share Bus der Netzgeräte
miteinander verbunden ist (Pin
22, max. 12 Geräte parallelschaltbar,
max. Ausgangsleistung ca. 0.9*Pmax.).
Damit im Redundanzbetrieb alle Netzgeräte
arbeiten ist eine Grundlast von
0,1*Pmax erforderlich.
Die Entkoppeldiode ist eingebaut.
Netzspannung
Die Power Supplies haben einen Weitbereichseingang
(90 VAC – 264 VAC,
130 VDC – 340 VDC).
Output OK Signal
Das Output OK Signal zeigt an, ob die
Ausgangsspannung vorhanden ist
(siehe Diagramm Output OK Signal).
Der Pullup Widerstand ist eingebaut.
Output power Limiting
In order to protect the unit the maximum
output currents reduced as the
temperature increases. Derating is
activated at 50 °C.
Current limiting
The power supply features short-circuit
protection. The output current is limited
according to an I/V curve. If the output
voltage is increased by the user, the
maximum output current must be
reduced by the same factor. The power
supply may otherwise be destroyed.
Example: VDC + 10 % => IDC - 10 %.
Over-voltage protection
The OVP is pre-set (see technical data).
When the over-voltage protection is
triggered the regulator is switched off.
The unit is automatically reset when
there is no longer any over-voltage.
Series operation
External inverse diodes should be used
at the output. Do not exceed a total
voltage of 200 V. If the current limiting is
triggered in a unit the load should be
removed briefly. Dangerous voltages
may occur at the output with series
operation:
SELV voltage only up to 60 VDC.
Parallel operation
The unit outputs are set up for parallel
operation to increase the output power
or for redundancy. The load share
control operates if the Current Share
Buses of the unit are linked together(Pin
22 max 12 units). max. output
performance approx. 0.9*Pmax. So that
all power supplies work in redundancy
mode, a basic load of 0.1*Pmax is
required.
The decoupling diode is built in.
Mains/line voltage
The power supplies have a broad
range input (90 VAC – 264 VAC, 130 VDC
– 340 VDC).
Output OK Signal
The Output OK Signal is on if there is an
existing output voltage(see diagram
Output OK Signal).
The pullup resistor is build in.
Limitation de puissance
Afin de protéger l’alimentation, les
courants de sortie max. diminuent á
mesure que la température augmente.
Le derating démarre à 50 °C.
Limitation de courant
Les alimentations sont conçues pour
pouvoir supporter un court-circuit
permanent. Le courant des sortie est
régulé selon une courbe caractéristique
I/V. Si l’utilisateur accroît la tension de
sortie, il doit veiller à réduire le courant
maximal de sortie dans la même
proportion, sinon l’alimentation risque
d’être détériorée.
Exemple: UDC + 10 % => IDC - 10 %.
Protection aux surtensions
L’OVP est prérèglé en usine (voir
Caractéristiques Techniques). Dans le
cas du déclenchement de la protection
aux surtensions, l’alimentation est
arrêtée. Lorsque la surtension disparait,
l’alimentation se remet en marche.
Branchement en série
Il faut prévoir des diodes de protection
contre les inversions de polarité. Ne pas
dépasser la tension totale de 200 V.
Lorsque l’un des appareils déclenche en
limitation de courant, il faut déconnecter la
charge pendant un court moment. Lors
d’une mise en série, des tensions
dangereuse peuvent apparaître à la
sortie:
tension SELV uniquement jusqu’à 60 VDC.
Branchement en parallèle
Pour accroitre la puissance ou pour une
utilisation en redondance des
alimentations les sorties seront reliées en
parallèle. Une répartition autonome de la
charge est assurée lorsque les sorties
Current Share Bus des alimentations sont
reliées entre elles (broche 22, max. 12
alimentations en parallèle, tension max.
de sortie env. 0.9*Pmax). Pour qu’en mode
de redondance toutes les alimentations
soient en service il faut une charge
minimale de 0,1*Pmax.
La diode de découplage est intégrée.
Adaptation de la tension secteur
L´alimentation dispose d´une plage
d´entrée secteur étendue. Elle s´adapte
automatiquement à la tension secteur
(90 VAC – 264 VAC, 130 VDC – 340 VDC).
Signal Output OK
Le signal Output OK indique la présence
ou non de la tension de sortie (voir
schéma Signal Output OK). La résistante
Pullup est intégrée.
Strombegrenzung
Current limiting
Limitation de courant
Parallelschaltung (CSB)
Parallel operation
Branchement en parallèle
Serienschaltung
Series operation
Branchement en série
V [ % ]
110 I [ % ]
100
+
+ +
I
-
-
PSU 2
PSU 1
+
-
-
PSU 3
RL
CSB
1
I 2
I n
Output OK Signal
Garantiebedingungen
Leistungsdauer
Für dieses Produkt leisten wir 2 Jahre Garantie.
Der Anspruch beginnt mit dem Tage der
Auslieferung.
Umfang der Mängelbeseitigung
Innerhalb der Garantiezeit beseitigen wir kostenlos
alle Funktionsfehler am Produkt, die auf mangelhafte
Ausführung bzw. Materialfehler zurückzuführen sind.
Weitergehende Ansprüche – insbesondere für
Folgeschäden – sind ausgeschlossen.
Garantieausschluß
Schäden und Funktionsstörungen verursacht durch
Nichtbeachten unserer Bedienungsanleitung sowie
Fall, Stoß, Verschmutzung oder sonstige unsachgemäße
Behandlung fallen nicht unter die Garantieleistung.
Die Garantie erlischt, wenn das Produkt von
unbefugter Seite geöffnet wurde. Eingriffe erfolgt
sind oder die Seriennummer am Produkt verändert
oder unkenntlich gemacht wurde.
Abwicklung des Garantieanspruches
Das vorliegende Produkt wurde sorgfältig geprüft
und eingestellt.
Bei berechtigten Beanstandungen schicken Sie uns
das Produkt bitte zurück. Zur Erhaltung Ihres
Garantieanspruches beachten Sie bitte folgendes:
Legen Sie eine möglichst genaue Beschreibung
des Defektes bei.
Das Produkt ist im Original-Karton oder gleichwertiger
Verpackung einzusenden und zwar
versichert und portofrei.
Warranty conditions
Duration
This product has a warranty of 2 years.
The warranty begins on the day of delivery
Cover of defects
Within the warranty period Schroff will repair free of
charge any faulty functioning of the product
resulting from faulty design or defective material.
All other claims under the warranty are excluded, in
particular consequential damage.
Warranty exclusion
The warranty does not cover damage or functional
defects caused by non-adherence to the
Company´s operating instructions or such caused
by dropping, knocking, contamination or other
untoward handling. The warranty is invalidated if
the product is opened by unauthorized personnel,
tampered with or the serial number on the product
has been changed or rendered illegible.
Claims under warranty
This product has been carefully checked. If you
have a valid claim, please return the product to
SCHROFF. In order to make a claim under the
warranty, ensure that the following is carried out:
Include a detailed description of the fault.
The product should be returned in the original
carton or similar packaging, insured and
post paid.
Garantie
Garantie contractuelle
Les conditions d‘applications de la garantie, et en
particulier la durée, l‘étendue et les cas d‘exclusion,
figurent dans nos conditions générales de ventes,
paragraphe 11 „Garantie contractuelle“.
Application de la garantie
Cette alimentation a été soigneusement contrôlée en
usine. En cas de réclamations, veuillez nous la
retourner accompagnée d‘une description la plus
précise possible du défaut constaté, et d‘une copie du
bon de livraison ou de la facture. Le produit doit nous
être retourné dans son emballage d‘origine port
assuré et payé.
Schroff n‘assume aucune responsabilité pour des
appareils non assurés et endommagés pendant le
transport.
Technische Daten Technical Data Caractéristiques techniques SEK 105 SEK 112 SEK 115 SEK 124 SEK 148
Eingangsgrößen Input parameters Valeurs d’entée 13100 - 043 - 044 - 041 - 045 - 046
Netzspannung Nennwerte VAC Mains/line voltage Nominal values VAC Tension secteur Valeurs nominales VAC 100 – 240 VAC
Arbeitsbereiche Operating ranges Plage de fonctionnement
90 – 264 VAC
128 – 370 VDC 4)
Netznennstrom bei 90 VAC / 187 VAC Mains/line current at 90 VAC / 187 VAC Courant nominal pour 90 VAC / 187 VAC 1,3 / 0,6 A
Netzfrequenzbereich Mains/line frequency Fréquence secteur 48 – 62 Hz
Leistungsfaktor cos j Performance factor cos j Facteur de puissance cos j 0,6
Wirkungsgrad typabhängig Efficiency, depending on type Rendement selon le type 69 – 80%
Einschaltstrom IP ( bei 230 VAC ) Current at switch-on IP ( at 230 VAC ) Courant d’appel IP ( pour 230 VAC ) < 20 A
Ableitstrom Leakage current Courant de fuite £ 500 μA
Ausgangsgrößen Output parameters Valeurs de sortie
Ausgangsleistung [ W ] Output [ W ] Puissance de sortie [ W ] 45 51 53
Ausgangsspannung
D V [ V ]
werkseitig 2) Output voltage D V
[ V ]
pre-set 2) Tension de sortie D V
[ V ]
Réglage usine 2) 5 12 15 24 48
Einstellbereich 1) Adjustment range 1) Plage de réglage 1) 4,2 – 6 11 –
13,5
13,5 –
16,5
21 –
25,5
43 – 50
Ausgangsstrom
(bei 90 - 264 VAC) [ A ]
0 ... 50 °C Output current
(at 90 - 264 VAC ) [ A ]
0 ... 50 °C Courant de sortie
(et 90 - 264 VAC ) [ A ]
0 ... 50 °C 9,0 4,2 3,4 2,1 1,1
70 °C 70 °C 70 °C 6,0 2,9 2,4 1,5 0,8
Kurzschlußstrom [ A ] Short-circuit current [ A ] Courant de court-circuit [ A ] < 11 < 6 < 4,5 < 3 < 2
Überspannungsschutz OVP(schaltet Netzgerät
ab), automatisch wiederkehrend,
werkseitig fest eingestellt [ V ]
Over-voltage protection pre-set (switches
power supply off) with automatic reset [ V ]
Protection surtensions OVP (coupe l’alimentation),
remise en marche automatique [ V ]
6 ±0,3 14 ±0,5 17 ±0,5 26 ± 0,5 52 ± 2
Restwelligkeit bei
[mVPP]
100 Hz Residual ripple at
[mVPP]
100 Hz Ondulation résiduelle
[mVPP]
100 Hz < 20 < 100 < 100 < 100 < 150
Taktfrequenz
(100 kHz)
Frequency
(100 kHz)
à la fréquence de
découpage (100 kHz)
< 40 < 50 < 50 < 50 < 60
Störspannung (BW: 100 MHz) [mVPP] Interference voltage (BW: 100 MHz) [mVPP] Tension parasite (BP: 100 MHz) [mVPP] < 100 < 200 < 200 < 200 < 200
Lastausregelung, statisch
( Lastwechsel 0 - 100 % ) [mV]
Load control, static
( load change 0 - 100 % ) [mV]
Régulation en charge statique
( variation charge 0 - 100 % ) [mV]
< 50 < 50 < 50 < 100 < 100
Netzausregelung 90 – 264 V [mV] Mains voltage change 90 – 264 V [mV] Régulation secteur 90 – 264 V [mV] < 10 < 25 < 25 < 100 < 100
Temperaturkoeffizient Temperature coefficient Coefficient de température - 0,015 %/K
CSB und Ausgang über Diode entkoppelt CSB and output via decoupling diode CSB et Sortie découpling par diode eingebaut / built in / monté
Dynamische Regelabweichungen
(Lastwechsel: 50 ... 100% mit 100 Hz;
dI/dt = 0,135 A/μs)
Dynamic control deviations
(Load change: 50 ... 100% at 100 Hz;
dI/dt = 0.135 A/μs)
Valeurs dynamiques de sortie
(Variation de charge: 50 ... 100% avec 100 Hz;
dI/dt = 0,135 A/μs)
Gesamtausregelzeit,
Toleranz 0,1% x V1 Nenn [ms]
Total control time,
Tolerance 0,1 % x V1 nom [ms]
Temps de réponse globall,
Tolérance 0,1% x V1 Nenn [ms]
< 1,5
Überschwingweite und Unterschwingweite
[ mV ]
Overshoot and undershoot [ mV ] Amplitude de dépassement et amplitude
négative [ mV ]
< 500 < 250 < 300 < 500
Schutz- und
Überwachungseinrichtungen
Protection and
control features
Dispositifs de protection
et surveillance
Einschaltzeit Soft start delay Temps de montée < 0,8 s
Netzsicherung, High Breaking träge Mains/line fuse, high breaking slow Fusible secteur, high breaking slow 4 A/250 VAC, 5 x 20 mm, DIN EN60127-2/V4)
Netzausfallüberbrückung bei
VAC = 187 VAC und 100 % Last
Mains/line failure buffer at
VAC = 187 VAC and 100 % load
Pontage microcoupures secteur avec
VAC = 187 VAC et charge 100 %
> 30 ms
Fernfühler kompensiert Remote control compensated Compensation max. 0,5 V
Strombegrenzungskennlinie Current limiting Limitation de courant U / I , V / I
Signalisierung „Ausgangsspannung ok“ “Output OK“ Signal Signalisation «tension de sortie OK» Output OK, low active, internal pull-up
max. 55 V / 50 mA
High Pegel [ V ] High Level [ V ] High signal [ V ] 5 12 15 24 48
Prüf- und Umweltbedingungen Test and environmental specifications Conditions de test et d’environnement
Klimaprüfung nach Climatic test to Epreuve climatique selon IEC 68-2-38
Schock- und Vibrationstest gemäß
Beschleunigung 2 g
Shock and vibration tests in accordance
Acceleration 2 g
Tests de chocs et vibrations selon
Accélération 2 g
EN 60068-2-6
Höhe 3 HE / Tiefe 160 mm / Breite [TE] Hight 3 U / depth 160mm / Width [HP] Hauteur 3 U / Prof. 160 mm, Largeur [F] 6
Gewicht (Masse) Weight Poids (masse) 0,55 kg
CE Störaussendung CE Transmission Compatibilité
électromagnétique
CE
Emission EN 50081-1
EN 55011class B, EN 55022 class B
Störfestigkeit,
Schärfeklasse 3
Susceptability,
degree of severity 3
CEM Immunité,
sévérity 3
EN 50082-2, EN 61000-4-2,EN 61000-4-3,
EN 61000-4-4 ,EN 61000-4-5, EN 61000-4-6
Sicherheit,
Schutzklasse 1
Safety,
Protection class 1
Sécurité,
Classe de protection 1
EN 60950 ( ERG )
Hochspannungsprüfung
nach EN 60950
Eingang-Ausgang High voltage test
to EN 60950
input-output Tests haute-tension
selon EN 60950
Entrée-Sortie 4,3 kVDC 3)
Eingang-PE input-PE Entrée-Masse 2,2 kVDC 3)
Ausgang-PE output-PE Sortie-Masse 0,7 kVDC 3)
UL 1950 UL 1950 UL 1950 No. E 153809
Netzgerät wartungsfrei Power supply, maintenance-free Alimentation sans entretien Ja / yes / oui
Kühlart Cooling Refroidissement Convection
Umgebungstemperatur Betrieb / Lagerung Ambient temperature Operation / Storage Température ambiante Service / Stockage 0 ... 70 °C / -20 ... + 85 °C
MTBF bei Vollast, TU = 40 °C MTBF at full load, Ta = 40 °C MTBF à pleine charge, Ta = 40 °C 500000 h
1) Bei Erhöhung der Ausgangsspannung DV
Strombegrenzung beachten.
2) Toleranz ± 100 mV.
3) ACHTUNG: Hochspannungsprüfung wurde durchgeführt.
Bei erneuter Prüfung darf max. 80% der Prüfspannung
angelegt werden. Bei unsachgemäßer
Prüfung (z.B. manche Bauteile müssen kurzgeschlossen
werden) kann das Gerät zerstört werden.
4) Für den DC-Betrieb ist eine geeignete Sicherung vorzuschalten,
zB. von Wickmann 19356 T 3,15 A
1) When increasing the output voltage DV check the
current limiting.
2) Tolerance ± 100 mV.
3) CAUTION: The high voltage test has been carried
out. Any repeat test must be carried out at max. 80%
of the test voltage. If the test is carried out incorrectly
(e.g. some components have to be short-circuited),
the unit may be destroyed.
4) For DC-operation you must put an additional fuse in
front, e.g. from Wickmann 19356 T 3,15 A
1) Lorsqu’on augmente la tension de sortie DV
il faut tenir compte de la limitation de courant.
2) Tolérance ± 100 mV.
3) ATTENTION: Les tests haute-tension ont été effectués.
En cas de répétition de ces tests, uniquement 80 % de
la tension d’essai peut être appliquée. En cas de tests
non appropriés (certains composants doivent être mis
en court-circuit), l’appareil peut être détruit.
5) L’utilisation d’un fusible adéquate est obligatoire pour le
fonctionnement en DC, par ex. Wickmann 19356
T 3,15 A
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Attention !
Observer les prescriptions et
règles de sécurité!
Avant la mise en service, lire la
notice d’utilisation.
Raccorder le conducteur de terre
(PE).
Si une protection contre les
contacts directs est nécessaire,
l’alimentation doit obligatoirement
être montée dans un boîtier.
L’appareil ne peut être ouvert que
par des personnes qualifiés!
La protection anti-feu est à
assurer par une enveloppe
indépendante de l’alimentation.
Consignes de sécurité
L’alimentation doit être munie d’une
face avant appropriée, afin d’éviter
tout contact avec des parties sous
tension.
Afin d’éviter les couplages parasites,
les câblages secteur et secondaires
doivent cheminer séparément.
Precautions!
Please read the safety
instructions carefully!
Please read these operating
instructions carefully before
switching on.
Connect the PE conductor before
operating.
The power supply should be
mounted in a case to avoid risk
of direct contact with live parts.
The power supply unit should be
opened by authorized service
personnel only!
Ensure correct installation for
conformity to fire regulations.
Safety instructions
To avoid interference, the mains/line
and output connections must be
physically separated from one
another.
Vorsicht!
Sicherheitsvorschriften,
-bestimmungen und -hinweise
beachten!
Vor dem Betrieb Bedienungsanleitung
lesen.
Vor dem Betrieb PE-Leiter
anschließen.
Direkter Berührschutz erfordert
unbedingt den Einbau in Gehäuse,
die das Berühren spannungsführender
Teile ausschließt.
Das Geräte darf nur von
Fachpersonal geöffnet werden!
Brandschutz ist durch das
übergeordnete Gefäßsystem
sicherzustellen
Sicherheitshinweise
Nur mit geeigneter Frontplatte
betreiben, um die Berührung
spannungsführender Teile zu
verhindern!
Um Störungseinkopplungen zu
vermeiden müssen Netz-/ und
Ausgangsleitungen getrennt verlegt
werden.
Jede Unterbrechung der Schutzleitung
innerhalb oder außerhalb
des Gerätes oder die Abkoppelung
des Schutzleiteranschlusses kann
das Gerät gefährlich machen;
absichtliche Unterbrechung ist
untersagt!
Vor dem Sicherungswechsel
Gerät vom Netz trennen.
Die Geräte sind werkseitig nur
einpolig abgesichert. Bei Netzanschluß
mit polverwechselbaren
Steckvorrichtungen ist eine zweite
Sicherung vorzusehen.
Durch Serienschaltung (Reihenschaltung)
mehrerer Stromversorgungen
können an den Ausgängen
lebensgefährliche Spannungen
(ab 60 VDC) auftreten
(SELV-Spannung nur bis 60 VDC)!
Beim Einbau des Gerätes Sicherheitsmaßnahmen
nach EN 60950
beachten!
Allgemeine Sicherheitsvorschriften
und -bestimmungen beachten!
Operate only with suitable front
panel to avoid contact with voltagebearing
parts!
The power supply should be
mounted in a case to avoid risk
of direct contact with live parts!
Do not disconnect ground/earth
inside or outside the power supply.
The company cannot be held
reponsible for unsafe operating
conditions resulting from deliberate
disconnection!
Disconnect the mains/line voltage
from the unit before changing the
fuse.
The units are fused for live only.
A second fuse should be used for
the neutral connection where the
polarity of the connectors can be
reversed.
When operating several power
supplies in series, dangerous
voltages may occur at the output
terminals; SELV voltage must be
limited to 60 VDC!
When mounting the unit read the
safety instructions to EN 60950!
Pour obtenir une protection contre
les contacts directs, l’appareil doit
obligatoirement être monté dans un
boîtier excluant toute possibilité de
contact avec des parties sous
tension.
Toute interruption de la ligne de
protection à l’intérieur ou à
l’extérieur de l’alimentation, de
même qu’une déconnexion de cette
ligne, peuvent rendre l’appareil
dangereux. Tout acte intentionnel
dans ce sens est strictement interdit.
Avant de remplacer le fusible,
couper l’appareil du secteur
L’alimentation ne dispose que d’une
protection unipolaire. Si le dispositif
de connexion au secteur est de
nature â favoriser une inversion
polaire, il faut prévoir un second
fusible.
Le couplage en série de plusieurs
alimentations peut occasionner des
tensions mortelles aux sorties ( à
partir de 60 VDC). Limite de tension
SELV = 60 VDC max.
Lors du montage de l’alimentation,
respecter les mesures de sécurité
prévues par la norme EN 60950.
Observer les prescriptions et règles
de sécurité générales.
EN 60950
Bedienungsanleitung
Operating instructions
Notice d’utilisation
SEK single (SEK 1xx)
(13100-041 – 13100-046)
Vor Inbetriebnahme diese Bedienungsanleitung sorgfältig lesen! Entstehen
durch Nichtbeachtung Schäden, erlöschen die Garantieansprüche.
Diese Dokumentation wurde mit größter Sorgfalt erstellt. Dennoch können
wir für die vollständige Richtigkeit keine Garantie übernehmen.
Please read these operating instructions carefully before applying power.
The warranty is subject to correct input voltages being applied. Repairs or
modifications made by anyone other than SCHROFF will invalidate the warranty.
This documentation has been compiled with the utmost care. We
cannot however guarantee its correctness in every respect.
Avant la mise en service, veuillez lire attentivement la présente notice
d'utilisation. Tout dommage dû à l'inobservation de nos instructions n'est
pas couvert par notre garantie. La présente documentation a été réalisée
avec le plus grand soin mais nous déclinons toute responsabilité en cas
d'erreur ou d'omission.
SCHROFF GMBH www.schroff.biz D/GB/F 11/06
Langenalber Straße 96-100, D-75334 Straubenhardt, Tel. +49 (7082) 794-0, Fax +49 (7082) 794-200
73972-035 Rev. 002
11396002
Basic-type Digital Temperature Controller E5CN/E5CN-U 1
Basic-type Digital Temperature Controller
E5CN/E5CN-U (48 x 48 mm)
New 48 x 48-mm Basic Temperature
Controller with Enhanced Functions and
Performance. Improved Indication
Accuracy and Preventive Maintenance
Function.
• Indication Accuracy
Thermocouple input: ±0.3% of PV (previous models: ±0.5%)
Pt input: ±0.2% of PV (previous models: ±0.5%)
Analog input: ±0.2% FS (previous models: ±0.5%)
• New E5CN-U Models (Plug-in Models) with analog inputs and
current outputs.
• A PV/SV-status display function can be set to alternate between
displaying the PV or SV and the status of the Temperature
Controller (auto/manual, RUN/STOP and alarms).
• Preventive maintenance for relays using a Control Output ON/OFF Counter.
Main I/O Functions
48 × 48-mm
E5CN
48 × 48-mm
E5CN-U
Refer to Safety Precautions on page 18.
Event Inputs
• None
• Two
Sensor Inputs
• Universal thermocouple/Pt inputs
(Models with temperature inputs)
• Analog current/voltage inputs
(Models with analog inputs)
Indication Accuracy
• Thermocouple input: ±0.3% of PV
• Pt input: ±0.2% of PV
• Analog input: ±0.2% FS
Sampling Period and control update
• 250 ms
Control Output 1
• Relay output
• Voltage output (for driving SSR)
• Current output
• Long-life relay output (hybrid)
Control Output 2
• None
• Voltage output
(for driving SSR)
2 Auxiliary Outputs
2 line Display: PV and SV 4-digit, 11 segment display
E5CN
• Auto/manual switching
• Temperature Controller status display
• Simple program function
• Control output ON/OFF count alarm
• PV change rate alarm
• Models optional with RS-485
communications
This data sheet is provided as a guideline for selecting products. Be sure to refer to the following user manuals for application precautions
and other information required for operation before attempting to use the product.
E5CN/E5AN/E5EN Digital Temperature Controllers User's Manual Basic Type (Cat. No. H156)
E5CN/E5AN/E5EN Digital Temperature Controllers Communications Manual Basic Type (Cat. No. H158)
2 Basic-type Digital Temperature Controller E5CN/E5CN-U
Lineup
Note: All models can be used for Heating, Cooling and Heating & Cooling control
Model Number Structure
Model Number Legend
Controllers
1. Control Output 1
R: Relay output
Q: Voltage output (for driving SSR)
C: Current output
Y: Long-life relay output (hybrid) ✽1
2. Auxiliary Outputs ✽2
2: Two outputs
3. Option
M: Option Unit can be mounted.
4. Input Type
T: Universal thermocouple/platinum resistance thermometer
L: Analog current/voltage input
5. Power Supply Voltage
Blank: 100 to 240 VAC
D: 24 VAC/VDC
6. Case Color
Blank: Black
W: Silver (contact your local sales for more information)
7. Terminal Cover
-500: With terminal cover
Option Units
1. Applicable Controller
CN: E5CN
2. Function 1
Blank: None
Q: Control output 2 (voltage for driving SSR)
P: Power supply for sensor
3. Function 2
Blank: None
H: Heater burnout/SSR failure/Heater overcurrent detection (CT1)
HH: Heater burnout/SSR failure/Heater overcurrent detection
(For 3-phase heater applications, 2x CT)
B: Two event inputs
03: RS-485 communications
H03: Heater burnout/SSR failure/Heater overcurrent detection
(CT1) + RS-485 communications
HB: Heater burnout/SSR failure/Heater overcurrent detection
(CT1) + Two event inputs
HH03: Heater burnout/SSR failure/Heater overcurrent detection
(For 3-phase heater applications, 2x CT)
4. Version
N2: Applicable only to models produced after January 2008
(Box marked with N6)
Note: Not all combinations of function 1 and function 2 specifications are possible for Option Units (E53-CN@@N2).
✽1. Always connect an AC load to a long-life relay output. The output will not turn OFF if a DC load is connected because a triac is used for
switching the circuit. For details, check the conditions in Ratings.
✽2. Auxiliary outputs are contact outputs that can be used to output alarms, control or results of logic operations.
Plug-in
Terminal block
E5CN
Basic Type
Analog input
Temperature input
2 control outputs
1 control output
2 control outputs
1 control output
2 auxiliary outputs
2 auxiliary outputs
2 auxiliary outputs
2 auxiliary outputs
Analog input
Temperature input
1 control output
1 control output 2 auxiliary outputs
2 auxiliary outputs
1 2 3 4 5 6 7
E5CN-@2M@@-@-500
1 2 3 4
E53-CN@@N2
Basic-type Digital Temperature Controller E5CN/E5CN-U 3
Ordering Information
Controllers with Terminal Blocks
Note: add power supply voltage to model to complete ordering code (ie. E5CN-R2MT-500 AC100-240 or E5CN-R2MTD-500 AC/DC24)
Option Units
One of the following Option Units can be mounted to provide the E5CN with additional functions.
Note: Option Units cannot be used for plug-in models.
These Option Units are applicable only to models produced after January 2008 (Box marked with N6).
Size Case color Power supply
voltage Input type Auxiliary outputs Control output 1 Model
1/16 DIN
48 × 48 × 78
(W × H × D)
Black
100 to 240 VAC
Thermocouple or
Resistance
thermometer
2
Relay output E5CN-R2MT-500
Voltage output (for driving SSR) E5CN-Q2MT-500
Current output E5CN-C2MT-500
Long-life relay output (hybrid) E5CN-Y2MT-500
24 VAC/VDC
Thermocouple or
Resistance
thermometer
2
Relay output E5CN-R2MTD-500
Voltage output (for driving SSR) E5CN-Q2MTD-500
Current output E5CN-C2MTD-500
100 to 240 VAC Analog
(current/voltage) 2
Relay output E5CN-R2ML-500
Voltage output (for driving SSR) E5CN-Q2ML-500
Current output E5CN-C2ML-500
Long-life relay output (hybrid) E5CN-Y2ML-500
24 VAC/VDC Analog
(current/voltage) 2
Relay output E5CN-R2MLD-500
Voltage output (for driving SSR) E5CN-Q2MLD-500
Current output E5CN-C2MLD-500
Functions Model
Event inputs E53-CNBN2
Event inputs Control output 2
(Voltage for driving SSR) E53-CNQBN2
Event inputs Heater burnout/SSR failure/Heater
overcurrent detection E53-CNHBN2
Event inputs External power supply for
ES1B E53-CNPBN2
Communications
RS-485 E53-CN03N2
Communications
RS-485
Control output 2
(Voltage for driving SSR) E53-CNQ03N2
Communications
RS-485
Heater burnout/SSR failure/Heater
overcurrent detection E53-CNH03N2
Communications
RS-485
3-phase heater burnout/SSR failure/
Heater overcurrent detection E53-CNHH03N2
Communications
RS-485
External power supply for
ES1B E53-CNP03N2
Heater burnout/SSR failure/Heater
overcurrent detection
Control output 2
(Voltage for driving SSR) E53-CNQHN2
3-phase heater burnout/SSR failure/
Heater overcurrent detection
Control output 2
(Voltage for driving SSR) E53-CNQHHN2
Heater burnout/SSR failure/Heater
overcurrent detection
External power supply for
ES1B E53-CNPHN2
4 Basic-type Digital Temperature Controller E5CN/E5CN-U
Model Number Structure
Model Number Legend (Plug-in-type Controllers)
1. Output Type
R: Relay output
Q: Voltage output (for driving SSR)
C: Current output
2. Number of Alarms
2: Two alarms
3. Input Type
T: Universal thermocouple/platinum resistance thermometer
L: Analog Input
4. Plug-in type
U: Plug-in type
Ordering Information
Plug-in-type Controllers
Note: add power supply voltage to model to complete ordering code. (ie. E5CN-R2TU AC100-240 or E5CN-R2TDU AC/DC24)
1 2 3 4
E5CN-@2@U
Size Case color Power supply voltage Input type Auxiliary outputs Control output 1 Model
1/16 DIN Black
100 to 240 VAC
Thermocouple
or resistance
thermometer
2
Relay output E5CN-R2TU
Voltage output (for driving SSR) E5CN-Q2TU
Current output E5CN-C2TU
Analog
(current/voltage) 2
Relay output E5CN-R2LU
Voltage output (for driving SSR) E5CN-Q2LU
Current output E5CN-C2LU
24 VAC/VDC
Thermocouple
or resistance
thermometer
2
Relay output E5CN-R2TDU
Voltage output (for driving SSR) E5CN-Q2TDU
Current output E5CN-C2TDU
Basic-type Digital Temperature Controller E5CN/E5CN-U 5
Accessories (Order Separately)
USB-Serial Conversion Cable
Terminal Cover
Note: The Terminal Cover comes with the E5CN-@@@-500 models.
Waterproof Packing
Note: The Waterproof Packing is included with the Controller only for
models with terminal blocks.
Current Transformers (CTs)
Adapter
Note: Use this Adapter when the panel has been previously prepared
for the E5B@ (72x72 mm panel cut-out).
Sockets (for Plug-in Models)
CX-Thermo Support Software
Model
E58-CIFQ1
Connectable models Terminal block models
Model E53-COV17
Model
Y92S-29
Hole diameter Model
5.8 dia. E54-CT1
12.0 dia. E54-CT3
Connectable models Model
Terminal block models Y92F-45
Type Model
Front-connecting Socket P2CF-11
Front-connecting Socket with Finger Protection P2CF-11-E
Back-connecting Socket P3GA-11
Terminal Cover for Back-connecting socket with
Finger Protection Y92A-48G
Model
EST2-2C-MV4
6 Basic-type Digital Temperature Controller E5CN/E5CN-U
Specifications
Ratings
Power supply voltage No D in model number: 100 to 240 VAC, 50/60 Hz
D in model number: 24 VAC, 50/60 Hz; 24 VDC
Operating voltage range 85% to 110% of rated supply voltage
Power
consumption
E5CN 100 to 240 VAC: 7.5 VA (max.) (E5CN-R2T at 100 VAC: 3.0 VA)
24 VAC/VDC: 5 VA/3 W (max.) (E5CN-R2TD at 24 VAC: 2.7 VA)
E5CN-U 100 to 240 VAC: 6 VA (max.)
24 VAC/VDC: 3 VA/2 W (max.) (models with current output: 4 VA/2 W)
Sensor input
Models with temperature inputs
Thermocouple: K, J, T, E, L, U, N, R, S, B, W, or PL II
Platinum resistance thermometer: Pt100 or JPt100
Infrared temperature sensor: 10 to 70° C, 60 to 120°C, 115 to 165° C, or 140 to 260°C
Voltage input: 0 to 50 mV
Models with analog inputs
Current input: 4 to 20 mA or 0 to 20 mA
Voltage input: 1 to 5 V, 0 to 5 V, or 0 to 10 V
Input impedance Current input: 150 Ω max., Voltage input: 1 MΩ min. (Use a 1:1 connection when connecting the ES2-HB.)
Control method ON/OFF control or 2-PID control (with auto-tuning)
Control
outputs
Relay output
E5CN SPST-NO, 250 VAC, 3 A (resistive load), electrical life: 100,000 operations, minimum applicable
load: 5 V, 10 mA
E5CN-U SPDT, 250 VAC, 3 A (resistive load), electrical life: 100,000 operations, minimum applicable load:
5 V, 10 mA
Voltage output
(for driving SSR)
E5CN
E5CN-U
Output voltage: 12 VDC ±15% (PNP), max. load current: 21 mA, with short-circuit protection
circuit
Current output E5CN 4 to 20 mA DC/0 to 20 mA DC, load: 600 Ω max., resolution: approx. 10,000
Long-life relay
output E5CN
SPST-NO, 250 VAC, 3 A (resistive load), electrical life: 1,000,000 operations, load power supply
voltage: 75 to 250 VAC (DC loads cannot be connected.), minimum applicable load: 5 V, 10 mA,
leakage current: 5 mA max. (250 VAC, 60 Hz)
Auxiliary
outputs
Number of outputs 2
Output specifications
Relay output: SPST-NO, 250 VAC, 3 A (resistive load), electrical life: 100,000 operations, minimum
applicable load: 5 V, 10 mA
Event
inputs
Number of inputs 2
External contact
input specifications
Contact input: ON: 1 kΩ max., OFF: 100 kΩ min.
Non-contact input: ON: Residual voltage: 1.5 V max., OFF: Leakage current: 0.1 mA max.
Current flow: Approx. 7 mA per contact
External power supply for ES1B 12 VDC ±10%, 20 mA, short-circuit protection circuit provided
Setting method Digital setting using front panel keys
Indication method 11-segment digital display and individual indicators (7-segment display emulation also possible)
Character height: PV: 11 mm, SV: 6.5 mm
Multi SP Up to four set points (SP0 to SP3) can be saved and selected using event inputs, key operations, or serial
communications.
Bank switching Not supported
Other functions
Manual output, heating/cooling control, loop burnout alarm, SP ramp, other alarm functions, heater burnout
detection, 40% AT, 100% AT, MV limiter, input digital filter, self-tuning, temperature input shift, run/stop,
protection functions, control output ON/OFF counter, extraction of square root, MV change rate limit, logic
operations, PV/SV status display, simple program, automatic cooling coefficient adjustment
Ambient operating temperature −10 to 55°C (with no condensation or icing), for 3-year warranty: −10 to 50°C
Ambient operating humidity 25% to 85%
Storage temperature −25 to 65°C (with no condensation or icing)
Basic-type Digital Temperature Controller E5CN/E5CN-U 7
Input Ranges
Thermocouple/Platinum Resistance Thermometer (Universal Inputs)
Models with Analog Inputs
Shaded settings are the default settings.
Input
Type
Platinum resistance
thermometer Thermocouple Infrared temperature
sensor
Analog
input
Name Pt100 JPt100 K J T E L U N R S B W PL
II
10 to
70°C
60 to
120
°C
115
to
165
°C
140
to
260
°C
0 to
50 mV
Temperature range (° C)
2300
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
−100.0
−200.0
2300
Usable
in the
following
ranges
by
scaling:
−1999 to
9999 or
−199.9 to
999.9
1800
1700 1700
1300 1300 1300
850 850 850
600
500.0 500.0 500.0
400.0 400 400.0 400 400.0
260
120 165
100.0 100.0 90
100
0.0 0.0 0 0 0 0 0 0 0 0
−20.0 −100 −20.0 −100
−200 −199.9 −199.9 −200 −200 −199.9 −200 −200 −199.9 −200
Setting
number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 24 25 19 20 21 22 23
Shaded settings are the default settings.
The applicable standards for the input types are as follows:
K, J, T, E, N, R, S, B: JIS C 1602-1995, IEC 584-1
L: Fe-CuNi, DIN 43710-1985
U: Cu-CuNi, DIN 43710-1985
W: W5Re/W26Re, ASTM E988-1990
JPt100: JIS C 1604-1989, JIS C 1606-1989
Pt100: JIS C 1604-1997, IEC 751
PL II: According to Platinel II electromotive force charts from BASF (previously
Engelhard)
Input Type Current Voltage
Input specification 4 to 20mA 0 to 20 mA 1 to 5 V 0 to 5 V 0 to 10 V
Setting range Usable in the following ranges by scaling:
−1999 to 9999, −199.9 to 999.9, −19.99 to 99.99 or −1.999 to 9.999
Setting number 0 1 2 3 4
8 Basic-type Digital Temperature Controller E5CN/E5CN-U
Alarm Outputs
Each alarm can be independently set to one of the following 13 alarm types. The default is 2: Upper limit.
Auxiliary outputs are allocated for alarms. ON delays and OFF delays (0 to 999 s) can also be specified.
Note: For models with heater burnout, SSR failure, and heater overcurrent detection, alarm 1 will be an OR output of the alarm selected from the
following alarm types and the alarms for heater burnout, SSR failure, and heater overcurrent. To output only a heater burnout alarm, SSR
failure alarm, and heater overcurrent alarm for alarm 1, set the alarm type to 0 (i.e., no alarm function).
✽1. With set values 1, 4 and 5, the upper and lower limit values can
be set independently for each alarm type, and are expressed as
“L” and “H.”
✽2. Set value: 1, Upper- and lower-limit alarm
✽3. Set value: 4, Upper- and lower-limit range
✽4. Set value: 5, Upper- and lower-limit with standby sequence
For Upper- and Lower-Limit Alarm Described Above
• Case 1 and 2
Always OFF when the upper-limit and lower-limit hysteresis
overlaps.
• Case 3: Always OFF
✽5. Set value: 5, Upper- and lower-limit with standby sequence
Always OFF when the upper-limit and lower-limit hysteresis
overlaps.
Set
value Alarm type
Alarm output operation
When X is
positive
When X is
negative
0 Alarm function
OFF Output OFF
1
✽1
Upper- and lowerlimit
✽2
2 Upper limit
3 Lower limit
4
✽1
Upper- and lowerlimit
range ✽3
5
✽1
Upper- and lowerlimit
with standby
sequence
✽4
6 Upper-limit with
standby sequence
7 Lower-limit with
standby sequence
8 Absolute-value
upper-limit
9 Absolute-value
lower-limit
10
Absolute-value
upper-limit with
standby sequence
11
Absolute-value
lower-limit with
standby sequence
12 LBA
(for alarm 1 only) ---
13 PV change rate
alarm ---
ON
OFF
SP
L H
SP
X
ON
OFF
SP
X
ON
OFF
SP
ON X
OFF
SP
ON X
OFF
SP
L H
ON
OFF
SP
L H
ON
OFF
✽5
SP
X
ON
OFF
SP
X
ON
OFF
SP
X
ON
OFF
SP
ON X
OFF
0
ON X
OFF
0
X
ON
OFF
0
X
ON
OFF
0
X
ON
OFF
0
X
ON
OFF
0
ON X
OFF
0
X
ON
OFF
0
X
ON
OFF
L H
H < 0, L > 0
⏐H⏐ < ⏐L⏐
SP
Case 1
L H
H > 0, L < 0
⏐H⏐ > ⏐L⏐
SP
Case 2
H L
H < 0, L < 0
SP
H L
H < 0, L > 0
SP ⏐H⏐ ≥ ⏐L⏐
H L
H > 0, L < 0
SP ⏐H⏐ ≤ ⏐L⏐
Case 3 (Always ON)
L H SP
Case 1
SP L H
Case 2
H SP L
L
L
H SP
SPH
Case 3 (Always OFF)
H < 0, L > 0
⏐H⏐ < ⏐L⏐
H > 0, L < 0
⏐H⏐ > ⏐L⏐
H < 0, L < 0
H < 0, L > 0
⏐H⏐ ≥ ⏐L⏐
H > 0, L < 0
⏐H⏐ ≤ ⏐L⏐
Basic-type Digital Temperature Controller E5CN/E5CN-U 9
Characteristics
✽1. The indication accuracy of K thermocouples in the −200 to 1300° C range, T and N thermocouples at a temperature of −100° C max., and U and L
thermocouples at any temperatures is ±2° C ±1 digit max. The indication accuracy of the B thermocouple at a temperature of 400° C max. is not specified.
The indication accuracy of B thermocouples in the 400 to 800° C range is ±3° C max. The indication accuracy of the R and S thermocouples at a
temperature of 200° C max. is ±3° C ±1 digit max. The indication accuracy of W thermocouples is ±0.3 of PV or ±3° C, whichever is greater, ±1 digit max.
The indication accuracy of PL II thermocouples is ±0.3 of PV or ±2° C, whichever is greater, ± 1 digit max.
✽2. Ambient temperature: −10° C to 23° C to 55° C, Voltage range: −15% to 10% of rated voltage
✽3. K thermocouple at −100°C max.: ±10° max.
✽4. “EU” stands for Engineering Unit and is used as the unit after scaling. For a temperature sensor, the EU is ° C or ° F.
✽5. When robust tuning (RT) is ON, the differential time is 0.0 to 999.9 (in units of 0.1 s).
✽6. External communications (RS-485) and cable communications for the Setup Tool can be used at the same time.
✽7. The E5CN-U plug-in model is certified for UL listing only when used together with the OMRON P2CF-11 Socket.
Indication accuracy
Thermocouple: ✽1
Terminal block models (E5CN): (±0.3% of indicated value or ±1° C, whichever is greater) ±1 digit max.
Plug-in models (E5CN-U): (±1% of indicated value or ±2° C, whichever is greater) ±1 digit max.
Platinum resistance thermometer input:
Terminal block models (E5CN) and plug-in models (E5CN-U): (±0.2% of indicated value or ±0.8° C, whichever is greater)
±1 digit max.
Analog input:
Terminal block models (E5CN) and plug-in models (E5CN-U): ±0.2% FS ±1 digit max.
CT input:
Terminal block models (E5CN): ±5% FS ±1 digit max.
Influence of temperature ✽2
Thermocouple input (R, S, B, W, PL II):
Terminal block models (E5CN): (±1% of PV or ±10° C, whichever is greater) ±1 digit max.
Plug-in models (E5CN-U): (±2% of PV or ±10° C, whichever is greater) ±1 digit max.
Other thermocouple input: ✽3
Terminal block models (E5CN): (±1% of PV or ±4° C, whichever is greater) ±1 digit max.
Plug-in models (E5CN-U): (±2% of PV or ±4° C, whichever is greater) ±1 digit max.
Platinum resistance thermometer input:
Terminal block models (E5CN) and plug-in models (E5CN-U):
(±1% of PV or ±2°C, whichever is greater) ±1 digit max.
Analog input:
Terminal block models (E5CN) and plug-in models (E5CN-U): (±1%FS) ±1 digit max.
Influence of voltage ✽2
Input sampling period 250 ms
Hysteresis
Models with thermocouple/platinum resistance thermometer input (universal input): 0.1 to 999.9 EU (in units of 0.1 EU) ✽4
Models with analog input: 0.01 to 99.99% FS (in units of 0.01% FS)
Proportional band (P)
Models with thermocouple/platinum resistance thermometer input (universal input): 0.1 to 999.9 EU (in units of 0.1 EU) ✽4
Models with analog input: 0.1 to 999.9% FS (in units of 0.1% FS)
Integral time (I) 0 to 3999 s (in units of 1 s)
Derivative time (D) 0 to 3999 s (in units of 1 s) ✽5
Control period 0.5, 1 to 99 s (in units of 1 s)
Manual reset value 0.0 to 100.0% (in units of 0.1%)
Alarm setting range −1999 to 9999 (decimal point position depends on input type)
Affect of signal source resistance
Thermocouple: 0.1° C/Ω max. (100 Ω max.)
Platinum resistance thermometer: 0.1° C/Ω max. (10 Ω max.)
Insulation resistance 20 MΩ min. (at 500 VDC)
Dielectric strength 2,300 VAC, 50 or 60 Hz for 1 min (between terminals with different charge)
Vibration
resistance
Malfunction 10 to 55 Hz, 20 m/s2 for 10 min each in X, Y, and Z directions
Destruction 10 to 55 Hz, 0.75-mm single amplitude for 2 hrs each in X, Y, and Z directions
Shock
resistance
Malfunction 100 m/s2, 3 times each in X, Y, and Z directions
Destruction 300 m/s2, 3 times each in X, Y, and Z directions
Weight
E5CN Controller: Approx. 150 g, Mounting Bracket: Approx. 10 g
E5CN-U Controller: Approx. 110 g, Mounting Bracket: Approx. 10 g
Degree of
protection
E5CN Front panel: IP66, Rear case: IP20, Terminals: IP00
E5CN-U Front panel: IP50, Rear case: IP20, Terminals: IP00
Memory protection Non-volatile memory (number of writes: 1,000,000 times)
Setup Tool CX-Thermo version 4.0 or higher
Setup Tool port
Provided on the bottom of the E5CN. Use this port to connect a computer to the E5CN when using the Setup Tool. An
E58-CIFQ1 USB-Serial Conversion Cable is required to connect the computer to the E5CN. ✽6
Standards
Approved
standards ✽7 UL 61010-1, CSA C22.2 No. 1010-1
Conformed
standards EN 61010-1 (IEC 61010-1): Pollution level 2, overcurrent category II
EMC
EMI: EN 61326
Radiated Interference Electromagnetic Field Strength: EN 55011 Group 1, class A
Noise Terminal Voltage: EN 55011 Group 1, class A
EMS: EN 61326
ESD Immunity: EN 61000-4-2
Electromagnetic Field Immunity: EN 61000-4-3
Burst Noise Immunity: EN 61000-4-4
Conducted Disturbance Immunity: EN 61000-4-6
Surge Immunity: EN 61000-4-5
Power Frequency Magnetic Field Immunity: EN 61000-4-8
Voltage Dip/Interrupting Immunity: EN 61000-4-11
10 Basic-type Digital Temperature Controller E5CN/E5CN-U
USB-Serial Conversion Cable
Note: A driver must be installed in the personal computer. Refer to
installation information in the operation manual for the
Conversion Cable.
Communications Specifications
✽ The baud rate, data bit length, stop bit length, and vertical parity can
be individually set using the Communications Setting Level.
Current Transformer (Order Separately)
Ratings
Heater Burnout Alarms, SSR Failure
Alarms, and Heater Overcurrent Alarms
✽1. For heater burnout alarms, the heater current will be measured
when the control output is ON, and the output assigned to the
alarm 1 function will turn ON if the heater current is lower than the
set value (i.e., heater burnout detection current value).
✽2. For SSR failure alarms, the heater current will be measured when
the control output is OFF, and the output assigned to the alarm 1
function will turn ON if the heater current is higher than the set
value (i.e., SSR failure detection current value).
✽3. For heater overcurrent alarms, the heater current will be
measured when the control output is ON, and the output assigned
to the alarm 1 function will turn ON if the heater current is higher
than the set value (i.e., heater overcurrent detection current
value).
Electrical Life Expectancy Curve for
Relays (Reference Values)
Note: Do not connect a DC load to a Controller with a Long-life Relay
Output.
Applicable OS Windows 2000, XP, or Vista
Applicable software
Thermo Mini, CX-Thermo version 4.0 or
higher
Applicable models
E5AN/E5EN/E5CN/E5CN-U/E5AN-H/
E5EN-H/E5CN-H
USB interface standard Conforms to USB Specification 1.1.
DTE speed 38400 bps
Connector
specifications
Computer: USB (type A plug)
Temperature Controller: Setup Tool port
(on bottom of Controller)
Power supply
Bus power (Supplied from USB host
controller.)
Power supply voltage 5 VDC
Current consumption 70 mA
Ambient operating
temperature
0 to 55°C (with no condensation or icing)
Ambient operating
humidity
10% to 80%
Storage temperature −20 to 60°C (with no condensation or
icing)
Storage humidity 10% to 80%
Altitude 2,000 m max.
Weight Approx. 100 g
Transmission line
connection method
RS-485: Multipoint
Communications RS-485 (two-wire, half duplex)
Synchronization
method
Start-stop synchronization
Protocol CompoWay/F, SYSWAY, or Modbus
Baud rate
1200, 2400, 4800, 9600, 19200, 38400, or
57600 bps
Transmission code ASCII
Data bit length ✽ 7 or 8 bits
Stop bit length ✽ 1 or 2 bits
Error detection
Vertical parity (none, even, odd)
Frame check sequence (FCS) with SYSWAY
Block check character (BCC) with
CompoWay/F or CRC-16 Modbus
Flow control None
Interface RS-485
Retry function None
Communications
buffer
217 bytes
Communications
response wait time
0 to 99 ms
Default: 20 ms
Dielectric strength 1,000 VAC for 1 min
Vibration resistance 50 Hz, 98 m/s2
Weight E54-CT1: Approx. 11.5 g, E54-CT3: Approx.
50 g
Accessories
(E54-CT3 only)
Armatures (2)
Plugs (2)
CT input
(for heater current detection)
Models with detection for single-phase
heaters: One input
Models with detection for single-phase
or three-phase heaters: Two inputs
Maximum heater current 50 A AC
Input current indication
accuracy ±5% FS ±1 digit max.
Heater burnout alarm
setting range ✽1
0.1 to 49.9 A (in units of 0.1 A)
Minimum detection ON time: 100 ms
SSR failure alarm setting
range ✽2
0.1 to 49.9 A (in units of 0.1 A)
Minimum detection OFF time: 100 ms
Heater overcurrent
alarm setting range ✽3
0.1 to 49.9 A (in units of 0.1 A)
Minimum detection ON time: 100 ms
500
300
100
50
30
10
5
3
1
0 1 2 3 4 5 6
E5CN
250 VAC, 30 VDC
(resistive load)
cosφ = 1
Switching current (A)
Life (× 104 operations)
Basic-type Digital Temperature Controller E5CN/E5CN-U 11
External Connections
• A voltage output (control output, for driving SSR) is not electrically insulated from the internal circuits. When using a grounding thermocouple,
do not connect any of the control output terminals to ground. (If the control output terminals are connected to ground, errors will occur in the
measured temperature values as a result of leakage current.)
• Consult with your OMRON representative before using the external power supply for the ES1B for any other purpose.
E5CN
Controllers
Option Units
E5CN-U
Note: For the Wiring Socket, purchase the P2CF-11 or PG3A-11 separately.
Relay output
250 VAC, 3 A (resistive load)
Voltage output (for driving SSR)
12 VDC, 21 mA
Current output
0 to 20 mA DC
Load: 600 Ω max.
4 to 20 mA DC
Long-life relay output
250 VAC, 3 A (resistive load)
Control output 1
+
−
A
B
B
+
−
Input power supply
Control output 1
Auxiliary outputs (relay outputs)
250 VAC, 3 A
(resistive load)
• 100 to 240 VAC
• 24 VAC/VDC (no polarity)
+
−
+
V −
Auxiliary output 2
mA
Auxiliary output 1
A heater burnout alarm, heater short alarm,
heater overcurrent alarm, or input alarm is
sent to the output to which the alarm 1
function is assigned.
DO NOT
USE
DO NOT
USE
DO NOT
USE
mA Volt T/c Pt
Analog input Temperature
input
1 1
1 2
1 3
1 4
1 5
E V 1
E V 2
E53-CNHBN2
Event inputs
and CT
1 1
1 2
1 3
1 4
1 5
E53-CNPBN2
Event Inputs and
External Power Supply
E V 1
E V 2
+
−
External
power supply
12 VDC,
20 mA
1 1
1 2
1 3
1 4
1 5
E53-CNPHN2
External Power
Supply and CT
+
−
External
power supply 12 VDC,
20 mA
1 1
1 2
1 3
1 4
1 5
B(+)
A(−)
RS-485
E53-CNP03N2
Communications (RS-485)
and External Power Supply
+
−
External
power supply
12 VDC,
20 mA
1 1
1 2
1 3
1 4
1 5
E53-CNQHN2
Control Output 2
and CT
+
−
Control output 2
1 1
1 2
1 3
1 4
1 5
E V 1
E V 2
E53-CNQBN2
Event Inputs and
Control Output 2
+
−
Control output 2
1 1
1 2
1 3
1 4
1 5
B(+)
A(−)
RS-485
E53-CNHH03N2
Communications
(RS-485) and CT2
1 1
1 2
1 3
1 4
1 5
B(+)
A(−)
RS-485
E53-CNQ03N2
Communications
(RS-485) and
Control Output 2
+
−
Control output 2
1 1
1 2
1 3
1 4
1 5
B(+)
A(−)
RS-485
E53-CN03N2
Communications
(RS-485)
1 1
1 2
1 3
1 4
1 5
E V 1
E V 2
E53-CNBN2
Event inputs
1 1
1 2
1 3
1 4
1 5
E53-CNQHHN2
Control Output 2
and CT2
+
−
Control output 2
1 1
1 2
1 3
1 4
1 5
B(+)
A(−)
RS-485
E53-CNH03N2
Communications
(RS-485) and CT
DO NOT
USE
DO NOT
USE
DO NOT
USE
DO NOT
USE
DO NOT
USE
DO NOT
USE
DO NOT
USE
DO NOT
USE
DO NOT
USE
DO NOT
USE
CT1 CT1
CT1
CT1 CT1
CT1
CT2
CT2
Voltage output (for driving SSR)
12 VDC, 21 mA
Control output 2
A
B
B
Auxiliary output
250 VAC, 3 A (resistive load)
Control output 1
Input power supply
• 100 to 240 VAC
• 24 VAC/VDC (no polarity)
Auxiliary output 1
(Relay outputs)
V
m A An input error is sent to the
output to which the alarm 1
function is assigned.
Current output
0 to 20 mA DC
Relay output
(three terminals used)
SPDT, 250 VAC, 3 A
(resistive load)
Voltage output
(for driving SSR)
12 VDC, 21 mA
Load: 600 W max.
4 to 20 mA DC
Control output 1
Auxiliary output 2
(Control output (cooling side))
DO NOT
USE
DO NOT
USE
DO NOT
USE
mA Volt T/c Pt
Analog input Temperature
input
12 Basic-type Digital Temperature Controller E5CN/E5CN-U
Nomenclature
Dimensions (Unit: mm)
Accessories (Order Separately)
USB-Serial Conversion Cable
Operation indicators
Level Key
Temperature unit
No.1 display
No. 2 display
Up Key
Mode Key Down Key
E5CN
E5CN-U
The front panel is the same for the E5CN and E5CN-U.
45+0.6
0
45+0.6
0
45+0.6
0
60 min.
(48 × number of units − 2.5)+1.0
0
Group mounting does not
allow waterproofing.
Panel Cutout
Mounted Separately Group Mounted
48 × 48
Terminal Cover
(E53-COV17)
(Accessory)
44.8 × 44.8 48.8
6
1.5
91
78
Mounting Adapter
(Accessory)
58
Waterproof
Packing
(Accessory)
E5CN
Terminal Models
Note: The terminal block cannot be removed.
• Recommended panel thickness is 1 to
5 mm.
• Group mounting is not possible in the
vertical direction. (Maintain the specified
mounting space between Controllers.)
• To mount the Controller so that it is
waterproof, insert the waterproof packing
onto the Controller.
• When two or more Controllers are
mounted, make sure that the surrounding
temperature does not exceed the
allowable operating temperature
specified in the specifications.
48 × 48
6 14.2
58 44.8 × 44.8
70.5
(84.7)
Mounting Adapter
(Accessory)
45+0.6
0
45+0.6
0
45+0.6
0
60 min.
(48 × number of units − 2.5)+1.0
0
Panel Cutout
Mounted Separately Group Mounted
E5CN-U
Plug-in Models
• Recommended panel thickness is 1 to 5
mm.
• Group mounting is not possible in the
vertical direction. (Maintain the specified
mounting space between Controllers.)
• When two or more Controllers are
mounted, make sure that the surrounding
temperature does not exceed the
allowable operating temperature specified
in the specifications.
(2,100)
250 1,765
USB connector (type A plug) Serial connector
LED indicator (RD)
LED indicator (SD)
E58-CIFQ1
Basic-type Digital Temperature Controller E5CN/E5CN-U 13
Current Transformers
48
48.8
22
9.1
Order the Waterproof Packing separately if it becomes lost or
damaged.
The Waterproof Packing can be used to achieve an IP66 degree of
protection.
(Deterioration, shrinking, or hardening of the waterproof packing may
occur depending on the operating environment. Therefore, periodic
replacement is recommended to ensure the level of waterproofing
specified in IP66. The time for periodic replacement depends on the
operating environment. Be sure to confirm this point at your site.
Consider one year a rough standard. OMRON shall not be liable for
the level of water resistance if the customer does not perform periodic
replacement.)
The Waterproof Packing does not need to be attached if a waterproof
structure is not required.
Terminal Cover
E53-COV17
Waterproof Packing
Y92S-29 (for DIN 48 × 48)
Note: The E53-COV10
cannot be used.
E54-CT3 Accessory
• Armature
30
21
15
5.8 dia.
25 3
40
10.5
2.8
7.5
10
Two, 3.5 dia.
40 × 40
30
12 dia.
9
2.36 dia.
15
30
Two, M3 (depth: 4)
Approx. 3 dia.
18
(22)
Approx. 6 dia.
Plug
Armature
Lead
E54-CT1
E54-CT3
Connection Example
• Plug
E54-CT1
Thru-current (Io) vs. Output Voltage
(Eo) (Reference Values)
Maximum continuous heater current: 50 A (50/60 Hz)
Number of windings: 400±2
Winding resistance: 18±2 Ω
Thru-current (Io) A (r.m.s.)
1 10 100 mA 1 10 100 1,000 A
Output voltage (Eo) V (r.m.s.)
100 V 50 Hz
Distortion
factor 10%
3%
1%
100 Ω
RL = 10 Ω
10 ∞
1
100 mV
10
1
100 μV
10
1 kΩ
E54-CT3
Thru-current (Io) vs. Output Voltage
(Eo) (Reference Values)
Maximum continuous heater current: 120 A (50/60 Hz)
(Maximum continuous heater current for the
Temperature Controller is 50 A.)
Number of windings: 400±2
Winding resistance: 8±0.8 Ω
3%
1%
1 kΩ
100 Ω
50 Ω
RL = 10 Ω
500 Ω
∞
Distortion
factor
10%
Thru-current (Io) A (r.m.s.)
1 10 100 mA 1 10 100 1,000 A
Output voltage (Eo) V (r.m.s.)
100 V 50 Hz
10
1
100 mV
10
1
100 μV
10
14 Basic-type Digital Temperature Controller E5CN/E5CN-U
Adapter
E5CN-U Wiring Socket
Note: A model with finger protection (P2CF-11-E) is also available.
Note: 1. Using any other sockets will adversely affect accuracy. Use only the specified sockets.
2. A Protective Cover for finger protection (Y92A-48G) is also available.
Fixture (Accessory)
69.6 to 77.6
67 × 67 87
72 × 72
4.7 76
72 × 72
48 × 48
Panel (1 to 8 mm)
77.3 (to back of E5CN)
2.2 4.7
Y92F-45 Note: Use this Adapter when the panel has already been prepared for the E5B@.
Mounted to E5CN
40±0.2
4.5
8 7 6 5
4
3
1 2
9
10 11
70 max.
4
Eleven, M3.5 × 7.5
sems screws 7.8
Two,
4.5-dia.
holes
50 max.
3
31.2 max.
35.4
Note: Can also be mounted to a DIN track.
Mounting Holes
Terminal Layout/Internal Connections
(Top View)
Two, 4.5 dia. mounting holes
Front-connecting Socket
P2CF-11
5 6 7 8
4
3
2
9
1 11 10
25.6
27 dia.
45
45
4.5 16.3 6.2
4 7 3
8.7
6
Terminal Layout/Internal Connections
(Bottom View)
Back-connecting Socket
P3GA-11
Basic-type Digital Temperature Controller E5CN/E5CN-U 15
Operation
Setting Levels Diagram
This diagram shows all of the setting levels. To move to the advanced function setting level and calibration level, you must enter passwords. Some
parameters are not displayed depending on the protect level setting and the conditions of use.
Control stops when you move from the operation level to the initial setting level.
Basic Type
✽1. You can return to the operation level by executing a software reset.
✽2. It is not possible to move to other levels from the calibration level by operating the keys on the front panel.
It can be done only by first turning OFF the power.
✽3. From the manual control level, key operations can be used to move to the operation level only.
Error Displays (Troubleshooting)
When an error occurs, the No.1 display shows the error code. Take necessary measure according to the error code, referring the table below.
Note: If the input value exceeds the display limit (-1999 to 9999), though it is within the control range, will be displayed under -1999 and
above 9999. Under these conditions, control output and alarm output will operate normally.
For details on the control range, refer to the E5CN/E5AN/E5EN Digital Temperature Controllers User's Manual Basic Type (Cat. No. H156).
✽These errors are displayed only when the PV/SP is displayed. Errors are not displayed for other displays.
No.1 display Meaning Action
Status at error
Control output Alarm output
s.err (S. Err)
Input error
✽
Check the wiring of inputs for miswiring, disconnections, and short-circuits and check the
input type. OFF Operates as above
the upper limit.
e333 (E333)
A/D
converter
error
Turn the power OFF then back ON again. If the display remains the same, the controller must
be repaired. If the display is restored to normal, then a probable cause can be external noise
affecting the control system. Check for external noise.
OFF OFF
e111 (E111)
Memory
error
Turn the power OFF then back ON again. If the display remains the same, the controller must
be repaired. If the display is restored to normal, then a probable cause can be external noise
affecting the control system. Check for external noise.
OFF OFF
Start in manual mode.
25
10 0
c
25
10 0
c
a- m
Power ON
✽3
Manual
mode
Press the O Key or the
PF Key for at least 1 s. ✽4
Press the O Key
for at least 3 s while
a-m is displayed.
(a-m will flash after
1st second.)
Operation
Level
Press the
O Key for
at least 1 s.
Press the O Key
for at least 1 s.
Input password.
Input password while
amoV is displayed. (Set
value −169)
Press the
O Key less than 1 s.
Press the O Key for at
least 3 s. (Display will flash
after 1st second.)
Control stops.
Press the
O Key for less than 1 s.
Press the
O+ M
Keys for at
least 3 s.
(Display
will flash
after 1st
second.)
Protect Level
Control in progress
Level change
Not displayed for some models
Control stopped
Start in automatic mode.
Adjustment
Level
Initial Setting
Level
Manual
Control Level
Advanced Function
Setting Level
Calibration Level
Communications
Setting
Level
Press the
O+ M
Keys for at
least 1 s.
*1
Note: The time taken to
move to the protect
level can be adjusted
by changing the
“Move to protect level
time” setting.
✽2
16 Basic-type Digital Temperature Controller E5CN/E5CN-U
M
M
M
M
M
M
M
psel
cwf
u-no
1
bps
9.6
len
7
sbit
2
prty
even
sdwt
20
Starting in manual mode.
M
M
M
M
M
M
pmov
0
oapt
0
pmsk
on
prlp
0
icpt
1
wtpt
off
25
M
M
M
M
M
M
M
M
M
M
ST (Self-tuning)
M
M
M
M
in-t
5
in-h
100
in-l
dp
d-u
sl-h
1300
sl-l
-200
cntl
onof
s-hc
stnd
st
on
ptrn
off
cp
20
c-cp
20
orev
or-r
0
0
c
M
M
M
l.adj
cmwt
off
at
off
M
M
M
M
M
M
ct1
0.0
0.0
0.0
hb1
0.0
hb2
0. 0
M
M
50.0
50.0
M
M
oc1
50.0
oc2
50.0
M
M
M
sp-0
0
sp-1
0
sp-2
0
sp-3
0
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
of-r
50.0
soak
1
c-sc
1.00
d
40
p
8.0
i
233
c-db
0.0
hys
1.0
chys
1.0
ol-l
-5.0
wt-b
off
mv-s
0.0
mv-e
0.0
ol-h
105.0
M
M
M
ins
0.0
insh
0.0
insl
0. 0
sprt
off
sqrp
0.0
M
M
M
a-m
25
25
0
M
M
M
M
M
M
M
sp-m
0
ct1
0.0
ct2
0.0
lcr1
0.0
lcr2
0.0
prst
rset
sktr
0
M
m-sp
0
r-s
run
M
M
M
M
M
M
M
M
M
M
M
M
c-o
0.0
al-1
0
al1h
0
al1l
0
al- 2
0
al2h
0
al2l
0
al-3
0
al3l
0
al3h
0
o
0.0
M
orl
0.0
M
ct2
lcr1
hs1
lcr2
hs2
0.0
0.0
alh1
0.2
M
alt1
2
M
Power ON
Starting in
automatic
mode.
Manual Control Level
PID
Control
only
PV/MV
Press the O Key less than 1 s.
Press the O Key less than 1 s.
Operation Level
Adjustment
Level
Adjustment Level
Display
Displayed only
once when
entering
adjustment level.
AT Execute/Cancel
Communications
Writing
Heater Current 1
Value Monitor
Heater Burnout
Detection 1
Heater Overcurrent
Detection 1
Heater Current 2
Value Monitor
Heater Burnout
Detection 2
Heater Overcurrent
Detection 2
Leakage Current 1
Monitor
Leakage Current 2
Monitor
HS Alarm 1
HS Alarm 2
C SP 0
C SP 1
C SP 2
SP used by
multi-SP
C SP 3
C
C
C
C
C
C
C Temperature Input Shift
1-point shift
2-point shift
Set either
of these
parameters.
Upper Limit
Temperature
Input Shift Value
Lower Limit
Temperature
Input Shift Value
Proportional Band
Integral Time
PID settings
Derivative Time
Cooling Coefficient
Heating/cooling
Dead Band
Manual Reset Value
Clear the offset during
stabilization of P or PD
control.
Hysteresis (Heating)
Hysteresis (Cooling)
Hysteresis settings
C
Soak Time
Wait Band
MV at Stop
MV at PV Error
C SP Ramp Set Value
MV Upper Limit
MV Lower Limit
MV Change Rate Limit
Extraction of Square Root
Low-cut Point
C Process Value
Added when Additional
PV display is ON.
C Process Value/
Set Point
C
C
C
Auto/Manual Switch
PID control only.
Added when
auto/manual select
addition is ON.
Multi-SP
Set Point Setting
Set Point During
SP Ramp
Heater Current 1 Value
Monitor
Heater Current 2 Value
Monitor
Leakage Current 1
Monitor
Leakage Current 2
Monitor
Program Start
Soak Time Remain
Press the O and M Keys for
at least 3 s.
Protect Level
Press the O and M Keys for at least 1 s.
Press the O Key
less than 1 s.
Communications
Setting Level
Note: The time taken to move to the protect
level can be adjusted by changing the
"Move to protect level time" setting.
Note: Displayed only for models with communications.
Changes are effective after cycling power or
after a software reset.
Move to Protect Level:
Displayed only when a password
is set. Restricts moving to protect
level.
Operation/Adjustment Protect:
Restricts displaying and
modifying menus in operation,
adjustment, and manual control
levels.
Initial Setting/
Communications Protect:
This protect level restricts movement
to the initial setting, communications
setting, and advanced function setting
levels.
Setting Change Protect:
Protects changes to setups by
operating the front panel keys.
Password to Move to Protect Level:
Password setting
Parameter Mask Enable:
Displayed only when a
parameter mask is set.
Protocol Setting:
Switches between
CompoWay/F (SYSWAY)
and Modbus.
Communications Unit No.
Communications
Baud Rate
CompoWay/F
(SYSWAY) only
Communications
Data Length
Communications
Stop Bits
Communications Parity
Send Data Wait Time
C
RUN/STOP
Alarm Value 1
Set either of these parameters.
Alarm Value
Upper Limit 1
Alarm Value
Lower Limit 1
C
C
C
C
Alarm Value 2
Set either of these parameters.
Alarm Value
Upper Limit 2
Alarm Value
Lower Limit 2
C Alarm Value 3
C
C
Alarm Value
Upper Limit 3
Alarm Value
Lower Limit 3
Set either of these parameters.
MV Monitor (Heating)
MV Monitor (Cooling)
Press the
O Key for
at least 1 s.
Press the O Key less than 1 s.
Initial Setting Level
Input Type
Scaling Upper Limit
Scaling Lower Limit
Decimal Point
For input type of analog
C
C
Temperature Unit
°C, °F
For input type of
temperature
SP Upper Limit
SP Lower Limit
Limit the set point
PID ON/OFF
Standard or
Heating/Cooling
For input type of
temperature, standard
control, or PID
Program Pattern
When assigning PID or
control output to ON/OFF
output
Control Period (Heating)
Control Period (Cooling)
Set the ON/OFF
output cycle.
Direct/Reverse Operation
C
Alarm 1 Type
Alarm 1
Hysteresis
Press the O Key for at least 3 s.
Other than the Auto/Manual Switch display
Press the
O Key for at
least 1 s.
Press the
O Key
for at
least 3 s.
Parameters
Basic Type
Some parameters are not displayed depending on
the model of the Controller and parameter settings.
For details, refer to the E5CN/E5AN/E5EN Digital
Temperature Controllers User's Manual Basic Type
(Cat. No. H156).
Basic-type Digital Temperature Controller E5CN/E5CN-U 17
M
M
M
M
M
M
a1lt
off
a2lt
off
a3lt
off
prlt
3
sero
off
cjc
on
rlrv
M
M
off
colr
red
pv-b
5.0
M
M
M
M
M
M
M
M
M
hsu
on
hsl
off
hsh
0.1
lba
0
lbal
8.0
lbab
3.0
out1
o
out2
none
M
init
off
M
M
M
M
M
M
M
M
mspu
off
spru
m
rest
a
sb1n
n-o
sb2n
n-o
sb3n
n-o
hbu
on
hbl
off
hbh
0.1
M
M
M
M
ra1m
0
ra2m
0
ra2
0
ra1
0
rac
0
M
M
M
M
M
spdp
4
odsl
o
pvdp
on
pvst
off
svst
off
M
M
cmov
0
inf
0.0
M
M
alfa
0.65
st-b
15.0
M
M
at-h
0.8
at-g
0.8
M
lcma
20.0
M M
M
M
M
M
a1on
0
a2on
0
a3 on
0
a1of
0
a2of
0
a3of
0
M
M
M
M
M
ocu
on
ocl
off
och
0.1
M
M
M
M
M
sub1
alm1
sub2
alm2
csel
on
t-u
m
alsp
sp-m
M
pvrp
4
csca
off
M
manl
off
M
M
M
pvad
off
o-dp
off
ret
off
M
istp
ins1
M
M
mvse
off
amad
off
rt
off
M
RT
M
M
M
M
M
M
alt2
2
a lt3
2
tr-t
off
tr-h
100.0
tr-l
0.0
M
o1-t
4-20
M
M
ev-m
1
ev-1
none
ev-2
stop
alh3
0.2
M
alh2
0.2
M
d. ref
0.2 5
Press the O Key for at least 1 s.
Advanced Function Setting Level
C
Alarm 2 Type
Alarm 3 Type
Alarm 2
Hysteresis
Alarm 3
Hysteresis
C
Transfer Output Type
Linear output
Transfer Output
Upper Limit
Transfer Output
Lower Limit
Linear Current Output
Linear output
Number of Multi-SP Uses
Two SPs: 1
Four SPs: 2
Event Input
Assignment 1
Event Input
Assignment 2
M
amov
0
M
sqr
off
M
Extraction of Square
Root Enable
Move to Advanced
Function Setting Level:
Displayed when initial
setting/communications
protect is set to 0.
Move by setting password (−169).
Parameter Initialization
Multi-SP Uses
SP Ramp Time Unit
Standby Sequence
Reset
Auxiliary Output 1
Open in Alarm
Auxiliary Output 2
Open in Alarm
Auxiliary Output 3
Open in Alarm
HB ON/OFF
Heater Burnout Latch
C
C
Heater Burnout
Hysteresis
ST Stable Range
AT Calculated Gain
α
C AT Hysteresis
Limit Cycle MV
Amplitude
Input Digital Filter
Additional PV Display
MV Display
Automatic Display
Return Time
Alarm 1 Latch
Alarm 2 Latch
Alarm 3 Latch
Move to Protect Level
Time
Input Error Output
Cold Junction
Compensation
Method
MB Command
Logic Switching
PV Change Color
PV Stable Band
Alarm 1 ON Delay
Alarm 2 ON Delay
Alarm 3 ON Delay
Alarm 1 OFF Delay
Alarm 2 OFF Delay
Alarm 3 OFF Delay
Input Shift Type
MV at Stop and Error
Addition
Auto/Manual Select
Addition
HS Alarm Use
HS Alarm Latch
HS Alarm Hysteresis
LBA Detection Time
C
C
LBA Level
LBA Band
Control Output 1
Assignment
Control Output 2
Assignment
Auxiliary Output 1
Assignment
Auxiliary Output 2
Assignment
Character Select
Soak Time Unit
Alarm SP Selection
Manual MV
Limit Enable
PV Rate of Change
Calculation Period
Automatic Cooling
Coefficient Adjustment
Heater Overcurrent
Use
Heater Overcurrent
Latch
Heater Overcurrent
Hysteresis
Move to Calibration
Level
"PV/SP" Display
Screen Selection
MV Display Selection
PV Decimal Point
Display
PV Status Display
Function
SV Status Display
Function
Display Refresh
Period
Control Output 1
ON/OFF Count
Monitor
Control Output 2
ON/OFF Count
Monitor
Control Output 1
ON/OFF Count
Alarm Set Value
Control Output 2
ON/OFF Count
Alarm Set Value
ON/OFF Counter
Reset
18 Basic-type Digital Temperature Controller E5CN/E5CN-U
Safety Precautions
!CAUTION
✽1. An SELV circuit is one separated from the power supply with
double insulation or reinforced insulation, that does not exceed
30 V r.m.s. and 42.4 V peak or 60 VDC.
✽2. A class 2 power supply is one tested and certified by UL as having
the current and voltage of the secondary output restricted to
specific levels.
✽3. The tightening torque for E5CN-U is 0.5 N·m.
Precautions for Safe Use
Be sure to observe the following precautions to prevent malfunction
or adverse affects on the performance or functionality of the product.
Not doing so may occasionally result in faulty operation.
1. This product is specifically designed for indoor use only.
Do not use this product in the following places:
• Places directly subject to heat radiated from heating equipment.
• Places subject to splashing liquid or oil atmosphere.
• Places subject to direct sunlight.
• Places subject to dust or corrosive gas (in particular, sulfide gas
and ammonia gas).
• Places subject to intense temperature change.
• Places subject to icing and condensation.
• Places subject to vibration and large shocks.
2. Use and store the product within the rated ambient temperature
and humidity.
Gang-mounting two or more Temperature Controllers, or mounting
Temperature Controllers above each other may cause heat to build
up inside the Temperature Controllers, which will shorten their
service life. In such a case, use forced cooling by fans or other
means of air ventilation to cool down the Temperature Controllers.
3. To allow heat to escape, do not block the area around the product.
Do not block the ventilation holes on the product.
4. Be sure to wire properly with correct polarity of terminals.
5. Use the specified size (M3.5, width 7.2 mm or less) crimped
terminals for wiring. To connect bare wires to the terminal block,
use stranded or solid copper wires with a gage of AWG24 to
AWG14 (equal to a cross-sectional area of 0.205 to 2.081 mm2).
(The stripping length is 5 to 6 mm.) Up to two wires of the same
size and type or two crimp terminals can be inserted into a single
terminal.
6. Do not wire the terminals that are not used.
7. To avoid inductive noise, keep the wiring for the product’s terminal
block away from power cables carry high voltages or large
currents. Also, do not wire power lines together with or parallel to
product wiring. Using shielded cables and using separate conduits
or ducts is recommended.
Attach a surge suppressor or noise filter to peripheral devices that
generate noise (in particular, motors, transformers, solenoids,
magnetic coils, or other equipment that have an inductance
component).
When a noise filter is used at the power supply, first check the
voltage or current, and attach the noise filter as close as possible
to the product.
Allow as much space as possible between the product and devices
that generate powerful high frequencies (high-frequency welders,
high-frequency sewing machines, etc.) or surge.
8. Use this product within the rated load and power supply.
9. Make sure that the rated voltage is attained within two seconds of
turning ON the power using a switch or relay contact. If the voltage
is applied gradually, the power may not be reset or output
malfunctions may occur.
10.Make sure that the Temperature Controller has 30 minutes or
more to warm up after turning ON the power before starting actual
control operations to ensure the correct temperature display.
Do not touch the terminals while power is being supplied.
Doing so may occasionally result in minor injury due to
electric shock.
Do not allow pieces of metal, wire clippings, or fine
metallic shavings or filings from installation to enter the
product. Doing so may occasionally result in electric
shock, fire, or malfunction.
Do not use the product where subject to flammable or
explosive gas. Otherwise, minor injury from explosion
may occasionally occur.
Do not leave the cable for the Support Software
connected to the product. Malfunction may occur due to
noise in the cable.
Do not use the Temperature Controller or Conversion
Cable if it is damaged. Doing so may occasionally result
in minor electric shock or fire.
Never disassemble, modify, or repair the product or touch
any of the internal parts. Minor electric shock, fire, or
malfunction may occasionally occur.
CAUTION - Risk of Fire and Electric Shock
a) This product is UL listed as Open Type Process
Control Equipment. It must be mounted in an
enclosure that does not allow fire to escape externally.
b) More than one disconnect switch may be required to
de-energize the equipment before servicing the
product.
c) Signal inputs are SELV, limited energy. ✽1
d) Caution: To reduce the risk of fire or electric shock, do
not interconnect the outputs of different Class 2
circuits. ✽2
If the output relays are used past their life expectancy,
contact fusing or burning may occasionally occur.
Always consider the application conditions and use the
output relays within their rated load and electrical life
expectancy. The life expectancy of output relays varies
considerably with the output load and switching
conditions.
Tighten the terminal screws to between 0.74 and
0.90 N·m. ✽3 Loose screws may occasionally result in
fire.
Set the parameters of the product so that they are
suitable for the system being controlled. If they are not
suitable, unexpected operation may occasionally result in
property damage or accidents.
A malfunction in the product may occasionally make
control operations impossible or prevent alarm outputs,
resulting in property damage. To maintain safety in the
event of malfunction of the product, take appropriate
safety measures, such as installing a monitoring device
on a separate line.
A semiconductor is used in the output section of long-life
relays. If excessive noise or surge is impressed on the
output terminals, a short-circuit failure is likely to occur. If
the output remains shorted, fire will occur due to
overheating of the heater or other cause. Take measures
in the overall system to prevent excessive temperature
increase and to prevent fire from spreading.
Do not allow pieces of metal or wire cuttings to get inside
the cable connector for the Support Software. Failure to
do so may occasionally result in minor electric shock, fire,
or damage to equipment.
Do not allow dust and dirt to collect between the pins in
the connector on the Conversion Cable. Failure to do so
may occasionally result in fire.
When inserting the body of the Temperature Controller
into the case, confirm that the hooks on the top and
bottom are securely engaged with the case. If the body of
the Temperature Controller is not inserted properly, faulty
contact in the terminal section or reduced water
resistance may occasionally result in fire or malfunction.
When connecting the Control Output Unit to the socket,
press it in until there is no gap between the Control Output
Unit and the socket. Otherwise contact faults in the
connector pins may occasionally result in fire or
malfunction.
Basic-type Digital Temperature Controller E5CN/E5CN-U 19
11.When executing self-tuning, turn ON power to the load (e.g.,
heater) at the same time as or before supplying power to the
product. If power is turned ON to the product before turning ON
power to the load, self-tuning will not be performed properly and
optimum control will not be achieved.
12.A switch or circuit breaker must be provided close to the product.
The switch or circuit breaker must be within easy reach of the
operator, and must be marked as a disconnecting means for this
unit.
13.Always turn OFF the power supply before pulling out the interior of
the product, and never touch nor apply shock to the terminals or
electronic components. When inserting the interior of the product,
do not allow the electronic components to touch the case.
14.Do not use paint thinner or similar chemical to clean with. Use
standard grade alcohol.
15.Design the system (e.g., control panel) considering the 2 seconds
of delay that the product's output to be set after power ON.
16.The output may turn OFF when shifting to certain levels. Take this
into consideration when performing control.
17.The number of EEPROM write operations is limited. Therefore,
use RAM write mode when frequently overwriting data during
communications or other operations.
18.Always touch a grounded piece of metal before touching the
Temperature Controller to discharge static electricity from your
body.
19.Do not remove the terminal block. Doing so may result in failure or
malfunction.
20.Control outputs (for driving SSR) that are voltage outputs are not
isolated from the internal circuits. When using a grounded
thermocouple, do not connect any of the control output terminals
to ground. (Doing so may result in an unwanted circuit path,
causing error in the measured temperature.)
21.When replacing the body of the Temperature Controller, check the
condition of the terminals. If corroded terminals are used, contact
failure in the terminals may cause the temperature inside the
Temperature Controller to increase, possibly resulting in fire. If the
terminals are corroded, replace the case as well.
22.Use suitable tools when taking the Temperature Controller apart
for disposal. Sharp parts inside the Temperature Controller may
cause injury.
23.Before connecting an Output Unit, confirm the specifications and
thoroughly read relevant information in the datasheet and manual
for the Temperature Controller.
24.Check the orientation of the connectors on the Conversion Cable
before connecting the Conversion Cable. Do not force a
connector if it does not connect smoothly. Using excessive force
may damage the connector.
25.Do not place heavy object on the Conversion Cable, bend the
cable past its natural bending radius, or pull on the cable with
undue force.
26.Do not connect or disconnect the Conversion Cable while
communications are in progress. Product faults or malfunction
may occur.
27.Make sure that the Conversion Cable's metal components are not
touching the external power terminals.
28.Do not touch the connectors on the Conversion Cable with wet
hands. Electrical shock may result.
29.Before using infrared communications, correctly attach the
enclosed Mounting Adapter to the cable for the Support Software.
When connecting the infrared port on the cable to the Support
Software into the Adapter, insert the connector to the specified
line. Communications may not be possible if the connector is not
connected properly.
Precautions for Correct Use
Service Life
1. Use the product within the following temperature and humidity
ranges:
Temperature: −10 to 55° C (with no icing or condensation)
Humidity: 25% to 85%
If the product is installed inside a control board, the ambient
temperature must be kept to under 55°C, including the
temperature around the product.
2. The service life of electronic devices like Temperature Controllers
is determined not only by the number of times the relay is switched
but also by the service life of internal electronic components.
Component service life is affected by the ambient temperature: the
higher the temperature, the shorter the service life and, the lower
the temperature, the longer the service life. Therefore, the service
life can be extended by lowering the temperature of the
Temperature Controller.
3. When two or more Temperature Controllers are mounted
horizontally close to each other or vertically next to one another,
the internal temperature will increase due to heat radiated by the
Temperature Controllers and the service life will decrease. In such
a case, use forced cooling by fans or other means of air ventilation
to cool down the Temperature Controllers. When providing forced
cooling, however, be careful not to cool down the terminals
sections alone to avoid measurement errors.
Measurement Accuracy
1. When extending or connecting the thermocouple lead wire, be sure
to use compensating wires that match the thermocouple types.
2. When extending or connecting the lead wire of the platinum
resistance thermometer, be sure to use wires that have low
resistance and keep the resistance of the three lead wires the
same.
3. Mount the product so that it is horizontally level.
4. If the measurement accuracy is low, check to see if input shift has
been set correctly.
Waterproofing
The degree of protection is as shown below. Sections without any
specification on their degree of protection or those with IP@0 are not
waterproof.
Front panel: IP66
Rear case: IP20, Terminal section: IP00
(E5CN-U: Front panel: IP50, rear case: IP20, terminals: IP00)
Operating Precautions
1. It takes approximately two seconds for the outputs to turn ON from
after the power supply is turned ON. Due consideration must be
given to this time when incorporating Temperature Controllers in a
sequence circuit.
2. When using self-tuning, turn ON power for the load (e.g., heater)
at the same time as or before supplying power to the Temperature
Controller. If power is turned ON for the Temperature Controller
before turning ON power for the load, self-tuning will not be
performed properly and optimum control will not be achieved.
3. When starting operation after the Temperature Controller has
warmed up, turn OFF the power and then turn it ON again at the
same time as turning ON power for the load. (Instead of turning
the Temperature Controller OFF and ON again, switching from
STOP mode to RUN mode can also be used.)
4. Avoid using the Controller in places near a radio, television set, or
wireless installing. These devices can cause radio disturbances
which adversely affect the performance of the Controller.
Others
1. The disk that is included with the Conversion Cable is designed for
a computer CD-ROM driver. Never attempt to play the disk in a
general-purpose audio player.
2. Do not connect or disconnect the Conversion Cable connector
repeatedly over a short period of time. The computer may
malfunction.
3. After connecting the Conversion Cable to the computer, check the
COM port number before starting communications. The computer
requires time to recognize the cable connection. This delay does
not indicate failure.
4. Do not connect the Conversion Cable through a USB hub. Doing
so may damage the Conversion Cable.
5. Do not use an extension cable to extend the Conversion Cable
length when connecting to the computer. Doing so may damage
the Conversion Cable.
20 Basic-type Digital Temperature Controller E5CN/E5CN-U
Mounting
Mounting to a Panel
For waterproof mounting, waterproof packing must be installed on the
Controller. Waterproofing is not possible when group mounting
several Controllers. Waterproof packing is not necessary when there
is no need for the waterproofing function.
1. The Panel Mounting Adapter is also included with the E5CN-U.
There is no waterproof packing included with the E5CN-U.
2. Insert the E5CN/E5CN-U into the mounting hole in the panel.
3. Push the adapter from the terminals up to the panel, and
temporarily fasten the E5CN/E5CN-U.
4. Tighten the two fastening screws on the adapter. Alternately
tighten the two screws little by little to maintain a balance. Tighten
the screws to a torque of 0.29 to 0.39 N·m.
Mounting the Terminal Cover
Make sure that the “UP” mark is facing up, and then attach the E53-
COV17 Terminal Cover to the holes on the top and bottom of the
Temperature Controller.
Removing the Temperature Controller from the
Case
The Temperature Controller can be removed from the case to perform
maintenance without removing the terminal leads. This is possible for
only the E5CN, E5AN, and E5EN, and not for the E5CN-U. Check the
specifications of the case and Temperature Controller before
removing the Temperature Controller from the case.
1. Insert a flat-blade screwdriver into the two tool insertion holes (one
on the top and one on the bottom) to release the hooks.
2. Insert the flat-blade screwdriver in the gap between the front panel
and rear case, and pull out the front panel slightly. Hold the top and
bottom of the front panel and carefully pull it out toward you,
without applying unnecessary force.
3. When inserting the body of the Temperature Controller into the
case, make sure the PCBs are parallel to each other, make sure
that the sealing rubber is in place, and press the E5CN toward the
rear case into position. While pushing the E5CN into place, push
down on the hooks on the top and bottom surfaces of the rear case
so that the hooks are securely locked in place. Be sure that
electronic components do not come into contact with the case.
Precautions when Wiring
• Separate input leads and power lines in order to prevent external
noise.
• Use wires with a gage of AWG24 (cross-sectional area:
0.205 mm2) to AWG14 (cross-sectional area: 2.081 mm2) twistedpair
cable (stripping length: 5 to 6 mm).
• Use crimp terminals when wiring the terminals.
• Tighten the terminal screws to a torque of 0.74 to 0.90 N·m,
however the terminal screws on the E5CN-U must be tightened to
a torque of 0.5 N·m.
• Use the following types of crimp terminals for M3.5 screws.
• Do not remove the terminal block. Doing so will result in
malfunction or failure.
E53-COV17
Terminal Cover
(Accessory) Adapter
(Accessory)
E5CN
E5CN-U
Waterproof packing
(Accessory) Panel
Order the P2CF-11 or
P3GA-11 Socket separately.
For Front-mounting Socket
(Panel mounting is also possible.
0.4 2.0
(1)
(2)
(3)
(1)
Flat-blade screwdriver
(Unit: mm)
Tool insertion hole
7.2 mm max.
7.2 mm max.
Basic-type Digital Temperature Controller E5CN/E5CN-U 21
Warranty and Application Considerations
Read and Understand This Catalog
Please read and understand this catalog before purchasing the products. Please consult your OMRON representative if you
have any questions or comments.
Warranty and Limitations of Liability
WARRANTY
OMRON's exclusive warranty is that the products are free from defects in materials and workmanship for a period of one year (or
other period if specified) from date of sale by OMRON.
OMRON MAKES NO WARRANTY OR REPRESENTATION, EXPRESS OR IMPLIED, REGARDING NON-INFRINGEMENT,
MERCHANTABILITY, OR FITNESS FOR PARTICULAR PURPOSE OF THE PRODUCTS. ANY BUYER OR USER
ACKNOWLEDGES THAT THE BUYER OR USER ALONE HAS DETERMINED THAT THE PRODUCTS WILL SUITABLY MEET
THE REQUIREMENTS OF THEIR INTENDED USE. OMRON DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR
IMPLIED.
LIMITATIONS OF LIABILITY
OMRON SHALL NOT BE RESPONSIBLE FOR SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES, LOSS OF PROFITS,
OR COMMERCIAL LOSS IN ANY WAY CONNECTED WITH THE PRODUCTS, WHETHER SUCH CLAIM IS BASED ON
CONTRACT, WARRANTY, NEGLIGENCE, OR STRICT LIABILITY.
In no event shall the responsibility of OMRON for any act exceed the individual price of the product on which liability is asserted.
IN NO EVENT SHALL OMRON BE RESPONSIBLE FOR WARRANTY, REPAIR, OR OTHER CLAIMS REGARDING THE
PRODUCTS UNLESS OMRON'S ANALYSIS CONFIRMS THAT THE PRODUCTS WERE PROPERLY HANDLED, STORED,
INSTALLED, AND MAINTAINED AND NOT SUBJECT TO CONTAMINATION, ABUSE, MISUSE, OR INAPPROPRIATE
MODIFICATION OR REPAIR.
Application Considerations
SUITABILITY FOR USE
OMRON shall not be responsible for conformity with any standards, codes, or regulations that apply to the combination of
products in the customer's application or use of the products.
Take all necessary steps to determine the suitability of the product for the systems, machines, and equipment with which it will
be used.
Know and observe all prohibitions of use applicable to this product.
NEVER USE THE PRODUCTS FOR AN APPLICATION INVOLVING SERIOUS RISK TO LIFE OR PROPERTY WITHOUT
ENSURING THAT THE SYSTEM AS A WHOLE HAS BEEN DESIGNED TO ADDRESS THE RISKS, AND THAT THE OMRON
PRODUCTS ARE PROPERLY RATED AND INSTALLED FOR THE INTENDED USE WITHIN THE OVERALL EQUIPMENT OR
SYSTEM.
Disclaimers
PERFORMANCE DATA
Performance data given in this catalog is provided as a guide for the user in determining suitability and does not constitute a
warranty. It may represent the result of OMRON's test conditions, and the users must correlate it to actual application
requirements. Actual performance is subject to the OMRON Warranty and Limitations of Liability.
CHANGE IN SPECIFICATIONS
Product specifications and accessories may be changed at any time based on improvements and other reasons. Consult with
your OMRON representative at any time to confirm actual specifications of purchased product.
DIMENSIONS AND WEIGHTS
Dimensions and weights are nominal and are not to be used for manufacturing purposes, even when tolerances are shown.
Cat. No. H04E-EN-01 In the interest of product improvement, specifications are subject to change without notice.
OMRON EUROPE B.V.
Wegalaan 67-69,
NL-2132 JD, Hoofddorp,
The Netherlands
Phone: +31 23 568 13 00
Fax: +31 23 568 13 88
www.industrial.omron.eu
ALL DIMENSIONS SHOWN ARE IN MILLIMETERS.
To convert millimeters into inches, multiply by 0.03937. To convert grams into ounces, multiply by 0.03527.
02/2008
GO FOR EXPERIENCE
The huge installed base of our easy-to-use control components, is proof of our experience.
Our control products with a display provide the clearest visibility and a perfect read-out.
Omron, your single source for all your control components needs.
We have been supplying quality components
for more than half a century
396
Control components
397
Control components
Control components – Table of contents
Temperature controllers 19
Product overview 398
Selection table 400
Basic temperature controllers K8AB-TH 402
E5L 403
E5C2 405
E5CSV 406
General purpose controllers E5_N 407
CelciuXº 410
Advanced and Multi-Loop controllers E5_N-H/E5_N-HT 412
E5_R/E5_R-T 414
Auxiliaries PRT1-SCU11/ES1B 416
ES1C 417
Power supplies 20
Product overview 418
Selection table 421
Single-phase S8VS 422
S8VM 423
S8JX-G 424
S8TS 425
S8T-DCBU-01/-02 426
Three-phase S8VT 427
Timers 21
Product overview 428
Selection table 430
Analogue solid state timers H3DS 432
H3DK 433
H3YN 434
H3CR 435
Digital timers H5CX 436
Motor timers H2C 437
Counters 22
Product overview 438
Selection table 440
Totalisers H7EC 442
H7ET 443
H7ER 444
Pre-set counters H8GN 445
H7CX 446
Cam positioners H8PS 447
Programmable relays 23
Product overview 448
Selection table 451
Programmable relays ZEN-10C 452
ZEN-20C 453
ZEN-8E 454
ZEN-PA 455
Digital panel indicators 24
Product overview 456
Selection table 458
1/32 DIN multi-function K3GN 460
1/8 DIN standard indicators K3MA-J, -L, -F 461
1/8 DIN advanced indicators –
analogue input
K3HB-X, -H, -V, -S 462
1/8 DIN advanced indicators –
digital input
K3HB-C, -P, -R 464
How many loops are required?
K8AB-TH E5C2 E5CSV
Single digital display
E5_N
What type of output?
No display Dual digital display
Voltage (pulse) Voltage (pulse)/
relay/mA linear
Relay
Basic General purpose
What type of output?
What type of control is needed?
Single loop
E5L
CELCIUXº – CONTROL AND CONNECTIVITY
The CelciuX° is designed to handle complex temperature profiles thanks to Omron’s unique Gradient Temperature Control (GTC)
algorithm and to offer easy program-less communication with Omron and third-party PLCs and HMI. Above all, the CelciuX°
incorporates all “simple to use” clever temperature control technology, like 2-PID, disturbance control and various ways of
tuning.
• Interfaces to a wide range of industrial networks
• Reduced engineering due to program-less communications, Smart Active Parts and Function Block Libraries
• One unit handling various types of input, such as Pt, Thermocouple, mA, and V input
Always the latest news on:
www.omron-industrial.com/celciux
CelciuXº – Multi Loop Temperature Controller
398
Temperature controllers
Page 402 Page 405 Page 403 Page 406 Page 407
E5_N-HT
SV programmer
Triple digital display
Advanced On-panel In-panel
CelciuXº
What type of mounting is required?
Multi-loop
E5_R
Standard
E5_R-T
SV programmer
E5_N-H
Standard
Triple digital display
Process
399
19 Temperature controllers
Page 412 Page 412 Page 414 Page 414 Page 410
400
Selection table
Category Alarm controller Analogue/digital
temperature
controller
Analogue
temperature
controller
Compact digital
temperature
controller
Digital temperature controller
Selection criteria
Model K8AB-TH E5L E5C2 E5CSV E5AN E5EN E5CN
Type Basic General purpose
Panel In-panel type In- & on-panel type On-panel type
Loops – Single loop
Size 22.5 mm wide 45x35 mm 1/16 DIN 1/16 DIN 1/4 DIN 1/8 DIN 1/16 DIN
Control mode
ON/OFF
PID – – *1
*1 P only
– – – –
2-PID *2
*2 2-PID is Omron´s easy to use high performance PID algorithm
– – –
Operation *3
*3 H = heat, H/C = heat or cool, H & C = heat and/or cool
– H/C H H/C H & C H & C H & C
Valve Control *4
*4 Valve control = relay up and down
– – – – – – –
Features
Accuracy ±2% ±1ºC – ±0.5% ±0.3% ±0.3% ±0.3%
Auto-tuning – – –
Self-tuning – – –
Transfer output – – – –
Remote input – – – – – – –
Number of alarms 1 – – 1 3 3 3
Heater alarm – – – – *5 *5 *5
IP rating front panel IP20 IP40 IP40 IP65 IP66 IP66 IP66
Display Rotary switch SV dial 3 digit
LCD
SV dial Single 3.5 digit Dual 4 digit
(colour change)
Dual 4 digit
(colour change)
Dual 4 digit
(colour change)
Supply
voltage
110/240 VAC
24 VAC/VDC – –
Comms *6
RS-232 – – – – –
RS-485 – – – –
Event IP – – –
QLP port *7 – – – –
DeviceNet – – – – – – –
Modbus – – – –
Control
output
Relay
SSR – – – – – – –
Voltage (pulse) – –
Linear voltage – – – – – – –
Linear current – – – –
Input type –
linear
mA – – – –
mV – – – –
V – – – –
Input type – thermocouple
K –
J – –
T – –
E – – –
L – –
U – – –
N – – –
R – –
S – – –
B – – –
W – – – –
PLII – – –
Input type –
RTD
Pt100 –
JPt100 – – –
THE – sensor provided – – –
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Temperature controllers
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19 Temperature controllers
*5. Heater alarm = heater burnout & SSR failure detection
*6. PROFIBUS-DP communication option via PRT1-SCU11 for E5_N(-H), E5_R, CelciuX°. More information on Page 416
*7. QLP: Quick Link Port to connected TC to PC using the smart USB cable E58-CIFQ1
*8. 3 Alarms per loop, 2 and 4 loop models are available.
Digital temperature controller Digital process controller
E5GN CelciuXº E5CN-H E5EN-H/AN-H E5_N-HT E5AR E5ER E5_R-T
General purpose Modular Universal SV Programmer Advanced SV Programmer
On-panel type In-panel type On-panel type
Same specification as corresponding E5_N-H
On-panel type
Same specifications as corresponding E5_R.
Single loop Multi-loop Single loop Multi-loop
1/32 DIN 31×96 mm 1/16 DIN 1/4, 1/8 DIN 1/4 DIN 1/8 DIN
– – – – – –
H & C H & C H & C H & C H & C H & C
– – –
±0.3% ±0.5% ±0.1% ±0.1% ±0.1% ±0.1%
– –
– – –
3 3 3 3 4 4
*5 *8 *5 *5 – –
IP66 – IP66 IP66 IP66 IP66
Dual 4 digit
(colour change)
LED Dual 5 digit
(colour change)
Triple 5 digit
(colour change)
Triple 5 digit Triple 5 digit
–
– – – –
– – –
–
– – – –
– – – –
– –
– –
– –
– – – – – –
407 410 412 375 414
402
K8AB-TH Basic temperature controllers
Protect your heating application
This temperature monitoring relay was designed specially for monitoring abnormal
temperatures to prevent excessive temperature increase and to protect equipment.
K8AB-TH provides temperature monitoring in slim design with a width of just
22.5 mm.
• Simple function settings using DIP switch
• Selectable alarm latch and SV setting protection
• Multi-input support for thermocouple or Pt100 sensor input
• Changeover relay: fail-safe selectable
• Alarm status identification with LED
Ordering information
Specifications
Input type Temperature setting range Setting unit Supply voltage Size in mm (HxWxD) Order code
Thermocouple/
Pt100
0 to 399°C/F 1°C/F 100 to 240 VAC 90x22.5x100 K8AB-TH11S AC100-240
24 VAC/VDC K8AB-TH11S AC/DC24
Thermocouple 0 to 1,800°C
0 to 3,200 °F *1
*1 Setting range depending on sensor type selected
10°C/F 100 to 240 VAC K8AB-TH12S AC100-240
24 VAC/VDC K8AB-TH12S AC/DC24
Item 100 to 240 VAC 50/60 Hz 24 VAC 50/60 Hz or 24 VDC
Allowable voltage range 85 to 110% of power supply voltage
Power consumption 5 VA max. 2 W max. (24 VDC), 4 VA max. (24 VAC)
Sensor inputs K8AB-TH11S Thermocouple: K, J, T, E; platinum-resistance thermometer: Pt100
K8AB-TH12S Thermocouple: K, J, T, E, B, R, S, PLII
Output relay One SPDT relay (3 A at 250 VAC, resistive load)
External inputs
(for latch setting)
Contact input ON: 1 k2 max., OFF: 100 k2 min.
Non-contact input ON residual voltage: 1.5 V max., OFF leakage current: 0.1 mA max.
Leakage current: Approx. 10 mA
Setting method Rotary switch setting (set of three switches)
Indicators Power (PWR): Green LED, relay output (ALM): Red LED
Other functions Alarm mode (upper limit/lower limit), output normally ON/OFF selection, output latch, setting protection,
fail-safe operation selectable, temperature unit°C/°F
Ambient operating temperature -10 to 55°C (with no condensation or icing); for 3-year guarantee: -10 to 50°C
Storage temperature -25 to 65°C (with no condensation or icing)
Setting accuracy ±2% of full scale
Hysteresis width 2°C
Output relay Resistive load 3 A at 250 VAC (cos= 1), 3 A at 30 VDC (L/R = 0 ms)
Inductive load 1 A at 250 VAC (cos= 0.4), 1 A at 30 VDC (L/R = 7 ms)
Minimum load 10 mA at 5 VDC
Maximum contact voltage 250 VAC
Maximum contact current 3 A AC
Maximum switching capacity 1,500 VA
Mechanical life 10,000,000 operations
Electrical life Make: 50,000 times, break: 30,000 times
Sampling cycle 500 ms
Weight 130 g
Degree of protection IP20
Memory protection Non-volatile memory (number or writes: 200,000)
Safety standards Approved standards EN 61010-1
Application standards EN 61326 and EN 61010-1 (pollution level 2, overvoltage category II)
Crimp terminals Two solid wires of 2.5 mm2 or two ferrules of 1.5 mm2 with insulation sleeves can be tightened together
Case colour Munsell 5Y8/1 (ivory)
Case material ABS resin (self-extinguishing resin)
Mounting Mounted to DIN-rail or with M4 screws
Size in mm (HxWxD) 90x22.5x100
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19 Temperature controllers
E5L Basic temperature controllers
Ideal for simple built-in control
This compact but powerful ON/OFF controller is provided with a sensor and is
available in an analogue or digital version. Mounting is in-panel with a standard
PTF14A-E socket.
• Available in 4 application specific ranges.
• Sensor provided to enable immediate usage.
• High capacity output of 10 A at 250 VAC for direct load switching.
• Simple operation and setting. Even simpler with digital model.
Ordering information
Options (Order separately)
Model Size Type Control Method Control Output Order code
E5L-A_ 45×35 mm Plug-in ON/OFF operation Relay E5L-A-30-20
E5L-A-0-50
E5L-A-0-100
E5L-A-100-200
E5L-C_ 45×35 mm Plug-in ON/OFF operation Relay E5L-C-30-20
E5L-C-0-100
E5L-C-100-200
Sockets
Type Order code
Front-connecting Socket PTF14A
PTF14A-E
E5L Basic temperature controllers
404
Specifications
* The accuracy of the accessory thermistor is not included.
Ratings
Item Model
E5L-A_ E5L-C_
Power supply voltage 100 to 240 VAC, 50/60 Hz
Operating voltage range 85% to 110% of the rated supply voltage
Power consumption Approx. 3 VA
Inputs Element-interchangeable thermistor
Control method ON/OFF control
Control output SPDT contacts, 250 VAC, 10 A, cos = 1 (resistive load) SPST-NO contacts, 250 VAC, 10 A, cos = 1 (resistive load)
Setting method Analogue setting Digital settings using keys on front panel
Indication method No display LCD digital display (character height: 12 mm)
Other functions Setting protection (key protection)
Input shift
Direct/reverse operation
Indication accuracy – ±(1°C + 1 digit) max.*
Setting accuracy – ±(1°C + 1 digit) max.*
Hysteresis -30 to 20°C models: Approx. 0.5 to 2.5°C (variable)
0 to 50°C models: Approx. 0.5 to 4°C (variable)
0 to 100°C models: Approx. 0.5 to 4°C (variable)
100 to 200°C models: Approx. 0.7 to 4°C (variable)
1 to 9°C (in increments of 1°C)
Repeat accuracy 1% FS max –
Minimum scale (standard scale) -30 to 20°C models and 0 to 50°C models: 5°C
0 to 100°C models and 100 to 200°C models: 10°C
–
Influence of temperature – ±([1% of PV or 2°C, whichever is greater]+ 1 digit) max.
Influence of voltage –
Sampling period – 2 s
Insulation resistance 100 MW max. (at 500 VDC)
Dielectric strength 2,300 VAC, 50/60 Hz for 1 min (between charged terminals and uncharged metallic parts, between power supply terminals and input
terminals, between power supply terminals and output terminals, and between input terminals and output terminals)
Vibration (malfunction) Frequency of 10 to 55 Hz, 0.5-mm double amplitude for 10 min each in X, Y, and Z directions
Vibration (destruction) Frequency of 10 to 55 Hz, 0.75-mm double amplitude for 2 h each in X, Y, and Z directions
Shock (malfunction) 147 m/s2, 3 times each in 6 directions 100 m/s2, 3 times each in 6 directions
Shock (destruction) 294 m/s2, 3 times each in 6 directions
Electrical life expectancy (control output relay) 100,000 operations min (at maximum applicable load)
Memory protection – Non-volatile memory (100,000 write operations)
Weight (Thermostat) Approx. 80 g (Thermostat only)
Degree of protection Front panel: IP40, Terminals: IP00
Approved standards –
Conformed standards EN 61010-1 (IEC 61010-1), Pollution Degree 2, Overvoltage Category II
EMC Directives EMI: EN61326-1
Radiated EMI: EN55011 Group 1 Class A
Conducted EMI: EN55011 Group 1 Class A
EMS: EN61326-1
Electrostatic discharge immunity: EN61000-4-2
Electromagnetic field strength immunity: EN61000-4-3
Burst noise immunity: EN61000-4-4
Conducted disturbance immunity: EN61000-4-6
Surge immunity: EN61000-4-5
Voltage dip and power interruption immunity: EN61000-4-11
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19 Temperature controllers
E5C2 Basic temperature controllers
Easy-to-use, basic temperature controller
with analogue dial setting
Omron's basic ON/OFF or PD controller features an analogue setting dial. This compact,
low-cost controller has a setting accuracy of 2% of full scale. It incorporates a
plug-in socket allowing for DIN-rail or flush mounting.
• Compact, cost-effective controller
• Control mode: ON/OFF or PD
• Control output: relay
• Power supply: 100-120 / 200-240VAC
• Thermocouple K: 0 to 1200°C, L: 0 to 400°C, Pt100: -50 to 200°C
Ordering information
Note: Specify either 100/110/120 VAC or 200/220/240 VAC when ordering.
Accessories
Specifications
Setting method Indication method Control mode Output Order code
Thermocouple Platinum resistance
thermometer Pt100
Thermistor THE
K (CA) chromel vs.
alumel
L (IC) iron
vs. constantan
Analogue setting No indication ON/OFF Relay E5C2-R20K E5C2-R20L-D E5C2-R20P-D E5C2-R20G
P Relay E5C2-R40K E5C2-R40L-D E5C2-R40P-D
Input ranges Thermocouple *1
*1 Values in ( ) are the minimum unit.
Platinum resistance thermometer Thermistor *2
*2 Values in ( ) are the thermistor resistive value.
K (CA) chromel vs. alumel L (IC) iron vs. constantan Pt100 THE
°C 0 to 200 (5),
0 to 300 (10),
0 to 400 (10),
0 to 600 (20),
0 to 800 (20),
0 to 1,000 (25),
0 to 1,200 (25)
0 to 200 (5),
0 to 300 (10),
0 to 400 (10)
5 to 450 (10)
-50 to 50 (2),
-20 to 80 (2),
0 to 50 (1),
0 to 100 (2),
0 to 200 (5),
0 to 300 (10),
0 to 400 (10)
-50 to 50 (2) (6 k at 0°C),
0 to 100 (2) (6 k at 0°C),
50 to 150 (2) (30 k at 0°C)
Functions Order code
Front connecting socket with finger protection P2CF-08-E
Back connecting socket (for flush mounting) P3G-08
Finger protection cover (for P3G-08) Y92A-48G
Protective front cover (IP66) Y92A-48B
Supply voltage 100/110/120 VAC or 200/220/240 VAC, 50/60 Hz
Thermocouple input type K, L (with sensor break detection)
RTD input type Pt100, THE
Control mode ON/OFF or P control
Setting method analogue setting
Output Relay, SPDT, 3 A at 250 VAC
Life expectancy Electrical: 100,000 operations min.
Setting accuracy ±2% FS max.
Hysteresis Approx. 0.5% FS (fixed)
Proportional band 3% FS (fixed)
Reset range 5 ±1% FS min.
Control period 20 s
IP Rating front panel IP40 (IP66 cover available)
IP rating terminals IP00
Ambient temperature -10 to 55°C
Size in mm (HxWxD) 48x48x96
406
E5CSV Basic temperature controllers
The easy way to perfect temperature control
This multi-range 1/16 DIN controller with alarm function offers field-selectable PID
control or ON/OFF control. The large, single display shows process value, direction of
deviation from set point, output and alarm status.
• All setting field configurable with switches
• Multi-input (Thermocouple/Pt100)
• Clearly visible 3.5 digit display with character height of 13.5 mm
• Control output: relay, voltage (for driving SSR)
• ON/OFF or 2-PID control with auto-tuning and self-tuning
Ordering information
Note:Other models are available on request.
Accessories
Specifications
Size in mm Supply voltage Number of alarm
points
Control output Order code
1/16 DIN
48Hx48Wx78D
100 to 240 VAC 1 Relay E5CSV-R1T-500
Voltage (for driving SSR) E5CSV-Q1T-500
24 VAC/VDC 1 Relay E5CSV-R1TD-500
Voltage (for driving SSR) E5CSV-Q1TD-500
Type Order code
Hard protective cover Y92A-48B
Supply voltage 100 to 240 VAC, 50/60 Hz or 24 VAC/VDC (depending on model)
Operating voltage range 85 to 110% of rated supply voltage
Power consumption 5 VA
Sensor input Multi-input (thermocouple/platinum resistance thermometer): K, J, L, T, U, N, R, Pt100, JPt100
Control output Relay output SPST-NO, 250 VAC, 3 A (resistive load)
Voltage output (for driving SSR) 12 VDC, 21 mA (with short-circuit protection circuit)
Control method ON/OFF or 2-PID (with auto-tune and self-tune)
Alarm output SPST-NO, 250 VAC, 1 A (resistive load)
Setting method Digital setting using front panel keys (functionality set-up with DIP switch)
Indication 7-segment digital display (character height: 13.5 mm) and deviation indicators
Ambient temperature -10 to 55°C (with no condensation or icing)
Setting/indication accuracy ±0.5% of indication value or ±1 °C, whichever is greater ±1 digit max.
Hysteresis (for ON/OFF control) 0.2% FS (0.1% FS for multi-input (thermocouple/platinum resistance thermometer) models)
Proportional band (P) 1 to 999°C (automatic adjustment using AT/ST)
Integral time (I) 0 to 1,999 s (automatic adjustment using AT/ST)
Derivative time (D) 0 to 1,999 s (automatic adjustment using AT/ST)
Control period 2/20 s
Sampling period 500 ms
Electrical life expectancy 100,000 operations min. (relay output models)
Weight Approx. 120 g (controller only)
Degree of protection Front panel: Equivalent to IP66; rear case: IP20; terminals: IP00
Memory protection EEPROM (non-volatile memory) (number of writes: 1,000,000)
Size in mm (HxWxD) 48x48x78
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19 Temperature controllers
E5_N General purpose controllers
Compact and intelligent
general purpose controllers
The E5_N general purpose line of temperature controllers is available in 4 standard
DIN formats. They all feature a high intensity dual LCD display with a wide viewing
angle. The whole series features 3 colour PV change for easy status recognition.
• Control mode: ON/OFF or 2-PID
• Control output: relay, hybrid relay, voltage (pulse) or linear current
• Power supply: 100/240 VAC or 24 VDC/VAC
• Easy PC connection for parameter cloning, setting and tuning
• Clear and intuitive set-up and operation
Ordering information
Note:- Output and Alarm Relays: 3 A/250 VAC, electrical life: 100,000 operations
- Output voltage (pulse): 12 V, 21 mA (ie. to drive solid state relays)
- Hybrid relay (long life relay) electrical life 1,000,000 operations
- Linear current: 0(4) to 20 mA
- Heater alarm / HA = heater burnout + SSR short detection + SSR overcurrent
- Voltage: Specify the power supply specifications (voltage) when ordering E5GN
Type Input Output Fixed option Alarms Order code
48x24 mm model (includes supply voltage indication)
On-panel temperature
(TC/Pt/mV)
relay – 1 relay E5GN-R1T-C AC100-240 E5GN-R1TD-C AC/DC24
RS-485 communication E5GN-R103T-C-FLK AC100-240 E5GN-R103TD-C-FLK AC/DC24
2 Event inputs E5GN-R1BT-C AC100-240 E5GN-R1BTD-C AC/DC24
voltage (pulse) – E5GN-Q1T-C AC100-240 E5GN-Q1TD-C AC/DC24
RS-485 communication E5GN-Q103T-C-FLK AC100-240 E5GN-Q103TD-C-FLK AC/DC24
2 Event inputs E5GN-Q1BT-C AC100-240 E5GN-Q1BTD-C AC/DC24
current (linear) – E5GN-C1T-C AC100-240 E5GN-C1TD-C AC/DC24
RS-485 communication E5GN-C103T-C-FLK AC100-240 E5GN-C103TD-C-FLK AC100-240
2 Event inputs E5GN-C1BT-C AC100-240 E5GN-C1BTD-C AC/DC24
relay – 2 relay E5GN-R2T-C AC100-240 E5GN-R2TD-C AC/DC24
RS-485 communication E5GN-R203T-C-FLK AC100-240 E5GN-R203TD-C-FLK AC100-240
2 Event inputs E5GN-R2BT-C AC100-240 E5GN-R2BTD-C AC/DC24
Heater Alarm E5GN-R2HT-C AC100-240 E5GN-R2HTD-C AC/DC24
voltage (pulse) – E5GN-Q2T-C AC100-240 E5GN-Q2TD-C AC/DC24
RS-485 communication E5GN-Q203T-C-FLK AC100-240 E5GN-Q203TD-C-FLK AC/DC24
2 Event inputs E5GN-Q2BT-C AC100-240 E5GN-Q2BTD-C AC/DC24
Heater Alarm E5GN-Q2HT-C AC100-240 E5GN-Q2HTD-C AC/DC24
analogue (mA/V) relay RS-485 communication 1 relay E5GN-R103L-FLK AC100-240 E5GN-R103LD-FLK AC/DC24
voltage (pulse) RS-485 communication E5GN-Q103L-FLK AC100-240 E5GN-Q103LD-FLK AC/DC24
current (linear) – E5GN-C1L-C AC100-240 E5GN-C1LD-C AC/DC24
Type Input Output Fixed option Alarms Order code
48x48 mm model (includes supply voltage indication)
On-panel temperature
(TC/Pt/mV)
relay – 2 relays E5CN-R2MT-500 AC100-240 E5CN-R2MTD-500 AC/DC24
voltage (pulse) E5CN-Q2MT-500 AC100-240 E5CN-Q2MTD-500 AC/DC24
linear current E5CN-C2MT-500 AC100-240 E5CN-C2MTD-500 AC/DC24
hybrid relay E5CN-Y2MT-500 AC100-240 –
analogue
(mA/V)
relay E5CN-R2ML-500 AC100-240 E5CN-R2MLD-500 AC/DC24
voltage (pulse) E5CN-Q2ML-500 AC100-240 E5CN-Q2MLD-500 AC/DC24
linear current E5CN-C2ML-500 AC100-240 E5CN-C2MLD-500 AC/DC24
hybrid relay E5CN-Y2ML-500 AC100-240 n/a
In-panel temperature
(TC/Pt/mV)
relay 2 relays E5CN-R2TU AC100-240 E5CN-R2TDU AC/DC24
voltage (pulse) E5CN-Q2TU AC100-240 E5CN-Q2TDU AC/DC24
linear current E5CN-C2TU AC100-240 E5CN-C2TDU AC/DC24
analogue
(mA/V)
relay E5CN-R2LU AC100-240 –
voltage (pulse) E5CN-Q2LU AC100-240 –
linear current E5CN-C2LU AC100-240 –
E5_N General purpose controllers
408
Accessories
E5CN option boards
(One slot available in each instrument; do no fit in E5CN-U types)
Note: Options with "N2" in the code, only fit in E5CN produced after January 2008 (marked N6
on the box)
E5CN series optional tools
Option Order code
2 Event inputs – – E53-CNBN2
– voltage (pulse) E53-CNQBN2
heater alarm – E53-CNHBN2
– power supply (12 VDC/20 mA) E53-CNPBN2
RS-485
serial
communications
(CompowayF/
Modbus RTU)
– – E53-CN03N2
– voltage (pulse) E53-CNQ03N2
heater alarm – E53-CNH03N2
3-phase HA – E53-CNHH03N2
– power supply (12 VDC/20 mA) E53-CNP03N2
– heater alarm voltage (pulse) E53-CNQHN2
3-phase HA voltage (pulse) E53-CNQHHN2
heater alarm power supply (12 VDC/20 mA) E53-CNPHN2
Option Order code
USB PC based configuration cable E58-CIFQ1
PC based configuration and tuning software CX-Thermo
PC based parameter cloning software (free) ThermoMini
Standard 11 pin socket for E5CN-_ _ _ U type P2CF-11-E
E5_N General purpose controllers
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19 Temperature controllers
Note:- Output and Alarm Relays: 3 A/250 VAC, electrical life: 100,000 operations
- Output voltage (pulse): 12 V, 21 mA (ie. to drive solid state relays)
- Hybrid relay (long life relay) electrical life 1,000,000 operations
- Linear current: 0(4) to 20 mA
- Heater alarm / HA = heater burnout + SSR short detection + SSR overcurrent
E5AN/-EN option boards
(one slot available in each instrument) E5AN/-EN series optional tools
Specifications
Type Input Output Fixed option Alarms Order code (includes supply voltage indication)
48x96 mm model 96x96 mm model
On-panel temperature
(TC/Pt/mV)
relay – 3 relays E5EN-R3MT-500-N AC100-240 E5AN-R3MT-500-N AC100-240
E5EN-R3MTD-500-N AC/DC24 E5AN-R3MTD-500-N AC/DC24
heater alarm E5EN-R3HMT-500-N AC100-240 E5AN-R3HMT-500-N AC100-240
E5EN-R3HMTD-500-N AC/DC24 E5AN-R3HMTD-500-N AC/DC24
3-phase heater alarm E5EN-R3HHMT-500-N AC100-240 E5AN-R3HHMT-500-N AC100-240
E5EN-R3HHMTD-500-N AC/DC24 E5AN-R3HHMTD-500-N AC/DC24
voltage (pulse) E5EN-R3QMT-500-N AC100-240 E5AN-R3QMT-500-N AC100-240
hybrid relay E5EN-R3YMT-500-N AC100-240 E5AN-R3YMT-500-N AC100-240
power supply E5EN-R3PMT-500-N AC100-240 E5AN-R3PMT-500-N AC100-240
voltage (pulse) – E5EN-Q3MT-500-N AC100-240 E5AN-Q3MT-500-N AC100-240
E5EN-Q3MTD-500-N AC/DC24 E5AN-Q3MTD-500-N AC/DC24
heater alarm E5EN-Q3HMT-500-N AC100-240 E5AN-Q3HMT-500-N AC100-240
E5EN-Q3HMTD-500-N AC/DC24 E5AN-Q3HMTD-500-N AC/DC24
3-phase heater alarm E5EN-Q3HHMT-500-N AC100-240 E5AN-Q3HHMT-500-N AC100-240
E5EN-Q3HHMTD-500-N AC/DC24 E5AN-Q3HHMTD-500-N AC/DC24
voltage (pulse) E5EN-Q3QMT-500-N AC100-240 E5AN-Q3QMT-500-N AC100-240
hybrid relay E5EN-Q3YMT-500-N AC100-240 E5AN-Q3YMT-500-N AC100-240
power supply E5EN-Q3PMT-500-N AC100-240 E5AN-Q3PMT-500-N AC100-240
linear current – E5EN-C3MT-500-N AC100-240 E5AN-C3MT-500-N AC100-240
E5EN-C3MTD-500-N AC/DC24 E5AN-C3MTD-500-N AC/DC24
voltage (pulse) E5EN-C3QMT-500-N AC100-240 E5AN-C3QMT-500-N AC100-240
hybrid relay E5EN-C3YMT-500-N AC100-240 E5AN-C3YMT-500-N AC100-240
analogue
(mA/V)
relay – E5EN-R3ML-500-N AC100-240 E5AN-R3ML-500-N AC100-240
heater alarm E5EN-R3HML-500-N AC100-240 E5AN-R3HML-500-N AC100-240
voltage (pulse) – E5EN-Q3ML-500-N AC100-240 E5AN-Q3ML-500-N AC100-240
heater alarm E5EN-Q3HML-500-N AC100-240 E5AN-Q3HML-500-N AC100-240
hybrid relay E5EN-Q3YML-500-N AC100-240 E5AN-Q3YML-500-N AC100-240
linear current – E5EN-C3ML-500-N AC100-240 E5AN-C3ML-500-N AC100-240
Option Order code
RS-232C communications (CompoWay/F/Modbus) E53-EN01
RS-485 communications (CompoWay/F/Modbus) E53-EN03
event input E53-AKB
Option Order code
USB PC based configuration cable E58-CIFQ1
PC based configuration and tuning software CX-Thermo
PC based parameter cloning software (free) ThermoMini
Supply voltage 100 to 240 VAC 50/60 Hz or 24 VAC, 50/60Hz; 24 VDC
Heater alarm yes, optional, choice of 1 or 3 phase
Thermocouple input type K, J, T, E, L, U, N, R, S, B, W or PL II
RTD input type Pt100, JPt100
Linear input type mV or "T" models
mA and V on "L" models
Control mode ON/OFF, 2-PID (heat or heat/cool)
Accuracy Thermocouple ± 0.3% (E5CN-U ± 1%)
Platinum resistance ± 0.2%
Analogue input ± 0.2% FS
Auto-tuning yes, 40% and 100% MV output limit selection. When using Heat/Cool: automatic cool gain adjustment
Self-tuning yes
RS-232C Only for AN/-EN: Optional, Protocol CompowayF or Modbus freely selectable
RS-485 optional, CompowayF or Modbus selectable
Event input optional
QLP port (USB connection PC) yes
Ambient temperature -10 to 55°C
IP Rating front panel IP66
Sampling period 250 ms
410
CelciuXº General purpose controllers
CelciuXº - Multi-Loop temperature control –
Control and Connectivity
CelciuXº is designed to handle complex temperature profiles thanks to Omron’s
unique Gradient temperature Control (GTC) algorithm and to offer easy program-less
communication with Omron and third-party PLCs and HMI. Above all, CelciuXº
incorporates all “simple to use” clever temperature control technology, like 2-PID,
disturbance control and various ways of tuning.
• Interfaces to a wide range of industrial networks
• Reduced engineering due to Program-less communications, Smart Active Parts
and Function Block Libraries
• Available with screw terminals and screw-less clamp terminals
• One unit handling various types of input, such as Pt, Thermocouple,
mA, and V input
• Gradient Temperature Control (GTC)
Ordering information
Accessories
Current transformer
Communications and cables
Type Control points Control outputs Auxiliary outputs Other functions Terminal Order code
Basic unit 2 2 voltage (puls) 2 transistor (NPN) *1
*1 For heating/cooling control applications, the auxiliary outputs on the 2-point models are used for cooling control.
On the 4-point models, heating/cooling control can be performed for two input points only.
2 CT input *2 + 2 event input
*2 When using the heater burnout alarm, purchase a Current Transformer (E54-CT1 or E54-CT3) separately.
M3 screws EJ1N-TC2A-QNHB
Basic unit 2 2 voltage (puls) 2 transistor (NPN) *1 2 CT input *2 + 2 event input Screw-less clamp EJ1N-TC2B-QNHB
Basic unit 2 2 current 2 transistor (NPN) *1 2 event input M3 screws EJ1N-TC2A-CNB
Basic unit 2 2 current 2 transistor (NPN) *1 2 event input Screw-less clamp EJ1N-TC2B-CNB
Basic unit 4 4 voltage (puls) – – M3 screws EJ1N-TC4A-QQ
Basic unit 4 4 voltage (puls) – – Screw-less clamp EJ1N-TC4B-QQ
High function unit – – 4 transistor (NPN) 4 event input M3 screws EJ1N-HFUA-NFLK
High function unit – – 4 transistor (NPN) 4 event input Screw-less clamp EJ1N-HFUB-NFLK
DeviceNet unit – – – – Screw connector EJ1N-HFUB-DRT
End unit *3
*3 An End unit is always required for connection to a Basic unit or an HFU. An HFU cannot operate without a Basic unit.
– – 2 transistor (NPN) – M3 screws EJ1C-EDUA-NFLK
End unit *3 – – 2 transistor (NPN) – Removable Connector EJ1C-EDUC-NFLK
Type Control points Control outputs Auxiliary outputs Other functions Terminal Order code
Basic unit 2 (GTC) 2 voltage (puls)*1
*1 Heating/cooling control is not supported for gradient temperature control.
2 transistor (NPN) 2 CT input*2
*2 When using the heater burnout alarm, use a Current Transformer (E54-CT1 or E54-CT3) (sold separately).
M3 screws EJ1G-TC2A-QNH
Basic unit 2 (GTC) 2 voltage (puls)*1 2 transistor (NPN) 2 CT input*2 Screw-less clamp EJ1G-TC2B-QNH
Basic unit 4 (GTC) 4 voltage (puls)*1 – – M3 screws EJ1G-TC4A-QQ
Basic unit 4 (GTC) 4 voltage (puls)*1 – – Screw-less clamp EJ1G-TC4B-QQ
High function unit – (GTC) – 4 transistor (NPN) – M3 screws EJ1G-HFUA-NFLK
High function unit – (GTC) – 4 transistor (NPN) – Screw-less clamp EJ1G-HFUB-NFLK
End unit*3
*3 An End-unit (EDU) is always required to connect an HFU and or a Basic TC unit for Communications and Power supply.
A GTC (Gradient Temperature Control) basic TC unit always requires a GTC HFU unit.
– – 2 transistor (NPN) – M3 screws EJ1C-EDUA-NFLK
End unit*3 – – 2 transistor (NPN) – Removable Connector EJ1C-EDUC-NFLK
Diameter Order code
5.8 dia. E54-CT1
12.0 dia. E54-CT3
Description Order code
G3ZA connecting cable 5 meter EJ1C-CBLA050
USB programming cable E58-CIFQ1
PC based configuration and tuning software CX-Thermo EST2-2C-MV4
PROFIBUS Gateway PRT1-SCU11
CelciuXº General purpose controllers
411
19 Temperature controllers
Specifications
Item Type EJ1_-TC2 EJ1_-TC4
Power supply voltage 24 VDC
Operating voltage range 85% to 110% of rated voltage
Power consumption 4 W max. (at maximum load) 5 W max. (at maximum load)
Input (see note)*1
*1 Inputs are fully multi-input. Therefore, platinum resistance thermometer, thermocouple, infrared thermosensor, and analogue input can be selected.
Thermocouple: K, J, T, E, L, U, N, R, S, B, W, PLII
ES1B Infrared Thermosensor: 10 to 70°C, 60 to 120°C, 115 to 165°C, 140 to 260°C.
Analogue input: 4 to 20 mA, 0 to 20 mA, 1 to 5 V, 0 to 5 V, 0 to 10 V
Platinum resistance thermometer: Pt100, JPt100
Input impedance Current input: 150max., voltage input: 1 M min.
Control outputs Voltage output Output voltage: 12 VDC ±15%, max. load current: 21 mA (PNP models with short-circuit protection circuit)
Transistor output Max. operating voltage: 30 V, max. load current: 100 mA –
Current output Current output range: 4 to 20 mA or 0 to 20 mA DC
Load: 500 max. (including transfer output)
(Resolution: Approx: 2,800 for 4 to 20 mA DC,
approx. 3,500 for 0 to 20 mA DC)
–
Event inputs Input points 2 –
Contact input ON: 1 k max., OFF. 100 k min. –
Non-contact input ON: Residual voltage: 1.5 V max.,
OFF: Leakage current: 0.1 mA max.
–
Outflow current: approx. 4 mA per point –
Number of input and control points Input points: 2, control points: 2 Input points: 4, control points: 4
Setting method Via communications
Control method ON/OFF control or 2-PID (with autotuning, selftuning, Heat & Cool autotuning and non-linear cool output selection)
Other functions Two-point input shift, digital input filter, remote SP, SP ramp, manual manipulated variable, manipulated variable limiter, interference overshoot adjustment,
loop burnout alarm, RUN/STOP, banks, I/O allocations, etc.
Alarm output 2 points via End unit
Communication RS-485, PROFIBUS, Modbus, DeviceNet RS-485, PROFIBUS, Modbus, DeviceNet
Size in mm (WxHxD) 31x96x109
Weight 180 g
Ambient temperature range Operating -10°C to 55°C, Storage -25°C to 65°C (with no icing or condensation)
Ambient humidity range Operating. 25% to 85% (with no condensation)
412
E5_N-H/E5_N-HT Advanced and Multi-Loop controllers
Universal compact digital
process controllers
The E5_N-H series of process controllers take the proven concept of the general
purpose E5_N series to a process level. Main features of the E5_N-H series are
universal inputs, process outputs and options such as transfer output, remote setpoint
and setvalue programmer.
• Control mode: ON/OFF or 2-PID, Valve control on EN-H/AN-H
• Control output: relay, voltage (pulse), SSR, linear current and voltage
• Power supply: 100/240 VAC or 24 VDC/VAC
• Easy PC connection for parameter cloning, setting and tuning
• Clear and intuitive set-up and operation
Ordering information
Note: - Output and Alarm Relays: 3 A/250 VAC, electrical life: 100,000 operations
- Output voltage (pulse): 12 V, 21 mA (ie. to drive solid state relays)
- Linear current: 0(4) to 20 mA
- Linear voltage output: 0 to 10 V
Accessories
E5CN-H option boards
(One slot available in each instrument)
Type Input Output Fixed option Alarms Order code
48x48 mm model (includes supply voltage indication)
On-panel Universal
TC/Pt/mV
mA/V
Relay output – 3 software
alarms
2 SUB
outputs
E5CN-HR2M-500 AC100-240 E5CN-HR2MD-500 AC/DC24
Voltage (pulse) E5CN-HQ2M-500 AC100-240 E5CN-HQ2MD-500 AC/DC24
Current output E5CN-HC2M-500 AC100-240 E5CN-HC2MD-500 AC/DC24
Linear voltage output E5CN-HV2M-500 AC100-240 E5CN-HV2MD-500 AC/DC24
Relay output SV programmer
(8 programs of
32 segments
E5CN-HTR2M-500 AC100-240 E5CN-HTR2MD-500 AC/DC24
Voltage (pulse) E5CN-HTQ2M-500 AC100-240 E5CN-HTQ2MD-500 AC/DC24
Current output E5CN-HTC2M-500 AC100-240 E5CN-HTC2MD-500 AC/DC24
Linear voltage output E5CN-HTV2M-500 AC100-240 E5CN-HTV2MD-500 AC/DC24
Option Order code
Event inputs E53-CNBN2
Event inputs Control output 2
Voltage (for driving SSR)
E53-CNQBN2
Event inputs Heater burnout/SSR failure/
Heater overcurrent detection
E53-CNHBN2
Event inputs Transfer output E53-CNBFN2
Communications
RS-232C
Control output 2
Voltage (for driving SSR)
E53-CN01N2
Communications
RS-232C
E53-CNQ01N2
Communications
RS-232C
Heater burnout/SSR failure/
Heater overcurrent detection
E53-CNH01N2
Communications
RS-485
E53-CN03N2
Communications
RS-485
Control output 2
Voltage (for driving SSR)
E53-CNQO3N2
Communications
RS-485
Heater burnout/SSR failure/
Heater overcurrent detection
E53-CNH03N2
Communications
RS-485
3-phase heater burnout/SSR failure/
Heater overcurrent detection
E53-CNHH03N2
Control output 2
Voltage (for driving SSR)
Transfer output E53-CNQFN2
Control output 2
Voltage (for driving SSR)
Heater burnout/SSR failure/
Heater overcurrent detection
E53-CNQHN2
Control output 2
Voltage (for driving SSR)
3-phase heater burnout/SSR failure/
Heater overcurrent detection
E53-CNQHHN2
E5_N-H/E5_N-HT Advanced and Multi-Loop controllers
413
19 Temperature controllers
Note: - All E5EN-H/AN-H have 2 event inputs
- All E5EN-H/AN-H have Remote Setpoint 4 to 20 mA input
Specifications E5CN-H/EN-H/AN-H E5AN-H/EN-H output option boards
(2 slots available in E5_N-HAA__-500 models:
SS models have 2 fixed SSR output modules)
E5AN-H/EN-H option boards
(one slot available in each instrument)
E5AN-H/EN-H series optional tools
Control method Auxiliary output Control output 1/2 Heater burnout Transfer output Order code (includes supply voltage indication)
96x96 mm model 48x96 mm model
Basic 2 alarm relays none fitted, 2 slots 1-phase E5AN-HAA2HBM-500 AC100-240 E5EN-HAA2HBM-500 AC100-240
none fitted, 2 slots E5AN-HAA2HBMD-500 AC/DC24 E5EN-HAA2HBMD-500 AC/DC24
2 SSR output fitted E5AN-HSS2HBM-500 AC100-240 E5EN-HSS2HBM-500 AC100-240
2 SSR output fitted E5AN-HSS2HBMD-500 AC/DC24 E5EN-HSS2HBMD-500 AC/DC24
none fitted, 2 slots 3-phase 4 to 20 mA
output
E5AN-HAA2HHBFM-500 AC100-240 E5EN-HAA2HHBFM-500 AC100-240
none fitted, 2 slots E5AN-HAA2HHBFMD-500 AC/DC24 E5EN-HAA2HHBFMD-500 AC/DC24
2 SSR output fitted E5AN-HSS2HHBFM-500 AC100-240 E5EN-HSS2HHBFM-500 AC100-240
2 SSR output fitted E5AN-HSS2HHBFMD-500 AC/DC24 E5EN-HSS2HHBFMD-500 AC/DC24
3 alarm relays none fitted, 2 slots E5AN-HAA3BFM-500 AC100-240 E5EN-HAA3BFM-500 AC100-240
none fitted, 2 slots E5AN-HAA3BFMD-500 AC/DC24 E5EN-HAA3BFMD-500 AC/DC24
2 SSR output fitted E5AN-HSS3BFM-500 AC100-240 E5EN-HSS3BFM-500 AC100-240
2 SSR output fitted E5AN-HSS3BFMD-500 AC/DC24 E5EN-HSS3BFMD-500 AC/DC24
Valve controller 2 alarm relays 2 relay output fitted E5AN-HPRR2BM-500 AC100-240 E5EN-HPRR2BM-500 AC100-240
E5AN-HPRR2BMD-500 AC/DC24 E5EN-HPRR2BMD-500 AC/DC24
4 to 20 mA
output
E5AN-HPRR2BFM-500 AC100-240 E5EN-HPRR2BFM-500 AC100-240
E5AN-HPRR2BFMD-500 AC/DC24 E5EN-HPRR2BFMD-500 AC/DC24
SV programmer
(8 programs of
32 segments
2 alarm relays none fitted, 2 slots 1-phase E5AN-HTAA2HBM-500 E5EN-HTAA2HBM-500 AC100-240
E5AN-HTAA2HBMD-500 E5EN-HTAA2HBMD-500 AC/DC24
3-phase 4 to 20 mA
output
E5AN-HTAA2HHBFM-500 E5EN-HTAA2HHBFM-500
E5AN-HTAA2HHBFMD-500 E5EN-HTAA2HHBFMD-500
3 alarm relays E5AN-HTAA3BFM-500 E5EN-HTAA3BFM-500
E5AN-HTAA3BFMD-500 E5EN-HTAA3BFMD-500
SV programmer and
valve controller
2 alarm relays 2 relay output fitted E5AN-HTPRR2BM-500 E5EN-HTPRR2BM-500
E5AN-HTPRR2BMD-500 E5EN-HTPRR2BMD-500
4 to 20 mA
output
E5AN-HTPRR2BFM-500 E5EN-HTPRR2BFM-500
E5AN-HTPRR2BFMD-500 E5EN-HTPRR2BFMD-500
Supply voltage 100 to 240 VAC 50/60 Hz or 24 VAC, 50/60Hz; 24 VDC
Sensor input Thermocouple: K, J, T, E, L, U, N, R, S, B, W or PL II
Platinum resistance thermometer: Pt100 or JPt100
Current input: 4 to 20 mA or 0 to 20 mA
Voltage input: 1 to 5 V, 0 to 5 V or 0 to 10 V
Control mode ON/OFF, 2-PID and valve (PRR)
Accuracy Thermocouple: (± 0.1% of indicated value or ±1°C, whichever
is greater) ± digit max. *1
Platinum resistance thermometer: (± 0.1% of indicated value
or ± 0.5°C, whichever is greater) ± 1 digit max.
Analogue input: ± 0.1% FS ± 1 digit max.
Auto-tuning yes, 40% and 100% MV output limit selection. When using
Heat/Cool: automatic cool gain adjustment
Self-tuning yes
RS-232C/RS-422/RS-485 optional, CompowayF or Modbus selectable
Event input Optional (Standard 2 event input in EN-H/AN-H)
QLP port (USB connection PC) yes
Ambient temperature -10 to 55°C
IP Rating front panel IP66
Sampling period 60 ms
Option Order code
Relay E53-RN
Voltage (pulse) PNP 12VDC E53-QN
Voltage (pulse) NPN 12VDC E53-Q3
Voltage (pulse) NPN 24VDC E53-Q4
Linear 4 to 20 mA E53-C3N
Linear 0 to 20 mA E53-C3DN
Linear 0 to 10 V E53-V34N
Linear 0 to 5 V E53-V35N
Option Order code
RS-232C communications (CompoWay/F/Modbus) E53-EN01
RS-422 communications (CompoWay/F/Modbus) E53-EN02
RS-485 communications (CompoWay/F/Modbus) E53-EN03
event input E53-AKB
Option Order code
USB PC based configuration cable E58-CIFQ1
PC based configuration and tuning software CX-Thermo EST2-2C-MV4
414
E5_R/E5_R-T Advanced and Multi-Loop controllers
Fast, accurate and equipped for
application specific needs
The E5_R series provides you with high accuracy inputs (0.01°C for Pt100) and
a 50 ms sample and control cycle for all four loops. Its unique Disturbance Overshoot
Reduction Adjustment ensures solid, robust control.
• Easy and clear read-out thanks to bright Liquid Crystal Display
• Exceptional versatility – multi-loop control, cascade control, and valve control
• Easy integration with DeviceNet, PROFIBUS or Modbus
• SV programmer optional, 32 programs with up to 256 segments
Ordering information
Note:- Voltage: Specify the power supply specifications (voltage) when ordering.
- Standard = heat and/or cool PID control, valve = valve positioning (relay up/down) (PRR)
- max 2 = 2 loops heat and/or cool or 1 loop cascade, ratio or remote SP
- max 4 = 4 loops heat and/or cool
- 1, 2 or 4 = number of analogue universal input 1 + pot = 1 universal and 1 slide wire feedback from valve
- QC = voltage (pulse) or current (switch), Q = voltage (pulse), C = current, 4R = 4 two pole relay, 2T = two transistor output NPN
Functions Loops Input Output Comms Order code
analogue Event Control Alarm 96x96 mm Supply voltage
standard 1 1 2 2 QC+Q 4R – E5AR-Q4B AC100-240 or DC/AC 24
standard 1 1 2 2 QC+Q 4R RS-485 E5AR-Q43B-FLK AC100-240 –
standard 1 1 6 2 QC+Q 4R RS-485 E5AR-Q43DB-FLK AC100-240 –
standard 1 1 6 4 QC+Q+C+C 4R RS-485 E5AR-QC43DB-FLK AC100-240 or DC/AC 24
standard max 2 2 4 2 QC+Q 4R RS-485 E5AR-Q43DW-FLK AC100-240 –
standard max 2 2 4 4 QC+Q+QC+Q 4R RS-485 E5AR-QQ43DW-FLK AC100-240 or DC/AC 24
standard max 4 4 4 4 QC+Q+QC+Q 4R RS-485 E5AR-QQ43DWW-FLK AC100-240 –
standard 1 1 2 2 C+C 4R – E5AR-C4B AC100-240 or DC/AC 24
standard 1 1 2 2 C+C 4R RS-485 E5AR-C43B-FLK AC100-240 –
standard 1 1 6 2 C+C 4R RS-485 E5AR-C43DB-FLK AC100-240 –
standard max 2 2 4 2 C+C 4R RS-485 E5AR-C43DW-FLK AC100-240 –
standard max 4 4 4 4 C+C+C+C 4R RS-485 E5AR-CC43DWW-FLK AC100-240 or DC/AC 24
valve 1 1 + pot 4 2 R+R 4R – E5AR-PR4DF AC100-240 or DC/AC 24
valve 1 1 + pot 4 4 R+R+QC+Q 4R RS-485 E5AR-PRQ43DF-FLK AC100-240 or DC/AC 24
standard 1 1 2 2 QC+Q 4R DeviceNet E5AR-Q4B-DRT AC100-240 or DC/AC 24
standard 1 1 2 4 QC+Q+C+C 4R DeviceNet E5AR-QC4B-DRT AC100-240 or DC/AC 24
standard max 2 2 – 4 QC+Q+QC+Q 4R DeviceNet E5AR-QQ4W-DRT AC100-240 or DC/AC 24
standard 1 1 2 2 C+C 4R DeviceNet E5AR-C4B-DRT AC100-240 or DC/AC 24
standard max 4 4 – 4 C+C+C+C 4R DeviceNet E5AR-CC4WW-DRT AC100-240 or DC/AC 24
valve 1 1 + pot – 2 R+R 4R DeviceNet E5AR-PR4F-DRT AC100-240 or DC/AC 24
valve 1 1 + pot – 4 R+R+QC+Q 4R DeviceNet E5AR-PRQ4F-DRT AC100-240 or DC/AC 24
SV programmer 1 1 2 2 QC+Q 4R – E5AR-TQ4B AC100-240 or DC/AC 24
SV programmer 1 1 2 2 C+C 4R – E5AR-TC4B AC100-240 or DC/AC 24
SV programmer 1 1 2 2 QC+Q 4R RS-485 E5AR-TQ43B-FLK AC100-240 –
SV programmer 1 1 2 2 C+C 4R RS-485 E5AR-TC43B-FLK AC100-240 –
SV programmer 1 1 10 2 QC+Q 10T RS-485 E5AR-TQE3MB-FLK AC100-240 –
SV programmer 1 1 10 2 C+C 10T RS-485 E5AR-TCE3MB-FLK AC100-240 –
SV programmer 1 1 10 4 QC+Q+C+C 10T RS-485 E5AR-TQCE3MB-FLK AC100-240 or DC/AC 24
SV programmer max 2 2 4 2 QC+Q 4R RS-485 E5AR-TQ43DW-FLK AC100-240 –
SV programmer max 2 2 4 2 C+C 4R RS-485 E5AR-TC43DW-FLK AC100-240 –
SV programmer max 2 2 8 4 QC+Q+QC+Q 10T RS-485 E5AR-TQQE3MW-FLK AC100-240 or DC/AC 24
SV programmer max 4 4 8 4 C+C+C+C 10T RS-485 E5AR-TCCE3MWW-FLK AC100-240 or DC/AC 24
SV programmer max 4 4 8 4 QC+Q+QC+Q 10T RS-485 E5AR-TQQE3MWW-FLK AC100-240 –
SV programmer + valve 1 1 + pot 4 2 R+R 4R – E5AR-TPR4DF AC100-240 or DC/AC 24
SV programmer + valve 1 1 + pot 8 4 R+R+QC+Q 10T RS-485 E5AR-TPRQE3MF-FLK AC100-240 or DC/AC 24
E5_R/E5_R-T Advanced and Multi-Loop controllers
415
19 Temperature controllers
Note:- Voltage: Specify the power supply specifications (voltage) when ordering.
- Standard = heat and/or cool PID control, valve = valve positioning (relay up/down) (PRR)
- max 2 = 2 loops heat and/or cool or 1 loop cascade, ratio or remote SP
- max 4 = 4 loops heat and/or cool
- 1, 2 or 4 = number of analogue universal input 1 + pot = 1 universal and 1 slide wire feedback from valve
- QC = voltage (pulse) or current (switch), Q = voltage (pulse), C = current, 4R = 4 two pole relay, 2T = two transistor output NPN
Accessories
E5_R/E5_R-T optional tools
Specifications
Functions Loops Input Output Comms Order code
analogue Event Control Alarm 48x96 mm Supply voltage
standard 1 1 2 2 QC+Q 4R – E5ER-Q4B AC100-240 or DC/AC 24
standard 1 1 2 2 QC+Q 4R RS-485 E5ER-Q43B-FLK AC100-240 –
standard 1 1 2 4 QC+Q+C+C 4R RS-485 E5ER-QC43B-FLK AC100-240 or DC/AC 24
standard 1 1 6 2 QC+Q 2T RS-485 E5ER-QT3DB-FLK AC100-240 –
standard max 2 2 4 2 QC+Q 2T RS-485 E5ER-QT3DW-FLK AC100-240 or DC/AC 24
standard 1 1 2 2 C+C 4R – E5ER-C4B AC100-240 or DC/AC 24
standard 1 1 2 2 C+C 4R RS-485 E5ER-C43B-FLK AC100-240 –
standard 1 1 6 2 C+C 2T RS-485 E5ER-CT3DB-FLK AC100-240 –
standard max 2 2 4 2 C+C 2T RS-485 E5ER-CT3DW-FLK AC100-240 or DC/AC 24
valve 1 1 + pot 4 2 R+R 2T – E5ER-PRTDF AC100-240 or DC/AC 24
valve 1 1 + pot – 4 R+R+QC+Q 4R RS-485 E5ER-PRQ43F-FLK AC100-240 or DC/AC 24
standard 1 1 2 2 QC+Q 2T DeviceNet E5ER-QTB-DRT AC100-240 or DC/AC 24
standard max 2 2 – 2 QC+Q 2T DeviceNet E5ER-QTW-DRT AC100-240 or DC/AC 24
standard 1 1 2 2 C+C 2T DeviceNet E5ER-CTB-DRT AC100-240 or DC/AC 24
standard max 2 2 – 2 C+C 2T DeviceNet E5ER-CTW-DRT AC100-240 or DC/AC 24
valve 1 1 + pot – 2 R+R 2T DeviceNet E5ER-PRTF-DRT AC100-240 or DC/AC 24
SV programmer 1 1 2 2 QC+Q 4R – E5ER-TQ4B AC100-240 or DC/AC 24
SV programmer 1 1 2 2 C+C 4R – E5ER-TC4B AC100-240 or DC/AC 24
SV programmer 1 1 2 2 QC+Q 4R RS-485 E5ER-TQC43B-FLK AC100-240 or DC/AC 24
SV programmer max 2 2 4 2 QC+Q 2T RS-485 E5ER-TQT3DW-FLK AC100-240 or DC/AC 24
SV programmer max 2 2 4 2 C+C 2T RS-485 E5ER-TCT3DW-FLK AC100-240 or DC/AC 24
SV programmer + valve 1 1 + pot 4 2 R+R 2T – E5ER-TPRTDF AC100-240 or DC/AC 24
SV programmer + valve 1 1 + pot – 3 R+R + QC 4R RS-485 E5ER-TPRQ43F-FLK AC100-240 or DC/AC 24
Terminal covers Order code
Terminal cover for E5AR E53-COV14
Terminal cover for E5ER E53-COV15
Option Order code
PC based configuration and tuning software CX-Thermo EST2-2C-MV4
Thermocouple input type K, J, T, E, L, U, N, R, S, B, W
RTD input type Pt100
Linear input type mA, V
Control mode 2-PID or ON/OFF control
Accuracy ±0.1% FS
Auto-tuning yes
RS-485 optional
Event input optional
Ambient temperature -10 to 55°C
IP rating front panel IP66
Sampling period 50 ms
Size in mm (HxWxD) E5ER: 96x48x110
E5AR: 96x96x110
416
PRT1-SCU11 Auxiliaries
Omron’s intelligent PROFIBUS and
CompoWay/F gateway
This gateway supports all CompoWay/F equipped products, including
temperature controllers, digital panel indicators, etc. It can also be used for
connecting MCW151-E and E5_K series.
• Cost-effectively integrates basic instruments into a PROFIBUS network
• Requires no complex protocol conversion writing
• Has function blocks for drag-and-drop configuration
• Connects up to 15 instruments to a single PROFIBUS point
Ordering information
Supports all CompoWay/F equipped units,
but has "drag-and-drop" function blocks for
• E5AN/E5EN/E5CN/E5GN
• E5ZN and CelciuXº (EJ1)
• E5AR/E5ER
• E5AK/E5EK
Specifications
ES1B
Achieve low-cost measurements with an
infrared thermosensor
This infrared thermosensor provides an accurate, stable and cost-effective way to
measure the temperature of objects. It behaves just like a standard K-type thermocouple,
which enables it to operate with any temperature controller or alarm unit.
• Cost-effective infrared thermosensor
• Contactless, meaning no deterioration, unlike thermocouples
• 4 temperature ranges available: 10-70°C, 60-120°C, 115-165°C and 140-260°C
• Response speed 300 ms
Ordering information
Dimensions (unit: mm)
Specifications
Name Order code
PROFIBUS remote terminal serial communications unit PRT1-SCU11
Storage temperature -20 to +75°C
Ambient temperature 0 to 55°C
Ambient humidity 10 to 90% (non-condensing)
EMC compliance EN 50081-2, EN 61131-2
Power supply +24 VDC (+10%/-15%)
Current consumption 80 mA (typical)
Weight 125 g (typical)
Communication interface RS-485 based PROFIBUS-DP
RS-422A Host link
RS-485 CompoWay/F
RS-232C Peripheral
Port supporting connection to thermotools
Size in mm (HxWxD) 90x40x65
Appearance and sensing
characteristics
Specification Order code
10 to 70°C ES1B 10-70C
60 to 120°C ES1B 60-120C
115 to 165°C ES1B 115-165C
140 to 260°C ES1B 140-260C 2 dia. 20 dia.
2 mm 20 mm 40 mm 60 mm
40 dia. 60 dia.
14.2 dia.
36.5
17.8
15
6.5
44.5 3,000
ABS resin
PVC-covered
(−25°C to 70°C)
Polyolefin tube
Screw M18×1.0
Green, output +
White, output −
Orange, power +
Shield, power −
Power supply voltage 12/24 VDC
Current consumption 20 mA max.
Accuracy ±5°C ±2% PV or ±2°C, whichever is larger
±10°C ±4% PV or ±4°C, whichever is larger
±30°C ±6% PV or ±6°C, whichever is larger
±40°C ±8% PV or ±8°C, whichever is larger
Reproducibility ±1% PV or ±1°C, whichever is larger
Temperature drift 0.4°C/°C max.
Receiver element Thermopile
Response speed Approximately 300 ms at response rate of 63%
Operating temperature -25 to 70°C (with no icing or condensation)
Allowable ambient humidity 35 to 85%
Degree of protection IP65
Size in mm head: 17.8 dia.×44.5 (screw M18×1.0),
cable 3,000
417
19 Temperature controllers
ES1C Auxiliaries
Achieve Superior Environmental Resistance
and a Wide Measurement Range of 0 to
400°C.
This gateway supports all CompoWay/F equipped products, including
temperature controllers, digital panel indicators, etc. It can also be used for
connecting MCW151-E and E5_K series.
• Flexible placement with slim cylindrical shape and long focus with a distance of
500 mm and area diameter of 80 mm.
• The SUS body and silicon lens resist ambient operating temperatures of up to
70×C and resist dust and water to the equivalent of IP67.
• Fast measurement with high-speed response of 100 ms/90%.
• Strong resistance to noise with output of 4 to 20 mA.
Ordering information
Measurement Range
Ratings and Characteristics
Dimensions (unit: mm)
Specification (measuring temperature range) Order code
0 to 400°C ES1C-A40
110 dia.
80 dia. 70 dia.
300
500
1000
[mm]
Note: The measurement range is the measurement diameter for an optical response of
90%. Make sure that the actual object to be measured is sufficiently larger than the
measurement diameters in the above figure.
Item Model ES1C
Power supply voltage 12 to 24 VDC
Operating voltage range 90% to 110% of rated voltage
Current consumption 70 mA max.
Measuring temperature range 0 to 400C
Measurement accuracy 0 to 200C: 2C, 201 to 400C: 1% (emissivity: 0.95)
Response time 100 ms/90%
Reproducibility 1C of reading value
Measurement wavelength 8 to 14 m
Light-receiving element Thermopile
Emissivity 0.95 fixed
Current output 4 to 20 mA DC, Load: 250 max.
Ambient temperature range Operating: 0 to 70C, Storage: 20 to 70C
(with no icing or condensation)
Ambient humidity range Operating and storage: 35% to 85%
Vibration resistance
(destruction)
1.5-mm amplitude at 10 to 55 Hz for 2 hours each
in the X, Y, and Z directions
Weight 180 g
Degree of protection Equivalent to IP67
12 dia. (lens diameter)
M18×P1.0
(cable length)
24 120 2,000
60
(threaded section)
S8VS S8JX-G
Compact
S8VT
Single-phase
Supply voltage?? Power factor correction??
Three-phase
Slim
S8VM
Yes No
PREVENT YOUR SYSTEM FROM STOPPING
The buffer block prevents equipment stoppage, data loss and other problems resulting
from momentary power failures. One S8TS-DCBU-02 buffer block provides a back-up
time of 500 ms at an output current of 2.5 A. Can be wired to the 24 VDC output from
any switch mode power supply
• Connects to both single-phase and three-phase 24 VDC power supplies
• Connects to an S8TS power supply via an S8T-BUS03 bus line connector
• Parallel connection up to 4 units to increase back-up time and capacity
S8TS-DCBU-02 – Buffer block against momentary power failures
418
Page 422 Page 427
Power supplies
Page 423 Page 424
S8TS
Which type of power supply you are looking for?
S8T-DCBU-01
Modular
S8T-DCBU-02
DC back-up
S8TS DC battery
back-up up to
several minutes
S8TS buffer block
momentary up to
500 ms
419
20 Power supplies
Page 425 Page 426 Page 426
420
421
20 Power supplies
Selection table Power supplies
Category Compact
Power Supplies Slim Power Supplies Modular
Selection criteria
Model S8VS S8VT S8VM S8JX-G S8TS
Phases Single-phase
Rated voltage 100 to 240 VAC
Voltage 24 V 24 V 12 V 24 V 5 V 12 V 15 V 24 V 5 V 12 V 24 V
Power
3 W – – – – – – – – – – –
7.5 W – – – – – – – – – – –
10 W – – – – – – – – – – –
15 W 0.65 A – 1.3 A 0.65 A 3 A 1.3 A 1 A 0.65 A – – –
25 W – – – – – – – – 5 A – –
30 W 1.3 A – 2.5 A 1.3 A – – – – – 2.5 A –
35 W 7 A 3 A 2.4 A 1.5 A – 2.5 A –
50 W – – 4.3 A 2.2 A 10 A 4.2 A – 2.1 A – – –
60 W 2.5 A – – – – – – – – 5 A 2.5 A
90 W – – – – – – – – – 7.5 A –
100 W – – 8.5 A 4.5 A 20 A 8.5 A – 4.5 A – – –
120 W 5 A 5 A – – – – – – – 10 A 5 A
150 W – – 12.5 A 6.5 A – – – 6.5 A – – –
180 W – – – – – – – – – – 7.5 A
240 W 10 A 10 A – – – – – – – – 10 A
300 W – – 27 A 14 A – – – 14 A – – –
480 W 20 A 20 A – – – – – – – – –
600 W – – 53 A 27 A – – – 27 A – – –
960 W – 40 A – – – – – – – – –
1500 W – – – 70 A – – – – – – –
Features
Conforms to
EN61000-3-2
with PFC – – – – with
PFC
with
PFC
with
PFC
DC back-up – – – – – – – –
Capacitor back-up – – – – – – – –
Undervoltage alarm – – – – – –
Overvoltage protection
Overload protection
DIN-rail mounting
Screw mounting
(with bracket)
– only 40 A – – –
EMI Class B – – – – – –
UL Class 2 only 60 W – – – – – – –
N+1 redundancy – – – – – – – –
Parallel operation – – – – – – –
Series operation
Page 422 427 423 424 425
Standard Available – No/not available
422
S8VS Single-phase
Compact power supply
The S8VS is our standard industrial din-rail mounted power supply. It is built to last
forever. Up to 60 W we provide them into a plastic housing, from 120 W the S8VS
is built in strong metal case. The full ranges provide a very good dimension/output
power ratio to optimize panel space uses. The range covers 6 models at 24 VDC with
wattage of 15, 30, 60, 120, 240 and 480 W. The 15 and 30 W are also available in
5 or 12 VDC output voltage. The range withstands high vibration and shocks.
The S8VS are fan-less power supplies.
• Wide AC input range from 85 to 264 VAC
• Micro S8VS output power range 15 and 30 W at 5, 12 and 24 VDC
• Micro can mounted, standard din-rail, horizontal or facing horizontal
any direction is okay
• S8VS models available from 60 to 480 W at 24 VDC, 4 models
Ordering information
Specifications
Power Output voltage Output current Under-voltage control Size in mm (HxWxD) Order code
15 W 5 VDC 2 A (10 W) yes, red LED 85x22.5x96.4 S8VS-01505
12 VDC 1.2 A S8VS-01512
24 VDC 0.65 A S8VS-01524
30 W 5 VDC 4 A (20 W) yes, red LED 85x22.5x96.4 S8VS-03005
12 VDC 2.5 A S8VS-03012
24 VDC 1.3 A S8VS-03024
60 W 24 VDC 2.5 A no 95x40x108.3 S8VS-06024
120 W 24 VDC 5 A no 115x50x121.3 S8VS-12024
240 W 24 VDC 10 A no 115x100x125.3 S8VS-24024
480 W 24 VDC 20 A no 115x150x127.2 S8VS-48024
Specification 15 W 30 W 60 W 120 W 240 W 480 W
Efficiency 77% min. (24 V) 80% min. (24 V) 78% min. 80% min. 80% min. 83% min.
Power factor – – – 0.95 min. 0.95 min. 0.95 min.
Input voltage 100 to 240 VAC (85 to 264 VAC), single-phase
Output
voltage
Voltage adjustment ±10 to ±15% (with V. ADJ) min.
Ripple 2% p-p max. (at rated input/output voltage)
Input variation 0.5% max. (at 85 to 264 VAC input, 100% load)
Temperature
influence
0.05%/°C max.
Overload protection 105 to 160% of rated load current, voltage drop, automatic reset
Overvoltage protection yes yes yes yes yes yes
Input
current
100 V 0.45 A max. 0.9 A max. 1.7 A max. 1.9 A max. 3.8 A max. 7.4 A max.
200 V 0.25 A max. 0.6 A max. 1.0 A max. 1.1 A max. 2.0 A max. 3.9 A max.
230 V 0.19 A
(5 V: 0.14 A)
0.37 A
(5 V: 0.27 A)
0.7 A typ. 0.6 A typ. 1.2 A typ. 2.4 A typ.
Output indicator yes (green) yes (green) yes (green) yes (green) yes (green) yes (green) LED
Weight 160 g 180 g 330 g 550 g 1,150 g 1,700 g max.
Operating temperature -10 to 60°C -10 to 60°C *1
*1 For 30 W model 24 V: No derating, 12 & 5 V: Derating beyond 50°C.
-10 to 60°C, derating beyond 40°C, no icing or condensation
Series operation yes (24 V only) yes yes yes yes yes
423
20 Power supplies
S8VM Single-phase
Slim size S8VM power supplies
All models have the same height of only 84.5 mm. These ranges cover up-to
1,500 W. The output voltages are 5, 12, 15 or 24 VDC. In this series we have standard
types and versions with two alarms up-to 150 W models: one for short dip in the
24 VDC supply, second one when the voltage gradually drops in time. The models
form 300 W/600 W/1,500 W are equipped with an overload alarm function.
• Widest range in DC-output voltage (5 V, 12 V, 15 V & 24 V) & wattage
(15 up-to 1,500 W)
• LED indication power ON
• Transistor output & LED indication under-voltage alarm 1 & 2 or Power failure
• All models can be Din-rail mounted (except 1,500W)
• EMI Class B, UL Class 1 division 2, SEMI-F47 (200VAC input)
Ordering information
Specifications
Power ratings Output voltage Output current Size in mm (HxWXD) Order code
DIN-rail mounting Undervoltage alarm type
Sinking (NPN) Sourcing (PNP)
15 W 12 V 1.3 A 84.5x35.1x94.4 S8VM-01512CD – –
24 V 0.65 A S8VM-01524CD S8VM-01524AD *1
*1 No alarm output built-in.
30 W 12 V 2.5 A 84.5x35.1x109.4 S8VM-03012CD – –
24 V 1.3 A S8VM-03024CD S8VM-03024AD *1
50 W 12 V 4.3 A 84.5x35.1x124.5 S8VM-05012CD – –
24 V 2.2 A S8VM-05024CD S8VM-05024AD S8VM-05024PD
100 W 12 V 8.5 A 84.5x36.6x164.5 S8VM-10012CD – –
24 V 4.5 A S8VM-10024CD S8VM-10024AD S8VM-10024PD
150 W 12 V 12.5 A 84.5x45.6x164.5 S8VM-15012CD – –
24 V 6.5 A S8VM-15024CD S8VM-15024AD S8VM-15024PD
Power ratings Output voltage Output current Size in mm (HxWXD) Bottom mounting DIN-rail adaptor Power failure output
300 W 12 V 27 A 84.5x62.5x188 S8VM-30012C S82Y-VM30D overload,
overvoltage
and overheat
24 V 14 A S8VM-30024C
600 W 12 V 53 A 84.5x101.8x192 S8VM-60012C S82Y-VM60D
24 V 27 A S8VM-60024C –
1,500 W 24 V 70 A 84.5x126.5x327 S8VM-15224C – –
Item 15 W 30 W 50 W 100 W 150 W 300 W 600 W 1,500 W
Efficiency 12 V models 78% min. 79% min. 79% min. 81% min. 81% min. 78% min. 79% min. –
24 V models 80% min. 81% min. 80% min. 82% min. 83% min. 81% min. 81% min. 82% min.
Input voltage 100 to 240 VAC, (85 to 264 VAC), single phase
Output Voltage adjustment -20% to 20% with V. ADJ min. (S8VM-_ _ _ 24A_ /P_ : -10% to 20%)
Ripple 12 V models 1.5% (p-p) max. 1.5% (p-p) max. 2.0% (p-p) max. –
24 V models 1.0% (p-p) max. 0.75% (p-p) max. 1.25% (p-p) max. 1.25% (p-p) max.
Input variation 0.4% max.
Temperature influence 0.02%/°C max.
Overload protection 105% to 160% of rated load current, voltage drop, automatic reset
Overvoltage protection yes
Output indicator yes (green)
Weight 180 g max. 220 g max. 290 g max. 460 g max. 530 g max. 1,100 g max. 1,700 g max. 3,800 g max.
Series operation yes
Remote sensing function no no no yes
424
S8JX-G Single-phase
Slim & economic power supply
The S8JX-G is Omron’s cost effective power supply delivering Omron’s quality and
reliability. The range of this Power Supply covers up to 600 W, the output voltages are
5, 12 or 24 VDC. The low profile and multiple mounting options help you reduce panel
space. With a minimum life expectancy of 10 years and protection against over-voltage,
over-current and short circuiting, the S8JX-G is as reliable as you may expect
from Omron.
• Wide range in DC-output voltage (5 V, 12 V, 15 V & 24 V) & wattage (15 to 600 W)
• LED indication power ON
• Over-voltage, over-current, and short circuit protection
• Vibration resistance 4,5 g
• All models can be DIN-rail mounted
• Approvals: UL, cUL, UL508 Listed, CE, SEMI F47, VDE
Ordering information
Specifications
Power Output voltage Output current Size in mm (HxWxD) Order code
15 W 5 V 3 A 91x40x90 S8JX-G01505CD
12 V 1.3 A S8JX-G01512CD
15 V 1 A S8JX-G01515CD
24 V 0.65 A S8JX-G01524CD
35 W 5 V 7 A 91x40x90 S8JX-G03505CD
12 V 3 A S8JX-G03512CD
15 V 2.4 A S8JX-G03515CD
24 V 1.5 A S8JX-G03524CD
50 W 5 V 10 A 92x40x100 S8JX-G05005CD
12 V 4.2 A S8JX-G05012CD
24 V 2.1 A S8JX-G05024CD
100 W 5 V 20 A 92x50x150 S8JX-G10005CD
12 V 8.5 A S8JX-G10012CD
24 V 4.5 A S8JX-G10024CD
150 W 24 V 6.5 A 92x50x150 S8JX-G15024CD
300 W 24 V 14 A 92x110x167 S8JX-G30024CD
600 W 24 V 27 A 92x150x160 S8JX-G60024C*1
*1 Additional accessory is required for DIN-rail mounting.
Item 15 W 35 W 50 W 100 W 150 W 300 W 600 W
Efficiency 100 to 240 V input 68% min. 73% min. 76% min. 76% min. 86% min. – –
100/200 V (Selected) – – – – – 82% min. 80% min.
Input voltage 100 to 240 VAC (85 to 264 VAC) 100 to 120 VAC (85 to 132 VAC)
200 to 240 VAC (170 to 264 VAC)
(Switchable)
100 to 370 VDC
Note: This range is not applicable for the safety standards.
Output Voltage adjustment -10% to 15% (with V. ADJ)
Ripple 2% (p-p) max.
Input variation 0.4% max.
Temperature influence 0.05%/°C max. (at rated input and output) 0.05%/°C max.
Overload protection 105% to 160% of rated load current, voltage drop, intermittent, automatic reset 105% of rated load
current, voltage
drop, intermittent,
automatic reset
105% of rated load
current, Inverted L
voltage drop, the circuit
will be shut OFF
when the overload
exceeds 5 s.
Overvoltage protection yes
Output indicator yes (green)
Weight 250 g max. 250 g max. 300 g max. 550 g max. 600 g max. 1,600 g max. 2,500 g max.
Series operation yes (For up to two Power Supplies; external diodes required.)
425
20 Power supplies
S8TS Single-phase
Industrial use, modular power supply for
multiple configurations
The S8TS is an expandable power supply; standard units can easily be snapped
together in parallel to provide you with ultimate flexibility. Expandable up to 4 units,
it can deliver a total power of 240W at 24VDC or a multi-output configuration.
• Improves system reliability by building up N+1 redundancy
• Standard unit; 60 W at 24 VDC, 30 W at 12 VDC and 25 W at 5 VDC
• Battery back-up unit protects against power outage (see accessories)
• Buffer unit protects against power glitches and outage (see accessories)
• EMI Class B, UL Class 2, UL Class 1 division 2
Ordering information
Accessories
Specifications
Basic block Order code
Output
voltage
Output current Screw terminal type Connector terminal type
With bus line connectors*1
*1 One S8T-BUS01 connector and one S8T-BUS02 connector are included as accessories.
Without bus line connectors*2
*2 Bus line connectors can be ordered separately if necessary.
With bus line connectors*1 Without bus line connectors*2
24 V 2.5 A S8TS-06024-E1*3
*3 Conforms to EMI class B with DC minus terminal ground.
S8TS-06024 S8TS-06024F-E1 S8TS-06024F
12 V 2.5 A S8TS-03012-E1 S8TS-03012 S8TS-03012F-E1 S8TS-03012F
5 V 5 A – S8TS-02505 – S8TS-02505F
Bus line connector
Type Number of connectors Order code
AC line + DC line bus
(For parallel operation)
1 connector S8T-BUS01
10 connectors*1
*1 One package contains 10 S8T-BUS01 connectors.
S8T-BUS11
AC line bus (For series operation
or isolated operation)
1 connector S8T-BUS02
10 connectors*2
*2 One package contains 10 S8T-BUS02 connectors.
S8T-BUS12
Item 5 V models 24/12 V models
Single operation Single operation Parallel operation
Efficiency 62% min. 24 V models: 75%, 12 V models: 70% min.
Power factor 0.8 min. 24 V models: 0.9 min., 12 V models: 0.8 min.
Input voltage 100 to 240 VAC, (85 to 264 VAC), single-phase
Output
voltage
Voltage adjustment 5 V ±10% min. 24 V models: 22 to 28 V, 12 V models: 12 V ±10% min.
Ripple 2% (p-p) max. 2% (p-p) max. 2% (p-p) max.
Input variation 0.5% max. – –
Temperature influence 0.05%/°C max. (with rated input, 10 to 100% load)
Overcurrent protection 105 to 125% of rated load current, inverted L drop, automatic reset
Overvoltage protection yes yes yes
Output indicator yes (green) yes (green) yes (green)
Weight 450 g max. 450 g max. 450 g max.
Series operation yes yes yes
Parallel operation no yes yes
Size in mm (HxWxD) 120x43x120
426
S8T-DCBU-01/-02 Single-phase
S8T-DCBU-01
The S8T-DCBU-01 battery backup block supplies 24 VDC for a fixed period of time
during AC input outages to considerably improve system reliability.
• Supplies 24 VDC for a long period of time during AC input outages
• For system reliability improvement
• Block power supply basic block is connected by the bus line connector
• Simple system configuration
• Alarms indicated on main unit and via alarm signal output
Ordering information
Note:The S8TS DC back-up block is for S8TS power supplies only.
Specifications
S8T-DCBU-02
Prevents equipment stoppage, data loss and other problems resulting from
momentary power failures. One S8T-DCBU-02 buffer block provides a back-up time
of 500 ms at an output current of 2.5 A. Can be wired to the 24 VDC output from any
switch mode power supply.
• Connects to all Omron power supplies: S8TS, S8VS, S82J, S82K, S8VM, S8PE
• Connects to both single-phase and three-phase power supplies
• Connects to an S8TS power supply via an S8T-BUS03 bus line connector
• Parallel connection up to 4 units to increase back-up time and capacity
• Complies with Semi F47-0200 standard
Ordering information
Accessories
Specifications
Product Input voltage Output voltage Output current Order code
DC back-up block 24 to 28 VDC 24 V 3.7 A/8 A S8T-DCBU-01
Battery holder – – – S82Y-TS01
Product Input voltage Output voltage Output current Type Order code
Basic block
(use together with the DC
back-up block)
100 to 240 VAC 24 V 2.5 A Screw
terminal type
With bus line connectors S8TS-06024-E1
Without bus line connectors S8TS-06024
Connector
terminal type
With bus line connectors S8TS-06024F-E1
Without bus line connectors S8TS-06024F
Product Back-up time Overcurrent protection
operating point selector
Order code
Battery 8 min./3.7 A 5.7 A (typ.) – LC-R122R2PG
4 min./8.0 A 5.7 A (typ.) 11.7 A (typ.) LC-R123R4PG
Item Size in mm (HxWxD)
S8T-DCBU-01 120x43x130
Battery holder 82x185.7x222.25
Input voltage Output voltage (during back-up operation) Output current Order code
24 VDC (24 to 28 VDC) 22.5 V 2.5 A S8T-DCBU-02
Type Number of connectors Order code
DC bus line connector (for use with S8TS only) 1 connector S8T-BUS03
10 connectors S8T-BUS13
Item Size in mm(HxWxD)
S8T-DCBU-02 120x43x120
427
20 Power supplies
S8VT Three-phase
Compact 3-phase input power supply
To make the compact power supply range complete we have our 3-phase S8VT
series, which give you the best power to footprint ratio. The range exists of 4 models
with wattage of 120, 240, 480 and 960 W all at 24 VDC. This version is constructed
from a very robust metal housing and all models are din-rail mounting. The input
range cover 3 phase voltage input from 340 to 576 VAC and single phase DC input
from 480 to 810 VDC.
• 5, 10, 20 and 40A; 24VDC output
• 3-phase input (340-576VAC) or 1-phase 480 to 810 VDC
• Compact design with best footprint on the market
• UL60950 (CSA22.2-60950), UL508 listing (CSA22.2-14) and CE
• Parallel & serial operation possible (all models)
Ordering information
Specifications
Power ratings Output voltage Output current Size in mm (HxWxD) Order code
120 W 24 V 5 A 125x45x130 S8VT-F12024E
240 W 24 V 10 A 170x45x130 S8VT-F24024E
480 W 24 V 20 A 170x100x130 S8VT-F48024E
960 W 24 V 40 A 170x195x130 S8VT-F96024E
Item 5 A 10 A 20 A 40 A
Efficiency 88% 90% 91% 91%
Voltage range 340 to 576 VAC 3 AC resp, 480 to 810 VDC (1 phase)
Output
voltage
Voltage adjustment 22.5 to 26.4 VDC min.
Ripple 100 mV max.
Input variation ±0.5% max.
Temperature
influence
Less than 0.05%/°C
Overload protection yes
Overvoltage protection yes
Output indicator yes (green)
Weight 750 g 1.0 kg 1.8 kg 3.3 kg
Series operation yes (for 2 units)
Parallel operation yes (for 2 units)
H2C
Motor timer
WHEN TIMING ACCURACY MATTERS!
The H5CX series offers multiple-functions and -timing ranges for precise timing control, as well as
real twin-timing and memory function. These and other added-value features ensure that the H5CX
covers almost every possible user requirement in timers.
• 15 different time functions
• Three colour display value, red, orange or green
• Models with instantaneous contact outputs
• 0.001 s to 9999 h, 10 ranges
H5CX – The most complete digital timer
428
Page 437
Timers
H3DK
22.5 mm
H3DS H3CR
17.5 mm
Which size is required?
Which mounting method is required?
Which type of timer is needed?
H3YN
DIN-rail Plug/front
Analogue
H5CX
48x24 mm 48x48 mm
Which size is required?
Digital
H8GN
timer/counter
429
21 Timers
Page 432 Page 433 Page 434 Page 435 Page 445 Page 436
430
Selection table
Category Analogue solid state timer
Selection criteria
Model H3DS-M H3DS-S H3DS-A H3DS-F H3DS-G H3DS-X H3DK-M H3DK-S H3DK-F H3DK-G H3DK-H
Mounting DIN-rail
Size 17.5 mm 22.5 mm
Type Multi-functional Twin timer Star-delta Two-wired Multi-functional Twin
timer
Star-delta Power
OFF-delay
Contact configuration
Time limit
Instantaneous – – – – – – – – –
Programmable
contacts
– – – – – – – – –
14 pins – – – – – – – – – – –
11 pins – – – – – – – – – – –
8 pins – – – – – – – – – – –
Screw terminals
Screw-less clamp
terminals
– – – – –
Screw-less clamp
sockets
– – – – – – – – – – –
Inputs
Voltage input – – – – – –
Outputs
Transistor – – – – – – – – – – –
Relay –
SCR – – – – – – – – – –
Relay
output
type
SPDT – – (2x)
SPST-NO – – – – (2x) – – – – – –
DPDT – – – – – – – – –
4PDT – – – – – – – – – – –
Features
Time
range
Total time
range
0.1 s to
120 h
1 s to 120 h 2 s to 120 h 0.1 s to 12 h 1 s to 120 s 0.1 s to
120 h
0.1 s to
1,200 h
0.1 s to
1,200 h
0.1 s to
1,200 h
1 s to 120 s 0.1 s to 120 s
Number of
sub ranges
7 7 7 6 2 7 12 12 8 2 2 (model
dependent)
Supply voltage 24 to
230 VAC or
24 to
48 VDC
24 to
230 VAC or
24 to
48 VDC
24 to
230 VAC or
24 to
48 VDC
24 to
230 VAC or
24 to
48 VDC
24 to
230 VAC or
24 to
48 VDC
24 to
230 VAC or
24 to
48 VDC
24 to
240 VAC/DC
or 12 VDC
24 to
240 VAC/DC
or 12 VDC
24 to
240 VAC/DC
or 12 VDC
24 to
240 VAC/DC,
240 to
440VAC,
12 VDC
100 to
120 VAC, 200
to 240 VAC,
24 to
48 VAC/DC
Number of operating
modes
8 4 1 2 1 1 8 4 1 1 1
Functions
ON-delay – – – – – –
Flicker OFF start – – – – – – –
Flicker ON start – – – – –
Signal
ON-/OFF-delay
– – – – – – – – –
Signal OFF-delay – – – – – – – –
Interval (signal or
power start)
– – – – – – –
One-shot output
(ON-delay)
– – – – – – –
ON-delay (fixed) – – – – – – – – –
Independent
ON/OFF time setting
– – – – – – – – – – –
Star-delta – – – – – – – – – –
Remarks
Transistor – – – – – – – – – –
Page 432 433
Timers
431
21 Timers
Category Analogue solid state timer Digital timer Motor timer
Selection criteria
Model H3YN H3CR-A H3CR-F H3CR-G H3CR-H H5CX H8GN H2C
Mounting Socket/on panel
Size 21.5 mm 1/16 DIN 1/32 DIN 1/16 DIN
Type Miniature Multifunctional
Twin timer Star-delta Power
OFF-delay
Multifunctional
Preset counter/
timer
Motor timer
Contact configuration
Time limit
Instantaneous – – –
Programmable
contacts
– – – – – –
14 pins – – – – – – –
11 pins – –
8 pins –
Screw terminals – – – – –
Screw-less clamp
terminals
– – – – – – – –
Screw-less clamp
sockets
– – – – – – –
Inputs
Voltage input – – – – – – –
Outputs
Transistor – – – – – –
Relay
SCR – – – – – – – –
Relay
output
type
SPDT – – –
SPST-NO – – – (2x) – – – –
DPDT – – – –
4PDT – – – – – – –
Features
Time
range
Total time
range
0.1 s to 10 h
(model
dependent)
0.05 s to 300 h,
0.1 s to 600 h
(model
dependent)
0.05 s to 30 h or
1.2 s to 300 h
(model
dependent)
0.5 s to 120 s 0.05 s to 12 s, 1.2
s to 12 min
0.001 s to 9999 h
(configurable)
0.000 s to 9999 h
(configurable)
0.2 s to 30 h
Number of
sub ranges
2 9 14 4 4 10 9 15
Supply voltage 24, 100 to 120,
200 to 230 VAC,
12, 24, 48, 100 to
110, 125 VDC
100 to 240 VAC,
100 to 125 VDC,
24 to 48 VAC,
12 to 48 VDC
100 to 240 VAC,
12 VDC,
24 VAC/DC, 48 to
125 VDC
100 to 120 VAC,
200 to 240 VAC
100 to 120 VAC,
200 to 240 VAC,
24 VAC/DC,
48 VDC, 100 to
125 VDC
100 to 240 VAC,
24 VAC,
12 to 24 VDC
24 VDC 24, 48, 100, 110,
115, 120, 200,
220, 240 VAC
Number of operating
modes
4 6 (model
dependent)
– 1 1 15 6 2
Functions
ON-delay – – –
Flicker OFF start – – –
Flicker ON start – – – –
Signal
ON-/OFF-delay
– – – – – –
Signal OFF-delay – – –
Interval (signal or
power start)
– – – –
One-shot output (ONdelay)
– – – – – –
ON-delay (fixed) – – – – – – –
Independent
ON/OFF time setting
– – – – – –
Star-delta – – – – – – –
Remarks
Transistor – – – – – –
Page 434 435 436 445 437
Standard Available – No/not available
432
H3DS Analogue solid state timers
DIN-rail mounted, standard 17.5 mm wide
solid state timer range
This broad range of timers includes many functionalities and has a wide AC/DC power
supply range. Models with screwless clamp connection available.
• 17.5 mm width, modular 45 mm
• DIN-rail mounting
• 24-48 VDC and 24-230 VAC
• 0.1 s to 120 h, 7 ranges
Ordering information
Specifications
Type Supply voltage Control output Time setting
range
Operating modes Order code
Screw
terminal type
Screw-less
clamp type
Multi-functional timer 24 to 230 VAC
(50/60 Hz)/
24 to 48 VDC
SPDT 0.1 s to120 h ON-delay, flicker OFF start, flicker ON start,
signal ON/OFF-delay, signal OFF-delay,
interval, one-shot
H3DS-ML H3DS-MLC
Standard timer ON-delay, flicker ON start, interval, oneshot
H3DS-SL H3DS-SLC
Single function timer ON-delay H3DS-AL H3DS-ALC
Twin timer Relay SPDT 0.1 s to 12 h Flicker OFF start, flicker ON start H3DS-FL H3DS-FLC
Star-delta timer 2x Relay SPST-NO 1 s to 120 s Star-delta H3DS-GL H3DS-GLC
Two-wired timer 24 to 230 VAC/VDC
(50/60 Hz)
SCR output 0.1 s to 120 h ON-delay H3DS-XL H3DS-XLC
Terminal block Screw terminal type: Clamps two 2.5 mm2 max. bar terminals without sleeves
Screw-less clamp type: Clamps two 1.5 mm2 max. bar terminals without sleeves
Mounting method DIN-rail mounting
Operating voltage range 85 to 110% of rated supply voltage
Power reset Minimum power-off time: 0.1 s, 0.5 s for H3DS-G
Reset voltage 2.4 VAC/VDC max., 1.0 VAC/VDC max. for H3DS-X
Voltage input Max. permissible capacitance between input lines (terminals B1 and A2): 2,000 pF
Load connectable in parallel with inputs (terminals B1 and A1)
H-level: 20.4 to 253 VAC/20.4 to 52.8 VDC
L-level: 0 to 2.4 VAC/VDC
Control output Contact output: 5 A at 250 VAC with resistive load (cos = 1)
5 A at 30 VDC with resistive load (cos = 1)
Ambient temperature Operating: -10 to 55°C (with no icing)
Storage: -25 to 65°C (with no icing)
Accuracy of operating time ±1% max. of FS (±1% ±10 ms max. at 1.2 s range)
Setting error ±10% ±50 ms max. of FS
Influence of voltage ±0.7% max. of FS (±0.7% ±10 ms max. at 1.2 s range)
Influence of temperature ±5% max. of FS (±5% ±10 ms max. at 1.2 s range)
Life expectancy (not H3DS-X) Mechanical: 10 million operations min. (under no load at 1,800 operations/h)
Electrical: 100,000 operations min. (5 A at 250 VAC, resistive load at 360 operations/h)
Size in mm(HxWxD) 80x17.5x73
433
21 Timers
H3DK Analogue solid state timers
DIN-rail mounted, standard 22.5 mm wide
solid state timer range
The H3DK series of timers provides a wide AC/DC power supply and time range to
reduce the number of items.
• Size in mm (HxWxD): 79x22.5x100
• DIN-rail mounting
• 12 VDC and 24-240 VAC/VDC (except -H). 240-440 VAC for -G
• Wide time setting range: 0.10 s - 1,200 h (except -H and -G), 12 ranges
(for -M and -S)
Ordering information
Specifications
Type Supply voltage Control output Time setting range Operating modes Order code
Multi-functional
standard timers
12 VDC SPDT 0.1 s to 1200 h ON-delay, flicker OFF start, flicker ON start,
signal ON/OFF-delay, signal OFF-delay, interval, one-shot
H3DK-M1A DC12
DPDT H3DK-M2A DC12 *1
*1 One output can be set to instantaneous.
SPDT ON-delay, flicker ON start, interval, one-shot H3DK-S1A DC12
DPDT H3DK-S2A DC12 *1
24 to 240 VAC/VDC SPDT ON-delay, flicker OFF start, flicker ON start,
signal ON/OFF-delay, signal OFF-delay, interval, one-shot
H3DK-M1 AC/DC24-240
DPDT H3DK-M2 AC/DC24-240 *1
SPDT ON-delay, flicker ON start, interval, one-shot H3DK-S1 AC/DC24-240
DPDT H3DK-S2 AC/DC24-240 *1
Twin timer 12 VDC SPDT 0.1 s to 12 h Flicker OFF start, flicker ON start H3DK-FA DC12
24 to 240 VAC/VDC H3DK-F AC/DC24-240
Star-delta timer 12 VDC 2x SPDT 1 to 120 s Star-delta H3DK-GA DC12
24 to 240 VAC/VDC H3DK-G AC/DC24-240
240 to 440 VAC H3DK-GE AC/DC240-440
Power OFF-delay timer 24 to 48 VAC/VDC SPDT 1 to 120 s Signal OFF-delay H3DK-HBL AC/DC24-48
0.1 to 12 s H3DK-HBS AC/DC24-48
100 to 120 VAC 1 to 120 s H3DK-HCL AC100-120V
0.1 to 12 s H3DK-HCS AC100-120V
200 to 240 VAC 1 to 120 s H3DK-HDL AC200-240V
0.1 to 12 s H3DK-HDS AC200-240V
Operating voltage range 85 to 110% of rated supply voltage (90 to 110% for the 12 VDC models).
Power reset Minimum power-off time: H3DK-M/S, H3DK-F: 0.1 s, H3DK-G: 0.5 s. (Not for H3DK-H)
Reset voltage 10% of rated voltage. (Not for H3DK-H)
Voltage input (H3DK-M/-S) 24 to 240 VAC/DC: H-level 20.4 to 264 VAC/VDC, L-level 0 to 2.4 VAC/VDC.
12 VDC: H-level 10.8 to 13.2 VDC, L-level 0 to 1.2 VDC.
Control output Contact output: 5 A at 250 VAC with resistive load (cos = 1), 5 A at 24 VDC (30 VDC for -M/-S) with resistive load (not for H3DK-GE)
Ambient temperature Operating: -20 to 55°C (with no icing), storage: -40 to 70°C (with no icing)
Accuracy of operating time ±1% of FS max. (±1% ±10 ms max. at 1.2 s range)
Setting error ±10% of FS ±0.05 s max.
Minimum input signal width 50 ms (start input) (Only for H3DK-M/S)
Influence of voltage ±0.5% of FS max. (±0.5% ±10 ms max. at 1.2 s range). For H3DK-G: ±0.5% of FS max.
Influence of temperature ±2% of FS max. (±2% ±10 ms max. at 1.2s range). For H3DK-G: ±2% of FS max.
Life expectancy Mechanical: 10 million operations min. (under no load at 1,800 operations/h)
Electrical: 100,000 operations min. (5 A at 250 VAC, resistive load at 360 operations/h)
Degree of protection IP30 (terminal block: IP20)
Terminal block Clamps two 2.5 mm2 max. bar terminals without sleeves
Size in mm (HxWxD) 79x22.5x100
434
H3YN Analogue solid state timers
Miniature timer with multiple time ranges
and multiple operating modes
H3YN features 4 multi-operating modes: ON-delay, interval,
flicker ON start and flicker OFF start.
• Size in mm (HxWxD): 28x21.5x52.6
• Plug-in
• All supply voltages available
• 0.1 s to 10 h
• DPDT (5A) or 4PDT (3A)
Ordering information
Accessories
Connecting socket Hold-down clips
Specifications
Supply voltage Functions Time-limit contact Order code
Short-time range model (0.1 s to 10 min) Long-time range model (0.1 min to 10 h)
12 VDC ON-delay
Interval
Flicker ON
Flicker OFF
DPDT H3YN-2 12DC H3YN-21 12DC
24 VAC H3YN-2 24AC H3YN-21 24AC
24 VDC H3YN-2 24DC H3YN-21 24DC
100 to 120 VAC H3YN-2 100-120AC H3YN-21 100-120AC
200 to 230 VAC H3YN-2 200-230AC H3YN-21 200-230AC
12 VDC 4PDT H3YN-4 12DC H3YN-41 12DC
24 VAC H3YN-4 24AC H3YN-41 24AC
24 VDC H3YN-4 24DC H3YN-41 24DC
100 to 120 VAC H3YN-4 100-120AC H3YN-41 100-120AC
200 to 230 VAC H3YN-4 200-230AC H3YN-41 200-230AC
Timer DIN-rail mounting/
front-connecting socket
Back-connecting socket
PCB terminal
H3YN-2/-21 PYF08A, PYF08A-N, PYF08A-E PY08-02
H3YN-4/-41 PYF14A, PYF14A-N, PYF14A-E PY14-02
Applicable socket Order code
PYF08A, PYF08A-N, PYF08A-E,
PYF14A, PYF14A-N, PYF14A-E
Y92H-3 (pair)
PY08, PY08-02, PY14-02 Y92H-4
Item H3YN-2/-4 H3YN-21/-41
Time ranges 0.1 s to 10 min (1 s, 10 s, 1 min, or 10 min max. selectable) 0.1 min to 10 h (1 min, 10 min, 1 h, or 10 h max. selectable)
Rated supply voltage 24, 100 to 120, 200 to 230 VAC (50/60 Hz)
12, 24, 48, 100 to 110, 125 VDC
Pin type Plug-in
Operating mode ON-delay, interval, flicker OFF start, or flicker ON start (selectable with DIP switch)
Operating voltage range 85 to 110% of rated supply voltage (12 VDC: 90 to 110% of rated supply voltage)
Reset voltage 10% min. of rated supply voltage
Control outputs DPDT: 5 A at 250 VAC, resistive load (cos = 1), 4PDT: 3 A at 250 VAC, resistive load (cos = 1)
Accuracy of operating time ±1% FS max. (1 s range: ±1% ±10 ms max.)
Setting error ±10% ±50 ms FS max.
Reset time Min. power-opening time: 0.1 s max. (including halfway reset)
Influence of voltage ±2% FS max.
Influence of temperature ±2% FS max.
Ambient temperature Operating: -10 to 50°C (with no icing), storage: -25 to 65°C (with no icing)
Degree of protection IP40
Size in mm (HxWxD) 28x21.5x52.6
435
21 Timers
H3CR Analogue solid state timers
DIN 48x48 mm multi-functional
timer series
This elaborate range of solid state timers provides you with
a multi-functional timer, twin timer, star-delta timer and a power
OFF-delay timer.
• 48x48 mm front-panel/plug-in
• High-/low-voltage models (except -H and -G)
• 0.05 s to 300 h (except -H and -G)
• DPDT, 5A at 250VAC
• Transistor 100mA at 30VDC
Ordering information
Accessories
Specifications
Output Number of pins Supply voltage Time range Operating mode Order code
Relay DPDT 11 100 to 240 VAC/100 to 125 VDC 0.05 s to 300 h ON-delay, flicker OFF start,
flicker ON start, signal ON/
OFF-delay, signal OFF-delay,
interval
H3CR-A 100-240AC/100-125DC
24 to 48 VAC/12 to 48 VDC H3CR-A 24-48AC/12-48DC
Transistor 24 to 48 VAC/12 to 48 VDC 0.05 s to 300 h H3CR-AS 24-48AC/12-48DC
Relay DPDT 8 100 to 240 VAC/100 to 125 VDC 0.05 s to 300 h ON-delay, flicker ON start,
interval, one-shot
H3CR-A8 100-240AC/100-125DC
24 to 48 VAC/12 to 48 VDC H3CR-A8 24-48AC/12-48DC
Transistor 24 to 48 VAC/12 to 48 VDC 0.05 s to 300 h H3CR-A8S 24-48AC/12-48DC
Relay SPDT 100 to 240 VAC/100 to 125 VDC H3CR-A8E 100-240AC/100-125DC
24 to 48 VAC/VDC H3CR-A8E 24-48AC/DC
Relay DPDT 11 100 to 240 VAC 0.05 s to 30 h Flicker OFF start H3CR-F 100-240AC
24 VAC/VDC H3CR-F 24AC/DC
8 100 to 240 VAC H3CR-F8 100-240AC
24 VAC/VDC H3CR-F8 24AC/DC
11 100 to 240 VAC 0.05 s to 30 h Flicker ON start H3CR-FN 100-240AC
24 VAC/VDC H3CR-FN 24AC/DC
8 100 to 240 VAC H3CR-F8N 100-240AC
24 VAC/VDC H3CR-F8N 24AC/DC
Time-limit contact and
instantaneous contact
100 to 120 VAC Star-delta H3CR-G8EL 100-120AC
200 to 240 VAC H3CR-G8EL 200-240AC
DPDT 8 100 to 120 VAC 0.05 to 12 s Power OFF-delay H3CR-H8LS 100-120AC
200 to 240 VAC H3CR-H8LS 200-240AC
24 VAC/VDC H3CR-H8LS 24AC/DC
100 to 120 VAC 0.05 to 12 m H3CR-H8LM 100-120AC
200 to 240 VAC H3CR-H8LM 200-240AC
24 VAC/VDC H3CR-H8LM 24AC/DC
Name/specifications Order code
Flush-mounting adapter Y92F-30
Protective cover Y92A-48B
Front connecting socket 8-pin, finger-safe
type, DIN-rail
P2CF-08-E
Front connecting socket 11-pin, finger-safe
type, DIN-rail
P2CF-11-E
Back connecting socket 8-pin P3G-08
11-pin P3GA-11
Name/specifications Order code
Time setting ring Setting a specific time Y92S-27
Limiting the setting range Y92S-28
Panel cover Light grey (5Y7/1) Y92P-48GL
Black (N1.5) Y92P-48GB
Accuracy of operating time ±0.2% FS max. (±0.2% ±10 ms max. in a range of 1.2 s)
Influence of voltage ±0.2% FS max. (±0.2% ±10 ms max. in a range of 1.2 s)
Influence of temperature ±1% FS max. (±1% ±10 ms max. in a range of 1.2 s)
Ambient temperature Operating: -10 to 55°C (with no icing),
storage: -25 to 65°C (with no icing)
Life expectancy Mechanical: 20,000,000 operations min. (under no load at 1,800 operations/h)
Electrical: 100,000 operations min. (5 A at 250 VAC, resistive load at 1,800 operations/h)
Size in mm (HxWxD) 48x48x66.6 (H3CR-A, -F), 48x48x78 (H3CR-G, -H)
Setting error ±5% FS ±50 ms
Degree of protection IP40 (panel surface)
Weight Approx. 90 g
436
H5CX Digital timers
The most complete digital standard timer on
the market
H5CX offers you the most complete series of products on the market today.
Based on extensive customer research, these new timers have been designed with
value added features that users both need and appreciate.
• Size in mm (HxWxD): 48x48x59 to 78 mm
• Three colour display value, red, green or orange
• Models with Instantaneous Contact Outputs
• 0.001 s to 9999 h, 10 ranges
• Input NPN, PNP and contact
Ordering information
Accessories
Specifications
Output type Supply voltage Functions External connection Size in mm (HxWxD) Inputs Order code
Contact output 100 to 240 VAC A: Signal ON-delay
A-1: Signal ON-delay 2
A-2: Power ON-delay 1
A-3: Power ON-delay 2
b: Repeat cycle 1
b-1: Repeat cycle 2
d: Signal OFF-delay
E: Interval
F: Cumulative
Z: ON/OFF-duty adjustable flicker
toff: Twin timer OFF start
ton: Twin timer ON start
Screw terminals 48x48x84 Signal, Reset, Gate
(NPN/PNP inputs)
H5CX-A-N
12 to 24 VDC/24 VAC 48x48x65 H5CX-AD-N
Transistor output 100 to 240 VAC 48x48x84 H5CX-AS-N
12 to 24 VDC/24 VAC 48x48x65 H5CX-ASD-N
Contact output 100 to 240 VAC 11-pin socket 48x48x69.7 Signal, Reset, Gate
(NPN/PNP inputs)
H5CX-A11-N
12 to 24 VDC/24 VAC H5CX-A11D-N
Transistor output 100 to 240 VAC H5CX-A11S-N
12 to 24 VDC/24 VAC H5CX-A11SD-N
Contact output 100 to 240 VAC 8-pin socket 48x48x69.7 Signal, Reset
(NPN inputs)
H5CX-L8-N
12 to 24 VDC/24 VAC H5CX-L8D-N
Transistor output 100 to 240 VAC H5CX-L8S-N
12 to 24 VDC/24 VAC H5CX-L8SD-N
Contact output
Models with instantaneous
contact outputs
100 to 240 VAC A-2: Power ON-delay 1
b: Repeat cycle 1
E: Interval
Z: ON/OFF-duty adjustable flicker
toff: Twin timer OFF start 1
ton: Twin timer ON start 1
– H5CX-L8E-N
12 to 24 VDC/24 VAC H5CX-L8ED-N
Transistor output 12 to 24 VDC A: Signal ON-delay 1
F: Cumulative
Screw terminals 48x48x65 Signal, Reset, Gate
(NPN/PNP inputs)
H5CX-BWSD-N
Name Order code
Flush-mounting adapter Y92F-30
Waterproof packing Y92S-29
Front-connecting socket 8-pin, finger safe type P2CF-08-E
11-pin, finger safe type P2CF-11-E
Back-connecting socket 8-pin P3G-08
11-pin P3GA-11
Hard cover Y92A-48
Soft cover Y92A-48F1
Front panels
(4-digit models)
Light gray Y92P-CXT4G
White Y92P-CXT4S
Item H5CX-A_ H5CX-A11_ H5CX-L8_
Display 7-segment, negative transmissive LCD
Present value: 12 mm high characters
red, orange or green (programmable) red
Set value: 6 mm high characters, green
Digits 4 digits
Total time range 0.001 s to 9,999 h (configurable)
Timer mode Elapsed time (Up), remaining time (Down) (selectable)
Input signals Signal, reset, gate Signal, reset
Key protection Yes
Memory backup EEPROM (overwrites: 100,000 times min.) that can store data for 10 years min.
Ambient temperature Operating: -10 to 55°C (no icing or condensation), side-by-side mounting: -10 to 50°C
Case colour Black (N1.5)
437
21 Timers
H2C Motor timers
DIN-sized (48x48) motor timer with
variable time ranges
This motor timer series provides you with many features, such as ON-delay,
time indicator, moving pointer and synchronous motor. Moreover, the LED indicator
shows the time operation, time range and the rated voltage.
• DIN-sized 48x48mm
• Front-panel/plug-in/DIN-rail
• All supply voltages available
• 0.2 s to 30 h
• SPDT, 6A at 250VAC
Ordering information
Note: Other voltages available on request
Accessories
Specifications
Operation/resetting system Internal connection Terminal Time-limit
contact
Instantaneou
s contact
Time range code Order code
Time-limit operation/
electric resetting
Separate motor and clutch connection 11-pin socket SPDT SPDT 1.25 s to 30 h
in 5 ranges
H2C-RSA 110AC
H2C-RSA 220AC
H2C-RSA 24AC
0.2 s to 6 h
in 5 ranges
H2C-RSB 110AC
H2C-RSB 220AC
H2C-RSB 24AC
0.5 s to 12 h
in 5 ranges
H2C-RSC 110AC
H2C-RSC 220AC
H2C-RSC 24AC
Time-limit operation/
self-resetting
Separate motor and clutch connection 11-pin socket SPDT SPDT 1.25 s to 30 h
in 5 ranges
H2C-SA 110AC
H2C-SA 220AC
H2C-SA 24AC
0.2 s to 6 h
in 5 ranges
H2C-SB 110AC
H2C-SB 220AC
H2C-SB 24AC
0.5 s to 12 h
in 5 ranges
H2C-SC 110AC
H2C-SC 220AC
H2C-SC 24AC
Name/specifications Order code
DIN-rail mounting/
front-connecting socket
8-pin, finger safe type P2CF-08-E
11-pin, finger safe type P2CF-11-E
Back-connecting socket 8-pin, screw terminal P3G-08
11-pin P3GA-11
Name/specifications Order code
Hold-down clip (pair) For PL08 and PL11 sockets Y92H-1
For PF085A socket Y92H-2
Flush mounting adapter Y92F-30
Time setting ring Y92A-Y1
Operating voltage range 85 to 110% of rated supply voltage
Reset voltage 10% max. of rated supply voltage
Reset time Min. power-opening time: 0.5 s, min. pulse width: 0.5 s
Control outputs 6 A at 250 VAC, resistive load (cos = 1)
Mounting method Flush mounting (except for H2C-F/-FR models), surface-mounting, DIN-rail mounting
Life expectancy Mechanical: 10,000,000 operations min.
Electrical: 500,000 operations min.
Motor life expectancy 20,000 h
Accuracy of operating time ±0.5% FS max. (±1% max. at 0.2 to 6 s for the time range code B or at 0.5 to 12 s for the time range code C)
Setting error ±2% FS max.
Reset time 0.5 s max.
Influence of voltage ±1% FS max.
Influence of temperature ±2% FS max.
Ambient temperature Operating: -10 to 50°C
Case colour Light grey (Munsell 5Y7/1)
Degree of protection IP40 (panel surface)
Size in mm (HxWxD) 48x48x77.5
H7ER
Speed
H7EC
Totalising
H7ET
Timer
Which type of application?
48x24 mm
(1/32 DIN)
Which size is required?
Totalising
MULTI-FUNCTIONAL PRESET COUNTER
The H7CX series offers the ultimate in versatility and intuitive programming.
• 7 basic functions in one
• Switching colour on threshold, green, orange & red
• Twin counter mode
• 12 different outputs modes
• Display 6 digits from -100 K +1 up to 1 M -1
H7CX – Designed with value added features
438
Page 442 Page 443 Page 444
Counters
H7CX
H8GN
counter/timer
48x24 mm
(1/32 DIN)
48x48 mm
(1/16 DIN)
Which size is required?
Pre-set counter
time count
What is the type of counting application?
H8PS
96x96 mm
(1/4 DIN)
Which size is required?
Cam positioner
439
22 Counters
Page 445 Page 446 Page 447
440
Selection table
Category Self-powered total Self-powered timer Self-powered tachometer
Selection criteria
Model H7EC H7ET H7ER
Display LCD
Size 1/32 DIN
Outputs
Control outputs – – –
5 stage – – –
Total –
Time – –
Preset – – –
Batch – – –
Dual – – –
Tachometer –
Inputs
Control inputs No-voltage, PNP/NPN, DC-voltage,
AC/DC multi-voltage
No-voltage, PNP/NPN, DC-voltage,
AC/DC multi-voltage
No-voltage,
PNP/NPN
Features
Dual operation – – –
Number of digits 8 7 4 or 5
NPN/PNP switch
Back-lit
External reset –
Manual reset –
Number of banks – – –
Built-in sensor power supply – – –
IP rating IP66 IP66 IP66
Terminals
Screw terminals
PCB terminals – – –
11-pin socket – – –
Supply
voltage
100 to 240 VAC – – –
12 to 24 VDC – – –
24 VDC
Comms – – –
Functions
Up –
Down – – –
Up/down – – –
Reversible – – –
Speed 0 to 30 Hz or 0 to 1 kHz – 1 or 10 kHz
Counting range 0 to 99999999 0.0 h to 999999.9 h <-->
0.0 h to 3999 d 23.9 h or
0 s to 999 h 59 min 59 s <-->
0.0 min to 9999 h 59.9 min
1000 s-1 or 1000 min-1; 1000 s-1 or
1000 min-1 <--> 10000 min-1
Colour
Beige
Black
Page 442 443 444
Counters
441
22 Counters
Counter type Pre-set counter/timer Pre-set counter Cam positioner
Selection criteria
Model H8GN H7CX H8PS
Display LCD negative transmissive LCD negative transmissive
Size 1/32 DIN 1/16 DIN 1/4 DIN
Outputs
Control outputs 1 relay (SPDT) 1 relay (SPDT), transistor NPN or PNP, cam outputs 8/16/32, run out,
tachometer
5 stage –
Total –
Time – –
Preset –
Batch –
Dual –
Tachometer – –
Inputs
Control inputs No-voltage No-voltage,
PNP/NPN
Encoder
Features
Dual operation
Number of digits PV: 4, SV: 4 PV: 4, SV: 4
or PV: 6, SV: 6
7
NPN/PNP switch – –
Back-lit –
External reset –
Manual reset 8 (16- and 32-output models only)
Number of banks 4 – –
Built-in sensor power supply – –
IP rating IP66 IP66 IP40
Terminals
Screw terminals
PCB terminals – –
11-pin socket – –
Supply
voltage
100 to 240 VAC – –
12 to 24 VDC – –
24 VDC –
Comms – –
Functions
Up –
Down –
Up/down – –
Reversible –
Speed 0 to 30 Hz or 0 to 5 kHz 0 to 30 Hz or 0 to 5 kHz –
Counting range -999 to 9999 -99999 to 999999 –
Colour
Beige – –
Black –
Page 445 446 447
Standard Available – No/not available
442
H7EC Totalisers
Self-powered LCD totaliser
The H7E series is available with large display with 8.6 mm character height.
It includes models with backlight for improved visibility in dimly lit places.
The H7E family includes total counters, time counters, tachometers and
PCB mounted counters.
• Size in mm (HxWxD): 24x48x55.5, 1/32 DIN size housing
• 8 digits, 8.6 mm character height
• Black or light-grey housing
• Dual input speed: 30 Hz <-> 1 kHz
• Short body: all models have a depth of 48.5 mm
Ordering information
Specifications
Count input Max. counting speed Display Order code
Light grey body Black body
No-voltage 30 Hz <-> 1 kHz (switchable) 7-segment LCD H7EC-N H7EC-N-B
PNP/NPN universal DC
voltage input
30 Hz <-> 1 kHz (switchable) 7-segment LCD H7EC-NV H7EC-NV-B
7-segment LCD with backlight H7EC-NV-H H7EC-NV-BH
AC/DC multi-voltage input 20 Hz 7-segment LCD H7EC-NFV H7EC-NFV-B
Item H7EC-NV-_/H7EC-NV-_H H7EC-NFV-_ H7EC-N-_
Operating mode Up type
Mounting method Flush mounting
External connections Screw terminals, optional wire-wrap terminals
Number of digits 8
Display 7-segment LCD with or without backlight, zero suppression (character height: 8.6 mm)
Max. counting speed 30 Hz/1 kHz 20 Hz 30 Hz/1 kHz
Case colour Light grey or black (-B models)
Attachment Waterproof packing, flush mounting bracket
Supply voltage Backlight model: 24 VDC (0.3 W max.)
(only for backlight)
No-backlight model: Not required
(powered by built-in battery)
Not required (powered by built-in battery)
Count input High (logic) level: 4.5 to 30 VDC
Low (logic) level: 0 to 2 VDC
(input impedance: Approx. 4.7 k)
High (logic) level:
24 to 240 VAC/VDC, 50/60 Hz
Low (logic) level:
0 to 2.4 VAC/VDC, 50/60 Hz
No voltage input
Maximum short-circuit impedance:
10 k max.
Short-circuit residual voltage: 0.5 V max.
Reset input No voltage input Minimum open impedance: 750 k min.
Maximum short-circuit impedance:
10 k max.
Short-circuit residual voltage: 0.5 V max.
Minimum open impedance: 750 k min.
Minimum signal width 20 Hz: 25 ms, 30 Hz: 16.7 ms, 1 KHz: 0.5 ms
Reset system External reset and manual reset: Minimum signal width of 20 ms
Ambient temperature Operating: -10 to 55°C (with no condensation or icing), storage: -25 to 65°C (with no condensation or icing)
Degree of protection Front-panel: IP66, NEMA4, terminal block: IP20
Battery life (reference) 7 years min. with continuous input at 25°C (lithium battery)
Size in mm (HxWxD) 24x48x55.5
443
22 Counters
H7ET Totalisers
Self-powered time counter
The H7E series is available with large display with 8.6mm character height.
It includes models with backlight for improved visibility in dimly lit places.
The H7E family includes total counters, time counters, tachometers and
PCB mounted counters.
• Size in mm (HxWxD) 24x48x55.5, 1/32 DIN size housing
• 7 digits, 8.6mm character height
• Black or light-grey housing
• Dual time range 999999.9 h <-> 3999 d 23.9 h
or 999 h 59 m 59 s <-> 9999 h 59.9m
Ordering information
Specifications
Timer input Display Order code
Time range 999999.9h <-> 3999d23.9h (switchable) Time range 999h59m59s <-> 9999h59.9m
Light grey body Black body Light grey body Black body
No-voltage input 7-segment LCD H7ET-N H7ET-N-B H7ET-N1 H7ET-N1-B
PNP/NPN universal
DC voltage input
7-segment LCD H7ET-NV H7ET-NV-B H7ET-NV1 H7ET-NV1-B
7-segment LCD with backlight H7ET-NV-H H7ET-NV-BH H7ET-NV1-H H7ET-NV1-BH
AC/DC multi-voltage input 7-segment LCD H7ET-NFV H7ET-NFV-B H7ET-NFV1 H7ET-NFV1-B
Item H7ET-NV_-_/H7ET-NV_-_H H7ET-NFV_-_ H7ET-N_-_
Operating mode Accumulating
Mounting method Flush mounting
External connections Screw terminals
Display 7-segment LCD with or without backlight, zero suppression (character height: 8.6 mm)
Number of digits 7
Case colour Light grey or black (-B models)
Attachment Waterproof packing, flush mounting bracket, time unit labels
Supply voltage Backlight model: 24 VDC (0.3 W max.)
(for backlight)
No-backlight model: Not required
(powered by built-in battery)
Not required (powered by built-in battery)
Timer input High (logic) level: 4.5 to 30 VDC
Low (logic) level: 0 to 2 VDC
(Input impedance: Approx. 4.7 k)
High (logic) level:
24 to 240 VAC/VDC, 50/60 Hz
Low (logic) level:
0 to 2.4 VAC/VDC, 50/60 Hz
No voltage input
Maximum short-circuit impedance:
10 k max.
Short-circuit residual voltage: 0.5 V max.
Reset input No voltage input Minimum open impedance: 750 k min.
Maximum short-circuit impedance:
10 k max.
Short-circuit residual voltage: 0.5 V max.
Minimum open impedance: 750 k min.
Minimum pulse width 1 s
Reset system External reset and manual reset: Minimum signal width of 20 ms
Ambient temperature Operating: -10 to 55°C (with no condensation or icing), storage: -25 to 65°C (with no condensation or icing)
Time accuracy ±100 ppm (25°C)
Degree of protection Front-panel: IP66, NEMA4 with waterproof packing, terminal block: IP20
Battery life (reference) 10 years min. with continuous input at 25°C (lithium battery)
Size in mm (HxWxD) 24x48x55.5
444
H7ER Totalisers
Self-powered tachometer
The H7E series is available with large display with 8.6mm character height.
It includes models with backlight for improved visibility in dimly lit places.
The H7E family includes total counters, time counters, tachometers and
PCB mounted counters.
• Size in mm (HxWxD) 24x48x53.5, 1/32 DIN size housing
• 5 digits, 8.6mm character height
• Black or light-grey housing
• Dual revolution display
Ordering information
Specifications
Count input Display Order code
Max. revolutions displayed (applicable encoder resolution)
1,000 s-1 (1 pulse/rev.)
1,000 min-1 (60 pulse/rev.)
1,000.0 s-1 (10 pulse/rev)
1,000.0 min-1 (600 pulse/rev) <->
10,000 min-1 (60 pulse/rev) (switchable)
Light grey body Black body Light grey body Black body
No-voltage input 7-segment LCD H7ER-N H7ER-N-B
PNP/NPN universal
DC voltage input
7-segment LCD H7ER-NV H7ER-NV-B H7ER-NV1 H7ER-NV1-B
7-segment LCD with backlight H7ER-NV-H H7ER-NV-BH H7ER-NV1-H H7ER-NV1-BH
Item H7ER-NV1-_/H7ER-NV1-_H H7ER-NV-_/H7ER-NV-_H H7ER-N-_
Operating mode Up type
Mounting method Flush mounting
External connections Screw terminals, wire-wrap terminals
Display 7-segment LCD with or without backlight, zero suppression (character height: 8.6 mm)
Number of digits 5 4
Max. revolutions displayed 1,000.0 s-1 (when encoder resolution
of 10 pulse/rev is used)
1,000.0 min-1 (when encoder resolution
of 600 pulse/rev is used)
<-> 10,000 min-1 (when encoder resolution
of 60 pulse/rev is used)
(switchable with switch)
1,000 s-1 (when encoder resolution of 1 pulse/rev is used)
1,000 min-1 (when encoder resolution of 60 pulse/rev is used)
Attachment Waterproof packing, flush mounting bracket, revolution unit labels
Supply voltage Backlight model: 24 VDC (0.3 W max.) (for backlight lit)
No-backlight model: Not required (powered by built-in battery)
Not required (powered by built-in battery)
Count input High (logic) level: 4.5 to 30 VDC
Low (logic) level: 0 to 2 VDC
(Input impedance: Approx. 4.7 k)
No voltage input
Maximum short-circuit impedance:
10 k max.
Short-circuit residual voltage: 0.5 V max.
Minimum open impedance: 750 k min.
Max. counting speed 10 kHz 1 kHz
Minimum signal width 10 kHz: 0.05 ms, 1 kHz: 0.5 ms
Ambient temperature Operating: -10 to 55°C (with no condensation or icing), storage: -25 to 65°C (with no condensation or icing)
Degree of protection Front-panel: IP66, NEMA4 with waterproof packing, terminal block: IP20
Battery life (reference) 7 years min. with continuous input at 25°C (lithium battery)
Size in mm (HxWxD) 24x48x53.5
445
22 Counters
H8GN Pre-set counters
World’s smallest compact preset
counter/timer
The H8GN is a 1/32 DIN timer and counter in one. It is simple to switch between the
timer and counter functions. During operation it is also possible to switch the display
to monitor the totalising count value in 8 digits. Many sophisticated functions come
as standard with H8GN.
• Size in mm (HxWxD) 24x48x83, 1/32 DIN size housing
• 8 digit display, 4 value and 4 set value
• Front mounting
• -999 to 9999
• 24 VDC
Ordering information
Specifications
Functions Supply voltage Output Order code
Communications
Counter Timer No communications RS-485
Counter: Up/down/reversible,
4 digits, N, F, C or K output modes
Total counter: 8 digits
A: ON-delay
B: Flicker
D: Signal OFF-delay
E: Interval
F: Accumulative
Z: ON/OFF-duty adjustable flicker
24 VDC Contact output (SPDT) H8GN-AD H8GN-AD-FLK
Rated supply voltage 24 VDC
Operating voltage range 85 to 110% of rated supply voltage
Power consumption 1.5 W max. (for max. DC load) (inrush current: 15 A max.)
Mounting method Flush-mounting
External connections Screw terminals (M3 screws)
Terminal screw tightening torque 0.5 Nm max.
Attachment Waterproof packing, flush-mounting bracket
Display 7-segment, negative transmissive LCD; time display (h, min, s); CMW, OUT, RST, TOTAL
Present value (red, 7 mm high characters); set value (green, 3.4 mm high characters)
Digits PV: 4 digits, SV: 4 digits, when total count value is displayed: 8 digits (zeros suppressed)
Memory backup EEPROM (non-volatile memory) (number of writes: 100,000 times)
Counter Maximum counting speed 30 Hz or 5 kHz
Counting range -999 to 9,999
Input modes Increment, decrement, individual, quadrature inputs
Timer Timer modes Elapsed time (up), remaining time (down)
Inputs Input signals For counter: CP1, CP2, and reset
For timer: Start, gate, and reset
Input method No-voltage input (contact short-circuit and open input)
Short-circuit (ON) impedance: 1 k max. (approx. 2 mA runoff current at 0 )
Short-circuit (ON) residual voltage: 2 VDC max.
Open (OFF) impedance: 100 k min.
Applied voltage: 30 VDC max.
Start, reset, gate Minimum input signal width: 1 or 20 ms (selectable)
Power reset Minimum power-opening time: 0.5 s
Control output SPDT contact output: 3 A at 250 VAC/30 VDC, resistive load (cos = 1)
Minimum applied load 10 mA at 5 VDC (failure level: P, reference value)
Reset system External, manual, and power supply resets (for timer in A, B, D, E, or Z modes)
Sensor waiting time 260 ms max.
(inputs cannot be received during sensor wait time if control outputs are turned OFF)
Timer function Accuracy of operating time and setting error
(including temperature and voltage effects)
Signal start: ±0.03% ±30 ms max.
Power-ON start: ±0.03% ±50 ms max.
Ambient
temperature
Operating storage -10 to 55°C (with no icing or condensation)
-25 to 65°C (with no icing or condensation)
Case colour Rear section: Grey smoke; front section: N1.5 (black)
Degree of protection Panel surface: IP66 and NEMA Type 4X (indoors); rear case: IP20, terminal block: IP20
Size in mm (HxWxD) 24x48x83
446
H7CX Pre-set counters
The most complete digital standard counter
on the market
H7CX offers you the most complete series of products on the market today.
Based on extensive customer research, these new counters have been designed with
value added features that users both need and appreciate.
• Size in mm (HxWxD) 48x48x59 to 78mm 1/16 DIN size housing
• Three colour display value, red, green or orange
• Twin counter mode
• 6 digit model -99,999 to 999,999, set value -99,999 to 999,999 or 0 to 999,999
• Input contact, NPN or PNP
Ordering information
Accessories
Specifications
Type External
connection
Sensor power
supply
Supply voltage Output type Digits Size in mm (HxWxD) Order code
1-stage counter
1-stage counter with total counter
2-stage counter
1-stage counter with batch counter
Dual counter (addition/subtraction)
Tachometer
Twin counter
Screw terminal 12 VDC 100 to 240 VAC Contact and transistor
output
6 48x48x84 H7CX-AU-N
12 to 24 VDC/24 VAC H7CX-AUD1-N
Transistor output (2x) H7CX-AUSD1-N
100 to 240 VAC Contact output (2x) H7CX-AW-N
12 to 24 VDC/24 VAC H7CX-AWD1-N
1-stage counter
1-stage counter with total counter
11-pin socket 12 VDC 100 to 240 VAC Contact output 48x48x69.7 H7CX-A11-N
12 to 24 VDC/24 VAC H7CX-A11D1-N
100 to 240 VAC Transistor output H7CX-A11S-N
12 to 24 VDC/24 VAC H7CX-A11SD1-N
Screw terminal 100 to 240 VAC Contact output 48x48x84 H7CX-A-N
100 to 240 VAC Transistor output H7CX-AS-N
Name Order code
Flush-mounting adapter Y92F-30
Waterproof packing Y92S-29
DIN-rail mounting/front-connecting socket 11-pin, finger safe type P2CF-11-E
Back-connecting socket 11-pin P3GA-11
Finger safe terminal cover for P3GA-11 Y92A-48G
Hard cover Y92A-48
Soft cover Y92A-48F1
Front panels
(4-digit models)
Light gray Y92P-CXC4G
White Y92P-CXC4S
Front panels
(6-digit models)
Light gray Y92P-CXC6G
White Y92P-CXC6S
Display 7-segment, negative transmissive LCD
Digits 6-digits: -99,999 to 999,999, SV range: -99999 to 999999 or 0 to 999999
Max. counting speed 30 Hz or 5 kHz (selectable, ON/OFF ratio 1:1)
Input modes Increment, decrement, increment/decrement (UP/DOWN A (command input), UP/DOWN B (individual inputs), or UP/DOWN C (quadrature inputs))
Control output Contact output: 3 A at 250 VAC/30 VDC, resistive load (cos= 1)
Minimum applied load: 10 mA at 5 VDC
Transistor output:NPN open collector, 100 mA at 30 VDC
Residual voltage: 1.5 VDC max. (approx. 1V)
Leakage current: 0.1 mA max.
Key protection Yes
Decimal point adjustment Yes (rightmost 3 digits)
Sensor waiting time 290 ms max.
Memory backup EEPROM (overwrites: 100,000 times min.) stores data 10 years min.
Ambient temperature Operating: -10 to 55°C (-10 to 50°C when mounted side by side)
Case colour Black (N1.5) (Optional Front Panels are available to change the Front Panel colour to light gray or white.)
Life expectancy Mechanical: 10,000,000 operations min.
Electrical: 100,000 operations min. (3 A at 250 VAC, resistive load)
Degree of protection Panel surface: IP66, NEMA 4 (indoors), and UL Type 4X (indoors)
447
22 Counters
H8PS Cam positioners
Compact, easy-to-use cam positioner
The H8PS provides high speed operation at 1,600 r/min and high-precision
settings to 0.5° ensuring widespread application. H8PS features a highly visible
display with back-lit negative transmissive LCD. Advance angle compensation
function compensates for output delays.
• 96 to 121.2Hx96Wx60.6 to 67.5D mm
• Front-panel / DIN-rail
• 24 VDC
• 8-, 16- and 32-outputs
• NPN/PNP 100 mA at 30 VDC
Ordering information
Encoders Accessories
Encoder accessories
Specifications
Number of
outputs
Mounting method Output configuration Bank function Size in mm (HxWxD) Order code
8-outputs Flush-mounting NPN transistor output No 96x96x67.5 H8PS-8B
PNP transistor output H8PS-8BP
Front-mounting/DIN-rail mounting NPN transistor output 96x96x60.6 H8PS-8BF
PNP transistor output H8PS-8BFP
16-outputs Flush-mounting NPN transistor output Yes 96x96x67.5 H8PS-16B
PNP transistor output H8PS-16BP
Front-mounting/DIN-rail mounting NPN transistor output 121.2x96x60.6 H8PS-16BF
PNP transistor output H8PS-16BFP
32-outputs Flush-mounting NPN transistor output 96x96x67.5 H8PS-32B
PNP transistor output H8PS-32BP
Front-mounting/DIN-rail mounting NPN transistor output 121.2x96x60.6 H8PS-32BF
PNP transistor output H8PS-32BFP
Type Resolution Cable length Order code
Economy 256 2 m E6CP-AG5C-C 256 2M
Standard 256 1 m E6C3-AG5C-C 256 1M
2 m E6C3-AG5C-C 256 2M
360 E6C3-AG5C-C 360 2M
720 E6C3-AG5C-C 720 2M
Rigid 256 2 m E6F-AG5C-C 256 2M
360 E6F-AG5C-C 360 2M
720 E6F-AG5C-C 720 2M
Name Specification Order code
Discrete wire output cable 2 m Y92S-41-200
Connector-type output cable 2 m E5ZE-CBL200
Support software CD-ROM H8PS-SOFT-V1
USB cable A miniB, 2 m Y92S-40
Parallel input adapter Two units can operate
in parallel
Y92C-30
Protective cover Y92A-96B
Watertight cover Y92A-96N
DIN-rail mounting base Y92F-91
Name Specification Order code
Shaft coupling for the E6CP Axis: 6 mm dia. E69-C06B
Shaft coupling for the E6C3 Axis: 8 mm dia. E69-C08B
Shaft coupling for the E6F Axis: 10 mm dia. E69-C10B
Extension cable 5 m (same for E6CP, E6C3, and E6F) E69-DF5
Rated supply voltage 24 VDC
Inputs Encoder input 8-output models: None; 16-/32-output models: Bank inputs 1/2/4, origin input, start input
External inputs Input signals 8-output models: None; 16-/32-output models: Bank inputs 1/2/4, origin input, start input
Input type No voltage inputs: ON impedance: 1 k max. (leakage current: Approx. 2 mA at 0 )
ON residual voltage: 2 V max., OFF impedance: 100 k min., applied voltage: 30 VDC max.
Minimum input signal width: 20 ms
Number of banks 8 banks (for 16-/32-output models only)
Display method 7-segment, negative transmissive LCD (main display: 11 mm (red), sub-display: 5.5 mm (green))
Memory backup method EEPROM (overwrites: 100,000 times min.) that can store data for 10 years min.
Ambient operating temperature -10 to 55°C (with no icing or condensation)
Storage temperature -25 to 65°C (with no icing or condensation)
Ambient humidity 25 to 85%
Degree of protection Panel surface: IP40, rear case: IP20
Case colour Light grey (Munsell 5Y7/1)
ZEN-10C2
10 (6 I, 4 O)
expandable
up to 34 I/O
ZEN-20C2
How many I/O points?
LED type
20 (12 I, 8 O)
expandable
up to 44 I/O
FLEXIBLE AUTOMATION EXPANDED
Our range is extended with a communication model. Now you have the possibility to
connect several ZEN in a network environment. This will enhance the ZEN series to
solve even more applications.
• RS-485 communication
• To connect up to 32 units
• Easy CompoWayF protocol
ZEN-C4 – More flexibility with RS-485 communication
448
Page 452 Page 453
Programmable relays
ZEN-10C1
What functionality is required?
ZEN-20C1 ZEN-10C3 ZEN-20C3 ZEN-10C4 ZEN-8E
10 (6 I, 4 O)
expandable
up to 34 I/O
20 (12 I, 8 O)
expandable
up to 44 I/O
10 (6 I, 4 O)
fixed I/O
20 (12 I, 8 O)
fixed I/O
10 (6 I, 4 O)
expandable
up to 33 I/O
with
communication
How many I/O points?
Display type with
buttons, calendar
and clock
Expansion
unit
8 I/O
(4 I, 4 O)
How many extra
I/O points?
449
23 Programmable relays
Page 452 Page 453 Page 452 Page 453 Page 452 Page 454
450
Programmable relays
451
23 Programmable relays
Model ZEN-10C ZEN-20C
Type CPU unit CPU unit
Features C1 With LCD Display,
program/control buttons,
calendar and real-time clock
With LCD display,
program/control buttons,
calendar and real-time clock
Features C2 With LED indication
Logic control
Programming by software
With LED indication
Logic control
Programming by software
Features C3 Same as C1 but not expandable. Same as C1 but not expandable.
Features C4 Same as C1 but instead of one output
relay you get RS-485 communication.
–
Features Starter kits Complete set with C1 CPU including
software, cable and manual
–
Number of I / O points 10 expandable up to 34 I/O
(C4 up to 33 I/O)
20 expandable up to 44 I/O
Inputs 6 12
Inputs/power supply 100 to 240 VAC or 12 to 24 VDC 100 to 240 VAC or 12 to 24 VDC
Outputs 4 relays (C4 = 3 relays) or
4 transistors
8 relays or 8 transistors
Page 452 453
– No/not available
Selection table
452
ZEN-10C Programmable relays
Flexible automation
The ZEN-10C offers simple logic control in a choice of four CPU units. Expansion is
possible on three of these CPU's of up to 34 I/O whereas the fourth (C3 Units) is fixed
at 10 I/O. All DC models have analogue input and a high-speed counter input up to
150 Hz.
• DC input/supply units have analogue input + high speed counter
• The ZEN-10C4 has RS-485 communication
• Expansion available with relay output or transistor output
• ZEN-Kits the best choice to start!
Ordering information
Specifications
Accessories
Name Number of
I/O points
Inputs (I)/
power supply
Outputs (Q) Type LCD, buttons
(B), calendar
and clock
Analogue
input/
comparators
(A)
8-digit
counter (F)/
comparators
(G)
No. of bits 16 No. of bits 8 Size in mm
(HxWxD)
Order code
CPU units 10
Expandable
up to
34 I/O
6 100 to 240 VAC 4 Relays LCD yes – – Work bits (M)
Holding bits (H)
Timers (T)
Counters (C)
Weekly timers (@)
LCD display (D)
Timer/counter
comparator (P)
Holding timers (#)
Button input (B)
90x70x56 ZEN-10C1AR-A-V2
LED – – – ZEN-10C2AR-A-V2
12 to 24 VDC LCD yes yes / 4 yes / 4 ZEN-10C1DR-D-V2
LED – yes / 4 yes / 4 ZEN-10C2DR-D-V2
Transistors
LCD yes yes / 4 yes / 4 ZEN-10C1DT-D-V2
LED – yes / 4 yes / 4 ZEN-10C2DT-D-V2
Fixed I/O 100 to 240 VAC Relays LCD yes – yes / 4 ZEN-10C3AR-A-V2
12 to 24 VDC LCD yes yes / 4 yes / 4 ZEN-10C3DR-D-V2
10
Expandable
up to
33 I/O
100 to 240 VAC 3 LCD/
Comm.
yes – yes / 4 ZEN-10C4AR-A-V2
12 to 24 VDC yes yes / 4 yes / 4 ZEN-10C4DR-D-V2
ZEN kit Set containing CPU unit (ZEN-10C1AR-A-V2), connecting cable,
ZEN support software and manual.
ZEN-KIT01-EV4
Set containing CPU unit (ZEN-10C1DR-D-V2), connecting cable,
ZEN support software and manual.
ZEN-KIT02-EV4
Item Specifications
ZEN-10C_AR-A-V2 ZEN-10C_D_-D-V2
Power supply voltage 100 to 240 VAC, 50/60 Hz 12 to 24 VDC (DC ripple rate: 5%)
Rated power supply voltage 85 to 264 VAC 10.8 to 28.8 VDC
Power consumption 9 VA max. 4 W max.
Inrush current 3 A max. 30 A max.
Ambient temperature 0°C to 55°C (-25°C to 55°C for ZEN-10C2 models (LED))
Ambient storage -20°C to 55°C (-40°C to 75°C for ZEN-10C2 models (LED))
Control method Stored program control
I/O control method Cyclic scan
Programming language Ladder diagram
Program capacity 96 lines (3 input conditions and 1 output per line)
LCD display 12 characters x 4 lines, with backlight (LCD-type CPU unit only)
Operation keys 8 (4 cursor keys and 4 operation keys) (LCD-type CPU unit only)
Super-capacitor holding time 2 days min. (25°C)
Battery life (ZEN-BAT01) 10 years min. (25°C)
Calendar & Clock function Accuracy: ± 15 s/month (at 25°C)
Name Description Order code
Memory Cassette EEPROM (for data security and copying) ZEN-ME01
Battery unit Battery (keeps time, date and bit values for 10 years at 25°C) ZEN-BAT01
Connecting Cable For the programming software, RS-232C cable, 9-way `D' connector for PC ZEN-CIF01
USB-Serial conversion cable USB-Serial conversion cable (to be used in combination with ZEN-CIF01) CS1W-CIF31
ZEN support software Runs on Windows ME, 2000, XP, NT4.0 Service Pack 3, Vista ZEN-SOFT01-V4
453
23 Programmable relays
ZEN-20C Programmable relays
Extended flexible automation
Ideal for small-scale control applications, the ZEN-20C provides an economical
alternative to discrete timers, counters and general purpose relays. With 12 Inputs
and 8 relay or transistor Outputs, and expansion possibilities of up to 44 I/O on C1
and C2 models, the ZEN-20C offers extended flexibility, with features such as
calendar and real time clock functionality.
• ZEN-20C1/C2 expandable up to 44 I/Os
• ZEN DC units have analogue input 0-10 VDC
• DC models have as well high speed counter 150 Hz
• Expansion available with relay output or transistor output
Ordering information
Specifications
Accessories
Name Number of
I/O points
Inputs (I)/
power supply
Outputs (Q) Type LCD, buttons
(B), calendar
and clock
Analogue
input/
comparators
(A)
8-digit
counter (F)/
comparators
(G)
No. of bits 16 No. of bits 8 Size in mm
(HxWxD)
Order code
CPU units 20 12 100 to 240 VAC 8 Relays LCD yes – – Work bits (M)
Holding bits (H)
Timers (T)
Counters (C)
Weekly timers (@)
LCD display (D)
Timer/counter
comparator (P)
Holding timers (#)
Button input (B)
90x122.5 x56 ZEN-20C1AR-A-V2
Expandable
up to 44 I/O
LED – – – ZEN-20C2AR-A-V2
12 to 24 VDC LCD yes yes / 4 yes / 4 ZEN-20C1DR-D-V2
LED – yes / 4 yes / 4 ZEN-20C1DR-D-V2
Transistors
LCD yes yes / 4 yes / 4 ZEN-20C1DT-D-V2
LED – yes / 4 yes / 4 ZEN-20C2DT-D-V2
Fixed I/O 100 to 240 VAC Relays LCD yes – yes / 4 ZEN-20C3AR-A-V2
12 to 24 VDC LCD yes yes / 4 yes / 4 ZEN-20C3DR-D-V2
Item Specifications
ZEN-20C_AR-A-V2 ZEN-20C_D_-D-V2
Power supply voltage 100 to 240 VAC, 50/60 Hz 12 to 24 VDC (DC ripple rate: 5%)
Rated power supply voltage 85 to 264 VAC 10.8 to 28.8 VDC
Power consumption 11 VA max. 5 W max.
Inrush current 4 A max. 30 A max.
Ambient temperature 0°C to 55°C (-25°C to 55°C for ZEN-20C2 models (LED))
Ambient storage -20°C to 55°C (-40°C to 75°C for ZEN-20C2 models (LED))
Control method Stored program control
I/O control method Cyclic scan
Programming language Ladder diagram
Program capacity 96 lines (3 input conditions and 1 output per line)
LCD display 12 characters x 4 lines, with backlight (LCD-type CPU unit only)
Operation keys 8 (4 cursor keys and 4 operation keys) (LCD-type CPU unit only)
Super-capacitor holding time 2 days min. (25°C)
Battery life (ZEN-BAT01) 10 years min. (25°C)
Calendar & Clock function Accuracy: ± 15 s/month (at 25°C) if applicable
Name Description Order code
Memory Cassette EEPROM (for data security and copying) ZEN-ME01
Battery unit Battery (keeps time, date and bit values for 10 years at 25°C) ZEN-BAT01
Connecting Cable For the programming software, RS-232C cable, 9-way `D' connector for PC ZEN-CIF01
USB-Serial conversion cable USB-Serial conversion cable (to be used in combination with ZEN-CIF01) CS1W-CIF31
ZEN support software Runs on Windows ME, 2000, XP, NT4.0 Service Pack 3, Vista ZEN-SOFT01-V4
454
ZEN-8E Programmable relays
ZEN Expansion units
To enlarge your ZEN application we provide three different expansion units in
only 35 mm width ZEN housing. All expansion units have standard 4 inputs and
4 outputs. You can add maximum 3 expansion units to one CPU.
• 4 inputs, 100 to 240VAC or 12 to 24VDC
• 4 outputs, either relays or transistors (only DC models)
• DIN-rail mounting
• Size in mm (HxWxD): 90x35x56
Ordering information
Specifications
Name Number of I/O points Inputs (X)/
power supply
Outputs (Y) Size in mm (HxWxD) Order code
Expansion I/O units 8 4 100 to 240 VAC 4 Relays 90x35x56 ZEN-8E1AR
12 to 24 VDC ZEN-8E1DR
Transistors ZEN-8E1DT
Item Specifications
ZEN-8E1AR ZEN-8E1D_
Power supply voltage 100 to 240 VAC, 50/60 Hz 12 to 24 VDC (DC ripple rate: 5% max.)
Rated power supply voltage 85 to 264 VAC 10.8 to 28.8 VDC
Power consumption 4 VA max. 2 W max.
Inrush current 1.5 A max. 15 A max.
Ambient temperature 0°C to 55°C (-25°C to 55°C for ZEN-10C2 models (LED))
Ambient storage -20°C to 55°C (-40°C to 75°C for ZEN-10C2 models (LED))
455
23 Programmable relays
ZEN-PA Programmable relays
ZEN Power Supply
The ZEN Power Supply has the same compact housing as our 10 I/O CPU units.
With a current/wattage output of 1.3 A/30 W it covers enough power to supply
the DC ZEN itself and the eventually used sensors. If needed parallel operation is
possible.
• Output voltage 24 VDC
• Output current 1.3 A
• Capacity 30 W
• Allows parallel operation
• Size in mm (HxWxD): 90x70x56
Ordering information
Specifications
Power rating Inputs voltage Output current Order code
30 W 100 to 240 VAC 1.3 A ZEN-PA03024
Item Specifications
Power rating 30 W
Efficiency 80% min. (24 V)
Input voltage 100 to 240 VAC (85 to 264 VAC), single-phase
Output voltage Voltage adjustment ±10% to ±15% (with V. ADJ) min. of rate output voltage
Ripple 2% (p-p) max. (-25°C to -10°C: 4% max.)
Input variation 0.5% max.
Temperature 0.05% / °C max.
Overload protection 105% to 135% of rated load current, inverted L drop, intermittent
Overvoltage protection yes
Input Current 100 V 0.8 A max.
200 V 0.45 A max.
Output indicator yes (green)
Weight 240 g max.
Operating temperature -10°C to 60°C
Parallel operation yes (2 units max.)
Which size is required?
K3GN K3MA-J K3MA-L K3MA-F
Which application is required?
Process Temperature
Frequency/
rate
Process/
frequency/
rate
General purpose
48x24 mm
(1/32 DIN)
LOOKING FOR PERFECT MEASURING & READ-OUT?
With our K3HB series we cover a wide range of applications. One of them is the
weighing indicator which performs perfect measurement in any weighing application.
The instrument can be equipped with a load-cell power supply of 10 V/100 mA.
Several option boards for communication, contact output boards or event inputs
are also available. On top of these you can get direct DeviceNet communication.
• High speed sampling 20 ms
• Equipped with position meter
• Two colour display for easy recognition
K3HB-V – For perfect weighing
456
Page 460 Page 461 Page 461 Page 461
Digital panel indicators
Which application is required?
K3HB-X
Process
K3HB-H
Temperature
Advanced
K3HB-V
Weighing
96x48 mm
(1/8 DIN)
K3HB-S
Linear sensor
K3HB-R
Rotary pulse
K3HB-P
Time interval
K3HB-C
Up/down
counting pulse
457
24 Digital panel indicators
Page 462 Page 462 Page 462 Page 462 Page 464 Page 464 Page 464
458
Selection table
Category Multifunctional digital
panel indicator Process indicator Temperature indicator Frequency/rate indicator Process indicator
Selection criteria
Model K3GN K3MA-J K3MA-L K3MA-F K3HB-X
Size 1/32 DIN 1/8 DIN
Features
Colour change display
Number of digits 5 5 4 5 5
Leading zero suppression
Forced zero function
Min./max. hold function
Average processing
User selectable inputs
Start-up compensating time – – –
Key protection
Decimal point position setting
Accuracy ±0.1% of full scale ±0.1% of full scale ±0.1% of full scale ±0.1% of full scale ±0.1% of full scale
(DC voltage &
DC current),
±0.5% of full scale
(AC voltage & AC current)
Input range 0 to 20 mA, 4 to 20 mA
or 0 to 5 V, 1 to 5 V,
-5 to 5 V, -10 to 10 V or
0 to 30 Hz or 0 to 5 kHz
0 to 20 mA, 4 to 20 mA
or 0 to 5 V, 1 to 5 V,
-5 to 5 V, -10 to 10 V
Pt100, JPt100 or
thermocouple K, J, T, E, L,
U, N, R, S, B
0 to 30 Hz or 0 to 5 kHz 0.000 to 10.000 A, 0.0000
to 19.999 mA, -199.99 to
199.99 mA, 4.000 to
20.000 mA, 0.0 to 400.0
V, 0.0000 to 1.999 V,
-199.99 to 199.99 V,
1.0000 to 5.0000 V
Sample rate 250 ms 250 ms 500 ms – 20 ms
Features Remote/local processing,
parameter initialisation,
programmable output
configuration,
process value hold
Teaching, comparative
output pattern selection,
parameter initialisation,
programmable output
configuration,
process value hold
Programmable output
configuration,
process value hold
Teaching, comparative
output pattern selection,
programmable output
configuration,
process value hold
Scaling, teaching,
averaging, output
hysteresis, output
OFF-delay, output test,
bank selection, reset,
comparative output
Sensor power supply – – –
Front
protection
IP rating IP66 IP66 IP66 IP66 IP66
Supply voltage 24 VDC 24 VAC/VDC or
100 to 240 VAC
24 VAC/VDC or
100 to 240 VAC
24 VAC/VDC or
100 to 240 VAC
100 to 240 VAC or
24 VAC/VDC
Inputs
NPN –
PNP –
Temperature – – – – –
Contact – – – –
Voltage pulse – – – –
Load cell – – – – –
DC voltage –
DC current – –
AC voltage – – – –
AC current – – – –
Outputs
Relay
NPN – – –
PNP – – –
Linear – – – –
BCD – – – – –
Comms – – –
Page 460 461 462
Digital panel indicators
459
24 Digital panel indicators
Temperature indicator Weighing indicator Linear sensor indicator Up/down counting pulse
indicator Time interval indicator Rotary pulse indicator
K3HB-H K3HB-V K3HB-S K3HB-C K3HB-P K3HB-R
1/8 DIN – –
5 5 5 5 5 5
– – – – –
Thermocouple: ±0.3%
of full scale,
Pt-100: ±0.2% of full scale
±0.1% of full scale One input: ±0.1%
of full scale,
two inputs: ±0.2%
of full scale
±0.08% rgd ±1 digit ±0.006% rgd ±1 digit
±0.02% rgd ±1 digit
Pt100, thermocouple K, J, T,
E, L, U, N, R, S, B, W
0.00 to 199.99 mV,
0.000 to 19.999 mV,
100.00 mV, 199.99 mV
0 to 20 mA, 4 to 20 mA,
0 to 5 V, -5 to 5 V,
-10 to 10 V
No voltage contact:
30 Hz, voltage pulse:
50 kHz, open collector:
50 kHz
No voltage contact:
30 Hz, voltage pulse:
50 kHz, open collector:
50 kHz
No voltage contact:
30 Hz, voltage pulse:
50 kHz, open collector:
50 kHz
20 ms 20 ms 0.5 ms – – –
Scaling, teaching, averaging,
output hysteresis, output
OFF-delay, output test, bank
selection, reset, comparative
output
Scaling, teaching, averaging,
output hysteresis, output
OFF-delay, output test, bank
selection, reset, comparative
output
Scaling, 2-input calculation,
teaching, averaging, output
hysteresis, output OFFdelay,
output test, bank
selection, reset, comparative
output
Scaling, measurement
operation selection, output
hysteresis, output OFFdelay,
output test, display
value selection, display
colour selection, key
protection, bank selection,
display refresh period,
maximum/minimum hold,
reset
Scaling, measurement
operation selection, output
hysteresis, output OFFdelay,
output test, teaching,
display value selection,
display colour selection, key
protection, bank selection,
display refresh period,
maximum/minimum hold,
reset
Scaling, measurement
operation selection,
averaging, previous average
value comparison, output
hysteresis, output
OFF-delay, output test,
teaching, display value
selection, display colour
selection, key protection,
bank selection,
display refresh period,
maximum /minimum hold,
reset
IP66 IP66 IP66 IP66 IP66 IP66
100 to 240 VAC or
24 VAC/VDC
100 to 240 VAC or
24 VAC/VDC
100 to 240 VAC or
24 VAC/VDC
100 to 240 VAC or
24 VAC/VDC
100 to 240 VAC or
24 VAC/VDC
100 to 240 VAC or
24 VAC/VDC
– – – – –
– – – – – –
– – –
– – – – –
– – – – –
– – – – –
– – – – – –
– – – – – –
– – –
462 464
Standard Available – No/not available
460
K3GN 1/32 DIN multi-function
Compact and intelligent digital
panel meter
The K3GN is able to cover a wide variety of applications with its 3 main functions:
process meter, RPM processor/tachometer and digital data display for PC/PLC.
Configuration is easy and the design is advanced and compact.
• Process indicator DC voltage/current
• RPM process/tachometer
• Digital data display for PC/PLC
• Very compact 1/32 DIN housing: Size in mm (HxWxD): 24x48x83mm
• 5-digit display with programmable display colour, in red or green
Ordering information
Specifications
Input type Supply voltage Output Order code
No communications RS-485
DC voltage/current, NPN 24 VDC Dual relays (SPST-NO) K3GN-NDC 24 DC K3GN-NDC-FLK 24 DC
Three NPN open collector K3GN-NDT1 24 DC K3GN-NDT1-FLK 24 DC
DC voltage/current, PNP Dual relays (SPST-NO) K3GN-PDC 24 DC K3GN-PDC-FLK 24 DC
Three PNP open collector K3GN-PDT2 24 DC K3GN-PDT2-FLK 24 DC
Supply voltage 24 VDC
Operating voltage range 85 to 110% of the rated supply voltage
Power consumption 2.5 W max. (at max. DC load with all indicators lit)
Ambient temperature Operating: -10 to 55°C (with no condensation or icing)
Storage: -25 to 65°C (with no condensation or icing)
Display refresh period Sampling period (sampling times multiplied by number of averaging times if average processing is selected)
Max. displayed digits 5 digits (-19999 to 99999)
Display 7-segment digital display, character height: 7.0 mm
Polarity display “-” is displayed automatically with a negative input signal
Zero display Leading zeros are not displayed
Scaling function Programmable with front-panel key inputs (range of display: -19999 to 99999).
The decimal point position can be set as desired.
External controls HOLD: (measurement value held)
ZERO: (forced-zero)
Hysteresis setting Programmable with front-panel key inputs (0001 to 9999)
Other functions Programmable colour display
Selectable output operating action
Teaching set values
Average processing (simple average)
Lockout configuration
Communications writing control (communications output models only)
Output Relays: 2 SPST-NO
Transistors: 3 NPN open collector
3 PNP open collector
Combinations:
Communications output (RS-485) + relay outputs
Communications output (RS-485) + transistor outputs
Communications output (RS-485) + transistor outputs (3 PNP open collector)
Communications Communications function: RS-485
Delay in comparative outputs (transistor outputs) 750 ms max.
Degree of protection Front-panel: NEMA4X for indoor use (equivalent to IP66)
Rear case: IEC standard IP20
Terminals: IEC standard IP20
Memory protection Non-volatile memory (EEPROM) (possible to rewrite 100,000 times)
Size in mm (HxWxD) 24x48x80
461
24 Digital panel indicators
K3MA-J, -L, -F 1/8 DIN standard indicators
Highly visible LCD display with
2 colour (red and green) LEDs
The K3MA series comes with a process meter, a frequency/rate meter and a temperature
meter of either 100 to 240 VAC or 24 VAC/VDC. All are equipped with the same
quality display and have the same short depth of 80 mm.
• 1/8 DIN size housing
• Highly visible, negative transmissive backlit LCD display
• 14.2 mm high characters
• 5 digits (-19,999 to 99,999), K3MA-L: 4 digits
• Front-panel IP66
Ordering information
Accessories
Specifications
Indicator Supply voltage Input type & ranges Output Order code
Process meter 100 to 240 VAC DC voltage: 0 to 5 V, 1 to 5 V, -5 to 5 V, -10 to 10 V
DC current: 0 to 20 mA, 4 to 20 mA
2 relay contact outputs (SPST-NO) K3MA-J-A2 100-240VAC
24 VAC/VDC 2 relay contact outputs (SPST-NO) K3MA-J-A2 24VAC/VDC
Temperature meter 100 to 240 VAC Platinum-resistance thermometer: Pt100, JPt100
or thermocouple K, J, T, E, L, U, N, R, S, B
1 relay contact output (SPDT) K3MA-L-C 100-240VAC
24 VAC/VDC 1 relay contact output (SPDT) K3MA-L-C 24VAC/VDC
Frequency/rate meter 100 to 240 VAC Rotary pulse: No voltage: 0.05 to 30.00 Hz;
open collector: 0.1 to 5000.0 Hz
2 relay contact outputs (SPST-NO) K3MA-F-A2 100-240VAC
24 VAC/VDC 2 relay contact outputs (SPST-NO) K3MA-F-A2 24VAC/VDC
Type Order code
Splash-proof soft cover K32-49SC
Hard cover K32-49HC
Item 100-240 VAC models 24 VAC/VDC models
Supply voltage 100 to 240 VAC 24 VAC (50/60 Hz), 24 VDC
Operating voltage range 85 to 110% of the rated supply voltage
Power consumption (under maximum load) 6 VA max. 4.5 VA max. (24 VAC) 4.5 W max. (24 VDC)
Ambient temperature Operating: -10 to 55°C (with no condensation or icing)
Storage: -25 to 65°C (with no condensation or icing)
Weight Approx. 200 g
Display 7-segment digital display, character height: 14.2 mm
Polarity display "-" is displayed automatically with a negative input signal
Zero display Leading zeros are not displayed
Hold function Max. hold (maximum value), min. hold (minimum value)
Hysteresis setting Programmable with front-panel key inputs (0001 to 9,999)
Delay in comparative outputs 1 s max.
Degree of protection Front-panel: NEMA4X for indoor use (equivalent to IP66)
Rear case: IEC standard IP20
Terminals: IEC standard IP00 + finger protection (VDE 0106/100)
Memory protection Non-volatile memory (EEPROM) (possible to rewrite 100,000 times)
Size in mm (HxWxD) 48x96x80
462
K3HB-X, -H, -V, -S 1/8 DIN advanced indicators - analogue input
Process, temperature, weighing and linear
sensor indicators
These indicators with analogue input feature a clear and easy-to-use colour change
display. All models are equipped with an IP66 housing. K3HB series is high speed,
with a sample rate of 50 Hz, and even 2,000 Hz for K3HB-S
• Position meter indication for easy monitoring
• Optional DeviceNet, RS-232C, RS-485
• Double display, with 5 digits, in two colours
• 1/8 DIN size housing
Ordering information
Option boards
Sensor power supply/output boards
Relay/transistor output boards
Event input boards
*1 CPA/CPB can be combined with relay outputs only.
*2 Only one of the following can be used by each digital indicator: RS-232C/RS-485 communications, a linear output, or DeviceNet communications.
K3HB has got three slots for option boards: Slot B, slot C and slot D.
Accessories
Type of indicator Input sensor type and range Supply voltage Order code
Process indicator
K3HB-X
AC current input, from 0.000 to 10.000 A, 0.0000 to 19.999 mA 100 to 240 VAC K3HB-XAA 100-240VAC
24 VAC/VDC K3HB-XAA 24VAC/VDC
DC current input, from ±199.99 mA, to 4.000 to 20.000 mA 100 to 240 VAC K3HB-XAD 100-240VAC
24 VAC/VDC K3HB-XAD 24VAC/VDC
AC voltage input, from 0.0 to 400.0 V to 0.0000 to 1.999 V 100 to 240 VAC K3HB-XVA 100-240VAC
24 VAC/VDC K3HB-XVA 24VAC/VDC
DC voltage input, from ±199.99 V to 1.0000 to 5.0000 V 100 to 240 VAC K3HB-XVD 100-240VAC
24 VAC/VDC K3HB-XVD 24VAC/VDC
Temperature indicator
K3HB-H
Temperature input Pt100, thermocouple K, J, T, E, L, U, N, R, S, B, W 100 to 240 VAC K3HB-HTA 100-240VAC
24 VAC/VDC K3HB-HTA 24VAC/VDC
Weighing indicator
K3HB-V
Load cell input (DC low voltage input), 0.00 to 199.99 mV, 0.000 to 19.999 mV,
100.00 mV, 199.999 mV
100 to 240 VAC K3HB-VLC 100-240 VAC
24 VAC/VDC K3HB-VLC 24VAC/VDC
Linear sensor indicator
K3HB-S
DC process input, 0 to 5 V, 1 to 5 V, -5 to 5 V, -10 to 10 V, 0 to 20 mA, 4 to 20 mA 24 VAC/VDC K3HB-SSD AC/DC24
100 to 240 VAC K3HB-SSD AC100-240
Slot Output Sensor power supply Communications Applicable indicator types Order code
B Relay PASS: SPDT 12 VDC ±10%, 80 mA – K3HB-X, -H, -S K33-CPA *1
Linear current DC0(4) - 20 mA – K3HB-X, -H, -S K33-L1 A *2
Linear voltage DC0(1) - 5 V, 0 to 10 V – K3HB-X, -H, -S K33-L2A *2
– – – K3HB-X, -H, -S K33-A *2
– – RS-232C K3HB-X, -H, -S K33-FLK1 A *2
– – RS-485 K3HB-X, -H, -S K33-FLK3A *2
Relay PASS: SPDT 10 VDC ±5%, 100 mA – K3HB-V K33-CPB *1
Linear current DC0(4) - 20 mA – K3HB-V K33-L1B *2
Linear voltage DC0(1) - 5 V, 0 to 10 V – K3HB-V K33-L2B *2
– – – K3HB-V K33-B *2
– – RS-232C K3HB-V K33-FLK1B *2
– – RS-485 K3HB-V K33-FLK3B *2
Slot Output Communications Order code
C Relay H/L: SPDT each – K34-C1
HH/H/LL/L: SPST-NO each – K34-C2
Transistor NPN open collector: HH/H/PASS/L/LL – K34-T1
PNP open collector: HH/H/PASS/L/LL – K34-T2
– – DeviceNet K34-DRT *2
Slot Input type Number of points Communications Order code
D NPN open collector 5 M3 terminal blocks K35-1
8 10-pin MIL connector K35-2
PNP open collector 5 M3 terminal blocks K35-3
8 10-pin MIL connector K35-4
Type Order code
Special cable (for event inputs with 8-pin connector) K32-DICN
K3HB-X, -H, -V, -S 1/8 DIN advanced indicators - analogue input
463
24 Digital panel indicators
Specifications
Power supply voltage 100 to 240 VAC (50/60 Hz), 24 VAC/VDC, DeviceNet power supply: 24 VDC
Allowable power supply voltage range 85 to 110% of the rated power supply voltage, DeviceNet power supply: 11 to 25 VDC
Power consumption 100 to 240 V: 18 VA max. (max. load), 24 VAC/DC: 11 VA/7 W max. (max. load)
Display method Negative LCD (backlit LED) display 7-segment digital display
(character height: PV: 14.2 mm (green/red); SV: 4.9 mm (green))
Ambient operating temperature -10 to 55°C (with no icing or condensation)
Display range -19,999 to 99,999
Weight Approx. 300 g (base unit only)
Degree of protection Front-panel Conforms to NEMA 4X for indoor use (equivalent to IP66)
Rear case IP20
Terminals IP00 + finger protection (VDE0106/100)
Memory protection EEPROM (non-volatile memory), number of rewrites: 100,000
Event input ratings Contact ON: 1 k max., OFF: 100 k min.
No-contact ON residual voltage: 2 V max., OFF leakage current: 0.1 mA max., load current: 4 mA max.
Maximum applied voltage: 30 VDC max.
Output ratings Transistor output Maximum load voltage 24 VDC
Maximum load current 50 mA
Leakage current 100 μA max.
Contact output
(resistive load)
Rated load 5 A at 250 VAC, 5 A at 30 VDC
Rated through current 5 A
Mechanical life expectancy 5,000,000 operations
Electrical life expectancy 100,000 operations
Linear output Allowable load impedance 500 max. (mA); 5 k min. (V)
Resolution Approx. 10,000
Output error ±0.5% FS
Size in mm (HxWxD) 48x96x100
464
K3HB-C, -P, -R 1/8 DIN advanced indicators - digital input
Rotary pulse, timer interval and
up/down counting pulse indicators
These indicators with analogue input feature a clear and easy-to-use colour change
display. All models are equipped with an IP66 housing. K3HB-R and -C are highspeed,
with a sample rate up to 50 kHz.
• Position meter indication for easy monitoring
• Optional DeviceNet, RS-232C, RS-485
• Double display, with 5 digits, in two colours
• 1/8 DIN size housing
Ordering information
Option boards
Sensor power supply/output boards
Relay/transistor output boards
Event input boards
*1 CPA can be combined with relay outputs only.
*2 Only one of the following can be used by each digital indicator: RS-232C/RS-485 communications, a linear output, or DeviceNet communications.
K3HB has got three slots for option boards: Slot B, slot C and slot D.
Accessories
Type of indicator Input ranges Supply voltage Input sensor Order code
Rotary pulse indicator K3HB-R No voltage contact: 30 Hz max.
Voltage pulse: 50 kHz max.
Open collector: 50 kHz max.
100 to 240 VAC NPN input/voltage pulse K3HB-RNB 100-240VAC
24 VAC/VDC K3HB-RNB 24VAC/VDC
100 to 240 VAC PNP input K3HB-RPB 100-240VAC
24 VAC/VDC K3HB-RPB 24VAC/VDC
100 to 240 VAC NPN K3HB-PNB 100-240VAC
100 to 240 VAC PNP K3HB-PPB 100-240VAC
Timer interval indicator K3HB-P 24 VAC/VDC PNP K3HB-PPB 24VAC/VDC
100 to 240 VAC NPN K3HB-CNB 100-240VAC
Up/down counting pulse indicator K3HB-C 24 VAC/VDC NPN K3HB-CNB 24VAC/VDC
24 VAC/VDC PNP K3HB-CPB 24VAC/VDC
Slot Output Sensor power supply Communications Order code
B Relay PASS: SPDT 12 VDC ±10%, 80 mA – K33-CPA *1
Linear current DC0(4) - 20 mA – K33-L1 A *2
Linear voltage DC0(1) - 5 V, 0 to 10 V – K33-L2A *2
– – – K33-A *2
– – RS-232C K33-FLK1 A *2
– – RS-485 K33-FLK3A *2
Slot Output Communications Order code
C Relay H/L: SPDT each – K34-C1
HH/H/LL/L: SPST-NO each – K34-C2
Transistor NPN open collector: HH/H/PASS/L/LL – K34-T1
PNP open collector: HH/H/PASS/L/LL – K34-T2
– DeviceNet K34-DRT *2
BCD + transistor NPN open collector: HH/H/PASS/L/LL – K34-BCD
Slot Input type Number of points Communications Order code
D NPN open collector 5 M3 terminal blocks K35-1
8 10-pin MIL connector K35-2
PNP open collector 5 M3 terminal blocks K35-3
8 10-pin MIL connector K35-4
Type Order code
Special cable (for event inputs with 8-pin connector) K32-DICN
Special BCD output cable K32-BCD
K3HB-C, -P, -R 1/8 DIN advanced indicators - digital input
465
24 Digital panel indicators
Specifications
Power supply voltage 100 to 240 VAC (50/60 Hz), 24 VAC/VDC, DeviceNet power supply: 24 VDC
Allowable power supply voltage range 85 to 110% of the rated power supply voltage, DeviceNet power supply: 11 to 25 VDC
Power consumption 100 to 240 V: 18 VA max. (max. load), 24 VAC/DC: 11 VA/7 W max. (max. load)
Display method Negative LCD (backlit LED) display 7-segment digital display
(character height: PV: 14.2 mm (green/red); SV: 4.9 mm (green))
Ambient operating temperature -10 to 55°C (with no icing or condensation)
Display range -19,999 to 99,999
Weight Approx. 300 g (base unit only)
Degree of protection Front-panel Conforms to NEMA 4X for indoor use (equivalent to IP66)
Rear case IP20
Terminals IP00 + finger protection (VDE0106/100)
Memory protection EEPROM (non-volatile memory), number of rewrites: 100,000
Event input ratings Contact ON: 1 k max., OFF: 100 k min.
No-contact ON residual voltage: 2 V max., OFF leakage current: 0.1 mA max., load current: 4 mA max.
Maximum applied voltage: 30 VDC max.
Output ratings Transistor output Maximum load voltage 24 VDC
Maximum load current 50 mA
Leakage current 100 μA max.
Contact output
(resistive load)
Rated load 5 A at 250 VAC, 5 A at 30 VDC
Rated through current 5 A
Mechanical life expectancy 5,000,000 operations
Electrical life expectancy 100,000 operations
Linear output Allowable load impedance 500 max. (mA); 5 k min. (V)
Resolution Approx. 10,000
Output error ±0.5% FS
Size in mm (HxWxD) 48x96x100
2010 Microchip Technology Inc. Preliminary DS41350E
PIC18F/LF1XK50
Data Sheet
20-Pin USB Flash Microcontrollers
with nanoWatt XLP Technology
DS41350E-page 2 Preliminary 2010 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-624-1
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2010 Microchip Technology Inc. Preliminary DS41350E-page 3
PIC18F/LF1XK50
Universal Serial Bus Features:
• USB V2.0 Compliant SIE
• Full Speed (12 Mb/s) and Low Speed (1.5 Mb/s)
• Supports Control, Interrupt, Isochronous and
Bulk Transfers
• Supports up to 16 Endpoints (8 bidirectional)
• 256-byte Dual Access RAM for USB
• Input-change interrupt on D+/D- for detecting
physical connection to USB host
High Performance RISC CPU:
• C Compiler Optimized Architecture:
- Optional extended instruction set designed to
optimize re-entrant code
- 256 bytes, data EEPROM
- Up to 16 Kbytes linear program memory
addressing
- Up to 768 bytes linear data memory
addressing
• Priority levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
Flexible Oscillator Structure:
• CPU divider to run the core slower than the USB
peripheral
• 16 MHz Internal Oscillator Block:
- Software selectable frequencies, 31 kHz to
16 MHz
- Provides a complete range of clock speeds
from 31 kHz to 32 MHz when used with PLL
- User tunable to compensate for frequency
drift
• Four Crystal modes, up to 48 MHz
• External Clock modes, up to 48 MHz
• 4X Phase Lock Loop (PLL)
• Secondary oscillator using Timer1 at 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if primary or secondary
oscillator stops
• Two-speed Oscillator Start-up
Special Microcontroller Features:
• Full 5.5V Operation – PIC18F1XK50
• 1.8V-3.6V Operation – PIC18LF1XK50
• Self-programmable under Software Control
• Programmable Brown-out Reset (BOR)
- With software enable option
• Extended Watchdog Timer (WDT)
- Programmable period from 4ms to 131s
• Single-supply 3V In-Circuit Serial Programming™
(ICSP™) via two pins
Extreme Low-Power Management
PIC18LF1XK50 with nanoWatt XLP:
• Sleep mode: 24 nA
• Watchdog Timer: 450 nA
• Timer1 Oscillator: 790 nA @ 32 kHz
Analog Features:
• Analog-to-Digital Converter (ADC) module:
- 10-bit resolution, 9 external channels
- Auto acquisition capability
- Conversion available during Sleep
- Internal 1.024V Fixed Voltage Reference
(FVR) channel
- Independent input multiplexing
• Dual Analog Comparators
- Rail-to-rail operation
- Independent input multiplexing
• Voltage Reference module:
- Programmable (% of VDD), 16 steps
- Two 16-level voltage ranges using VREF pins
- Programmable Fixed Voltage Reference
(FVR), 3 levels
• On-chip 3.2V LDO Regulator – (PIC18F1XK50)
Peripheral Highlights:
• 14 I/O Pins plus 1 Input-only pin:
- High-current sink/source 25 mA/25 mA
- 7 Programmable weak pull-ups
- 7 Programmable Interrupt-on-change pins
- 3 programmable external interrupts
- Programmable slew rate
• Enhanced Capture/Compare/PWM (ECCP)
module:
- One, two, three, or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and Auto-restart
• Master Synchronous Serial Port (MSSP) module:
- 3-wire SPI (supports all 4 modes)
- I2C™ Master and Slave modes (Slave mode
address masking)
• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module:
- Supports RS-485, RS-232 and LIN 2.0
- RS-232 operation using internal oscillator
- Auto-Baud Detect
- Auto-Wake-up on Break
• SR Latch mode
20-Pin USB Flash Microcontrollers with nanoWatt XLP Technology
PIC18F/LF1XK50
DS41350E-page 4 Preliminary 2010 Microchip Technology Inc.
-
Pin Diagrams
Pin Diagrams
Device
Program Memory Data Memory
I/O(1)
10-bit
A/D
(ch)(2)
ECCP
(PWM)
MSSP
EUSART
Comp. Timers
Flash 8/16-bit USB
(bytes)
# Single-Word
Instructions
SRAM
(bytes)
EEPROM
(bytes) SPI Master
I2C™
PIC18F13K50/
PIC18LF13K50
8K 4096 512(3) 256 15 11 1 Y Y 1 2 1/3 Y
PIC18F14K50/
PIC18LF14K50
16K 8192 768(3) 256 15 11 1 Y Y 1 2 1/3 Y
Note 1: One pin is input only.
2: Channel count includes internal Fixed Voltage Reference (FVR) and Programmable Voltage Reference (CVREF) channels.
3: Includes the dual port RAM used by the USB module which is shared with the data memory.
20-pin PDIP, SSOP, SOIC (300 MIL)
10
2
345
6
1
8
7
9
11
12
13
14
15
16
19
20
18
17
VDD
RA5/IOCA5/OSC1/CLKIN
RA4/AN3/IOCA3/OSC2/CLKOUT
RA3/IOCA3/MCLR/VPP
RC5/CCP1/P1A/T0CKI
RC4/P1B/C12OUT/SRQ
RC3/AN7/P1C/C12IN3-/PGM
RC6/AN8/SS/T13CKI/T1OSCI
RC7/AN9/SDO/T1OSCO
RB7/IOCB7/TX/CK
VSS
RA0/IOCA0/D+/PGD
RA1/IOCA1/D-/PGC
VUSB
RC0/AN4/C12IN+/INT0/VREF+
RC1/AN5/C12IN1-/INT1/VREFRC2/
AN6/P1D/C12IN2-/CVREF/INT2
RB4/AN10/IOCB4/SDI/SDA
RB5/AN11/IOCB5/RX/DT
RB6/IOCB6/SCK/SCL
PIC18F/LF1XK50
20-pin QFN (5x5)
8 9
23
1
14
15
16
10
11
6
12
13
20 19 18 17
7
5
4
PIC18F1XK50/
PIC18LF1XK50
RA3/MCLR/VPP
RC5/CCP1/P1A/T0CKI
RC4/P1B/C12OUT/SRQ
RC3/AN7/P1C/C12IN3-/PGM
RC6/AN8/SS/T13CKI/T1OSCI
RC7/AN9/SDO/T1OSCO
RB7/TX/CK
RB4/AN10/SDI/SDA
RB5/AN11/RX/DT
RB6/SCK/SCL
RC2/AN6/P1D/C12IN2-/CVREF/INT2
RC1/AN1/C12IN1-/INT1/VREFRC0/
AN4/C12IN+/INT0/VREF+
VUSB
RA1/D-/PGC
RA0/D+/PGD
Vss
VDD
RA4/AN3/OSC2/CLKO
RA5/OSC1/CLKI
2010 Microchip Technology Inc. Preliminary DS41350E-page 5
PIC18F/LF1XK50
TABLE 1: PIC18F/LF1XK50 PIN SUMMARY
Pin
I/O
Analog
Comparator
Reference
ECCP
EUSART
MSSP
Timers
Interrupts
Pull-up
USB
Basic
19 RA0 IOCA0 D+ PGD
18 RA1 IOCA1 D- PGC
4 RA3(1) IOCA3 Y MCLR/VPP
3 RA4 AN3 IOCA4 Y OSC2/CLKOUT
2 RA5 IOCA5 Y OSC1/CLKIN
13 RB4 AN10 SDI/SDA IOCB4 Y
12 RB5 AN11 RX/DT IOCB5 Y
11 RB6 SCL/SCK IOCB6 Y
10 RB7 TX/CK IOCB7 Y
16 RC0 AN4 C12IN+ VREF+ INT0
15 RC1 AN5 C12IN1- VREF- INT1
14 RC2 AN6 C12IN2- CVREF P1D INT2
7 RC3 AN7 C12IN3- P1C PGM
6 RC4 C12OUT P1B SRQ
5 RC5 CCP1/P1A T0CKI
8 RC6 AN8 SS T13CKI/T1OSCI
9 RC7 AN9 SDO T1OSCO
17 VUSB
1 VDD
20 VSS
Note 1: Input only.
PIC18F/LF1XK50
DS41350E-page 6 Preliminary 2010 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 15
3.0 Memory Organization ................................................................................................................................................................. 29
4.0 Flash Program Memory.............................................................................................................................................................. 51
5.0 Data EEPROM Memory ............................................................................................................................................................. 61
6.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 65
7.0 Interrupts .................................................................................................................................................................................... 67
8.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 81
9.0 I/O Ports ..................................................................................................................................................................................... 83
10.0 Timer0 Module ......................................................................................................................................................................... 101
11.0 Timer1 Module ......................................................................................................................................................................... 105
12.0 Timer2 Module ......................................................................................................................................................................... 111
13.0 Timer3 Module ......................................................................................................................................................................... 113
14.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 117
15.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 139
16.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 181
17.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 209
18.0 Comparator Module.................................................................................................................................................................. 223
19.0 Power-Managed Modes ........................................................................................................................................................... 235
20.0 SR Latch................................................................................................................................................................................... 241
21.0 Voltage References.................................................................................................................................................................. 245
22.0 Universal Serial Bus (USB) ...................................................................................................................................................... 251
23.0 Reset ........................................................................................................................................................................................ 277
24.0 Special Features of the CPU.................................................................................................................................................... 291
25.0 Instruction Set Summary .......................................................................................................................................................... 309
26.0 Development Support............................................................................................................................................................... 359
27.0 Electrical Specifications............................................................................................................................................................ 363
28.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 397
29.0 Packaging Information.............................................................................................................................................................. 399
Appendix A: Revision History............................................................................................................................................................. 405
Appendix B: Device Differences......................................................................................................................................................... 406
Index .................................................................................................................................................................................................. 407
The Microchip Web Site ..................................................................................................................................................................... 417
Customer Change Notification Service .............................................................................................................................................. 417
Customer Support .............................................................................................................................................................................. 417
Reader Response .............................................................................................................................................................................. 418
Product Identification System............................................................................................................................................................. 419
2010 Microchip Technology Inc. Preliminary DS41350E-page 7
PIC18F/LF1XK50
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.
We welcome your feedback.
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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• Your local Microchip sales office (see last page)
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When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include
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Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
PIC18F/LF1XK50
DS41350E-page 8 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 9
PIC18F1XK50/PIC18LF1XK50
1.0 DEVICE OVERVIEW
This document contains device specific information for
the following devices:
This family offers the advantages of all PIC18
microcontrollers – namely, high computational
performance at an economical price – with the addition
of high-endurance, Flash program memory. On top of
these features, the PIC18F/LF1XK50 family introduces
design enhancements that make these
microcontrollers a logical choice for many highperformance,
power sensitive applications.
1.1 New Core Features
1.1.1 nanoWatt XLP TECHNOLOGY
All of the devices in the PIC18F/LF1XK50 family incorporate
a range of features that can significantly reduce
power consumption during operation. Key items
include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
• On-the-fly Mode Switching: The powermanaged
modes are invoked by user code during
operation, allowing the user to incorporate powersaving
ideas into their application’s software
design.
• Low Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer are minimized. See
Section 27.0 “Electrical Specifications”
for values.
1.1.2 MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18F/LF1XK50 family offer
ten different oscillator options, allowing users a wide
range of choices in developing application hardware.
These include:
• Four Crystal modes, using crystals or ceramic
resonators
• External Clock modes, offering the option of using
two pins (oscillator input and a divide-by-4 clock
output) or one pin (oscillator input, with the second
pin reassigned as general I/O)
• External RC Oscillator modes with the same pin
options as the External Clock modes
• An internal oscillator block which contains a
16 MHz HFINTOSC oscillator and a 31 kHz
LFINTOSC oscillator which together provide 8
user selectable clock frequencies, from 31 kHz to
16 MHz. This option frees the two oscillator pins
for use as additional general purpose I/O.
• A Phase Lock Loop (PLL) frequency multiplier,
available to both the high-speed crystal and internal
oscillator modes, which allows clock speeds of
up to 48 MHz. Used with the internal oscillator, the
PLL gives users a complete selection of clock
speeds, from 31 kHz to 32 MHz – all without using
an external crystal or clock circuit.
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the LFINTOSC. If a clock
failure occurs, the controller is switched to the
internal oscillator block, allowing for continued
operation or a safe application shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
• PIC18F13K50 • PIC18F14K50
• PIC18LF13K50 • PIC18LF14K50
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 10 Preliminary 2010 Microchip Technology Inc.
1.2 Other Special Features
• Memory Endurance: The Flash cells for both
program memory and data EEPROM are rated to
last for many thousands of erase/write cycles – up to
1K for program memory and 100K for EEPROM.
Data retention without refresh is conservatively
estimated to be greater than 40 years.
• Self-programmability: These devices can write
to their own program memory spaces under
internal software control. Using a bootloader
routine located in the code protected Boot Block,
it is possible to create an application that can
update itself in the field.
• Extended Instruction Set: The PIC18F/
LF1XK50 family introduces an optional extension
to the PIC18 instruction set, which adds 8 new
instructions and an Indexed Addressing mode.
This extension has been specifically designed to
optimize re-entrant application code originally
developed in high-level languages, such as C.
• Enhanced CCP module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include:
- Auto-Shutdown, for disabling PWM outputs
on interrupt or other select conditions
- Auto-Restart, to reactivate outputs once the
condition has cleared
- Output steering to selectively enable one or
more of 4 outputs to provide the PWM signal.
• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation and provides support for the LIN
bus protocol. Other enhancements include
automatic baud rate detection and a 16-bit Baud
Rate Generator for improved resolution.
• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reduce code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit
postscaler, allowing an extended time-out range
that is stable across operating voltage and
temperature. See Section 27.0 “Electrical
Specifications” for time-out periods.
1.3 Details on Individual Family
Members
Devices in the PIC18F/LF1XK50 family are available in
20-pin packages. Block diagrams for the two groups
are shown in Figure 1-1.
The devices are differentiated from each other in the
following ways:
1. Flash program memory:
• 8 Kbytes for PIC18F13K50/PIC18LF13K50
• 16 Kbytes for PIC18F14K50/PIC18LF14K50
2. On-chip 3.2V LDO regulator for PIC18F13K50
and PIC18F14K50.
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1 and I/O
description are in Table 1-2.
2010 Microchip Technology Inc. Preliminary DS41350E-page 11
PIC18F1XK50/PIC18LF1XK50
TABLE 1-1: DEVICE FEATURES FOR THE PIC18F/LF1XK50 (20-PIN DEVICES)
Features PIC18F13K50 PIC18LF13K50 PIC18F14K50 PIC18LF14K50
LDO Regulator Yes No Yes No
Program Memory (Bytes) 8K 16K
Program Memory (Instructions) 4096 8192
Data Memory (Bytes) 512 768
Operating Frequency DC – 48 MHz
Interrupt Sources 30
I/O Ports Ports A, B, C
Timers 4
Enhanced Capture/ Compare/PWM Modules 1
Serial Communications MSSP, Enhanced USART, USB
10-Bit Analog-to-Digital Module 9 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled
Packages 20-Pin PDIP, SSOP, SOIC (300 mil) and QFN (5x5)
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 12 Preliminary 2010 Microchip Technology Inc.
FIGURE 1-1: PIC18F/LF1XK50 BLOCK DIAGRAM
Instruction
Decode and
Control
PORTA
PORTB
PORTC
RA1
RA0
Data Latch
Data Memory
Address Latch
Data Address<12>
12
BSR FSR0 Access
FSR1
FSR2
inc/dec
logic
Address
4 12 4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODH PRODL
8 x 8 Multiply
8
BITOP
8 8
ALU<8>
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PCLATU
PCU
Note 1: RA3 is only available when MCLR functionality is disabled.
2: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used
as digital I/O. Refer to Section 2.0 “Oscillator Module” for additional information.
3: PIC18F13K50/PIC18F14K50 only.
Comparator MSSP EUSART 10-bit
ADC
Timer0 Timer1 Timer2 Timer3
ECCP1
BOR
Data
EEPROM
W
Instruction Bus <16>
STKPTR Bank
8
State machine
control signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(2)
OSC2(2)
VDD,
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
VSS Band Gap
MCLR(1)
Block
LFINTOSC
Oscillator
16 MHz
Oscillator
Single-Supply
Programming
T1OSO
T1OSI
FVR
FVR FVR
CVREF
Address Latch
Program Memory
Data Latch
CVREF
RA3
RA4
RA5
RB4
RB5
RB6
RB7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
(512/768 bytes)
VUSB USB
Module
USB
LDO(3)
Regulator
2010 Microchip Technology Inc. Preliminary DS41350E-page 13
PIC18F1XK50/PIC18LF1XK50
TABLE 1-2: PIC18F/LF1XK50 PINOUT I/O DESCRIPTIONS
Pin Name Pin
Number
Pin
Type
Buffer
Type Description
RA0/D+/PGD
RA0
D+
PGD
19
I
I/O
I/O
TTL
XCVR
ST
Digital input
USB differential plus line (input/output)
ICSP™ programming data pin
RA1/D-/PGC
RA1
DPGC
18
I
I/O
I/O
TTL
XCVR
ST
Digital input
USB differential minus line (input/output)
ICSP™ programming clock pin
RA3/MCLR/VPP
RA3
MCLR
VPP
4
IIP
ST
ST
—
Master Clear (input) or programming voltage (input)
Digital input
Active-low Master Clear with internal pull-up
High voltage programming input
RA4/AN3/OSC2/CLKOUT
RA4
AN3
OSC2
CLKOUT
3
I/O
IO
O
TTL
Analog
XTAL
CMOS
Digital I/O
ADC channel 3
Oscillator crystal output. Connect to crystal or resonator
in Crystal Oscillator mode
In RC mode, OSC2 pin outputs CLKOUT which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate
RA5/OSC1/CLKIN
RA5
OSC1
CLKIN
2
I/O
I
I
TTL
XTAL
CMOS
Digital I/O
Oscillator crystal input or external clock input
ST buffer when configured in RC mode; analog other
wise
External clock source input. Always associated with the
pin function OSC1 (See related OSC1/CLKIN, OSC2,
CLKOUT pins
RB4/AN10/SDI/SDA
RB4
AN10
SDI
SDA
13
I/O
II
I/O
TTL
Analog
ST
ST
Digital I/O
ADC channel 10
SPI data in
I2C™ data I/O
RB5/AN11/RX/DT
RB5
AN11
RX
DT
12
I/O
II I/O
TLL
Analog
ST
ST
Digital I/O
ADC channel 11
EUSART asynchronous receive
EUSART synchronous data (see related RX/TX)
RB6/SCK/SCI
RB6
SCK
SCI
11
I/O
I/O
I/O
TLL
ST
ST
Digital I/O
Synchronous serial clock input/output for SPI mode
Synchronous serial clock input/output for I2C™ mode
RB7/TX/CK
RB7
TX
CK
10
I/O
O
I/O
TLL
CMOS
ST
Digital I/O
EUSART asynchronous transmit
EUSART synchronous clock (see related RX/DT)
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input I = Input
O = Output P = Power
XTAL= Crystal Oscillator XCVR = USB Differential Transceiver
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 14 Preliminary 2010 Microchip Technology Inc.
RC0/AN4/C12IN+/INT0/VREF+
RC0
AN4
C12IN+
INT0
VREF+
16
I/O
IIII
ST
Analog
Analog
ST
Analog
Digital I/O
ADC channel 4
Comparator C1 and C2 non-inverting input
External interrupt 0
Comparator reference voltage (high) input
RC1/AN5/C12IN-/INT1/VREFRC1
AN5
C12ININT1
VREF-
15
I/O
IIII
ST
Analog
Analog
ST
Analog
Digital I/O
ADC channel 5
Comparator C1 and C2 non-inverting input
External interrupt 0
Comparator reference voltage (low) input
RC2/AN6/P1D/C12IN2-/CVREF/INT2
RC2
AN6
P1D
C12IN2-
CVREF
INT2
14
I/O
IOIOI
ST
Analog
CMOS
Analog
Analog
ST
Digital I/O
ADC channel 6
Enhanced CCP1 PWM output
Comparator C1 and C2 inverting input
Comparator reference voltage output
External interrupt 0
RC3/AN7/P1C/C12IN3-/PGM
RC3
AN7
P1C
C12IN3-
PGM
7
I/O
IOI
I/O
ST
Analog
CMOS
Analog
ST
Digital I/O
ADC channel 7
Enhanced CCP1 PWM output
Comparator C1 and C2 inverting input
Low-Voltage ICSP Programming enable pin
RC4/P1B/C12OUT/SRQ
RC4
P1B
C12OUT
SRQ
6
I/O
OOO
ST
CMOS
CMOS
CMOS
Digital I/O
Enhanced CCP1 PWM output
Comparator C1 and C2 output
SR Latch output
RC5/CCP1/P1A/T0CKI
RC5
CCP1
P1A
T0CKI
5
I/O
I/O
OI
ST
ST
CMOS
ST
Digital I/O
Capture 1 input/Compare 1 output/PWM 1 output
Enhanced CCP1 PWM output
Timer0 external clock input
RC6/AN8/SS/T13CKI/T1OSCI
RC6
AN8
SS
T13CKI
T1OSCI
8
I/O
IIII
ST
Analog
TTL
ST
XTAL
Digital I/O
ADC channel 8
SPI slave select input
Timer0 and Timer3 external clock input
Timer1 oscillator input
RC7/AN9/SDO/T1OSCO
RC7
AN9
SDO
T1OSCO
9
I/O
IOO
ST
Analog
CMOS
XTAL
Digital I/O
ADC channel 9
SPI data out
Timer1 oscillator output
VSS 20 P — Ground reference for logic and I/O pins
VDD 1 P — Positive supply for logic and I/O pins
VUSB 17 P — Positive supply for USB transceiver
TABLE 1-2: PIC18F/LF1XK50 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin
Number
Pin
Type
Buffer
Type Description
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input I = Input
O = Output P = Power
XTAL= Crystal Oscillator XCVR = USB Differential Transceiver
2010 Microchip Technology Inc. Preliminary DS41350E-page 15
PIC18F/LF1XK50
2.0 OSCILLATOR MODULE
2.1 Overview
The oscillator module has a variety of clock sources
and features that allow it to be used in a wide range of
applications, maximizing performance and minimizing
power consumption. Figure 2-1 illustrates a block
diagram of the oscillator module.
Key features of the oscillator module include:
• System Clock Selection
- Primary External Oscillator
- Secondary External Oscillator
- Internal Oscillator
• Oscillator Start-up Timer
• System Clock Selection
• Clock Switching
• 4x Phase Lock Loop Frequency Multiplier
• CPU Clock Divider
• USB Operation
- Low Speed
- Full Speed
• Two-Speed Start-up Mode
• Fail-Safe Clock Monitoring
2.2 System Clock Selection
The SCS bits of the OSCCON register select between
the following clock sources:
• Primary External Oscillator
• Secondary External Oscillator
• Internal Oscillator
TABLE 2-1: SYSTEM CLOCK SELECTION
The default state of the SCS bits sets the system clock
to be the oscillator defined by the FOSC bits of the
CONFIG1H Configuration register. The system clock
will always be defined by the FOSC bits until the SCS
bits are modified in software.
When the Internal Oscillator is selected as the system
clock, the IRCF bits of the OSCCON register and the
INTSRC bit of the OSCTUNE register will select either
the LFINTOSC or the HFINTOSC. The LFINTOSC is
selected when the IRCF<2:0> = 000 and the INTSRC
bit is clear. All other combinations of the IRCF bits and
the INTSRC bit will select the HFINTOSC as the
system clock.
2.3 Primary External Oscillator
The Primary External Oscillator’s mode of operation is
selected by setting the FOSC<3:0> bits of the
CONFIG1H Configuration register. The oscillator can
be set to the following modes:
• LP: Low-Power Crystal
• XT: Crystal/Ceramic Resonator
• HS: High-Speed Crystal Resonator
• RC: External RC Oscillator
• EC: External Clock
Additionally, the Primary External Oscillator may be
shut-down under firmware control to save power.
Note: The frequency of the system clock will be
referred to as FOSC throughout this
document.
Configuration Selection
SCS <1:0> System Clock
1x Internal Oscillator
01 Secondary External Oscillator
00
(Default after Reset)
Oscillator defined by
FOSC<3:0>
PIC18F/LF1XK50
DS41350E-page 16 Preliminary 2010 Microchip Technology Inc.
FIGURE 2-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
4 x PLL
FOSC<3:0>
OSC2
OSC1
Sleep
CPU
Peripherals
IDLEN
Postscaler
MUX
MUX
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
250 kHz
500 kHz
IRCF<2:0>
111
110
101
100
011
010
001
000 31 kHz
31 kHz
LFINTOSC
Internal
Oscillator
Block
Clock
HFINTOSC Control SCS<1:0>
16 MHz
0
1
INTSRC
Primary
PIC18F/LF1XK50
Sleep
Sleep
System
Secondary
T1OSCEN
Enable
Oscillator
T1OSI
T1OSO
PCLKEN
PRI_SD
2
CPU
Divider 0
1
1
0
USBDIV
FOSC<3:0>
Low Speed USB
High Speed USB
PLLEN
SPLLEN
Oscillator
Watchdog
Timer
Oscillator
Fail-Safe
Clock
Two-Speed
Start-up
Clock
00
1x
01
2010 Microchip Technology Inc. Preliminary DS41350E-page 17
PIC18F/LF1XK50
2.3.1 PRIMARY EXTERNAL OSCILLATOR
SHUT-DOWN
The Primary External Oscillator can be enabled or disabled
via software. To enable software control of the
Primary External Oscillator, the PCLKEN bit of the
CONFIG1H Configuration register must be set. With
the PCLKEN bit set, the Primary External Oscillator is
controlled by the PRI_SD bit of the OSCCON2 register.
The Primary External Oscillator will be enabled when
the PRI_SD bit is set, and disabled when the PRI_SD
bit is clear.
2.3.2 LP, XT AND HS OSCILLATOR
MODES
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 2-2). The mode selects a low,
medium or high gain setting of the internal inverteramplifier
to support various resonator types and speed.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is best suited
to drive resonators with a low drive level specification, for
example, tuning fork type crystals.
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.
Figure 2-2 and Figure 2-3 show typical circuits for
quartz crystal and ceramic resonators, respectively.
FIGURE 2-2: QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
Note: The Primary External Oscillator cannot be
shut down when it is selected as the
System Clock. To shut down the oscillator,
the system clock source must be either
the Secondary Oscillator or the Internal
Oscillator.
Note 1: Quartz crystal characteristics vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
C1
C2
Quartz
RS(1)
OSC1/CLKIN
RF(2) Sleep
To Internal
Logic
PIC® MCU
Crystal
OSC2/CLKOUT
PIC18F/LF1XK50
DS41350E-page 18 Preliminary 2010 Microchip Technology Inc.
FIGURE 2-3: CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
2.3.3 EXTERNAL RC
The External Resistor-Capacitor (RC) mode supports
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. In RC mode, the RC circuit connects to OSC1,
allowing OSC2 to be configured as an IO or as
CLKOUT. The CLKOUT function is selected by the
FOSC bits of the CONFIG1H Configuration register.
When OSC2 is configured as CLKOUT, the frequency
at the pin is the frequency of the RC oscillator divided by
4. Figure 2-4 shows the external RC mode connections.
FIGURE 2-4: EXTERNAL RC MODES
The RC oscillator frequency is a function of the supply
voltage, the resistor REXT, the capacitor CEXT and the
operating temperature. Other factors affecting the
oscillator frequency are:
• Input threshold voltage variation
• Component tolerances
• Variation in capacitance due to packaging
2.3.4 EXTERNAL CLOCK
The External Clock (EC) mode allows an externally
generated logic level clock to be used as the system’s
clock source. When operating in this mode, the
external clock source is connected to the OSC1
allowing OSC2 to be configured as an I/O or as
CLKOUT. The CLKOUT function is selected by the
FOSC bits of the CONFIG1H Configuration register.
When OSC2 is configured as CLKOUT, the frequency
at the pin is the frequency of the EC oscillator divided
by 4.
Three different power settings are available for EC
mode. The power settings allow for a reduced IDD of the
device, if the EC clock is known to be in a specific
range. If there is an expected range of frequencies for
the EC clock, select the power mode for the highest
frequency.
EC Low power 0 – 250 kHz
EC Medium power 250 kHz – 4 MHz
EC High power 4 – 48 MHz
2.4 Secondary External Oscillator
The Secondary External Oscillator is designed to drive
an external 32.768 kHz crystal. This oscillator is
enabled or disabled by the T1OSCEN bit of the T1CON
register. See Section 11.0 “Timer1 Module” for more
information.
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
C1
C2 Ceramic RS(1)
OSC1/CLKIN
RF(2) Sleep
To Internal
Logic
PIC® MCU
RP(3)
Resonator
OSC2/CLKOUT
OSC2/CLKOUT(1)
CEXT
REXT
PIC® MCU
OSC1/CLKIN
FOSC/4 or
Internal
Clock
VDD
VSS
Recommended values: 10 k REXT 100 k
CEXT > 20 pF
Note 1: Alternate pin functions are listed in
Section 1.0 “Device Overview”.
2: Output depends upon RC or RCIO clock mode.
I/O(2)
2010 Microchip Technology Inc. Preliminary DS41350E-page 19
PIC18F/LF1XK50
2.5 Internal Oscillator
The internal oscillator module contains two independent
oscillators which are:
• LFINTOSC: Low-Frequency Internal Oscillator
• HFINTOSC: High-Frequency Internal Oscillator
When operating with either oscillator, OSC1 will be an
I/O and OSC2 will be either an I/O or CLKOUT. The
CLKOUT function is selected by the FOSC bits of the
CONFIG1H Configuration register. When OSC2 is
configured as CLKOUT, the frequency at the pin is the
frequency of the Internal Oscillator divided by 4.
2.5.1 LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
a 31 kHz internal clock source. The LFINTOSC
oscillator is the clock source for:
• Power-up Timer
• Watchdog Timer
• Fail-Safe Clock Monitor
The LFINTOSC is enabled when any of the following
conditions are true:
• Power-up Timer is enabled (PWRTEN = 0)
• Watchdog Timer is enabled (WDTEN = 1)
• Watchdog Timer is enabled by software
(WDTEN = 0 and SWDTEN = 1)
• Fail-Safe Clock Monitor is enabled (FCMEM = 1)
• SCS1=1 and IRCF<2:0> = 000 and INTSRC = 0
• FOSC<3:0> selects the internal oscillator as the
primary clock and IRCF<2:0> = 000 and
INTSRC = 0
• IESO = 1 (Two-Speed Start-up) and
IRCF<2:0> = 000 and INTSRC = 0
2.5.2 HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is
a precision oscillator that is factory-calibrated to
operate at 16 MHz. The output of the HFINTOSC
connects to a postscaler and a multiplexer (see
Figure 2-1). One of eight frequencies can be selected
using the IRCF<2:0> bits of the OSCCON register. The
following frequencies are available from the
HFINTOSC:
• 16 MHZ
• 8 MHZ
• 4 MHZ
• 2 MHZ
• 1 MHZ (Default after Reset)
• 500 kHz
• 250 kHz
• 31 kHz
The HFIOFS bit of the OSCCON register indicates
whether the HFINTOSC is stable.
The HFINTOSC is enabled if any of the following
conditions are true:
• SCS1 = 1 and IRCF<2:0> 000
• SCS1 = 1 and IRCF<2:0> = 000 and INTSRC = 1
• FOSC<3:0> selects the internal oscillator as the
primary clock and
- IRCF<2:0> 000 or
- IRCF<2:0> = 000 and INTSRC = 1
• IESO = 1 (Two-Speed Start-up) and
- IRCF<2:0> 000 or
- IRCF<2:0> = 000 and INTSRC = 1
• FCMEM=1 (Fail Safe Clock Monitoring) and
- IRCF<2:0> 000 or
- IRCF<2:0> = 000 and INTSRC = 1
Note 1: Selecting 31 kHz from the HFINTOSC
oscillator requires IRCF<2:0> = 000 and
the INTSRC bit of the OSCTUNE register
to be set. If the INTSRC bit is clear, the
system clock will come from the
LFINTOSC.
2: Additional adjustments to the frequency
of the HFINTOSC can made via the
OSCTUNE registers. See Register 2-3
for more details
PIC18F/LF1XK50
DS41350E-page 20 Preliminary 2010 Microchip Technology Inc.
2.6 Oscillator Control
The Oscillator Control (OSCCON) (Register 2-1) and the
Oscillator Control 2 (OSCCON2) (Register 2-2) registers
control the system clock and frequency selection
options.
REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0 R/W-0 R/W-1 R/W-1 R-q R-0 R/W-0 R/W-0
IDLEN IRCF2 IRCF1 IRCF0 OSTS(1) HFIOFS SCS1 SCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IDLEN: Idle Enable bit
1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction
bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits
111 = 16 MHz
110 = 8 MHz
101 = 4 MHz
100 = 2 MHz
011 = 1 MHz(3)
010 = 500 kHz
001 = 250 kHz
000 = 31 kHz(2)
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Device is running from the clock defined by FOSC<2:0> of the CONFIG1 register
0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC)
bit 2 HFIOFS: HFINTOSC Frequency Stable bit
1 = HFINTOSC frequency is stable
0 = HFINTOSC frequency is not stable
bit 1-0 SCS<1:0>: System Clock Select bits
1x = Internal oscillator block
01 = Secondary (Timer1) oscillator
00 = Primary clock (determined by CONFIG1H[FOSC<3:0>]).
Note 1: Reset state depends on state of the IESO Configuration bit.
2: Source selected by the INTSRC bit of the OSCTUNE register, see text.
3: Default output frequency of HFINTOSC on Reset.
2010 Microchip Technology Inc. Preliminary DS41350E-page 21
PIC18F/LF1XK50
REGISTER 2-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R-x
— — — — — PRI_SD HFIOFL LFIOFS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-3 Unimplemented: Read as ‘0’
bit 2 PRI_SD: Primary Oscillator Drive Circuit shutdown bit
1 = Oscillator drive circuit on
0 = Oscillator drive circuit off (zero power)
bit 1 HFIOFL: HFINTOSC Frequency Locked bit
1 = HFINTOSC is in lock
0 = HFINTOSC has not yet locked
bit 0 LFIOFS: LFINTOSC Frequency Stable bit
1 = LFINTOSC is stable
0 = LFINTOSC is not stable
PIC18F/LF1XK50
DS41350E-page 22 Preliminary 2010 Microchip Technology Inc.
2.6.1 OSCTUNE REGISTER
The HFINTOSC is factory calibrated, but can be
adjusted in software by writing to the TUN<5:0> bits of
the OSCTUNE register (Register 2-3).
The default value of the TUN<5:0> is ‘000000’. The
value is a 6-bit two’s complement number.
When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
frequency. Code execution continues during this shift,
while giving no indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
The operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor
(FSCM) and peripherals, are not affected by the
change in frequency.
The OSCTUNE register also implements the INTSRC
and SPLLEN bits, which control certain features of the
internal oscillator block.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31 kHz
frequency option is selected. This is covered in greater
detail in Section 2.5.1 “LFINTOSC”.
The SPLLEN bit controls the operation of the frequency
multiplier. For more details about the function of the
SPLLEN bit see Section 2.9 “4x Phase Lock Loop
Frequency Multiplier”
REGISTER 2-3: OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTSRC SPLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 16 MHz HFINTOSC source (divide-by-512 enabled)
0 = 31 kHz device clock derived directly from LFINTOSC internal oscillator
bit 6 SPLLEN: Software Controlled Frequency Multiplier PLL bit
1 = PLL enabled (for HFINTOSC 8 MHz only)
0 = PLL disabled
bit 5-0 TUN<5:0>: Frequency Tuning bits
011111 = Maximum frequency
011110 =
• • •
000001 =
000000 = Oscillator module is running at the factory calibrated frequency.
111111 =
• • •
100000 = Minimum frequency
2010 Microchip Technology Inc. Preliminary DS41350E-page 23
PIC18F/LF1XK50
2.7 Oscillator Start-up Timer
The Primary External Oscillator, when configured for
LP, XT or HS modes, incorporates an Oscillator Start-up
Timer (OST). The OST ensures that the oscillator starts
and provides a stable clock to the oscillator module.
The OST times out when 1024 oscillations on OSC1
have occurred. During the OST period, with the system
clock set to the Primary External Oscillator, the program
counter does not increment suspending program
execution. The OST period will occur following:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Wake-up from Sleep
• Oscillator being enabled
• Expiration of Power-up Timer (PWRT)
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Start-up
mode can be selected. See Section 2.12 “Two-Speed
Start-up Mode” for more information.
2.8 Clock Switching
The device contains circuitry to prevent clock “glitches”
due to a change of the system clock source. To
accomplish this, a short pause in the system clock
occurs during the clock switch. If the new clock source
is not stable (e.g., OST is active), the device will
continue to execute from the old clock source until the
new clock source becomes stable. The timing of a
clock switch is as follows:
1. SCS<1:0> bits of the OSCCON register are
modified.
2. The system clock will continue to operate from
the old clock until the new clock is ready.
3. Clock switch circuitry waits for two consecutive
rising edges of the old clock after the new clock
is ready.
4. The system clock is held low, starting at the next
falling edge of the old clock.
5. Clock switch circuitry waits for an additional two
rising edges of the new clock.
6. On the next falling edge of the new clock, the
low hold on the system clock is release and the
new clock is switched in as the system clock.
7. Clock switch is complete.
Refer to Figure 2-5 for more details.
FIGURE 2-5: CLOCK SWITCH TIMING
Old Clock
New Clock
IRCF <2:0>
System Clock
Start-up Time(1) Clock Sync Running
High Speed Low Speed
Select Old Select New
New Clk Ready
Low Speed High Speed
Old Clock
New Clock
IRCF <2:0>
System Clock
Start-up Time(1) Clock Sync Running
Select Old Select New
New Clk Ready
Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode.
PIC18F/LF1XK50
DS41350E-page 24 Preliminary 2010 Microchip Technology Inc.
TABLE 2-2: EXAMPLES OF DELAYS DUE TO CLOCK SWITCHING
2.9 4x Phase Lock Loop Frequency
Multiplier
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower-frequency
external oscillator or to operate at 32 MHz with the
HFINTOSC. The PLL is designed for an input
frequency from 4 MHz to 12 MHz. The PLL multiplies
its input frequency by a factor of four when the PLL is
enabled. This may be useful for customers who are
concerned with EMI, due to high-frequency crystals.
Two bits control the PLL: the PLLEN bit of the
CONFIG1H Configuration register and the SPLLEN bit
of the OSCTUNE register. The PLL is enabled when
the PLLEN bit is set and it is under software control
when the PLLEN bit is cleared.
TABLE 2-3: PLL CONFIGURATION
2.9.1 32 MHZ INTERNAL OSCILLATOR
FREQUENCY SELECTION
The Internal Oscillator Block can be used with the 4X
PLL associated with the External Oscillator Block to
produce a 32 MHz internal system clock source. The
following settings are required to use the 32 MHz internal
clock source:
• The FOSC bits in CONFIG1H must be set to use
the INTOSC source as the device system clock
(FOSC<3:0> = 1000 or 1001).
• The SCS bits in the OSCCON register must be
cleared to use the clock determined by
FOSC<3:0> in CONFIG1H (SCS<1:0> = 00).
• The IRCF bits in the OSCCON register must be
set to the 8 MHz HFINTOSC set to use
(IRCF<2:0> = 110).
• The SPLLEN bit in the OSCTUNE register must
be set to enable the 4xPLL, or the PLLEN bit of
CONFIG1H must be progr mmed to a ‘1’.
The 4xPLL is not available for use with the internal
oscillator when the SCS bits of the OSCCON register
are set to ‘1x’. The SCS bits must be set to ‘00’ to use
the 4xPLL with the internal oscillator.
2.10 CPU Clock Divider
The CPU Clock Divider allows the system clock to run
at a slower speed than the Low/Full Speed USB
module clock while sharing the same clock source.
Only the oscillator defined by the settings of the FOSC
bits of the CONFIG1H Configuration register may be
used with the CPU Clock Divider. The CPU Clock
Divider is controlled by the CPUDIV bits of the
CONFIG1L Configuration register. Setting the CPUDIV
bits will set the system clock to:
• Equal the clock speed of the USB module
• Half the clock speed of the USB module
• One third the clock speed of the USB module
• One fourth the clock speed of the USB module
For more information on the CPU Clock Divider, see
Figure 2-1 and Register 24-1 CONFIG1L.
Switch From Switch To Oscillator Delay
Sleep/POR LFINTOSC
HFINTOSC
Oscillator Warm-up Delay (TWARM)
Sleep/POR LP, XT, HS 1024 clock cycles
Sleep/POR EC, RC 8 clock cycles
PLLEN SPLLEN PLL Status
1 x PLL enabled
0 1 PLL enabled
0 0 PLL disabled
Note: When using the PLLEN bit of CONFIG1H,
the 4xPLL cannot be disabled by software
and the 8 MHz HFINTOSC option will no
longer be available.
2010 Microchip Technology Inc. Preliminary DS41350E-page 25
PIC18F/LF1XK50
2.11 USB Operation
The USB module is designed to operate in two different
modes:
• Low Speed
• Full Speed
Because of timing requirements imposed by the USB
specifications, the Primary External Oscillator is
required for the USB module. The FOSC bits of the
CONFIG1H Configuration register must be set to either
External Clock (EC) High-power or HS mode with a
clock frequency of 6, 12 or 48 MHz.
2.11.1 LOW SPEED OPERATION
For Low Speed USB operation, a 6 MHz clock is
required for the USB module. To generate the 6 MHz
clock, only 2 Oscillator modes are allowed:
• EC High-power mode
• HS mode
Table 2-4 shows the recommended Clock mode for
low-speed operation.
2.11.2 FULL-SPEED OPERATION
For full-speed USB operation, a 48 MHz clock is
required for the USB module. To generate the 48 MHz
clock, only 2 Oscillator modes are allowed:
• EC High-power mode
• HS mode
Table 2-5 shows the recommended Clock mode for fullspeed
operation.
Note: Users must run USB low speed operation
using a CPU clock frequency of 24 MHz or
slower (64 MHz is optimal). If anything
higher than 24 MHz is used, a firmware
delay of at least 14 instruction cycles is
required.
PIC18F/LF1XK50
DS41350E-page 26 Preliminary 2010 Microchip Technology Inc.
TABLE 2-4: LOW SPEED USB CLOCK SETTINGS
TABLE 2-5: FULL-SPEED USB CLOCK SETTINGS
Clock Mode Clock
Frequency USBDIV 4x PLL
Enabled CPUDIV<1:0> System Clock
Frequency (MHz)
EC High/HS
12 MHz 1
Yes
00 48
01 24
10 16
11 12
No
00 12
01 6
10 4
11 3
6 MHz 0
Yes
00 24
01 12
10 8
11 6
No
00 6
01 3
10 2
11 1.5
Note: The system clock frequency in Table 2-4
only applies if the OSCCON register bits
SCS<1:0> = 00. By changing these bits,
the system clock can operate down to
31 kHz.
Clock Mode Clock Frequency 4x PLL Enabled CPUDIV<1:0> System Clock Frequency
(MHz)
EC High 48 MHz No
00 48
01 24
10 16
11 12
EC High/HS 12 MHz Yes
00 48
01 24
10 16
11 12
Note: The system clock frequency in the above
table only applies if the OSCCON register
bits SCS<1:0> = 00. By changing these
bits, the system clock can operate down to
31 kHz.
2010 Microchip Technology Inc. Preliminary DS41350E-page 27
PIC18F/LF1XK50
2.12 Two-Speed Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
Oscillator Start-up Timer (OST) and code execution. In
applications that make heavy use of the Sleep mode,
Two-Speed Start-up will remove the OST period, which
can reduce the overall power consumption of the
device.
Two-Speed Start-up mode is enabled by setting the
IESO bit of the CONFIG1H Configuration register. With
Two-Speed Start-up enabled, the device will execute
instructions using the internal oscillator during the
Primary External Oscillator OST period.
When the system clock is set to the Primary External
Oscillator and the oscillator is configured for LP, XT or
HS modes, the device will not execute code during the
OST period. The OST will suspend program execution
until 1024 oscillations are counted. Two-Speed Start-up
mode minimizes the delay in code execution by
operating from the internal oscillator while the OST is
active. The system clock will switch back to the Primary
External Oscillator after the OST period has expired.
Two-speed Start-up will become active after:
• Power-on Reset (POR)
• Power-up Timer (PWRT), if enabled
• Wake-up from Sleep
The OSTS bit of the OSCCON register reports which
oscillator the device is currently using for operation.
The device is running from the oscillator defined by the
FOSC bits of the CONFIG1H Configuration register
when the OSTS bit is set. The device is running from
the internal oscillator when the OSTS bit is clear.
2.13 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
CONFIG1H Configuration register. The FSCM is
applicable to all external oscillator modes (LP, XT, HS,
EC and RC).
FIGURE 2-6: FSCM BLOCK DIAGRAM
2.13.1 FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 2-6. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire halfcycle
of the sample clock elapses before the primary
clock goes low.
2.13.2 FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSCFIF of the PIR2 register. The OSCFIF flag will
generate an interrupt if the OSCFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation. An automatic
transition back to the failed clock source will not occur.
The internal clock source chosen by the FSCM is
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
External
LFINTOSC ÷ 64
S
R
Q
31 kHz
(~32 s)
488 Hz
(~2 ms)
Clock Monitor
Latch
Clock
Failure
Detected
Oscillator
Clock
Q
Sample Clock
PIC18F/LF1XK50
DS41350E-page 28 Preliminary 2010 Microchip Technology Inc.
2.13.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared by either one of the
following:
• Any Reset
• By toggling the SCS1 bit of the OSCCON register
Both of these conditions restart the OST. While the
OST is running, the device continues to operate from
the INTOSC selected in OSCCON. When the OST
times out, the Fail-Safe condition is cleared and the
device automatically switches over to the external clock
source. The Fail-Safe condition need not be cleared
before the OSCFIF flag is cleared.
2.13.4 RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.
FIGURE 2-7: FSCM TIMING DIAGRAM
TABLE 2-6: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Note: Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit of the OSCCON register to verify
the oscillator start-up and that the system
clock switchover has successfully
completed.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
page
CONFIG1H IESO FCMEN PCLKEN PLLEN FOSC3 FOSC2 FOSC1 FOSC0 296
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS HFIOFS SCS1 SCS0 286
OSCTUNE INTSRC SPLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 288
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE — 288
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF — 288
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 105
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
OSCFIF
System
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
(Q)
Test Test Test
Clock Monitor Output
2010 Microchip Technology Inc. Preliminary DS41350E-page 29
PIC18F1XK50/PIC18LF1XK50
3.0 MEMORY ORGANIZATION
There are three types of memory in PIC18 Enhanced
microcontroller devices:
• Program Memory
• Data RAM
• Data EEPROM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for concurrent
access of the two memory spaces. The data
EEPROM, for practical purposes, can be regarded as
a peripheral device, since it is addressed and accessed
through a set of control registers.
Additional detailed information on the operation of the
Flash program memory is provided in Section 4.0
“Flash Program Memory”. Data EEPROM is
discussed separately in Section 5.0 “Data EEPROM
Memory”.
3.1 Program Memory Organization
PIC18 microcontrollers implement a 21-bit program
counter, which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOP instruction).
This family of devices contain the following:
• PIC18F13K50: 8 Kbytes of Flash Memory, up to
4,096 single-word instructions
• PIC18F14K50: 16 Kbytes of Flash Memory, up to
8,192 single-word instructions
PIC18 devices have two interrupt vectors and one
Reset vector. The Reset vector address is at 0000h
and the interrupt vector addresses are at 0008h and
0018h.
The program memory map for PIC18F/LF1XK50
devices is shown in Figure 3-1. Memory block details
are shown in Figure 24-2.
FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F/LF1XK50 DEVICES
PC<20:0>
Stack Level 1
Stack Level 31
Reset Vector
Low Priority Interrupt Vector
CALL,RCALL,RETURN
RETFIE,RETLW
21
0000h
0018h
High Priority Interrupt Vector 0008h
User Memory Space
1FFFFFh
4000h
3FFFh
200000h
On-Chip
Program Memory
Read ‘0’
1FFFh
2000h
On-Chip
Program Memory
Read ‘0’
PIC18F14K50
PIC18F13K50
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 30 Preliminary 2010 Microchip Technology Inc.
3.1.1 PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 3.1.4.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit (LSb) of PCL is
fixed to a value of ‘0’. The PC increments by 2 to
address sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
3.1.2 RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL
instruction is executed or an interrupt is Acknowledged.
The PC value is pulled off the stack on a RETURN,
RETLW or a RETFIE instruction. PCLATU and PCLATH
are not affected by any of the RETURN or CALL
instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the Top-of-
Stack (TOS) Special File Registers. Data can also be
pushed to, or popped from the stack, using these
registers.
A CALL type instruction causes a push onto the stack;
the Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack; the contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full or has overflowed or has underflowed.
3.1.2.1 Top-of-Stack Access
Only the top of the return address stack (TOS) is readable
and writable. A set of three registers, TOSU:TOSH:TOSL,
hold the contents of the stack location pointed to by the
STKPTR register (Figure 3-2). This allows users to
implement a software stack if necessary. After a CALL,
RCALL or interrupt, the software can read the pushed
value by reading the TOSU:TOSH:TOSL registers. These
values can be placed on a user defined software stack. At
return time, the software can return these values to
TOSU:TOSH:TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 3-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
00011
001A34h
11111
11110
11101
00010
00001
00000
00010
Return Address Stack <20:0>
Top-of-Stack
000D58h
TOSU TOSH TOSL
00h 1Ah 34h
STKPTR<4:0>
Top-of-Stack Registers Stack Pointer
2010 Microchip Technology Inc. Preliminary DS41350E-page 31
PIC18F1XK50/PIC18LF1XK50
3.1.2.2 Return Stack Pointer (STKPTR)
The STKPTR register (Register 3-1) contains the Stack
Pointer value, the STKFUL (stack full) bit and the
STKUNF (stack underflow) bits. The value of the Stack
Pointer can be 0 through 31. The Stack Pointer increments
before values are pushed onto the stack and
decrements after values are popped off the stack. On
Reset, the Stack Pointer value will be zero. The user
may read and write the Stack Pointer value. This feature
can be used by a Real-Time Operating System
(RTOS) for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Overflow
Reset Enable) Configuration bit. (Refer to
Section 24.1 “Configuration Bits” for a description of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
3.1.2.3 PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack without disturbing normal program execution
is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by decrementing
the Stack Pointer. The previous value pushed
onto the stack then becomes the TOS value.
Note: Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
REGISTER 3-1: STKPTR: STACK POINTER REGISTER
R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 STKFUL: Stack Full Flag bit(1)
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6 STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5 Unimplemented: Read as ‘0’
bit 4-0 SP<4:0>: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 32 Preliminary 2010 Microchip Technology Inc.
3.1.2.4 Stack Full and Underflow Resets
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a full
or underflow will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
3.1.3 FAST REGISTER STACK
A fast register stack is provided for the Status, WREG
and BSR registers, to provide a “fast return” option for
interrupts. The stack for each register is only one level
deep and is neither readable nor writable. It is loaded
with the current value of the corresponding register
when the processor vectors for an interrupt. All interrupt
sources will push values into the stack registers.
The values in the registers are then loaded back into
their associated registers if the RETFIE, FAST
instruction is used to return from the interrupt.
If both low and high priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low priority interrupts. If a high priority interrupt occurs
while servicing a low priority interrupt, the stack register
values stored by the low priority interrupt will be
overwritten. In these cases, users must save the key
registers by software during a low priority interrupt.
If interrupt priority is not used, all interrupts may use the
fast register stack for returns from interrupt. If no
interrupts are used, the fast register stack can be used
to restore the Status, WREG and BSR registers at the
end of a subroutine call. To use the fast register stack
for a subroutine call, a CALL label, FAST instruction
must be executed to save the Status, WREG and BSR
registers to the fast register stack. A RETURN, FAST
instruction is then executed to restore these registers
from the fast register stack.
Example 3-1 shows a source code example that uses
the fast register stack during a subroutine call and
return.
EXAMPLE 3-1: FAST REGISTER STACK
CODE EXAMPLE
3.1.4 LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
3.1.4.1 Computed GOTO
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 3-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 3-2: COMPUTED GOTO USING
AN OFFSET VALUE
3.1.4.2 Table Reads and Table Writes
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per program
word by using table reads and writes. The Table
Pointer (TBLPTR) register specifies the byte address
and the Table Latch (TABLAT) register contains the
data that is read from or written to program memory.
Data is transferred to or from program memory one
byte at a time.
Table read and table write operations are discussed
further in Section 4.1 “Table Reads and Table
Writes”.
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
RETURN, FAST ;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
MOVF OFFSET, W
CALL TABLE
ORG nn00h
TABLE ADDWF PCL
RETLW nnh
RETLW nnh
RETLW nnh
.
.
.
2010 Microchip Technology Inc. Preliminary DS41350E-page 33
PIC18F1XK50/PIC18LF1XK50
3.2 PIC18 Instruction Cycle
3.2.1 CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the
instruction register during Q4. The instruction is
decoded and executed during the following Q1 through
Q4. The clocks and instruction execution flow are
shown in Figure 3-3.
3.2.2 INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute take
another instruction cycle. However, due to the
pipelining, each instruction effectively executes in one
cycle. If an instruction causes the program counter to
change (e.g., GOTO), then two cycles are required to
complete the instruction (Example 3-3).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-3: CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-3: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC PC + 2 PC + 4
Fetch INST (PC)
Execute INST (PC – 2)
Fetch INST (PC + 2)
Execute INST (PC)
Fetch INST (PC + 4)
Execute INST (PC + 2)
Internal
Phase
Clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
TCY0 TCY1 TCY2 TCY3 TCY4 TCY5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 34 Preliminary 2010 Microchip Technology Inc.
3.2.3 INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes.
Instructions are stored as either two bytes or four bytes
in program memory. The Least Significant Byte (LSB)
of an instruction word is always stored in a program
memory location with an even address (LSb = 0). To
maintain alignment with instruction boundaries, the PC
increments in steps of 2 and the LSb will always read
‘0’ (see Section 3.1.1 “Program Counter”).
Figure 3-4 shows an example of how instruction words
are stored in the program memory.
The CALL and GOTO instructions have the absolute
program memory address embedded into the
instruction. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 3-4 shows how the
instruction GOTO 0006h is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 25.0 “Instruction Set Summary”
provides further details of the instruction set.
FIGURE 3-4: INSTRUCTIONS IN PROGRAM MEMORY
3.2.4 TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instruction always has
‘1111’ as its four Most Significant bits (MSb); the other
12 bits are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed
and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 3-4 shows how this works.
EXAMPLE 3-4: TWO-WORD INSTRUCTIONS
Word Address
LSB = 1 LSB = 0
Program Memory
Byte Locations
000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 0006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
Note: See Section 3.6 “PIC18 Instruction
Execution and the Extended Instruction
Set” for information on two-word
instructions in the extended instruction set.
CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word
1111 0100 0101 0110 ; 2nd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code
2010 Microchip Technology Inc. Preliminary DS41350E-page 35
PIC18F1XK50/PIC18LF1XK50
3.3 Data Memory Organization
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. Figure 3-5 and
Figure 3-6 show the data memory organization for the
PIC18F/LF1XK50 devices.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256-byte
memory space that provides fast access to SFRs and
the lower portion of GPR Bank 0 without using the Bank
Select Register (BSR). Section 3.3.3 “Access Bank”
provides a detailed description of the Access RAM.
3.3.1 USB RAM
Part of the data memory is actually mapped to a special
dual access RAM. When the USB module is disabled,
the GPRs in these banks are used like any other GPR
in the data memory space.
When the USB module is enabled, the memory in these
banks is allocated as buffer RAM for USB operation.
This area is shared between the microcontroller core
and the USB Serial Interface Engine (SIE) and is used
to transfer data directly between the two.
It is theoretically possible to use the areas of USB RAM
that are not allocated as USB buffers for normal
scratchpad memory or other variable storage. In
practice, the dynamic nature of buffer allocation makes
this risky at best. Additional information on USB RAM
and buffer operation is provided in Section 22.0
“Universal Serial Bus (USB)”
3.3.2 BANK SELECT REGISTER (BSR)
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accomplished
with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR<3:0>). The upper four bits
are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLB instruction.
The value of the BSR indicates the bank in data
memory; the 8 bits in the instruction show the location
in the bank and can be thought of as an offset from the
bank’s lower boundary. The relationship between the
BSRs value and the bank division in data memory is
shown in Figure 3-5 and Figure 3-6.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR
is 0Fh will end up resetting the program counter.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory maps in
Figure 3-5 and Figure 3-6 indicate which banks are
implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
Note: The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 3.5 “Data Memory and the
Extended Instruction Set” for more
information.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 36 Preliminary 2010 Microchip Technology Inc.
FIGURE 3-5: DATA MEMORY MAP FOR PIC18F13K50/PIC18LF13K50 DEVICES
Bank 0
Bank 1
Bank 14
Bank 15
BSR<3:0> Data Memory Map
= 0000
= 0001
= 1111
060h
05Fh
F60h
FFFh
00h
5Fh
60h
FFh
Access Bank
When ‘a’ = 0:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are
general purpose RAM
(from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
When ‘a’ = 1:
The BSR specifies the Bank
used by the instruction.
F5Fh
F00h
EFFh
1FFh
100h
0FFh
Access RAM 000h
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Access RAM High
Access RAM Low
Bank 2
= 0110
= 0010
(SFRs)
2FFh
200h
3FFh
300h
4FFh
400h
5FFh
500h
6FFh
600h
7FFh
700h
8FFh
800h
9FFh
900h
AFFh
A00h
BFFh
B00h
CFFh
C00h
DFFh
D00h
E00h
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
= 0011
= 0100
= 0101
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
Unused
Read 00h
Unused
Unused
Read 00h
F53h
SFR(1)
Note 1: SFRs occupying F53h to F5Fh address space are not in the virtual bank
(DPRAM)
2010 Microchip Technology Inc. Preliminary DS41350E-page 37
PIC18F1XK50/PIC18LF1XK50
FIGURE 3-6: DATA MEMORY MAP FOR PIC18F14K50/PIC18LF14K50 DEVICES
Bank 0
Bank 1
Bank 14
Bank 15
BSR<3:0> Data Memory Map
= 0000
= 0001
= 1111
060h
05Fh
00h
5Fh
60h
FFh
Access Bank
When ‘a’ = 0:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are
general purpose RAM
(from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
When ‘a’ = 1:
The BSR specifies the Bank
used by the instruction.
F00h
EFFh
1FFh
100h
0FFh
Access RAM 000h
FFh
00h
FFh
00h
GPR
GPR
Access RAM High
Access RAM Low
Bank 2
= 0110
= 0010
(SFRs)
2FFh
200h
3FFh
300h
4FFh
400h
5FFh
500h
6FFh
600h
7FFh
700h
8FFh
800h
9FFh
900h
AFFh
A00h
BFFh
B00h
CFFh
C00h
DFFh
D00h
E00h
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
GPR
FFh
00h
= 0011
= 0100
= 0101
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
Unused
Read 00h
Note 1: SFRs occupying F53h to F5Fh address space are not in the virtual bank
F60h
FFFh
F5Fh
FFh
00h
SFR
Unused
F53h
SFR(1)
(DPRAM)
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 38 Preliminary 2010 Microchip Technology Inc.
FIGURE 3-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data Memory
Bank Select(2)
7 0
From Opcode(2)
0 0 0 0
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
Bank 3
through
Bank 13
0 0 1 1 1 1 1 1 1 1 1 1
7 0
BSR(1)
2010 Microchip Technology Inc. Preliminary DS41350E-page 39
PIC18F1XK50/PIC18LF1XK50
3.3.3 ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation, but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of memory
(00h-5Fh) in Bank 0 and the last 160 bytes of memory
(60h-FFh) in Block 15. The lower half is known as
the “Access RAM” and is composed of GPRs. This
upper half is also where the device’s SFRs are
mapped. These two areas are mapped contiguously in
the Access Bank and can be addressed in a linear
fashion by an 8-bit address (Figure 3-5 and Figure 3-
6).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle, without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 3.5.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
3.3.4 GENERAL PURPOSE REGISTER
FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM, which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom of
the SFR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
3.3.5 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
the top portion of Bank 15 (F60h to FFFh). A list of
these registers is given in Table 3-1 and Table 3-2.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of a
peripheral feature are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 40 Preliminary 2010 Microchip Technology Inc.
TABLE 3-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F/LF1XK50 DEVICES
Address Name Address Name Address Name Address Name Address Name
FFFh TOSU FD7h TMR0H FAFh SPBRG F87h —(2) F5Fh UEIR
FFEh TOSH FD6h TMR0L FAEh RCREG F86h —(2) F5Eh UFRMH
FFDh TOSL FD5h T0CON FADh TXREG F85h —(2) F5Dh UFRML
FFCh STKPTR FD4h —(2) FACh TXSTA F84h —(2) F5Ch UADDR
FFBh PCLATU FD3h OSCCON FABh RCSTA F83h —(2) F5Bh UEIE
FFAh PCLATH FD2h OSCCON2 FAAh — F82h PORTC F5Ah UEP7
FF9h PCL FD1h WDTCON FA9h EEADR F81h PORTB F59h UEP6
FF8h TBLPTRU FD0h RCON FA8h EEDATA F80h PORTA F58h UEP5
FF7h TBLPTRH FCFh TMR1H FA7h EECON2(1) F7Fh ANSELH F57h UEP4
FF6h TBLPTRL FCEh TMR1L FA6h EECON1 F7Eh ANSEL F56h UEP3
FF5h TABLAT FCDh T1CON FA5h —(2) F7Dh —(2) F55h UEP2
FF4h PRODH FCCh TMR2 FA4h —(2) F7Ch —(2) F54h UEP1
FF3h PRODL FCBh PR2 FA3h —(2) F7Bh —(2) F53h UEP0
FF2h INTCON FCAh T2CON FA2h IPR2 F7Ah IOCB
FF1h INTCON2 FC9h SSPBUF FA1h PIR2 F79h IOCA
FF0h INTCON3 FC8h SSPADD FA0h PIE2 F78h WPUB
FEFh INDF0(1) FC7h SSPSTAT F9Fh IPR1 F77h WPUA
FEEh POSTINC0(1) FC6h SSPCON1 F9Eh PIR1 F76h SLRCON
FEDh POSTDEC0(1) FC5h SSPCON2 F9Dh PIE1 F75h —(2)
FECh PREINC0(1) FC4h ADRESH F9Ch —(2) F74h —(2)
FEBh PLUSW0(1) FC3h ADRESL F9Bh OSCTUNE F73h —(2)
FEAh FSR0H FC2h ADCON0 F9Ah —(2) F72h —(2)
FE9h FSR0L FC1h ADCON1 F99h —(2) F71h —(2)
FE8h WREG FC0h ADCON2 F98h —(2) F70h —(2)
FE7h INDF1(1) FBFh CCPR1H F97h —(2) F6Fh SSPMASK
FE6h POSTINC1(1) FBEh CCPR1L F96h —(2) F6Eh —(2)
FE5h POSTDEC1(1) FBDh CCP1CON F95h —(2) F6Dh CM1CON0
FE4h PREINC1(1) FBCh REFCON2 F94h TRISC F6Ch CM2CON1
FE3h PLUSW1(1) FBBh REFCON1 F93h TRISB F6Bh CM2CON0
FE2h FSR1H FBAh REFCON0 F92h TRISA F6Ah —(2)
FE1h FSR1L FB9h PSTRCON F91h —(2) F69h SRCON1
FE0h BSR FB8h BAUDCON F90h —(2) F68h SRCON0
FDFh INDF2(1) FB7h PWM1CON F8Fh —(2) F67h —(2)
FDEh POSTINC2(1) FB6h ECCP1AS F8Eh —(2) F66h —(2)
FDDh POSTDEC2(1) FB5h —(2) F8Dh —(2) F65h —(2)
FDCh PREINC2(1) FB4h —(2) F8Ch —(2) F64h UCON
FDBh PLUSW2(1) FB3h TMR3H F8Bh LATC F63h USTAT
FDAh FSR2H FB2h TMR3L F8Ah LATB F62h UIR
FD9h FSR2L FB1h T3CON F89h LATA F61h UCFG
FD8h STATUS FB0h SPBRGH F88h —(2) F60h UIE
Note 1: This is not a physical register.
2: Unimplemented registers are read as ‘0’.
2010 Microchip Technology Inc. Preliminary DS41350E-page 41
PIC18F1XK50/PIC18LF1XK50
TABLE 3-2: REGISTER FILE SUMMARY (PIC18F/LF1XK50)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on
page:
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 285, 30
TOSH Top-of-Stack, High Byte (TOS<15:8>) 0000 0000 285, 30
TOSL Top-of-Stack, Low Byte (TOS<7:0>) 0000 0000 285, 30
STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 285, 31
PCLATU — — — Holding Register for PC<20:16> ---0 0000 285, 30
PCLATH Holding Register for PC<15:8> 0000 0000 285, 30
PCL PC, Low Byte (PC<7:0>) 0000 0000 285, 30
TBLPTRU — — — Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) ---0 0000 285, 54
TBLPTRH Program Memory Table Pointer, High Byte (TBLPTR<15:8>) 0000 0000 285, 54
TBLPTRL Program Memory Table Pointer, Low Byte (TBLPTR<7:0>) 0000 0000 285, 54
TABLAT Program Memory Table Latch 0000 0000 285, 54
PRODH Product Register, High Byte xxxx xxxx 285, 65
PRODL Product Register, Low Byte xxxx xxxx 285, 65
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 0000 000x 285, 70
INTCON2 RABPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP 1111 -1-1 285, 71
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 285, 72
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 285, 47
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 285, 47
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 285, 47
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 285, 47
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value
of FSR0 offset by W
N/A 285, 47
FSR0H — — — — Indirect Data Memory Address Pointer 0, High Byte ---- 0000 285, 47
FSR0L Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxx 285, 47
WREG Working Register xxxx xxxx 285
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 285, 47
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 285, 47
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 285, 47
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 285, 47
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value
of FSR1 offset by W
N/A 285, 47
FSR1H — — — — Indirect Data Memory Address Pointer 1, High Byte ---- 0000 286, 47
FSR1L Indirect Data Memory Address Pointer 1, Low Byte xxxx xxxx 286, 47
BSR — — — — Bank Select Register ---- 0000 286, 35
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 286, 47
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 286, 47
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 286, 47
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 286, 47
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value
of FSR2 offset by W
N/A 286, 47
FSR2H — — — — Indirect Data Memory Address Pointer 2, High Byte ---- 0000 286, 47
FSR2L Indirect Data Memory Address Pointer 2, Low Byte xxxx xxxx 286, 47
STATUS — — — N OV Z DC C ---x xxxx 286, 45
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 23.4 “Brown-out Reset (BOR)”.
2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.
3: Bits RA0 and RA1 are available only when USB is disabled.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 42 Preliminary 2010 Microchip Technology Inc.
TMR0H Timer0 Register, High Byte 0000 0000 286, 103
TMR0L Timer0 Register, Low Byte xxxx xxxx 286, 103
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 286, 101
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOSF SCS1 SCS0 0011 qq00 286, 20
OSCCON2 — — — — — PRI_SD HFIOFL LFIOFS ---- -10x 286, 21
WDTCON — — — — — — — SWDTEN --- ---0 286, 303
RCON IPEN SBOREN(1) — RI TO PD POR BOR 0q-1 11q0 277,
284, 79
TMR1H Timer1 Register, High Byte xxxx xxxx 286, 110
TMR1L Timer1 Register, Low Bytes xxxx xxxx 286, 110
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 286, 105
TMR2 Timer2 Register 0000 0000 286, 112
PR2 Timer2 Period Register 1111 1111 286, 112
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 286, 111
SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 286,
143, 144
SSPADD SSP Address Register in I2C™ Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 286, 144
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 286,
137, 146
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 286,
137, 146
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 286, 147
ADRESH A/D Result Register, High Byte xxxx xxxx 287, 221
ADRESL A/D Result Register, Low Byte xxxx xxxx 287, 221
ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 287, 215
ADCON1 — — — — PVCFG1 PVCFG0 NVCFG1 NVCFG0 ---- 0000 287, 216
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 287, 217
CCPR1H Capture/Compare/PWM Register 1, High Byte xxxx xxxx 287, 138
CCPR1L Capture/Compare/PWM Register 1, Low Byte xxxx xxxx 287, 138
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 287, 117
REFCON2 — — — DAC1R4 DAC1R3 DAC1R2 DAC1R1 DAC1R0 ---0 0000 287, 248
REFCON1 D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 — D1NSS 000- 00-0 287, 248
REFCON0 FVR1EN FVR1ST FVR1S1 FVR1S0 — — — — 0001 00-- 287, 247
PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 287, 134
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 0100 0-00 287, 192
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 287, 133
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 287, 129
TMR3H Timer3 Register, High Byte xxxx xxxx 287, 115
TMR3L Timer3 Register, Low Byte xxxx xxxx 287, 115
T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 287, 113
TABLE 3-2: REGISTER FILE SUMMARY (PIC18F/LF1XK50) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on
page:
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 23.4 “Brown-out Reset (BOR)”.
2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.
3: Bits RA0 and RA1 are available only when USB is disabled.
2010 Microchip Technology Inc. Preliminary DS41350E-page 43
PIC18F1XK50/PIC18LF1XK50
SPBRGH EUSART Baud Rate Generator Register, High Byte 0000 0000 287, 181
SPBRG EUSART Baud Rate Generator Register, Low Byte 0000 0000 287, 181
RCREG EUSART Receive Register 0000 0000 287, 182
TXREG EUSART Transmit Register 0000 0000 287, 181
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 287, 190
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 287, 191
EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 287, 52,
61
EEDATA EEPROM Data Register 0000 0000 287, 52,
61
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 287, 52,
61
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 287, 53,
61
IPR2 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP – 1111 111- 288, 78
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF – 0000 000- 288, 74
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE – 0000 000- 288, 76
IPR1 – ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP -111 1111 288, 77
PIR1 – ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 288, 73
PIE1 – ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 288, 75
OSCTUNE INTSRC SPLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000 22, 288
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 288, 94
TRISB TRISB7 TRISB6 TRISB5 TRISB4 – – – – 1111 ---- 288, 89
TRISA – – TRISA5 TRISA4 – – – – --11 ---- 288, 83
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 288, 94
LATB LATB7 LATB6 LATB5 LATB4 – – – – xxxx ---- 288, 89
LATA – – LATA5 LATA4 – – – – --xx ---- 288, 83
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 288, 94
PORTB RB7 RB6 RB5 RB4 – – – – xxxx ---- 288, 89
PORTA – – RA5 RA4 RA3(2) – RA1(3) RA0(3) --xx x-xx 288, 83
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 288, 99
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 — — — 1111 1--- 288, 98
IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 288, 89
IOCA — — IOCA5 IOCA4 IOCA3 — IOCA1 IOCA0 --00 0-00 288, 83
WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 288, 89
WPUA — — WPUA5 WPUA4 WPUA3 — — — --11 1--- 285, 89
SLRCON — — — — — SLRC SLRB SLRA ---- -111 288, 100
SSPMSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 288, 154
CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 1000 288, 229
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 0000 0000 288, 230
CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 1000 288, 230
SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 288, 243
SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 288, 242
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — -0x0 000- 288, 252
TABLE 3-2: REGISTER FILE SUMMARY (PIC18F/LF1XK50) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on
page:
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 23.4 “Brown-out Reset (BOR)”.
2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.
3: Bits RA0 and RA1 are available only when USB is disabled.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 44 Preliminary 2010 Microchip Technology Inc.
USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — -xxx xxx- 289, 256
UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 289, 266
UCFG UTEYE — — UPUEN — FSEN PPB1 PPB0 0--0 -000 289, 254
UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 289, 268
UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000 289, 269
UFRMH — — — — — FRM10 FRM9 FRM8 ---- -xxx 289, 252
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx 289, 252
UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 289, 258
UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 289, 270
UEP7 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 289, 257
UEP6 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 289, 257
UEP5 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 289, 257
UEP4 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 289, 257
UEP3 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 289, 257
UEP2 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 289, 257
UEP1 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 289, 257
UEP0 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 285, 257
TABLE 3-2: REGISTER FILE SUMMARY (PIC18F/LF1XK50) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on
page:
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 23.4 “Brown-out Reset (BOR)”.
2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.
3: Bits RA0 and RA1 are available only when USB is disabled.
2010 Microchip Technology Inc. Preliminary DS41350E-page 45
PIC18F1XK50/PIC18LF1XK50
3.3.6 STATUS REGISTER
The STATUS register, shown in Register 3-2, contains
the arithmetic status of the ALU. As with any other SFR,
it can be the operand for any instruction.
If the STATUS register is the destination for an instruction
that affects the Z, DC, C, OV or N bits, the results
of the instruction are not written; instead, the STATUS
register is updated according to the instruction performed.
Therefore, the result of an instruction with the
STATUS register as its destination may be different
than intended. As an example, CLRF STATUS will set
the Z bit and leave the remaining Status bits
unchanged (‘000u u1uu’).
It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the STATUS
register, because these instructions do not affect the Z,
C, DC, OV or N bits in the STATUS register.
For other instructions that do not affect Status bits, see
the instruction set summaries in Table 25-2 and
Table 25-3.
Note: The C and DC bits operate as the borrow
and digit borrow bits, respectively, in
subtraction.
REGISTER 3-2: STATUS: STATUS REGISTER
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — N OV Z DC(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 N: Negative bit
This bit is used for signed arithmetic (two’s complement). It indicates whether the result was negative
(ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3 OV: Overflow bit
This bit is used for signed arithmetic (two’s complement). It indicates an overflow of the 7-bit magnitude
which causes the sign bit (bit 7 of the result) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 46 Preliminary 2010 Microchip Technology Inc.
3.4 Data Addressing Modes
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:
• Inherent
• Literal
• Direct
• Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 3.5.1 “Indexed
Addressing with Literal Offset”.
3.4.1 INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any argument
at all; they either perform an operation that globally
affects the device or they operate implicitly on one
register. This addressing mode is known as Inherent
Addressing. Examples include SLEEP, RESET and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
3.4.2 DIRECT ADDRESSING
Direct addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and byteoriented
instructions use some version of direct
addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 3.3.4 “General
Purpose Register File”) or a location in the Access
Bank (Section 3.3.3 “Access Bank”) as the data
source for the instruction.
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 3.3.2 “Bank Select Register (BSR)”) are
used with the address to determine the complete 12-bit
address of the register. When ‘a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its original
contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
3.4.3 INDIRECT ADDRESSING
Indirect addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations which are to be read
or written. Since the FSRs are themselves located in
RAM as Special File Registers, they can also be
directly manipulated under program control. This
makes FSRs very useful in implementing data structures,
such as tables and arrays in data memory.
The registers for indirect addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code, using
loops, such as the example of clearing an entire RAM
bank in Example 3-5.
EXAMPLE 3-5: HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
Note: The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 3.5 “Data Memory
and the Extended Instruction Set” for
more information.
LFSR FSR0, 100h ;
NEXT CLRF POSTINC0 ; Clear INDF
; register then
; inc pointer
BTFSS FSR0H, 1 ; All done with
; Bank1?
BRA NEXT ; NO, clear next
CONTINUE ; YES, continue
2010 Microchip Technology Inc. Preliminary DS41350E-page 47
PIC18F1XK50/PIC18LF1XK50
3.4.3.1 FSR Registers and the INDF
Operand
At the core of indirect addressing are three sets of registers:
FSR0, FSR1 and FSR2. Each represents a pair
of 8-bit registers, FSRnH and FSRnL. Each FSR pair
holds a 12-bit value, therefore the four upper bits of the
FSRnH register are not used. The 12-bit FSR value can
address the entire range of the data memory in a linear
fashion. The FSR register pairs, then, serve as pointers
to data memory locations.
Indirect addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers: they are
mapped in the SFR space but are not physically
implemented. Reading or writing to a particular INDF
register actually accesses its corresponding FSR
register pair. A read from INDF1, for example, reads
the data at the address indicated by FSR1H:FSR1L.
Instructions that use the INDF registers as operands
actually use the contents of their corresponding FSR as
a pointer to the instruction’s target. The INDF operand
is just a convenient way of using the pointer.
Because indirect addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
3.4.3.2 FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers which cannot be directly
read or written. Accessing these registers actually
accesses the location to which the associated FSR
register pair points, and also performs a specific action
on the FSR value. They are:
• POSTDEC: accesses the location to which the
FSR points, then automatically decrements the
FSR by 1 afterwards
• POSTINC: accesses the location to which the
FSR points, then automatically increments the
FSR by 1 afterwards
• PREINC: automatically increments the FSR by 1,
then uses the location to which the FSR points in
the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the location to which the result points in the
operation.
In this context, accessing an INDF register uses the
value in the associated FSR register without changing
it. Similarly, accessing a PLUSW register gives the
FSR value an offset by that in the W register; however,
neither W nor the FSR is actually changed in the
operation. Accessing the other virtual registers
changes the value of the FSR register.
FIGURE 3-8: INDIRECT ADDRESSING
FSR1H:FSR1L
7 0
Data Memory
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
Bank 3
through
Bank 13
ADDWF, INDF1, 1
7 0
Using an instruction with one of the
indirect addressing registers as the
operand....
...uses the 12-bit address stored in
the FSR pair associated with that
register....
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair contains
ECCh. This means the contents of
location ECCh will be added to that
of the W register and stored back in
ECCh.
x x x x 1 1 1 0 1 1 0 0 1 1 0 0
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 48 Preliminary 2010 Microchip Technology Inc.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, rollovers
of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of indexed addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
3.4.3.3 Operations by FSRs on FSRs
Indirect addressing operations that target other FSRs
or virtual registers represent special cases. For
example, using an FSR to point to one of the virtual
registers will not result in successful operations. As a
specific case, assume that FSR0H:FSR0L contains
FE7h, the address of INDF1. Attempts to read the
value of the INDF1 using INDF0 as an operand will
return 00h. Attempts to write to INDF1 using INDF0 as
the operand will result in a NOP.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to either
the INDF2 or POSTDEC2 register will write the same
value to the FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses indirect addressing.
Similarly, operations by indirect addressing are generally
permitted on all other SFRs. Users should exercise the
appropriate caution that they do not inadvertently change
settings that might affect the operation of the device.
3.5 Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifically,
the use of the Access Bank for many of the core
PIC18 instructions is different; this is due to the introduction
of a new addressing mode for the data memory
space.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect addressing
with FSR0 and FSR1 also remain unchanged.
3.5.1 INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of indirect addressing using the FSR2
register pair within Access RAM. Under the proper
conditions, instructions that use the Access Bank – that
is, most bit-oriented and byte-oriented instructions –
can invoke a form of indexed addressing using an
offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset, or Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0) and
• The file address argument is less than or equal to
5Fh.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in direct addressing), or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer,
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
3.5.2 INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use direct
addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set.
Instructions that only use Inherent or Literal Addressing
modes are unaffected.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’), or include a file address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the
different possible addressing modes when the
extended instruction set is enabled is shown in
Figure 3-9.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 25.2.1
“Extended Instruction Syntax”.
2010 Microchip Technology Inc. Preliminary DS41350E-page 49
PIC18F1XK50/PIC18LF1XK50
FIGURE 3-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When ‘a’ = 0 and f 60h:
The instruction executes in
Direct Forced mode. ‘f’ is interpreted
as a location in the
Access RAM between 060h
and 0FFh. This is the same as
locations F60h to FFFh
(Bank 15) of data memory.
Locations below 60h are not
available in this addressing
mode.
When ‘a’ = 0 and f5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When ‘a’ = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is interpreted
as a location in one of
the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
000h
060h
100h
F00h
F60h
FFFh
Valid range
00h
60h
FFh
Data Memory
Access RAM
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
000h
060h
100h
F00h
F60h
FFFh
Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
FSR2H FSR2L
001001da ffffffff
001001da ffffffff
000h
060h
100h
F00h
F60h
FFFh
Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
for ‘f’
BSR
00000000
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DS41350E-page 50 Preliminary 2010 Microchip Technology Inc.
3.5.3 MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the first 96 locations of Access
RAM (00h to 5Fh) are mapped. Rather than containing
just the contents of the bottom section of Bank 0, this
mode maps the contents from a user defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower boundary
of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described (see Section 3.3.3 “Access
Bank”). An example of Access Bank remapping in this
addressing mode is shown in Figure 3-10.
Remapping of the Access Bank applies only to operations
using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use direct addressing as before.
3.6 PIC18 Instruction Execution and
the Extended Instruction Set
Enabling the extended instruction set adds eight
additional commands to the existing PIC18 instruction
set. These instructions are executed as described in
Section 25.2 “Extended Instruction Set”.
FIGURE 3-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET
ADDRESSING
Data Memory
000h
100h
200h
F60h
F00h
FFFh
Bank 1
Bank 15
Bank 2
through
Bank 14
SFRs
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
Special File Registers at
F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 0 addresses below
5Fh can still be addressed
by using the BSR. Access Bank
00h
60h
FFh
SFRs
Bank 1 “Window”
Bank 0
Window
Example Situation:
120h
17Fh
5Fh
Bank 1
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PIC18F1XK50/PIC18LF1XK50
4.0 FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
A read from program memory is executed one byte at
a time. A write to program memory is executed on
blocks of 16 or 8 bytes at a time depending on the specific
device (See Table 4-1). Program memory is
erased in blocks of 64 bytes at a time. The difference
between the write and erase block sizes requires from
1 to 8 block writes to restore the contents of a single
block erase. A bulk erase operation can not be issued
from user code.
TABLE 4-1: WRITE/ERASE BLOCK SIZES
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
4.1 Table Reads and Table Writes
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
The table read operation retrieves one byte of data
directly from program memory and places it into the
TABLAT register. Figure 4-1 shows the operation of a
table read.
The table write operation stores one byte of data from the
TABLAT register into a write block holding register. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 4.5 “Writing
to Flash Program Memory”. Figure 4-2 shows the
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. Tables containing
data, rather than program instructions, are not
required to be word aligned. Therefore, a table can start
and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word aligned.
FIGURE 4-1: TABLE READ OPERATION
Device Write Block
Size (bytes)
Erase Block
Size (bytes)
PIC18F13K50 8 64
PIC18F14K50 16 64
Table Pointer(1)
Table Latch (8-bit)
Program Memory
TBLPTRH TBLPTRL
TABLAT
TBLPTRU
Instruction: TBLRD*
Note 1: Table Pointer register points to a byte in program memory.
Program Memory
(TBLPTR)
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DS41350E-page 52 Preliminary 2010 Microchip Technology Inc.
FIGURE 4-2: TABLE WRITE OPERATION
4.2 Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
4.2.1 EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 4-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The EEPGD control bit determines if the access will be
a program or data EEPROM memory access. When
EEPGD is clear, any subsequent operations will
operate on the data EEPROM memory. When EEPGD
is set, any subsequent operations will operate on the
program memory.
The CFGS control bit determines if the access will be
to the Configuration/Calibration registers or to program
memory/data EEPROM memory. When CFGS is set,
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 24.0
“Special Features of the CPU”). When CFGS is clear,
memory selection access is determined by EEPGD.
The FREE bit allows the program memory erase operation.
When FREE is set, an erase operation is initiated
on the next WR command. When FREE is clear, only
writes are enabled.
The WREN bit, when set, will allow a write operation.
The WREN bit is clear on power-up.
The WRERR bit is set by hardware when the WR bit is
set and cleared when the internal programming timer
expires and the write operation is complete.
The WR control bit initiates write operations. The WR
bit cannot be cleared, only set, by firmware. Then WR
bit is cleared by hardware at the completion of the write
operation.
Table Pointer(1) Table Latch (8-bit)
TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
TBLPTRU
Instruction: TBLWT*
Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL
actually point to an address within the write block holding registers. The MSBs of the Table Pointer determine
where the write block will eventually be written. The process for writing the holding registers to the
program memory array is discussed in Section 4.5 “Writing to Flash Program Memory”.
Program Memory Holding Registers
Note: During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
Note: The EEIF interrupt flag bit of the PIR2
register is set when the write is complete.
The EEIF flag stays set until cleared by
firmware.
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PIC18F1XK50/PIC18LF1XK50
REGISTER 4-1: EECON1: DATA EEPROM CONTROL 1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row (Block) Erase Enable bit
1 = Erase the program memory block addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write-only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0 = The write operation completed
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) by software.)
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only
be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.
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DS41350E-page 54 Preliminary 2010 Microchip Technology Inc.
4.2.2 TABLAT – TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
4.2.3 TBLPTR – TABLE POINTER
REGISTER
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers
join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the Configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 4-2. These operations on the TBLPTR affect only
the low-order 21 bits.
4.2.4 TABLE POINTER BOUNDARIES
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
directly into the TABLAT register.
When a TBLWT is executed the byte in the TABLAT register
is written, not to Flash memory but, to a holding
register in preparation for a program memory write. The
holding registers constitute a write block which varies
depending on the device (See Table 4-1).The 3, 4, or 5
LSbs of the TBLPTRL register determine which specific
address within the holding register block is written to.
The MSBs of the Table Pointer have no effect during
TBLWT operations.
When a program memory write is executed the entire
holding register block is written to the Flash memory at
the address determined by the MSbs of the TBLPTR.
The 3, 4, or 5 LSBs are ignored during Flash memory
writes. For more detail, see Section 4.5 “Writing to
Flash Program Memory”.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
Figure 4-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 4-2: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
FIGURE 4-3: TABLE POINTER BOUNDARIES BASED ON OPERATION
Example Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*-
TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
21 16 15 8 7 0
TABLE ERASE/WRITE TABLE WRITE
TABLE READ – TBLPTR<21:0>
TBLPTRU TBLPTRH TBLPTRL
TBLPTR<21:n+1>(1) TBLPTR(1)
Note 1: n = 3, 4, 5, or 6 for block sizes of 8, 16, 32 or 64 bytes, respectively.
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PIC18F1XK50/PIC18LF1XK50
4.3 Reading the Flash Program
Memory
The TBLRD instruction retrieves data from program
memory and places it into data RAM. Table reads from
program memory are performed one byte at a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 4-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 4-4: READS FROM FLASH PROGRAM MEMORY
EXAMPLE 4-1: READING A FLASH PROGRAM MEMORY WORD
(Even Byte Address)
Program Memory
(Odd Byte Address)
TBLRD TABLAT
TBLPTR = xxxxx1
FETCH Instruction Register
(IR) Read Register
TBLPTR = xxxxx0
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_WORD
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment
MOVFW TABLAT, W ; get data
MOVF WORD_ODD
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DS41350E-page 56 Preliminary 2010 Microchip Technology Inc.
4.4 Erasing Flash Program Memory
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP™ control, can larger blocks of program memory
be bulk erased. Word erase in the Flash array is not
supported.
When initiating an erase sequence from the Microcontroller
itself, a block of 64 bytes of program memory is
erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased. The
TBLPTR<5:0> bits are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash program
memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
The write initiate sequence for EECON2, shown as
steps 4 through 6 in Section 4.4.1 “Flash Program
Memory Erase Sequence”, is used to guard against
accidental writes. This is sometimes referred to as a
long write.
A long write is necessary for erasing the internal
Flash. Instruction execution is halted during the long
write cycle. The long write is terminated by the internal
programming timer.
4.4.1 FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory is:
1. Load Table Pointer register with address of
block being erased.
2. Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
6. Set the WR bit. This will begin the block erase
cycle.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
8. Re-enable interrupts.
EXAMPLE 4-2: ERASING A FLASH PROGRAM MEMORY BLOCK
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_BLOCK
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable block Erase operation
BCF INTCON, GIE ; disable interrupts
Required MOVLW 55h
Sequence MOVWF EECON2 ; write 55h
MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
2010 Microchip Technology Inc. Preliminary DS41350E-page 57
PIC18F1XK50/PIC18LF1XK50
4.5 Writing to Flash Program Memory
The programming block size is 8 or 16 bytes,
depending on the device (See Table 4-1). Word or byte
programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are only as many holding registers as there are bytes
in a write block (See Table 4-1).
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed 8, or 16
times, depending on the device, for each programming
operation. All of the table write operations will essentially
be short writes because only the holding registers
are written. After all the holding registers have been
written, the programming operation of that block of
memory is started by configuring the EECON1 register
for a program memory write and performing the long
write sequence.
The long write is necessary for programming the internal
Flash. Instruction execution is halted during a long
write cycle. The long write will be terminated by the
internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
FIGURE 4-5: TABLE WRITES TO FLASH PROGRAM MEMORY
4.5.1 FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer register with address being
erased.
4. Execute the block erase procedure.
5. Load Table Pointer register with address of first
byte being written.
6. Write the 8 or 16-byte block into the holding
registers with auto-increment.
7. Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
8. Disable interrupts.
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Re-enable interrupts.
14. Repeat steps 6 to 13 for each block until all 64
bytes are written.
15. Verify the memory (table read).
This procedure will require about 6 ms to update each
write block of memory. An example of the required code
is given in Example 4-3.
Note: The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may
be modified, provided that the change does
not attempt to change any bit from a ‘0’ to a
‘1’. When modifying individual bytes, it is
not necessary to load all holding registers
before executing a long write operation.
TABLAT
TBLPTR = xxxx00 TBLPTR = xxxx01 TBLPTR = xxxxYY(1)
Write Register
TBLPTR = xxxx02
Program Memory
Holding Register Holding Register Holding Register Holding Register
8 8 8 8
Note 1: YY = x7, xF, or 1F for 8, 16 or 32 byte write blocks, respectively.
Note: Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the bytes in the
holding registers.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 58 Preliminary 2010 Microchip Technology Inc.
EXAMPLE 4-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW D'64’ ; number of bytes in erase block
MOVWF COUNTER
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_BLOCK
TBLRD*+ ; read into TABLAT, and inc
MOVF TABLAT, W ; get data
MOVWF POSTINC0 ; store data
DECFSZ COUNTER ; done?
BRA READ_BLOCK ; repeat
MODIFY_WORD
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW NEW_DATA_LOW ; update buffer word
MOVWF POSTINC0
MOVLW NEW_DATA_HIGH
MOVWF INDF0
ERASE_BLOCK
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
TBLRD*- ; dummy read decrement
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
WRITE_BUFFER_BACK
MOVLW BlockSize ; number of bytes in holding register
MOVWF COUNTER
MOVLW D’64’/BlockSize ; number of write blocks in 64 bytes
MOVWF COUNTER2
WRITE_BYTE_TO_HREGS
MOVF POSTINC0, W ; get low byte of buffer data
MOVWF TABLAT ; present data to table latch
TBLWT+* ; write data, perform a short write
; to internal TBLWT holding register.
2010 Microchip Technology Inc. Preliminary DS41350E-page 59
PIC18F1XK50/PIC18LF1XK50
EXAMPLE 4-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
4.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
4.5.3 UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset or a WDT Time-out Reset
during normal operation, the WRERR bit will be set
which the user can check to decide whether a rewrite
of the location(s) is needed.
4.5.4 PROTECTION AGAINST
SPURIOUS WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 24.0 “Special Features of the
CPU” for more detail.
4.6 Flash Program Operation During
Code Protection
See Section 24.3 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 4-3: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
DECFSZ COUNTER ; loop until holding registers are full
BRA WRITE_WORD_TO_HREGS
PROGRAM_MEMORY
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start program (CPU stall)
DCFSZ COUNTER2 ; repeat for remaining write blocks
BRA WRITE_BYTE_TO_HREGS ;
BSF INTCON, GIE ; re-enable interrupts
BCF EECON1, WREN ; disable write to memory
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
page
TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 285
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 285
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 285
TABLAT Program Memory Table Latch 285
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
EECON2 EEPROM Control Register 2 (not a physical register) 287
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 287
IPR2 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP — 288
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF — 288
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE — 288
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
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DS41350E-page 60 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 61
PIC18F/LF1XK50
5.0 DATA EEPROM MEMORY
The data EEPROM is a nonvolatile memory array,
separate from the data RAM and program memory,
which is used for long-term storage of program data. It
is not directly mapped in either the register file or
program memory space but is indirectly addressed
through the Special Function Registers (SFRs). The
EEPROM is readable and writable during normal
operation over the entire VDD range.
Four SFRs are used to read and write to the data
EEPROM as well as the program memory. They are:
• EECON1
• EECON2
• EEDATA
• EEADR
The data EEPROM allows byte read and write. When
interfacing to the data memory block, EEDATA holds
the 8-bit data for read/write and the EEADR register
pair hold the address of the EEPROM location being
accessed.
The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write).
The write time is controlled by an on-chip timer; it will
vary with voltage and temperature as well as from chipto-
chip. Please refer to parameter US122 (Table 27-13
in Section 27.0 “Electrical Specifications”) for exact
limits.
5.1 EEADR Register
The EEADR register is used to address the data
EEPROM for read and write operations. The 8-bit
range of the register can address a memory range of
256 bytes (00h to FFh).
5.2 EECON1 and EECON2 Registers
Access to the data EEPROM is controlled by two
registers: EECON1 and EECON2. These are the same
registers which control access to the program memory
and are used in a similar manner for the data
EEPROM.
The EECON1 register (Register 5-1) is the control
register for data and program memory access. Control
bit EEPGD determines if the access will be to program
or data EEPROM memory. When the EEPGD bit is
clear, operations will access the data EEPROM
memory. When the EEPGD bit is set, program memory
is accessed.
Control bit, CFGS, determines if the access will be to
the Configuration registers or to program memory/data
EEPROM memory. When the CFGS bit is set,
subsequent operations access Configuration registers.
When the CFGS bit is clear, the EEPGD bit selects
either program Flash or data EEPROM memory.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear.
The WRERR bit is set by hardware when the WR bit is
set and cleared when the internal programming timer
expires and the write operation is complete.
The WR control bit initiates write operations. The bit
can be set but not cleared by software. It is cleared only
by hardware at the completion of the write operation.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 4.1 “Table Reads
and Table Writes” regarding table reads.
The EECON2 register is not a physical register. It is
used exclusively in the memory write and erase
sequences. Reading EECON2 will read all ‘0’s.
Note: During normal operation, the WRERR
may read as ‘1’. This can indicate that a
write operation was prematurely terminated
by a Reset, or a write operation was
attempted improperly.
Note: The EEIF interrupt flag bit of the PIR2
register is set when the write is complete.
It must be cleared by software.
PIC18F/LF1XK50
DS41350E-page 62 Preliminary 2010 Microchip Technology Inc.
REGISTER 5-1: EECON1: DATA EEPROM CONTROL 1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row (Block) Erase Enable bit
1 = Erase the program memory block addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write-only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0 = The write operation completed
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) by software.)
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only
be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.
2010 Microchip Technology Inc. Preliminary DS41350E-page 63
PIC18F/LF1XK50
5.3 Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD control
bit of the EECON1 register and then set control bit,
RD. The data is available on the very next instruction
cycle; therefore, the EEDATA register can be read by
the next instruction. EEDATA will hold this value until
another read operation, or until it is written to by the
user (during a write operation).
The basic process is shown in Example 5-1.
5.4 Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data written
to the EEDATA register. The sequence in
Example 5-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
should be kept clear at all times, except when updating
the EEPROM. The WREN bit is not cleared by
hardware.
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared by hardware and the EEPROM Interrupt Flag
bit, EEIF, is set. The user may either enable this
interrupt or poll this bit. EEIF must be cleared by
software.
5.5 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
EXAMPLE 5-1: DATA EEPROM READ
EXAMPLE 5-2: DATA EEPROM WRITE
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to read
BCF EECON1, EEPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, RD ; EEPROM Read
MOVF EEDATA, W ; W = EEDATA
MOVLW DATA_EE_ADDR_LOW ;
MOVWF EEADR ; Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDATA ; Data Memory Value to write
BCF EECON1, EEPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable Interrupts
MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW 0AAh ;
MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BSF INTCON, GIE ; Enable Interrupts
; User code execution
BCF EECON1, WREN ; Disable writes on write complete (EEIF set)
PIC18F/LF1XK50
DS41350E-page 64 Preliminary 2010 Microchip Technology Inc.
5.6 Operation During Code-Protect
Data EEPROM memory has its own code-protect bits in
Configuration Words. External read and write
operations are disabled if code protection is enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect Configuration bit. Refer to Section 24.0
“Special Features of the CPU” for additional
information.
5.7 Protection Against Spurious Write
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are blocked
during the Power-up Timer period (TPWRT,
parameter 33).
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
5.8 Using the Data EEPROM
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated often).
When variables in one section change frequently, while
variables in another section do not change, it is possible
to exceed the total number of write cycles to the
EEPROM without exceeding the total number of write
cycles to a single byte. If this is the case, then an array
refresh must be performed. For this reason, variables
that change infrequently (such as constants, IDs,
calibration, etc.) should be stored in Flash program
memory.
EXAMPLE 5-3: DATA EEPROM REFRESH ROUTINE
TABLE 5-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 287
EEDATA EEPROM Data Register 287
EECON2 EEPROM Control Register 2 (not a physical register) 287
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 287
IPR2 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP — 288
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF — 288
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE — 288
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
CLRF EEADR ; Start at address 0
BCF EECON1, CFGS ; Set for memory
BCF EECON1, EEPGD ; Set for Data EEPROM
BCF INTCON, GIE ; Disable interrupts
BSF EECON1, WREN ; Enable writes
Loop ; Loop to refresh array
BSF EECON1, RD ; Read current address
MOVLW 55h ;
MOVWF EECON2 ; Write 55h
MOVLW 0AAh ;
MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BTFSC EECON1, WR ; Wait for write to complete
BRA $-2
INCFSZ EEADR, F ; Increment address
BRA LOOP ; Not zero, do it again
BCF EECON1, WREN ; Disable writes
BSF INTCON, GIE ; Enable interrupts
2010 Microchip Technology Inc. Preliminary DS41350E-page 65
PIC18F/LF1XK50
6.0 8 x 8 HARDWARE MULTIPLIER
6.1 Introduction
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applications
previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 6-1.
6.2 Operation
Example 6-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 6-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
EXAMPLE 6-1: 8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 6-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
TABLE 6-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG2
Routine Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz @ 10 MHz @ 4 MHz
8 x 8 unsigned
Without hardware multiply 13 69 6.9 s 27.6 s 69 s
Hardware multiply 1 1 100 ns 400 ns 1 s
8 x 8 signed
Without hardware multiply 33 91 9.1 s 36.4 s 91 s
Hardware multiply 6 6 600 ns 2.4 s 6 s
16 x 16 unsigned
Without hardware multiply 21 242 24.2 s 96.8 s 242 s
Hardware multiply 28 28 2.8 s 11.2 s 28 s
16 x 16 signed
Without hardware multiply 52 254 25.4 s 102.6 s 254 s
Hardware multiply 35 40 4.0 s 16.0 s 40 s
PIC18F/LF1XK50
DS41350E-page 66 Preliminary 2010 Microchip Technology Inc.
Example 6-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 6-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES<3:0>).
EQUATION 6-1: 16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 6-3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
Example 6-4 shows the sequence to do a 16 x 16
signed multiply. Equation 6-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES<3:0>). To account for the sign bits of the arguments,
the MSb for each argument pair is tested and
the appropriate subtractions are done.
EQUATION 6-2: 16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 6-4: 16 x 16 SIGNED
MULTIPLY ROUTINE
RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L) +
(-1 ARG2H<7> ARG1H:ARG1L 216) +
(-1 ARG1H<7> ARG2H:ARG2L 216)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
BRA SIGN_ARG1 ; no, check ARG1
MOVF ARG1L, W ;
SUBWF RES2 ;
MOVF ARG1H, W ;
SUBWFB RES3
;
SIGN_ARG1
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
BRA CONT_CODE ; no, done
MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3
;
CONT_CODE
:
2010 Microchip Technology Inc. Preliminary DS41350E-page 67
PIC18F/LF1XK50
7.0 INTERRUPTS
The PIC18F/LF1XK50 devices have multiple interrupt
sources and an interrupt priority feature that allows
most interrupt sources to be assigned a high priority
level or a low priority level. The high priority interrupt
vector is at 0008h and the low priority interrupt vector is
at 0018h. A high priority interrupt event will interrupt a
low priority interrupt that may be in progress.
There are ten registers which are used to control
interrupt operation. These registers are:
• RCON
• INTCON
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2
It is recommended that the Microchip header files supplied
with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
In general, interrupt sources have three bits to control
their operation. They are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
7.1 Mid-Range Compatibility
When the IPEN bit is cleared (default state), the interrupt
priority feature is disabled and interrupts are compatible
with PIC® microcontroller mid-range devices. In
Compatibility mode, the interrupt priority bits of the IPRx
registers have no effect. The PEIE bit of the INTCON
register is the global interrupt enable for the peripherals.
The PEIE bit disables only the peripheral interrupt
sources and enables the peripheral interrupt sources
when the GIE bit is also set. The GIE bit of the INTCON
register is the global interrupt enable which enables all
non-peripheral interrupt sources and disables all
interrupt sources, including the peripherals. All interrupts
branch to address 0008h in Compatibility mode.
7.2 Interrupt Priority
The interrupt priority feature is enabled by setting the
IPEN bit of the RCON register. When interrupt priority
is enabled the GIE and PEIE global interrupt enable
bits of Compatibility mode are replaced by the GIEH
high priority, and GIEL low priority, global interrupt
enables. When set, the GIEH bit of the INTCON register
enables all interrupts that have their associated
IPRx register or INTCONx register priority bit set (high
priority). When clear, the GIEL bit disables all interrupt
sources including those selected as low priority. When
clear, the GIEL bit of the INTCON register disables only
the interrupts that have their associated priority bit
cleared (low priority). When set, the GIEL bit enables
the low priority sources when the GIEH bit is also set.
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are all set, the interrupt will
vector immediately to address 0008h for high priority,
or 0018h for low priority, depending on level of the
interrupting source’s priority bit. Individual interrupts
can be disabled through their corresponding interrupt
enable bits.
7.3 Interrupt Response
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. The
GIE bit is the global interrupt enable when the IPEN bit
is cleared. When the IPEN bit is set, enabling interrupt
priority levels, the GIEH bit is the high priority global
interrupt enable and the GIEL bit is the low priority
global interrupt enable. High priority interrupt sources
can interrupt a low priority interrupt. Low priority
interrupts are not processed while high priority
interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits in the INTCONx and PIRx
registers. The interrupt flag bits must be cleared by
software before re-enabling interrupts to avoid
repeating the same interrupt.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the PORTB interrupt-on-change, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one-cycle or two-cycle
PIC18F/LF1XK50
DS41350E-page 68 Preliminary 2010 Microchip Technology Inc.
instructions. Individual interrupt flag bits are set,
regardless of the status of their corresponding enable
bits or the global interrupt enable bit.
Note: Do not use the MOVFF instruction to modify
any of the interrupt control registers
while any interrupt is enabled. Doing so
may cause erratic microcontroller behavior.
2010 Microchip Technology Inc. Preliminary DS41350E-page 69
PIC18F/LF1XK50
FIGURE 7-1: PIC18 INTERRUPT LOGIC
TMR0IE
GIEH/GIE
GIEL/PEIE
Wake-up if in
Interrupt to CPU
Vector to Location
0008h
INT2IF
INT2IE
INT2IP
INT1IF
INT1IE
INT1IP
TMR0IF
TMR0IE
TMR0IP
RABIF
RABIE
RABIP
IPEN
TMR0IF
TMR0IP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
RABIF
RABIE
RABIP
INT0IF
INT0IE
GIEL/PEIE
Interrupt to CPU
Vector to Location
IPEN
IPEN
0018h
SSPIF
SSPIE
SSPIP
SSPIF
SSPIE
SSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
Additional Peripheral Interrupts
ADIF
ADIE
ADIP
High Priority Interrupt Generation
Low Priority Interrupt Generation
RCIF
RCIE
RCIP
Additional Peripheral Interrupts
Idle or Sleep modes
GIEH/GIE
Note 1: The RABIF interrupt also requires the individual pin IOCA and IOCB enable.
(1)
(1)
PIC18F/LF1XK50
DS41350E-page 70 Preliminary 2010 Microchip Technology Inc.
7.4 INTCON Registers
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts including peripherals
When IPEN = 1:
1 = Enables all high priority interrupts
0 = Disables all interrupts including low priority.
bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority interrupts
0 = Disables all low priority interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3 RABIE: RA and RB Port Change Interrupt Enable bit(2)
1 = Enables the RA and RB port change interrupt
0 = Disables the RA and RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared by software)
0 = TMR0 register did not overflow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared by software)
0 = The INT0 external interrupt did not occur
bit 0 RABIF: RA and RB Port Change Interrupt Flag bit(1)
1 = At least one of the RA <5:3> or RB<7:4> pins changed state (must be cleared by software)
0 = None of the RA<5:3> or RB<7:4> pins have changed state
Note 1: A mismatch condition will continue to set the RABIF bit. Reading PORTA and PORTB will end the
mismatch condition and allow the bit to be cleared.
2: RA and RB port change interrupts also require the individual pin IOCA and IOCB enable.
2010 Microchip Technology Inc. Preliminary DS41350E-page 71
PIC18F/LF1XK50
REGISTER 7-2: INTCON2: INTERRUPT CONTROL 2 REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1
RABPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RABPU: PORTA and PORTB Pull-up Enable bit
1 = All PORTA and PORTB pull-ups are disabled
0 = PORTA and PORTB pull-ups are enabled provided that the pin is an input and the corresponding
WPUA and WPUB bits are set.
bit 6 INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5 INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4 INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3 Unimplemented: Read as ‘0’
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 Unimplemented: Read as ‘0’
bit 0 RABIP: RA and RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
PIC18F/LF1XK50
DS41350E-page 72 Preliminary 2010 Microchip Technology Inc.
REGISTER 7-3: INTCON3: INTERRUPT CONTROL 3 REGISTER
R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 Unimplemented: Read as ‘0’
bit 4 INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3 INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2 Unimplemented: Read as ‘0’
bit 1 INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared by software)
0 = The INT2 external interrupt did not occur
bit 0 INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared by software)
0 = The INT1 external interrupt did not occur
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
2010 Microchip Technology Inc. Preliminary DS41350E-page 73
PIC18F/LF1XK50
7.5 PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request Flag registers (PIR1 and PIR2).
Note 1: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the
state of its corresponding enable bit or the
Global Interrupt Enable bit, GIE of the
INTCON register.
2: User software should ensure the appropriate
interrupt flag bits are cleared prior
to enabling an interrupt and after servicing
that interrupt.
REGISTER 7-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared by software)
0 = The A/D conversion is not complete or has not been started
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The EUSART receive buffer is empty
bit 4 TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The EUSART transmit buffer is full
bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared by software)
0 = Waiting to transmit/receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared by software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared by software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared by software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared by software)
0 = TMR1 register did not overflow
PIC18F/LF1XK50
DS41350E-page 74 Preliminary 2010 Microchip Technology Inc.
REGISTER 7-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit
1 = Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software)
0 = Device clock operating
bit 6 C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator C1 output has changed (must be cleared by software)
0 = Comparator C1 output has not changed
bit 5 C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator C2 output has changed (must be cleared by software)
0 = Comparator C2 output has not changed
bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1 = The write operation is complete (must be cleared by software)
0 = The write operation is not complete or has not been started
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision occurred (must be cleared by software)
0 = No bus collision occurred
bit 2 USBIF: USB Interrupt Flag bit
1 = USB has requested an interrupt (must be cleared in software)
0 = No USB interrupt request
bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared by software)
0 = TMR3 register did not overflow
bit 0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 75
PIC18F/LF1XK50
7.6 PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Enable registers (PIE1 and PIE2). When IPEN = 0, the
PEIE bit must be set to enable any of these peripheral
interrupts.
REGISTER 7-6: PIE1: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5 RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
PIC18F/LF1XK50
DS41350E-page 76 Preliminary 2010 Microchip Technology Inc.
REGISTER 7-7: PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6 C1IE: Comparator C1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5 C2IE: Comparator C2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 USBIE: USB Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 77
PIC18F/LF1XK50
7.7 IPR Registers
The IPR registers contain the individual priority bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Priority registers (IPR1 and IPR2). Using the priority bits
requires that the Interrupt Priority Enable (IPEN) bit be
set.
REGISTER 7-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 RCIP: EUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TXIP: EUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
PIC18F/LF1XK50
DS41350E-page 78 Preliminary 2010 Microchip Technology Inc.
REGISTER 7-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0
OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 C1IP: Comparator C1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 C2IP: Comparator C2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 USBIP: USB Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 79
PIC18F/LF1XK50
7.8 RCON Register
The RCON register contains flag bits which are used to
determine the cause of the last Reset or wake-up from
Idle or Sleep modes. RCON also contains the IPEN bit
which enables interrupt priorities.
The operation of the SBOREN bit and the Reset flag
bits is discussed in more detail in Section 23.1 “RCON
Register”.
REGISTER 7-10: RCON: RESET CONTROL REGISTER
R/W-0 R/W-1 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN SBOREN(1) — RI TO PD POR(2) BOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 SBOREN: BOR Software Enable bit(1)
If BOREN<1:0> = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN<1:0> = 00, 10 or 11:
Bit is disabled and read as ‘0’.
bit 5 Unimplemented: Read as ‘0’
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware or Power-on Reset)
0 = The RESET instruction was executed causing a device Reset (must be set in firmware after a
code-executed Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit(2)
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit(3)
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs)
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.
2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this
register and Section 23.6 “Reset State of Registers” for additional information.
3: See Table 23-3.
PIC18F/LF1XK50
DS41350E-page 80 Preliminary 2010 Microchip Technology Inc.
7.9 INTn Pin Interrupts
External interrupts on the RC0/INT0, RC1/INT1 and
RC2/INT2 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge; if
the bit is clear, the trigger is on the falling edge. When
a valid edge appears on the RCx/INTx pin, the
corresponding flag bit, INTxF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxE. Flag bit, INTxF, must be cleared by software in
the Interrupt Service Routine before re-enabling the
interrupt.
All external interrupts (INT0, INT1 and INT2) can wakeup
the processor from Idle or Sleep modes if bit INTxE
was set prior to going into those modes. If the Global
Interrupt Enable bit, GIE, is set, the processor will
branch to the interrupt vector following wake-up.
Interrupt priority for INT1 and INT2 is determined by
the value contained in the interrupt priority bits,
INT1IP and INT2IP of the INTCON3 register. There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
7.10 TMR0 Interrupt
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
pair (FFFFh 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE of the INTCON register. Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP of the INTCON2 register.
See Section 10.0 “Timer0 Module” for further details
on the Timer0 module.
7.11 PORTA and PORTB Interrupt-on-
Change
An input change on PORTA or PORTB sets flag bit,
RABIF of the INTCON register. The interrupt can be
enabled/disabled by setting/clearing enable bit, RABIE
of the INTCON register. Pins must also be individually
enabled with the IOCA and IOCB register. Interrupt
priority for PORTA and PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RABIP of the INTCON2 register.
7.12 Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 3.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 7-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 7-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP ; W_TEMP is in virtual bank
MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR ; Restore BSR
MOVF W_TEMP, W ; Restore WREG
MOVFF STATUS_TEMP, STATUS ; Restore STATUS
2010 Microchip Technology Inc. Preliminary DS41350E-page 81
PIC18F1XK50/PIC18LF1XK50
8.0 LOW DROPOUT (LDO)
VOLTAGE REGULATOR
The PIC18F1XK50 devices differ from the
PIC18LF1XK50 devices due to an internal Low
Dropout (LDO) voltage regulator. The PIC18F1XK50
contain an internal LDO, while the PIC18LF1XK50 do
not.
The lithography of the die allows a maximum operating
voltage of the nominal 3.6V on the internal digital logic.
In order to continue to support 5.0V designs, a LDO
voltage regulator is integrated on the die. The LDO
voltage regulator allows for the internal digital logic to
operate at 3.3V, while I/O’s operate at 5.0V (VDD).
The LDO voltage regulator requires an external bypass
capacitor for stability. The VUSB pin is required to have
an external bypass capacitor. It is recommended that
the capacitor be a ceramic cap between 0.22 to 0.47 μF.
On power-up, the external capacitor will look like a
large load on the LDO voltage regulator. To prevent
erroneous operation, the device is held in Reset while
a constant current source charges the external
capacitor. After the cap is fully charged, the device is
released from Reset. For more information, refer to
Section 27.0 “Electrical Specifications”.
PIC18F1XK50/PIC18LF1XK50
DS41350E-page 82 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 83
PIC18F/LF1XK50
9.0 I/O PORTS
There are up to three ports available. Some pins of the
I/O ports are multiplexed with an alternate function from
the peripheral features on the device. In general, when
a peripheral is enabled, that pin may not be used as a
general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The PORTA Data Latch (LATA register) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 9-1.
FIGURE 9-1: GENERIC I/O PORT
OPERATION
9.1 PORTA, TRISA and LATA Registers
PORTA is 5 bits wide. PORTA<5:4> bits are
bidirectional ports and PORTA<3,1:0> bits are inputonly
ports. The corresponding data direction register is
TRISA. Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enable the
output driver and put the contents of the output latch on
the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the PORT latch.
The PORTA Data Latch (LATA) register is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
All of the PORTA pins are individually configurable as
interrupt-on-change pins. Control bits in the IOCA
register enable (when set) or disable (when clear) the
interrupt function for each pin.
When set, the RABIE bit of the INTCON register
enables interrupts on all pins which also have their
corresponding IOCA bit set. When clear, the RABIE
bit disables all interrupt-on-changes.
Only pins configured as inputs can cause this interrupt
to occur (i.e., any pin configured as an output is
excluded from the interrupt-on-change comparison).
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTA Change Interrupt flag
bit (RABIF) in the INTCON register.
This interrupt can wake the device from the Sleep
mode, or any of the Idle modes. The user, in the
Interrupt Service Routine, can clear the interrupt in the
following manner:
a) Any read or write of PORTA to clear the mismatch
condition (except when PORTA is the
source or destination of a MOVFF instruction).
b) Clear the flag bit, RABIF.
A mismatch condition will continue to set the RABIF flag
bit. Reading or writing PORTA will end the mismatch
condition and allow the RABIF bit to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Reset. After either one of these Resets, the
RABIF flag will continue to be set if a mismatch is present.
Data
Bus
WR LAT
WR TRIS
RD Port
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
I/O pin(1)
D Q
CK
D Q
CK
EN
Q D
EN
RD LAT
or Port
Note 1: I/O pins have diode protection to VDD and VSS.
PIC18F/LF1XK50
DS41350E-page 84 Preliminary 2010 Microchip Technology Inc.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTA is only used for the interrupt-on-change
feature. Polling of PORTA is not recommended while
using the interrupt-on-change feature.
Each of the PORTA pins has an individually controlled
weak internal pull-up. When set, each bit of the WPUA
register enables the corresponding pin pull-up. When
cleared, the RABPU bit of the INTCON2 register
enables pull-ups on all pins which also have their corresponding
WPUA bit set. When set, the RABPU bit
disables all weak pull-ups. The weak pull-up is automatically
turned off when the port pin is configured as
an output. The pull-ups are disabled on a Power-on
Reset.
RA0 and RA1 are multiplexed with the USB module
and can serve as the differential data lines for the onchip
USB transceiver.
RA0 and RA1 do not have TRISA bits associated with
them. As digital port pins, they can only function as
digital inputs. When configured for USB operation, the
data direction is determined by the configuration and
status of the USB module at a given time.
RA3 is an input only pin. Its operation is controlled by
the MCLRE bit of the CONFIG3H register. When
selected as a port pin (MCLRE = 0), it functions as a
digital input only pin; as such, it does not have TRIS or
LAT bits associated with its operation.
Pins RA4 and RA5 are multiplexed with the main oscillator
pins; they are enabled as oscillator or I/O pins by
the selection of the main oscillator in the Configuration
register (see Section 24.1 “Configuration Bits” for
details). When they are not used as port pins, RA4 and
RA5 and their associated TRIS and LAT bits read as
‘0’.
Pin RA4 is multiplexed with an analog input. The operation
of pin RA4 as analog is selected by setting the
ANS3 bit in the ANSEL register which is the default setting
after a Power-on Reset.
EXAMPLE 9-1: INITIALIZING PORTA
Note 1: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the
RABIF interrupt flag may not get set. Furthermore,
since a read or write on a port
affects all bits of that port, care must be
taken when using multiple pins in Interrupt-
on-change mode. Changes on one
pin may not be seen while servicing
changes on another pin.
2: When configured for USB operation,
interrupt-on-change functionality on RA0
and RA1 is automatically disabled.
3: In order for the digital inputs to function
on the RA<1:0> port pins, the interrupton-
change pins must be enabled (IOCA
<1:0> = 11) and the USB module must be
disabled (USBEN = 0).
Note: On a Power-on Reset, RA4 is configured
as analog inputs by default and read as
‘0’; RA<1:0> and RA<5:3> are configured
as digital inputs.
Note: On a Power-on Reset, RA3 is enabled as
a digital input only if Master Clear
functionality is disabled.
Note: On a Power-on Reset, RA4 is configured
as analog inputs and read as ‘0’.
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
CLRF LATA ; Alternate method
; to clear output
; data latches
MOVLW 030h ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<5:4> as output
2010 Microchip Technology Inc. Preliminary DS41350E-page 85
PIC18F/LF1XK50
REGISTER 9-1: PORTA: PORTA REGISTER
U-0 U-0 R/W-x R/W-x R-x U-0 R/W-x R/W-x
— — RA5 RA4 RA3 — RA1 RA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-3 RA<5:3>: PORTA I/O Pin bit(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 2 Unimplemented: Read as ‘0’
bit 1-0 RA<1:0>: PORTA I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0).
Otherwise, RA3 reads as ‘0’. This bit is read-only.
REGISTER 9-2: TRISA: PORTA TRI-STATE REGISTER
U-0 U-0 R/W-1 R/W-1 U-0 U-0 U-0 U-0
— — TRISA5 TRISA4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 TRISA<5:4>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
bit 3-0 Unimplemented: Read as ‘0’
Note 1: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
PIC18F/LF1XK50
DS41350E-page 86 Preliminary 2010 Microchip Technology Inc.
REGISTER 9-3: WPUA: WEAK PULL-UP PORTA REGISTER
U-0 U-0 R/W-1 R/W-1 RW-1 U-0 U-0 U-0
— — WPUA5 WPUA4 WPUA3 — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-3 WPUA<5:3>: Weak Pull-up Enable bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 2 Unimplemented: Read as ‘0’
bit 1-0 WPUA<1:0>: Weak Pull-up Enable bit
1 = Pull-up enabled
0 = Pull-up disabled
REGISTER 9-4: IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER
U-0 U-0 R/W-0 R/W-0 R-0 U-0 R/W-0 R/W-0
— — IOCA5 IOCA4 IOCA3 — IOCA1 IOCA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-3 IOCA<5:3>: PORTA I/O Pin bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
bit 2 Unimplemented: Read as ‘0’
bit 1-0 IOCA<1:0>: PORTA I/O Pin bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
REGISTER 9-5: LATA: PORTA DATA LATCH REGISTER
U-0 U-0 R/W-x R/W-x U-0 U-0 U-0 U-0
— — LATA5 LATA4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 LATA<5:4>: RA<5:4> Port I/O Output Latch Register bits
bit 3-0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 87
PIC18F/LF1XK50
TABLE 9-1: PORTA I/O SUMMARY
Pin Function TRIS
Setting I/O I/O
Type Description
RA0/IOCA0/D+/
PGD
RA0 —(1) I TTL PORTA<0> data input; disabled when USB enabled.
IOCA0 —(1) I TTL Interrupt-on-pin change; disabled when USB enabled.
D+ —(1) I XCVR USB bus differential plus line input (internal transceiver).
—(1) O XCVR USB bus differential plus line output (internal transceiver).
PGD —(1) O DIG Serial execution data output for ICSP™.
—(1) I ST Serial execution data input for ICSP™.
RA1/IOCA1/D-/
PGC
RA1 —(1) I TTL PORTA<1> data input; disabled when USB enabled.
IOCA1 —(1) I TTL Interrupt-on-pin change; disabled when USB enabled.
D- —(1) I XCVR USB bus differential minus line input (internal transceiver).
—(1) O XCVR USB bus differential minus line output (internal transceiver).
PGC —(1) O DIG Serial execution clock output for ICSP™.
—(1) I ST Serial execution clock input for ICSP™.
RA3/IOCA3/MCLR/
VPP
RA3 —(2) I ST PORTA<3> data input; enabled when MCLRE Configuration bit is
clear; Programmable weak pull-up.
IOCA3 —(1) I TTL Interrupt-on-pin change
MCLR — I ST External Master Clear input; enabled when MCLRE Configuration bit is
set.
VPP — I ANA High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
RA4/IOCA4/AN3/
OSC2/CLKOUT
RA4 0 O DIG LATA<4> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
1 I TTL PORTA<4> data input; Programmable weak pull-up. Enabled in RCIO,
INTIO2 and ECIO modes only.
IOCA4 1 I TTL Interrupt-on-pin change
AN3 1 I ANA A/D input channel 3. Default configuration on POR.
OSC2 x O ANA Main oscillator feedback output connection (XT, HS and LP modes).
CLKOUT x O DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator
modes.
RA5/IOCA5/OSC1/
CLKIN
RA5 0 O DIG LATA<5> data output. Disabled in external oscillator modes.
1 I TTL PORTA<5> data input. Disabled in external oscillator modes; Programmable
weak pull-up.
IOCA5 1 I TTL Interrupt-on-pin change
OSC1 x I ANA Main oscillator input connection.
CLKIN x I ANA Main clock input connection.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: RA0 and RA1 do not have corresponding TRISA bits. In Port mode, these pins are input only. USB data direction is
determined by the USB configuration.
2: RA3 does not have a corresponding TRISA bit. This pin is always an input regardless of mode.
PIC18F/LF1XK50
DS41350E-page 88 Preliminary 2010 Microchip Technology Inc.
TABLE 9-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
page
PORTA — — RA5(1) RA4(1) RA3(2) — RA1(3) RA0(3) 288
LATA — — LATA5(1) LATA4(1) — — — — 288
TRISA — — TRISA5(1) TRISA4(1) — — — — 288
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 — — — 288
SLRCON — — — — — SLRC SLRB SLRA 288
IOCA — — IOCA5 IOCA4 IOCA3(2) — IOCA1(3) IOCA0(3) 288
WPUA — — WPUA5 WPUA4 WPUA3(2) — — — 288
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 288
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
INTCON2 RABPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP 285
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA<5:4> and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
2: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
3: RA1 and RA0 are only available as port pins when the USB module is disabled (UCON<3> = 0).
2010 Microchip Technology Inc. Preliminary DS41350E-page 89
PIC18F/LF1XK50
9.2 PORTB, TRISB and LATB
Registers
PORTB is an 4-bit wide, bidirectional port. The corresponding
data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., disable the output driver). Clearing a
TRISB bit (= 0) will make the corresponding PORTB
pin an output (i.e., enable the output driver and put the
contents of the output latch on the selected pin).
The PORTB Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
EXAMPLE 9-2: INITIALIZING PORTB
All PORTB pins are individually configurable as
interrupt-on-change pins. Control bits in the IOCB register
enable (when set) or disable (when clear) the
interrupt function for each pin.
When set, the RABIE bit of the INTCON register
enables interrupts on all pins which also have their
corresponding IOCB bit set. When clear, the RABIE
bit disables all interrupt-on-changes.
Only pins configured as inputs can cause this interrupt
to occur (i.e., any pin configured as an output is
excluded from the interrupt-on-change comparison).
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTB. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTB Change Interrupt flag
bit (RABIF) in the INTCON register.
This interrupt can wake the device from the Sleep
mode, or any of the Idle modes. The user, in the
Interrupt Service Routine, can clear the interrupt in the
following manner:
a) Any read or write of PORTB to clear the mismatch
condition (except when PORTB is the
source or destination of a MOVFF instruction).
b) Clear the flag bit, RABIF.
A mismatch condition will continue to set the RABIF flag
bit. Reading or writing PORTB will end the mismatch
condition and allow the RABIF bit to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Reset. After either one of these Resets, the
RABIF flag will continue to be set if a mismatch is present.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
All PORTB pins have individually controlled weak internal
pull-up. When set, each bit of the WPUB register
enables the corresponding pin pull-up. When cleared,
the RABPU bit of the INTCON2 register enables pullups
on all pins which also have their corresponding
WPUB bit set. When set, the RABPU bit disables all
weak pull-ups. The weak pull-up is automatically turned
off when the port pin is configured as an output. The
pull-ups are disabled on a Power-on Reset.
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
CLRF LATB ; Alternate method
; to clear output
; data latches
MOVLW 0F0h ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<7:4> as outputs
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RABIF
interrupt flag may not get set. Furthermore,
since a read or write on a port affects all
bits of that port, care must be taken when
using multiple pins in Interrupt-on-change
mode. Changes on one pin may not be
seen while servicing changes on another
pin.
Note: On a Power-on Reset, RB<5:4> are
configured as analog inputs by default and
read as ‘0’.
PIC18F/LF1XK50
DS41350E-page 90 Preliminary 2010 Microchip Technology Inc.
REGISTER 9-6: PORTB: PORTB REGISTER
R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0
RB7 RB6 RB5 RB4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 RB<7:4>: PORTB I/O Pin bit
1 = Port pin is >VIH
0 = Port pin is : PORTB Tri-State Control bit
1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
bit 3-0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 91
PIC18F/LF1XK50
REGISTER 9-8: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0
WPUB7 WPUB6 WPUB5 WPUB4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 WPUB<7:4>: Weak Pull-up Enable bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 3-0 Unimplemented: Read as ‘0’
REGISTER 9-9: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
IOCB7 IOCB6 IOCB5 IOCB4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 IOCB<7:4>: Interrupt-on-change bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
bit 3-0 Unimplemented: Read as ‘0’
REGISTER 9-10: LATB: PORTB DATA LATCH REGISTER
R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0
LATB7 LATB6 LATB5 LATB4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 LATB<7:4>: RB<7:4> Port I/O Output Latch Register bits
bit 3-0 Unimplemented: Read as ‘0’
PIC18F/LF1XK50
DS41350E-page 92 Preliminary 2010 Microchip Technology Inc.
TABLE 9-3: PORTB I/O SUMMARY
Pin Function TRIS
Setting I/O I/O
Type Description
RB4/IOCB4/AN10/
SDI/SDA
RB4 0 O DIG LATB<4> data output; not affected by analog input.
1 I TTL PORTB<4> data input; Programmable weak pull-up.
IOCB4 1 I TTL Interrupt-on-pin change.
AN10 1 I ANA ADC input channel 10.
SDI 1 I ST SPI data input (MSSP module).
SDA 1 I DIG I2C™ data output (MSSP module); takes priority over port data.
1 O I2C I2C™ data input (MSSP module); input type depends on module
setting.
RB5/IOCB5/AN11/
RX/DT
RB5 0 O DIG LATB<5> data output.
1 I TTL PORTB<5> data input; Programmable weak pull-up.
IOCB5 1 I TTL Interrupt-on-pin change.
AN11 1 I ANA ADC input channel 11.
RX 1 I ST Asynchronous serial receive data input (USART module).
DT 1 O DIGSynchronous serial data output (USART module); takes priority over
port data.
1 I STSynchronous serial data input (USART module). User must configure
as an input.
RB6/IOCB6/SCK/
SCL
RB6 0 O DIG LATB<6> data output.
1 I TTL PORTB<6> data input; Programmable weak pull-up.
IOCB6 1 I TTL Interrupt-on-pin change.
SCK 0 O DIG SPI clock output (MSSP module); takes priority over port data.
1 I ST SPI clock input (MSSP module).
SCL 0 O DIG I2C™ clock output (MSSP module); takes priority over port data.
1 I I2C I2C™ clock input (MSSP module); input type depends on module
setting.
RB7/IOCB7/TX/CK RB7 0 O DIG LATB<7> data output.
1 I TTL PORTB<7> data input; Programmable weak pull-up.
IOCB7 1 I TTL Interrupt-on-pin change.
TX 1 O DIGAsynchronous serial transmit data output (USART module); takes
priority over port data. User must configure as output.
CK 1 O DIGSynchronous serial clock output (USART module); takes priority over
port data.
1 I ST Synchronous serial clock input (USART module).
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
2010 Microchip Technology Inc. Preliminary DS41350E-page 93
PIC18F/LF1XK50
TABLE 9-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTB RB7 RB6 RB5 RB4 — — — — 288
LATB LATB7 LATB6 LATB5 LATB4 — — — — 288
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 288
WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 288
IOCB IOCB7 IOCB6 IOCB5 IOCB4 288
SLRCON — — — — — SLRC SLRB SLRA 288
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
INTCON2 RABPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP 285
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 288
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 286
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
PIC18F/LF1XK50
DS41350E-page 94 Preliminary 2010 Microchip Technology Inc.
9.3 PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bidirectional port. The corresponding
data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., disable the output driver). Clearing a
TRISC bit (= 0) will make the corresponding PORTC
pin an output (i.e., enable the output driver and put the
contents of the output latch on the selected pin).
The PORTC Data Latch register (LATC) is also
memory mapped. Read-modify-write operations on the
LATC register read and write the latched output value
for PORTC.
All the pins on PORTC are implemented with Schmitt
Trigger input buffer. Each pin is individually configurable
as an input or output.
EXAMPLE 9-3: INITIALIZING PORTC
Note: On a Power-on Reset, RC<7:6> and
RC<3:0> are configured as analog inputs
and read as ‘0’.
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
CLRF LATC ; Alternate method
; to clear output
; data latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
REGISTER 9-11: PORTC: PORTC REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 RC<7:0>: PORTC I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 9-12: TRISC: PORTC TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TRISC<7:0>: PORTC Tri-State Control bit
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
2010 Microchip Technology Inc. Preliminary DS41350E-page 95
PIC18F/LF1XK50
REGISTER 9-13: LATC: PORTC DATA LATCH REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 LATC<7:0>: RB<7:0> Port I/O Output Latch Register bits
PIC18F/LF1XK50
DS41350E-page 96 Preliminary 2010 Microchip Technology Inc.
TABLE 9-14: PORTC I/O SUMMARY
Pin Function TRIS
Setting I/O I/O
Type Description
RC0/AN4/
C12IN+/VREF+/
INT0
RC0 0 O DIG LATC<0> data output.
1 I ST PORTC<0> data input.
AN4 1 I ANA A/D input channel 4.
C12IN+ 1 I ANA Comparators C1 and C2 non-inverting input. Analog select is
shared with ADC.
VREF+ 1 I ANA ADC and comparator voltage reference high input.
INT0 1 I ST External Interrupt 0 input.
RC1/AN5/
C12IN1-/VREF-/
INT1
RC1 0 O DIG LATC<1> data output.
1 I ST PORTC<1> data input.
AN5 1 I ANA A/D input channel 5.
C12IN1- 1 I ANA Comparators C1 and C2 inverting input. Analog select is
shared with ADC.
VREF- 1 I ANA ADC and comparator voltage reference low input.
INT1 1 I ST External Interrupt 1 input.
RC2/AN6/
C12IN2-/CVREF/
P1D/INT2
RC2 0 O DIG LATC<2> data output.
1 I ST PORTC<2> data input.
AN6 1 I ANA A/D input channel 6.
C12IN2- 1 I ANA Comparators C1 and C2 inverting input, channel 2. Analog select is
shared with ADC.
CVREF x O ANA Voltage reference output. Enabling this feature disables digital I/O.
P1D 0 O DIG ECCP1 Enhanced PWM output, channel D. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
INT2 1 I ST External Interrupt 2 input.
RC3/AN7/
C12IN3-/P1C/
PGM
RC3 0 O DIG LATC<3> data output.
1 I ST PORTC<3> data input.
AN7 1 I ANA A/D input channel 7.
C12IN3- 1 I ANA Comparators C1 and C2 inverting input, channel 3. Analog select is
shared with ADC.
P1C 0 O DIG ECCP1 Enhanced PWM output, channel C. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
PGM x I ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP
Configuration bit; all other pin functions disabled.
RC4/C12OUT/
P1B
RC4 0 O DIG LATC<4> data output.
1 I ST PORTC<4> data input.
C12OUT 0 O DIG Comparator 1 and 2 output; takes priority over port data.
P1B 0 O DIG ECCP1 Enhanced PWM output, channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
2010 Microchip Technology Inc. Preliminary DS41350E-page 97
PIC18F/LF1XK50
TABLE 9-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
RC5/CCP1/P1A/
T0CKI
RC5 0 O DIG LATC<5> data output.
1 I ST PORTC<5> data input.
CCP1 0 O DIG ECCP1 compare or PWM output; takes priority over port data.
1 I ST ECCP1 capture input.
P1A 0 0 DIG ECCP1 Enhanced PWM output, channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data
T0CKI 1 I ST Timer0 counter input.
RC6/AN8/SS/
T13CKI/T1OSCI
RC6 0 O DIG LATC<6> data output.
1 I ST PORTC<6> data input.
AN8 1 I ANA A/D input channel 8.
SS 1 I TTL Slave select input for SSP (MSSP module)
T13CKI 1 I ST Timer1 and Timer3 counter input.
T1OSCI x O ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
RC7/AN9/SDO/
T1OSCO
RC7 0 O DIG LATC<7> data output.
1 I ST PORTC<7> data input.
AN9 1 I ANA A/D input channel 9.
SDO 0 I DIG SPI data output (MSSP module); takes priority over port data.
T1OSCO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 288
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 288
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 — — — 288
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 288
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 286
T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 287
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 286
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 287
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 287
PSTRCON — — — STRSYNC STRD STRC STRB STRA 287
SLRCON — — — — — SLRC SLRB SLRA 288
REFCON1 D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 --- D1NSS 287
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
INTCON2 RABPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP 285
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 285
TABLE 9-14: PORTC I/O SUMMARY (CONTINUED)
Pin Function TRIS
Setting I/O I/O
Type Description
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
PIC18F/LF1XK50
DS41350E-page 98 Preliminary 2010 Microchip Technology Inc.
9.4 Port Analog Control
Some port pins are multiplexed with analog functions
such as the Analog-to-Digital Converter and comparators.
When these I/O pins are to be used as analog
inputs it is necessary to disable the digital input buffer
to avoid excessive current caused by improper biasing
of the digital input. Individual control of the digital input
buffers on pins which share analog functions is provided
by the ANSEL and ANSELH registers. Setting an
ANSx bit high will disable the associated digital input
buffer and cause all reads of that pin to return ‘0’ while
allowing analog functions of that pin to operate
correctly.
The state of the ANSx bits has no affect on digital
output functions. A pin with the associated TRISx bit
clear and ANSx bit set will still operate as a digital
output but the Input mode will be analog.
REGISTER 9-15: ANSEL: ANALOG SELECT REGISTER 1
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0
ANS7 ANS6 ANS5 ANS4 ANS3 — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ANS7: RC3 Analog Select Control bit
1 = Digital input buffer of RC3 is disabled
0 = Digital input buffer of RC3 is enabled
bit 6 ANS6: RC2 Analog Select Control bit
1 = Digital input buffer of RC2 is disabled
0 = Digital input buffer of RC2 is enabled
bit 5 ANS5: RC1 Analog Select Control bit
1 = Digital input buffer of RC1 is disabled
0 = Digital input buffer of RC1 is enabled
bit 4 ANS4: RC0 Analog Select Control bit
1 = Digital input buffer of RC0 is disabled
0 = Digital input buffer of RC0 is enabled
bit 3 ANS3: RA4 Analog Select Control bit
1 = Digital input buffer of RA4 is disabled
0 = Digital input buffer of RA4 is enabled
bit 2-0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 99
PIC18F/LF1XK50
REGISTER 9-16: ANSELH: ANALOG SELECT REGISTER 2
U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
— — — — ANS11 ANS10 ANS9 ANS8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3 ANS11: RB5 Analog Select Control bit
1 = Digital input buffer of RB5 is disabled
0 = Digital input buffer of RB5 is enabled
bit 2 ANS10: RB4 Analog Select Control bit
1 = Digital input buffer of RB4 is disabled
0 = Digital input buffer of RB4 is enabled
bit 1 ANS9: RC7 Analog Select Control bit
1 = Digital input buffer of RC7 is disabled
0 = Digital input buffer of RC7 is enabled
bit 0 ANS8: RC6 Analog Select Control bit
1 = Digital input buffer of RC6 is disabled
0 = Digital input buffer of RC6 is enabled
PIC18F/LF1XK50
DS41350E-page 100 Preliminary 2010 Microchip Technology Inc.
9.5 Port Slew Rate Control
The output slew rate of each port is programmable to
select either the standard transition rate or a reduced
transition rate of 0.1 times the standard to minimize
EMI. The reduced transition time is the default slew
rate for all ports.
REGISTER 9-17: SLRCON: SLEW RATE CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1
— — — — — SLRC SLRB SLRA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-3 Unimplemented: Read as ‘0’
bit 2 SLRC: PORTC Slew Rate Control bit
1 = All outputs on PORTC slew at 0.1 times the standard rate
0 = All outputs on PORTC slew at the standard rate
bit 1 SLRB: PORTB Slew Rate Control bit
1 = All outputs on PORTB slew at 0.1 times the standard rate
0 = All outputs on PORTB slew at the standard rate
bit 0 SLRA: PORTA Slew Rate Control bit
1 = All outputs on PORTA slew at 0.1 times the standard rate(1)
0 = All outputs on PORTA slew at the standard rate
Note 1: The slew rate of RA4 defaults to standard rate when the pin is used as CLKOUT.
2010 Microchip Technology Inc. Preliminary DS41350E-page 101
PIC18F/LF1XK50
10.0 TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or counter
in both 8-bit or 16-bit modes
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt-on-overflow
The T0CON register (Register 10-1) controls all
aspects of the module’s operation, including the
prescale selection. It is both readable and writable.
A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 10-1. Figure 10-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
REGISTER 10-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6 T08BIT: Timer0 8-bit/16-bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits
111 = 1:256 prescale value
110 = 1:128 prescale value
101 = 1:64 prescale value
100 = 1:32 prescale value
011 = 1:16 prescale value
010 = 1:8 prescale value
001 = 1:4 prescale value
000 = 1:2 prescale value
PIC18F/LF1XK50
DS41350E-page 102 Preliminary 2010 Microchip Technology Inc.
10.1 Timer0 Operation
Timer0 can operate as either a timer or a counter; the
mode is selected with the T0CS bit of the T0CON
register. In Timer mode (T0CS = 0), the module
increments on every clock by default unless a different
prescaler value is selected (see Section 10.3
“Prescaler”). Timer0 incrementing is inhibited for two
instruction cycles following a TMR0 register write. The
user can work around this by adjusting the value written
to the TMR0 register to compensate for the anticipated
missing increments.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising or falling edge of the T0CKI pin. The incrementing
edge is determined by the Timer0 Source Edge
Select bit, T0SE of the T0CON register; clearing this bit
selects the rising edge. Restrictions on the external
clock input are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements (see
Table 27-6) to ensure that the external clock can be
synchronized with the internal phase clock (TOSC).
There is a delay between synchronization and the
onset of incrementing the timer/counter.
10.2 Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode; it is actually a buffered version of the real high
byte of Timer0 which is neither directly readable nor
writable (refer to Figure 10-2). TMR0H is updated with
the contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without the need to verify that the read of the
high and low byte were valid. Invalid reads could
otherwise occur due to a rollover between successive
reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. Writing
to TMR0H does not directly affect Timer0. Instead, the
high byte of Timer0 is updated with the contents of
TMR0H when a write occurs to TMR0L. This allows all
16 bits of Timer0 to be updated at once.
FIGURE 10-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
T0SE
0
1
0
1
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks
TMR0L
(2 TCY Delay)
PSA Internal Data Bus
T0PS<2:0>
Set
TMR0IF
on Overflow
3 8
8
2010 Microchip Technology Inc. Preliminary DS41350E-page 103
PIC18F/LF1XK50
FIGURE 10-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)
10.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS<2:0> bits of the
T0CON register which determine the prescaler
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When the prescaler is assigned,
prescale values from 1:2 through 1:256 in integer
power-of-2 increments are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
10.3.1 SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
10.4 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register
overflows from FFh to 00h in 8-bit mode, or from
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF flag bit. The interrupt can be masked by clearing
the TMR0IE bit of the INTCON register. Before
re-enabling the interrupt, the TMR0IF bit must be
cleared by software in the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 10-1: REGISTERS ASSOCIATED WITH TIMER0
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
T0SE
0
1
0
1
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks
TMR0L
(2 TCY Delay)
Internal Data Bus
8
PSA
T0PS<2:0>
Set
TMR0IF
on Overflow
3
TMR0
TMR0H
High Byte
8
8
8
Read TMR0L
Write TMR0L
8
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
TMR0L Timer0 Register, Low Byte 286
TMR0H Timer0 Register, High Byte 286
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 286
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
Legend: Shaded cells are not used by Timer0.
Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
PIC18F/LF1XK50
DS41350E-page 104 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 105
PIC18F/LF1XK50
11.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates the
following features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
• Selectable internal or external clock source and
Timer1 oscillator options
• Interrupt-on-overflow
• Reset on CCP Special Event Trigger
• Device clock status flag (T1RUN)
A simplified block diagram of the Timer1 module is
shown in Figure 11-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 11-2.
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
Timer1 is controlled through the T1CON Control
register (Register 11-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON of the T1CON register.
REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of TImer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 6 T1RUN: Timer1 System Clock Status bit
1 = Main system clock is derived from Timer1 oscillator
0 = Main system clock is derived from another source
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from the T13CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
PIC18F/LF1XK50
DS41350E-page 106 Preliminary 2010 Microchip Technology Inc.
11.1 Timer1 Operation
Timer1 can operate in one of the following modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS of the T1CON register. When TMR1CS is
cleared (= 0), Timer1 increments on every internal
instruction cycle (FOSC/4). When the bit is set, Timer1
increments on every rising edge of either the Timer1
external clock input or the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled, the digital
circuitry associated with the T1OSI and T1OSO pins is
disabled. This means the values of TRISC<1:0> are
ignored and the pins are read as ‘0’.
FIGURE 11-1: TIMER1 BLOCK DIAGRAM
FIGURE 11-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T1SYNC
TMR1CS
T1CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
On/Off
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSI/T13CKI
T1OSO
1
0
TMR1ON
TMR1L
Set
TMR1IF
on Overflow
TMR1
Clear TMR1 High Byte
(CCP Special Event Trigger)
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer1
Timer1 Clock Input
T1SYNC
TMR1CS
T1CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSI/T13CKI
T1OSO
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR1L
Internal Data Bus
8
Set
TMR1IF
on Overflow
TMR1
TMR1H
High Byte
8
8
8
Read TMR1L
Write TMR1L
8
TMR1ON
Clear TMR1
(CCP Special Event Trigger)
Timer1 Oscillator
On/Off
Timer1
Timer1 Clock Input
2010 Microchip Technology Inc. Preliminary DS41350E-page 107
PIC18F/LF1XK50
11.2 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 11-2). When the RD16 control bit of the
T1CON register is set, the address for TMR1H is
mapped to a buffer register for the high byte of Timer1.
A read from TMR1L will load the contents of the high
byte of Timer1 into the Timer1 high byte buffer. This
provides the user with the ability to accurately read all
16 bits of Timer1 without the need to determine
whether a read of the high byte, followed by a read of
the low byte, has become invalid due to a rollover or
carry between reads.
Writing to TMR1H does not directly affect Timer1.
Instead, the high byte of Timer1 is updated with the
contents of TMR1H when a write occurs to TMR1L.
This allows all 16 bits of Timer1 to be updated at once.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
11.3 Timer1 Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN of the T1CON register. The
oscillator is a low-power circuit rated for 32 kHz crystals.
It will continue to run during all power-managed modes.
The circuit for a typical LP oscillator is shown in
Figure 11-3. Table 11-1 shows the capacitor selection for
the Timer1 oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 11-3: EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
TABLE 11-1: CAPACITOR SELECTION FOR
THE TIMER OSCILLATOR
11.3.1 USING TIMER1 AS A
CLOCK SOURCE
The Timer1 oscillator is also available as a clock source
in power-managed modes. By setting the clock select
bits, SCS<1:0> of the OSCCON register, to ‘01’, the
device switches to SEC_RUN mode; both the CPU and
peripherals are clocked from the Timer1 oscillator. If the
IDLEN bit of the OSCCON register is cleared and a
SLEEP instruction is executed, the device enters
SEC_IDLE mode. Additional details are available in
Section 19.0 “Power-Managed Modes”.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN of
the T1CON register, is set. This can be used to determine
the controller’s current clocking mode. It can also
indicate which clock source is currently being used by
the Fail-Safe Clock Monitor. If the Clock Monitor is
enabled and the Timer1 oscillator fails while providing
the clock, polling the T1RUN bit will indicate whether
the clock is being provided by the Timer1 oscillator or
another source.
Note: See the Notes with Table 11-1 for additional
information about capacitor selection.
C1
C2
XTAL
T1OSI
T1OSO
32.768 kHz
27 pF
27 pF
PIC® MCU
Osc Type Freq C1 C2
LP 32 kHz 27 pF(1) 27 pF(1)
Note 1: Microchip suggests these values only as
a starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Capacitor values are for design guidance
only.
PIC18F/LF1XK50
DS41350E-page 108 Preliminary 2010 Microchip Technology Inc.
11.3.2 TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 11-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-speed circuit must be located near the oscillator
(such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 11-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
FIGURE 11-4: OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
11.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow,
which is latched in the TMR1IF interrupt flag bit of the
PIR1 register. This interrupt can be enabled or disabled
by setting or clearing the TMR1IE Interrupt Enable bit
of the PIE1 register.
11.5 Resetting Timer1 Using the CCP
Special Event Trigger
If either of the CCP modules is configured to use Timer1
and generate a Special Event Trigger in Compare mode
(CCP1M<3:0> or CCP2M<3:0> = 1011), this signal will
reset Timer1. The trigger from CCP2 will also start an
A/D conversion if the A/D module is enabled (see
Section 14.3.4 “Special Event Trigger” for more
information).
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRH:CCPRL register pair
effectively becomes a period register for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special Event Trigger, the write operation will take
precedence.
VDD
OSC1
VSS
OSC2
RC0
RC1
RC2
Note: Not drawn to scale.
Note: The Special Event Triggers from the
CCP2 module will not set the TMR1IF
interrupt flag bit of the PIR1 register.
2010 Microchip Technology Inc. Preliminary DS41350E-page 109
PIC18F/LF1XK50
11.6 Using Timer1 as a Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 11.3 “Timer1 Oscillator”
above) gives users the option to include RTC functionality
to their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
The application code routine, RTCisr, shown in
Example 11-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine, which increments the seconds counter by
one; additional counters for minutes and hours are
incremented on overflows of the less significant
counters.
Since the register pair is 16 bits wide, a 32.768 kHz
clock source will take 2 seconds to count up to overflow.
To force the overflow at the required one-second
intervals, it is necessary to preload it; the simplest
method is to set the MSb of TMR1H with a BSF instruction.
Note that the TMR1L register is never preloaded
or altered; doing so may introduce cumulative error
over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
EXAMPLE 11-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW 80h ; Preload TMR1 register pair
MOVWF TMR1H ; for 1 second overflow
CLRF TMR1L
MOVLW b’00001111’ ; Configure for external clock,
MOVWF T1CON ; Asynchronous operation, external oscillator
CLRF secs ; Initialize timekeeping registers
CLRF mins ;
MOVLW .12
MOVWF hours
BSF PIE1, TMR1IE ; Enable Timer1 interrupt
RETURN
RTCisr
BSF TMR1H, 7 ; Preload for 1 sec overflow
BCF PIR1, TMR1IF ; Clear interrupt flag
INCF secs, F ; Increment seconds
MOVLW .59 ; 60 seconds elapsed?
CPFSGT secs
RETURN ; No, done
CLRF secs ; Clear seconds
INCF mins, F ; Increment minutes
MOVLW .59 ; 60 minutes elapsed?
CPFSGT mins
RETURN ; No, done
CLRF mins ; clear minutes
INCF hours, F ; Increment hours
MOVLW .23 ; 24 hours elapsed?
CPFSGT hours
RETURN ; No, done
CLRF hours ; Reset hours
RETURN ; Done
PIC18F/LF1XK50
DS41350E-page 110 Preliminary 2010 Microchip Technology Inc.
TABLE 11-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
TMR1L Timer1 Register, Low Byte 286
TMR1H Timer1 Register, High Byte 286
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 286
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 288
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 286
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
2010 Microchip Technology Inc. Preliminary DS41350E-page 111
PIC18F/LF1XK50
12.0 TIMER2 MODULE
The Timer2 module timer incorporates the following
features:
• 8-bit timer and period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4 and
1:16)
• Software programmable postscaler (1:1 through
1:16)
• Interrupt on TMR2-to-PR2 match
• Optional use as the shift clock for the MSSP
module
The module is controlled through the T2CON register
(Register 12-1), which enables or disables the timer
and configures the prescaler and postscaler. Timer2
can be shut off by clearing control bit, TMR2ON of the
T2CON register, to minimize power consumption.
A simplified block diagram of the module is shown in
Figure 12-1.
12.1 Timer2 Operation
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 4-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and
divide-by-16 prescale options; these are selected by
the prescaler control bits, T2CKPS<1:0> of the T2CON
register. The value of TMR2 is compared to that of the
period register, PR2, on each clock cycle. When the
two values match, the comparator generates a match
signal as the timer output. This signal also resets the
value of TMR2 to 00h on the next cycle and drives the
output counter/postscaler (see Section 12.2 “Timer2
Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 12-1: T2CON: TIMER2 CONTROL REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
PIC18F/LF1XK50
DS41350E-page 112 Preliminary 2010 Microchip Technology Inc.
12.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match) provides
the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF of the PIR1 register. The
interrupt is enabled by setting the TMR2 Match Interrupt
Enable bit, TMR2IE of the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> of the T2CON register.
12.3 Timer2 Output
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode. Additional
information is provided in Section 14.0 “Master
Synchronous Serial Port (MSSP) Module”.
FIGURE 12-1: TIMER2 BLOCK DIAGRAM
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
TMR2 Timer2 Register 286
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 286
PR2 Timer2 Period Register 286
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Comparator
TMR2 Output
TMR2
Postscaler
Prescaler
PR2
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
4
T2OUTPS<3:0>
T2CKPS<1:0>
Set TMR2IF
Internal Data Bus
8
Reset
TMR2/PR2
8 8
(to PWM or MSSP)
Match
2010 Microchip Technology Inc. Preliminary DS41350E-page 113
PIC18F/LF1XK50
13.0 TIMER3 MODULE
The Timer3 module timer/counter incorporates these
features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
• Module Reset on CCP Special Event Trigger
A simplified block diagram of the Timer3 module is
shown in Figure 13-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 13-2.
The Timer3 module is controlled through the T3CON
register (Register 13-1). It also selects the clock source
options for the CCP modules (see Section 14.1.1
“CCP Module and Timer Resources” for more
information).
REGISTER 13-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
bit 6 Unimplemented: Read as ‘0’
bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T3CCP1: Timer3 and Timer1 to CCP1 Enable bits
1 = Timer3 is the clock source for compare/capture of ECCP1
0 = Timer1 is the clock source for compare/capture of ECCP1
bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1 TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first
falling edge)
0 = Internal clock (FOSC/4)
bit 0 TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
PIC18F/LF1XK50
DS41350E-page 114 Preliminary 2010 Microchip Technology Inc.
13.1 Timer3 Operation
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS of the T3CON register. When TMR3CS is
cleared (= 0), Timer3 increments on every internal
instruction cycle (FOSC/4). When the bit is set, Timer3
increments on every rising edge of the Timer1 external
clock input or the Timer1 oscillator, if enabled.
As with Timer1, the digital circuitry associated with the
RC1/T1OSI and RC0/T1OSO/T13CKI pins is disabled
when the Timer1 oscillator is enabled. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
FIGURE 13-1: TIMER3 BLOCK DIAGRAM
T3SYNC
TMR3CS
T3CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSO/T13CKI
T1OSI
1
0
TMR3ON
TMR3L
Set
TMR3IF
on Overflow
TMR3
High Byte
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer3
CCP1 Special Event Trigger
CCP1 Select from T3CON<3>
Clear TMR3
Timer1 Clock Input
2010 Microchip Technology Inc. Preliminary DS41350E-page 115
PIC18F/LF1XK50
FIGURE 13-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
13.2 Timer3 16-Bit Read/Write Mode
Timer3 can be configured for 16-bit reads and writes
(see Figure 13-2). When the RD16 control bit of the
T3CON register is set, the address for TMR3H is
mapped to a buffer register for the high byte of Timer3.
A read from TMR3L will load the contents of the high
byte of Timer3 into the Timer3 High Byte Buffer register.
This provides the user with the ability to accurately read
all 16 bits of Timer1 without having to determine
whether a read of the high byte, followed by a read of
the low byte, has become invalid due to a rollover
between reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
13.3 Using the Timer1 Oscillator as the
Timer3 Clock Source
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN bit of the T1CON register. To use
it as the Timer3 clock source, the TMR3CS bit must
also be set. As previously noted, this also configures
Timer3 to increment on every rising edge of the
oscillator source.
The Timer1 oscillator is described in Section 11.0
“Timer1 Module”.
13.4 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF of the PIR2
register. This interrupt can be enabled or disabled by
setting or clearing the Timer3 Interrupt Enable bit,
TMR3IE of the PIE2 register.
T3SYNC
TMR3CS
T3CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T13CKI/T1OSI
T1OSO
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR3L
Internal Data Bus
8
Set
TMR3IF
on Overflow
TMR3
TMR3H
High Byte
8
8
8
Read TMR1L
Write TMR1L
8
TMR3ON
CCP1 Special Event Trigger
Timer1 Oscillator
On/Off
Timer3
Timer1 Clock Input
CCP1 Select from T3CON<3>
Clear TMR3
PIC18F/LF1XK50
DS41350E-page 116 Preliminary 2010 Microchip Technology Inc.
13.5 Resetting Timer3 Using the CCP
Special Event Trigger
If CCP1 module is configured to use Timer3 and to generate
a Special Event Trigger in Compare mode
(CCP1M<3:0>), this signal will reset Timer3. It will also
start an A/D conversion if the A/D module is enabled
(see Section 17.2.8 “Special Event Trigger” for more
information).
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPR1H:CCPR1L register
pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from a CCP module, the write will
take precedence.
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF CCP2IF 288
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE CCP2IE 288
IPR2 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP CCP2IP 288
TMR3L Timer3 Register, Low Byte 287
TMR3H Timer3 Register, High Byte 287
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 286
T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 287
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 288
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
2010 Microchip Technology Inc. Preliminary DS41350E-page 117
PIC18F/LF1XK50
14.0 ENHANCED
CAPTURE/COMPARE/PWM
(ECCP) MODULE
PIC18F/LF1XK50 devices have one ECCP
(Capture/Compare/PWM) module. The module
contains a 16-bit register which can operate as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Slave Duty Cycle register.
CCP1 is implemented as a standard CCP module with
enhanced PWM capabilities. These include:
• Provision for 2 or 4 output channels
• Output steering
• Programmable polarity
• Programmable dead-band control
• Automatic shutdown and restart.
The enhanced features are discussed in detail in
Section 14.4 “PWM (Enhanced Mode)”.
REGISTER 14-1: CCP1CON: ENHANCED CAPTURE/COMPARE/PWM CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 P1M<1:0>: Enhanced PWM Output Configuration bits
If CCP1M<3:2> = 00, 01, 10:
xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins
If CCP1M<3:2> = 11:
00 = Single output: P1A, P1B, P1C and P1D controlled by steering (See Section 14.4.7 “Pulse Steering
Mode”).
01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins
11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
bit 5-4 DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in
CCPR1L.
bit 3-0 CCP1M<3:0>: Enhanced CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Reserved
0010 = Compare mode, toggle output on match
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF)
1001 = Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF)
1010 = Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state
1011 = Compare mode, trigger special event (ECCP resets TMR1 or TMR3, start A/D conversion, sets
CC1IF bit)
1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low
PIC18F/LF1XK50
DS41350E-page 118 Preliminary 2010 Microchip Technology Inc.
In addition to the expanded range of modes available
through the CCP1CON register and ECCP1AS
register, the ECCP module has two additional registers
associated with Enhanced PWM operation and
auto-shutdown features. They are:
• PWM1CON (Dead-band delay)
• PSTRCON (output steering)
14.1 ECCP Outputs and Configuration
The enhanced CCP module may have up to four PWM
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTC. The outputs that
are active depend on the CCP operating mode
selected. The pin assignments are summarized in
Table 14-2.
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting the P1M<1:0>
and CCP1M<3:0> bits. The appropriate TRISC
direction bits for the port pins must also be set as
outputs.
14.1.1 CCP MODULE AND TIMER
RESOURCES
The CCP modules utilize Timers 1, 2 or 3, depending
on the mode selected. Timer1 and Timer3 are available
to modules in Capture or Compare modes, while
Timer2 is available for modules in PWM mode.
TABLE 14-1: CCP MODE – TIMER
RESOURCE
The assignment of a particular timer to a module is
determined by the Timer-to-CCP enable bits in the
T3CON register (Register 13-1). The interactions
between the two modules are summarized in
Figure 14-1. In Asynchronous Counter mode, the
capture operation will not work reliably.
CCP/ECCP Mode Timer Resource
Capture Timer1 or Timer3
Compare Timer1 or Timer3
PWM Timer2
2010 Microchip Technology Inc. Preliminary DS41350E-page 119
PIC18F/LF1XK50
14.2 Capture Mode
In Capture mode, the CCPR1H:CCPR1L register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
CCP1 pin. An event is defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCP1M<3:0> of the CCP1CON register. When a capture
is made, the interrupt request flag bit, CCP1IF, is
set; it must be cleared by software. If another capture
occurs before the value in register CCPR1 is read, the
old captured value is overwritten by the new captured
value.
14.2.1 CCP PIN CONFIGURATION
In Capture mode, the appropriate CCP1 pin should be
configured as an input by setting the corresponding
TRIS direction bit.
14.2.2 TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer to
be used with each CCP module is selected in the T3CON
register (see Section 14.1.1 “CCP Module and Timer
Resources”).
14.2.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE interrupt enable bit clear to avoid false interrupts.
The interrupt flag bit, CCP1IF, should also be
cleared following any such change in operating mode.
14.2.4 CCP PRESCALER
There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCP1M<3:0>). Whenever the
CCP module is turned off or Capture mode is disabled,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 14-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 14-1: CHANGING BETWEEN
CAPTURE PRESCALERS
FIGURE 14-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
Note: If the CCP1 pin is configured as an output,
a write to the port can cause a capture
condition.
CLRF CCP1CON ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF CCP1CON ; Load CCP1CON with
; this value
CCPR1H CCPR1L
TMR1H TMR1L
Set CCP1IF
TMR3
Enable
Q1:Q4
CCP1CON<3:0>
CCP1 pin
Prescaler
1, 4, 16
and
Edge Detect
TMR1
Enable
T3CCP1
T3CCP1
TMR3H TMR3L
4
4
PIC18F/LF1XK50
DS41350E-page 120 Preliminary 2010 Microchip Technology Inc.
14.3 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP1
pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (CCP1M<3:0>). At the same time, the interrupt
flag bit, CCP1IF, is set.
14.3.1 CCP PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the appropriate TRIS bit.
14.3.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation will not work reliably.
14.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 pin is not affected.
Only the CCP1IF interrupt flag is affected.
14.3.4 SPECIAL EVENT TRIGGER
The CCP module is equipped with a Special Event Trigger.
This is an internal hardware signal generated in
Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCP1M<3:0> = 1011).
The Special Event Trigger resets the timer register pair
for whichever timer resource is currently assigned as the
module’s time base. This allows the CCPR1 registers to
serve as a programmable period register for either timer.
The Special Event Trigger can also start an A/D conversion.
In order to do this, the A/D converter must already
be enabled.
FIGURE 14-2: COMPARE MODE OPERATION BLOCK DIAGRAM
Note: Clearing the CCP1CON register will force
the CCP1 compare output latch (depending
on device configuration) to the default
low level. This is not the PORTC I/O data
latch.
TMR1H TMR1L
TMR3H TMR3L
CCPR1H CCPR1L
Comparator
T3CCP1
Set CCP1IF
1
0
S Q
R
Output
Logic
Special Event Trigger
CCP1 pin
TRIS
CCP1CON<3:0>
4 Output Enable
(Timer1/Timer3 Reset, A/D Trigger)
Compare
Match
2010 Microchip Technology Inc. Preliminary DS41350E-page 121
PIC18F/LF1XK50
14.4 PWM (Enhanced Mode)
The Enhanced PWM Mode can generate a PWM signal
on up to four different output pins with up to 10-bits of
resolution. It can do this through four different PWM
output modes:
• Single PWM
• Half-Bridge PWM
• Full-Bridge PWM, Forward mode
• Full-Bridge PWM, Reverse mode
To select an Enhanced PWM mode, the P1M bits of the
CCP1CON register must be set appropriately.
The PWM outputs are multiplexed with I/O pins and are
designated P1A, P1B, P1C and P1D. The polarity of the
PWM pins is configurable and is selected by setting the
CCP1M bits in the CCP1CON register appropriately.
Table 14-1 shows the pin assignments for each
Enhanced PWM mode.
Figure 14-3 shows an example of a simplified block
diagram of the Enhanced PWM module.
FIGURE 14-3: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
TABLE 14-2: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
Note: To prevent the generation of an
incomplete waveform when the PWM is
first enabled, the ECCP module waits until
the start of a new PWM period before
generating a PWM signal.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(1)
R Q
S
Duty Cycle Registers
DC1B<1:0>
Clear Timer2,
toggle PWM pin and
latch duty cycle
Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit
time base.
TRIS
CCP1/P1A
TRIS
P1B
TRIS
P1C
TRIS
P1D
Output
Controller
P1M<1:0>
2
CCP1M<3:0>
4
PWM1CON
CCP1/P1A
P1B
P1C
P1D
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
ECCP Mode P1M<1:0> CCP1/P1A P1B P1C P1D
Single 00 Yes(1) Yes(1) Yes(1) Yes(1)
Half-Bridge 10 Yes Yes No No
Full-Bridge, Forward 01 Yes Yes Yes Yes
Full-Bridge, Reverse 11 Yes Yes Yes Yes
Note 1: Outputs are enabled by pulse steering in Single mode. See Register 14-4.
PIC18F/LF1XK50
DS41350E-page 122 Preliminary 2010 Microchip Technology Inc.
FIGURE 14-4: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH
STATE)
0
Period
00
10
01
11
Signal
PR2+1
P1M<1:0>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Pulse
Width
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 14.4.6 “Programmable Dead-Band Delay
mode”).
2010 Microchip Technology Inc. Preliminary DS41350E-page 123
PIC18F/LF1XK50
FIGURE 14-5: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0
Period
00
10
01
11
Signal
PR2+1
P1M<1:0>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Pulse
Width
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 14.4.6 “Programmable Dead-Band Delay
mode”).
PIC18F/LF1XK50
DS41350E-page 124 Preliminary 2010 Microchip Technology Inc.
14.4.1 HALF-BRIDGE MODE
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the CCP1/P1A pin, while the complementary PWM
output signal is output on the P1B pin (see
Figure 14-6). This mode can be used for Half-Bridge
applications, as shown in Figure 14-7, or for Full-Bridge
applications, where four power switches are being
modulated with two PWM signals.
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in
Half-Bridge power devices. The value of the PDC<6:0>
bits of the PWM1CON register sets the number of
instruction cycles before the output is driven active. If the
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. See
Section 14.4.6 “Programmable Dead-Band Delay
mode” for more details of the dead-band delay
operations.
Since the P1A and P1B outputs are multiplexed with
the PORT data latches, the associated TRIS bits must
be cleared to configure P1A and P1B as outputs.
FIGURE 14-6: EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
FIGURE 14-7: EXAMPLE OF HALF-BRIDGE APPLICATIONS
Period
Pulse Width
td
td
(1)
P1A(2)
P1B(2)
td = Dead-Band Delay
Period
(1) (1)
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
P1A
P1B
FET
Driver
FET
Driver
Load
+
-
+
-
FET
Driver
FET
Driver
V+
Load
FET
Driver
FET
Driver
P1A
P1B
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
2010 Microchip Technology Inc. Preliminary DS41350E-page 125
PIC18F/LF1XK50
14.4.2 FULL-BRIDGE MODE
In Full-Bridge mode, all four pins are used as outputs.
An example of Full-Bridge application is shown in
Figure 14-8.
In the Forward mode, pin CCP1/P1A is driven to its
active state, pin P1D is modulated, while P1B and P1C
will be driven to their inactive state as shown in
Figure 14-9.
In the Reverse mode, P1C is driven to its active state,
pin P1B is modulated, while P1A and P1D will be driven
to their inactive state as shown Figure 14-9.
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORT data latches. The associated TRIS bits must
be cleared to configure the P1A, P1B, P1C and P1D
pins as outputs.
FIGURE 14-8: EXAMPLE OF FULL-BRIDGE APPLICATION
P1A
P1C
FET
Driver
FET
Driver
V+
VLoad
FET
Driver
FET
Driver
P1B
P1D
QA
QB QD
QC
PIC18F/LF1XK50
DS41350E-page 126 Preliminary 2010 Microchip Technology Inc.
FIGURE 14-9: EXAMPLE OF FULL-BRIDGE PWM OUTPUT
Period
Pulse Width
P1A(2)
P1B(2)
P1C(2)
P1D(2)
Forward Mode
(1)
Period
Pulse Width
P1A(2)
P1C(2)
P1D(2)
P1B(2)
Reverse Mode
(1)
(1) (1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signal is shown as active-high.
2010 Microchip Technology Inc. Preliminary DS41350E-page 127
PIC18F/LF1XK50
14.4.2.1 Direction Change in Full-Bridge
Mode
In the Full-Bridge mode, the P1M1 bit in the CCP1CON
register allows users to control the forward/reverse
direction. When the application firmware changes this
direction control bit, the module will change to the new
direction on the next PWM cycle.
A direction change is initiated in software by changing
the P1M1 bit of the CCP1CON register. The following
sequence occurs prior to the end of the current PWM
period:
• The modulated outputs (P1B and P1D) are placed
in their inactive state.
• The associated unmodulated outputs (P1A and
P1C) are switched to drive in the opposite
direction.
• PWM modulation resumes at the beginning of the
next period.
See Figure 14-10 for an illustration of this sequence.
The Full-Bridge mode does not provide dead-band
delay. As one output is modulated at a time, dead-band
delay is generally not required. There is a situation
where dead-band delay is required. This situation
occurs when both of the following conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn off time of the power switch, including
the power device and driver circuit, is greater
than the turn on time.
Figure 14-11 shows an example of the PWM direction
changing from forward to reverse, at a near 100% duty
cycle. In this example, at time t1, the output P1A and
P1D become inactive, while output P1C becomes
active. Since the turn off time of the power devices is
longer than the turn on time, a shoot-through current
will flow through power devices QC and QD (see
Figure 14-8) for the duration of ‘t’. The same
phenomenon will occur to power devices QA and QB
for PWM direction change from reverse to forward.
If changing PWM direction at high duty cycle is required
for an application, two possible solutions for eliminating
the shoot-through current are:
1. Reduce PWM duty cycle for one PWM period
before changing directions.
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
FIGURE 14-10: EXAMPLE OF PWM DIRECTION CHANGE
Pulse Width
Period(1)
Signal
Note 1: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle.
Period
P1A (Active-High)
P1B (Active-High)
P1C (Active-High)
P1D (Active-High)
Pulse Width
PIC18F/LF1XK50
DS41350E-page 128 Preliminary 2010 Microchip Technology Inc.
FIGURE 14-11: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
14.4.3 START-UP CONSIDERATIONS
When any PWM mode is used, the application
hardware must use the proper external pull-up and/or
pull-down resistors on the PWM output pins.
The CCP1M<1:0> bits of the CCP1CON register allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output pins
(P1A/P1C and P1B/P1D). The PWM output polarities
must be selected before the PWM pin output drivers are
enabled. Changing the polarity configuration while the
PWM pin output drivers are enable is not recommended
since it may result in damage to the application circuits.
The P1A, P1B, P1C and P1D output latches may not be
in the proper states when the PWM module is
initialized. Enabling the PWM pin output drivers at the
same time as the Enhanced PWM modes may cause
damage to the application circuit. The Enhanced PWM
modes must be enabled in the proper Output mode and
complete a full PWM cycle before enabling the PWM
pin output drivers. The completion of a full PWM cycle
is indicated by the TMR2IF bit of the PIR1 register
being set as the second PWM period begins.
Forward Period Reverse Period
P1A
TON
TOFF
T = TOFF – TON
P1B
P1C
P1D
External Switch D
Potential
Shoot-Through Current
Note 1: All signals are shown as active-high.
2: TON is the turn on delay of power switch QC and its driver.
3: TOFF is the turn off delay of power switch QD and its driver.
External Switch C
t1
PW
PW
Note: When the microcontroller is released from
Reset, all of the I/O pins are in the
high-impedance state. The external circuits
must keep the power switch devices
in the Off state until the microcontroller
drives the I/O pins with the proper signal
levels or activates the PWM output(s).
2010 Microchip Technology Inc. Preliminary DS41350E-page 129
PIC18F/LF1XK50
14.4.4 ENHANCED PWM
AUTO-SHUTDOWN MODE
The PWM mode supports an Auto-Shutdown mode that
will disable the PWM outputs when an external
shutdown event occurs. Auto-Shutdown mode places
the PWM output pins into a predetermined state. This
mode is used to help prevent the PWM from damaging
the application.
The auto-shutdown sources are selected using the
ECCPAS<2:0> bits of the ECCPAS register. A shutdown
event may be generated by:
• A logic ‘0’ on the INT0 pin
• A logic ‘1’ on a comparator (Cx) output
A shutdown condition is indicated by the ECCPASE
(Auto-Shutdown Event Status) bit of the ECCPAS
register. If the bit is a ‘0’, the PWM pins are operating
normally. If the bit is a ‘1’, the PWM outputs are in the
shutdown state.
When a shutdown event occurs, two things happen:
The ECCPASE bit is set to ‘1’. The ECCPASE will
remain set until cleared in firmware or an auto-restart
occurs (see Section 14.4.5 “Auto-Restart Mode”).
The enabled PWM pins are asynchronously placed in
their shutdown states. The PWM output pins are
grouped into pairs [P1A/P1C] and [P1B/P1D]. The state
of each pin pair is determined by the PSSAC and
PSSBD bits of the ECCPAS register. Each pin pair may
be placed into one of three states:
• Drive logic ‘1’
• Drive logic ‘0’
• Tri-state (high-impedance)
REGISTER 14-2: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit
1 = A shutdown event has occurred; ECCP outputs are in shutdown state
0 = ECCP outputs are operating
bit 6-4 ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits
000 = Auto-Shutdown is disabled
001 = Comparator C1OUT output is high
010 = Comparator C2OUT output is high
011 = Either Comparator C1OUT or C2OUT is high
100 = VIL on INT0 pin
101 = VIL on INT0 pin or Comparator C1OUT output is high
110 = VIL on INT0 pin or Comparator C2OUT output is high
111 = VIL on INT0 pin or Comparator C1OUT or Comparator C2OUT is high
bit 3-2 PSSACn: Pins P1A and P1C Shutdown State Control bits
00 = Drive pins P1A and P1C to ‘0’
01 = Drive pins P1A and P1C to ‘1’
1x = Pins P1A and P1C tri-state
bit 1-0 PSSBDn: Pins P1B and P1D Shutdown State Control bits
00 = Drive pins P1B and P1D to ‘0’
01 = Drive pins P1B and P1D to ‘1’
1x = Pins P1B and P1D tri-state
PIC18F/LF1XK50
DS41350E-page 130 Preliminary 2010 Microchip Technology Inc.
FIGURE 14-12: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0)
Note 1: The auto-shutdown condition is a
level-based signal, not an edge-based
signal. As long as the level is present, the
auto-shutdown will persist.
2: Writing to the ECCPASE bit is disabled
while an auto-shutdown condition
persists.
3: Once the auto-shutdown condition has
been removed and the PWM restarted
(either through firmware or auto-restart)
the PWM signal will always restart at the
beginning of the next PWM period.
4: Prior to an auto-shutdown event caused
by a comparator output or INT pin event,
a software shutdown can be triggered in
firmware by setting the CCPxASE bit to a
‘1’. The auto-restart feature tracks the
active status of a shutdown caused by a
comparator output or INT pin event only
so, if it is enabled at this time. It will immediately
clear this bit and restart the ECCP
module at the beginning of the next PWM
period.
Shutdown
PWM
ECCPASE bit
Activity
Event
Shutdown
Event Occurs
Shutdown
Event Clears
PWM
Resumes
Normal PWM
Start of
PWM Period
ECCPASE
Cleared by
Firmware
PWM Period
2010 Microchip Technology Inc. Preliminary DS41350E-page 131
PIC18F/LF1XK50
14.4.5 AUTO-RESTART MODE
The Enhanced PWM can be configured to automatically
restart the PWM signal once the auto-shutdown
condition has been removed. Auto-restart is enabled by
setting the PRSEN bit in the PWM1CON register.
If auto-restart is enabled, the ECCPASE bit will remain
set as long as the auto-shutdown condition is active.
When the auto-shutdown condition is removed, the
ECCPASE bit will be cleared via hardware and normal
operation will resume.
FIGURE 14-13: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1)
Shutdown
PWM
ECCPASE bit
Activity
Event
Shutdown
Event Occurs
Shutdown
Event Clears
PWM
Resumes
Normal PWM
Start of
PWM Period
PWM Period
PIC18F/LF1XK50
DS41350E-page 132 Preliminary 2010 Microchip Technology Inc.
14.4.6 PROGRAMMABLE DEAD-BAND
DELAY MODE
In Half-Bridge applications where all power switches
are modulated at the PWM frequency, the power
switches normally require more time to turn off than to
turn on. If both the upper and lower power switches are
switched at the same time (one turned on, and the
other turned off), both switches may be on for a short
period of time until one switch completely turns off.
During this brief interval, a very high current
(shoot-through current) will flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from
flowing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
In Half-Bridge mode, a digitally programmable
dead-band delay is available to avoid shoot-through
current from destroying the bridge power switches. The
delay occurs at the signal transition from the non-active
state to the active state. See Figure 14-14 for
illustration. The lower seven bits of the associated
PWM1CON register (Register 14-3) sets the delay
period in terms of microcontroller instruction cycles
(TCY or 4 TOSC).
FIGURE 14-14: EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
FIGURE 14-15: EXAMPLE OF HALF-BRIDGE APPLICATIONS
Period
Pulse Width
td
td
(1)
P1A(2)
P1B(2)
td = Dead-Band Delay
Period
(1) (1)
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
P1A
P1B
FET
Driver
FET
Driver
V+
VLoad
+
V-
+
VStandard
Half-Bridge Circuit (“Push-Pull”)
2010 Microchip Technology Inc. Preliminary DS41350E-page 133
PIC18F/LF1XK50
REGISTER 14-3: PWM1CON: ENHANCED PWM CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes
away; the PWM restarts automatically
0 = Upon auto-shutdown, ECCPASE must be cleared by software to restart the PWM
bit 6-0 PDC<6:0>: PWM Delay Count bits
PDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal
should transition active and the actual time it transitions active
PIC18F/LF1XK50
DS41350E-page 134 Preliminary 2010 Microchip Technology Inc.
14.4.7 PULSE STEERING MODE
In Single Output mode, pulse steering allows any of the
PWM pins to be the modulated signal. Additionally, the
same PWM signal can be simultaneously available on
multiple pins.
Once the Single Output mode is selected
(CCP1M<3:2> = 11 and P1M<1:0> = 00 of the
CCP1CON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STR bits of the
PSTRCON register, as shown in Table 14-2.
While the PWM Steering mode is active, CCP1M<1:0>
bits of the CCP1CON register select the PWM output
polarity for the P1 pins.
The PWM auto-shutdown operation also applies to
PWM Steering mode as described in Section 14.4.4
“Enhanced PWM Auto-shutdown mode”. An
auto-shutdown event will only affect pins that have
PWM outputs enabled.
Note: The associated TRIS bits must be set to
output (‘0’) to enable the pin output driver
in order to see the PWM signal on the pin.
REGISTER 14-4: PSTRCON: PULSE STEERING CONTROL REGISTER(1)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
— — — STRSYNC STRD STRC STRB STRA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 STRSYNC: Steering Sync bit
1 = Output steering update occurs on next PWM period
0 = Output steering update occurs at the beginning of the instruction cycle boundary
bit 3 STRD: Steering Enable bit D
1 = P1D pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1D pin is assigned to port pin
bit 2 STRC: Steering Enable bit C
1 = P1C pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1C pin is assigned to port pin
bit 1 STRB: Steering Enable bit B
1 = P1B pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1B pin is assigned to port pin
bit 0 STRA: Steering Enable bit A
1 = P1A pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1A pin is assigned to port pin
Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> = 11 and
P1M<1:0> = 00.
2010 Microchip Technology Inc. Preliminary DS41350E-page 135
PIC18F/LF1XK50
FIGURE 14-16: SIMPLIFIED STEERING
BLOCK DIAGRAM
1
0 TRIS
P1A pin
PORT Data
P1A Signal
STRA
1
0
TRIS
P1B pin
PORT Data
STRB
1
0
TRIS
P1C pin
PORT Data
STRC
1
0
TRIS
P1D pin
PORT Data
STRD
Note 1: Port outputs are configured as shown when
the CCP1CON register bits P1M<1:0> = 00
and CCP1M<3:2> = 11.
2: Single PWM output requires setting at least
one of the STRx bits.
CCP1M1
CCP1M0
CCP1M1
CCP1M0
PIC18F/LF1XK50
DS41350E-page 136 Preliminary 2010 Microchip Technology Inc.
14.4.7.1 Steering Synchronization
The STRSYNC bit of the PSTRCON register gives the
user two selections of when the steering event will
happen. When the STRSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that
writes to the PSTRCON register. In this case, the
output signal at the P1 pins may be an
incomplete PWM waveform. This operation is useful
when the user firmware needs to immediately remove
a PWM signal from the pin.
When the STRSYNC bit is ‘1’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
Figures 14-17 and 14-18 illustrate the timing diagrams
of the PWM steering depending on the STRSYNC
setting.
FIGURE 14-17: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)
FIGURE 14-18: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION
(STRSYNC = 1)
PWM
P1n = PWM
STRn
P1 PORT Data
PWM Period
PORT Data
PWM
PORT Data
P1n = PWM
STRn
P1 PORT Data
2010 Microchip Technology Inc. Preliminary DS41350E-page 137
PIC18F/LF1XK50
14.4.8 OPERATION IN POWER-MANAGED
MODES
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCP pin is driving a value, it will continue
to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from HFINTOSC
and the postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP module without change. In all other
power-managed modes, the selected power-managed
mode clock will clock Timer2. Other power-managed
mode clocks will most likely be different than the
primary clock frequency.
14.4.8.1 Operation with Fail-Safe
Clock Monitor
If the Fail-Safe Clock Monitor is enabled, a clock failure
will force the device into the RC_RUN Power-Managed
mode and the OSCFIF bit of the PIR2 register will be
set. The ECCP will then be clocked from the internal
oscillator clock source, which may have a different
clock frequency than the primary clock.
See the previous section for additional details.
14.4.9 EFFECTS OF A RESET
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the CCP registers to their
Reset states.
This forces the enhanced CCP module to reset to a
state compatible with the standard CCP module.
PIC18F/LF1XK50
DS41350E-page 138 Preliminary 2010 Microchip Technology Inc.
TABLE 14-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
RCON IPEN SBOREN — RI TO PD POR BOR 284
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF — 288
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE — 288
IPR2 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP — 288
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
TMR1L Timer1 Register, Low Byte 286
TMR1H Timer1 Register, High Byte 286
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 286
TMR2 Timer2 Register 286
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 286
PR2 Timer2 Period Register 286
TMR3L Timer3 Register, Low Byte 287
TMR3H Timer3 Register, High Byte 287
T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 287
CCPR1L Capture/Compare/PWM Register 1, Low Byte 287
CCPR1H Capture/Compare/PWM Register 1, High Byte 287
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 287
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 287
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 287
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
2010 Microchip Technology Inc. Preliminary DS41350E-page 139
PIC18F/LF1XK50
15.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
15.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, display
drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
• Master mode
• Multi-Master mode
• Slave mode
15.2 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
• Serial Data Out – SDO
• Serial Data In – SDI
• Serial Clock – SCK
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select – SS
Figure 15-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 15-1: MSSP BLOCK DIAGRAM
(SPI MODE)
( )
Read Write
Internal
Data Bus
SSPSR Reg
SSPM<3:0>
bit 0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
Prescaler TOSC
4, 16, 64
2
Edge
Select
2
4
TRIS bit
SDO
SSPBUF Reg
SDI/SDA
SS
SCK/SCL
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DS41350E-page 140 Preliminary 2010 Microchip Technology Inc.
15.2.1 REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
• SSPCON1 – Control Register
• SSPSTAT – STATUS register
• SSPBUF – Serial Receive/Transmit Buffer
• SSPSR – Shift Register (Not directly accessible)
SSPCON1 and SSPSTAT are the control and STATUS
registers in SPI mode operation. The SSPCON1 register
is readable and writable. The lower 6 bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in and
out. SSPBUF provides indirect access to the SSPSR
register. SSPBUF is the buffer register to which data
bytes are written, and from which data bytes are read.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
REGISTER 15-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6 CKE: SPI Clock Select bit(1)
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
bit 5 D/A: Data/Address bit
Used in I2C mode only.
bit 4 P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
bit 3 S: Start bit
Used in I2C mode only.
bit 2 R/W: Read/Write Information bit
Used in I2C mode only.
bit 1 UA: Update Address bit
Used in I2C mode only.
bit 0 BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Note 1: Polarity of clock state is set by the CKP bit of the SSPCON1 register.
2010 Microchip Technology Inc. Preliminary DS41350E-page 141
PIC18F/LF1XK50
REGISTER 15-2: SSPCON1: MSSP CONTROL 1 REGISTER (SPI MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared by software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,
the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared by software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit(2)
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits(3)
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.
PIC18F/LF1XK50
DS41350E-page 142 Preliminary 2010 Microchip Technology Inc.
15.2.2 OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the Buffer Full detect bit, BF of the
SSPSTAT register, and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the write collision detect bit WCOL
of the SSPCON1 register, will be set. User software
must clear the WCOL bit to allow the following write(s)
to the SSPBUF register to complete successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF of the SSPSTAT register, indicates
when SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to
be used, then software polling can be done to ensure
that a write collision does not occur. Example 15-1
shows the loading of the SSPBUF (SSPSR) for data
transmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP STATUS register (SSPSTAT)
indicates the various status conditions.
EXAMPLE 15-1: LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?
BRA LOOP ;No
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit
2010 Microchip Technology Inc. Preliminary DS41350E-page 143
PIC18F/LF1XK50
15.2.3 ENABLING SPI I/O
To enable the serial port, SSP Enable bit, SSPEN of the
SSPCON1 register, must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port function,
some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI is automatically controlled by the SPI module
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
TRIS bit cleared
• SCK (Slave mode) must have corresponding
TRIS bit set
• SS must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
15.2.4 TYPICAL CONNECTION
Figure 15-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their programmed
clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data–Slave sends dummy data
• Master sends data–Slave sends data
• Master sends dummy data–Slave sends data
FIGURE 15-2: TYPICAL SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
Processor 1
SCK
SPI Master SSPM<3:0> = 00xx
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDI
SDO
Processor 2
SCK
SPI Slave SSPM<3:0> = 010x
Serial Clock
SS
Slave Select
General I/O
(optional)
PIC18F/LF1XK50
DS41350E-page 144 Preliminary 2010 Microchip Technology Inc.
15.2.5 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 15-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be disabled
(programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set).
The clock polarity is selected by appropriately
programming the CKP bit of the SSPCON1 register.
This then, would give waveforms for SPI
communication as shown in Figure 15-3, Figure 15-5
and Figure 15-6, where the MSB is transmitted first. In
Master mode, the SPI clock rate (bit rate) is user
programmable to be one of the following:
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 64 MHz) of
16.00 Mbps.
Figure 15-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 15-3: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
Modes
Input
Sample
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
bit 0
2010 Microchip Technology Inc. Preliminary DS41350E-page 145
PIC18F/LF1XK50
15.2.6 SLAVE MODE
In Slave mode, the data is transmitted and received as
external clock pulses appear on SCK. When the last bit
is latched, the SSPIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the clock
line must match the proper Idle state. The clock line can
be observed by reading the SCK pin. The Idle state is
determined by the CKP bit of the SSPCON1 register.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
15.2.7 SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 0100). When the SS pin is low,
transmission and reception are enabled and the SDO
pin is driven. When the SS pin goes high, the SDO pin
is no longer driven, even if in the middle of a transmitted
byte and becomes a floating output. External
pull-up/pull-down resistors may be desirable depending
on the application.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
FIGURE 15-4: SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is
set to VDD.
2: When the SPI is used in Slave mode with
CKE set the SS pin control must also be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 bit 6 bit 7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit 0
bit 7
bit 0
PIC18F/LF1XK50
DS41350E-page 146 Preliminary 2010 Microchip Technology Inc.
FIGURE 15-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 15-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Optional
bit 0
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Not Optional
2010 Microchip Technology Inc. Preliminary DS41350E-page 147
PIC18F/LF1XK50
15.2.8 OPERATION IN POWER-MANAGED
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
In all Idle modes, a clock is provided to the peripherals.
That clock could be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTOSC source. See Section 19.0 “Power-Managed
Modes” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
When MSSP interrupts are enabled, after the master
completes sending data, an MSSP interrupt will wake
the controller:
• from Sleep, in slave mode
• from Idle, in slave or master mode
If an exit from Sleep or Idle mode is not desired, MSSP
interrupts should be disabled.
In SPI master mode, when the Sleep mode is selected,
all module clocks are halted and the transmission/
reception will remain in that state until the devices
wakes. After the device returns to RUN mode, the module
will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set
and if enabled, will wake the device.
15.2.9 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
15.2.10 BUS MODE COMPATIBILITY
Table 15-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 15-1: SPI BUS MODES
There is also an SMP bit which controls when the data
is sampled.
TABLE 15-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Standard SPI Mode
Terminology
Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 288
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
SSPBUF SSP Receive Buffer/Transmit Register 286
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 286
SSPSTAT SMP CKE D/A P S R/W UA BF 286
Legend: Shaded cells are not used by the MSSP in SPI mode.
PIC18F/LF1XK50
DS41350E-page 148 Preliminary 2010 Microchip Technology Inc.
15.3 I2C Mode
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock – SCL
• Serial data – SDA
FIGURE 15-7: MSSP BLOCK DIAGRAM
(I2C™ MODE)
15.3.1 REGISTERS
The MSSP module has seven registers for I2C
operation. These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
• MSSP Address Mask (SSPMSK)
SSPCON1, SSPCON2 and SSPSTAT are the control
and STATUS registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read-only.
The upper two bits of the SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
When the MSSP is configured in Master mode, the
SSPADD register acts as the Baud Rate Generator
reload value. When the MSSP is configured for I2C
slave mode the SSPADD register holds the slave
device address. The MSSP can be configured to
respond to a range of addresses by qualifying selected
bits of the address register with the SSPMSK register.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
Note: The user must configure these pins as
inputs with the corresponding TRIS bits.
Read Write
SSPSR Reg
Match Detect
SSPADD Reg
Start and
Stop bit Detect
SSPBUF Reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT Reg)
SCK/SCL
SDI/SDA
Shift
Clock
MSb LSb
SSPMSK Reg
2010 Microchip Technology Inc. Preliminary DS41350E-page 149
PIC18F/LF1XK50
REGISTER 15-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P(1) S(1) R/W(2, 3) UA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high-speed mode (400 kHz)
bit 6 CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received was an address
bit 4 P: Stop bit(1)
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3 S: Start bit(1)
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
bit 2 R/W: Read/Write Information bit (I2C mode only)(2, 3)
In Slave mode:
1 = Read
0 = Write
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
bit 1 UA: Update Address bit (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
In Transmit mode:
1 = SSPBUF is full
0 = SSPBUF is empty
In Receive mode:
1 = SSPBUF is full (does not include the ACK and Stop bits)
0 = SSPBUF is empty (does not include the ACK and Stop bits)
Note 1: This bit is cleared on Reset and when SSPEN is cleared.
2: This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the Master mode is active.
PIC18F/LF1XK50
DS41350E-page 150 Preliminary 2010 Microchip Technology Inc.
REGISTER 15-4: SSPCON1: MSSP CONTROL 1 REGISTER (I2C MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission
to be started (must be cleared by software)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared by
software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6 SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared
by software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
When enabled, the SDA and SCL pins must be properly configured as inputs.
bit 4 CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (Slave Idle)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
2010 Microchip Technology Inc. Preliminary DS41350E-page 151
PIC18F/LF1XK50
REGISTER 15-5: SSPCON2: MSSP CONTROL REGISTER (I2C MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT(2) ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GCEN: General Call Enable bit (Slave mode only)
1 = Generate interrupt when a general call address 0x00 or 00h is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(2)
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(1)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence Idle
bit 3 RCEN: Receive Enable bit (Master mode only)(1)
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2 PEN: Stop Condition Enable bit (Master mode only)(1)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only)(1)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit(1)
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, these bits may not
be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
PIC18F/LF1XK50
DS41350E-page 152 Preliminary 2010 Microchip Technology Inc.
15.3.2 OPERATION
The MSSP module functions are enabled by setting
SSPEN bit of the SSPCON1 register.
The SSPCON1 register allows control of the I2C
operation. Four mode selection bits of the SSPCON1
register allow one of the following I2C modes to be
selected:
• I2C Master mode, clock = (FOSC/(4*(SSPADD + 1))
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I2C Firmware Controlled Master mode, slave is
Idle
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRIS bits
15.3.3 SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured
as inputs. The MSSP module will override the
input state with the output data when required
(slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
When an address is matched, or the data transfer after
an address match is received, the hardware
automatically will generate the Acknowledge (ACK)
pulse and load the SSPBUF register with the received
value currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF bit of the SSPSTAT register,
is set before the transfer is received.
• The overflow bit, SSPOV bit of the SSPCON1
register, is set before the transfer is received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF of the PIR1 register is
set. The BF bit is cleared by reading the SSPBUF
register, while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in Section 27.0 “Electrical
Specifications”.
15.3.3.1 Addressing
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. MSSP Interrupt Flag bit, SSPIF of the PIR1 register,
is set (interrupt is generated, if enabled) on
the falling edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W of the SSPSTAT register must specify
a write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for 10-bit
address is as follows, with steps 7 through 9 for the
slave-transmitter:
1. Receive first (high) byte of address (bits SSPIF,
BF and UA of the SSPSTAT register are set).
2. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
3. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set). If the address
matches then the SCL is held until the next step.
Otherwise the SCL line is not held.
5. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
6. Update the SSPADD register with the first (high)
byte of address. (This will clear bit UA and
release a held SCL line.)
7. Receive Repeated Start condition.
8. Receive first (high) byte of address with R/W bit
set (bits SSPIF, BF, R/W are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
10. Load SSPBUF with byte the slave is to transmit,
sets the BF bit.
11. Set the CKP bit to release SCL.
Note: To ensure proper operation of the module,
pull-up resistors must be provided externally
to the SCL and SDA pins.
2010 Microchip Technology Inc. Preliminary DS41350E-page 153
PIC18F/LF1XK50
15.3.3.2 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF bit of the SSPSTAT
register is set, or bit SSPOV bit of the SSPCON1
register is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF of the PIR1 register, must be
cleared by software.
When the SEN bit of the SSPCON2 register is set, SCL
will be held low (clock stretch) following each data
transfer. The clock must be released by setting the
CKP bit of the SSPCON1 register. See Section 15.3.4
“Clock Stretching” for more detail.
15.3.3.3 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin SCK/SCL is held low
regardless of SEN (see Section 15.3.4 “Clock
Stretching” for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPBUF register
which also loads the SSPSR register. Then pin
SCK/SCL should be released by setting the CKP bit of
the SSPCON1 register. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time
(Figure 15-9).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is complete.
In this case, when the ACK is latched by the slave, the
slave logic is reset (resets SSPSTAT register) and the
slave monitors for another occurrence of the Start bit. If
the SDA line was low (ACK), the next transmit data must
be loaded into the SSPBUF register. Again, pin
SCK/SCL must be released by setting bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared by software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
PIC18F/LF1XK50
DS41350E-page 154 Preliminary 2010 Microchip Technology Inc.
FIGURE 15-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
R/W = 0 Receiving Data ACK Receiving Data ACK
ACK
Receiving Address
Cleared by software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP (CKP does not reset to ‘0’ when SEN = 0)
2010 Microchip Technology Inc. Preliminary DS41350E-page 155
PIC18F/LF1XK50
FIGURE 15-9: I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9
SSPBUF is written by software
Cleared by software
From SSPIF ISR
Data in
sampled
S
ACK
R/W = 0 Transmitting Data
ACK
Receiving Address
A7 D7
9 1
D6 D5 D4 D3 D2 D1 D0
2 3 4 5 6 7 8 9
SSPBUF is written by software
Cleared by software
From SSPIF ISR
Transmitting Data
D7
1
CKP
P
ACK
CKP is set by software CKP is set by software
SCL held low
while CPU
responds to SSPIF
SSPBUF is read by software
Bus master
terminates software
PIC18F/LF1XK50
DS41350E-page 156 Preliminary 2010 Microchip Technology Inc.
FIGURE 15-10: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared by software
D2
6
(PIR1<3>)
Cleared by software
Receive Second Byte of Address
Cleared by hardware
when SSPADD is updated
with low byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
ACK
CKP
1 2 3 4 5 7 8 9
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared by software Cleared by software
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until
update of SSPADD has
taken place
2010 Microchip Technology Inc. Preliminary DS41350E-page 157
PIC18F/LF1XK50
FIGURE 15-11: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 0 A8
R/W=1
ACK ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus Master
sends Stop
condition
A9
6
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address.
UA
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address.
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
1 2 3 4 5 7 8 9
D7 D6 D5 D4 D3 D1
ACK
D2
6
Transmitting Data Byte
D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
Cleared in software
Completion of
clears BF flag
CKP
CKP is set in software, initiates transmission
CKP is automatically cleared in hardware holding SCL low
Clock is held low until
update of SSPADD has
taken place
data transmission
Clock is held low until
CKP is set to ‘1’
Bus Master
sends Restarts
condition
Dummy read of SSPBUF
to clear BF flag
PIC18F/LF1XK50
DS41350E-page 158 Preliminary 2010 Microchip Technology Inc.
15.3.3.4 SSP Mask Register
An SSP Mask (SSPMSK) register is available in I2C
Slave mode as a mask for the value held in the
SSPSR register during an address comparison
operation. A zero (‘0’) bit in the SSPMSK register has
the effect of making the corresponding bit in the
SSPSR register a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
This register must be initiated prior to setting
SSPM<3:0> bits to select the I2C Slave mode (7-bit or
10-bit address).
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
REGISTER 15-6: SSPMSK: SSP MASK REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPADD to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address(1)
I2C Slave mode, 10-bit Address (SSPM<3:0> = 0111):
1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
Note 1: The MSK0 bit is used only in 10-bit slave mode. In all other modes, this bit has no effect.
2010 Microchip Technology Inc. Preliminary DS41350E-page 159
PIC18F/LF1XK50
REGISTER 15-7: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Master mode:
bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode — Most significant address byte:
bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care.” Bit pattern
sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are
compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<9:8>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care.”
10-Bit Slave mode — Least significant address byte:
bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address
7-Bit Slave mode:
bit 7-1 ADD<6:0>: 7-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care.”
PIC18F/LF1XK50
DS41350E-page 160 Preliminary 2010 Microchip Technology Inc.
15.3.4 CLOCK STRETCHING
Both 7-bit and 10-bit Slave modes implement
automatic clock stretching during a transmit sequence.
The SEN bit of the SSPCON2 register allows clock
stretching to be enabled during receives. Setting SEN
will cause the SCL pin to be held low at the end of
each data receive sequence.
15.3.4.1 Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence if the BF
bit is set, the CKP bit of the SSPCON1 register is
automatically cleared, forcing the SCL output to be
held low. The CKP being cleared to ‘0’ will assert the
SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another data transfer
sequence. This will prevent buffer overruns from
occurring (see Figure 15-13).
15.3.4.2 Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
15.3.4.3 Clock Stretching for 7-bit Slave
Transmit Mode
7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
ninth clock. This occurs regardless of the state of the
SEN bit.
The user’s ISR must set the CKP bit before transmission
is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another data transfer sequence (see
Figure 15-9).
15.3.4.4 Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is controlled
during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is automatic with the hardware
clearing CKP, as in 7-bit Slave Transmit mode
(see Figure 15-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set by software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge
of the ninth clock, the CKP bit will not be
cleared and clock stretching will not
occur.
2: The CKP bit can be set by software
regardless of the state of the BF bit.
2010 Microchip Technology Inc. Preliminary DS41350E-page 161
PIC18F/LF1XK50
15.3.4.5 Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already sampled
low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 15-12).
FIGURE 15-12: CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX DX – 1
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON1
CKP
Master device
deasserts clock
Master device
asserts clock
PIC18F/LF1XK50
DS41350E-page 162 Preliminary 2010 Microchip Technology Inc.
FIGURE 15-13: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
R/W = 0 Receiving Data ACK Receiving Data ACK
ACK
Receiving Address
Cleared by software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP
CKP
written
to ‘1’ in
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to ‘0’ and no clock
stretching will occur
software
Clock is held low until
CKP is set to ‘1’
Clock is not held low
because buffer full bit is
clear prior to falling edge
of 9th clock
Clock is not held low
because ACK = 1
BF is set after falling
edge of the 9th clock,
CKP is reset to ‘0’ and
clock stretching occurs
2010 Microchip Technology Inc. Preliminary DS41350E-page 163
PIC18F/LF1XK50
FIGURE 15-14: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared by software
D2
6
(PIR1<3>)
Cleared by software
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address after falling edge
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address after falling edge
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
ACK
CKP
1 2 3 4 5 7 8 9
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared by software Cleared by software
SSPOV (SSPCON1<6>)
CKP written to ‘1’
Note: An update of the SSPADD register before
the falling edge of the ninth clock will have
no effect on UA and UA will remain set.
Note: An update of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set.
by software
Clock is held low until
update of SSPADD has
taken place
of ninth clock of ninth clock
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
Dummy read of SSPBUF
to clear BF flag
Clock is held low until
CKP is set to ‘1’
Clock is not held low
because ACK = 1
PIC18F/LF1XK50
DS41350E-page 164 Preliminary 2010 Microchip Technology Inc.
15.3.5 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
GCEN bit of the SSPCON2 is set. Following a Start bit
detect, 8 bits are shifted into the SSPSR and the
address is compared against the SSPADD. It is also
compared to the general call address and fixed in
hardware.
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit of the SSPSTAT register is set. If the general call
address is sampled when the GCEN bit is set, while the
slave is configured in 10-bit Address mode, then the
second half of the address is not necessary, the UA bit
will not be set and the slave will begin receiving data
after the Acknowledge (Figure 15-15).
FIGURE 15-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
SDA
SCL
S
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
Cleared by software
SSPBUF is read
R/W = 0
General Call Address ACK
Address is compared to General Call Address
GCEN (SSPCON2<7>)
Receiving Data ACK
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set interrupt
‘0’
‘1’
2010 Microchip Technology Inc. Preliminary DS41350E-page 165
PIC18F/LF1XK50
15.3.6 MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop conditions.
The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I2C bus may be taken when the P bit is set, or the
bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt, if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
FIGURE 15-16: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)
Note: The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Read Write
SSPSR
Start bit, Stop bit,
SSPBUF
Internal
Data Bus
Set/Reset, S, P, WCOL
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL
SCL In
Bus Collision
SDA In
Receive Enable
Clock Cntl
Clock Arbitrate/WCOL Detect
(hold off clock source)
SSPADD<6:0>
Baud
Set SSPIF, BCLIF
Reset ACKSTAT, PEN
Rate
Generator
SSPM<3:0>
Start bit Detect
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DS41350E-page 166 Preliminary 2010 Microchip Technology Inc.
15.3.6.1 I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmitted,
an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted contains
the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an Acknowledge bit is transmitted.
Start and Stop conditions indicate the beginning
and end of transmission.
A Baud Rate Generator is used to set the clock
frequency output on SCL. See Section 15.3.7 “Baud
Rate” for more detail.
A typical transmit sequence would go as follows:
1. The user generates a Start condition by setting
the SEN bit of the SSPCON2 register.
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. Address is shifted out the SDA pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out the SDA pin until all 8 bits are
transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
11. The user generates a Stop condition by setting
the PEN bit of the SSPCON2 register.
12. Interrupt is generated once the Stop condition is
complete.
2010 Microchip Technology Inc. Preliminary DS41350E-page 167
PIC18F/LF1XK50
15.3.7 BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the SSPADD register
(Figure 15-17). When a write occurs to SSPBUF, the
Baud Rate Generator will automatically begin counting.
Once the given operation is complete (i.e.,
transmission of the last data bit is followed by ACK), the
internal clock will automatically stop counting and the
SCL pin will remain in its last state.
Table 15-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
EQUATION 15-1:
FIGURE 15-17: BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 15-3: I2C™ CLOCK RATE W/BRG
FSCL FOSC
SSPADD + 14 = ----------------------------------------------
SSPM<3:0>
CLKOUT BRG Down Counter FOSC/2
SSPADD<7:0>
SSPM<3:0>
SCL
Reload
Control
Reload
FOSC FCY BRG Value FSCL
(2 Rollovers of BRG)
48 MHz 12 MHz 0Bh 1 MHz(1)
48 MHz 12 MHz 1Dh 400 kHz
48 MHz 12 MHz 77h 100 kHz
40 MHz 10 MHz 18h 400 kHz(1)
40 MHz 10 MHz 1Fh 312.5 kHz
40 MHz 10 MHz 63h 100 kHz
16 MHz 4 MHz 09h 400 kHz(1)
16 MHz 4 MHz 0Ch 308 kHz
16 MHz 4 MHz 27h 100 kHz
4 MHz 1 MHz 02h 333 kHz(1)
4 MHz 1 MHz 09h 100 kHz
4 MHz 1 MHz 00h 1 MHz(1)
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
PIC18F/LF1XK50
DS41350E-page 168 Preliminary 2010 Microchip Technology Inc.
15.3.7.1 Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 15-18).
FIGURE 15-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
SCL deasserted but slave holds
DX DX – 1
BRG
SCL is sampled high, reload takes
place and BRG starts its count
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
2010 Microchip Technology Inc. Preliminary DS41350E-page 169
PIC18F/LF1XK50
15.3.8 I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable bit, SEN bit of the SSPCON2 register. If the
SDA and SCL pins are sampled high, the Baud Rate
Generator is reloaded with the contents of
SSPADD<6:0> and starts its count. If SCL and SDA are
both sampled high when the Baud Rate Generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit of the SSPSTAT1
register to be set. Following this, the Baud Rate Generator
is reloaded with the contents of SSPADD<7:0>
and resumes its count. When the Baud Rate Generator
times out (TBRG), the SEN bit of the SSPCON2 register
will be automatically cleared by hardware; the Baud
Rate Generator is suspended, leaving the SDA line
held low and the Start condition is complete.
15.3.8.1 WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
FIGURE 15-19: FIRST START BIT TIMING
Note: If at the beginning of the Start condition,
the SDA and SCL pins are already sampled
low, or if during the Start condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is aborted
and the I2C module is reset into its Idle
state.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
SDA
SCL
S
TBRG
1st bit 2nd bit
TBRG
SDA = 1,
SCL = 1 At completion of Start bit,
TBRG Write to SSPBUF occurs here
hardware clears SEN bit
TBRG
Write to SEN bit occurs here
Set S bit (SSPSTAT<3>)
and sets SSPIF bit
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DS41350E-page 170 Preliminary 2010 Microchip Technology Inc.
15.3.9 I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
of the SSPCON2 register is programmed high and the
I2C logic module is in the Idle state. When the RSEN bit
is set, the SCL pin is asserted low. When the SCL pin
is sampled low, the Baud Rate Generator is loaded and
begins counting. The SDA pin is released (brought
high) for one Baud Rate Generator count (TBRG). When
the Baud Rate Generator times out, if SDA is sampled
high, the SCL pin will be deasserted (brought high).
When SCL is sampled high, the Baud Rate Generator
is reloaded and begins counting. SDA and SCL must
be sampled high for one TBRG. This action is then followed
by assertion of the SDA pin (SDA = 0) for one
TBRG while SCL is high. Following this, the RSEN bit of
the SSPCON2 register will be automatically cleared
and the Baud Rate Generator will not be reloaded,
leaving the SDA pin held low. As soon as a Start condition
is detected on the SDA and SCL pins, the S bit of
the SSPSTAT register will be set. The SSPIF bit will not
be set until the Baud Rate Generator has timed out.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After the
first eight bits are transmitted and an ACK is received,
the user may then transmit an additional eight bits of
address (10-bit mode) or eight bits of data (7-bit mode).
15.3.9.1 WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-20: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
SDA
SCL
Sr = Repeated Start
Write to SSPCON2
on falling edge of ninth clock, Write to SSPBUF occurs here
end of Xmit
At completion of Start bit,
hardware clears RSEN bit
1st bit
S bit set by hardware
TBRG
TBRG
SDA = 1,
SDA = 1,
SCL (no change).
SCL = 1
occurs here.
TBRG TBRG TBRG
and sets SSPIF
RSEN bit set by hardware
2010 Microchip Technology Inc. Preliminary DS41350E-page 171
PIC18F/LF1XK50
15.3.10 I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next transmission.
Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification
parameter SP106). SCL is held low for one Baud Rate
Generator rollover count (TBRG). Data should be valid
before SCL is released high (see data setup time specification
parameter SP107). When the SCL pin is
released high, it is held that way for TBRG. The data on
the SDA pin must remain stable for that duration and
some hold time after the next falling edge of SCL. After
the eighth bit is shifted out (the falling edge of the eighth
clock), the BF flag is cleared and the master releases
SDA. This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received properly.
The status of ACK is written into the ACKDT bit on
the falling edge of the ninth clock. If the master receives
an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 15-21).
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
deassert the SDA pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDA pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT status bit of the
SSPCON2 register. Following the falling edge of the
ninth clock transmission of the address, the SSPIF is
set, the BF flag is cleared and the Baud Rate Generator
is turned off until another write to the SSPBUF takes
place, holding SCL low and allowing SDA to float.
15.3.10.1 BF Status Flag
In Transmit mode, the BF bit of the SSPSTAT register
is set when the CPU writes to SSPBUF and is cleared
when all 8 bits are shifted out.
15.3.10.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).
WCOL must be cleared by software before the next
transmission.
15.3.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPCON2
register is cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowledge
when it has recognized its address (including a
general call), or when the slave has properly received
its data.
15.3.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN bit of the SSPCON2
register.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the contents
of the SSPSR are loaded into the SSPBUF, the
BF flag bit is set, the SSPIF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCL low. The MSSP is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable, ACKEN
bit of the SSPCON2 register.
15.3.11.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
15.3.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
15.3.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
Note: The MSSP module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be disregarded.
PIC18F/LF1XK50
DS41350E-page 172 Preliminary 2010 Microchip Technology Inc.
FIGURE 15-21: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
ACK
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
Cleared by software service routine
SSPBUF is written by software
from SSP interrupt
After Start condition, SEN cleared by hardware
S
SSPBUF written with 7-bit address and R/W
start transmit
SCL held low
while CPU
responds to SSPIF
SEN = 0
of 10-bit Address
Write SSPCON2<0> SEN = 1
Start condition begins From slave, clear ACKSTAT bit SSPCON2<6>
ACKSTAT in
SSPCON2 = 1
Cleared by software
SSPBUF written
PEN
R/W
Cleared by software
2010 Microchip Technology Inc. Preliminary DS41350E-page 173
PIC18F/LF1XK50
FIGURE 15-22: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
5 6 7 8 9
D7 D6 D5 D4 D3 D2 D1 D0
S
SDA A7 A6 A5 A4 A3 A2 A1
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4
Bus master
terminates
transfer
ACK
Receiving Data from Slave Receiving Data from Slave
ACK D7 D6 D5 D4 D3 D2 D1 D0
Transmit Address to Slave R/W = 0
SSPIF
BF
ACK is not sent
Write to SSPCON2<0> (SEN = 1),
Write to SSPBUF occurs here,
ACK from Slave
Master configured as a receiver
by programming SSPCON2<3> (RCEN = 1)
PEN bit = 1
written here
Data shifted in on falling edge of CLK
Cleared by software
start XMIT
SEN = 0
SSPOV
SDA = 0, SCL = 1
while CPU
(SSPSTAT<0>)
ACK
Cleared by software Cleared by software
Set SSPIF interrupt
at end of receive
Set P bit
(SSPSTAT<4>)
and SSPIF
Cleared in
software
ACK from Master
Set SSPIF at end
Set SSPIF interrupt
at end of Acknowledge
sequence
Set SSPIF interrupt
at end of Acknowledge
sequence
of receive
Set ACKEN, start Acknowledge sequence
SSPOV is set because
SSPBUF is still full
SDA = ACKDT = 1
RCEN cleared
automatically
RCEN = 1, start
next receive
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
RCEN cleared
automatically
responds to SSPIF
ACKEN
begin Start condition
Cleared by software
SDA = ACKDT = 0
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
RCEN
Master configured as a receiver
by programming SSPCON2<3> (RCEN = 1)
RCEN cleared
automatically
ACK from Master
SDA = ACKDT = 0
RCEN cleared
automatically
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DS41350E-page 174 Preliminary 2010 Microchip Technology Inc.
15.3.12 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to generate
an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 15-23).
15.3.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
15.3.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSPSTAT register is set. A TBRG later, the PEN bit is
cleared and the SSPIF bit is set (Figure 15-24).
15.3.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-23: ACKNOWLEDGE SEQUENCE WAVEFORM
FIGURE 15-24: STOP CONDITION RECEIVE OR TRANSMIT MODE
Note: TBRG = one Baud Rate Generator period.
SDA
SCL
SSPIF set at
Acknowledge sequence starts here,
write to SSPCON2 ACKEN automatically cleared
Cleared in
TBRG TBRG
the end of receive
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software SSPIF set at the end
of Acknowledge sequence
Cleared in
software
ACK
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON2,
set PEN
Falling edge of
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
9th clock
SCL brought high after TBRG
Note: TBRG = one Baud Rate Generator period.
TBRG TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
TBRG
to setup Stop condition
ACK
P
TBRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
2010 Microchip Technology Inc. Preliminary DS41350E-page 175
PIC18F/LF1XK50
15.3.14 SLEEP OPERATION
While in Sleep mode, the I2C Slave module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
15.3.15 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
15.3.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit of the SSPSTAT register is set,
or the bus is Idle, with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will generate
the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
15.3.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitration.
When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 15-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deasserted
and the respective control bits in the SSPCON2
register are cleared. When the user services the bus collision
Interrupt Service Routine and if the I2C bus is free,
the user can resume communication by asserting a Start
condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination
of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 15-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source
Sample SDA. While SCL is high,
data doesn’t match what is driven
Bus collision has occurred.
Set bus collision
interrupt (BCLIF)
by the master.
by master
Data changes
while SCL = 0
PIC18F/LF1XK50
DS41350E-page 176 Preliminary 2010 Microchip Technology Inc.
15.3.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 15-26).
b) SCL is sampled low before SDA is asserted low
(Figure 15-27).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
• the MSSP module is reset to its Idle state
(Figure 15-26).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded and counts down. If the
SCL pin is sampled low while SDA is high, a bus
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 15-28). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0; if the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
FIGURE 15-26: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The reason that bus collision is not a factor
during a Start condition is that no two
bus masters can assert a Start condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address following
the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SDA
SCL
SEN
SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SSP module reset into Idle state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SDA = 0, SCL = 1.
BCLIF
S
SSPIF
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared by software
SSPIF and BCLIF are
cleared by software
Set BCLIF,
Start condition. Set BCLIF.
2010 Microchip Technology Inc. Preliminary DS41350E-page 177
PIC18F/LF1XK50
FIGURE 15-27: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 15-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SCL
SEN
bus collision occurs. Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Interrupt cleared
by software
bus collision occurs. Set BCLIF.
SCL = 0 before BRG time-out,
‘0’ ‘0’
‘0’ ‘0’
SDA
SCL
SEN
Set S
Less than TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
S
Interrupts cleared
set SSPIF by software
SDA = 0, SCL = 1,
SCL pulled low after BRG
time-out
Set SSPIF
‘0’
SDA pulled low by other master.
Reset BRG and assert SDA.
Set SEN, enable START
sequence if SDA = 1, SCL = 1
PIC18F/LF1XK50
DS41350E-page 178 Preliminary 2010 Microchip Technology Inc.
15.3.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD and counts
down to 0. The SCL pin is then deasserted and when
sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 15-29).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see Figure 15-30.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 15-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 15-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
Cleared by software
‘0’
‘0’
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
by software
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
TBRG TBRG
‘0’
2010 Microchip Technology Inc. Preliminary DS41350E-page 179
PIC18F/LF1XK50
15.3.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD and
counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 15-31). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 15-32).
FIGURE 15-31: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 15-32: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
set BCLIF
‘0’
‘0’
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA SCL goes low before SDA goes high,
set BCLIF
‘0’
‘0’
PIC18F/LF1XK50
DS41350E-page 180 Preliminary 2010 Microchip Technology Inc.
TABLE 15-4: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on
page
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR2 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP — 288
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF — 288
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE — 288
SSPADD SSP Address Register in I2C™ Slave Mode. SSP Baud Rate Reload Register in I2C Master
Mode.
286
SSPBUF SSP Receive Buffer/Transmit Register 286
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 286
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 286
SSPMSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 288
SSPSTAT SMP CKE D/A P S R/W UA BF 286
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 288
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by I2C™.
2010 Microchip Technology Inc. Preliminary DS41350E-page 181
PIC18F/LF1XK50
16.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
The EUSART module includes the following capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock and data polarity
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 16-1 and Figure 16-2.
FIGURE 16-1: EUSART TRANSMIT BLOCK DIAGRAM
TXIF
TXIE
Interrupt
TXEN
TX9D
MSb LSb
Data Bus
TXREG Register
Transmit Shift Register (TSR)
(8) 0
TX9
TRMT SPEN
TX/CK pin
Pin Buffer
and Control
8
SPBRGH SPBRG
BRG16
FOSC ÷ n
n
+ 1 Multiplier x4 x16 x64
SYNC 1 X 0 0 0
BRGH X 1 1 0 0
BRG16 X 1 0 1 0
Baud Rate Generator
• • •
PIC18F/LF1XK50
DS41350E-page 182 Preliminary 2010 Microchip Technology Inc.
FIGURE 16-2: EUSART RECEIVE BLOCK DIAGRAM
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCTL)
These registers are detailed in Register 16-1,
Register 16-2 and Register 16-3, respectively.
For all modes of EUSART operation, the TRIS control
bits corresponding to the RX/DT and TX/CK pins should
be set to ‘1’. The EUSART control will automatically
reconfigure the pin from input to output, as needed.
RX/DT pin
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR
FERR
MSb RSR Register LSb
RX9D RCREG Register
FIFO
RCIF Interrupt
RCIE
Data Bus
8
Stop (8) 7 1 0 START
RX9
• • •
SPBRGH SPBRG
BRG16
RCIDL
FOSC ÷ n
+ 1 Multiplier x4 x16 x64 n
SYNC 1 X 0 0 0
BRGH X 1 1 0 0
BRG16 X 1 0 1 0
Baud Rate Generator
2010 Microchip Technology Inc. Preliminary DS41350E-page 183
PIC18F/LF1XK50
16.1 EUSART Asynchronous Mode
The EUSART transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH mark state which
represents a ‘1’ data bit, and a VOL space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output level of that bit without returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the mark state. Each character
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is 8 bits. Each transmitted bit persists for a period
of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud
Rate Generator is used to derive standard baud rate
frequencies from the system oscillator. See Table 16-5
for examples of baud rate configurations.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but share the same data format and baud
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data bit.
16.1.1 EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 16-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXREG register.
16.1.1.1 Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
• TXEN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and automatically
configures the TX/CK I/O pin as an output. If the TX/CK
pin is shared with an analog peripheral the analog I/O
function must be disabled by clearing the corresponding
ANSEL bit.
16.1.1.2 Transmitting Data
A transmission is initiated by writing a character to the
TXREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXREG is then transferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the Start bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXREG.
16.1.1.3 Transmit Data Polarity
The polarity of the transmit data can be controlled with
the CKTXP bit of the BAUDCON register. The default
state of this bit is ‘0’ which selects high true transmit
idle and data bits. Setting the CKTXP bit to ‘1’ will invert
the transmit data resulting in low true idle and data bits.
The CKTXP bit controls transmit data polarity only in
Asynchronous mode. In Synchronous mode the
CKTXP bit has a different function.
Note 1: When the SPEN bit is set the RX/DT I/O
pin is automatically configured as an input,
regardless of the state of the corresponding
TRIS bit and whether or not the
EUSART receiver is enabled. The RX/DT
pin data can be read via a normal PORT
read but PORT latch data output is precluded.
2: The TXIF transmitter interrupt flag is set
when the TXEN enable bit is set.
PIC18F/LF1XK50
DS41350E-page 184 Preliminary 2010 Microchip Technology Inc.
16.1.1.4 Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
character is being held for transmission in the TXREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new character has been
queued for transmission in the TXREG. The TXIF flag bit
is not cleared immediately upon writing TXREG. TXIF
becomes valid in the second instruction cycle following
the write execution. Polling TXIF immediately following
the TXREG write will return invalid results. The TXIF bit
is read-only, it cannot be set or cleared by software.
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXREG is empty,
regardless of the state of TXIE enable bit.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
of the transmission to the TXREG.
16.1.1.5 TSR Status
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user needs to
poll this bit to determine the TSR status.
16.1.1.6 Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set the
EUSART will shift 9 bits out for each character transmitted.
The TX9D bit of the TXSTA register is the ninth,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the 8 Least Significant bits into the TXREG. All nine bits
of data will be transferred to the TSR shift register
immediately after the TXREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 16.1.2.8 “Address
Detection” for more information on the Address mode.
16.1.1.7 Asynchronous Transmission Set-up:
1. Initialize the SPBRGH:SPBRG register pair and
the BRGH and BRG16 bits to achieve the desired
baud rate (see Section 16.3 “EUSART Baud
Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If 9-bit transmission is desired, set the TX9 control
bit. A set ninth data bit will indicate that the 8
Least Significant data bits are an address when
the receiver is set for address detection.
4. Set the CKTXP control bit if inverted transmit
data polarity is desired.
5. Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
6. If interrupts are desired, set the TXIE interrupt
enable bit. An interrupt will occur immediately
provided that the GIE and PEIE bits of the
INTCON register are also set.
7. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
8. Load 8-bit data into the TXREG register. This
will start the transmission.
Note: The TSR register is not mapped in data
memory, so it is not available to the user.
2010 Microchip Technology Inc. Preliminary DS41350E-page 185
PIC18F/LF1XK50
FIGURE 16-3: ASYNCHRONOUS TRANSMISSION
FIGURE 16-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
TABLE 16-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
TXREG EUSART Transmit Register 287
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 287
SPBRGH EUSART Baud Rate Generator Register, High Byte 287
SPBRG EUSART Baud Rate Generator Register, Low Byte 287
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Word 1
Stop bit
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RB7/TX/CK
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 TCY
pin
Transmit Shift Reg
Write to TXREG
BRG Output
(Shift Clock)
RB7/TX/CK
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
Start bit Stop bit Start bit
Transmit Shift Reg
Word 1 Word 2
bit 0 bit 1 bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
pin
PIC18F/LF1XK50
DS41350E-page 186 Preliminary 2010 Microchip Technology Inc.
16.1.2 EUSART ASYNCHRONOUS
RECEIVER
The Asynchronous mode would typically be used in
RS-232 systems. The receiver block diagram is shown
in Figure 16-2. The data is received on the RX/DT pin
and drives the data recovery block. The data recovery
block is actually a high-speed shifter operating at 16
times the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all 8 or 9
bits of the character have been shifted in, they are
immediately transferred to a two character
First-In-First-Out (FIFO) memory. The FIFO buffering
allows reception of two complete characters and the
start of a third character before software must start
servicing the EUSART receiver. The FIFO and RSR
registers are not directly accessible by software.
Access to the received data is via the RCREG register.
16.1.2.1 Enabling the Receiver
The EUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCSTA register enables the
receiver circuitry of the EUSART. Clearing the SYNC bit
of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART. The RX/DT I/O
pin must be configured as an input by setting the
corresponding TRIS control bit. If the RX/DT pin is
shared with an analog peripheral the analog I/O function
must be disabled by clearing the corresponding ANSEL
bit.
16.1.2.2 Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit counts a full bit time to the center of the
next bit. The bit is then sampled by a majority detect
circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
This repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
character. See Section 16.1.2.5 “Receive Framing
Error” for more information on framing errors.
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCREG register.
16.1.2.3 Receive Data Polarity
The polarity of the receive data can be controlled with
the DTRXP bit of the BAUDCON register. The default
state of this bit is ‘0’ which selects high true receive idle
and data bits. Setting the DTRXP bit to ‘1’ will invert the
receive data resulting in low true idle and data bits. The
DTRXP bit controls receive data polarity only in
Asynchronous mode. In synchronous mode the
DTRXP bit has a different function.
Note: When the SPEN bit is set the TX/CK I/O
pin is automatically configured as an
output, regardless of the state of the
corresponding TRIS bit and whether or
not the EUSART transmitter is enabled.
The PORT latch is disconnected from the
output driver so it is not possible to use the
TX/CK pin as a general purpose output.
Note: If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition is cleared. See Section 16.1.2.6
“Receive Overrun Error” for more
information on overrun errors.
2010 Microchip Technology Inc. Preliminary DS41350E-page 187
PIC18F/LF1XK50
16.1.2.4 Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set
whenever the EUSART receiver is enabled and there is
an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting the following
bits:
• RCIE interrupt enable bit of the PIE1 register
• PEIE peripheral interrupt enable bit of the
INTCON register
• GIE global interrupt enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
16.1.2.5 Receive Framing Error
Each character in the receive FIFO buffer has a
corresponding framing error status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCSTA register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCREG.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCSTA register which resets the EUSART.
Clearing the CREN bit of the RCSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
16.1.2.6 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated If a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is set.
The characters already in the FIFO buffer can be read
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.
16.1.2.7 Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set, the EUSART
will shift 9 bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.
16.1.2.8 Address Detection
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCIF interrupt
bit. All other characters will be ignored.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
Note: If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.
PIC18F/LF1XK50
DS41350E-page 188 Preliminary 2010 Microchip Technology Inc.
16.1.2.9 Asynchronous Reception Set-up:
1. Initialize the SPBRGH:SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 16.3 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the serial port by setting the SPEN bit
and the RX/DT pin TRIS bit. The SYNC bit must
be clear for asynchronous operation.
3. If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
4. If 9-bit reception is desired, set the RX9 bit.
5. Set the DTRXP if inverted receive polarity is
desired.
6. Enable reception by setting the CREN bit.
7. The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
8. Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
9. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
16.1.2.10 9-bit Address Detection Mode Set-up
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 16.3 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
3. If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
4. Enable 9-bit reception by setting the RX9 bit.
5. Enable address detection by setting the ADDEN
bit.
6. Set the DTRXP if inverted receive polarity is
desired.
7. Enable reception by setting the CREN bit.
8. The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
9. Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
10. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 16-5: ASYNCHRONOUS RECEPTION
Start
bit bit 0 bit 1 bit 7/8 Stop bit 0 bit 7/8
bit
Start
bit
Start
bit 7/8 Stop bit
bit
RX/DT pin
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
RCIDL
2010 Microchip Technology Inc. Preliminary DS41350E-page 189
PIC18F/LF1XK50
TABLE 16-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
RCREG EUSART Receive Register 287
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 287
SPBRGH EUSART Baud Rate Generator Register, High Byte 287
SPBRG EUSART Baud Rate Generator Register, Low Byte 287
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
PIC18F/LF1XK50
DS41350E-page 190 Preliminary 2010 Microchip Technology Inc.
16.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block output
(HFINTOSC). However, the HFINTOSC frequency
may drift as VDD or temperature changes, and this
directly affects the asynchronous baud rate. Two methods
may be used to adjust the baud rate clock, but both
require a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the HFINTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See Section 2.6.1
“OSCTUNE Register” for more information.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 16.3.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
2010 Microchip Technology Inc. Preliminary DS41350E-page 191
PIC18F/LF1XK50
REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
PIC18F/LF1XK50
DS41350E-page 192 Preliminary 2010 Microchip Technology Inc.
REGISTER 16-3: BAUDCON: BAUD RATE CONTROL REGISTER
R-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ABDOVF: Auto-Baud Detect Overflow bit
Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been detected and the receiver is active
Synchronous mode:
Don’t care
bit 5 DTRXP: Data/Receive Polarity Select bit
Asynchronous mode:
1 = Receive data (RX) is inverted (active-low)
0 = Receive data (RX) is not inverted (active-high)
Synchronous mode:
1 = Data (DT) is inverted (active-low)
0 = Data (DT) is not inverted (active-high)
bit 4 CKTXP: Clock/Transmit Polarity Select bit
Asynchronous mode:
1 = Idle state for transmit (TX) is low
0 = Idle state for transmit (TX) is high
Synchronous mode:
1 = Data changes on the falling edge of the clock and is sampled on the rising edge of the clock
0 = Data changes on the rising edge of the clock and is sampled on the falling edge of the clock
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used (SPBRGH:SPBRG)
0 = 8-bit Baud Rate Generator is used (SPBRG)
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge. No character will be received but RCIF will be set on the falling
edge. WUE will automatically clear on the rising edge.
0 = Receiver is operating normally
Synchronous mode:
Don’t care
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care
2010 Microchip Technology Inc. Preliminary DS41350E-page 193
PIC18F/LF1XK50
16.3 EUSART Baud Rate Generator
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCON register selects 16-bit
mode.
The SPBRGH:SPBRG register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCON register. In
Synchronous mode, the BRGH bit is ignored.
Table 16-3 contains the formulas for determining the
baud rate. Example 16-1 provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 16-5. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
Writing a new value to the SPBRGH, SPBRG register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
EXAMPLE 16-1: CALCULATING BAUD
RATE ERROR
TABLE 16-3: BAUD RATE FORMULAS
TABLE 16-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
Solving for SPBRGH:SPBRG:
Desired Baud Rate FOSC
64[SPBRGH:SPBRG] + 1 = --------------------------------------------------------------------
= 25.042 = 25
Calculated Baud Rate 16000000
6425 + 1 = ---------------------------
= 9615
Error Calc. Baud Rate – Desired Baud Rate
Desired Baud Rate
= --------------------------------------------------------------------------------------------
9615 – 9600
9600
= ---------------------------------- = 0.16%
FOSC X = 64 * (Desired Baud Rate)
( )-1
16,000,000
= 64 * 9600
( )-1
Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)]
0 0 1 8-bit/Asynchronous
FOSC/[16 (n+1)]
0 1 0 16-bit/Asynchronous
0 1 1 16-bit/Asynchronous
1 0 x 8-bit/Synchronous FOSC/[4 (n+1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH, SPBRG register pair
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values
on page
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 287
SPBRGH EUSART Baud Rate Generator Register, High Byte 287
SPBRG EUSART Baud Rate Generator Register, Low Byte 287
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
PIC18F/LF1XK50
DS41350E-page 194 Preliminary 2010 Microchip Technology Inc.
TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 12.000 MHz FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300 — — — — — — — — — — — —
1200 — — — 1200 0.00 239 1202 0.16 155 1200 0.00 143
2400 — — — 2400 0.00 119 2404 0.16 77 2400 0.00 71
9600 9615 0.16 77 9600 0.00 29 9375 -2.34 19 9600 0.00 17
10417 10417 0.00 71 10286 -1.26 27 10417 0.00 17 10165 -2.42 16
19.2k 19.23k 0.16 38 19.20k 0.00 14 18.75k -2.34 9 19.20k 0.00 8
57.6k 57.69k 0.16 12 57.60k 0.00 7 — — — 57.60k 0.00 2
115.2k — — — — — — — — — — — —
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300 — — — 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —
9600 9615 0.16 12 — — — 9600 0.00 5 — — —
10417 10417 0.00 11 10417 0.00 5 — — — — — —
19.2k — — — — — — 19.20k 0.00 2 — — —
57.6k — — — — — — 57.60k 0.00 0 — — —
115.2k — — — — — — — — — — — —
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 12.000 MHz FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 — — — 9600 0.00 119 9615 0.16 77 9600 0.00 71
10417 — — — 10378 -0.37 110 10417 0.00 71 10473 0.53 65
19.2k 19.23k 0.16 155 19.20k 0.00 59 19.23k 0.16 38 19.20k 0.00 35
57.6k 57.69k 0.16 51 57.60k 0.00 19 57.69k 0.16 12 57.60k 0.00 11
115.2k 115.38k 0.16 25 115.2k 0.00 9 — — — 115.2k 0.00 5
2010 Microchip Technology Inc. Preliminary DS41350E-page 195
PIC18F/LF1XK50
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 12.000 MHz FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
300 300.0 0.00 9999 300.0 0.00 3839 300 0.00 2499 300.0 0.00 2303
1200 1200.1 0.00 2499 1200 0.00 959 1200 0.00 624 1200 0.00 575
2400 2400 0.00 1249 2400 0.00 479 2404 0.16 311 2400 0.00 287
9600 9615 0.16 311 9600 0.00 119 9615 0.16 77 9600 0.00 71
10417 10417 0.00 287 10378 -0.37 110 10417 0.00 71 10473 0.53 65
19.2k 19.23k 0.16 155 19.20k 0.00 59 19.23k 0.16 38 19.20k 0.00 35
57.6k 57.69k 0.16 51 57.60k 0.00 19 57.69k 0.16 12 57.60k 0.00 11
115.2k 115.38k 0.16 25 115.2k 0.00 9 — — — 115.2k 0.00 5
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
PIC18F/LF1XK50
DS41350E-page 196 Preliminary 2010 Microchip Technology Inc.
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 12.000 MHz FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
300 300 0.00 39999 300.0 0.00 15359 300 0.00 9999 300.0 0.00 9215
1200 1200 0.00 9999 1200 0.00 3839 1200 0.00 2499 1200 0.00 2303
2400 2400 0.00 4999 2400 0.00 1919 2400 0.00 1249 2400 0.00 1151
9600 9600 0.00 1249 9600 0.00 479 9615 0.16 311 9600 0.00 287
10417 10417 0.00 1151 10425 0.08 441 10417 0.00 287 10433 0.16 264
19.2k 19.20k 0.00 624 19.20k 0.00 239 19.23k 0.16 155 19.20k 0.00 143
57.6k 57.69k 0.16 207 57.60k 0.00 79 57.69k 0.16 51 57.60k 0.00 47
115.2k 115.38k 0.16 103 115.2k 0.00 39 115.38k 0.16 25 115.2k 0.00 23
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
Actual
Rate
%
Error
SPBRGH
:SPBRG
(decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0.00 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —
TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
2010 Microchip Technology Inc. Preliminary DS41350E-page 197
PIC18F/LF1XK50
16.3.1 AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDCON register starts
the auto-baud calibration sequence (Figure 16-6).
While the ABD sequence takes place, the EUSART
state machine is held in Idle. On the first rising edge of
the receive line, after the Start bit, the SPBRG begins
counting up using the BRG counter clock as shown in
Table 16-6. The fifth rising edge will occur on the RX pin
at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPBRGH:SPBRG register pair, the ABDEN
bit is automatically cleared, and the RCIF interrupt flag
is set. A read operation on the RCREG needs to be
performed to clear the RCIF interrupt. RCREG content
should be discarded. When calibrating for modes that
do not use the SPBRGH register the user can verify
that the SPBRG register did not overflow by checking
for 00h in the SPBRGH register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 16-6. During ABD,
both the SPBRGH and SPBRG registers are used as a
16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH
and SPBRG registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
TABLE 16-6: BRG COUNTER CLOCK RATES
FIGURE 16-6: AUTOMATIC BAUD RATE CALIBRATION
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
Section 16.3.3 “Auto-Wake-up on
Break”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
3: During the auto-baud process, the
auto-baud counter starts counting at 1.
Upon completion of the auto-baud
sequence, to achieve maximum accuracy,
subtract 1 from the SPBRGH:SPBRG
register pair.
BRG16 BRGH BRG Base
Clock
BRG ABD
Clock
0 0 FOSC/64 FOSC/512
0 1 FOSC/16 FOSC/128
1 0 FOSC/16 FOSC/128
1 1 FOSC/4 FOSC/32
Note: During the ABD sequence, SPBRG and
SPBRGH registers are both used as a 16-bit
counter, independent of BRG16 setting.
BRG Value
RX pin
ABDEN bit
RCIF bit
bit 0 bit 1
(Interrupt)
Read
RCREG
BRG Clock
Start
Set by User Auto Cleared
XXXXh 0000h
Edge #1
bit 2 bit 3
Edge #2
bit 4 bit 5
Edge #3
bit 6 bit 7
Edge #4
Stop bit
Edge #5
001Ch
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
SPBRG XXh 1Ch
SPBRGH XXh 00h
RCIDL
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DS41350E-page 198 Preliminary 2010 Microchip Technology Inc.
16.3.2 AUTO-BAUD OVERFLOW
During the course of automatic baud detection, the
ABDOVF bit of the BAUDCON register will be set if the
baud rate counter overflows before the fifth rising edge
is detected on the RX pin. The ABDOVF bit indicates
that the counter has exceeded the maximum count that
can fit in the 16 bits of the SPBRGH:SPBRG register
pair. After the ABDOVF has been set, the counter continues
to count until the fifth rising edge is detected on
the RX pin. Upon detecting the fifth RX edge, the hardware
will set the RCIF Interrupt Flag and clear the
ABDEN bit of the BAUDCON register. The RCIF flag
can be subsequently cleared by reading the RCREG
register. The ABDOVF flag of the BAUDCON register
can be cleared by software directly.
To terminate the auto-baud process before the RCIF
flag is set, clear the ABDEN bit then clear the ABDOVF
bit of the BAUDCON register. The ABDOVF bit will
remain set if the ABDEN bit is not cleared first.
16.3.3 AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The Auto-Wake-up feature allows the
controller to wake-up due to activity on the RX/DT line.
This feature is available only in Asynchronous mode.
The Auto-Wake-up feature is enabled by setting the
WUE bit of the BAUDCON register. Once set, the normal
receive sequence on RX/DT is disabled, and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 16-7), and asynchronously if
the device is in Sleep mode (Figure 16-8). The interrupt
condition is cleared by reading the RCREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.
16.3.3.1 Special Considerations
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all ‘0’s. This must be 10 or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
Oscillator Startup Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared by
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared by software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
2010 Microchip Technology Inc. Preliminary DS41350E-page 199
PIC18F/LF1XK50
FIGURE 16-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
FIGURE 16-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2Q3Q4 Q1Q2Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3 Q4 Q1Q2 Q3Q4
OSC1
WUE bit
RX/DT Line
RCIF
Bit set by user Auto Cleared
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1 Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
OSC1
WUE bit
RX/DT Line
RCIF
Bit Set by User Auto Cleared
Cleared due to User Read of RCREG
Sleep Command Executed
Note 1
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Sleep Ends
PIC18F/LF1XK50
DS41350E-page 200 Preliminary 2010 Microchip Technology Inc.
16.3.4 BREAK CHARACTER SEQUENCE
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 ‘0’ bits and a Stop bit.
To send a Break character, set the SENDB and TXEN
bits of the TXSTA register. The Break character transmission
is then initiated by a write to the TXREG. The
value of data written to TXREG will be ignored and all
‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The TRMT bit of the TXSTA register indicates when the
transmit operation is active or Idle, just as it does during
normal transmission. See Figure 16-9 for the timing of
the Break character sequence.
16.3.4.1 Break and Sync Transmit Sequence
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
16.3.5 RECEIVING A BREAK CHARACTER
The Enhanced EUSART module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RCSTA register and the Received data
as indicated by RCREG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
A Break character has been received when;
• RCIF bit is set
• FERR bit is set
• RCREG = 00h
The second method uses the Auto-Wake-up feature
described in Section 16.3.3 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RCIF interrupt, and receive the next data byte followed
by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUDCON register before placing the EUSART in
Sleep mode.
FIGURE 16-9: SEND BREAK CHARACTER SEQUENCE
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
Start bit bit 0 bit 1 bit 11 Stop bit
Break
TXIF bit
(Transmit
interrupt Flag)
TX (pin)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB
(send Break
control bit)
SENDB Sampled Here Auto Cleared
2010 Microchip Technology Inc. Preliminary DS41350E-page 201
PIC18F/LF1XK50
16.4 EUSART Synchronous Mode
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary
circuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and
transmit shift registers. Since the data line is
bidirectional, synchronous operation is half-duplex
only. Half-duplex refers to the fact that master and
slave devices can receive and transmit data but not
both simultaneously. The EUSART can operate as
either a master or slave device.
Start and Stop bits are not used in synchronous
transmissions.
16.4.1 SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART
for Synchronous Master operation:
• SYNC = 1
• CSRC = 1
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Setting the CSRC
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
The TRIS bits corresponding to the RX/DT and TX/CK
pins should be set.
16.4.1.1 Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a master transmits the clock on the TX/CK line. The
TX/CK pin output driver is automatically enabled when
the EUSART is configured for synchronous transmit or
receive operation. Serial data bits change on the leading
edge to ensure they are valid at the trailing edge of each
clock. One clock cycle is generated for each data bit.
Only as many clock cycles are generated as there are
data bits.
16.4.1.2 Clock Polarity
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the CKTXP
bit of the BAUDCON register. Setting the CKTXP bit
sets the clock Idle state as high. When the CKTXP bit
is set, the data changes on the falling edge of each
clock and is sampled on the rising edge of each clock.
Clearing the CKTXP bit sets the Idle state as low. When
the CKTXP bit is cleared, the data changes on the
rising edge of each clock and is sampled on the falling
edge of each clock.
16.4.1.3 Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are automatically
enabled when the EUSART is configured for
synchronous master transmit operation.
A transmission is initiated by writing a character to the
TXREG register. If the TSR still contains all or part of a
previous character the new character data is held in the
TXREG until the last bit of the previous character has
been transmitted. If this is the first character, or the previous
character has been completely flushed from the
TSR, the data in the TXREG is immediately transferred
to the TSR. The transmission of the character commences
immediately following the transfer of the data
to the TSR from the TXREG.
Each data bit changes on the leading edge of the master
clock and remains valid until the subsequent leading
clock edge.
16.4.1.4 Data Polarity
The polarity of the transmit and receive data can be
controlled with the DTRXP bit of the BAUDCON register.
The default state of this bit is ‘0’ which selects high
true transmit and receive data. Setting the DTRXP bit
to ‘1’ will invert the data resulting in low true transmit
and receive data.
Note: The TSR register is not mapped in data
memory, so it is not available to the user.
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DS41350E-page 202 Preliminary 2010 Microchip Technology Inc.
16.4.1.5 Synchronous Master Transmission
Set-up:
1. Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 16.3 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC. Set the
TRIS bits corresponding to the RX/DT and
TX/CK I/O pins.
3. Disable Receive mode by clearing bits SREN
and CREN.
4. Enable Transmit mode by setting the TXEN bit.
5. If 9-bit transmission is desired, set the TX9 bit.
6. If interrupts are desired, set the TXIE, GIE and
PEIE interrupt enable bits.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
8. Start transmission by loading data to the TXREG
register.
FIGURE 16-10: SYNCHRONOUS TRANSMISSION
FIGURE 16-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
bit 0 bit 1 bit 7
Word 1
bit 2 bit 0 bit 1 bit 7
RX/DT
Write to
TXREG Reg
TXIF bit
(Interrupt Flag)
TXEN bit
‘1’ ‘1’
Word 2
TRMT bit
Write Word 1 Write Word 2
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
pin
TX/CK pin
TX/CK pin
(SCKP = 0)
(SCKP = 1)
RX/DT pin
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bit
2010 Microchip Technology Inc. Preliminary DS41350E-page 203
PIC18F/LF1XK50
TABLE 16-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
16.4.1.6 Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver must be disabled by setting the
corresponding TRIS bits when the EUSART is
configured for synchronous master receive operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial character
is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the
character is automatically transferred to the two
character receive FIFO. The Least Significant eight bits
of the top character in the receive FIFO are available in
RCREG. The RCIF bit remains set as long as there are
un-read characters in the receive FIFO.
16.4.1.7 Slave Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The
TX/CK pin output driver must be disabled by setting the
associated TRIS bit when the device is configured for
synchronous slave transmit or receive operation. Serial
data bits change on the leading edge to ensure they are
valid at the trailing edge of each clock. One data bit is
transferred for each clock cycle. Only as many clock
cycles should be received as there are data bits.
16.4.1.8 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
TXREG EUSART Transmit Register 287
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 287
SPBRGH EUSART Baud Rate Generator Register, High Byte 287
SPBRG EUSART Baud Rate Generator Register, Low Byte 287
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
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DS41350E-page 204 Preliminary 2010 Microchip Technology Inc.
16.4.1.9 Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.
16.4.1.10 Synchronous Master Reception
Set-up:
1. Initialize the SPBRGH, SPBRG register pair for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC. Disable
RX/DT and TX/CK output drivers by setting the
corresponding TRIS bits.
3. Ensure bits CREN and SREN are clear.
4. If using interrupts, set the GIE and PEIE bits of
the INTCON register and set RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
7. Interrupt flag bit RCIF will be set when reception
of a character is complete. An interrupt will be
generated if the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
FIGURE 16-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)
2010 Microchip Technology Inc. Preliminary DS41350E-page 205
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TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
16.4.2 SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
RX/DT and TX/CK pin output drivers must be disabled
by setting the corresponding TRIS bits.
16.4.2.1 EUSART Synchronous Slave
Transmit
The operation of the Synchronous Master and Slave
modes are identical (see Section 16.4.1.3
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1. The first character will immediately transfer to
the TSR register and transmit.
2. The second word will remain in TXREG register.
3. The TXIF bit will not be set.
4. After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
5. If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
16.4.2.2 Synchronous Slave Transmission
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit. Set the TRIS bits corresponding to
the RX/DT and TX/CK I/O pins.
2. Clear the CREN and SREN bits.
3. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
4. If 9-bit transmission is desired, set the TX9 bit.
5. Enable transmission by setting the TXEN bit.
6. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
7. Start transmission by writing the Least
Significant 8 bits to the TXREG register.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
RCREG EUSART Receive Register 287
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 287
SPBRGH EUSART Baud Rate Generator Register, High Byte 287
SPBRG EUSART Baud Rate Generator Register, Low Byte 287
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
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DS41350E-page 206 Preliminary 2010 Microchip Technology Inc.
TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
16.4.2.3 EUSART Synchronous Slave
Reception
The operation of the Synchronous Master and Slave
modes is identical (Section 16.4.1.6 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
never Idle
• SREN bit, which is a “don't care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
16.4.2.4 Synchronous Slave Reception
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit. Set the TRIS bits corresponding to
the RX/DT and TX/CK I/O pins.
2. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
RCIE bit.
3. If 9-bit reception is desired, set the RX9 bit.
4. Set the CREN bit to enable reception.
5. The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
6. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
7. Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
8. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
TXREG EUSART Transmit Register 287
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 287
SPBRGH EUSART Baud Rate Generator Register, High Byte 287
SPBRG EUSART Baud Rate Generator Register, Low Byte 287
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
2010 Microchip Technology Inc. Preliminary DS41350E-page 207
PIC18F/LF1XK50
TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
RCREG EUSART Receive Register 287
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 287
SPBRGH EUSART Baud Rate Generator Register, High Byte 287
SPBRG EUSART Baud Rate Generator Register, Low Byte 287
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
PIC18F/LF1XK50
DS41350E-page 208 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 209
PIC18F/LF1XK50
17.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
The ADC voltage reference is software selectable to
either VDD, or a voltage applied to the external reference
pins.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
Figure 17-1 shows the block diagram of the ADC.
FIGURE 17-1: ADC BLOCK DIAGRAM
ADC
AN4
AVDD
VREF+
ADON
GO/DONE
CHS<3:0>
ADRESH ADRESL
10
10
ADFM
VSS
AN5
AN6
AN7
AN3
AN8
AN9
AN10
AN11
AVSS
VREFNVCFG[
1:0] = 00
FVR
0000
0001
0010
0011
0100
0101
0111
0110
1000
1001
1010
1011
1100
1101
1110
1111
Unused
Unused
0 = Left Justify
1 = Right Justify
Unused
Unused
Unused
DAC
NVCFG[1:0] = 01
FVR
PVCFG[1:0] = 00
PVCFG[1:0] = 01
PVCFG[1:0] = 10
PIC18F/LF1XK50
DS41350E-page 210 Preliminary 2010 Microchip Technology Inc.
17.1 ADC Configuration
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• Results formatting
17.1.1 PORT CONFIGURATION
The ANSEL, ANSELH, TRISA, TRISB and TRISE registers
all configure the A/D port pins. Any port pin
needed as an analog input should have its corresponding
ANSx bit set to disable the digital input buffer and
TRISx bit set to disable the digital output driver. If the
TRISx bit is cleared, the digital output level (VOH or
VOL) will be converted.
The A/D operation is independent of the state of the
ANSx bits and the TRIS bits.
17.1.2 CHANNEL SELECTION
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 17.2
“ADC Operation” for more information.
17.1.3 ADC VOLTAGE REFERENCE
The PVCFG and NVCFG bits of the ADCON1 register
provide independent control of the positive and
negative voltage references, respectively. The positive
voltage reference can be either VDD, FVR or an
external voltage source. The negative voltage
reference can be either VSS or an external voltage
source.
17.1.4 SELECTING AND CONFIGURING
ACQUISITION TIME
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
Acquisition time is set with the ACQT<2:0> bits of the
ADCON2 register. Acquisition delays cover a range of
2 to 20 TAD. When the GO/DONE bit is set, the A/D
module continues to sample the input for the selected
acquisition time, then automatically begins a conversion.
Since the acquisition time is programmed, there is
no need to wait for an acquisition time between selecting
a channel and setting the GO/DONE bit.
Manual acquisition is selected when
ACQT<2:0> = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT<2:0> bits and
is compatible with devices that do not offer
programmable acquisition times.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. When an acquisition time is programmed, there
is no indication of when the acquisition time ends and
the conversion begins.
17.1.5 CONVERSION CLOCK
The source of the conversion clock is software selectable
via the ADCS bits of the ADCON2 register. There
are seven possible clock options:
• FOSC/2
• FOSC/4
• FOSC/8
• FOSC/16
• FOSC/32
• FOSC/64
• FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11 TAD periods
as shown in Figure 17-3.
For correct conversion, the appropriate TAD specification
must be met. See A/D conversion requirements in
Table 27-9 for more information. Table 17-1 gives
examples of appropriate ADC clock selections.
Note 1: When reading the PORT register, all pins
with their corresponding ANSx bit set
read as cleared (a low level). However,
analog conversion of pins configured as
digital inputs (ANSx bit cleared and
TRISx bit set) will be accurately
converted.
2: Analog levels on any pin with the corresponding
ANSx bit cleared may cause
the digital input buffer to consume current
out of the device’s specification limits.
Note: Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
2010 Microchip Technology Inc. Preliminary DS41350E-page 211
PIC18F/LF1XK50
17.1.6 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
Conversion. The ADC interrupt flag is the ADIF bit in
the PIR1 register. The ADC interrupt enable is the ADIE
bit in the PIE1 register. The ADIF bit must be cleared by
software.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine. Please see Section 17.1.6
“Interrupts” for more information.
TABLE 17-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
17.1.7 RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON2 register controls the output format.
Figure 17-2 shows the two output formats.
FIGURE 17-2: 10-BIT A/D CONVERSION RESULT FORMAT
Note: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC Clock Source ADCS<2:0> 48 MHz 16 MHz 4 MHz 1 MHz
FOSC/2 000 41.67 ns(2) 125 ns(2) 500 ns(2) 2.0 s
FOSC/4 100 83.33 ns(2) 250 ns(2) 1.0 s 4.0 s
FOSC/8 001 167 ns(2) 500 ns(2) 2.0 s 8.0 s(3)
FOSC/16 101 333 ns(2) 1.0 s 4.0 s 16.0 s(3)
FOSC/32 010 667 ns(2) 2.0 s 8.0 s(3) 32.0 s(3)
FOSC/64 110 1.33 s 4.0 s 16.0 s(3) 64.0 s(3)
FRC x11 1-4 s(1,4) 1-4 s(1,4) 1-4 s(1,4) 1-4 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.7 s.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
10-bit A/D Result Unimplemented: Read as ‘0’
(ADFM = 1) MSB LSB
bit 7 bit 0 bit 7 bit 0
Unimplemented: Read as ‘0’ 10-bit A/D Result
PIC18F/LF1XK50
DS41350E-page 212 Preliminary 2010 Microchip Technology Inc.
17.2 ADC Operation
17.2.1 STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will, depending
on the ACQT bits of the ADCON2 register, either
immediately start the Analog-to-Digital conversion or
start an acquisition delay followed by the Analog-to-
Digital conversion.
Figure 17-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT<2:0> bits
are cleared. A conversion is started after the following
instruction to allow entry into SLEEP mode before the
conversion begins.
Figure 17-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT<2:0> bits
are set to ‘010’ which selects a 4 TAD acquisition time
before the conversion starts.
FIGURE 17-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 17-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note: The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 17.2.9 “A/D Conversion
Procedure”.
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD11
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TCY - TAD TAD9 TAD10
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
On the following cycle:
2 TAD
Discharge
1 2 3 4 5 6 7 8 11
Set GO bit
(Holding capacitor is disconnected from analog input)
9 10
Conversion starts
1 2 3 4
(Holding capacitor continues
acquiring input)
TACQT Cycles TAD Cycles
Automatic
Acquisition
Time
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
On the following cycle:
2 TAD
Discharge
2010 Microchip Technology Inc. Preliminary DS41350E-page 213
PIC18F/LF1XK50
17.2.2 COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF flag bit
• Update the ADRESH:ADRESL registers with new
conversion result
17.2.3 DISCHARGE
The discharge phase is used to initialize the value of
the capacitor array. The array is discharged after every
sample. This feature helps to optimize the unity-gain
amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
17.2.4 TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared by software. The
ADRESH:ADRESL registers will be updated with the
partially complete Analog-to-Digital conversion
sample. Unconverted bits will match the last bit
converted.
17.2.5 DELAY BETWEEN CONVERSIONS
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can
be started. After this wait, the currently selected
channel is reconnected to the charge holding capacitor
commencing the next acquisition.
17.2.6 ADC OPERATION IN POWERMANAGED
MODES
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the clock source to be used in that
mode. After entering the mode, an A/D acquisition or
conversion may be started. Once started, the device
should continue to be clocked by the same clock
source until the conversion has been completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D FRC
clock source should be selected.
17.2.7 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conversion
to be aborted and the ADC module is turned off,
although the ADON bit remains set.
17.2.8 SPECIAL EVENT TRIGGER
The CCP1 Special Event Trigger allows periodic ADC
measurements without software intervention. When
this trigger occurs, the GO/DONE bit is set by hardware
and the Timer1 or Timer3 counter resets to zero.
Using the Special Event Trigger does not assure proper
ADC timing. It is the user’s responsibility to ensure that
the ADC timing requirements are met.
See Section 14.3.4 “Special Event Trigger” for more
information.
Note: A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
PIC18F/LF1XK50
DS41350E-page 214 Preliminary 2010 Microchip Technology Inc.
17.2.9 A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1. Configure Port:
• Disable pin output driver (See TRIS register)
• Configure pin as analog
2. Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Select result format
• Select acquisition delay
• Turn on ADC module
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
4. Wait the required acquisition time(2).
5. Start conversion by setting the GO/DONE bit.
6. Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 17-1: A/D CONVERSION
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Software delay required if ACQT bits are
set to zero delay. See Section 17.3 “A/D
Acquisition Requirements”.
;This code block configures the ADC
;for polling, Vdd and Vss as reference, Frc
clock and AN4 input.
;
;Conversion start & polling for completion
; are included.
;
MOVLW B’10101111’ ;right justify, Frc,
MOVWF ADCON2 ; & 12 TAD ACQ time
MOVLW B’00000000’ ;ADC ref = Vdd,Vss
MOVWF ADCON1 ;
BSF TRISC,0 ;Set RC0 to input
BSF ANSEL,4 ;Set RC0 to analog
MOVLW B’00010001’ ;AN4, ADC on
MOVWF ADCON0 ;
BSF ADCON0,GO ;Start conversion
ADCPoll:
BTFSC ADCON0,GO ;Is conversion done?
BRA ADCPoll ;No, test again
; Result is complete - store 2 MSbits in
; RESULTHI and 8 LSbits in RESULTLO
MOVFF ADRESH,RESULTHI
MOVFF ADRESL,RESULTLO
2010 Microchip Technology Inc. Preliminary DS41350E-page 215
PIC18F/LF1XK50
17.2.10 ADC REGISTER DEFINITIONS
The following registers are used to control the operation
of the ADC.
Note: Analog pin control is performed by the
ANSEL and ANSELH registers. For
ANSEL and ANSELH registers, see
Register 9-15 and Register 9-16,
respectively.
REGISTER 17-1: ADCON0: A/D CONTROL REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-2 CHS<3:0>: Analog Channel Select bits
0000 = Reserved
0001 = Reserved
0010 = Reserved
0011 = AN3
0100 = AN4
0101 = AN5
0110 = AN6
0111 = AN7
1000 = AN8
1001 = AN9
1010 = AN10
1011 = AN11
1100 = Reserved
1101 = Reserved
1110 = DAC
1111 = FVR
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1: Selecting reserved channels will yield unpredictable results as unimplemented input channels are left
floating.
PIC18F/LF1XK50
DS41350E-page 216 Preliminary 2010 Microchip Technology Inc.
REGISTER 17-2: ADCON1: A/D CONTROL REGISTER 1
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — PVCFG1 PVCFG0 NVCFG1 NVCFG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3-2 PVCFG<1:0>: Positive Voltage Reference select bit
00 = Positive voltage reference supplied internally by VDD.
01 = Positive voltage reference supplied externally through VREF+ pin.
10 = Positive voltage reference supplied internally through FVR.
11 = Reserved.
bit 1-0 NVCFG<1:0>: Negative Voltage Reference select bit
00 = Negative voltage reference supplied internally by VSS.
01 = Negative voltage reference supplied externally through VREF- pin.
10 = Reserved.
11 = Reserved.
2010 Microchip Technology Inc. Preliminary DS41350E-page 217
PIC18F/LF1XK50
REGISTER 17-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ADFM: A/D Conversion Result Format Select bit
1 = Right justified
0 = Left justified
bit 6 Unimplemented: Read as ‘0’
bit 5-3 ACQT<2:0>: A/D Acquisition time select bits. Acquisition time is the duration that the A/D charge
holding capacitor remains connected to A/D channel from the instant the GO/DONE bit is set until
conversions begins.
000 = 0(1)
001 = 2 TAD
010 = 4 TAD
011 = 6 TAD
100 = 8 TAD
101 = 12 TAD
110 = 16 TAD
111 = 20 TAD
bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal)
Note 1: When the A/D clock source is selected as FRC then the start of conversion is delayed by one instruction
cycle after the GO/DONE bit is set to allow the SLEEP instruction to be executed.
PIC18F/LF1XK50
DS41350E-page 218 Preliminary 2010 Microchip Technology Inc.
REGISTER 17-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ADRES<9:2>: ADC Result Register bits
Upper 8 bits of 10-bit conversion result
REGISTER 17-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES1 ADRES0 — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 ADRES<1:0>: ADC Result Register bits
Lower 2 bits of 10-bit conversion result
bit 5-0 Reserved: Do not use.
REGISTER 17-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— — — — — — ADRES9 ADRES8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Reserved: Do not use.
bit 1-0 ADRES<9:8>: ADC Result Register bits
Upper 2 bits of 10-bit conversion result
REGISTER 17-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ADRES<7:0>: ADC Result Register bits
Lower 8 bits of 10-bit conversion result
2010 Microchip Technology Inc. Preliminary DS41350E-page 219
PIC18F/LF1XK50
17.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 17-5. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 17-5.
The maximum recommended impedance for analog
sources is 10 k. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 17-1 may be used. This equation
assumes that 1/2 LSb error is used (1024 steps for the
ADC). The 1/2 LSb error is the maximum error allowed
for the ADC to meet its specified resolution.
EQUATION 17-1: ACQUISITION TIME EXAMPLE
TACQ Amplifier Settling Time Hold Capacitor Charging = + Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 5μs + TC + Temperature - 25°C0.05μs/°C
TC = –CHOLDRIC + RSS + RS ln(1/2047)
= –13.5pF1k + 700 + 10k ln(0.0004885)
= 1.20μs
TACQ = 5μs + 1.20μs + 50°C- 25°C0.05μs/°C
= 7.45μs
VAPPLIED 1 e
–Tc
-R----C----
–
VAPPLIED 1 1
– -2---0---4---7-
=
VAPPLIED 1 1
– -2---0---4---7-
= VCHOLD
VAPPLIED 1 e
–TC
--R----C---
–
= VCHOLD
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
The value for TC can be approximated with the following equations:
Solving for TC:
Therefore:
Assumptions: Temperature = 50°C and external impedance of 10k 3.0V VDD
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
PIC18F/LF1XK50
DS41350E-page 220 Preliminary 2010 Microchip Technology Inc.
FIGURE 17-5: ANALOG INPUT MODEL
FIGURE 17-6: ADC TRANSFER FUNCTION
VA CPIN
Rs ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V I LEAKAGE(1)
RIC 1k
Sampling
Switch
SS Rss
CHOLD = 13.5 pF
VSS/VREF-
2.5V
Rss (k)
2.0V
1.5V
.1 1 10
VDD
Legend: CPIN
VT
I LEAKAGE
RIC
SS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance
various junctions
Discharge
Switch
3.0V
3.5V
100
Note 1: See Section 27.0 “Electrical Specifications”.
3FFh
3FEh
ADC Output Code
3FDh
3FCh
004h
003h
002h
001h
000h
Full-Scale
3FBh
1/2 LSB ideal
VSS/VREF- Zero-Scale
Transition
VDD/VREF+
Transition
1/2 LSB ideal
Full-Scale Range
Analog Input Voltage
2010 Microchip Technology Inc. Preliminary DS41350E-page 221
PIC18F/LF1XK50
TABLE 17-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
ADRESH A/D Result Register, High Byte 287
ADRESL A/D Result Register, Low Byte 287
ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 287
ADCON1 — — — — PVCFG1 PVCFG0 NVCFG1 NVCFG0 287
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 287
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 — — — 288
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 288
TRISA – – TRISA5 TRISA4 – – – – 288
TRISB TRISB7 TRISB6 TRISB5 TRISB4 – – – – 288
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
PIC18F/LF1XK50
DS41350E-page 222 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 223
PIC18F/LF1XK50
18.0 COMPARATOR MODULE
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
The comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of the program execution. The Analog
Comparator module includes the following features:
• Independent comparator control
• Programmable input selection
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
• Wake-up from Sleep
• Programmable Speed/Power optimization
• PWM shutdown
• Programmable and fixed voltage reference
18.1 Comparator Overview
A single comparator is shown in Figure 18-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
FIGURE 18-1: SINGLE COMPARATOR
–
VIN+ +
VINOutput
Output
VIN+
VINNote:
The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
PIC18F/LF1XK50
DS41350E-page 224 Preliminary 2010 Microchip Technology Inc.
FIGURE 18-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.
4: Positive going pulse generated on both falling and rising edges of the bit.
MUX
C1
C1POL
C1OUT To PWM Logic
0
1
2
3
C1ON(1)
C1CH<1:0>
2
0
1
C1R
MUX
RD_CM1CON0
Set C1IF
To
C1VINC1VIN+
AGND
C12IN1-
C12IN2-
C12IN3-
C1IN+
D Q
Q1 EN
Data Bus
D Q
EN
CL
Q3*RD_CM1CON0
NReset
+
-
0
1
MUX
VREF
C1RSEL
FVR
C1SP
C1VREF C1OE
C12OUT
0
1
C1SYNC
From TMR1L[0](4)
D Q
SYNCC1OUT
C2OE
2010 Microchip Technology Inc. Preliminary DS41350E-page 225
PIC18F/LF1XK50
FIGURE 18-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
MUX
C2
C2POL
C2OUT To PWM Logic
0
1
2
3
C2ON(1)
C2CH<1:0>
2 D Q
EN
D Q
EN
CL
RD_CM2CON0
Q3*RD_CM2CON0
Q1
Set C2IF
To
NRESET
C2VINC2VIN+
C12OUT pin
AGND
C12IN1-
C12IN2-
C12IN3-
Data Bus
Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.
4: Positive going pulse generated on both falling and rising edges of the bit.
0
1
C2R
MUX
C2IN+
0
1
MUX
VREF
C2RSEL
FVR
C2SP
C2VREF
0
1
C2SYNC
C20E
D Q
From TMR1L[0] SYNCC2OUT (4)
PIC18F/LF1XK50
DS41350E-page 226 Preliminary 2010 Microchip Technology Inc.
18.2 Comparator Control
Each comparator has a separate control and
Configuration register: CM1CON0 for Comparator C1
and CM2CON0 for Comparator C2. In addition,
Comparator C2 has a second control register,
CM2CON1, for controlling the interaction with Timer1 and
simultaneous reading of both comparator outputs.
The CM1CON0 and CM2CON0 registers (see Registers
18-1 and 18-2, respectively) contain the control and
status bits for the following:
• Enable
• Input selection
• Reference selection
• Output selection
• Output polarity
• Speed selection
18.2.1 COMPARATOR ENABLE
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
18.2.2 COMPARATOR INPUT SELECTION
The CxCH<1:0> bits of the CMxCON0 register direct
one of four analog input pins to the comparator
inverting input.
18.2.3 COMPARATOR REFERENCE
SELECTION
Setting the CxR bit of the CMxCON0 register directs an
internal voltage reference or an analog input pin to the
non-inverting input of the comparator. See
Section 21.0 “VOLTAGE REFERENCES” for more
information on the Internal Voltage Reference module.
18.2.4 COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CM2CON1 register. In order
to make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
Both comparators share the same output pin
(C12OUT). Priority is determined by the states of the
C1OE and C2OE bits.
TABLE 18-1: COMPARATOR OUTPUT
PRIORITY
18.2.5 COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Table 18-2 shows the output state versus input
conditions, including polarity control.
18.2.6 COMPARATOR SPEED SELECTION
The trade-off between speed or power can be optimized
during program execution with the CxSP control
bit. The default state for this bit is ‘1’ which selects the
normal speed mode. Device power consumption can
be optimized at the cost of slower comparator propagation
delay by clearing the CxSP bit to ‘0’.
18.3 Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the
comparator differs from the settling time of the voltage
reference. Therefore, both of these times must be
considered when determining the total response time
to a comparator input change. See the Comparator and
Voltage Reference Specifications in Section 27.0
“Electrical Specifications” for more details.
Note: To use CxIN+ and C12INx- pins as analog
inputs, the appropriate bits must be set in
the ANSEL register and the
corresponding TRIS bits must also be set
to disable the output drivers.
C10E C2OE C12OUT
0 0 I/O
0 1 C2OUT
1 0 C1OUT
1 1 C2OUT
Note 1: The CxOE bit overrides the PORT data
latch. Setting the CxON has no impact on
the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
TABLE 18-2: COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition CxPOL CxOUT
CxVIN- > CxVIN+ 0 0
CxVIN- < CxVIN+ 0 1
CxVIN- > CxVIN+ 1 1
CxVIN- < CxVIN+ 1 0
2010 Microchip Technology Inc. Preliminary DS41350E-page 227
PIC18F/LF1XK50
18.4 Comparator Interrupt Operation
The comparator interrupt flag can be set whenever
there is a change in the output value of the comparator.
Changes are recognized by means of a mismatch
circuit which consists of two latches and an exclusiveor
gate (see Figure 18-2 and Figure 18-3). One latch is
updated with the comparator output level when the
CMxCON0 register is read. This latch retains the value
until the next read of the CMxCON0 register or the
occurrence of a Reset. The other latch of the mismatch
circuit is updated on every Q1 system clock. A
mismatch condition will occur when a comparator
output change is clocked through the second latch on
the Q1 clock cycle. At this point the two mismatch
latches have opposite output levels which is detected
by the exclusive-or gate and fed to the interrupt
circuitry. The mismatch condition persists until either
the CMxCON0 register is read or the comparator
output returns to the previous state.
The comparator interrupt is set by the mismatch edge
and not the mismatch level. This means that the interrupt
flag can be reset without the additional step of
reading or writing the CMxCON0 register to clear the
mismatch registers. When the mismatch registers are
cleared, an interrupt will occur upon the comparator’s
return to the previous state, otherwise no interrupt will
be generated.
Software will need to maintain information about the
status of the comparator output, as read from the
CMxCON0 register, or CM2CON1 register, to determine
the actual change that has occurred. See Figures 18-4
and 18-5.
The CxIF bit of the PIR2 register is the comparator
interrupt flag. This bit must be reset by software by
clearing it to ‘0’. Since it is also possible to write a ‘1’ to
this register, an interrupt can be generated.
In mid-range Compatibility mode the CxIE bit of the
PIE2 register and the PEIE and GIE bits of the INTCON
register must all be set to enable comparator interrupts.
If any of these bits are cleared, the interrupt is not
enabled, although the CxIF bit of the PIR2 register will
still be set if an interrupt condition occurs.
18.4.1 PRESETTING THE MISMATCH
LATCHES
The comparator mismatch latches can be preset to the
desired state before the comparators are enabled.
When the comparator is off the CxPOL bit controls the
CxOUT level. Set the CxPOL bit to the desired CxOUT
non-interrupt level while the CxON bit is cleared. Then,
configure the desired CxPOL level in the same instruction
that the CxON bit is set. Since all register writes are
performed as a Read-Modify-Write, the mismatch
latches will be cleared during the instruction Read
phase and the actual configuration of the CxON and
CxPOL bits will be occur in the final Write phase.
FIGURE 18-4: COMPARATOR
INTERRUPT TIMING W/O
CMxCON0 READ
FIGURE 18-5: COMPARATOR
INTERRUPT TIMING WITH
CMxCON0 READ
Note 1: A write operation to the CMxCON0
register will also clear the mismatch
condition because all writes include a read
operation at the beginning of the write
cycle.
2: Comparator interrupts will operate
correctly regardless of the state of CxOE.
Note 1: If a change in the CMxCON0 register
(CxOUT) should occur when a read operation
is being executed (start of the Q2
cycle), then the CxIF interrupt flag of the
PIR2 register may not get set.
2: When either comparator is first enabled,
bias circuitry in the Comparator module
may cause an invalid output from the
comparator until the bias circuitry is
stable. Allow about 1 s for bias settling
then clear the mismatch condition and
interrupt flags before enabling comparator
interrupts.
Q1
Q3
CxIN+
CxOUT
Set CxIF (edge)
CxIF
TRT
Reset by Software
Q1
Q3
CxIN+
CxOUT
Set CxIF (edge)
CxIF
TRT
Cleared by CMxCON0 Read Reset by Software
PIC18F/LF1XK50
DS41350E-page 228 Preliminary 2010 Microchip Technology Inc.
18.5 Operation During Sleep
The comparator, if enabled before entering Sleep mode,
remains active during Sleep. The additional current
consumed by the comparator is shown separately in the
Section 27.0 “Electrical Specifications”. If the
comparator is not used to wake the device, power
consumption can be minimized while in Sleep mode by
turning off the comparator. Each comparator is turned off
by clearing the CxON bit of the CMxCON0 register.
A change to the comparator output can wake-up the
device from Sleep. To enable the comparator to wake
the device from Sleep, the CxIE bit of the PIE2 register
and the PEIE bit of the INTCON register must be set.
The instruction following the SLEEP instruction always
executes following a wake from Sleep. If the GIE bit of
the INTCON register is also set, the device will then
execute the Interrupt Service Routine.
18.6 Effects of a Reset
A device Reset forces the CMxCON0 and CM2CON1
registers to their Reset states. This forces both
comparators and the voltage references to their Off
states.
2010 Microchip Technology Inc. Preliminary DS41350E-page 229
PIC18F/LF1XK50
REGISTER 18-1: CM1CON0: COMPARATOR 1 CONTROL REGISTER 0
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 C1ON: Comparator C1 Enable bit
1 = Comparator C1 is enabled
0 = Comparator C1 is disabled
bit 6 C1OUT: Comparator C1 Output bit
If C1POL = 1 (inverted polarity):
C1OUT = 0 when C1VIN+ > C1VINC1OUT
= 1 when C1VIN+ < C1VINIf
C1POL = 0 (non-inverted polarity):
C1OUT = 1 when C1VIN+ > C1VINC1OUT
= 0 when C1VIN+ < C1VINbit
5 C1OE: Comparator C1 Output Enable bit
If C2OE = 0 (C2 output disable)
0 = C1OUT is internal only
1 = C1OUT is present on the C12OUT pin(1)
If C2OE = 1 (C2 output enable)
0 = C1OUT is internal only
1 = C2OUT is present on the C12OUT pin(1)
bit 4 C1POL: Comparator C1 Output Polarity Select bit
1 = C1OUT logic is inverted
0 = C1OUT logic is not inverted
bit 3 C1SP: Comparator C1 Speed/Power Select bit
1 = C1 operates in normal power, higher speed mode
0 = C1 operates in low-power, low-speed mode
bit 2 C1R: Comparator C1 Reference Select bit (non-inverting input)
1 = C1VIN+ connects to C1VREF output
0 = C1VIN+ connects to C12IN+ pin
bit 1-0 C1CH<1:0>: Comparator C1 Channel Select bit
00 = C1VIN- connects to AGND
01 = C12IN1- pin of C1 connects to C1VIN-
10 = C12IN2- pin of C1 connects to C1VIN-
11 = C12IN3- pin of C1 connects to C1VINNote
1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding port
TRIS bit = 0.
PIC18F/LF1XK50
DS41350E-page 230 Preliminary 2010 Microchip Technology Inc.
REGISTER 18-2: CM2CON0: COMPARATOR 2 CONTROL REGISTER 0
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 C2ON: Comparator C2 Enable bit
1 = Comparator C2 is enabled
0 = Comparator C2 is disabled
bit 6 C2OUT: Comparator C2 Output bit
If C2POL = 1 (inverted polarity):
C2OUT = 0 when C2VIN+ > C2VINC2OUT
= 1 when C2VIN+ < C2VINIf
C2POL = 0 (non-inverted polarity):
C2OUT = 1 when C2VIN+ > C2VINC2OUT
= 0 when C2VIN+ < C2VINbit
5 C2OE: Comparator C2 Output Enable bit
1 = C2OUT is present on C12OUT pin(1)
0 = C2OUT is internal only
bit 4 C2POL: Comparator C2 Output Polarity Select bit
1 = C2OUT logic is inverted
0 = C2OUT logic is not inverted
bit 3 C2SP: Comparator C2 Speed/Power Select bit
1 = C2 operates in normal power, higher speed mode
0 = C2 operates in low-power, low-speed mode
bit 2 C2R: Comparator C2 Reference Select bits (non-inverting input)
1 = C2VIN+ connects to C2VREF
0 = C2VIN+ connects to C2IN+ pin
bit 1-0 C2CH<1:0>: Comparator C2 Channel Select bits
00 = C1VIN- connects to AGND
01 = C12IN1- pin of C2 connects to C2VIN-
10 = C12IN2- pin of C2 connects to C2VIN-
11 = C12IN3- pin of C2 connects to C2VINNote
1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port
TRIS bit = 0.
2010 Microchip Technology Inc. Preliminary DS41350E-page 231
PIC18F/LF1XK50
18.7 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 18-6. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
FIGURE 18-6: ANALOG INPUT MODEL
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
VA
Rs < 10K
CPIN
5 pF
VDD
VT 0.6V
VT 0.6V
RIC
ILEAKAGE(1)
Vss
AIN
Legend: CPIN = Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
VT = Threshold Voltage
Note 1: See Section 27.0 “Electrical Specifications”.
PIC18F/LF1XK50
DS41350E-page 232 Preliminary 2010 Microchip Technology Inc.
18.8 Additional Comparator Features
There are four additional comparator features:
• Simultaneous read of comparator outputs
• Internal reference selection
• Hysteresis selection
• Output Synchronization
18.8.1 SIMULTANEOUS COMPARATOR
OUTPUT READ
The MC1OUT and MC2OUT bits of the CM2CON1
register are mirror copies of both comparator outputs.
The ability to read both outputs simultaneously from a
single register eliminates the timing skew of reading
separate registers.
18.8.2 INTERNAL REFERENCE
SELECTION
There are two internal voltage references available to
the non-inverting input of each comparator. One of
these is the Fixed Voltage Reference (FVR) and the
other is the variable Comparator Voltage Reference
(CVREF). The CxRSEL bit of the CM2CON register
determines which of these references is routed to the
Comparator Voltage reference output (CXVREF). Further
routing to the comparator is accomplished by the
CxR bit of the CMxCON0 register. See Section 21.1
“Voltage Reference” and Figure 18-2 and Figure 18-3
for more detail.
18.8.3 COMPARATOR HYSTERESIS
The Comparator Cx have selectable hysteresis. The
hysteresis can be enable by setting the CxHYS bit of
the CM2CON1 register. See Section 27.0 “Electrical
Specifications” for more details.
18.8.4 SYNCHRONIZING COMPARATOR
OUTPUT TO TIMER 1
The Comparator Cx output can be synchronized with
Timer1 by setting the CxSYNC bit of the CM2CON1
register. When enabled, the Cx output is latched on
the rising edge of the Timer1 source clock. If a prescaler
is used with Timer1, the comparator output is
latched after the prescaling function. To prevent a
race condition, the comparator output is latched on
the rising edge of the Timer1 clock source and Timer1
increments on the rising edge of its clock source. See
the Comparator Block Diagram (Figure 18-2 and
Figure 18-3) and the Timer1 Block Diagram
(Figure 18-2) for more information.
Note 1: Obtaining the status of C1OUT or
C2OUT by reading CM2CON1 does not
affect the comparator interrupt mismatch
registers.
2010 Microchip Technology Inc. Preliminary DS41350E-page 233
PIC18F/LF1XK50
REGISTER 18-3: CM2CON1: COMPARATOR 2 CONTROL REGISTER 1
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 MC1OUT: Mirror Copy of C1OUT bit
bit 6 MC2OUT: Mirror Copy of C2OUT bit
bit 5 C1RSEL: Comparator C1 Reference Select bit
1 = FVR routed to C1VREF input
0 = CVREF routed to C1VREF input
bit 4 C2RSEL: Comparator C2 Reference Select bit
1 = FVR routed to C2VREF input
0 = CVREF routed to C2VREF input
bit 3 C1HYS: Comparator C1 Hysteresis Enable bit
1 = Comparator C1 hysteresis enabled
0 = Comparator C1 hysteresis disabled
bit 2 C2HYS: Comparator C2 Hysteresis Enable bit
1 = Comparator C2 hysteresis enabled
0 = Comparator C2 hysteresis disabled
bit 1 C1SYNC: C1 Output Synchronous Mode bit
1 = C1 output is synchronous to rising edge to TMR1 clock
0 = C1 output is asynchronous
bit 0 C2SYNC: C2 Output Synchronous Mode bit
1 = C2 output is synchronous to rising edge to TMR1 clock
0 = C2 output is asynchronous
PIC18F/LF1XK50
DS41350E-page 234 Preliminary 2010 Microchip Technology Inc.
TABLE 18-3: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 288
CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 288
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 288
REFCON0 FVR1EN FVR1ST FVR1S1 FVR1S0 — — — — 287
REFCON1 D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 — D1NSS 287
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF — 288
PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE — 288
IPR2 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP — 288
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 288
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 288
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 — — — 288
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
2010 Microchip Technology Inc. Preliminary DS41350E-page 235
PIC18F/LF1XK50
19.0 POWER-MANAGED MODES
PIC18F/LF1XK50 devices offer a total of seven operating
modes for more efficient power management.
These modes provide a variety of options for selective
power conservation in applications where resources
may be limited (i.e., battery-powered devices).
There are three categories of power-managed modes:
• Run modes
• Idle modes
• Sleep mode
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator
block); the Sleep mode does not use a clock source.
The power-managed modes include several powersaving
features offered on previous PIC® microcontroller
devices. One is the clock switching feature which allows
the controller to use the Timer1 oscillator in place of the
primary oscillator. Also included is the Sleep mode,
offered by all PIC® microcontroller devices, where all
device clocks are stopped.
19.1 Selecting Power-Managed Modes
Selecting a power-managed mode requires two
decisions:
• Whether or not the CPU is to be clocked
• The selection of a clock source
The IDLEN bit of the OSCCON register controls CPU
clocking, while the SCS<1:0> bits of the OSCCON
register select the clock source. The individual modes,
bit settings, clock sources and affected modules are
summarized in Table 19-1.
19.1.1 CLOCK SOURCES
The SCS<1:0> bits allow the selection of one of three
clock sources for power-managed modes. They are:
• the primary clock, as defined by the FOSC<3:0>
Configuration bits
• the secondary clock (the Timer1 oscillator)
• the internal oscillator block
19.1.2 ENTERING POWER-MANAGED
MODES
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. Refer to
Section 2.8 “Clock Switching” for more information.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit of the OSCCON register.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured
correctly, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
TABLE 19-1: POWER-MANAGED MODES
Mode
OSCCON Bits Module Clocking
Available Clock and Oscillator Source
IDLEN(1) SCS<1:0> CPU Peripherals
Sleep 0 N/A Off Off None – All clocks are disabled
PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, RC, EC and Internal
Oscillator Block(2).
This is the normal full power execution mode.
SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator
RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2)
PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator
RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2)
Note 1: IDLEN reflects its value when the SLEEP instruction is executed.
2: Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source.
PIC18F/LF1XK50
DS41350E-page 236 Preliminary 2010 Microchip Technology Inc.
19.1.3 MULTIPLE FUNCTIONS OF THE
SLEEP COMMAND
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit of the OSCCON register at the time the
instruction is executed. All clocks stop and minimum
power is consumed when SLEEP is executed with the
IDLEN bit cleared. The system clock continues to supply
a clock to the peripherals but is disconnected from
the CPU when SLEEP is executed with the IDLEN bit
set.
19.2 Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
19.2.1 PRI_RUN MODE
The PRI_RUN mode is the normal, full power execution
mode of the microcontroller. This is also the default
mode upon a device Reset, unless Two-Speed Start-up
is enabled (see Section 2.12 “Two-Speed Start-up
Mode” for details). In this mode, the device operated
off the oscillator defined by the FOSC bits of the
CONFIGH Configuration register.
19.2.2 SEC_RUN MODE
In SEC_RUN mode, the CPU and peripherals are
clocked from the secondary external oscillator. This
gives users the option of lower power consumption
while still using a high accuracy clock source.
SEC_RUN mode is entered by setting the SCS<1:0>
bits of the OSCCON register to ‘01’. When SEC_RUN
mode is active all of the following are true:
• The main clock source is switched to the
secondary external oscillator
• Primary external oscillator is shut down
• T1RUN bit of the T1CON register is set
• OSTS bit is cleared.
19.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator. In this mode, the
primary external oscillator is shut down. RC_RUN
mode provides the best power conservation of all the
Run modes when the LFINTOSC is the system clock.
RC_RUN mode is entered by setting the SCS1 bit.
When the clock source is switched from the primary
oscillator to the internal oscillator, the primary oscillator
is shut down and the OSTS bit is cleared. The IRCF bits
may be modified at any time to immediately change the
clock speed.
Note: The secondary external oscillator should
already be running prior to entering
SEC_RUN mode. If the T1OSCEN bit is
not set when the SCS<1:0> bits are set to
‘01’, entry to SEC_RUN mode will not
occur until T1OSCEN bit is set and secondary
external oscillator is ready.
2010 Microchip Technology Inc. Preliminary DS41350E-page 237
PIC18F/LF1XK50
19.3 Sleep Mode
The Power-Managed Sleep mode in the PIC18F/
LF1XK50 devices is identical to the legacy Sleep mode
offered in all other PIC® microcontroller devices. It is
entered by clearing the IDLEN bit of the OSCCON
register and executing the SLEEP instruction. This shuts
down the selected oscillator (Figure 19-1) and all clock
source status bits are cleared.
Entering the Sleep mode from either Run or Idle mode
does not require a clock switch. This is because no
clocks are needed once the controller has entered
Sleep. If the WDT is selected, the LFINTOSC source
will continue to operate. If the Timer1 oscillator is
enabled, it will also continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see Figure 19-2), or it will be clocked
from the internal oscillator block if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled
(see Section 24.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
19.4 Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected by the SCS<1:0> bits; however, the CPU
will not be clocked. The clock source status bits are not
affected. Setting IDLEN and executing a SLEEP instruction
provides a quick method of switching from a given
Run mode to its corresponding Idle mode.
If the WDT is selected, the LFINTOSC source will continue
to operate. If the Timer1 oscillator is enabled, it
will also continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out, or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD while it
becomes ready to execute code. When the CPU
begins executing code, it resumes with the same clock
source for the current Idle mode. For example, when
waking from RC_IDLE mode, the internal oscillator
block will clock the CPU and peripherals (in other
words, RC_RUN mode). The IDLEN and SCS bits are
not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS<1:0> bits.
FIGURE 19-1: TRANSITION TIMING FOR ENTRY TO SLEEP MODE
FIGURE 19-2: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q2 Q3 Q4
OSC1
Peripheral
Sleep
Program
Q1 Q1
Counter
Clock
CPU
Clock
PC PC + 2
Q3 Q4 Q1 Q2
OSC1
Peripheral
Program PC
PLL Clock
Q3 Q4
Output
CPU Clock
Q1 Q2 Q3 Q4 Q1 Q2
Clock
Counter PC + 4 PC + 6
Q1 Q2 Q3 Q4
Wake Event
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
TOST(1) TPLL(1)
OSTS bit set
PC + 2
PIC18F/LF1XK50
DS41350E-page 238 Preliminary 2010 Microchip Technology Inc.
19.4.1 PRI_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm-up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruction.
If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC<3:0> Configuration bits. The OSTS bit
remains set (see Figure 19-3).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wakeup,
the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see Figure 19-4).
19.4.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by setting
the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS<1:0> bits to ‘01’ and execute
SLEEP. When the clock source is switched to the
Timer1 oscillator, the primary oscillator is shut down,
the OSTS bit is cleared and the T1RUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD following the wake event, the CPU begins executing
code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 19-
4).
FIGURE 19-3: TRANSITION TIMING FOR ENTRY TO IDLE MODE
FIGURE 19-4: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Note: The Timer1 oscillator should already be
running prior to entering SEC_IDLE
mode. If the T1OSCEN bit is not set when
the SLEEP instruction is executed, the
main system clock will continue to operate
in the previously selected mode and the
corresponding IDLE mode will be entered
(i.e., PRI_IDLE or RC_IDLE).
Q1
Peripheral
Program PC PC + 2
OSC1
Q3 Q4 Q1
CPU Clock
Clock
Counter
Q2
OSC1
Peripheral
Program PC
CPU Clock
Q1 Q3 Q4
Clock
Counter
Q2
Wake Event
TCSD
2010 Microchip Technology Inc. Preliminary DS41350E-page 239
PIC18F/LF1XK50
19.4.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the peripherals
continue to be clocked from the internal oscillator
block from the HFINTOSC multiplexer output. This
mode allows for controllable power conservation during
Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. It is recommended
that SCS0 also be cleared, although its value is
ignored, to maintain software compatibility with future
devices. The HFINTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When the
clock source is switched to the HFINTOSC multiplexer,
the primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value, or the
INTSRC bit is set, the HFINTOSC output is enabled.
The IOSF bit becomes set, after the HFINTOSC output
becomes stable, after an interval of TIOBST. Clocks to
the peripherals continue while the HFINTOSC source
stabilizes. If the IRCF bits were previously at a nonzero
value, or INTSRC was set before the SLEEP
instruction was executed and the HFINTOSC source
was already stable, the IOSF bit will remain set. If the
IRCF bits and INTSRC are all clear, the HFINTOSC
output will not be enabled, the IOSF bit will remain clear
and there will be no indication of the current clock
source.
When a wake event occurs, the peripherals continue to
be clocked from the HFINTOSC multiplexer output.
After a delay of TCSD following the wake event, the CPU
begins executing code being clocked by the
HFINTOSC multiplexer. The IDLEN and SCS bits are
not affected by the wake-up. The LFINTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
19.5 Exiting Idle and Sleep Modes
An exit from Sleep mode or any of the Idle modes is
triggered by any one of the following:
• an interrupt
• a Reset
• a Watchdog Time-out
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 19.2 “Run Modes”,
Section 19.3 “Sleep Mode” and Section 19.4 “Idle
Modes”).
19.5.1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode or the Sleep mode to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The PEIE bIt must also
be set If the desired interrupt enable bit is in a PIE
register. The exit sequence is initiated when the
corresponding interrupt flag bit is set.
The instruction immediately following the SLEEP
instruction is executed on all exits by interrupt from Idle
or Sleep modes. Code execution then branches to the
interrupt vector if the GIE/GIEH bit of the INTCON
register is set, otherwise code execution continues
without branching (see Section 7.0 “Interrupts”).
A fixed delay of interval TCSD following the wake event
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
19.5.2 EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 19.2 “Run
Modes” and Section 19.3 “Sleep Mode”). If the
device is executing code (all Run modes), the time-out
will result in a WDT Reset (see Section 24.2 “Watchdog
Timer (WDT)”).
The WDT timer and postscaler are cleared by any one
of the following:
• executing a SLEEP instruction
• executing a CLRWDT instruction
• the loss of the currently selected clock source
when the Fail-Safe Clock Monitor is enabled
• modifying the IRCF bits in the OSCCON register
when the internal oscillator block is the device
clock source
PIC18F/LF1XK50
DS41350E-page 240 Preliminary 2010 Microchip Technology Inc.
19.5.3 EXIT BY RESET
Exiting Sleep and Idle modes by Reset causes code
execution to restart at address 0. See Section 23.0
“Reset” for more details.
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator. Exit
delays are summarized in Table 19-2.
19.5.4 EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped and
• the primary clock source is not any of the LP, XT,
HS or HSPLL modes.
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC, INTOSC,
and INTOSCIO modes). However, a fixed delay of
interval TCSD following the wake event is still required
when leaving Sleep and Idle modes to allow the CPU
to prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
TABLE 19-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
before Wake-up
Clock Source
after Wake-up Exit Delay Clock Ready Status
Bit (OSCCON)
Primary Device Clock
(PRI_IDLE mode)
LP, XT, HS
TCSD HSPLL (1) OSTS
EC, RC
HFINTOSC(2) IOSF
T1OSC or LFINTOSC(1)
LP, XT, HS TOST(3)
HSPLL TOST + tPLL OSTS
(3)
EC, RC TCSD(1)
HFINTOSC(1) TIOBST(4) IOSF
HFINTOSC(2)
LP, XT, HS TOST(4)
HSPLL TOST + tPLL OSTS
(3)
EC, RC TCSD(1)
HFINTOSC(1) None IOSF
None
(Sleep mode)
LP, XT, HS TOST(3)
HSPLL TOST + tPLL OSTS
(3)
EC, RC TCSD(1)
HFINTOSC(1) TIOBST(4) IOSF
Note 1: TCSD is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other
required delays (see Section 19.4 “Idle Modes”). On Reset, HFINTOSC defaults to 1 MHz.
2: Includes both the HFINTOSC 16 MHz source and postscaler derived frequencies.
3: TOST is the Oscillator Start-up Timer. tPLL is the PLL Lock-out Timer (parameter F12).
4: Execution continues during the HFINTOSC stabilization period, TIOBST.
2010 Microchip Technology Inc. Preliminary DS41350E-page 241
PIC18F/LF1XK50
20.0 SR LATCH
The module consists of a single SR Latch with multiple
Set and Reset inputs as well as selectable latch output.
The SR Latch module includes the following features:
• Programmable input selection
• SR Latch output is available internally/externally
• Selectable Q and Q output
• Firmware Set and Reset
20.1 Latch Operation
The latch is a Set-Reset latch that does not depend on a
clock source. Each of the Set and Reset inputs are
active-high. The latch can be Set or Reset by CxOUT,
INT1 pin, or variable clock. Additionally the SRPS and
the SRPR bits of the SRCON0 register may be used to
Set or Reset the SR Latch, respectively. The latch is
reset-dominant, therefore, if both Set and Reset inputs
are high the latch will go to the Reset state. Both the
SRPS and SRPR bits are self resetting which means
that a single write to either of the bits is all that is
necessary to complete a latch Set or Reset operation.
20.2 Latch Output
The SRQEN and SRNQEN bits of the SRCON0 register
control the latch output selection. Only one of the SR
latch’s outputs may be directly output to an I/O pin at a
time. Priority is determined by the state of bits SRQEN
and SRNQEN in registers SRCON0.
TABLE 20-1: SR LATCH OUTPUT
CONTROL
The applicable TRIS bit of the corresponding port must
be cleared to enable the port pin output driver.
20.3 Effects of a Reset
Upon any device Reset, the SR latch is not initialized.
The user’s firmware is responsible to initialize the latch
output before enabling it to the output pins.
FIGURE 20-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM
SRLEN SRQEN SRNQEN SR Latch Output
to Port I/O
0 X X I/O
1 0 0 I/O
1 0 1 Q
1 1 0 Q
1 1 1 Q
SRPS
S
R
Q
Q
Note 1: If R = 1 and S = 1 simultaneously, Q = 0, Q = 1
2: Pulse generator causes a 2 Q-state pulse width.
3: Output shown for reference only. See I/O port pin block diagram for more detail.
4: Name denotes the source of connection at the comparator output.
Pulse
Gen(2)
SR
Latch(1)
SRNQEN
SRQ pin(3)
SRQEN
SRNQEN
SRSPE
SRSC2E
INT1
SRSCKE
SRCLK
SYNCC2OUT(4)
SRSC1E
SYNCC1OUT(4)
SRPR Pulse
Gen(2)
SRRPE
SRRC2E
INT1
SRRCKE
SRCLK
SYNCC2OUT(4)
SRRC1E
SYNCC1OUT(4)
SRLEN
SRLEN
PIC18F/LF1XK50
DS41350E-page 242 Preliminary 2010 Microchip Technology Inc.
TABLE 20-2: SRCLK FREQUENCY TABLE
SRCLK Divider FOSC = 20 MHz FOSC = 16 MHz FOSC = 8 MHz FOSC = 4 MHz FOSC = 1 MHz
111 512 25.6 s 32 s 64 s 128 s 512 s
110 256 12.8 s 16 s 32 s 64 s 256 s
101 128 6.4 s 8 s 16 s 32 s 128 s
100 64 3.2 s 4 s 8 s 16 s 64 s
011 32 1.6 s 2 s 4 s 8 s 32 s
010 16 0.8 s 1 s 2 s 4 s 16 s
001 8 0.4 s 0.5 s 1 s 2 s 8 s
000 4 0.2 s 0.25 s 0.5 s 1 s 4 s
REGISTER 20-1: SRCON0: SR LATCH CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SRLEN: SR Latch Enable bit(1)
1 = SR latch is enabled
0 = SR latch is disabled
bit 6-4 SRCLK<2:0>(1): SR Latch Clock divider bits
000 = 1/4 Peripheral cycle clock
001 = 1/8 Peripheral cycle clock
010 = 1/16 Peripheral cycle clock
011 = 1/32 Peripheral cycle clock
100 = 1/64 Peripheral cycle clock
101 = 1/128 Peripheral cycle clock
110 = 1/256 Peripheral cycle clock
111 = 1/512 Peripheral cycle clock
bit 3 SRQEN: SR Latch Q Output Enable bit
If SRNQEN = 0
1 = Q is present on the RC4 pin
0 = Q is internal only
bit 2 SRNQEN: SR Latch Q Output Enable bit
1 = Q is present on the RC4 pin
0 = Q is internal only
bit 1 SRPS: Pulse Set Input of the SR Latch
1 = Pulse input
0 = Always reads back ‘0’
bit 0 SRPR: Pulse Reset Input of the SR Latch
1 = Pulse input
0 = Always reads back ‘0’
Note 1: Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the set and Reset
inputs of the latch.
2010 Microchip Technology Inc. Preliminary DS41350E-page 243
PIC18F/LF1XK50
TABLE 20-3: REGISTERS ASSOCIATED WITH THE SR LATCH
REGISTER 20-2: SRCON1: SR LATCH CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SRSPE: SR Latch Peripheral Set Enable bit
1 = INT1 pin status sets SR Latch
0 = INT1pin status has no effect on SR Latch
bit 6 SRSCKE: SR Latch Set Clock Enable bit
1 = Set input of SR latch is pulsed with SRCLK
0 = Set input of SR latch is not pulsed with SRCLK
bit 5 SRSC2E: SR Latch C2 Set Enable bit
1 = C2 Comparator output sets SR Latch
0 = C2 Comparator output has no effect on SR Latch
bit 4 SRSC1E: SR Latch C1 Set Enable bit
1 = C1 Comparator output sets SR Latch
0 = C1 Comparator output has no effect on SR Latch
bit 3 SRRPE: SR Latch Peripheral Reset Enable bit
1 = INT1 pin resets SR Latch
0 = INT1 pin has no effect on SR Latch
bit 2 SRRCKE: SR Latch Reset Clock Enable bit
1 = Reset input of SR latch is pulsed with SRCLK
0 = Reset input of SR latch is not pulsed with SRCLK
bit 1 SRRC2E: SR Latch C2 Reset Enable bit
1 = C2 Comparator output resets SR Latch
0 = C2 Comparator output has no effect on SR Latch
bit 0 SRRC1E: SR Latch C1 Reset Enable bit
1 = C1 Comparator output resets SR Latch
0 = C1 Comparator output has no effect on SR Latch
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 288
SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 288
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 288
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 285
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
Legend: Shaded cells are not used with the comparator voltage reference.
PIC18F/LF1XK50
DS41350E-page 244 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 245
PIC18F/LF1XK50
21.0 VOLTAGE REFERENCES
There are two independent voltage references
available:
• Programmable Voltage Reference
• 1.024V Fixed Voltage Reference
21.1 Voltage Reference
The Voltage Reference module provides an internally
generated voltage reference for the comparators and
the DAC module. The following features are available:
• Independent from Comparator operation
• Single 32-level voltage ranges
• Output clamped to VSS
• Ratiometric with VDD
• 1.024V Fixed Reference Voltage (FVR)
The REFCON1 register (Register 21-2) controls the
Voltage Reference module shown in Figure 21-1.
21.1.1 INDEPENDENT OPERATION
The voltage reference is independent of the
comparator configuration. Setting the D1EN bit of the
REFCON1 register will enable the voltage reference by
allowing current to flow in the VREF voltage divider.
When the D1EN bit is cleared, current flow in the VREF
voltage divider is disabled minimizing the power drain
of the voltage reference peripheral.
21.1.2 OUTPUT VOLTAGE SELECTION
The VREF voltage reference has 32 voltage level
ranges. The 32 levels are set with the DAC1R<4:0>
bits of the REFCON2 register.
The VREF output voltage is determined by the following
equations:
EQUATION 21-1: VREF OUTPUT VOLTAGE
21.1.3 OUTPUT RATIOMETRIC TO VDD
The comparator voltage reference is VDD derived and
therefore, the VREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 27.0
“Electrical Specifications”.
21.1.4 VOLTAGE REFERENCE OUTPUT
The VREF voltage reference can be output to the device
CVREF pin by setting the DAC1OE bit of the REFCON1
register to ‘1’. Selecting the reference voltage for output
on the VREF pin automatically overrides the digital
output buffer and digital input threshold detector functions
of that pin. Reading the CVREF pin when it has
been configured for reference voltage output will
always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the voltage reference output for external
connections to CVREF. Figure 21-2 shows an example
buffering technique.
21.1.5 OPERATION DURING SLEEP
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the RECON1 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
21.1.6 EFFECTS OF A RESET
A device Reset affects the following:
• Voltage reference is disabled
• Fixed voltage reference is disabled
• VREF is removed from the CVREF pin
• The DAC1R<4:0> range select bits are cleared
VOUT VSOURCE – VSOURCE x DAC1R[4:0]
25 -------------------------------- + VSOURCE
= -
IF D1EN = 1
IF D1EN = 0 & D1LPS = 1 & DAC1R[4:0] = 11111:
VOUT = VSOURCE+
IF D1EN = 0 & D1LPS = 1 & DAC1R[4:0] = 00000:
VOUT = VSOURCE-
+ -
PIC18F/LF1XK50
DS41350E-page 246 Preliminary 2010 Microchip Technology Inc.
21.2 FVR Reference Module
The FVR reference is a stable fixed voltage reference,
independent of VDD, with a nominal output voltage of
1.024V. This reference can be enabled by setting the
FVR1EN bit of the REFCON0 register to ‘1’. The FVR
voltage reference can be routed to the comparators or
an ADC input channel.
21.2.1 FVR STABILIZATION PERIOD
When the Fixed Voltage Reference module is enabled, it
will require some time for the reference and its amplifier
circuits to stabilize. The user program must include a
small delay routine to allow the module to settle. The
FVR1ST stable bit of the REFCON0 register also
indicates that the FVR reference has been operating long
enough to be stable. See Section 27.0 “Electrical
Specifications” for the minimum delay requirement.
FIGURE 21-1: VOLTAGE REFERENCE BLOCK DIAGRAM
16-to-1 MUX
DAC1R<4:0>
R
VDD
VREF+
D1PSS<1:0> = 00
D1NSS = 0
VREF- D1NSS = 1
R
R
R
R
R
R
32 Steps
VREF
FVR1
D1PSS<1:0> = 01
D1PSS<1:0> = 10
CVREF pin
DAC1OE
FVR1S<1:0>
X1
X2
X4
2
FVR
+
_
FVR1EN
FVR1ST
1.024V Fixed
Reference
D1EN
D1LPS
R
D1EN
D1LPS
2010 Microchip Technology Inc. Preliminary DS41350E-page 247
PIC18F/LF1XK50
FIGURE 21-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
REGISTER 21-1: REFCON0: REFERENCE CONTROL REGISTER 0
R/W-0 R-0 R/W-0 R/W-1 U-0 U-0 U-0 U-0
FVR1EN FVR1ST FVR1S1 FVR1S0 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 FVR1EN: Fixed Voltage Reference 1 Enable bit
0 = FVR is disabled
1 = FVR is enabled
bit 6 FVR1ST: Fixed Voltage Reference 1 Stable bit
0 = FVR is not stable
1 = FVR is stable
bit 5-4 FVR1S<1:0>: Fixed Voltage Reference 1 Voltage Select bits
00 = Reserved, do not use
01 = 1.024V (x1)
10 = 2.048V (x2)
11 = 4.096V (x4)
bit 3-0 Unimplemented: Read as ‘0’
Buffered CVREF Output
+–
CVREF
Module
Voltage
Reference
Output
Impedance
R(1)
CVREF
Note 1: R is dependent upon the voltage reference Configuration bits, CVR<3:0> and CVRR.
PIC18F1XK50/
PIC18LF1XK50
PIC18F/LF1XK50
DS41350E-page 248 Preliminary 2010 Microchip Technology Inc.
REGISTER 21-2: REFCON1: REFERENCE CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0
D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 --- D1NSS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 D1EN: DAC 1 Enable bit
0 = DAC 1 is disabled
1 = DAC 1 is enabled
bit 6 D1LPS: DAC 1 Low-Power Voltage State Select bit
0 = VDAC = DAC1 Negative reference source selected
1 = VDAC = DAC1 Positive reference source selected
bit 5 DAC1OE: DAC 1 Voltage Output Enable bit
1 = DAC 1 voltage level is also outputed on the RC2/AN6/P1D/C12IN2-/CVREF/INT2 pin
0 = DAC 1 voltage level is disconnected from RC2/AN6/P1D/C12IN2-/CVREF/INT2 pin
bit 4 Unimplemented: Read as ‘0’
bit 3-2 D1PSS<1:0>: DAC 1 Positive Source Select bits
00 = VDD
01 = VREF+
10 = FVR output
11 = Reserved, do not use
bit 1 Unimplemented: Read as ‘0’
bit 0 D1NSS: DAC1 Negative Source Select bits
0 = VSS
1 = VREFREGISTER
21-3: REFCON2: REFERENCE CONTROL REGISTER 2
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
--- --- --- DAC1R4 DAC1R3 DAC1R2 DAC1R1 DAC1R0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 DAC1R<4:0>: DAC1 Voltage Output Select bits
VOUT = ((VSOURCE+) - (VSOURCE-))*(DAC1R<4:0>/(2^5)) + VSOURCENote
1: The output select bits are always right justified to ensure that any number of bits can be used without
affecting the register layout.
2010 Microchip Technology Inc. Preliminary DS41350E-page 249
PIC18F/LF1XK50
TABLE 21-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
REFCON0 FVR1EN FVR1ST FVR1S1 FVR1S0 — — — — 287
REFCON1 D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 — D1NSS 287
REFCON2 — — — DAC1R4 DAC1R3 DAC1R2 DAC1R1 DAC1R0 287
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 288
Legend: Shaded cells are not used with the comparator voltage reference.
PIC18F/LF1XK50
DS41350E-page 250 Preliminary 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. Preliminary DS41350E-page 251
PIC18F/LF1XK50
22.0 UNIVERSAL SERIAL BUS
(USB)
This section describes the details of the USB
peripheral. Because of the very specific nature of the
module, knowledge of USB is expected. Some
high-level USB information is provided in
Section 22.10 “Overview of USB” only for application
design reference. Designers are encouraged to refer to
the official specification published by the USB Implementers
Forum (USB-IF) for the latest information.
USB Specification Revision 2.0 is the most current
specification at the time of publication of this document.
22.1 Overview of the USB Peripheral
PIC18F1XK50/PIC18LF1XK50 devices contain a
full-speed and low-speed, compatible USB Serial Interface
Engine (SIE) that allows fast communication
between any USB host and the PIC® microcontroller.
The SIE can be interfaced directly to the USB by
utilizing the internal transceiver.
Some special hardware features have been included to
improve performance. Dual access port memory in the
device’s data memory space (USB RAM) has been
supplied to share direct memory access between the
microcontroller core and the SIE. Buffer descriptors are
also provided, allowing users to freely program endpoint
memory usage within the USB RAM space.
Figure 22-1 presents a general overview of the USB
peripheral and its features.
FIGURE 22-1: USB PERIPHERAL AND OPTIONS
256 byte
USB RAM
USB
SIE
USB Control and
Transceiver
P
P
D+
DInternal
Pull-ups
External 3.3V
Supply
FSEN
UPUEN
USB Clock from the
Oscillator Module
Optional
External
Pull-ups(1)
(Full (Low
PIC18F1XK50/PIC18LF1XK50 Family
USB Bus
FS
Speed) Speed)
Note 1: The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used.
2: PIC18F13K50/PIC18F14K50 only.
Configuration
VUSB
3.3V LDO Regulator(2)
PIC18F/LF1XK50
DS41350E-page 252 Preliminary 2010 Microchip Technology Inc.
22.2 USB Status and Control
The operation of the USB module is configured and
managed through three control registers. In addition, a
total of 14 registers are used to manage the actual USB
transactions. The registers are:
• USB Control register (UCON)
• USB Configuration register (UCFG)
• USB Transfer Status register (USTAT)
• USB Device Address register (UADDR)
• Frame Number registers (UFRMH:UFRML)
• Endpoint Enable registers 0 through 7 (UEPn)
22.2.1 USB CONTROL REGISTER (UCON)
The USB Control register (Register 22-1) contains bits
needed to control the module behavior during transfers.
The register contains bits that control the following:
• Main USB Peripheral Enable
• Ping-Pong Buffer Pointer Reset
• Control of the Suspend mode
• Packet Transfer Disable
In addition, the USB Control register contains a status
bit, SE0 (UCON<5>), which is used to indicate the
occurrence of a single-ended zero on the bus. When
the USB module is enabled, this bit should be monitored
to determine whether the differential data lines
have come out of a single-ended zero condition. This
helps to differentiate the initial power-up state from the
USB Reset signal.
The overall operation of the USB module is controlled
by the USBEN bit (UCON<3>). Setting this bit activates
the module and resets all of the PPBI bits in the Buffer
Descriptor Table to ‘0’. This bit also activates the internal
pull-up resistors, if they are enabled. Thus, this bit
can be used as a soft attach/detach to the USB.
Although all Status and control bits are ignored when
this bit is clear, the module needs to be fully preconfigured
prior to setting this bit. This bit cannot be set until
the USB module is supplied with an active clock
source. If the PLL is being used, it should be enabled
at least two milliseconds (enough time for the PLL to
lock) before attempting to set the USBEN bit.
REGISTER 22-1: UCON: USB CONTROL REGISTER
U-0 R/W-0 R-x R/C-0 R/W-0 R/W-0 R/W-0 U-0
— PPBRST SE0 PKTDIS USBEN(1) RESUME SUSPND —
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 PPBRST: Ping-Pong Buffers Reset bit
1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) banks
0 = Ping-Pong Buffer Pointers not being reset
bit 5 SE0: Live Single-Ended Zero Flag bit
1 = Single-ended zero active on the USB bus
0 = No single-ended zero detected
bit 4 PKTDIS: Packet Transfer Disable bit
1 = SIE token and packet processing disabled, automatically set when a SETUP token is received
0 = SIE token and packet processing enabled
bit 3 USBEN: USB Module Enable bit(1)
1 = USB module and supporting circuitry enabled (device attached)
0 = USB module and supporting circuitry disabled (device detached)
bit 2 RESUME: Resume Signaling Enable bit
1 = Resume signaling activated
0 = Resume signaling disabled
bit 1 SUSPND: Suspend USB bit
1 = USB module and supporting circuitry in Power Conserve mode, SIE clock inactive
0 = USB module and supporting circuitry in normal operation, SIE clock clocked at the configured rate
bit 0 Unimplemented: Read as ‘0’
Note 1: This bit cannot be set if the USB module does not have an appropriate clock source.
2010 Microchip Technology Inc. Preliminary DS41350E-page 253
PIC18F/LF1XK50
The PPBRST bit (UCON<6>) controls the Reset status
when Double-Buffering mode (ping-pong buffering) is
used. When the PPBRST bit is set, all Ping-Pong Buffer
Pointers are set to the Even buffers. PPBRST has
to be cleared by firmware. This bit is ignored in buffering
modes not using ping-pong buffering.
The PKTDIS bit (UCON<4>) is a flag indicating that the
SIE has disabled packet transmission and reception.
This bit is set by the SIE when a SETUP token is
received to allow setup processing. This bit cannot be
set by the microcontroller, only cleared; clearing it
allows the SIE to continue transmission and/or
reception. Any pending events within the Buffer
Descriptor Table will still be available, indicated within
the USTAT register’s FIFO buffer.
The RESUME bit (UCON<2>) allows the peripheral to
perform a remote wake-up by executing Resume
signaling. To generate a valid remote wake-up,
firmware must set RESUME for 10 ms and then clear
the bit. For more information on “resume signaling”,
see the “Universal Serial Bus Specification
Revision 2.0”.
The SUSPND bit (UCON<1>) places the module and
supporting circuitry in a Low-Power mode. The input
clock to the SIE is also disabled. This bit should be set
by the software in response to an IDLEIF interrupt. It
should be reset by the microcontroller firmware after an
ACTVIF interrupt is observed. When this bit is active,
the device remains attached to the bus but the transceiver
outputs remain Idle. The voltage on the VUSB pin
may vary depending on the value of this bit. Setting this
bit before a IDLEIF request will result in unpredictable
bus behavior.
22.2.2 USB CONFIGURATION REGISTER
(UCFG)
Prior to communicating over USB, the module’s
associated internal and/or external hardware must be
configured. Most of the configuration is performed with
the UCFG register (Register 22-2).The UFCG register
contains most of the bits that control the system level
behavior of the USB module. These include:
• Bus Speed (full speed versus low speed)
• On-Chip Pull-up Resistor Enable
• Ping-Pong Buffer Usage
The UTEYE bit, UCFG<7>, enables eye pattern generation,
which aids in module testing, debugging and
USB certifications.
22.2.2.1 Internal Transceiver
The USB peripheral has a built-in, USB 2.0, full-speed
and low-speed capable transceiver, internally connected
to the SIE. This feature is useful for low-cost,
single chip applications. Enabling the USB module
(USBEN = 1) will also enable the internal transceiver.
The FSEN bit (UCFG<2>) controls the transceiver
speed; setting the bit enables full-speed operation.
The on-chip USB pull-up resistors are controlled by the
UPUEN bit (UCFG<4>). They can only be selected
when the on-chip transceiver is enabled.
The internal USB transceiver obtains power from the
VUSB pin. In order to meet USB signalling level
specifications, VUSB must be supplied with a voltage
source between 3.0V and 3.6V. The best electrical
signal quality is obtained when a 3.3V supply is used
and locally bypassed with a high quality ceramic
capacitor. The capacitor should be placed as close as
possible to the VUSB and VSS pins found on the same
edge of the package (i.e., route ground of the capacitor
to VSS pin 20 on 20-lead PDIP, SOIC, SSOP and QFN
packaged parts).
The D+ and D- signal lines can be routed directly to
their respective pins on the USB connector or cable (for
hard-wired applications). No additional resistors,
capacitors, or magnetic components are required as
the D+ and D- drivers have controlled slew rate and
output impedance intended to match with the
characteristic impedance of the USB cable.
In order to meet the USB specifications, the traces
should be less than 30 cm long. Ideally, these traces
should be designed to have a characteristic impedance
matching that of the USB cable.
Note: While in Suspend mode, a typical
bus-powered USB device is limited to
500 A of current. This is the complete
current which may be drawn by the PIC
device and its supporting circuitry. Care
should be taken to assure minimum
current draw when the device enters
Suspend mode.
Note: The USB speed, transceiver and pull-up
should only be configured during the module
setup phase. It is not recommended to
switch these settings while the module is
enabled.
PIC18F/LF1XK50
DS41350E-page 254 Preliminary 2010 Microchip Technology Inc.
REGISTER 22-2: UCFG: USB CONFIGURATION REGISTER
R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
UTEYE — — UPUEN(1) — FSEN(1) PPB1 PPB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UTEYE: USB Eye Pattern Test Enable bit
1 = Eye pattern test enabled
0 = Eye pattern test disabled
bit 6-5 Unimplemented: Read as ‘0’
bit 4 UPUEN: USB On-Chip Pull-up Enable bit(1)
1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)
0 = On-chip pull-up disabled
bit 3 Unimplemented: Read as ‘0’
bit 2 FSEN: Full-Speed Enable bit(1)
1 = Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz
0 = Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz
bit 1-0 PPB<1:0>: Ping-Pong Buffers Configuration bits
11 = Even/Odd ping-pong buffers enabled for Endpoints 1 to 15
10 = Even/Odd ping-pong buffers enabled for all endpoints
01 = Even/Odd ping-pong buffer enabled for OUT Endpoint 0
00 = Even/Odd ping-pong buffers disabled
Note 1: The UPUEN, and FSEN bits should never be changed while the USB module is enabled. These values
must be preconfigured prior to enabling the module.
2010 Microchip Technology Inc. Preliminary DS41350E-page 255
PIC18F/LF1XK50
22.2.2.2 Internal Pull-up Resistors
The PIC18F1XK50/PIC18LF1XK50 devices have
built-in pull-up resistors designed to meet the requirements
for low-speed and full-speed USB. The UPUEN
bit (UCFG<4>) enables the internal pull-ups.
Figure 22-1 shows the pull-ups and their control.
22.2.2.3 External Pull-up Resistors
External pull-up may also be used. The VUSB pin may be
used to pull up D+ or D-. The pull-up resistor must be
1.5 k (±5%) as required by the USB specifications.
Figure 22-2 shows an example.
FIGURE 22-2: EXTERNAL CIRCUITRY
22.2.2.4 Ping-Pong Buffer Configuration
The usage of ping-pong buffers is configured using the
PPB<1:0> bits. Refer to Section 22.4.4 “Ping-Pong
Buffering” for a complete explanation of the ping-pong
buffers.
22.2.2.5 Eye Pattern Test Enable
An automatic eye pattern test can be generated by the
module when the UCFG<7> bit is set. The eye pattern
output will be observable based on module settings,
meaning that the user is first responsible for configuring
the SIE clock settings, pull-up resistor and Transceiver
mode. In addition, the module has to be enabled.
Once UTEYE is set, the module emulates a switch from
a receive to transmit state and will start transmitting a
J-K-J-K bit sequence (K-J-K-J for full speed). The
sequence will be repeated indefinitely while the Eye
Pattern Test mode is enabled.
Note that this bit should never be set while the module
is connected to an actual USB system. This Test mode
is intended for board verification to aid with USB certification
tests. It is intended to show a system developer
the noise integrity of the USB signals which can be
affected by board traces, impedance mismatches and
proximity to other system components. It does not
properly test the transition from a receive to a transmit
state. Although the eye pattern is not meant to replace
the more complex USB certification test, it should aid
during first order system debugging.
Note: The official USB specifications require
that USB devices must never source any
current onto the +5V VBUS line of the USB
cable. Additionally, USB devices must
never source any current on the D+ and
D- data lines whenever the +5V VBUS line
is less than 1.17V. In order to meet this
requirement, applications which are not
purely bus powered should monitor the
VBUS line and avoid turning on the USB
module and the D+ or D- pull-up resistor
until VBUS is greater than 1.17V. VBUS can
be connected to and monitored by any 5V
tolerant I/O pin for this purpose.
PIC®
Microcontroller
Host
Controller/HUB
VUSB
D+
DNote:
The above setting shows a typical connection
for a full-speed configuration using an on-chip
regulator and an external pull-up resistor.
1.5 k
PIC18F/LF1XK50
DS41350E-page 256 Preliminary 2010 Microchip Technology Inc.
22.2.3 USB STATUS REGISTER (USTAT)
The USB Status register reports the transaction status
within the SIE. When the SIE issues a USB transfer
complete interrupt, USTAT should be read to determine
the status of the transfer. USTAT contains the transfer
endpoint number, direction and Ping-Pong Buffer
Pointer value (if used).
The USTAT register is actually a read window into a
four-byte status FIFO, maintained by the SIE. It allows
the microcontroller to process one transfer while the
SIE processes additional endpoints (Figure 22-3).
When the SIE completes using a buffer for reading or
writing data, it updates the USTAT register. If another
USB transfer is performed before a transaction
complete interrupt is serviced, the SIE will store the
status of the next transfer into the status FIFO.
Clearing the transfer complete flag bit, TRNIF, causes
the SIE to advance the FIFO. If the next data in the
FIFO holding register is valid, the SIE will reassert the
interrupt within 6 TCY of clearing TRNIF. If no additional
data is present, TRNIF will remain clear; USTAT data
will no longer be reliable.
FIGURE 22-3: USTAT FIFO
Note: The data in the USB Status register is
valid two SIE clocks after the TRNIF interrupt
flag is asserted.
In low-speed operation with the system
clock operating at 48 MHz, a delay may
be required between receiving the TRNIF
interrupt and processing the data in the
USTAT register.
Note: If an endpoint request is received while
the USTAT FIFO is full, the SIE will
automatically issue a NAK back to the
host.
Data Bus
USTAT from SIE
4-Byte FIFO
for USTAT
Clearing TRNIF
Advances FIFO
REGISTER 22-3: USTAT: USB STATUS REGISTER
U-0 U-0 R-x R-x R-x R-x R-x U-0
— — ENDP2 ENDP1 ENDP0 DIR PPBI(1) —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-3 ENDP<2:0>: Encoded Number of Last Endpoint Activity bits
(represents the number of the BDT updated by the last USB transfer)
111 = Endpoint 7
110 = Endpoint 6
....
001 = Endpoint 1
000 = Endpoint 0
bit 2 DIR: Last BD Direction Indicator bit
1 = The last transaction was an IN token
0 = The last transaction was an OUT or SETUP token
bit 1 PPBI: Ping-Pong BD Pointer Indicator bit(1)
1 = The last transaction was to the Odd BD bank
0 = The last transaction was to the Even BD bank
bit 0 Unimplemented: Read as ‘0’
Note 1: This bit is only valid for endpoints with available Even and Odd BD registers.
2010 Microchip Technology Inc. Preliminary DS41350E-page 257
PIC18F/LF1XK50
22.2.4 USB ENDPOINT CONTROL
Each of the 8 possible bidirectional endpoints has its
own independent control register, UEPn (where ‘n’ represents
the endpoint number). Each register has an
identical complement of control bits. The prototype is
shown in Register 22-4.
The EPHSHK bit (UEPn<4>) controls handshaking for
the endpoint; setting this bit enables USB handshaking.
Typically, this bit is always set except when using
isochronous endpoints.
The EPCONDIS bit (UEPn<3>) is used to enable or
disable USB control operations (SETUP) through the
endpoint. Clearing this bit enables SETUP transactions.
Note that the corresponding EPINEN and
EPOUTEN bits must be set to enable IN and OUT
transactions. For Endpoint 0, this bit should always be
cleared since the USB specifications identify
Endpoint 0 as the default control endpoint.
The EPOUTEN bit (UEPn<2>) is used to enable or disable
USB OUT transactions from the host. Setting this
bit enables OUT transactions. Similarly, the EPINEN bit
(UEPn<1>) enables or disables USB IN transactions
from the host.
The EPSTALL bit (UEPn<0>) is used to indicate a
STALL condition for the endpoint. If a STALL is issued
on a particular endpoint, the EPSTALL bit for that endpoint
pair will be set by the SIE. This bit remains set
until it is cleared through firmware, or until the SIE is
reset.
REGISTER 22-4: UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP7)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake enabled
0 = Endpoint handshake disabled (typically used for isochronous endpoints)
bit 3 EPCONDIS: Bidirectional Endpoint Control bit
If EPOUTEN = 1 and EPINEN = 1:
1 = Disable Endpoint n from control transfers; only IN and OUT transfers allowed
0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed
bit 2 EPOUTEN: Endpoint Output Enable bit
1 = Endpoint n output enabled
0 = Endpoint n output disabled
bit 1 EPINEN: Endpoint Input Enable bit
1 = Endpoint n input enabled
0 = Endpoint n input disabled
bit 0 EPSTALL: Endpoint STALL Enable bit(1)
1 = Endpoint n is stalled
0 = Endpoint n is not stalled
Note 1: Valid only if Endpoint n is enabled; otherwise, the bit is ignored.
PIC18F/LF1XK50
DS41350E-page 258 Preliminary 2010 Microchip Technology Inc.
22.2.5 USB ADDRESS REGISTER
(UADDR)
The USB Address register contains the unique USB
address that the peripheral will decode when active.
UADDR is reset to 00h when a USB Reset is received,
indicated by URSTIF, or when a Reset is received from
the microcontroller. The USB address must be written
by the microcontroller during the USB setup phase
(enumeration) as part of the Microchip USB firmware
support.
22.2.6 USB FRAME NUMBER REGISTERS
(UFRMH:UFRML)
The Frame Number registers contain the 11-bit frame
number. The low-order byte is contained in UFRML,
while the three high-order bits are contained in
UFRMH. The register pair is updated with the current
frame number whenever a SOF token is received. For
the microcontroller, these registers are read-only. The
Frame Number registers are primarily used for
isochronous transfers. The contents of the UFRMH and
UFRML registers are only valid when the 48 MHz SIE
clock is active (i.e., contents are inaccurate when
SUSPND (UCON<1>) bit = 1).
22.3 USB RAM
USB data moves between the microcontroller core and
the SIE through a memory space known as the USB
RAM. This is a special dual access memory that is
mapped into the normal data memory space in Bank 2
(200h to 2FFh) for a total of 256 bytes (Figure 22-4).
Bank 2 (200h through 27Fh) is used specifically for
endpoint buffer control. Depending on the type of buffering
being used, all but 8 bytes of Bank 2 may also be
available for use as USB buffer space.
Although USB RAM is available to the microcontroller
as data memory, the sections that are being accessed
by the SIE should not be accessed by the
microcontroller. A semaphore mechanism is used to
determine the access to a particular buffer at any given
time. This is discussed in Section 22.4.1.1 “Buffer
Ownership”.
FIGURE 22-4: IMPLEMENTATION OF
USB RAM IN DATA
MEMORY SPACE
200h
2FFh
Buffer Descriptors,
USB Data or User Data
SFRs
1FFh
000h
F60h
FFFh
Banks 2
(USB RAM)
F5Fh
F53h
F52h
300h
Banks 3
to 14
User Data
Unused
Banks 15
USB Data or
User Data
27Fh
280h
Banks 0
to 1
2010 Microchip Technology Inc. Preliminary DS41350E-page 259
PIC18F/LF1XK50
22.4 Buffer Descriptors and the Buffer
Descriptor Table
The registers in Bank 2 are used specifically for endpoint
buffer control in a structure known as the Buffer
Descriptor Table (BDT). This provides a flexible method
for users to construct and control endpoint buffers of
various lengths and configuration.
The BDT is composed of Buffer Descriptors (BD) which
are used to define and control the actual buffers in the
USB RAM space. Each BD, in turn, consists of four registers,
where n represents one of the 32 possible BDs
(range of 0 to 31):
• BDnSTAT: BD Status register
• BDnCNT: BD Byte Count register
• BDnADRL: BD Address Low register
• BDnADRH: BD Address High register
BDs always occur as a four-byte block in the sequence,
BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address
of BDnSTAT is always an offset of (4n – 1) (in hexadecimal)
from 200h, with n being the buffer descriptor
number.
Depending on the buffering configuration used
(Section 22.4.4 “Ping-Pong Buffering”), there are up
to 16, 17 or 32 sets of buffer descriptors. At a minimum,
the BDT must be at least 8 bytes long. This is because
the USB specification mandates that every device must
have Endpoint 0 with both input and output for initial
setup. Depending on the endpoint and buffering
configuration, the BDT can be as long as 128 bytes.
Although they can be thought of as Special Function
Registers, the Buffer Descriptor Status and Address
registers are not hardware mapped, as conventional
microcontroller SFRs in Bank 15 are. If the endpoint corresponding
to a particular BD is not enabled, its registers
are not used. Instead of appearing as unimplemented
addresses, however, they appear as available RAM.
Only when an endpoint is enabled by setting the
UEPn<1> bit does the memory at those addresses
become functional as BD registers. As with any address
in the data memory space, the BD registers have an
indeterminate value on any device Reset.
An example of a BD for a 64-byte buffer, starting at
280h, is shown in Figure 22-5. A particular set of BD
registers is only valid if the corresponding endpoint has
been enabled using the UEPn register. All BD registers
are available in USB RAM. The BD for each endpoint
should be set up prior to enabling the endpoint.
22.4.1 BD STATUS AND CONFIGURATION
Buffer descriptors not only define the size of an endpoint
buffer, but also determine its configuration and
control. Most of the configuration is done with the BD
Status register, BDnSTAT. Each BD has its own unique
and correspondingly numbered BDnSTAT register.
FIGURE 22-5: EXAMPLE OF A BUFFER
DESCRIPTOR
Unlike other control registers, the bit configuration for
the BDnSTAT register is context sensitive. There are
two distinct configurations, depending on whether the
microcontroller or the USB module is modifying the BD
and buffer at a particular time. Only three bit definitions
are shared between the two.
22.4.1.1 Buffer Ownership
Because the buffers and their BDs are shared between
the CPU and the USB module, a simple semaphore
mechanism is used to distinguish which is allowed to
update the BD and associated buffers in memory.
This is done by using the UOWN bit (BDnSTAT<7>) as
a semaphore to distinguish which is allowed to update
the BD and associated buffers in memory. UOWN is the
only bit that is shared between the two configurations
of BDnSTAT.
When UOWN is clear, the BD entry is “owned” by the
microcontroller core. When the UOWN bit is set, the BD
entry and the buffer memory are “owned” by the USB
peripheral. The core should not modify the BD or its
corresponding data buffer during this time. Note that
the microcontroller core can still read BDnSTAT while
the SIE owns the buffer and vice versa.
The buffer descriptors have a different meaning based
on the source of the register update. Prior to placing
ownership with the USB peripheral, the user can configure
the basic operation of the peripheral through the
BDnSTAT bits. During this time, the byte count and buffer
location registers can also be set.
When UOWN is set, the user can no longer depend on
the values that were written to the BDs. From this point,
the SIE updates the BDs as necessary, overwriting the
original BD values. The BDnSTAT register is updated
by the SIE with the token PID and the transfer count,
BDnCNT, is updated.
200h
USB Data
Buffer
Buffer
BD0STAT
BD0CNT
BD0ADRL
BD0ADRH
201h
202h
203h
280h
2BFh
Descriptor
Note: Memory regions not to scale.
40h
00h
05h
Starting
Size of Block
(xxh)
Address Registers Contents
Address
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DS41350E-page 260 Preliminary 2010 Microchip Technology Inc.
The BDnSTAT byte of the BDT should always be the
last byte updated when preparing to arm an endpoint.
The SIE will clear the UOWN bit when a transaction
has completed.
No hardware mechanism exists to block access when
the UOWN bit is set. Thus, unexpected behavior can
occur if the microcontroller attempts to modify memory
when the SIE owns it. Similarly, reading such memory
may produce inaccurate data until the USB peripheral
returns ownership to the microcontroller.
22.4.1.2 BDnSTAT Register (CPU Mode)
When UOWN = 0, the microcontroller core owns the
BD. At this point, the other seven bits of the register
take on control functions.
The Data Toggle Sync Enable bit, DTSEN
(BDnSTAT<3>), controls data toggle parity checking.
Setting DTSEN enables data toggle synchronization by
the SIE. When enabled, it checks the data packet’s parity
against the value of DTS (BDnSTAT<6>). If a packet
arrives with an incorrect synchronization, the data will
essentially be ignored. It will not be written to the USB
RAM and the USB transfer complete interrupt flag will
not be set. The SIE will send an ACK token back to the
host to Acknowledge receipt, however. The effects of
the DTSEN bit on the SIE are summarized in
Table 22-1.
The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides
support for control transfers, usually one-time stalls on
Endpoint 0. It also provides support for the
SET_FEATURE/CLEAR_FEATURE commands specified
in Chapter 9 of the USB specification; typically,
continuous STALLs to any endpoint other than the
default control endpoint.
The BSTALL bit enables buffer stalls. Setting BSTALL
causes the SIE to return a STALL token to the host if a
received token would use the BD in that location. The
EPSTALL bit in the corresponding UEPn control register
is set and a STALL interrupt is generated when a
STALL is issued to the host. The UOWN bit remains set
and the BDs are not changed unless a SETUP token is
received. In this case, the STALL condition is cleared
and the ownership of the BD is returned to the
microcontroller core.
The BD<9:8> bits (BDnSTAT<1:0>) store the two Most
Significant digits of the SIE byte count; the lower 8 digits
are stored in the corresponding BDnCNT register.
See Section 22.4.2 “BD Byte Count” for more
information.
TABLE 22-1: EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION
OUT Packet
from Host
BDnSTAT Settings Device Response after Receiving Packet
DTSEN DTS Handshake UOWN TRNIF BDnSTAT and USTAT Status
DATA0 1 0 ACK 0 1 Updated
DATA1 1 0 ACK 1 0 Not Updated
DATA0 1 1 ACK 1 0 Not Updated
DATA1 1 1 ACK 0 1 Updated
Either 0 x ACK 0 1 Updated
Either, with error x x NAK 1 0 Not Updated
Legend: x = don’t care
2010 Microchip Technology Inc. Preliminary DS41350E-page 261
PIC18F/LF1XK50
REGISTER 22-5: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD31STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE)
R/W-x R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x
UOWN(1) DTS(2) —(3) —(3) DTSEN BSTALL BC9 BC8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UOWN: USB Own bit(1)
0 = The microcontroller core owns the BD and its corresponding buffer
bit 6 DTS: Data Toggle Synchronization bit(2)
1 = Data 1 packet
0 = Data 0 packet
bit 5-4 Unimplemented: These bits should always be programmed to ‘0’(3).
bit 3 DTSEN: Data Toggle Synchronization Enable bit
1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored
except for a SETUP transaction, which is accepted even if the data toggle bits do not match
0 = No data toggle synchronization is performed
bit 2 BSTALL: Buffer Stall Enable bit
1 = Buffer stall enabled; STALL handshake issued if a token is received that would use the BD in the
given location (UOWN bit remains set, BD value is unchanged)
0 = Buffer stall disabled
bit 1-0 BC<9:8>: Byte Count 9 and 8 bits
The byte count bits represent the number of bytes that will be transmitted for an IN token or received
during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023.
Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module.
2: This bit is ignored unless DTSEN = 1.
3: If these bits are set, USB communication may not work. Hence, these bits should always be maintained as
‘0’.
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DS41350E-page 262 Preliminary 2010 Microchip Technology Inc.
22.4.1.3 BDnSTAT Register (SIE Mode)
When the BD and its buffer are owned by the SIE, most
of the bits in BDnSTAT take on a different meaning. The
configuration is shown in Register 22-6. Once the
UOWN bit is set, any data or control settings previously
written there by the user will be overwritten with data
from the SIE.
The BDnSTAT register is updated by the SIE with the
token Packet Identifier (PID) which is stored in
BDnSTAT<5:3>. The transfer count in the corresponding
BDnCNT register is updated. Values that overflow
the 8-bit register carry over to the two Most Significant
digits of the count, stored in BDnSTAT<1:0>.
22.4.2 BD BYTE COUNT
The byte count represents the total number of bytes
that will be transmitted during an IN transfer. After an IN
transfer, the SIE will return the number of bytes sent to
the host.
For an OUT transfer, the byte count represents the
maximum number of bytes that can be received and
stored in USB RAM. After an OUT transfer, the SIE will
return the actual number of bytes received. If the
number of bytes received exceeds the corresponding
byte count, the data packet will be rejected and a NAK
handshake will be generated. When this happens, the
byte count will not be updated.
The 10-bit byte count is distributed over two registers.
The lower 8 bits of the count reside in the BDnCNT
register. The upper two bits reside in BDnSTAT<1:0>.
This represents a valid byte range of 0 to 1023.
22.4.3 BD ADDRESS VALIDATION
The BD Address register pair contains the starting RAM
address location for the corresponding endpoint buffer.
No mechanism is available in hardware to validate the
BD address.
If the value of the BD address does not point to an
address in the USB RAM, or if it points to an address
within another endpoint’s buffer, data is likely to be lost
or overwritten. Similarly, overlapping a receive buffer
(OUT endpoint) with a BD location in use can yield
unexpected results. When developing USB
applications, the user may want to consider the
inclusion of software-based address validation in their
code.
REGISTER 22-6: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD31STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE MCU)
R/W-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
UOWN — PID3 PID2 PID1 PID0 BC9 BC8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UOWN: USB Own bit
1 = The SIE owns the BD and its corresponding buffer
bit 6 Reserved: Not written by the SIE
bit 5-2 PID<3:0>: Packet Identifier bits
The received token PID value of the last transfer (IN, OUT or SETUP transactions only).
bit 1-0 BC<9:8>: Byte Count 9 and 8 bits
These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer
and the actual number of bytes transmitted on an IN transfer.
2010 Microchip Technology Inc. Preliminary DS41350E-page 263
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22.4.4 PING-PONG BUFFERING
An endpoint is defined to have a ping-pong buffer when
it has two sets of BD entries: one set for an Even
transfer and one set for an Odd transfer. This allows the
CPU to process one BD while the SIE is processing the
other BD. Double-buffering BDs in this way allows for
maximum throughput to/from the USB.
The USB module supports four modes of operation:
• No ping-pong support
• Ping-pong buffer support for OUT Endpoint 0 only
• Ping-pong buffer support for all endpoints
• Ping-pong buffer support for all other Endpoints
except Endpoint 0
The ping-pong buffer settings are configured using the
PPB<1:0> bits in the UCFG register.
The USB module keeps track of the Ping-Pong Pointer
individually for each endpoint. All pointers are initially
reset to the Even BD when the module is enabled. After
the completion of a transaction (UOWN cleared by the
SIE), the pointer is toggled to the Odd BD. After the
completion of the next transaction, the pointer is
toggled back to the Even BD and so on.
The Even/Odd status of the last transaction is stored in
the PPBI bit of the USTAT register. The user can reset
all Ping-Pong Pointers to Even using the PPBRST bit.
Figure 22-6 shows the four different modes of
operation and how USB RAM is filled with the BDs.
BDs have a fixed relationship to a particular endpoint,
depending on the buffering configuration. The mapping
of BDs to endpoints is detailed in Table 22-2. This
relationship also means that gaps may occur in the
BDT if endpoints are not enabled contiguously. This
theoretically means that the BDs for disabled endpoints
could be used as buffer space. In practice, users
should avoid using such spaces in the BDT unless a
method of validating BD addresses is implemented.
FIGURE 22-6: BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES
EP1 IN Even
EP1 OUT Even
EP1 OUT Odd
EP1 IN Odd
Descriptor
Descriptor
Descriptor
Descriptor
EP1 IN
EP7 IN
EP1 OUT
EP0 OUT
PPB<1:0> = 00
EP0 IN
EP1 IN
No Ping-Pong
EP7 IN
EP0 IN
EP0 OUT Even
PPB<1:0> = 01
EP0 OUT Odd
EP1 OUT
Ping-Pong Buffer
EP7 IN Odd
EP0 IN Even
EP0 OUT Even
PPB<1:0> = 10
EP0 OUT Odd
EP0 IN Odd
Ping-Pong Buffers
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
200h
2FFh 2FFh 2FFh
200h 200h
23Fh
243h
Available
as
Data RAM Available
as
Data RAM
Maximum Memory
Used: 64 bytes
Maximum BDs:
16 (BD0 to BD15)
Maximum Memory
Used: 68 bytes
Maximum BDs:
17 (BD0 to BD16)
Maximum Memory
Used: 128 bytes
Maximum BDs:
32 (BD0 to BD31)
Note: Memory area not shown to scale.
Descriptor
Descriptor
Descriptor
Descriptor
Buffers on EP0 OUT on all EPs
EP1 IN Even
EP1 OUT Even
EP1 OUT Odd
EP1 IN Odd
Descriptor
Descriptor
Descriptor
Descriptor
EP7 IN Odd
EP0 OUT
PPB<1:0> = 11
EP0 IN
Ping-Pong Buffers
Descriptor
Descriptor
Descriptor
2FFh
200h
Maximum Memory
Used: 120 bytes
Maximum BDs:
30 (BD0 to BD29)
on all other EPs
except EP0
Available
as
Data RAM
277h
27Fh
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DS41350E-page 264 Preliminary 2010 Microchip Technology Inc.
TABLE 22-2: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT
BUFFERING MODES
TABLE 22-3: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS
Endpoint
BDs Assigned to Endpoint
Mode 0
(No Ping-Pong)
Mode 1
(Ping-Pong on EP0 OUT)
Mode 2
(Ping-Pong on all EPs)
Mode 3
(Ping-Pong on all other EPs,
except EP0)
Out In Out In Out In Out In
0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1
1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O) 4 (E), 5 (O)
2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 6 (E), 7 (O) 8 (E), 9 (O)
3 6 7 7 8 12 (E), 13 (O) 14 (E), 15 (O) 10 (E), 11 (O) 12 (E), 13 (O)
4 8 9 9 10 16 (E), 17 (O) 18 (E), 19 (O) 14 (E), 15 (O) 16 (E), 17 (O)
5 10 11 11 12 20 (E), 21 (O) 22 (E), 23 (O) 18 (E), 19 (O) 20 (E), 21 (O)
6 12 13 13 14 24 (E), 25 (O) 26 (E), 27 (O) 22 (E), 23 (O) 24 (E), 25 (O)
7 14 15 15 16 28 (E), 29 (O) 30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O)
Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BDnSTAT(1) UOWN DTS(4) PID3(2) PID2(2) PID1(2)
DTSEN(3)
PID0(2)
BSTALL(3)
BC9 BC8
BDnCNT(1) Byte Count
BDnADRL(1) Buffer Address Low
BDnADRH(1) Buffer Address High
Note 1: For buffer descriptor registers, n may have a value of 0 to 31. For the sake of brevity, all 32 registers are
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
2: Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID<3:0> values once the register
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for DTSEN and BSTALL are no longer valid.
3: Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the
BDnSTAT register are used to configure the DTSEN and BSTALL settings.
4: This bit is ignored unless DTSEN = 1.
2010 Microchip Technology Inc. Preliminary DS41350E-page 265
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22.5 USB Interrupts
The USB module can generate multiple interrupt conditions.
To accommodate all of these interrupt sources,
the module is provided with its own interrupt logic
structure, similar to that of the microcontroller. USB
interrupts are enabled with one set of control registers
and trapped with a separate set of flag registers. All
sources are funneled into a single USB interrupt
request, USBIF (PIR2<2>), in the microcontroller’s
interrupt logic.
Figure 22-7 shows the interrupt logic for the USB
module. There are two layers of interrupt registers in
the USB module. The top level consists of overall USB
Status interrupts; these are enabled and flagged in the
UIE and UIR registers, respectively. The second level
consists of USB error conditions, which are enabled
and flagged in the UEIR and UEIE registers. An
interrupt condition in any of these triggers a USB Error
Interrupt Flag (UERRIF) in the top level.
Interrupts may be used to trap routine events in a USB
transaction. Figure 22-8 shows some common events
within a USB frame and their corresponding interrupts.
FIGURE 22-7: USB INTERRUPT LOGIC FUNNEL
FIGURE 22-8: EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
BTSEF
BTSEE
BTOEF
BTOEE
DFN8EF
DFN8EE
CRC16EF
CRC16EE
CRC5EF
CRC5EE
PIDEF
PIDEE
SOFIF
SOFIE
TRNIF
TRNIE
IDLEIF
IDLEIE
STALLIF
STALLIE
ACTVIF
ACTVIE
URSTIF
URSTIE
UERRIF
UERRIE
USBIF
Second Level USB Interrupts
(USB Error Conditions)
UEIR (Flag) and UEIE (Enable) Registers
Top Level USB Interrupts
(USB Status Interrupts)
UIR (Flag) and UIE (Enable) Registers
USB Reset
RESET SOF SETUP DATA STATUS SOF
SETUPToken Data ACK
Start-of-Frame (SOF) OUT Token Empty Data ACK
IN Token Data ACK
SOFIF
URSTIF
1 ms Frame
Differential Data
From Host From Host To Host
From Host To Host From Host
From Host From Host To Host
Transaction
Control Transfer(1)
Transaction
Complete
Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.
Set TRNIF
Set TRNIF
Set TRNIF
PIC18F/LF1XK50
DS41350E-page 266 Preliminary 2010 Microchip Technology Inc.
22.5.1 USB INTERRUPT STATUS
REGISTER (UIR)
The USB Interrupt Status register (Register 22-7) contains
the flag bits for each of the USB Status interrupt
sources. Each of these sources has a corresponding
interrupt enable bit in the UIE register. All of the USB
status flags are ORed together to generate the USBIF
interrupt flag for the microcontroller’s interrupt funnel.
Once an interrupt bit has been set by the SIE, it must
be cleared by software by writing a ‘0’. The flag bits
can also be set in software which can aid in firmware
debugging.
REGISTER 22-7: UIR: USB INTERRUPT STATUS REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0
— SOFIF STALLIF IDLEIF(1) TRNIF(2) ACTVIF(3) UERRIF(4) URSTIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 SOFIF: Start-of-Frame Token Interrupt bit
1 = A Start-of-Frame token received by the SIE
0 = No Start-of-Frame token received by the SIE
bit 5 STALLIF: A STALL Handshake Interrupt bit
1 = A STALL handshake was sent by the SIE
0 = A STALL handshake has not been sent
bit 4 IDLEIF: Idle Detect Interrupt bit(1)
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
bit 3 TRNIF: Transaction Complete Interrupt bit(2)
1 = Processing of pending transaction is complete; read USTAT register for endpoint information
0 = Processing of pending transaction is not complete or no transaction is pending
bit 2 ACTVIF: Bus Activity Detect Interrupt bit(3)
1 = Activity on the D+/D- lines was detected
0 = No activity detected on the D+/D- lines
bit 1 UERRIF: USB Error Condition Interrupt bit(4)
1 = An unmasked error condition has occurred
0 = No unmasked error condition has occurred.
bit 0 URSTIF: USB Reset Interrupt bit
1 = Valid USB Reset occurred; 00h is loaded into UADDR register
0 = No USB Reset has occurred
Note 1: Once an Idle state is detected, the user may want to place the USB module in Suspend mode.
2: Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens).
3: This bit is typically unmasked only following the detection of a UIDLE interrupt event.
4: Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and
cannot be set or cleared by the user.
2010 Microchip Technology Inc. Preliminary DS41350E-page 267
PIC18F/LF1XK50
22.5.1.1 Bus Activity Detect Interrupt Bit
(ACTVIF)
The ACTVIF bit cannot be cleared immediately after
the USB module wakes up from Suspend or while the
USB module is suspended. A few clock cycles are
required to synchronize the internal hardware state
machine before the ACTVIF bit can be cleared by
firmware. Clearing the ACTVIF bit before the internal
hardware is synchronized may not have an effect on
the value of ACTVIF. Additionally, if the USB module
uses the clock from the 48 MHz PLL source, then after
clearing the SUSPND bit, the USB module may not be
immediately operational while waiting for the 48 MHz
PLL to lock. The application code should clear the
ACTVIF flag as shown in Example 22-1.
Only one ACTVIF interrupt is generated when resuming
from the USB bus Idle condition. If user firmware
clears the ACTVIF bit, the bit will not immediately
become set again, even when there is continuous bus
traffic. Bus traffic must cease long enough to generate
another IDLEIF condition before another ACTVIF
interrupt can be generated.
EXAMPLE 22-1: CLEARING ACTVIF BIT (UIR<2>)
Assembly:
BCF UCON, SUSPND
LOOP:
BTFSS UIR, ACTVIF
BRA DONE
BCF UIR, ACTVIF
BRA LOOP
DONE:
C:
UCONbits.SUSPND = 0;
while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; }
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DS41350E-page 268 Preliminary 2010 Microchip Technology Inc.
22.5.2 USB INTERRUPT ENABLE
REGISTER (UIE)
The USB Interrupt Enable register (Register 22-8)
contains the enable bits for the USB Status interrupt
sources. Setting any of these bits will enable the
respective interrupt source in the UIR register.
The values in this register only affect the propagation
of an interrupt condition to the microcontroller’s interrupt
logic. The flag bits are still set by their interrupt
conditions, allowing them to be polled and serviced
without actually generating an interrupt.
REGISTER 22-8: UIE: USB INTERRUPT ENABLE REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 SOFIE: Start-of-Frame Token Interrupt Enable bit
1 = Start-of-Frame token interrupt enabled
0 = Start-of-Frame token interrupt disabled
bit 5 STALLIE: STALL Handshake Interrupt Enable bit
1 = STALL interrupt enabled
0 = STALL interrupt disabled
bit 4 IDLEIE: Idle Detect Interrupt Enable bit
1 = Idle detect interrupt enabled
0 = Idle detect interrupt disabled
bit 3 TRNIE: Transaction Complete Interrupt Enable bit
1 = Transaction interrupt enabled
0 = Transaction interrupt disabled
bit 2 ACTVIE: Bus Activity Detect Interrupt Enable bit
1 = Bus activity detect interrupt enabled
0 = Bus activity detect interrupt disabled
bit 1 UERRIE: USB Error Interrupt Enable bit
1 = USB error interrupt enabled
0 = USB error interrupt disabled
bit 0 URSTIE: USB Reset Interrupt Enable bit
1 = USB Reset interrupt enabled
0 = USB Reset interrupt disabled
2010 Microchip Technology Inc. Preliminary DS41350E-page 269
PIC18F/LF1XK50
22.5.3 USB ERROR INTERRUPT STATUS
REGISTER (UEIR)
The USB Error Interrupt Status register (Register 22-9)
contains the flag bits for each of the error sources
within the USB peripheral. Each of these sources is
controlled by a corresponding interrupt enable bit in
the UEIE register. All of the USB error flags are ORed
together to generate the USB Error Interrupt Flag
(UERRIF) at the top level of the interrupt logic.
Each error bit is set as soon as the error condition is
detected. Thus, the interrupt will typically not
correspond with the end of a token being processed.
Once an interrupt bit has been set by the SIE, it must
be cleared by software by writing a ‘0’.
REGISTER 22-9: UEIR: USB ERROR INTERRUPT STATUS REGISTER
R/C-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF
bit 7 bit 0
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 BTSEF: Bit Stuff Error Flag bit
1 = A bit stuff error has been detected
0 = No bit stuff error
bit 6-5 Unimplemented: Read as ‘0’
bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit
1 = Bus turnaround time-out has occurred (more than 16 bit times of Idle from previous EOP elapsed)
0 = No bus turnaround time-out
bit 3 DFN8EF: Data Field Size Error Flag bit
1 = The data field was not an integral number of bytes
0 = The data field was an integral number of bytes
bit 2 CRC16EF: CRC16 Failure Flag bit
1 = The CRC16 failed
0 = The CRC16 passed
bit 1 CRC5EF: CRC5 Host Error Flag bit
1 = The token packet was rejected due to a CRC5 error
0 = The token packet was accepted
bit 0 PIDEF: PID Check Failure Flag bit
1 = PID check failed
0 = PID check passed
PIC18F/LF1XK50
DS41350E-page 270 Preliminary 2010 Microchip Technology Inc.
22.5.4 USB ERROR INTERRUPT ENABLE
REGISTER (UEIE)
The USB Error Interrupt Enable register
(Register 22-10) contains the enable bits for each of
the USB error interrupt sources. Setting any of these
bits will enable the respective error interrupt source in
the UEIR register to propagate into the UERR bit at
the top level of the interrupt logic.
As with the UIE register, the enable bits only affect the
propagation of an interrupt condition to the microcontroller’s
interrupt logic. The flag bits are still set by
their interrupt conditions, allowing them to be polled
and serviced without actually generating an interrupt.
REGISTER 22-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit
1 = Bit stuff error interrupt enabled
0 = Bit stuff error interrupt disabled
bit 6-5 Unimplemented: Read as ‘0’
bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1 = Bus turnaround time-out error interrupt enabled
0 = Bus turnaround time-out error interrupt disabled
bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit
1 = Data field size error interrupt enabled
0 = Data field size error interrupt disabled
bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit
1 = CRC16 failure interrupt enabled
0 = CRC16 failure interrupt disabled
bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit
1 = CRC5 host error interrupt enabled
0 = CRC5 host error interrupt disabled
bit 0 PIDEE: PID Check Failure Interrupt Enable bit
1 = PID check failure interrupt enabled
0 = PID check failure interrupt disabled
2010 Microchip Technology Inc. Preliminary DS41350E-page 271
PIC18F/LF1XK50
22.6 USB Power Modes
Many USB applications will likely have several different
sets of power requirements and configuration. The
most common power modes encountered are Bus
Power Only, Self-Power Only and Dual Power with
Self-Power Dominance. The most common cases are
presented here. Also provided is a means of estimating
the current consumption of the USB transceiver.
22.6.1 BUS POWER ONLY
In Bus Power Only mode, all power for the application
is drawn from the USB (Figure 22-9). This is effectively
the simplest power method for the device.
In order to meet the inrush current requirements of the
USB 2.0 specifications, the total effective capacitance
appearing across VBUS and ground must be no more
than 10 μF. If not, some kind of inrush liming is
required. For more details, see section 7.2.4 of the
USB 2.0 specification.
According to the USB 2.0 specification, all USB devices
must also support a Low-Power Suspend mode. In the
USB Suspend mode, devices must consume no more
than 500 A (or 2.5 mA for high powered devices that
are remote wake-up capable) from the 5V VBUS line of
the USB cable.
The host signals the USB device to enter the Suspend
mode by stopping all USB traffic to that device for more
than 3 ms. This condition will cause the IDLEIF bit in
the UIR register to become set.
During the USB Suspend mode, the D+ or D- pull-up
resistor must remain active, which will consume some
of the allowed suspend current: 500 A/2.5 mA budget.
FIGURE 22-9: BUS POWER ONLY
22.6.2 SELF-POWER ONLY
In Self-Power Only mode, the USB application provides
its own power, with very little power being pulled from
the USB. Figure 22-10 shows an example.
In order to meet compliance specifications, the USB
module (and the D+ or D- pull-up resistor) should not
be enabled until the host actively drives VBUS high.
The application should never source any current onto
the 5V VBUS pin of the USB cable.
FIGURE 22-10: SELF-POWER ONLY
VDD
VUSB
VSS
VBUS
VDD
VUSB
VSS
VSELF
PIC18F/LF1XK50
DS41350E-page 272 Preliminary 2010 Microchip Technology Inc.
22.6.3 DUAL POWER WITH SELF-POWER
DOMINANCE
Some applications may require a dual power option.
This allows the application to use internal power primarily,
but switch to power from the USB when no internal
power is available. Figure 22-11 shows a simple
Dual Power with Self-Power Dominance mode example,
which automatically switches between Self-Power
Only and USB Bus Power Only modes.
Dual power devices must also meet all of the special
requirements for inrush current and Suspend mode
current and must not enable the USB module until
VBUS is driven high. See Section 22.6.1 “Bus Power
Only” and Section 22.6.2 “Self-Power Only” for
descriptions of those requirements. Additionally, dual
power devices must never source current onto the 5V
VBUS pin of the USB cable.
FIGURE 22-11: DUAL POWER EXAMPLE
22.6.4 USB TRANSCEIVER CURRENT
CONSUMPTION
The USB transceiver consumes a variable amount of
current depending on the characteristic impedance of
the USB cable, the length of the cable, the VUSB supply
voltage and the actual data patterns moving across the
USB cable. Longer cables have larger capacitances
and consume more total energy when switching output
states.
Data patterns that consist of “IN” traffic consume far
more current than “OUT” traffic. IN traffic requires the
PIC® device to drive the USB cable, whereas OUT
traffic requires that the host drive the USB cable.
The data that is sent across the USB cable is NRZI
encoded. In the NRZI encoding scheme, ‘0’ bits cause
a toggling of the output state of the transceiver (either
from a “J” state to a “K” state, or vise versa). With the
exception of the effects of bit-stuffing, NRZI encoded ‘1’
bits do not cause the output state of the transceiver to
change. Therefore, IN traffic consisting of data bits of
value, ‘0’, cause the most current consumption, as the
transceiver must charge/discharge the USB cable in
order to change states.
More details about NRZI encoding and bit-stuffing can
be found in the USB 2.0 specification’s section 7.1,
although knowledge of such details is not required to
make USB applications using the
PIC18F1XK50/PIC18LF1XK50 of microcontrollers.
Among other things, the SIE handles bit-stuffing/
unstuffing, NRZI encoding/decoding and CRC
generation/checking in hardware.
The total transceiver current consumption will be
application-specific. However, to help estimate how
much current actually may be required in full-speed
applications, Equation 22-1 can be used.
Example 22-2 shows how this equation can be used for
a theoretical application.
Note: Users should keep in mind the limits for
devices drawing power from the USB.
According to USB Specification 2.0, this
cannot exceed 100 mA per low-power
device or 500 mA per high-power device.
VDD
VUSB
VSS
VBUS
VSELF
~5V
~5V
100 k
2010 Microchip Technology Inc. Preliminary DS41350E-page 273
PIC18F/LF1XK50
EQUATION 22-1: ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION
EXAMPLE 22-2: CALCULATING USB TRANSCEIVER CURRENT†
IXCVR = + IPULLUP
(60 mA • VUSB • PZERO • PIN • LCABLE)
(3.3V • 5m)
Legend: VUSB: Voltage applied to the VUSB pin in volts. (Should be 3.0V to 3.6V.)
PZERO: Percentage (in decimal) of the IN traffic bits sent by the PIC® device that are a value of ‘0’.
PIN: Percentage (in decimal) of total bus bandwidth that is used for IN traffic.
LCABLE: Length (in meters) of the USB cable. The USB 2.0 specification requires that full-speed applications
use cables no longer than 5m.
IPULLUP: Current which the nominal, 1.5 k pull-up resistor (when enabled) must supply to the USB cable. On
the host or hub end of the USB cable, 15 k nominal resistors (14.25 k to 24.8 k) are present which
pull both the D+ and D- lines to ground. During bus Idle conditions (such as between packets or during
USB Suspend mode), this results in up to 218 A of quiescent current drawn at 3.3V.
IPULLUP is also dependant on bus traffic conditions and can be as high as 2.2 mA when the USB bandwidth
is fully utilized (either IN or OUT traffic) for data that drives the lines to the “K” state most of the time.
For this example, the following assumptions are made about the application:
• 3.3V will be applied to VUSB and VDD, with the core voltage regulator enabled.
• This is a full-speed application that uses one interrupt IN endpoint that can send one packet of 64 bytes every
1 ms, with no restrictions on the values of the bytes being sent. The application may or may not have additional
traffic on OUT endpoints.
• A regular USB “B” or “mini-B” connector will be used on the application circuit board.
In this case, PZERO = 100% = 1, because there should be no restriction on the value of the data moving through
the IN endpoint. All 64 kBps of data could potentially be bytes of value, 00h. Since ‘0’ bits cause toggling of the
output state of the transceiver, they cause the USB transceiver to consume extra current charging/discharging the
cable. In this case, 100% of the data bits sent can be of value ‘0’. This should be considered the “max” value, as
normal data will consist of a fair mix of ones and zeros.
This application uses 64 kBps for IN traffic out of the total bus bandwidth of 1.5 MBps (12 Mbps), therefore:
Since a regular “B” or “mini-B” connector is used in this application, the end user may plug in any type of cable up
to the maximum allowed 5 m length. Therefore, we use the worst-case length:
LCABLE = 5 meters
Assume IPULLUP = 2.2 mA. The actual value of IPULLUP will likely be closer to 218 A, but allow for the worst-case.
USB bandwidth is shared between all the devices which are plugged into the root port (via hubs). If the application
is plugged into a USB 1.1 hub that has other devices plugged into it, your device may see host to device traffic on
the bus, even if it is not addressed to your device. Since any traffic, regardless of source, can increase the IPULLUP
current above the base 218 A, it is safest to allow for the worst-case of 2.2 mA.
Therefore:
The calculated value should be considered an approximation and additional guardband or application-specific product
testing is recommended. The transceiver current is “in addition to” the rest of the current consumed by the
PIC18F1XK50/PIC18LF1XK50 device that is needed to run the core, drive the other I/O lines, power the various
modules, etc.
Pin =
64 kBps
1.5 MBps = 4.3% = 0.043
IXCVR = (60 mA • 3.3V • 1 • 0.043 • 5m) + 2.2 mA = 4.8 mA
(3.3V • 5m)
PIC18F/LF1XK50
DS41350E-page 274 Preliminary 2010 Microchip Technology Inc.
22.7 Oscillator
The USB module has specific clock requirements. For
full-speed operation, the clock source must be 48 MHz.
Even so, the microcontroller core and other peripherals
are not required to run at that clock speed. Available
clocking options are described in detail in Section 2.11
“USB Operation”.
22.8 Interrupt-On-Change for D+/Dpins
The PIC18F/LF1XK50 has interrupt-on-change functionality
on both D+ and D- data pins. This feature
allows the device to detect voltage level changes
when first connected to a USB host/hub.
The USB host/hub has 15K pull-down resistors on the D+
and D- pins. When the PIC18F/LF1XK50 attaches to the
bus the D+ and D- pins can detect voltage changes.
External resistors are needed for each pin to maintain a
high state on the pins when detached.
The USB module must be disable (USBEN = 0) for the
interrupt-on-change to function. Enabling the USB
module (USBEN = 1) will automatically disable the
interrupt-on-change for D+ and D- pins. Refer to
Section 7.11 “PORTA and PORTB Interrupt-
on-Change” for mode detail.
22.9 USB Firmware and Drivers
Microchip provides a number of application-specific
resources, such as USB firmware and driver support.
Refer to www.microchip.com for the latest firmware and
driver support.
TABLE 22-4: REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on
Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 70
IPR2 OSCFIP C1IP C2IP EEIP BCL1IP USBIP TMR3IP — 78
PIR2 OSCFIF C1IF C2IF EEIF BCL1IF USBIF TMR3IF — 74
PIE2 OSCFIE C1IE C2IE EEIE BCL1IE USBIE TMR3IE — 76
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 252
UCFG UTEYE — — UPUEN — FSEN PPB1 PPB0 254
USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — 256
UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 258
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 252
UFRMH — — — — — FRM10 FRM9 FRM8 252
UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF 266
UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE 268
UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 269
UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 270
UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 257
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 22-3.
2010 Microchip Technology Inc. Preliminary DS41350E-page 275
PIC18F/LF1XK50
22.10 Overview of USB
This section presents some of the basic USB concepts
and useful information necessary to design a USB
device. Although much information is provided in this
section, there is a plethora of information provided
within the USB specifications and class specifications.
Thus, the reader is encouraged to refer to the USB
specifications for more information (www.usb.org). If
you are very familiar with the details of USB, then this
section serves as a basic, high-level refresher of USB.
22.10.1 LAYERED FRAMEWORK
USB device functionality is structured into a layered
framework graphically shown in Figure 22-12. Each
level is associated with a functional level within the
device. The highest layer, other than the device, is the
configuration. A device may have multiple configurations.
For example, a particular device may have
multiple power requirements based on Self-Power Only
or Bus Power Only modes.
For each configuration, there may be multiple
interfaces. Each interface could support a particular
mode of that configuration.
Below the interface is the endpoint(s). Data is directly
moved at this level. There can be as many as
16 bidirectional endpoints. Endpoint 0 is always a
control endpoint and by default, when the device is on
the bus, Endpoint 0 must be available to configure the
device.
22.10.2 FRAMES
Information communicated on the bus is grouped into
1 ms time slots, referred to as frames. Each frame can
contain many transactions to various devices and
endpoints. Figure 22-8 shows an example of a
transaction within a frame.
22.10.3 TRANSFERS
There are four transfer types defined in the USB
specification.
• Isochronous: This type provides a transfer
method for large amounts of data (up to
1023 bytes) with timely delivery ensured;
however, the data integrity is not ensured. This is
good for streaming applications where small data
loss is not critical, such as audio.
• Bulk: This type of transfer method allows for large
amounts of data to be transferred with ensured
data integrity; however, the delivery timeliness is
not ensured.
• Interrupt: This type of transfer provides for
ensured timely delivery for small blocks of data,
plus data integrity is ensured.
• Control: This type provides for device setup
control.
While full-speed devices support all transfer types,
low-speed devices are limited to interrupt and control
transfers only.
22.10.4 POWER
Power is available from the Universal Serial Bus. The
USB specification defines the bus power requirements.
Devices may either be self-powered or bus powered.
Self-powered devices draw power from an external
source, while bus powered devices use power supplied
from the bus.
FIGURE 22-12: USB LAYERS
Device
Configuration
Interface
Endpoint
Interface
Endpoint Endpoint Endpoint Endpoint
To other Configurations (if any)
To other Interfaces (if any)
PIC18F/LF1XK50
DS41350E-page 276 Preliminary 2010 Microchip Technology Inc.
The USB specification limits the power taken from the
bus. Each device is ensured 100 mA at approximately
5V (one unit load). Additional power may be requested,
up to a maximum of 500 mA. Note that power above
one unit load is a request and the host or hub is not
obligated to provide the extra current. Thus, a device
capable of consuming more than one unit load must be
able to maintain a low-power configuration of a one unit
load or less, if necessary.
The USB specification also defines a Suspend mode.
In this situation, current must be limited to 500 A,
averaged over 1 second. A device must enter a
Suspend state after 3 ms of inactivity (i.e., no SOF
tokens for 3 ms). A device entering Suspend mode
must drop current consumption within 10 ms after
Suspend. Likewise, when signaling a wake-up, the
device must signal a wake-up within 10 ms of drawing
current above the Suspend limit.
22.10.5 ENUMERATION
When the device is initially attached to the bus, the host
enters an enumeration process in an attempt to identify
the device. Essentially, the host interrogates the device,
gathering information such as power consumption, data
rates and sizes, protocol and other descriptive
information; descriptors contain this information. A
typical enumeration process would be as follows:
1. USB Reset: Reset the device. Thus, the device
is not configured and does not have an address
(address 0).
2. Get Device Descriptor: The host requests a
small portion of the device descriptor.
3. USB Reset: Reset the device again.
4. Set Address: The host assigns an address to the
device.
5. Get Device Descriptor: The host retrieves the
device descriptor, gathering info such as
manufacturer, type of device, maximum control
packet size.
6. Get configuration descriptors.
7. Get any other descriptors.
8. Set a configuration.
The exact enumeration process depends on the host.
22.10.6 DESCRIPTORS
There are eight different standard descriptor types of
which five are most important for this device.
22.10.6.1 Device Descriptor
The device descriptor provides general information,
such as manufacturer, product number, serial number,
the class of the device and the number of configurations.
There is only one device descriptor.
22.10.6.2 Configuration Descriptor
The configuration descriptor provides information on
the power requirements of the device and how many
different interfaces are supported when in this configuration.
There may be more than one configuration for a
device (i.e., low-power and high-power configurations).
22.10.6.3 Interface Descriptor
The interface descriptor details the number of endpoints
used in this interface, as well as the class of the
interface. There may be more than one interface for a
configuration.
22.10.6.4 Endpoint Descriptor
The endpoint descriptor identifies the transfer type
(Section 22.10.3 “Transfers”) and direction, as well
as some other specifics for the endpoint. There may be
many endpoints in a device and endpoints may be
shared in different configurations.
22.10.6.5 String Descriptor
Many of the previous descriptors reference one or
more string descriptors. String descriptors provide
human readable information about the layer
(Section 22.10.1 “Layered Framework”) they
describe. Often these strings show up in the host to
help the user identify the device. String descriptors are
generally optional to save memory and are encoded in
a unicode format.
22.10.7 BUS SPEED
Each USB device must indicate its bus presence and
speed to the host. This is accomplished through a
1.5 k resistor which is connected to the bus at the
time of the attachment event.
Depending on the speed of the device, the resistor
either pulls up the D+ or D- line to 3.3V. For a
low-speed device, the pull-up resistor is connected to
the D- line. For a full-speed device, the pull-up resistor
is connected to the D+ line.
22.10.8 CLASS SPECIFICATIONS AND
DRIVERS
USB specifications include class specifications which
operating system vendors optionally support.
Examples of classes include Audio, Mass Storage,
Communications and Human Interface (HID). In most
cases, a driver is required at the host side to ‘talk’ to the
USB device. In custom applications, a driver may need
to be developed. Fortunately, drivers are available for
most common host systems for the most common
classes of devices. Thus, these drivers can be reused.
2010 Microchip Technology Inc. Preliminary DS41350E-page 277
PIC18F/LF1XK50
23.0 RESET
The PIC18F/LF1XK50 devices differentiate between
various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 3.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 24.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 23-1.
23.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 23-1). The lower five bits of the register
indicate that a specific Reset event has occurred.
In most cases, these bits can only be cleared by the
event and must be set by the application after the
event. The state of these flag bits, taken together, can
be read to indicate the type of Reset that just occurred.
This is described in more detail in Section 23.6 “Reset
State of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 7.0 “Interrupts”. BOR is covered in
Section 23.4 “Brown-out Reset (BOR)”.
FIGURE 23-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR
VDD
OSC1
WDT
Time-out
VDD Rise
Detect
OST/PWRT
LFINTOSC
POR Pulse
OST(2)
10-bit Ripple Counter
PWRT(2)
11-bit Ripple Counter
Enable OST(1)
Enable PWRT
Note 1: See Table 23-2 for time-out situations.
2: PWRT and OST counters are reset by POR and BOR. See Sections 23.3 and 23.4.
Brown-out
Reset
BOREN
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
1024 Cycles
32 s 65.5 ms
MCLRE
S
R Q
Chip_Reset
PIC18F/LF1XK50
DS41350E-page 278 Preliminary 2010 Microchip Technology Inc.
REGISTER 23-1: RCON: RESET CONTROL REGISTER
R/W-0 R/W-1 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN SBOREN(1) — RI TO PD POR(2) BOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’