TSV6390, TSV6390A, TSV6391, TSV6391A - Farnell Element 14
TSV6390, TSV6390A, TSV6391, TSV6391A - Farnell Element 14
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Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
![[TXT]](http://www.audentia-gestion.fr/icons/text.gif)
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TSV6390, TSV6390A, TSV6391, TSV6391A
Micropower (60 μA), wide bandwidth (2.4 MHz) CMOS op-amps
Features
■ Low offset voltage: 500 μV max (A version)
■ Low power consumption: 60 μA typ at 5 V
■ Low supply voltage: 1.5 V – 5.5 V
■ Gain bandwidth product: 2.4 MHz typical
■ Stable in gain configuration (-3 or +4)
■ Low power shutdown mode: 5 nA typical
■ High output current: 63 mA at VCC= 5 V
■ Low input bias current: 1 pA typical
■ Rail-to-rail input and output
■ Extended temperature range: -40°C to +125°C
■ 4 kV human body model
Applications
■ Battery-powered applications
■ Portable devices
■ Signal conditioning
■ Active filtering
■ Medical instrumentation
Description
The TSV6390 and TSV6391 devices are single
operational amplifiers offering low voltage, low
power operation and rail-to-rail input and output.
With a very low input bias current and low offset
voltage (500 μV maximum for the A version), the
TSV6390 and TSV6391 are ideal for applications
requiring precision. The devices can operate at
power supplies ranging from 1.5 to 5.5 V, and are
therefore ideal for battery-powered devices,
extending battery life.
When used with a gain (above -3 or +4), these
products feature an excellent speed/power
consumption ratio, offering a 2.4 MHz gain
bandwidth product while consuming only 60 μA at
a 5 V supply voltage.
The TSV6390 comes with a shutdown function.
Both the TSV6390 and TSV6391 have a high
tolerance to ESD, sustaining 4 kV for the human
body model.
Additionally, they are offered in micropackages,
SC70-6 and SOT23-6 for the TSV6390 and
SC70-5 and SOT23-5 for the TSV6391. They are
guaranteed for industrial temperature ranges from
-40° C to +125° C.
All these features combined make the TSV6390
and TSV6391 ideal for sensor interfaces,
battery-supplied and portable applications, as
well as active filtering.
TSV6390ICT/ILT
TSV6391ICT/ILT
SC70-6/SOT23-6
SC70-5/SOT23-5
VCCIn+
In- Out
1
2
3
6
4
+_ 5 SHDN
VCC+
VCCIn+
In- Out
1
2
3
5
4
+_
VCC+
www.st.com
Contents TSV6390, TSV6390A, TSV6391, TSV6391A
2/22 Doc ID 17118 Rev 1
Contents
1 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Rail-to-rail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 Shutdown function (TSV6390) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 Optimization of DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6 Driving resistive and capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7 PCB layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.8 Macromodel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 SOT23-5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 SOT23-6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 SC70-5 (or SOT323-5) package mechanical data . . . . . . . . . . . . . . . . . . 17
4.4 SC70-6 (or SOT323-6) package mechanical data . . . . . . . . . . . . . . . . . . 18
5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TSV6390, TSV6390A, TSV6391, TSV6391A Absolute maximum ratings and operating conditions
Doc ID 17118 Rev 1 3/22
1 Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings (AMR)
Symbol Parameter Value Unit
VCC Supply voltage(1)
1. All voltage values, except differential voltages, are with respect to network ground terminal.
6 V
Vid Differential input voltage (2)
2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal.
±VCC V
Vin Input voltage (3)
3. VCC-Vin must not exceed 6 V, Vin must not exceed 6 V.
VCC- -0.2 to VCC+ +0.2 V
Iin Input current (4)
4. Input current must be limited by a resistor in series with the inputs.
10 mA
SHDN Shutdown voltage(3) VCC- -0.2 to VCC+ +0.2 V
Tstg Storage temperature -65 to +150 °C
Rthja
Thermal resistance junction to ambient(5)(6)
SC70-5
SOT23-5
SOT23-6
SC70-6
5. Short-circuits can cause excessive heating and destructive dissipation.
6. Rth are typical values.
205
250
240
232
°C/W
Tj Maximum junction temperature 150 °C
ESD
HBM: human body model(7)
7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for
all couples of pin combinations with other pins floating.
4 kV
MM: machine model(8)
8. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between
two pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin
combinations with other pins floating.
300 V
CDM: charged device model(9)
9. Charged device model: all pins plus package are charged together to the specified voltage and then
discharged directly to the ground.
1.5 kV
Latch-up immunity 200 mA
Table 2. Operating conditions
Symbol Parameter Value Unit
VCC Supply voltage 1.5 to 5.5 V
Vicm Common mode input voltage range VCC- -0.1 to VCC+ +0.1 V
Toper Operating free air temperature range -40 to +125 °C
Electrical characteristics TSV6390, TSV6390A, TSV6391, TSV6391A
4/22 Doc ID 17118 Rev 1
2 Electrical characteristics
Table 3. Electrical characteristics at VCC+ = +1.8 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C
and RL connected to VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
Vio Offset voltage
TSV6390-TSV6391
TSV6390A-TSV6391A
3
0.5
mV
Tmin < Top < Tmax
TSV6390-TSV6391
TSV6390A-TSV6391A
4.5
2
DVio Input offset voltage drift 2 μV/°C
Iio
Input offset current (1)
(Vout = VCC/2)
1 10
pA
Tmin < Top < Tmax 1 100
Iib
Input bias current(1)
(Vout = VCC/2)
1 10
pA
Tmin < Top < Tmax 1 100
CMR
Common mode rejection ratio
20 log (ΔVic/ΔVio)
0 V to 1.8 V, Vout = 0.9 V 53 74
dB
Tmin < Top < Tmax 51
Avd Large signal voltage gain
RL= 10 kΩ, Vout = 0.5 V to 1.3 V 85 95
dB
Tmin < Top < Tmax 80
VOH High level output voltage
RL = 10 kΩ 35 5
mV
Tmin < Top < Tmax 50
VOL Low level output voltage
RL = 10 kΩ 4 35
mV
Tmin < Top < Tmax 50
Iout
Isink
Vout = 1.8 V 6 12
mA
Tmin < Top < Tmax 4
Isource
Vout = 0 V 6 10
mA
Tmin < Top < Tmax 4
ICC
Supply current
SHDN = VCC
No load, Vout = VCC/2 40 50 60
μA
Tmin < Top < Tmax 62
AC performance
GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 2 MHz
Gain Minimum gain for stability
Phase margin = 60°, Rf = 10 kΩ,
RL = 10 kΩ, CL = 20 pF
+4
-3
V/V
SR Slew rate
RL = 10 kΩ, CL = 100 pF,
Vout = 0.5 V to 1.3 V
0.7 V/μs
en Equivalent input noise voltage
f = 1 kHz
f = 10 kHz
60
33
1. Guaranteed by design.
nV
Hz
-----------
TSV6390, TSV6390A, TSV6391, TSV6391A Electrical characteristics
Doc ID 17118 Rev 1 5/22
Table 4. Shutdown characteristics VCC = 1.8 V (TSV6390)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
ICC
Supply current in shutdown
mode (all operators)
SHDN = VCC- 2.5 50 nA
Tmin < Top < 85° C 200 nA
Tmin < Top < 125° C 1.5 μA
ton Amplifier turn-on time
RL = 2 kΩ,
Vout = VCC- to VCC - + 0.2 V
300 ns
toff Amplifier turn-off time
RL = 2 kΩ, Vout = VCC+ - 0.5 V to
VCC+ - 0.7 V
20 ns
VIH SHDN logic high 1.3 V
VIL SHDN logic low 0.5 V
IIH SHDN current high SHDN = VCC+ 10 pA
IIL SHDN current low SHDN = VCC- 10 pA
IOLeak
Output leakage in shutdown
mode
SHDN = VCC- 50 pA
Tmin < Top < Tmax 1 nA
Electrical characteristics TSV6390, TSV6390A, TSV6391, TSV6391A
6/22 Doc ID 17118 Rev 1
Table 5. VCC+ = +3.3 V, VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C, RL connected to VCC/2
(unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
Vio Offset voltage
TSV6390-TSV6391
TSV6390A-TSV6391A
3
0.5
mV
Tmin < Top < Tmax
TSV6390-TSV6391
TSV6390A-TSV6391A
4.5
2
DVio Input offset voltage drift 2 μV/°C
Iio Input offset current(1)
1 10
pA
Tmin < Top < Tmax 1 100
Iib Input bias current(1)
1 10
pA
Tmin < Top < Tmax 1 100
CMR
Common mode rejection
ratio 20 log (ΔVic/ΔVio)
0 V to 3.3 V, Vout = 1.65 V 57 79
dB
Tmin < Top < Tmax 53
Avd Large signal voltage gain
RL = 10 kΩ, Vout = 0.5 V to 2.8 V 88 98
dB
Tmin < Top < Tmax 83
VOH High level output voltage
RL = 10 kΩ 35 6
mV
Tmin. < Top < Tmax 50
VOL Low level output voltage
RL = 10 kΩ 7 35
mV
Tmin < Top < Tmax 50
Iout
Isink
Vout = 3.3 V 23 45
mA
Tmin < Top < Tmax 20 42
Isource
Vout = 0 V 23 38
mA
Tmin < Top < Tmax 20
ICC
Supply current
SHDN = VCC
No load, Vout= VCC/2 43 55 64 μA
Tmin < Top < Tmax 66 μA
AC performance
GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 2.2 MHz
Gain Minimum gain for stability
Phase margin = 60°, Rf = 10 kΩ,
RL = 10 kΩ, CL = 20 pF,
+4
-3
V/V
SR Slew rate
RL = 10 kΩ, CL = 100 pF,
Vout = 0.5 V to 2.8 V
0.9 V/μs
en
Equivalent input noise
voltage
f = 1 kHz 65
1. Guaranteed by design.
nV
Hz
-----------
TSV6390, TSV6390A, TSV6391, TSV6391A Electrical characteristics
Doc ID 17118 Rev 1 7/22
Table 6. Electrical characteristics at VCC+ = +5 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C and
RL connected to VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
Vio Offset voltage
TSV6390-TSV6391
TSV6390A-TSV6391A
3
0.5
mV
Tmin < Top < Tmax
TSV6390-TSV6391
TSV6390A-TSV6391A
4.5
2
mV
DVio Input offset voltage drift 2 μV/°C
Iio
Input offset current(1)
(Vout = VCC/2)
1 10
pA
Tmin < Top < Tmax 1 100
Iib
Input bias current(1)
(Vout = VCC/2)
1 10
pA
Tmin < Top < Tmax 1 100
CMR
Common mode rejection ratio
20 log (ΔVic/ΔVio)
0 V to 5 V, Vout = 2.5 V 60 80
dB
Tmin < Top < Tmax 55
SVR
Supply voltage rejection ratio
20 log (ΔVCC/ΔVio)
VCC = 1.8 to 5 V 75 93
dB
Tmin < Top < Tmax 73
Avd Large signal voltage gain
RL= 10 kΩ, Vout= 0.5 V to 4.5 V 89 98
dB
Tmin < Top < Tmax 84
VOH High level output voltage
RL = 10 kΩ 35 7
mV
Tmin < Top < Tmax 50
VOL Low level output voltage
RL = 10 kΩ 6 35
mV
Tmin < Top < Tmax 50
Iout
Isink
Vout = 5 V 40 65
mA
Tmin < Top < Tmax 35
Isource
Vout = 0 V 40 72 mA
Tmin < Top < Tmax 35
ICC
Supply current
SHDN = VCC
No load, Vout=VCC/2 50 60 69
μA
Tmin < Top < Tmax 72
AC performance
GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 2.4 MHz
Gain Minimum gain for stability
Phase margin = 60°, Rf = 10 kΩ,
RL = 10 kΩ, CL = 20 pF,
+4
-3
V/V
SR Slew rate RL = 10 kΩ, CL = 100 pF 1.1 V/μs
Electrical characteristics TSV6390, TSV6390A, TSV6391, TSV6391A
8/22 Doc ID 17118 Rev 1
en Equivalent input noise voltage
f = 1 kHz
f = 10 kHz
60
33
THD+N
Total harmonic distortion +
noise
Av = -10, fin = 1 kHz, R= 100 kΩ,
Vicm = Vcc/2, Vin = 40 mVpp
0.11 %
1. Guaranteed by design.
Table 6. Electrical characteristics at VCC+ = +5 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C and
RL connected to VCC/2 (unless otherwise specified) (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit
nV
Hz
-----------
Table 7. Shutdown characteristics VCC = 5 V (TSV6390)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
ICC
Supply current in shutdown
mode (all operators)
SHDN = VCC- 5 50 nA
Tmin < Top < 85° C 200 nA
Tmin < Top < 125° C 1.5 μA
ton Amplifier turn-on time
RL = 2 kΩ,
Vout = VCC- to VCC - + 0.2 V
300 ns
toff Amplifier turn-off time
RL = 2 Ω, Vout = VCC+ - 0.5 V to
VCC+ - 0.7 V
30 ns
VIH SHDN logic high 4.5 V
VIL SHDN logic low 0.5 V
IIH SHDN current high SHDN = VCC+ 10 pA
IIL SHDN current low SHDN = VCC- 10 pA
IOLeak
Output leakage in shutdown
mode
SHDN = VCC- 50 pA
Tmin < Top < Tmax 1 nA
TSV6390, TSV6390A, TSV6391, TSV6391A Electrical characteristics
Doc ID 17118 Rev 1 9/22
Figure 1. Supply current vs. supply voltage
at Vicm = VCC/2
Figure 2. Output current vs. output voltage at
VCC = 1.5 V
Figure 3. Output current vs. output voltage at
VCC = 5 V
Figure 4. Peaking at closed loop gain = -10
10000 100000 1000000
0
5
10
15
20
VCC=5V
VCC=1.5V
Closed loop gain = -10
T=25 C,CLoad=100pF, Vicm=VCC/2,
RLoad=2.2kΩ for Iout giving
minimum stability on a typical part
Gain (dB)
Frequency (Hz)
Figure 5. Peaking at closed loop gain = -3 at
VCC = 1.5 V
Figure 6. Peaking at closed loop gain = -3 at
VCC = 5 V
10000 100000 1000000
0
2
4
6
8
10
12
14
RLoad=100kΩ
RLoad T=25 C, V =2.2kΩ icm=VCC/2
ACL=-3, VCC=1.5V
CLoad=33pF
RLoad= 100kΩ connected to VCC/2
RLoad= 2.2kΩ for Iout giving
minimum stability on a typical part
Gain (dB)
Frequency (Hz)
10000 100000 1000000
0
2
4
6
8
10
12
14
RLoad=2.2kΩ
T=25 C, Vicm=VCC/2
ACL=-3, VCC=5V
CLoad=33pF
RLoad=100kΩ
RLoad= 100kΩ connected to VCC/2
RLoad= 2.2kΩ for Iout giving
minimum stability on a typical part
Gain (dB)
Frequency (Hz)
Electrical characteristics TSV6390, TSV6390A, TSV6391, TSV6391A
10/22 Doc ID 17118 Rev 1
Figure 7. Positive slew rate vs. supply
voltage
Figure 8. Negative slew rate vs. supply
voltage
Figure 9. Distortion + noise vs. output
voltage at VCC = 1.8 V
Figure 10. Distortion + noise vs. output
voltage at VCC = 5 V
RLoad=2kΩ, CLoad=100pF, ACL=−10
Vin: from 0.5V to VCC+− 0.5V
SR calculated from 10% to 90%
Vicm=VCC/2
T=25°C
T=125°C
T=−40°C
Slew rate (V/ s)
Supply voltage (V)
T=25°C
RLoad=2kΩ, CLoad=100pF, ACL=−10
Vin: from VCC+−0.5V to 0.5V
SR calculated from 10% to 90%
Vicm=VCC/2
T=125°C
T=−40°C
Slew rate (V/ s)
Supply voltage (V)
Ω
Ω
THD + N (%)
Output voltage (Vrms)
Ω
Ω
THD + N (%)
Ouput voltage (Vrms)
Figure 11. Slew rate timing Figure 12. Noise vs. frequency at VCC = 5 V
Vin
Vout
RLoad=2kΩ, CLoad=100pF,
Vicm=VCC/2, ACL=−10
T=25°C, VCC=5V
Amplitude (V)
Time (μs) 10 100 1000 10000
10
100
Equivalent Input Voltage Noise (nV/VHz)
Vcc=5V
Tamb=25 C
Vicm=4.5V
Vicm=2.5V
TSV6390, TSV6390A, TSV6391, TSV6391A Application information
Doc ID 17118 Rev 1 11/22
3 Application information
3.1 Operating voltages
The TSV6390 and TSV6391 can operate from 1.5 to 5.5 V. Their parameters are fully
specified for 1.8, 3.3 and 5 V power supplies. However, the parameters are very stable in the
full VCC range and several characterization curves show the TSV639x characteristics at
1.5 V. Additionally, the main specifications are guaranteed in extended temperature ranges
from -40° C to +125° C.
3.2 Rail-to-rail input
The TSV6390 and TSV6391 are built with two complementary PMOS and NMOS input
differential pairs. The devices have a rail-to-rail input, and the input common mode range is
extended from VCC- -0.1 V to VCC+ +0.1 V. The transition between the two pairs appears at
VCC+ -0.7 V. In the transition region, the performance of CMRR, PSRR, Vio and THD is
slightly degraded (as shown in Figure 13 and Figure 14 for Vio vs. Vicm).
The devices are guaranteed without phase reversal.
3.3 Rail-to-rail output
The operational amplifiers’ output levels can go close to the rails: 35 mV maximum above
and below the rail when connected to a 10 kΩ resistive load to VCC/2.
3.4 Shutdown function (TSV6390)
The operational amplifier is enabled when the SHDN pin is pulled high. To disable the
amplifier, the SHDN must be pulled down to VCC-. When in shutdown mode, the amplifier’s
output is in a high impedance state. The SHDN pin must never be left floating, but tied to
VCC+ or VCC-.
Figure 13. Input offset voltage vs input
common mode at VCC = 1.5 V
Figure 14. Input offset voltage vs input
common mode at VCC = 5 V
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
Input Offset Voltage (mV)
Input Common Mode Voltage (V)
0.0 1.0 2.0 3.0 4.0 5.0
-0.4
-0.2
0.0
0.2
0.4
Input Offset Voltage (mV)
Input Common Mode Voltage (V)
Application information TSV6390, TSV6390A, TSV6391, TSV6391A
12/22 Doc ID 17118 Rev 1
The turn-on and turn-off times are calculated for an output variation of ±200 mV (Figure 15
and Figure 16 show the test configurations).
Figure 15. Test configuration for turn-on time
(Vout pulled down)
Figure 16. Test configuration for turn-off time
(Vout pulled down)
+ VCC GND
2 KΩ
+
-
DUT
GND
VCC - 0.5 V
+ VCC GND
2 KΩ
+
-
DUT
GND
VCC - 0.5 V
Figure 17. Turn-on time, VCC = 5 V,
Vout pulled down, T = 25° C
Figure 18. Turn-off time, VCC= 5 V,
Vout pulled down, T = 25° C
Shutdown pulse
Vout
Vcc = 5V
T = 25°C
Voltage (V)
Time( s)
Shutdown pulse
Vout
Vcc = 5V
T = 25°C
Output voltage (V) Time( s)
TSV6390, TSV6390A, TSV6391, TSV6391A Application information
Doc ID 17118 Rev 1 13/22
3.5 Optimization of DC and AC parameters
These devices use an innovative approach to reduce the spread of the main DC and AC
parameters. An internal adjustment achieves a very narrow spread of the current
consumption (60 μA typical, min/max at ±17 %). Parameters linked to the current
consumption value, such as GBP, SR and AVd, benefit from this narrow dispersion.
3.6 Driving resistive and capacitive loads
These products are micropower, low-voltage operational amplifiers optimized to drive rather
large resistive loads, above 2 kΩ. For lower resistive loads, the THD level may significantly
increase.
These operational amplifiers have a relatively low internal compensation capacitor, making
them very fast while consuming very little. They are ideal when used in a non-inverting
configuration or in an inverting configuration in the following conditions.
● IGainI ≥ 3 in an inverting configuration (CL = 20 pF, RL = 100 kΩ) or IgainI ≥ 10
(CL = 100 pF, RL = 100 kΩ)
● Gain ≥ +4 in a non-inverting configuration (CL = 20 pF, RL = 100 kΩ) or gain ≥ +11
(CL = 100 pF, RL= 100 kΩ)
As these operational amplifiers are not unity gain stable, for a low closed-loop gain it is
recommended to use the TSV62x (29 μA, 420 kHz) or TSV63x (60 μA, 880 kHz) which are
unity gain stable.
3.7 PCB layouts
For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible
to the power supply pins.
3.8 Macromodel
An accurate macromodel of the TSV6390 and TSV6391 is available on STMicroelectronics’
web site at www.st.com. This model is a trade-off between accuracy and complexity (that is,
time simulation) of the TSV639x operational amplifiers. It emulates the nominal
performances of a typical device within the specified operating conditions mentioned in the
datasheet. It also helps to validate a design approach and to select the right operational
amplifier, but it does not replace on-board measurements.
Table 8. Related products
Part # Icc (μA) at 5 V GBP (MHz) SR (V/μs)
Minimum gain for
stability
(CLoad = 100 pF)
TSV620-1 29 0.42 0.14 1
TSV6290-1 29 1.3 0.5 +11
TSV630-1 60 0.88 0.34 1
TSV6390-1 60 2.4 1.1 +11
Package information TSV6390, TSV6390A, TSV6391, TSV6391A
14/22 Doc ID 17118 Rev 1
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
TSV6390, TSV6390A, TSV6391, TSV6391A Package information
Doc ID 17118 Rev 1 15/22
4.1 SOT23-5 package mechanical data
Figure 19. SOT23-5L package mechanical drawing
Table 9. SOT23-5L package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.90 1.20 1.45 0.035 0.047 0.057
A1 0.15 0.006
A2 0.90 1.05 1.30 0.035 0.041 0.051
B 0.35 0.40 0.50 0.013 0.015 0.019
C 0.09 0.15 0.20 0.003 0.006 0.008
D 2.80 2.90 3.00 0.110 0.114 0.118
D1 1.90 0.075
e 0.95 0.037
E 2.60 2.80 3.00 0.102 0.110 0.118
F 1.50 1.60 1.75 0.059 0.063 0.069
L 0.10 0.35 0.60 0.004 0.013 0.023
K 0° 10°
Package information TSV6390, TSV6390A, TSV6391, TSV6391A
16/22 Doc ID 17118 Rev 1
4.2 SOT23-6 package mechanical data
Figure 20. SOT23-6L package mechanical drawing
Table 10. SOT23-6L package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.90 1.45 0.035 0.057
A1 0.10 0.004
A2 0.90 1.30 0.035 0.051
b 0.35 0.50 0.013 0.019
c 0.09 0.20 0.003 0.008
D 2.80 3.05 0.110 0.120
E 1.50 1.75 0.060 0.069
e 0.95 0.037
H 2.60 3.00 0.102 0.118
L 0.10 0.60 0.004 0.024
° 0 10°
TSV6390, TSV6390A, TSV6391, TSV6391A Package information
Doc ID 17118 Rev 1 17/22
4.3 SC70-5 (or SOT323-5) package mechanical data
Figure 21. SC70-5 (or SOT323-5) package mechanical drawing
Table 11. SC70-5 (or SOT323-5) package mechanical data
Ref
Dimensions
Millimeters Inches
Min Typ Max Min Typ Max
A 0.80 1.10 0.315 0.043
A1 0.10 0.004
A2 0.80 0.90 1.00 0.315 0.035 0.039
b 0.15 0.30 0.006 0.012
c 0.10 0.22 0.004 0.009
D 1.80 2.00 2.20 0.071 0.079 0.087
E 1.80 2.10 2.40 0.071 0.083 0.094
E1 1.15 1.25 1.35 0.045 0.049 0.053
e 0.65 0.025
e1 1.30 0.051
L 0.26 0.36 0.46 0.010 0.014 0.018
< 0° 8°
SEATING PLANE
GAUGE PLANE
DIMENSIONS IN MM
SIDE VIEW
TOP VIEW
COPLANAR LEADS
Package information TSV6390, TSV6390A, TSV6391, TSV6391A
18/22 Doc ID 17118 Rev 1
4.4 SC70-6 (or SOT323-6) package mechanical data
Figure 22. SC70-6 (or SOT323-6) package mechanical drawing
Table 12. SC70-6 (or SOT323-6) package mechanical data
Ref
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.80 1.10 0.031 0.043
A1 0.10 0.004
A2 0.80 1.00 0.031 0.039
b 0.15 0.30 0.006 0.012
c 0.10 0.18 0.004 0.007
D 1.80 2.20 0.071 0.086
E 1.15 1.35 0.045 0.053
e 0.65 0.026
HE 1.80 2.40 0.071 0.094
L 0.10 0.40 0.004 0.016
Q1 0.10 0.40 0.004 0.016
TSV6390, TSV6390A, TSV6391, TSV6391A Package information
Doc ID 17118 Rev 1 19/22
Figure 23. SC70-6 (or SOT323-6) package footprint
Ordering information TSV6390, TSV6390A, TSV6391, TSV6391A
20/22 Doc ID 17118 Rev 1
5 Ordering information
Table 13. Order codes
Part number
Temperature
range
Package Packing Marking
TSV6390ILT
-40°C to +125°C
SOT23-6
Tape & reel
K109
TSV6390ICT SC70-6 K19
TSV6390AILT SOT23-6 K142
TSV6390AICT SC70-6 K42
TSV6391ILT SOT23-5 K108
TSV6391ICT SC70-5 K20
TSV6391AILT SOT23-5 K141
TSV6391AICT SC70-5 K41
TSV6390, TSV6390A, TSV6391, TSV6391A Revision history
Doc ID 17118 Rev 1 21/22
6 Revision history
Table 14. Document revision history
Date Revision Changes
09-Mar-2010 1 Initial release.
TSV6390, TSV6390A, TSV6391, TSV6391A
22/22 Doc ID 17118 Rev 1
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General Description
The MAX3222E/MAX3232E/MAX3237E/MAX3241E/
MAX3246E +3.0V-powered EIA/TIA-232 and V.28/V.24
communications interface devices feature low power consumption,
high data-rate capabilities, and enhanced
electrostatic-discharge (ESD) protection. The enhanced
ESD structure protects all transmitter outputs and
receiver inputs to ±15kV using IEC 1000-4-2 Air-Gap
Discharge, ±8kV using IEC 1000-4-2 Contact Discharge
(±9kV for MAX3246E), and ±15kV using the Human Body
Model. The logic and receiver I/O pins of the MAX3237E
are protected to the above standards, while the transmitter
output pins are protected to ±15kV using the Human
Body Model.
A proprietary low-dropout transmitter output stage delivers
true RS-232 performance from a +3.0V to +5.5V power
supply, using an internal dual charge pump. The charge
pump requires only four small 0.1μF capacitors for operation
from a +3.3V supply. Each device guarantees operation
at data rates of 250kbps while maintaining RS-232
output levels. The MAX3237E guarantees operation at
250kbps in the normal operating mode and 1Mbps in the
MegaBaud™ operating mode, while maintaining RS-232-
compliant output levels.
The MAX3222E/MAX3232E have two receivers and two
transmitters. The MAX3222E features a 1μA shutdown
mode that reduces power consumption in battery-powered
portable systems. The MAX3222E receivers remain
active in shutdown mode, allowing monitoring of external
devices while consuming only 1μA of supply current. The
MAX3222E and MAX3232E are pin, package, and functionally
compatible with the industry-standard MAX242
and MAX232, respectively.
The MAX3241E/MAX3246E are complete serial ports
(three drivers/five receivers) designed for notebook and
subnotebook computers. The MAX3237E (five drivers/
three receivers) is ideal for peripheral applications that
require fast data transfer. These devices feature a shutdown
mode in which all receivers remain active, while
consuming only 1μA (MAX3241E/MAX3246E) or 10nA
(MAX3237E).
The MAX3222E, MAX3232E, and MAX3241E are available
in space-saving SO, SSOP, TQFN and TSSOP packages.
The MAX3237E is offered in an SSOP package.
The MAX3246E is offered in the ultra-small 6 x 6 UCSP™
package.
Applications
Battery-Powered Equipment Printers
Cell Phones Smart Phones
Cell-Phone Data Cables xDSL Modems
Notebook, Subnotebook,
and Palmtop Computers
Next-Generation Device Features
♦ For Space-Constrained Applications
MAX3228E/MAX3229E: ±15kV ESD-Protected,
+2.5V to +5.5V, RS-232 Transceivers in UCSP
♦ For Low-Voltage or Data Cable Applications
MAX3380E/MAX3381E: +2.35V to +5.5V, 1μA,
2Tx/2Rx, RS-232 Transceivers with ±15kV
ESD-Protected I/O and Logic Pins MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
________________________________________________________________ Maxim Integrated Products 1
19-1298; Rev 10; 1/06
_______________Ordering Information
Ordering Information continued at end of data sheet.
*Dice are tested at TA = +25°C, DC parameters only.
**EP = Exposed paddle.
Pin Configurations, Selector Guide, and Typical Operating
Circuits appear at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE
PINPACKAGE
PKG
CODE
MAX3222ECTP 0°C to +70°C
20 Thin QFNEP**
(5mm x
5mm)
T2055-5
MAX3222ECUP 0°C to +70°C 20 TSSOP —
MAX3222ECAP 0°C to +70°C 20 SSOP —
MAX3222ECWN 0°C to +70°C 18 Wide SO —
MAX3222ECPN 0°C to +70°C 18 Plastic DIP —
MAX3222EC/D 0°C to +70°C Dice* —
MAX3222EETP -40°C to +85°C
20 Thin QFNEP**
(5mm x
5mm)
T2055-5
MAX3222EEUP -40°C to +85°C 20 TSSOP —
MAX3222EEAP -40°C to +85°C 20 SSOP —
MAX3222EEWN -40°C to +85°C 18 Wide SO —
MAX3222EEPN -40°C to +85°C 18 Plastic DIP —
MAX3232ECAE 0°C to +70°C 16 SSOP —
MAX3232ECWE 0°C to +70°C 16 Wide SO —
MAX3232ECPE 0°C to +70°C 16 Plastic DIP —
MegaBaud and UCSP are trademarks of Maxim Integrated
Products, Inc.
†Covered by U.S. Patent numbers 4,636,930; 4,679,134;
4,777,577; 4,797,899; 4,809,152; 4,897,774; 4,999,761; and
other patents pending.
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = +3V to +5.5V, C1–C4 = 0.1μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 3, 4)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to GND..............................................................-0.3V to +6V
V+ to GND (Note 1) ..................................................-0.3V to +7V
V- to GND (Note 1) ...................................................+0.3V to -7V
V+ + |V-| (Note 1).................................................................+13V
Input Voltages
T_IN, EN, SHDN, MBAUD to GND ........................-0.3V to +6V
R_IN to GND .....................................................................±25V
Output Voltages
T_OUT to GND...............................................................±13.2V
R_OUT, R_OUTB (MAX3241E)................-0.3V to (VCC + 0.3V)
Short-Circuit Duration, T_OUT to GND.......................Continuous
Continuous Power Dissipation (TA = +70°C)
16-Pin SSOP (derate 7.14mW/°C above +70°C) ..........571mW
16-Pin TSSOP (derate 9.4mW/°C above +70°C) .......754.7mW
16-Pin TQFN (derate 20.8mW/°C above +70°C) .....1666.7mW
16-Pin Wide SO (derate 9.52mW/°C above +70°C) .....762mW
18-Pin Wide SO (derate 9.52mW/°C above +70°C) .....762mW
18-Pin PDIP (derate 11.11mW/°C above +70°C)..........889mW
20-Pin TQFN (derate 21.3mW/°C above +70°C) ........1702mW
20-Pin TSSOP (derate 10.9mW/°C above +70°C) ........879mW
20-Pin SSOP (derate 8.00mW/°C above +70°C) ..........640mW
28-Pin SSOP (derate 9.52mW/°C above +70°C) ..........762mW
28-Pin Wide SO (derate 12.50mW/°C above +70°C).............1W
28-Pin TSSOP (derate 12.8mW/°C above +70°C) ......1026mW
32-Lead Thin QFN (derate 33.3mW/°C above +70°C)..2666mW
6 x 6 UCSP (derate 12.6mW/°C above +70°C).............1010mW
Operating Temperature Ranges
MAX32_ _EC_ _ ...................................................0°C to +70°C
MAX32_ _EE_ _.................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Bump Reflow Temperature (Note 2)
Infrared, 15s..................................................................+200°C
Vapor Phase, 20s..........................................................+215°C
Note 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.
Note 2: This device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device
can be exposed to during board-level solder attach and rework. This limit permits only the use of the solder profiles recommended
in the industry-standard specification, JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and convection reflow.
Preheating is required. Hand or wave soldering is not allowed.
PARAMETER CONDITIONS MIN TYP MAX UNITS
DC CHARACTERISTICS (VCC = +3.3V or +5V, TA = +25°C)
MAX3222E, MAX3232E,
MAX3241E, MAX3246E
0.3 1
Supply Current SHDN = VCC, no load
MAX3237E 0.5 2.0
mA
SHDN = GND 1 10 μA
Shutdown Supply Current
SHDN = R_IN = GND, T_IN = GND or VCC (MAX3237E) 10 300 nA
LOGIC INPUTS
Input Logic Low T_IN, EN, SHDN, MBAUD 0.8 V
VCC = +3.3V 2.0
Input Logic High T_IN, EN, SHDN, MBAUD
VCC = +5.0V 2.4
V
Transmitter Input Hysteresis 0.5 V
T_IN, EN, SHDN
MAX3222E, MAX3232E,
MAX3241E, MAX3246E
±0.01 ±1
Input Leakage Current
T_IN, SHDN, MBAUD MAX3237E (Note 5) 9 18
μA
RECEIVER OUTPUTS
Output Leakage Current
R_OUT (MAX3222E/MAX3237E/MAX3241E/
MAX3246E), EN = VCC, receivers disabled
±0.05 ±10 μA
Output-Voltage Low
IOUT = 1.6mA (MAX3222E/MAX3232E/MAX3241E/
MAX3246E), IOUT = 1.0mA (MAX3237E)
0.4 V
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3V to +5.5V, C1–C4 = 0.1μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 3, 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output-Voltage High IOUT = -1.0mA
VCC -
0.6
VCC -
0.1
V
RECEIVER INPUTS
Input Voltage Range -25 +25 V
VCC = +3.3V 0.6 1.1
Input Threshold Low TA = +25°C
VCC = +5.0V 0.8 1.5
V
VCC = +3.3V 1.5 2.4
Input Threshold High TA = +25°C
VCC = +5.0V 2.0 2.4
V
Input Hysteresis 0.5 V
Input Resistance TA = +25°C 3 5 7 kΩ
TRANSMITTER OUTPUTS
Output Voltage Swing
All transmitter outputs loaded with 3kΩ to ground
(Note 6)
±5 ±5.4 V
Output Resistance VCC = 0, transmitter output = ±2V 300 50k Ω
Output Short-Circuit Current ±60 mA
Output Leakage Current
V C C = 0 or + 3.0V to + 5.5V , V OU T = ± 12V , tr ansm i tter s
d i sab l ed ( M AX 3222E /M AX 3232E /M AX 3241E /M AX 3246E )
±25 μA
MOUSE DRIVABILITY (MAX3241E)
Transmitter Output Voltage
T1IN = T2IN = GND, T3IN = VCC, T3OUT loaded with
3kΩ to GND, T1OUT and T2OUT loaded with 2.5mA
each
±5 V
ESD PROTECTION
Human Body Model ±15
IEC 1000-4-2 Air-Gap Discharge (except MAX3237E) ±15
IEC 1000-4-2 Contact Discharge (except MAX3237E) ±8
R_IN, T_OUT
IEC 1000-4-2 Contact Discharge (MAX3246E only) ±9
kV
Human Body Model ±15
IEC1000-4-2 Air-Gap Discharge ±15
T_IN, R_IN, R_OUT, EN, SHDN,
MBAUD
MAX3237E
IEC1000-4-2 Contact Discharge ±8
kV
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS—MAX3237E
(VCC = +3V to +5.5V, C1–C4 = 0.1μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
Note 3:MAX3222E/MAX3232E/MAX3241E: C1–C4 = 0.1μF tested at +3.3V ±10%; C1 = 0.047μF, C2, C3, C4 = 0.33μF tested at +5.0V
±10%. MAX3237E: C1–C4 = 0.1μF tested at +3.3V ±5%, C1–C4 = 0.22μF tested at +3.3V ±10%; C1 = 0.047μF, C2, C3, C4 =
0.33μF tested at +5.0V ±10%. MAX3246E; C1-C4 = 0.22μF tested at +3.3V ±10%; C1 = 0.22μF, C2, C3, C4 = 0.54μF tested at
5.0V ±10%.
Note 4: MAX3246E devices are production tested at +25°C. All limits are guaranteed by design over the operating temperature range.
Note 5: The MAX3237E logic inputs have an active positive feedback resistor. The input current goes to zero when the inputs are at
the supply rails.
Note 6: MAX3241EEUI is specified at TA = +25°C.
Note 7: Transmitter skew is measured at the transmitter zero crosspoints.
PARAMETER CONDITIONS MIN TYP MAX UNITS
RL = 3kΩ, CL = 1000pF, one transmitter switching,
MBAUD = GND
250
VCC = +3.0V to +4.5V, RL = 3kΩ, CL = 250pF,
one transmitter switching, MBAUD = VCC
Maximum Data Rate 1000
VCC = +4.5V to +5.5V, RL = 3kΩ, CL = 1000pF,
one transmitter switching, MBAUD = VCC
1000
kbps
tPHL 0.15
Receiver Propagation Delay R_IN to R_OUT, CL = 150pF
tPLH 0.15
μs
Receiver Output Enable Time Normal operation 2.6 μs
Receiver Output Disable Time Normal operation 2.4 μs
| tPHL - tPLH |, MBAUD = GND
Transmitter Skew (Note 7)
| tPHL - tPLH |, MBAUD = VCC
100 ns
Receiver Skew | tPHL - tPLH | 50 ns
CL = 150pF MBAUD = GND 6 30
to 1000pF
MBAUD = VCC 24 150
VCC = +3.3V,
RL = 3kΩ to 7kΩ,
+3.0V to -3.0V or
-3.0V to +3.0V,
TA = +25°C
CL = 150pF to 2500pF,
MBAUD = GND
4 30
Transition-Region Slew Rate V/μs
TIMING CHARACTERISTICS—MAX3222E/MAX3232E/MAX3241E/MAX3246E
(VCC = +3V to +5.5V, C1–C4 = 0.1μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 3, 4)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TA = TMIN to TMAX
(MAX3222E/MAX3232E/
MAX3241E) (Note 6)
250
Maximum Data Rate
RL = 3kΩ,
CL = 1000pF,
one transmitter
switching TA = + 25°C ( M AX 3246E ) 250
kbps
tPHL 0.15
Receiver Propagation Delay
tPLH
Receiver input to receiver output,
CL = 150pF 0.15
μs
Receiver Output Enable Time Normal operation (except MAX3232E) 200 ns
Receiver Output Disable Time Normal operation (except MAX3232E) 200 ns
Transmitter Skew |tPHL - tPLH| (Note 7) 100 ns
Receiver Skew |tPHL - tPLH| 50 ns
Transition-Region Slew Rate
V C C = + 3.3V , TA = + 25°C ,
RL = 3kΩ to 7kΩ , m easur ed
fr om + 3.0V to - 3.0V or - 3.0V to
+ 3.0V , one tr ansm i tter sw i tchi ng
CL = 150pF
to 1000pF
6 30 V/μs
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
_______________________________________________________________________________________ 5
-6
-4
-2
0
2
4
6
0
MAX3237E
TRANSMITTER OUTPUT VOLTAGE
vs. LOAD CAPACITANCE (MBAUD = GND)
MAX3237E toc07
LOAD CAPACITANCE (pF)
TRANSMITTER OUTPUT VOLTAGE (V)
500 1000 1500 2000 2500 3000
FOR DATA RATES UP TO 250kbps
1 TRANSMITTER AT 250kbps
4 TRANSMITTERS AT 15.6kbps
ALL TRANSMITTERS LOADED
WITH 3kΩ + CL
5
3
1
-1
-3
-5
VOUT+
VOUT-
-6
-2
-4
2
0
4
6
-5
-3
1
-1
3
5
0 500 1000 1500 2000 2500 3000
MAX3246E toc07A
LOAD CAPACITANCE (pF)
TRANSMITTER OUTPUT VOLTAGE (V)
VOUTVOUT+
FOR DATA RATES UP TO 250kbps
1 TRANSMITTER 250kbps
4 TRANSMITTERS 15.6kbps
ALL TRANSMITTERS LOADED
WITH 3kΩ + CL
MAX3237E
TRANSMITTER OUTPUT VOLTAGE
vs. LOAD CAPACITANCE
-7.5
-5.0
-2.5
0
2.5
5.0
7.5
0
MAX3237E
TRANSMITTER OUTPUT VOLTAGE
vs. LOAD CAPACITANCE (MBAUD = VCC)
MAX3237E toc08
LOAD CAPACITANCE (pF)
TRANSMITTER OUTPUT VOLTAGE (V)
500 1000 1500 2000
1 TRANSMITTER AT FULL DATA RATE
4 TRANSMITTERS AT 1/16 DATA RATE
3kΩ + CL LOAD, EACH OUTPUT
2Mbps 1.5Mbps
1Mbps
2Mbps
1Mbps
1.5Mbps
__________________________________________Typical Operating Characteristics
(VCC = +3.3V, 250kbps data rate, 0.1μF capacitors, all transmitters loaded with 3kΩ and CL, TA = +25°C, unless otherwise noted.)
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
0 1000 2000 3000 4000 5000
MAX3241E
TRANSMITTER OUTPUT VOLTAGE
vs. LOAD CAPACITANCE
MAX3237E to04
LOAD CAPACITANCE (pF)
TRANSMITTER OUTPUT VOLTAGE (V)
1 TRANSMITTER AT 250kbps
2 TRANSMITTERS AT 15.6kbps
VOUT+
VOUT-
0
30
20
10
40
50
60
0 1000 2000 3000 4000 5000
MAX3241E
OPERATING SUPPLY CURRENT
vs. LOAD CAPACITANCE
MAX3237E toc06
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
250kbps
120kbps
20kbps
1 TRANSMITTER AT 250kbps
2 TRANSMITTERS AT 15.6kbps
0
4
2
8
6
12
10
14
0 1000 2000 3000 4000 5000
MAX3241E
SLEW RATE vs. LOAD CAPACITANCE
MAX3237E toc05
LOAD CAPACITANCE (pF)
SLEW RATE (V/μs)
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
0 1000 2000 3000 4000 5000
MAX3222E/MAX3232E
TRANSMITTER OUTPUT VOLTAGE
vs. LOAD CAPACITANCE
MAX3237E toc01
LOAD CAPACITANCE (pF)
TRANSMITTER OUTPUT VOLTAGE (V)
T1 TRANSMITTING AT 250kbps
T2 TRANSMITTING AT 15.6kbps
VOUT+
VOUT-
0
6
2
4
10
8
14
12
16
0 1000 2000 3000 4000 5000
MAX3222E/MAX3232E
SLEW RATE vs. LOAD CAPACITANCE
MAX3237E toc02
LOAD CAPACITANCE (pF)
SLEW RATE (V/μs)
+SLEW
FOR DATA RATES UP TO 250kbps
-SLEW
0
25
20
15
5
10
35
30
40
45
0 1000 2000 3000 4000 5000
MAX3222E/MAX3232E
OPERATING SUPPLY CURRENT
vs. LOAD CAPACITANCE
MAX3237E toc03
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
250kbps
120kbps
20kbps
T1 TRANSMITTING AT 250kbps
T2 TRANSMITTING AT 15.6kbps
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VCC = +3.3V, 250kbps data rate, 0.1μF capacitors, all transmitters loaded with 3kΩ and CL, TA = +25°C, unless otherwise noted.)
0
20
60
40
80
100
0
MAX3237E
TRANSMITTER SKEW vs. LOAD CAPACITANCE
(MBAUD = VCC)
MAX3237E toc12
LOAD CAPACITANCE (pF)
500 1000 1500 2000
TRANSMITTER SKEW (ns)
|tPLH - tPHL|
1 TRANSMITTER AT 500kbps
4 TRANSMITTERS AT 1/16 DATA RATE
ALL TRANSMITTERS LOADED
WITH 3kΩ + CL -6
-2
-4
2
0
4
6
-3
-5
1
-1
3
5
2.0 2.5 3.0 3.5 4.0 4.5 5.0
MAX3237E toc13
SUPPLY VOLTAGE (V)
TRANSMITTER OUTPUT VOLTAGE (V)
VOUTVOUT+
1 TRANSMITTER AT 250kbps
4 TRANSMITTERS AT 15.6kbps
ALL TRANSMITTERS LOADED
WITH 3kΩ +1000pF
MAX3237E
TRANSMITTER OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE (MBAUD = GND)
0
10
20
30
40
50
2.0
MAX3237E SUPPLY CURRENT
vs. SUPPLY VOLTAGE (MBAUD = GND)
MAX3237E toc14
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
2.5 3.0 3.5 4.0 4.5 5.0
1 TRANSMITTER AT 250kbps
4 TRANSMITTERS AT 15.6kbps
ALL TRANSMITTERS LOADED
WITH 3kΩ AND 1000pF
MAX3246E
TRANSMITTER OUTPUT VOLTAGE
vs. LOAD CAPACITANCE
MAX3237E toc15
LOAD CAPACITANCE (pF)
TRANSMITTER OUTPUT VOLTAGE (V)
1000 2000 3000 4000
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
-6
0 5000
1 TRANSMITTER AT 250kbps
2 TRANSMITTERS AT 15.6kbps
VOUTVOUT+
4
6
8
10
12
14
16
0
MAX3246E
SLEW RATE vs. LOAD CAPACITANCE
MAX3237E toc16
LOAD CAPACITANCE (pF)
SLEW RATE (V/μs)
1000 2000 3000 4000 5000
SR+
SR-
0
10
20
30
40
50
60
0
MAX3246E
OPERATING SUPPLY CURRENT
vs. LOAD CAPACITANCE
MAX3237E toc17
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
1000 2000 3000 4000 5000
1 TRANSMITTER AT 250kbps
2 TRANSMITTERS AT 15.6kbps
55
45
35
25
15
5
250kbps
120kbps
20kbps
0
2
4
6
8
10
12
0
MAX3237E
SLEW RATE vs. LOAD CAPACITANCE
(MBAUD = GND)
MAX3237E toc09
LOAD CAPACITANCE (pF)
SLEW RATE (V/μs)
500 1000 1500 2000 2500 3000
SR+
SR-
1 TRANSMITTER AT 250kbps
4 TRANSMITTERS AT 15.6kbps
ALL TRANSMITTERS LOADED
WITH 3kΩ + CL
0
10
20
30
50
40
60
70
0
MAX3237E
SLEW RATE vs. LOAD CAPACITANCE
(MBAUD = VCC)
MAX3237E toc10
LOAD CAPACITANCE (pF)
SLEW RATE (V/μs)
500 1000 1500 2000
-SLEW, 1Mbps
+SLEW, 1Mbps
1 TRANSMITTER AT FULL DATA RATE
4 TRANSMITTERS AT 1/16 DATA RATE
3kΩ + CL LOAD EACH OUTPUT
-SLEW, 2Mbps
+SLEW, 2Mbps
0
10
20
30
40
50
0
MAX3237E
SUPPLY CURRENT vs. LOAD CAPACITANCE
WHEN TRANSMITTING DATA (MBAUD = GND)
MAX3237E toc11
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
500 1000 1500 2000 2500 3000
250kbps
120kbps
20kbps
1 TRANSMITTER AT 20kbps, 120kbps, 250kbps
4 TRANSMITTERS AT 15.6kbps
ALL TRANSMITTERS LOADED
WITH 3kΩ + CL
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
_______________________________________________________________________________________ 7
*These pins have an active positive feedback resistor internal to the MAX3237E, allowing unused inputs to be left unconnected.
Pin Description
PIN
MAX3222E MAX3232E MAX3241E
TQFN SO/
DIP
TSSOP/
SSOP TQFN
SO/DIP/
SSOP/
16-PIN
TSSOP
20-PIN
TSSOP
MAX3237E SSOP/
SO QFN
MAX3246E
NAME FUNCTION
19 1 1 — — — 13* 23 22 B3 EN
Receiver Enable. Active
low.
1 2 2 16 1 2 28 28 28 F3 C1+
Positive Terminal of
Voltage-Doubler Charge-
Pump Capacitor
20 3 3 15 2 3 27 27 27 F1 V+ +5.5V Generated by the
Charge Pump
2 4 4 1 3 4 25 24 23 F4 C1-
Negative Terminal of
Voltage-Doubler Charge-
Pump Capacitor
3 5 5 2 4 5 1 1 29 E1 C2+
Positive Terminal of
Inverting Charge-Pump
Capacitor
4 6 6 3 5 6 3 2 30 D1 C2-
Negative Terminal of
Inverting Charge-Pump
Capacitor
5 7 7 4 6 7 4 3 31 C1 V- -5.5V Generated by the
Charge Pump
6, 15 8,
15 8, 17 5,
12 7, 14 8, 17 5, 6, 7,
10, 12
9,
10,
11
6,
7,
8
F6, E6,
D6 T_OUT RS-232 Transmitter
Outputs
7, 14 9,
14 9, 16 6,
11 8, 13 9, 16 8, 9, 11 4–8 1–5
A4, A5,
A6, B6,
C6
R_IN RS-232 Receiver Inputs
8, 13 10,
13 10, 15 7,
10 9, 12 12,
15
18, 20,
21
15–19
13,
14,
15,
17, 18
C2, B1,
A1, A2,
A3
R_OUT TTL/CMOS Receiver
Outputs
10, 11 11,
12 12, 13 8, 9 10, 11 13,
14
17*, 19*,
22*, 23*,
24*
12,
13,
14
10,
11,
12
E3, E2,
D2 T_IN TTL/CMOS Transmitter
Inputs
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
8 _______________________________________________________________________________________
Pin Description (continued)
PIN
MAX3222E MAX3232E MAX3241E
TQFN SO/
DIP
TSSOP/
SSOP TQFN
SO/DIP/
SSOP/
16-PIN
TSSOP
20-PIN
TSSOP
MAX3237E SSOP/
SO/
TSSOP
QFN
MAX3246E
NAME FUNCTION
16 16 18 13 15 18 2 25 24 F5 GND Ground
17 17 19 14 16 19 26 26 26 F2 VCC
+3.0V to +5.5V Supply
Voltage
18 18 20 — — — 14* 22 21 B2 SHDN
Shutdown Control. Active
low.
9, 12 — 11, 14 — — 1, 10,
11, 20 — —
9, 16,
25,
32
C3, D3, B4,
C4, D4, E4,
B5, C5, D5,
E5
N.C.
No Connection. For
MAX3246E, these
locations are not
populated with solder
bumps.
— — — — — — 15* — — — MBAUD
MegaBaud Control Input.
Connect to GND for
normal operation; connect
to VCC for 1Mbps
transmission rates.
— — — — — — 16 20,
21 19, 20 — R_OUTB
Noninverting
Complementary Receiver
Outputs. Always active.
EP — — EP — — — — EP — GND
Exposed Paddle. Solder
the exposed paddle to
the ground alone or leave
unconnected.
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
_______________________________________________________________________________________ 9
Detailed Description
Dual Charge-Pump Voltage Converter
The MAX3222E/MAX3232E/MAX3237E/MAX3241E/
MAX3246Es’ internal power supply consists of a regulated
dual charge pump that provides output voltages
of +5.5V (doubling charge pump) and -5.5V (inverting
charge pump) over the +3.0V to +5.5V VCC range. The
charge pump operates in discontinuous mode; if the
output voltages are less than 5.5V, the charge pump is
enabled, and if the output voltages exceed 5.5V, the
charge pump is disabled. Each charge pump requires
a flying capacitor (C1, C2) and a reservoir capacitor
(C3, C4) to generate the V+ and V- supplies (Figure 1).
RS-232 Transmitters
The transmitters are inverting level translators that convert
TTL/CMOS-logic levels to ±5V EIA/TIA-232-compliant
levels.
The MAX3222E/MAX3232E/MAX3237E/MAX3241E/
MAX3246E transmitters guarantee a 250kbps data rate
with worst-case loads of 3kΩ in parallel with 1000pF,
providing compatibility with PC-to-PC communication
software (such as LapLink™). Transmitters can be paralleled
to drive multiple receivers or mice.
The MAX3222E/MAX3237E/MAX3241E/MAX3246E
transmitters are disabled and the outputs are forced
into a high-impedance state when the device is in shutdown
mode (SHDN = GND). The MAX3222E/
MAX3232E/MAX3237E/MAX3241E/MAX3246E permit
the outputs to be driven up to ±12V in shutdown.
The MAX3222E/MAX3232E/MAX3241E/MAX3246E
transmitter inputs do not have pullup resistors. Connect
unused inputs to GND or VCC. The MAX3237E’s transmitter
inputs have a 400kΩ active positive-feedback
resistor, allowing unused inputs to be left unconnected.
MAX3237E MegaBaud Operation
For higher-speed serial communications, the
MAX3237E features MegaBaud operation. In
MegaBaud operating mode (MBAUD = VCC), the
MAX3237E transmitters guarantee a 1Mbps data rate
with worst-case loads of 3kΩ in parallel with 250pF for
+3.0V < VCC < +4.5V. For +5V ±10% operation, the
MAX3237E transmitters guarantee a 1Mbps data rate
into worst-case loads of 3kΩ in parallel with 1000pF.
RS-232 Receivers
The receivers convert RS-232 signals to CMOS-logic
output levels. The MAX3222E/MAX3237E/MAX3241E/
MAX3246E receivers have inverting three-state outputs.
Drive EN high to place the receiver(s) into a highimpedance
state. Receivers can be either active or
inactive in shutdown (Table 1).
MAX3222E
MAX3232E
MAX3237E
MAX3241E
MAX3246E
5kΩ
R_ OUT R_ IN
C2-
C2+
C1-
C1+
VV+
VCC
C4
C1 C3
C2
0.1μF
VCC
T_ IN T_ OUT
GND
7kΩ 150pF
MAX3222E
MAX3232E
MAX3237E
MAX3241E
MAX3246E
5kΩ
R_ OUT R_ IN
C2-
C2+
C1-
C1+
VV+
VCC
C4
C1 C3
C2
0.1μF
VCC
T_ IN T_ OUT
GND 3kΩ
1000pF
(2500pF, MAX3237E only)
MINIMUM SLEW-RATE TEST CIRCUIT MAXIMUM SLEW-RATE TEST CIRCUIT
Figure 1. Slew-Rate Test Circuits
LapLink is a trademark of Traveling Software.
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
10 ______________________________________________________________________________________
The complementary outputs on the MAX3237E/
MAX3241E (R_OUTB) are always active, regardless of the
state of EN or SHDN. This allows the device to be used
for ring indicator applications without forward biasing
other devices connected to the receiver outputs. This is
ideal for systems where VCC drops to zero in shutdown
to accommodate peripherals such as UARTs (Figure 2).
MAX3222E/MAX3237E/MAX3241E/
MAX3246E Shutdown Mode
Supply current falls to less than 1μA in shutdown mode
(SHDN = low). The MAX3237E’s supply current falls
to10nA (typ) when all receiver inputs are in the invalid
range (-0.3V < R_IN < +0.3). When shut down, the
device’s charge pumps are shut off, V+ is pulled down
to VCC, V- is pulled to ground, and the transmitter outputs
are disabled (high impedance). The time required
to recover from shutdown is typically 100μs, as shown
in Figure 3. Connect SHDN to VCC if shutdown mode is
not used. SHDN has no effect on R_OUT or R_OUTB
(MAX3237E/MAX3241E).
±15kV ESD Protection
As with all Maxim devices, ESD-protection structures
are incorporated to protect against electrostatic discharges
encountered during handling and assembly.
The driver outputs and receiver inputs of the
MAX3222E/MAX3232E/MAX3237E/MAX3241E/MAX3246E
have extra protection against static electricity. Maxim’s
engineers have developed state-of-the-art structures to
protect these pins against ESD of ±15kV without damage.
The ESD structures withstand high ESD in all states:
normal operation, shutdown, and powered down. After
an ESD event, Maxim’s E versions keep working without
latchup, whereas competing RS-232 products can latch
and must be powered down to remove latchup.
Furthermore, the MAX3237E logic I/O pins also have
±15kV ESD protection. Protecting the logic I/O pins to
±15kV makes the MAX3237E ideal for data cable
applications.
T1OUT
R1OUTB
Tx
5kΩ
UART
VCC
T1IN
LOGIC
TRANSITION
DETECTOR
R1OUT R1IN
THREE-STATED
EN = VCC
SHDN = GND
VCC
TO
μP
Rx
PREVIOUS
RS-232
Tx
UART
PROTECTION
DIODE
PROTECTION
DIODE
SHDN = GND
VCC
VCC
GND
Rx
5kΩ
a) OLDER RS-232: POWERED-DOWN UART DRAWS CURRENT FROM
A ACTIVE RECEIVER OUTPUT IN SHUTDOWN.
b) NEW MAX3237E/MAX3241E: EN SHUTS DOWN RECEIVER OUTPUTS
B (EXCEPT FOR B OUTPUTS), SO NO CURRENT FLOWS TO UART IN SHUTDOWN.
B B OUTPUTS INDICATE RECEIVER ACTIVITY DURING SHUTDOWN WITH EN HIGH.
GND
MAX3237E/MAX3241E
Figure 2. Detection of RS-232 Activity when the UART and
Interface are Shut Down; Comparison of MAX3237E/MAX3241E
(b) with Previous Transceivers (a)
40μs/div
SHDN
T2OUT
T1OUT
5V/div
0
2V/div
0
VCC = 3.3V
C1–C4 = 0.1μF
Figure 3. Transmitter Outputs Recovering from Shutdown or
Powering Up
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
______________________________________________________________________________________ 11
ESD protection can be tested in various ways; the
transmitter outputs and receiver inputs for the
MAX3222E/MAX3232E/MAX3241E/MAX3246E are
characterized for protection to the following limits:
• ±15kV using the Human Body Model
• ±8kV using the Contact Discharge method specified
in IEC 1000-4-2
• ±9kV (MAX3246E only) using the Contact Discharge
method specified in IEC 1000-4-2
• ±15kV using the Air-Gap Discharge method specified
in IEC 1000-4-2
CHARGE-CURRENTLIMIT
RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1MΩ
RD
1500Ω
HIGHVOLTAGE
DC
SOURCE
DEVICEUNDERTEST
Figure 4a. Human Body ESD Test Model
IP 100%
90%
36.8%
tRL
TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
0
AMPERES
Figure 4b. Human Body Model Current Waveform
CHARGE-CURRENTLIMIT
RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
RC
50MΩ to 100MΩ
RD
330Ω
HIGHVOLTAGE
DC
SOURCE
DEVICEUNDERTEST
Figure 5a. IEC 1000-4-2 ESD Test Model
tr = 0.7ns to 1ns
30ns
60ns
t
100%
90%
10%
IPEAK
I
Figure 5b. IEC 1000-4-2 ESD Generator Current Waveform
Table 1. MAX3222E/MAX3237E/MAX3241E/
MAX3246E Shutdown and Enable Control
Truth Table
SHDN EN T_OUT R_OUT
R_OUTB
(MAX3237E/
MAX3241E)
0 0
High
impedance
Active Active
0 1
High
impedance
High
impedance
Active
1 0 Active Active Active
1 1 Active
High
impedance
Active
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
12 ______________________________________________________________________________________
For the MAX3237E, all logic and RS-232 I/O pins are
characterized for protection to ±15kV per the Human
Body Model.
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Human Body Model
Figure 4a shows the Human Body Model, and Figure
4b shows the current waveform it generates when discharged
into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the test device through a
1.5kΩ resistor.
IEC 1000-4-2
The IEC 1000-4-2 standard covers ESD testing and
performance of finished equipment; it does not specifically
refer to integrated circuits. The MAX3222E/
MAX3232E/MAX3237E/MAX3241E/MAX3246E help you
design equipment that meets level 4 (the highest level)
of IEC 1000-4-2, without the need for additional ESDprotection
components.
The major difference between tests done using the
Human Body Model and IEC 1000-4-2 is higher peak
current in IEC 1000-4-2, because series resistance is
lower in the IEC 1000-4-2 model. Hence, the ESD withstand
voltage measured to IEC 1000-4-2 is generally
lower than that measured using the Human Body
Model. Figure 5a shows the IEC 1000-4-2 model, and
Figure 5b shows the current waveform for the ±8kV IEC
1000-4-2 level 4 ESD Contact Discharge test. The Air-
Gap Discharge test involves approaching the device
with a charged probe. The Contact Discharge method
connects the probe to the device before the probe is
energized.
Machine Model
The Machine Model for ESD tests all pins using a
200pF storage capacitor and zero discharge resistance.
Its objective is to emulate the stress caused by
contact that occurs with handling and assembly during
manufacturing. All pins require this protection during
manufacturing, not just RS-232 inputs and outputs.
Therefore, after PC board assembly, the Machine
Model is less relevant to I/O ports.
Table 2. Required Minimum Capacitor
Values
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
0 1 2 3 4 5 6 7 8 9 10
MAX3222E-fig06a
LOAD CURRENT PER TRANSMITTER (mA)
TRANSMITTER OUTPUT VOLTAGE (V)
VOUT+
VOUTVOUT+
VCC VOUTVCC
= 3.0V
Figure 6a. MAX3241E Transmitter Output Voltage vs. Load
Table 3. Logic-Family Compatibility with Current Per Transmitter
Various Supply Voltages
VCC
(V)
C1
(μF)
C2, C3, C4
(μF)
MAX3222E/MAX3232E/MAX3241E
3.0 to 3.6 0.1 0.1
4.5 to 5.5 0.047 0.33
3.0 to 5.5 0.1 0.47
MAX3237E/MAX3246E
3.0 to 3.6 0.22 0.22
3.15 to 3.6 0.1 0.1
4.5 to 5.5 0.047 0.33
3.0 to 5.5 0.22 1.0
SYSTEM
POWER-SUPPLY
VOLTAGE
(V)
VCC SUPPLY
VOLTAGE
(V)
COMPATIBILITY
3.3 3.3
Compatible with all
CMOS families
5 5
Compatible with all
TTL and CMOS
families
5 3.3
C om p ati b l e w i th AC T
and H C T C M OS , and
w i th AC , H C , or
C D 4000 C M O S
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
______________________________________________________________________________________ 13
Applications Information
Capacitor Selection
The capacitor type used for C1–C4 is not critical for
proper operation; polarized or nonpolarized capacitors
can be used. The charge pump requires 0.1μF capacitors
for 3.3V operation. For other supply voltages, see
Table 2 for required capacitor values. Do not use values
smaller than those listed in Table 2. Increasing the
capacitor values (e.g., by a factor of 2) reduces ripple
on the transmitter outputs and slightly reduces power
consumption. C2, C3, and C4 can be increased without
changing C1’s value. However, do not increase C1
without also increasing the values of C2, C3, C4,
and CBYPASS to maintain the proper ratios (C1 to
the other capacitors).
When using the minimum required capacitor values,
make sure the capacitor value does not degrade
excessively with temperature. If in doubt, use capacitors
with a larger nominal value. The capacitor’s equivalent
series resistance (ESR), which usually rises at low
temperatures, influences the amount of ripple on V+
and V-.
Power-Supply Decoupling
In most circumstances, a 0.1μF VCC bypass capacitor
is adequate. In applications sensitive to power-supply
noise, use a capacitor of the same value as chargepump
capacitor C1. Connect bypass capacitors as
close to the IC as possible.
Operation Down to 2.7V
Transmitter outputs meet EIA/TIA-562 levels of ±3.7V
with supply voltages as low as 2.7V.
MAX3241E
23 EN
15 R5OUT
16 R4OUT
17 R3OUT
18 R2OUT
19 R1OUT
20 R2OUTB
21 R1OUTB
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
R5IN 8
VCC
R4IN 7
6
R2IN 5
R1IN 4
SHDN 22
GND
25
12 T3IN
13 T2IN
14 T1IN
2 C2-
1 C2+
24 C1-
28 C1+
T3OUT 11
+V
COMPUTER SERIAL PORT
+V
-V
GND
Tx
T2OUT 10
T1OUT 9
V-
3
V+
VCC 27
VCC
C4
C1 C3
C2
CBYPASS
VCC = +3.0V TO +5.5V
26
R3IN
MOUSE
Figure 6b. Mouse Driver Test Circuit
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
14 ______________________________________________________________________________________
Figure 7. Loopback Test Circuit
2μs/div
T1IN
T1OUT
R1OUT
5V/div
5V/div
V 5V/div CC = 3.3V
C1–C4 = 0.1μF
Figure 8. MAX3241E Loopback Test Result at 120kbps
2μs/div
T1IN
T1OUT
R1OUT
5V/div
5V/div
5V/div
VCC = 3.3V, C1–C4 = 0.1μF
Figure 9. MAX3241E Loopback Test Result at 250kbps
+5V
0
+5V
0
-5V
+5V
0
T_IN
T_OUT
5kΩ + 250pF
R_OUT
400ns/div
VCC = 3.3V
C1–C4 = 0.1μF
Figure 10. MAX3237E Loopback Test Result at 1000kbps
(MBAUD = VCC)
MAX3222E
MAX3232E
MAX3237E
MAX3241E
MAX3246E
5kΩ
R_ OUT R_ IN
C2-
C2+
C1-
C1+
VV+
VCC
C4
C1 C3
C2
0.1μF
VCC
T_ IN T_ OUT
GND
1000pF
Transmitter Outputs Recovering
from Shutdown
Figure 3 shows two transmitter outputs recovering from
shutdown mode. As they become active, the two transmitter
outputs are shown going to opposite RS-232 levels
(one transmitter input is high; the other is low). Each
transmitter is loaded with 3kΩ in parallel with 2500pF.
The transmitter outputs display no ringing or undesirable
transients as they come out of shutdown. Note that
the transmitters are enabled only when the magnitude
of V- exceeds approximately -3.0V.
Mouse Drivability
The MAX3241E is designed to power serial mice while
operating from low-voltage power supplies. It has
been tested with leading mouse brands from manufacturers
such as Microsoft and Logitech. The
MAX3241E successfully drove all serial mice tested
and met their current and voltage requirements.
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
______________________________________________________________________________________ 15
Figure 6a shows the transmitter output voltages under
increasing load current at +3.0V. Figure 6b shows a
typical mouse connection using the MAX3241E.
High Data Rates
The MAX3222E/MAX3232E/MAX3237E/MAX3241E/
MAX3246E maintain the RS-232 ±5V minimum transmitter
output voltage even at high data rates. Figure 7
shows a transmitter loopback test circuit. Figure 8
shows a loopback test result at 120kbps, and Figure 9
shows the same test at 250kbps. For Figure 8, all transmitters
were driven simultaneously at 120kbps into RS-
232 loads in parallel with 1000pF. For Figure 9, a single
transmitter was driven at 250kbps, and all transmitters
were loaded with an RS-232 receiver in parallel with
1000pF.
The MAX3237E maintains the RS-232 ±5.0V minimum
transmitter output voltage at data rates up to 1Mbps.
Figure 10 shows a loopback test result at 1Mbps with
MBAUD = VCC. For Figure 10, all transmitters were
loaded with an RS-232 receiver in parallel with 250pF.
Interconnection with 3V and 5V Logic
The MAX3222E/MAX3232E/MAX3237E/MAX3241E/
MAX3246E can directly interface with various 5V logic
families, including ACT and HCT CMOS. See Table 3
for more information on possible combinations of interconnections.
UCSP Reliability
The UCSP represents a unique packaging form factor
that may not perform equally to a packaged product
through traditional mechanical reliability tests. UCSP
reliability is integrally linked to the user’s assembly
methods, circuit board material, and usage environment.
The user should closely review these areas when
considering use of a UCSP package. Performance
through Operating Life Test and Moisture Resistance
remains uncompromised as the wafer-fabrication
process primarily determines it.
Mechanical stress performance is a greater consideration
for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be considered.
Table 4 shows the testing done to characterize
the UCSP reliability performance. In conclusion, the
UCSP is capable of performing reliably through environmental
stresses as indicated by the results in the
table. Additional usage data and recommendations are
detailed in the UCSP application note, which can be
found on Maxim’s website at www.maxim-ic.com.
Table 4. Reliability Test Data
TEST CONDITIONS DURATION
FAILURES PER
SAMPLE SIZE
Temperature Cycle
TA = -35°C to +85°C,
TA = -40°C to +100°C
150 cycles,
900 cycles
0/10,
0/200
Operating Life TA = +70°C 240 hours 0/10
Moisture Resistance TA = +20°C to +60°C, 90% RH 240 hours 0/10
Low-Temperature Storage TA = -20°C 240 hours 0/10
Low-Temperature Operational TA = -10°C 24 hours 0/10
Solderability 8-hour steam age — 0/15
ESD ±15kV, Human Body Model — 0/5
High-Temperature Operating
Life
TJ = +150°C 168 hours 0/45
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
16 ______________________________________________________________________________________
__________________________________________________________Pin Configurations
20
19
18
17
16
15
14
13
1
2
3
8
12
10 11
4
5
6
7
SHDN
VCC
GND
C1- T1OUT
V+
C1+
EN
R1IN
R1OUT
T1IN
T2IN
T2OUT
VC2-
C2+
R2IN 9
R2OUT
TSSOP/SSOP
N.C.
N.C.
MAX3222E
20
19
18
17
16
15
14
13
1
2
3
8
12
10 11
4
5
6
7
N.C.
VCC
GND
C1- T1OUT
V+
C1+
N.C.
R1IN
R1OUT
T2IN
R2OUT
T2OUT
VC2-
C2+
R2IN 9
N.C.
TSSOP
T1IN
N.C.
MAX3232E
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VCC
GND
T1OUT
C2+ R1IN
C1-
V+
C1+
MAX3232E
R1OUT
T1IN
T2IN
R2IN R2OUT
T2OUT
VC2-
SO/DIP/SSOP/TSSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C1+
V+
VCC
GND
C1-
EN
R5OUT
SHDN
R1OUTB
R2OUTB
R1OUT
R2OUT
R3OUT
R4OUT
T1IN
T2IN
T3IN
T3OUT
T2OUT
T1OUT
R5IN
R4IN
R3IN
R2IN
R1IN
VC2-
C2+
SSOP/SO/TSSOP QFN
MAX3241E
TOP VIEW
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C1+
V+
VCC
C1-
T1IN
T2IN
MBAUD
T3IN
R1OUT
R2OUT
T4IN
R3OUT
T5IN
R1OUTB
SHDN
EN
T5OUT
R3IN
T4OUT
R2IN
R1IN
T3OUT
T2OUT
T1OUT
VC2-
GND
C2+
SSOP
MAX3237E
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
SHDN
VCC
GND
C1- T1OUT
V+
C1+
EN
R1IN
R1OUT
T1IN
T2OUT T2IN
VC2-
C2+
R2IN 9 10 R2OUT
SO/DIP
MAX3222E
32
31
30
29
28
27
26
N.C.
VC2-
C2+
C1+
V+
VCC
25 N.C.
9
10
11
12
13
14
15
N.C.
T3IN
T2IN
T1IN
R5OUT
R4OUT
R3OUT
N.C. 16
17
18
19
20
21
22
23
R2OUT
R1OUT
R2OUTB
R1OUTB
SHDN
EN
C1-
8
7
6
5
4
3
2
T3OUT
T2OUT
T1OUT
R5IN
R4IN
R3IN
R2IN
MAX3241E
R1IN 1 24 GND
TOP VIEW
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
______________________________________________________________________________________ 17
Pin Configurations (continued)
19
20
18
17
7
6
8
C1-
C2-
V-
9
C1+
R1IN
N.C.
T1IN
T1OUT
1 2
SHDN
4 5
15 14 12 11
EN
V+
EXPOSED
PADDLE
EXPOSED
PADDLE
N.C.
R2OUT
R2IN
T2OUT
MAX3222E
C2+ R1OUT
3
13
VCC
GND 16 10 T2IN
TQFN
TOP VIEW
15
16
14
13
6
5
7
C2+
V-
8
C1-
R1IN
T1IN
T1OUT
1 2
VCC
4
12 11 9
V+
C1+
T2IN
R2OUT
R2IN
T2OUT
MAX3232E
C2- R1OUT
3
10
GND
TQFN
TOP VIEW
UCSP
F2 F3 F4 F5 F6
E3 E6
D6
C6
B3 B6
A2 A3 A4 A5 A6
TOP VIEW
(BUMPS ON BOTTOM)
T1OUT
VCC C1+ C1- GND
R3IN
R4OUT R5OUT R1IN R2IN
R4IN
R5IN
T3OUT
T2OUT
B2: SHDN
C2: R1OUT
D2: T3IN
E2: T2IN
B3: EN
E3: T1IN
BUMPS B4, B5, C3, C4,
C5, D3, D4, D5, E4, AND
E5 NOT POPULATED
E2
D2
C2
B2
F1
E1
D1
C1
B1
A1
V+
R3OUT
R2OUT
VC2-
C2+
MAX3246E
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
18 ______________________________________________________________________________________
__________________________________________________Typical Operating Circuits
10 R2OUT
1
13 R1OUT
R2IN 9
18
GND
16
RS-232
OUTPUTS
TTL/CMOS
INPUTS
11 T2IN
12 T1IN
C2-
6
5 C2+
4 C1-
2 C1+
R1IN 14
T2OUT 8
T1OUT 15
V-
7
V+
VCC 3
17
C1
0.1μF
C2
0.1μF
CBYPASS
+3.3V
RS-232
INPUTS
TTL/CMOS
OUTPUTS
5kΩ
EN 5kΩ
SHDN
C3*
0.1μF
C4
0.1μF
NOTE: PIN NUMBERS REFER TO SO/DIP PACKAGES.
MAX3222E PINOUT REFERS TO SO/DIP PACKAGES.
MAX3232E PINOUT REFERS TO TSSOP/SSOP/SO/DIP/ PACKAGES
*C3 CAN BE RETURNED TO EITHER VCC OR GROUND.
9 R2OUT
12 R1OUT
R2IN 8
GND
15
RS-232
OUTPUTS
TTL/CMOS
INPUTS
10 T2IN
11 T1IN
C2-
5
4 C2+
3 C1-
1 C1+
R1IN 13
T2OUT 7
T1OUT 14
V-
6
V+
VCC 2
C4
0.1μF
16
C1
0.1μF
C2
0.1μF
CBYPASS
+3.3V
RS-232
INPUTS
TTL/CMOS
OUTPUTS
C3*
0.1μF
5kΩ
5kΩ
SEE TABLE 2 FOR CAPACITOR SELECTION.
MAX3222E MAX3232E
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
______________________________________________________________________________________ 19
_____________________________________Typical Operating Circuits (continued)
23 EN
15 R5OUT
16 R4OUT
17 R3OUT
18 R2OUT
19 R1OUT
20 R2OUTB
21 R1OUTB
TTL/CMOS
OUTPUTS
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
R5IN 8
*C3 CAN BE RETURNED TO EITHER VCC OR GROUND.
R4IN 7
R3IN 6
R2IN 5
R1IN 4
RS-232
INPUTS
SHDN 22
GND
25
RS-232
OUTPUTS
TTL/CMOS
INPUTS
12 T3IN
13 T2IN
14 T1IN
C2-
2
1 C2+
24 C1-
28 C1+
T3OUT 11
T2OUT 10
T1OUT 9
V-
3
V+
VCC 27
C4
0.1μF
C3*
0.1μF
C1
0.1μF
C2
0.1μF
26
+3.3V
CBYPASS
MAX3241E
13 EN
18 R3OUT
20 R2OUT
21 R1OUT
16 R1OUTB
LOGIC
OUTPUTS
5kΩ
5kΩ
5kΩ
R3IN 11
R2IN 9
R1IN 8
RS-232
INPUTS
GND
2
RS-232
OUTPUTS
LOGIC
INPUTS
22 T3IN
23 T2IN
24 T1IN
C2-
3
1 C2+
25 C1-
28 C1+
T3OUT 7
T2OUT 6
T1OUT 5
T1
T2
T3
R1
R2
R3
V-
4
V+
VCC 27
0.1μF
0.1μF
0.1μF
0.1μF
26
MBAUD 15
17 T5IN
19 T4IN
T5OUT 12
T4OUT 10
SHDN
14
T4
T5
C3*
CBYPASS
+3.3V
MAX3237E
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
20 ______________________________________________________________________________________
_____________________________________Typical Operating Circuits (continued)
B3 EN
A3 R5OUT
A2 R4OUT
A1 R3OUT
B1 R2OUT
C2 R1OUT
TTL/CMOS
OUTPUTS
5kΩ
5kΩ
5kΩ
5kΩ
5kΩ
R5IN C6
*C3 CAN BE RETURNED TO EITHER VCC OR GROUND.
R4IN B6
R3IN A6
R2IN A5
R1IN A4
RS-232
INPUTS
SHDN B2
GND
F5
RS-232
OUTPUTS
TTL/CMOS
INPUTS
D2 T3IN
E2 T2IN
E3 T1IN
C2-
D1
E1 C2+
F4 C1-
F3 C1+
T3OUT D6
T2OUT E6
T1OUT F6
VC1
V+
VCC F1
C4
0.1μF
C3*
0.1μF
C1
0.1μF
C2
0.1μF
F2
+3.3V
CBYPASS
MAX3246E
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
______________________________________________________________________________________ 21
Selector Guide
PART
NO. OF
DRIVERS/
RECEIVERS
LOW-POWER
SHUTDOWN
GUARANTEED
DATA RATE
(bps)
MAX3222E 2/2 ✔ 250k
MAX3232E 2/2 — 250k
MAX3237E
(Normal)
5/3 ✔ 250k
MAX3237E
(MegaBaud)
5/3 ✔ 1M
MAX3241E 3/5 ✔ 250k
MAX3246E 3/5 ✔ 250k
___________________Chip Information
TRANSISTOR COUNT:
MAX3222E/MAX3232E: 1129
MAX3237E: 2110
MAX3241E: 1335
MAX3246E: 842
PROCESS: BICMOS
Ordering Information (continued)
PART TEMP RANGE
PINPACKAGE
PKG
CODE
MAX3232ECTE 0°C to +70°C
16 Thin QFNEP**
(5mm x
5mm)
T1655-2
MAX3232ECUE 0°C to +70°C 16 TSSOP —
MAX3232ECUP 0°C to +70°C 20 TSSOP —
MAX3232EEAE -40°C to +85°C 16 SSOP —
MAX3232EEWE -40°C to +85°C 16 Wide SO —
MAX3232EEPE -40°C to +85°C 16 Plastic DIP —
MAX3232EETE -40°C to +85°C
16 Thin QFNEP**
(5mm x
5mm)
T1655-2
MAX3232EEUE -40°C to +85°C 16 TSSOP —
MAX3232EEUP -40°C to +85°C 20 TSSOP —
MAX3237ECAI 0°C to +70°C 28 SSOP —
MAX3237EEAI -40°C to +85°C 28 SSOP —
MAX3241ECAI 0°C to +70°C 28 SSOP —
MAX3241ECWI 0°C to +70°C 28 Wide SO —
MAX3241ECUI 0°C to +70°C 28 TSSOP —
MAX3241ECTJ 0°C to +70°C 32 Thin QFN —
MAX3241EEAI -40°C to +85°C 28 SSOP —
MAX3241EEWI -40°C to +85°C 28 Wide SO —
MAX3241EEUI -40°C to +85°C 28 TSSOP —
MAX3246ECBX-T 0°C to +70°C 6 x 6 UCSP† —
MAX3246EEBX-T -40°C to +85°C 6 x 6 UCSP† —
†Requires solder temperature profile described in the Absolute
Maximum Ratings section. UCSP Reliability is integrally linked
to the user’s assembly methods, circuit board material, and
environment. Refer to the UCSP Reliability Notice in the UCSP
Reliability section of this datasheet for more information.
**EP = Exposed paddle.
24L QFN THIN.EPS
PACKAGE OUTLINE,
21-0139 2
1 E
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
PACKAGE OUTLINE,
21-0139 2
2 E
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
22 ______________________________________________________________________________________
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
______________________________________________________________________________________ 23
TSSOP4.40mm.EPS
PACKAGE OUTLINE, TSSOP 4.40mm BODY
21-0066 1
1
I
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
24 ______________________________________________________________________________________
36L,UCSP.EPS
21-0082 1
1
K
PACKAGE OUTLINE, 6x6 UCSP
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
______________________________________________________________________________________ 25
SOICW.EPS
PACKAGE OUTLINE, .300" SOIC
1
1
21-0042 B
APPROVAL DOCUMENT CONTROL NO. REV.
PROPRIETARY INFORMATION
TITLE:
TOP VIEW
FRONT VIEW
MAX
0.012
0.104
0.019
0.299
0.013
INCHES
0.291
0.009
E
C
DIM
0.014
0.004
B
A1
MIN
A 0.093
0.23
7.40 7.60
0.32
MILLIMETERS
0.10
0.35
2.35
MIN
0.49
0.30
MAX
2.65
L 0.016 0.050 0.40 1.27
D 0.496 0.512
D
DIM MIN
D
INCHES
MAX
12.60 13.00
MILLIMETERS
MIN MAX
20 AC
0.447 0.463 11.35 11.75 18 AB
0.398 0.413 10.10 10.50 16 AA
N MS013
SIDE VIEW
H 0.394 0.419 10.00 10.65
e 0.050 1.27
D 0.598 0.614 15.20 15.60 24 AD
D 0.697 0.713 17.70 18.10 28 AE
E H
N
D
e B A1
A
0∞-8∞
C
L
1
VARIATIONS:
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
SSOP.EPS
PACKAGE OUTLINE, SSOP, 5.3 MM
1
1
21-0056 C
APPROVAL DOCUMENT CONTROL NO. REV.
PROPRIETARY INFORMATION
TITLE:
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
H 7.90
L
0∞
0.301
0.025
8∞
0.311
0.037
0∞
7.65
0.63
8∞
0.95
MAX
5.38
MILLIMETERS
B
C
D
E
e
A1
DIM
A
SEE VARIATIONS
0.0256 BSC
0.010
0.004
0.205
0.002
0.015
0.008
0.212
0.008
INCHES
MIN MAX
0.078
0.65 BSC
0.25
0.09
5.20
0.05
0.38
0.20
0.21
MIN
1.73 1.99
MILLIMETERS
6.07
6.07
10.07
8.07
7.07
INCHES
D
D
D
D
D
0.239
0.239
0.397
0.317
0.278
MIN
0.249
0.249
0.407
0.328
0.289
MAX MIN
6.33
6.33
10.33
8.33
7.33
14L
16L
28L
24L
20L
MAX N
A
D
e A1 L
C
E H
N
2 1
B
0.068
MAX3222E/MAX3232E/MAX3237E/MAX3241E†/MAX3246E
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PDIPN.EPS
Revision History
Pages changed at Rev 10: 1–4, 9, 11, 21, 22, 26
PCB Keyswitches 4 - 23
4
RF
RF short-travel keyswitches
General data
RF 15 (15 x 15 mm) and RF 19 (19 x 19 mm) with distinct key click, for use under an overlay or with RK 90 keycaps. Can be
fully illuminated.
Content
RF 15 short-travel keyswitch 4 - 26
RF 15 short-travel keyswitch, non-illuminated 4 - 28
RF 15 short-travel keyswitch, fully illuminated with 2 LEDs 4 - 29
RF 15 short-travel keyswitch, 1 LED spot-illumination 4 - 30
RF 15 N short-travel keyswitch 4 - 32
RF 15 N short-travel keyswitch, non-illuminated 4 - 35
RF 15 R short-travel keyswitch 4 - 36
RF 15 R low short-travel keyswitch, non-illuminated 4 - 39
RF 15 R high short-travel keyswitch, non-illuminated 4 - 39
RF 15 R low short-travel keyswitch, 1 LED spot-illumination 4 - 40
RF 15 R high short-travel keyswitch, 1 LED spot-illumination 4 - 41
RF 15 H short-travel keyswitch 4 - 42
RF 15 H short-travel keyswitch, non-illuminated 4 - 44
RF 15 H short-travel keyswitch, fully illuminated 4 - 45
RF 15 signal indicator 4 - 46
RF 15 signal indicator, fully illuminated, 1 LED 4 - 48
RF 19 short-travel keyswitch 4 - 50
RF 19 short-travel keyswitch, non-illuminated 4 - 53
RF 19 short-travel keyswitch, fully illuminated with 2 LEDs 4 - 54
RF 19 short-travel keyswitch, 1 LED spot-illumination 4 - 55
RF 19 short-travel keyswitch, 1 NC + 1 NO 4 - 56
RF 19 short-travel keyswitch, non-illuminated 4 - 58
RF 19 H short-travel keyswitch 4 - 60
RF 19 H keyswitch, non-illuminated 4 - 62
RF 19 H short-travel keyswitch, fully illuminated 4 - 63
RF 19 signal indicator 4 - 64
RF 19 signal indicator, 1/2 x 1-module 4 - 66
RF 19 signal indicator, 1/2 x 2-module 4 - 66
RF 19 signal indicator, 1 x 1-module 4 - 67
RF 19 signal indicator, 1 x 2-module 4 - 67
4 - 24 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF special accessories 4 - 68
Extension plunger for RF 15 N, round head 4 - 68
Extension plunger for RF 15 N, round head, with recess for LED 4 - 69
Keycap for RF 15, snap-on, for overall height 12.5 mm 4 - 69
Spacers, round 4 - 70
Spacers, triangular 4 - 71
LED spacer for RF 15 N 4 - 72
PCB Keyswitches 4 - 25
4
RF
RF short-travel keyswitches
Specifications LED
3 mm LED
2 mm LED
Max. forward current lF:
Current reduction from: T0 = 50 °C:
Wavelength typ:
Forward voltage UF/lF typ:
Reverse voltage UR/lF typ:
Ambient temperature, operating:
(valid for 25 °C)
30 mA
approx 0.5 mA/°C
635 nm
2 V/10 mA
5 V/100 μA min.
- 20 °C . . . + 80 °C
Red LED
30 mA
approx 0.5 mA/°C
565 nm
2 V/10 mA
5 V/100 μA min.
- 20 °C . . . + 80 °C
Green LED
20 mA
approx 0.2 mA/°C
586 nm
2 V/10 mA
5 V/100 μA min.
- 20 °C . . . + 80 °C
Yellow LED
Max. forward current lF:
Current reduction from: T0 = 50 °C:
Wavelength typ:
Forward voltage UF/lF typ:
Reverse voltage UR/lF typ:
Ambient temperature, operating:
20 mA
approx 0.6 mA/°C
470 nm
2.7 V/10 mA
5V/100 μA min.
- 20 °C . . . + 80 °C
Blue LED
25 mA
--
3.6 V/20 mA
-
- 20 °C . . . + 80 °C
White LED
30 mA
-
510-545 nm
3.5 V/20 mA
-
-30 °C . . . + 100 °C
Green LED superbright
Max. forward current lF:
Current reduction from: T0 = 50 °C:
Light current fV/lF typ:
Wavelength typ:
Forward voltage UF/lF typ:
Reverse voltage UR/lF typ:
Ambient temperature, operating:
(valid for 25 °C)
30 mA
0.5 mA/°C
-
637 nm
1.8 V/20 mA
5 V/100 μA min.
- 55 °C . . . + 100 °C
Red LED
30 mA
0.5 mA/°C
-
569 nm
2.1 V/10 mA
5 V/100 μA min.
- 40 °C . . . + 100 °C
Green LED
50 mA
0.8 mA/°C
250 mIm/20 mA
590 nm
1.9 V/20 mA
5 V/100 μA min.
-40 °C . . . + 100 °C
Yellow LED
Max. forward current lF:
Current reduction from: T0 = 50 °C:
Light current fV/lF typ:
Wavelength typ:
Forward voltage UF/lF typ:
Reverse voltage UR/lF typ:
Ambient temperature, operating:
30 mA
-
-
464-485 nm
3.6 V/20 mA
- 20 °C . . . + 80 °C
Blue LED
30 mA
approx 0.6 mA/°C
-
635/565 nm
2 V/10 mA
-
- 20 °C . . . + 80 °C
Multi-colour LED
Rated power
of series:
PV = IF
2 x RV
Calculating the
series resistor:
RV =
Example for 5 Volt:
RV = = 150 Ω (= standard value)
UB - UF
IF
5V - 2.0 V
0.02 A
4 - 26 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 15 short-travel keyswitch
General data
Low-profile keyboards with RF 15 components should be designed with a 19.05 mm grid. With this grid, frame webs remain
free between the individual keys. The overlay can be glued onto these frame webs; we recommend area embossing
over the keys for the overlays.
Technical data
General information
Colour of lens see order block
Recommended key grid 19.05 mm
Dimensions
Length 15 mm
Width 15 mm
Overall height 9.7 mm
Mechanical design
Mounting soldering into PCB
Terminals contacts tin-plated, fix
contact Ag plated
Contact system snap-action contact
Contact arrangement 1 NO
Contact materials Au/Ag
Illumination spot-/fully illuminated
LED colour see order block
LED type see order block
Mechanical characteristics
Operating force max. 2 ... 3 N
Operating travel 0.5 mm
Switching travel 0.5 mm
Robustness min. with through-plated PCB
100 N
Electrical characteristics
Rated voltage min. Au: 0.02 V, Ag: 3 V
Rated voltage max. Au: 42 V, Ag: 50 V
Rated current min. Au: 0,01 mA, Ag: 0,1 mA
Rated current max. Au: 100 mA, Ag: 250 mA
Rated power max. (ohmic
load) Au: 2 W, Ag: 12.5 W
Contact resistance when
new max. 100 mΩ
Contact resistance acc.
to life max. 3 Ω
Insulation resistance 109 Ω
ESD strength (underneath
overlay) 15 kV
Bouncing time max. 5 ms
Other specifications
Ambient temp. operating
min. -25 °C
Ambient temp. operating
max. +70 °C
Storage temperature min. -40 °C
Storage temperature max.
(product) +80 °C
Storage temperature max.
(in tube) +50 °C
Resistance to constant
environment according to
IEC 600 68-2-3 and 2-30
Resistance at variable
environment according to
IEC 600 68-2-14 and 2-33
Operating life min. 1,000,000
Soldering time max. 2,5 sec.
Soldering temperature
max. 250 °C
Flammability of materials UL 94 HB
PCB Keyswitches 4 - 27
4
RF
RF short-travel keyswitches
F 1 = Max. operating force
F 2 = Force at contact
F 2 is max. 55% of F 1
View on component side, all hole diameters 1,1 +/- 0,1 mm
Operation characteristic limits RF
Keyswitch,
non-illuminated
Keyswitch,
fully illuminated
Keyswitch,
spot-illuminated
Force/Travel Diagram – Keyswitch RF 15 Circuit Diagram – Keyswitch RF 15
Dimensional Drawing RF 15
Hole Pattern RF 15 Hole Pattern – Front Panel
Stock items are marked
by bold printed order numbers.
4 - 28 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 15 short-travel keyswitch, non-illuminated
Contact materials Illumination Colour of lens LED colour LED type Order no.
Ag not illuminated transparent 3.14.100.006/0000
Au not illuminated transparent 3.14.100.001/0000
Technical data see page 4 - 26
Accessories:
Keycap for RF 15, snap-on, for overall height 12.5 mm: 5.46.654.059/0227
For keycaps, refer to chapter accessories and system RK 90.
If exchangeable legends are required, or if an overall height of 12.5 mm is required, a keycap can be mounted on the non-illuminated
keys. The keycap legend is visible through a window in the overlay. You can change the legend by replacing the keycap.
Stock items are marked
by bold printed order numbers.
PCB Keyswitches 4 - 29
4
RF
RF short-travel keyswitches
RF 15 short-travel keyswitch, fully illuminated with 2 LEDs
Illuminated area
10.8 x 10.8 mm
Housing
Actuator
Lens
Pict.: red
Contact materials Illumination Colour of lens LED colour LED type Order no.
Ag fully illuminated
2 LEDs
red red 2 mm 3.14.200.021/0000
Ag fully illuminated
2 LEDs
green green 2 mm 3.14.200.022/0000
Ag fully illuminated
2 LEDs
yellow yellow 2 mm 3.14.200.023/0000
Ag fully illuminated
2 LEDs
orange yellow 2 mm 3.14.200.024/0000
Ag fully illuminated
2 LEDs
blue blue 2 mm 3.14.200.025/0000
Au fully illuminated
2 LEDs
green green 2 mm 3.14.200.012/0000
Au fully illuminated
2 LEDs
yellow yellow 2 mm 3.14.200.013/0000
Au fully illuminated
2 LEDs
orange yellow 2 mm 3.14.200.014/0000
Au fully illuminated
2 LEDs
blue blue 2 mm 3.14.200.015/0000
Technical data see page 4 - 26
For keycaps, refer to RK 90 system design.
Technical data of LED see seperate page at the beginning of this chapter.
Stock items are marked
by bold printed order numbers.
4 - 30 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 15 short-travel keyswitch, 1 LED spot-illumination
Pict.: red
Contact materials Illumination Colour of lens LED colour LED type Order no.
Ag spot illumination
1 LED
opaque white blue 3 mm 3.14.100.040/0000
Ag spot illumination
1 LED
transparent red 3 mm 3.14.100.041/0000
Ag spot illumination
1 LED
transparent green 3 mm 3.14.100.042/0000
Ag spot illumination
1 LED
transparent yellow 3 mm 3.14.100.043/0000
Au spot illumination
1 LED
opaque white blue 3 mm 3.14.100.030/0000
Au spot illumination
1 LED
transparent red 3 mm 3.14.100.031/0000
Au spot illumination
1 LED
transparent green 3 mm 3.14.100.032/0000
Au spot illumination
1 LED
transparent yellow 3 mm 3.14.100.033/0000
Technical data see page 4 - 26
Double-spot LED illumination available on request
Technical data of LED see seperate page at the beginning of this chapter.
4 - 32 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 15 N short-travel keyswitch
General data
The RF 15N keyswitch provides a minimum overall height of 6.2 mm. The overall height can be varied by extension plungers
which are inserted into the cross-like notches on the actuator tops.
LEDs can only be arranged separately next to the keyswitches up to an overall height of 10 mm (i.e. without plunger or
with small plunger).
Keyswitches with overall heights of 12 mm or more can be provided with a maximum of 2 LEDs which are inserted into
the recesses of the keyswitch housing. LEDs of keyswitches with overall heights of 12.5 mm or more should be placed onto
LED spacers in order to obtain satisfactory illumination.
Technical data
General information
Colour of lens see order block
Recommended key grid 19.05 mm
Dimensions
Length 15 mm
Width 15 mm
Overall height 6.2 mm
Mechanical design
Mounting soldering into PCB
Terminals contacts tin-plated, fix
contact Ag plated
Contact system snap-action contact
Contact arrangement 1 NO
Contact materials Au/Ag
Illumination external 3 mm LED
possible if height ‹ 12 mm
Mechanical characteristics
Operating force max. 2 ... 3 N
Operating travel 0.5 mm
Switching travel 0.5 mm
Robustness min. with through-plated PCB
100 N
Electrical characteristics
Rated voltage min. Au: 0.02 V, Ag: 3 V
Rated voltage max. Au: 42 V, Ag: 50 V
Rated current min. Au: 0,01 mA, Ag: 0,1 mA
Rated current max. Au: 100 mA, Ag: 250 mA
Rated power max.
(ohmic load) Au: 2 W, Ag: 12.5 W
Contact resistance when
new max. 100 mΩ
Contact resistance acc.
to life max. 3 Ω
Insulation resistance 109 Ω
ESD strength (underneath
overlay) 15 kV
Bouncing time max. 5 ms
Other specifications
Ambient temp. operating
min. -25 °C
Ambient temp. operating
max. +70 °C
Storage temperature min. -40 °C
Storage temperature max.
(product) +80 °C
Storage temperature max.
(in tube) +50 °C
Resistance to constant
environment according to
IEC 600 68-2-3 and 2-30
Resistance at variable
environment according to
IEC 600 68-2-14 and 2-33
Operating life min. 1,000,000
Soldering time max. 2,5 sec.
Soldering temperature
max. 250 °C
Flammability of materials UL 94 HB
PCB Keyswitches 4 - 33
4
RF
RF short-travel keyswitches
F 1 = Max. operating force
F 2 = Force at contact
F 2 is max. 55% of F 1
Operation characteristic limits RF
Keyswitch,
non illuminated
Keyswitch,
spot-illuminated
Force/Travel Diagram – Keyswitch RF 15 N Circuit Diagram – Keyswitch RF 15 N
Dimensional Drawings RF 15 N
4 - 34 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 15 N without plunger RF 15 N with plunger ø 10 mm, non-illuminated
RF 15 N with plunger ø 10 mm, illuminated RF 15 N with plunger ø 15 mm, illuminated
View on component side
All hole diameters 1,1 +/- 0,1 mm
PCB layout Keyswitch 1/400” grid
Hole Pattern RF 15 N
Hole Patterns – Front Panel RF 15 N
Stock items are marked
by bold printed order numbers.
PCB Keyswitches 4 - 35
4
RF
Description Photo Order no. Page
Accessories RF 15 N short-travel keyswitch
LED yellow, 3mm 1.90.690.103/0000 5 - 20
LED spacer for RF 15 N, Ø 5 mm, spacing length 2.2 mm,
light grey, for use with overall height of 12.5 mm
5.30.109.010/0756
Extension plunger for RF 15 N, Ø 10 mm, overall height
22.5 mm
5.46.011.028/0710
Extension plunger for RF 15 N, Ø 15 mm, overall height
22.5 mm
5.46.017.028/0710
RF 15 N short-travel keyswitch, non-illuminated
Contact materials Illumination Recommended key grid Overall height Order no.
Au external 3 mm LED possible if
height < 12 mm
19.05 mm 6.2 mm 3.14.100.601/0000
Ag external 3 mm LED possible if
height < 12 mm
19.05 mm 6.2 mm 3.14.100.606/0000
Technical data see page 4 - 32
For keycaps, refer to RK 90 system design.
Double-spot LED illumination available on request.
4 - 36 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 15 R short-travel keyswitch
with 3 mm LED, green
Pict.: with 2 mm LED, red
General data
The round actuator of the RF 15 R keyswitch requires round front panel cut-outs. These make it possible to use a narrow
keyboard grid of only 15.24 mm with sufficiently large frame webs between the individual keys. We recommend area
embossing over the actuators for the overlay.
Technical data
General information
Recommended key grid 15.24 mm
Dimensions
Length 15 mm
Width 15 mm
Overall height 9,7/12,5 mm
Mechanical design
Mounting soldering into PCB
Terminals contacts tin-plated, fix
contact Ag plated
Contact system snap-action contact
Contact arrangement 1 NO
Contact materials Au/Ag
Illumination spot illumination
LED colour see order block
LED type see order block
Mechanical characteristics
Operating force max. 2 ... 3 N
Operating travel 0.5 mm
Switching travel 0.5 mm
Robustness min. with through-plated PCB
100 N
Electrical characteristics
Rated voltage min. Au: 0.02 V, Ag: 3 V
Rated voltage max. Au: 42 V, Ag: 50 V
Rated current min. Au: 0,01 mA, Ag: 0,1 mA
Rated current max. Au: 100 mA, Ag: 250 mA
Rated power max.
(ohmic load) Au: 2 W, Ag: 12.5 W
Contact resistance when
new max. 100 mΩ
Contact resistance acc.
to life max. 3 Ω
Insulation resistance 109 Ω
ESD strength (underneath
overlay) 15 kV
Bouncing time max. 5 ms
Other specifications
Ambient temp. operating
min. -25 °C
Ambient temp. operating
max. +70 °C
Storage temperature min. -40 °C
Storage temperature max.
(product) +80 °C
Storage temperature max.
(in tube) +50 °C
Resistance to constant
environment according to
IEC 600 68-2-3 and 2-30
Resistance at variable
environment according to
IEC 600 68-2-14 and 2-33
Operating life min. 1,000,000
Soldering time max. 2,5 sec.
Soldering temperature
max. 250 °C
Flammability of materials UL 94 HB
PCB Keyswitches 4 - 37
4
RF
RF short-travel keyswitches
F 1 = Max. operating force
F 2 = Force at contact
F 2 is max. 55% of F 1
View on component side
All hole diameters 1,1 +/- 0,1 mm
PCB layout Keyswitch 1/400” grid
Operation characteristic limits RF
Keyswitch,
non-illuminated
Keyswitch,
spot-illuminated
Force/Travel Diagram – Keyswitch RF 15 R Circuit Diagram – Keyswitch RF 15 R
Dimensional Drawing RF 15 R
Hole Pattern RF 15 R
4 - 38 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 15 R, non-illuminated RF 15 R, illuminated
Hole Pattern – Front Panel RF 15 R
Stock items are marked
by bold printed order numbers.
PCB Keyswitches 4 - 39
4
RF
RF short-travel keyswitches
RF 15 R low short-travel keyswitch, non-illuminated
Contact materials Overall height Illumination LED type LED colour Order no.
Au 9.7 mm not illuminated 3.14.100.501/0000
Ag 9.7 mm not illuminated 3.14.100.506/0000
Technical data see page 4 - 36
RF 15 R high short-travel keyswitch, non-illuminated
Contact materials Overall height Illumination LED type LED colour Order no.
Au 12.5 mm not illuminated 3.14.100.801/0000
Ag 12.5 mm not illuminated 3.14.100.806/0000
Technical data see page 4 - 36
Stock items are marked
by bold printed order numbers.
4 - 40 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 15 R low short-travel keyswitch, 1 LED spot-illumination
Pict.: with 2 mm LED, red
Contact materials Overall height Illumination LED type LED colour Order no.
Au 9.7 mm spot illumination
1 LED
2 mm red 3.14.100.531/0000
Au 9.7 mm spot illumination
1 LED
2 mm green 3.14.100.532/0000
Au 9.7 mm spot illumination
1 LED
2 mm yellow 3.14.100.533/0000
Ag 9.7 mm spot illumination
1 LED
2 mm red 3.14.100.541/0000
Ag 9.7 mm spot illumination
1 LED
2 mm green 3.14.100.542/0000
Ag 9.7 mm spot illumination
1 LED
2 mm yellow 3.14.100.543/0000
Technical data see page 4 - 36
Versions with 2 LEDs available on request.
Technical data of LED see seperate page at the beginning of this chapter.
Stock items are marked
by bold printed order numbers.
PCB Keyswitches 4 - 41
4
RF
RF short-travel keyswitches
RF 15 R high short-travel keyswitch, 1 LED spot-illumination
Pict.: with 3 mm LED, green
Contact materials Overall height Illumination LED type LED colour Order no.
Au 12.5 mm spot illumination
1 LED
3 mm blue 3.14.100.830/0000
Au 12.5 mm spot illumination
1 LED
3 mm red 3.14.100.831/0000
Au 12.5 mm spot illumination
1 LED
3 mm green 3.14.100.832/0000
Au 12.5 mm spot illumination
1 LED
3 mm yellow 3.14.100.833/0000
Ag 12.5 mm spot illumination
1 LED
3 mm blue 3.14.100.840/0000
Ag 12.5 mm spot illumination
1 LED
3 mm red 3.14.100.841/0000
Ag 12.5 mm spot illumination
1 LED
3 mm green 3.14.100.842/0000
Ag 12.5 mm spot illumination
1 LED
3 mm yellow 3.14.100.843/0000
Technical data see page 4 - 36
Versions with 2 LEDs available on request.
Technical data of LED see seperate page at the beginning of the chapter.
4 - 42 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 15 H short-travel keyswitch
yellow
General data
Application notes:
The RF 15 H key has an overall height of 12.5 mm and can be fully illuminated. When designing membrane keyboards,
we recommend using a key grid of at least 19.05 mm and a 0.13 mm overlay with area embossing over the keys.
You can use the O-ring (accessory) to block the key and use it as an indicator field or blank spaceholder.
Technical data
General information
Colour of lens see order block
Recommended key grid 20 mm
Dimensions
Length 15 mm
Width 15 mm
Overall height 12.5 mm
Mechanical design
Mounting soldering into PCB
Terminals see order block
Contact system snap-action contact
Contact arrangement 1 NO
Contact materials Au/Ag
Illumination not illuminated / fully illuminated
LED colour see order block
LED type see order block
Mechanical characteristics
Operating force max. 2 ... 3 N
Operating travel 0.5 mm
Switching travel 0.5 mm
Robustness min. with through-plated PCB
100 N
Electrical characteristics
Rated voltage min. Au: 0.02 V, Ag: 3 V
Rated voltage max. Au: 42 V, Ag: 50 V
Rated current min. Au: 0,01 mA, Ag: 0,1 mA
Rated current max. Au: 100 mA, Ag: 250 mA
Rated power max.
(ohmic load) Au: 2 W, Ag: 12.5 W
Contact resistance when
new max. 100 mΩ
Contact resistance acc.
to life max. 3 Ω
Insulation resistance 109 Ω
ESD strength (underneath
overlay) 15 kV
Bouncing time max. 5 ms
Other specifications
Ambient temp. operating
min. -25 °C
Ambient temp. operating
max. +70 °C
Storage temperature min. -40 °C
Storage temperature max.
(product) +80 °C
Storage temperature max.
(in tube) +50 °C
Resistance to constant
environment according to
IEC 600 68-2-3 and 2-30
Resistance at variable
environment according to
IEC 600 68-2-14 and 2-33
Operating life min. 1,000,000
Soldering time max. 2,5 sec.
Soldering temperature
max. 250 °C
Flammability of materials UL 94 HB
PCB Keyswitches 4 - 43
4
RF
RF short-travel keyswitches
F 1 = Max. operating force
F 2 = Force at contact
F 2 is max. 55% of F 1
No metal webs with 15.24 mm. View on component side.
All hole diameters 1,1 +/- 0,1 mm. PCB layout Keyswitch 1/400” grid.
Operation characteristic limits RF
Keyswitch,
non-illuminated
Keyswitch,
fully illuminated
Force/Travel Diagram – Keyswitch RF 15 H Circuit Diagram – Keyswitch RF 15 H
Dimensional Drawing
Hole Pattern Hole Pattern – Front Panel
Stock items are marked
by bold printed order numbers.
4 - 44 PCB Keyswitches
4
RF
RF short-travel keyswitches
Description Photo Order no. Page
Accessories RF 15 H short-travel keyswitch
O-ring, black, for blocking the operating stroke 5.30.120.009/0100 5 - 27
RF 15 H short-travel keyswitch, non-illuminated
overall height
housing
actuator
lens
illuminated area
Contact materials Illumination Colour of lens LED colour LED type Order no.
Au not illuminated white 3.14.100.702/0000
Ag not illuminated white 3.14.100.707/0000
Technical data see page 4 - 42
Stock items are marked
by bold printed order numbers.
PCB Keyswitches 4 - 45
4
RF
RF short-travel keyswitches
RF 15 H short-travel keyswitch, fully illuminated
overall height
housing
actuator
lens
illuminated area
Pict.: yellow
Contact materials Illumination Colour of lens LED colour LED type Order no.
Au fully illuminated
2 LEDs
red red 2 mm 3.14.200.731/0000
Au fully illuminated
2 LEDs
green green 2 mm 3.14.200.732/0000
Au fully illuminated
1 LED
green green super bright 3 mm 3.14.200.736/0000
Au fully illuminated
2 LEDs
yellow yellow 2 mm 3.14.200.733/0000
Au fully illuminated
1 LED
white white 3 mm 3.14.200.735/0000
Au fully illuminated
2 LEDs
orange yellow 2 mm 3.14.200.738/0000
Au fully illuminated
1 LED
blue blue 3 mm 3.14.200.739/0000
Au fully illuminated
2 LEDs
white multi colour 3 mm 3.14.100.734/0000
Ag fully illuminated
2 LEDs
red red 2 mm 3.14.200.741/0000
Ag fully illuminated
2 LEDs
green green 2 mm 3.14.200.742/0000
Ag fully illuminated
1 LED
green green super bright 3 mm 3.14.200.746/0000
Ag fully illuminated
2 LEDs
yellow yellow 2 mm 3.14.200.743/0000
Ag fully illuminated
1 LED
white white 3 mm 3.14.200.745/0000
Ag fully illuminated
2 LEDs
orange yellow 2 mm 3.14.200.748/0000
Ag fully illuminated
1 LED
blue blue 3 mm 3.14.200.749/0000
Ag fully illuminated
2 LEDs
white multi colour 3 mm 3.14.100.744/0000
Technical data see page 4 - 42
When using the keyswitches with multicolour LEDs the illumination colour can be varied from red to green by change of polarity. Due to
the frequency of the polarity-changes the colours red, green, yellow as well as all secondary colours from these are possible.
Technical data of LED see seperate page of the beginning of this chapter.
4 - 46 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 15 signal indicator
Pict.: green
Technical data
General information
Colour of lens see order block
Recommended key grid 19.05 mm
Dimensions
Length 15 mm
Width 15 mm
Overall height 9.7 mm
Mechanical design
Mounting soldering into PCB
Illumination fully illuminated 1 LED
LED colour see order block
LED type 2 mm
Other specifications
Ambient temp. operating
min. -25 °C
Ambient temp. operating
max. +70 °C
Storage temperature min. -40 °C
Storage temperature max.
(product) +80 °C
Storage temperature max.
(in tube) +50 °C
Resistance to constant
environment according to
IEC 600 68-2-3 and 2-30
Resistance at variable
environment according to
IEC 600 68-2-14 and 2-33
Soldering time max. 2,5 sec.
Soldering temperature
max. 250 °C
Flammability of materials UL 94 HB
PCB Keyswitches 4 - 47
4
RF
Dimensional Drawing Signal Indicator RF 15
Hole Pattern Hole Pattern – Front Panel
No metal webs with 15.24 mm. View on component side.
All hole diameters 1,1 +/- 0,1 mm.
RF short-travel keyswitches
Stock items are marked
by bold printed order numbers.
4 - 48 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 15 signal indicator, fully illuminated, 1 LED
Pict.: green
Overall height Illumination Colour of lens LED colour LED type Order no.
9.7 mm fully illuminated
1 LED
red red 2 mm 3.14.200.051/0000
9.7 mm fully illuminated
1 LED
green green 2 mm 3.14.200.052/0000
9.7 mm fully illuminated
1 LED
yellow yellow 2 mm 3.14.200.053/0000
9.7 mm fully illuminated
1 LED
orange yellow 2 mm 3.14.200.054/0000
9.7 mm fully illuminated
1 LED
blue blue 2 mm 3.14.200.055/0000
Technical data see page 4 - 46
For more information, see LEDs.
Technical data of LED see seperate page of the beginning of this chapter.
4 - 50 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 19 short-travel keyswitch
General data
Application notes:
RF 19 keys offer a large actuation area. When designing low-profile keyboards with a grid of >= 23 mm, frame webs remain
free between the individual keys.
The overlay can be glued onto these frame webs; we recommend area embossing over the keys for the overlay.
Technical data
General information
Colour of lens see order block
Recommended key grid 23 mm
Dimensions
Length 19.05 mm
Width 19.05 mm
Overall height 9.7 mm
Mechanical design
Mounting soldering into PCB
Terminals contacts tin-plated, fix
contact Ag plated
Contact system snap-action contact
Contact arrangement 1 NO
Contact materials Au/Ag
Illumination spot-/fully illuminated
LED colour see order block
LED type see order block
Mechanical characteristics
Operating force max. 2 ... 3 N
Operating travel 0.5 mm
Switching travel 0.5 mm
Robustness min. with through-plated PCB
100 N
Electrical characteristics
Rated voltage min. Au: 0.02 V, Ag: 3 V
Rated voltage max. Au: 42 V, Ag: 50 V
Rated current min. Au: 0,01 mA, Ag: 0,1 mA
Rated current max. Au: 100 mA, Ag: 250 mA
Rated power max.
(ohmic load) Au: 2 W, Ag: 12.5 W
Contact resistance when
new max. 100 mΩ
Contact resistance acc.
to life max. 3 Ω
Insulation resistance 109 Ω
ESD strength (underneath
overlay) 15 kV
Bouncing time max. 5 ms
Other specifications
Ambient temp. operating
min. -25 °C
Ambient temp. operating
max. +70 °C
Storage temperature min. -40 °C
Storage temperature max.
(product) +80 °C
Storage temperature max.
(in tube) +50 °C
Resistance to constant
environment according to
IEC 600 68-2-3 and 2-30
Resistance at variable
environment according to
IEC 600 68-2-14 and 2-33
Operating life min. 1,000,000
Soldering time max. 2,5 sec.
Soldering temperature
max. 250 °C
Flammability of materials UL 94 HB
PCB Keyswitches 4 - 51
4
RF
RF short-travel keyswitches
F 1 = Max. operating force
F 2 = Force at contact
F 2 is max. 55% of F 1
Operation characteristic limits RF
Keyswitch,
non-illuminated
Keyswitch,
fully illuminated
Keyswitch,
spot-illuminated
Force/Travel Diagram – Keyswitch RF 19 Circuit Diagram – Keyswitch RF 19
Dimensional Drawing
4 - 52 PCB Keyswitches
4
RF
RF short-travel keyswitches
* The LED may be positioned either on the left-hand or right-hand side.
Standard version: LED on left-hand side
View on component side, all hole diameters 1,1 +/- 0,1 mm
Hole Patterns RF 19
Hole Patterns – Front Panel RF 19
Stock items are marked
by bold printed order numbers.
PCB Keyswitches 4 - 53
4
RF
RF short-travel keyswitches
RF 19 short-travel keyswitch, non-illuminated
Contact materials Illumination Colour of lens LED colour LED type Order no.
Au not illuminated transparent 3.14.001.001/0000
Ag not illuminated transparent 3.14.001.006/0000
Technical data see page 4 - 50
Stock items are marked
by bold printed order numbers.
4 - 54 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 19 short-travel keyswitch, fully illuminated with 2 LEDs
Contact materials Illumination Colour of lens LED colour LED type Order no.
Au fully illuminated
2 LEDs
red red 2 mm 3.14.002.011/0000
Au fully illuminated
2 LEDs
green green 2 mm 3.14.002.012/0000
Au fully illuminated
2 LEDs
yellow yellow 2 mm 3.14.002.013/0000
Au fully illuminated
2 LEDs
orange yellow 2 mm 3.14.002.014/0000
Au fully illuminated
2 LEDs
blue blue 2 mm 3.14.002.015/0000
Ag fully illuminated
2 LEDs
red red 2 mm 3.14.002.021/0000
Ag fully illuminated
2 LEDs
green green 2 mm 3.14.002.022/0000
Ag fully illuminated
2 LEDs
yellow yellow 2 mm 3.14.002.023/0000
Ag fully illuminated
2 LEDs
orange yellow 2 mm 3.14.002.024/0000
Ag fully illuminated
2 LEDs
blue blue 2 mm 3.14.002.025/0000
Technical data see page 4 - 50
Technical data of LED see seperate page of the beginning of this chapter.
Stock items are marked
by bold printed order numbers.
PCB Keyswitches 4 - 55
4
RF
RF short-travel keyswitches
RF 19 short-travel keyswitch, 1 LED spot-illumination
Pict.: red
Contact materials Illumination Colour of lens LED colour LED type Order no.
Au spot illumination
1 LED
opaque white blue 3 mm 3.14.001.030/0000
Au spot illumination
1 LED
transparent red 3 mm 3.14.001.031/0000
Au spot illumination
1 LED
transparent green 3 mm 3.14.001.032/0000
Au spot illumination
1 LED
transparent yellow 3 mm 3.14.001.033/0000
Ag spot illumination
1 LED
opaque white blue 3 mm 3.14.001.040/0000
Ag spot illumination
1 LED
transparent red 3 mm 3.14.001.041/0000
Ag spot illumination
1 LED
transparent green 3 mm 3.14.001.042/0000
Ag spot illumination
1 LED
transparent yellow 3 mm 3.14.001.043/0000
Technical data see page 4 - 50
Versions with 2 LEDs available on request.
Technical data of LED see seperate page of the beginning of this chapter.
4 - 56 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 19 short-travel keyswitch, 1 NC + 1 NO
Technical data
General information
Recommended key grid 23 mm
Dimensions
Length 19.05 mm
Width 19.05 mm
Overall height 9.7 mm
Mechanical design
Mounting soldering into PCB
Terminals contacts tin-plated, fix
contact Ag plated
Contact system bridge contact
Contact arrangement 1 NC + 1 NO
Contact materials Au/Ag
Illumination none
Mechanical characteristics
Operating force max. 2 ... 3 N
Operating travel 0.5 mm
Switching travel 0.5 mm
Robustness min. with through-plated PCB
100 N
Electrical characteristics
Rated voltage min. Au: 0,02 V, Ag: 3 V V
Rated voltage max. Au: 42 V, Ag: 50 V V
Rated current min. Au: 0,01 mA, Ag: 0,1 mA
mA
Rated current max. Au: 100 mA, Ag: 250 mA
mA
Rated power max.
(ohmic load) Au: 2 W, Ag: 12.5 W
Contact resistance when
new max. 100 mΩ
Contact resistance acc.
to life max. 3 Ω
Insulation resistance 2 x 106 Ω
ESD strength (underneath
overlay) 15 kV
Bouncing time max. 5 ms
Other specifications
Ambient temp. operating
min. -25 °C
Ambient temp. operating
max. +70 °C
Storage temperature min. -40 °C
Storage temperature max.
(product) +80 °C
Storage temperature max.
(in tube) +50 °C
Resistance to constant
environment according to
IEC 600 68-2-3 and 2-30
Resistance at variable
environment according to
IEC 600 68-2-14 and 2-33
Operating life min. 100000
Soldering time max. 5 sec.
Soldering temperature
max. 265 °C
Flammability of materials UL 94 HB
For keycaps, refer to RK 90.
PCB Keyswitches 4 - 57
4
RF
RF short-travel keyswitches
Dimensional Drawing
Hole Pattern Hole Pattern – Front Panel
Circuit Diagram
view on component side
Stock items are marked
by bold printed order numbers.
4 - 58 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 19 short-travel keyswitch, non-illuminated
Contact materials Contact arrangement Illumination Colour of lens Order no.
Au 1 NC + 1 NO not illuminated opaque white 1.16.000.991/0000
Ag 1 NC + 1 NO not illuminated opaque white 1.16.000.990/0000
Technical data see page 4 - 56
4 - 60 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 19 H short-travel keyswitch
General data
Application notes:
The RF 19H key has an overall height of 12.5 mm and can be fully illuminated. When designing membrane keyboards, we
recommend using a key grid of at least 23 mm and a 0.13 mm overlay with area embossing over the keys.
You can use the O-ring (accessory) to block the key and use it as an indicator field or blank spaceholder.
Technical data
General information
Colour of lens see order block
Recommended key grid 24 mm
Dimensions
Length 19.05 mm
Width 19.05 mm
Overall height 12.5 mm
Mechanical design
Mounting soldering into PCB
Terminals contacts tin-plated, fix
contact Ag plated
Contact system snap-action contact
Contact arrangement 1 NO
Contact materials Au/Ag
Illumination spot-/fully illuminated
LED colour see order block
LED type see order block
Mechanical characteristics
Operating force max. 2 ... 3 N
Operating travel 0.5 mm
Switching travel 0.5 mm
Robustness min. with through-plated PCB
100 N
Electrical characteristics
Rated voltage min. Au: 0.02 V, Ag: 3 V
Rated voltage max. Au: 42 V, Ag: 50 V
Rated current min. Au: 0,01 mA, Ag: 0,1 mA
Rated current max. Au: 100 mA, Ag: 250 mA
Rated power max.
(ohmic load) Au: 2 W, Ag: 12.5 W
Contact resistance when
new max. 100 mΩ
Contact resistance acc.
to life max. 3 Ω
Insulation resistance 109 Ω
ESD strength (underneath
overlay) 15 kV
Bouncing time max. 5 ms
Other specifications
Ambient temp. operating
min. -25 °C
Ambient temp. operating
max. +70 °C
Storage temperature min. -40 °C
Storage temperature max.
(product) +80 °C
Storage temperature max.
(in tube) +50 °C
Resistance to constant
environment according to
IEC 600 68-2-3 and 2-30
Resistance at variable
environment according to
IEC 600 68-2-14 and 2-33
Operating life min. 1,000,000
Soldering time max. 2,5 sec.
Soldering temperature
max. 250 °C
Flammability of materials UL 94 HB
PCB Keyswitches 4 - 61
4
RF
RF short-travel keyswitches
F 1 = Max. operating force
F 2 = Force at contact
F 2 is max. 55% of F 1
Operation characteristic limits RF
Keyswitch,
non illuminated
Keyswitch,
fully illuminated
Force/Travel Diagram – Keyswitch RF 19 H Circuit Diagram – Keyswitch RF 19 H
Dimensional Drawing
4 - 62 PCB Keyswitches
4
RF
Stock items are marked
by bold printed order numbers.
RF short-travel keyswitches
Description Photo Order no. Page
Accessories RF 19 H short-travel keyswitch
O-ring, black, 17.0 x 1.5, for blocking RF 19H keys 5.30.125.003/0100 5 - 27
RF 19 H keyswitch, non-illuminated
Contact materials Illumination Colour of lens LED colour LED type Order no.
Au not illuminated white 3.14.001.501/0000
Ag not illuminated white 3.14.001.506/0000
Technical data see page 4 - 60
* The LED may be positioned either on the left-hand or
right-hand side.
Standard version: LED on left-hand side
View on component side, all hole diameters
1,1 +/- 0,1 mm
Hole Pattern RF 19 H Hole Pattern – Front Panel RF 19 H
LED
Keyswitch not illuminated
Stock items are marked
by bold printed order numbers.
PCB Keyswitches 4 - 63
4
RF
RF short-travel keyswitches
RF 19 H short-travel keyswitch, fully illuminated
Contact materials Illumination Colour of lens LED colour LED type Order no.
Au fully illuminated
2 LEDs
red red 2 mm 3.14.002.613/0000
Au fully illuminated
2 LEDs
green green 2 mm 3.14.002.632/0000
Au fully illuminated
1 LED
green green super bright 3 mm 3.14.002.633/0000
Au fully illuminated
2 LEDs
yellow yellow 2 mm 3.14.002.653/0000
Au fully illuminated
1 LED
white white 3 mm 3.14.002.684/0000
Au fully illuminated
2 LEDs
orange yellow 2 mm 3.14.002.673/0000
Au fully illuminated
2 LEDs
white multi colour 3 mm 3.14.001.672/0000
Au fully illuminated
1 LED
blue blue 3 mm 3.14.002.683/0000
Ag fully illuminated
2 LEDs
red red 2 mm 3.14.002.623/0000
Ag fully illuminated
2 LEDs
green green 2 mm 3.14.002.642/0000
Ag fully illuminated
1 LED
green green super bright 3 mm 3.14.002.643/0000
Ag fully illuminated
1 LED
blue blue super bright 3 mm 3.14.002.688/0000
Ag fully illuminated
2 LEDs
yellow yellow 2 mm 3.14.002.663/0000
Ag fully illuminated
1 LED
white white 3 mm 3.14.002.689/0000
Ag fully illuminated
2 LEDs
orange yellow 2 mm 3.14.002.678/0000
Ag fully illuminated
2 LEDs
white multi colour 3 mm 3.14.001.682/0000
Technical data see page 4 - 60
When using the keyswitches with multicolour LEDs the illumination colour can be varied from red to green by change of polarity. Due to
the frequency of the polarity-changes the colours red, green, yellow as well as all secondary colours from these are possible.
Technical data of LED see seperate page of the beginning of this chapter.
4 - 64 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 19 signal indicator
1 x 2-module
0.5 x 2-module
1 x 1-module
Pict.: 0.5 x 1-module
Technical data
General information
Colour of lens see order block
Recommended key grid 23/x mm
Dimensions
Length see order block
Width see order block
Overall height 9.15 mm
Mechanical design
Mounting soldering into PCB
Illumination see order block
LED colour see order block
LED type see order block
Other specifications
Ambient temp. operating
min. -25 °C
Ambient temp. operating
max. +70 °C
Storage temperature min. -40 °C
Storage temperature max.
(product) +80 °C
Storage temperature max.
(in tube) +50 °C
Resistance to constant
environment according to
IEC 600 68-2-3 and 2-30
Resistance at variable
environment according to
IEC 600 68-2-14 and 2-33
Soldering time max. 2,5 sec.
Soldering temperature
max. 250 °C
Flammability of materials UL 94 HB
PCB Keyswitches 4 - 65
4
RF
RF short-travel keyswitches
* The LED may be positioned either on the left-hand or right-hand side.
Standard verstion: LED on left-hand side
View on component side, all hole diameters 1,1 +/- 0,1 mm
Front panel cut-out = outer keyswitch size + 1 mm
Dimensional Drawing Signal Indicator RF 19
Hole Patterns RF 19
Stock items are marked
by bold printed order numbers.
4 - 66 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF 19 signal indicator, 1/2 x 1-module
Housing
Lens
Illuminated area
16.4 x 7.8 mm
Pict.: 0,5 x 1-module, yellow
Illumination Colour of lens LED colour LED type Order no.
fully illuminated
1 LED
red red 2 mm 3.14.002.061/0000
fully illuminated
1 LED
green green 2 mm 3.14.002.062/0000
fully illuminated
1 LED
yellow yellow 2 mm 3.14.002.063/0000
fully illuminated
1 LED
orange yellow 2 mm 3.14.002.064/0000
Technical data see page 4 - 64
For more information, see LEDs.
RF 19 signal indicator, 1/2 x 2-module
Pict.: 0,5 x 2-module, yellow
Illumination Colour of lens LED colour LED type Order no.
fully illuminated
3 LEDs
red red 2 mm 3.14.002.908/0000
fully illuminated
3 LEDs
green green 2 mm 3.14.002.909/0000
fully illuminated
3 LEDs
yellow yellow 2 mm 3.14.002.910/0000
fully illuminated
3 LEDs
orange yellow 2 mm 3.14.002.911/0000
Technical data see page 4 - 64
For more information, see LEDs.
Stock items are marked
by bold printed order numbers.
PCB Keyswitches 4 - 67
4
RF
RF short-travel keyswitches
RF 19 signal indicator, 1 x 1-module
Pict.: 1 x 1-module, green
Illumination Colour of lens LED colour LED type Order no.
fully illuminated
2 LEDs
red red 2 mm 3.14.002.051/0000
fully illuminated
2 LEDs
green green 2 mm 3.14.002.052/0000
fully illuminated
2 LEDs
yellow yellow 2 mm 3.14.002.053/0000
fully illuminated
2 LEDs
orange yellow 2 mm 3.14.002.054/0000
fully illuminated
2 LEDs
blue blue 2 mm 3.14.001.659/0000
Technical data see page 4 - 64
For more information, see LEDs.
Suitable for RK 90 system design, illuminated for 2-module keycap.
RF 19 signal indicator, 1 x 2-module
Pict.: 1 x 2-module, red
Illumination Colour of lens LED colour LED type Order no.
fully illuminated
5 LEDs
red red 2 mm 3.14.002.071/0000
fully illuminated
5 LEDs
green green 2 mm 3.14.002.072/0000
fully illuminated
5 LEDs
yellow yellow 2 mm 3.14.002.073/0000
fully illuminated
5 LEDs
orange yellow 2 mm 3.14.002.074/0000
Technical data see page 4 - 64
For more information, see LEDs.
Stock items are marked
by bold printed order numbers.
4 - 68 PCB Keyswitches
4
RF
RF short-travel keyswitches
RF special accessories
Pict.: light grey round and triangular versions
Extension plunger for RF 15 N, round head
Pict.: light grey
Length Width Overall height Diameter Colour Order no.
9 mm 10 mm 5.46.011.036/0710
9.7 mm 10 mm 5.46.011.030/0710
12.5 mm 10 mm 5.46.011.037/0710
13 mm 10 mm 5.46.011.038/0710
22.5 mm 10 mm 5.46.011.028/0710
Length of plunger = Overall height - 4.25 mm.
Stock items are marked
by bold printed order numbers.
PCB Keyswitches 4 - 69
4
RF
RF short-travel keyswitches
Extension plunger for RF 15 N, round head, with recess for LED
Length Width Overall height Diameter Colour Order no.
9 mm 15 mm 5.46.017.036/0710
9.7 mm 15 mm 5.46.017.030/0710
12.5 mm 15 mm 5.46.017.037/0710
13 mm 15 mm 5.46.017.038/0710
22.5 mm 15 mm 5.46.017.028/0710
Keycap for RF 15, snap-on, for overall height 12.5 mm
Length Width Overall height Diameter Colour Order no.
14.2 mm 14.2 mm 12.5 mm beige 5.46.654.059/0227
Stock items are marked
by bold printed order numbers.
4 - 70 PCB Keyswitches
4
RF
RF short-travel keyswitches
Spacers, round
Overlay
Front panel
Spacer
PCB
Length Width Overall height Diameter Colour Order no.
6.2 mm blue 5.30.759.251/0000
9.00 mm green 5.30.759.046/0000
3.50 mm blue transparent 5.30.759.023/0000
4 mm green 5.30.759.025/0000
4.25 mm blue 5.30.759.026/0000
4.50 mm red 5.30.759.027/0000
4.75 mm blue transparent 5.30.759.028/0000
5 mm black 5.30.759.029/0000
5.25 mm yellow orange
transparent
5.30.759.030/0000
5.50 mm yellow 5.30.759.031/0000
5.75 mm green 5.30.759.032/0000
6 mm blue 5.30.759.033/0000
6.25 mm red 5.30.759.034/0000
6.50 mm blue transparent 5.30.759.035/0000
6.75 mm black 5.30.759.036/0000
7 mm yellow orange
transparent
5.30.759.037/0000
7.25 mm yellow 5.30.759.038/0000
7.50 mm green 5.30.759.039/0000
7.75 mm blue 5.30.759.040/0000
8 mm red 5.30.759.041/0000
8.25 mm blue transparent 5.30.759.042/0000
10.00 mm black 5.30.759.043/0104
Stock items are marked
by bold printed order numbers.
PCB Keyswitches 4 - 71
4
RF
RF short-travel keyswitches
Spacers, triangular
Countersink
from height > 4 mm
Overlay
Front panel
Spacer
PCB
Length Width Overall height Diameter Colour Order no.
6.2 mm blue 5.30.759.253/0000
2.50 mm blue 5.30.759.094/0000
2.75 mm red 5.30.759.095/0000
3 mm blue transparent 5.30.759.096/0000
3.25 mm black 5.30.759.097/0000
3.50 mm yellow orange
transparent
5.30.759.098/0000
3.75 mm yellow 5.30.759.099/0000
4 mm green 5.30.759.100/0000
4.25 mm blue 5.30.759.101/0000
4.50 mm red 5.30.759.102/0000
4.75 mm blue transparent 5.30.759.103/0000
5 mm black 5.30.759.104/0000
5.25 mm yellow orange
transparent
5.30.759.105/0000
5.50 mm yellow 5.30.759.106/0000
5.75 mm green 5.30.759.107/0000
6 mm blue 5.30.759.108/0000
6.25 mm red 5.30.759.109/0000
6.50 mm blue transparent 5.30.759.110/0000
6.75 mm black 5.30.759.111/0000
7 mm yellow orange
transparent
5.30.759.112/0000
7.25 mm yellow 5.30.759.113/0000
7.50 mm green 5.30.759.114/0000
7.75 mm blue 5.30.759.115/0000
Stock items are marked
by bold printed order numbers.
4 - 72 PCB Keyswitches
4
RF
RF short-travel keyswitches
Length Width Overall height Diameter Colour Order no.
8 mm red 5.30.759.116/0000
8.25 mm blue transparent 5.30.759.117/0000
10.00 mm black 5.30.759.124/0000
10.25 mm yellow orange
transparent
5.30.759.125/0000
LED spacer for RF 15 N
Pict.: light grey
Length
Characteristic 1
Width Overall height Order no.
Characteristic 2
Diameter Colour
2.2 mm 12.5 mm 5 mm light grey 5.30.109.010/0756
12 mm 22.5 mm 5 mm black 5.30.109.019/0105
9 mm blue 5.30.759.254/0000
TL082
Wide Bandwidth Dual JFET Input Operational Amplifier
General Description
These devices are low cost, high speed, dual JFET input
operational amplifiers with an internally trimmed input offset
voltage (BI-FET II™ technology). They require low supply
current yet maintain a large gain bandwidth product and fast
slew rate. In addition, well matched high voltage JFET input
devices provide very low input bias and offset currents. The
TL082 is pin compatible with the standard LM1558 allowing
designers to immediately upgrade the overall performance of
existing LM1558 and most LM358 designs.
These amplifiers may be used in applications such as high
speed integrators, fast D/A converters, sample and hold
circuits and many other circuits requiring low input offset
voltage, low input bias current, high input impedance, high
slew rate and wide bandwidth. The devices also exhibit low
noise and offset voltage drift.
Features
n Internally trimmed offset voltage: 15 mV
n Low input bias current: 50 pA
n Low input noise voltage: 16nV/√Hz
n Low input noise current: 0.01 pA/√Hz
n Wide gain bandwidth: 4 MHz
n High slew rate: 13 V/μs
n Low supply current: 3.6 mA
n High input impedance: 1012Ω
n Low total harmonic distortion: ≤0.02%
n Low 1/f noise corner: 50 Hz
n Fast settling time to 0.01%: 2 μs
Typical Connection
00835701
Connection Diagram
DIP/SO Package (Top View)
00835703
Order Number TL082CM or TL082CP
See NS Package Number M08A or N08E
Simplified Schematic
00835702
BI-FET II™ is a trademark of National Semiconductor Corp.
August 2000
TL082 Wide Bandwidth Dual JFET Input Operational Amplifier
© 2004 National Semiconductor Corporation DS008357 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage ±18V
Power Dissipation (Note 2)
Operating Temperature Range 0°C to +70°C
Tj(MAX) 150°C
Differential Input Voltage ±30V
Input Voltage Range (Note 3) ±15V
Output Short Circuit Duration Continuous
Storage Temperature Range −65°C to +150°C
Lead Temp. (Soldering, 10 seconds) 260°C
ESD rating to be determined.
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage
to the device may occur. Operating Ratings indicate conditions for which the
device is functional, but do not guarantee specific performance limits.
DC Electrical Characteristics (Note 5)
Symbol Parameter Conditions TL082C Units
Min Typ Max
VOS Input Offset Voltage RS = 10 kΩ, TA = 25°C 5 15 mV
Over Temperature 20 mV
ΔVOS/ΔT Average TC of Input Offset RS = 10 kΩ 10 μV/°C
Voltage
IOS Input Offset Current Tj = 25°C, (Notes 5, 6) 25 200 pA
Tj ≤ 70°C 4 nA
IB Input Bias Current Tj = 25°C, (Notes 5, 6) 50 400 pA
Tj ≤ 70°C 8 nA
RIN Input Resistance Tj = 25°C 1012 Ω
AVOL Large Signal Voltage Gain VS = ±15V, TA = 25°C 25 100 V/mV
VO = ±10V, RL = 2 kΩ
Over Temperature 15 V/mV
VO Output Voltage Swing VS = ±15V, RL = 10 kΩ ±12 ±13.5 V
VCM Input Common-Mode Voltage VS = ±15V ±11 +15 V
Range −12 V
CMRR Common-Mode Rejection Ratio RS ≤ 10 kΩ 70 100 dB
PSRR Supply Voltage Rejection Ratio (Note 7) 70 100 dB
IS Supply Current 3.6 5.6 mA
TL082
www.national.com 2
AC Electrical Characteristics (Note 5)
Symbol Parameter Conditions TL082C Units
Min Typ Max
Amplifier to Amplifier Coupling TA = 25°C, f = 1Hz- −120 dB
20 kHz (Input Referred)
SR Slew Rate VS = ±15V, TA = 25°C 8 13 V/μs
GBW Gain Bandwidth Product VS = ±15V, TA = 25°C 4 MHz
en Equivalent Input Noise Voltage TA = 25°C, RS = 100Ω, 25 nV/√Hz
f = 1000 Hz
in Equivalent Input Noise Current Tj = 25°C, f = 1000 Hz 0.01 pA/√Hz
THD Total Harmonic Distortion AV = +10, RL = 10k,
VO = 20 Vp − p,
BW = 20 Hz−20 kHz
<0.02 %
Note 2: For operating at elevated temperature, the device must be derated based on a thermal resistance of 115°C/W junction to ambient for the N package.
Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 4: The power dissipation limit, however, cannot be exceeded.
Note 5: These specifications apply for VS = ±15V and 0°C ≤TA ≤ +70°C. VOS, IB and IOS are measured at VCM = 0.
Note 6: The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature, Tj. Due to the limited
production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient
temperature as a result of internal power dissipation, PD. Tj = TA + θjA PD where θjA is the thermal resistance from junction to ambient. Use of a heat sink is
recommended if input bias current is to be kept to a minimum.
Note 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. VS
= ±6V to ±15V.
Typical Performance Characteristics
Input Bias Current Input Bias Current
00835718
00835719
TL082
3 www.national.com
Typical Performance Characteristics (Continued)
Supply Current
Positive Common-Mode Input
Voltage Limit
00835720
00835721
Negative Common-Mode Input
Voltage Limit Positive Current Limit
00835722 00835723
Negative Current Limit Voltage Swing
00835724
00835725
TL082
www.national.com 4
Typical Performance Characteristics (Continued)
Output Voltage Swing Gain Bandwidth
00835726
00835727
Bode Plot Slew Rate
00835728 00835729
Distortion vs Frequency
Undistorted Output
Voltage Swing
00835730 00835731
TL082
5 www.national.com
Typical Performance Characteristics (Continued)
Open Loop Frequency
Response
Common-Mode Rejection
Ratio
00835732 00835733
Power Supply Rejection
Ratio
Equivalent Input Noise
Voltage
00835734
00835735
Open Loop Voltage
Gain (V/V) Output Impedance
00835736 00835737
TL082
www.national.com 6
Typical Performance Characteristics (Continued)
Inverter Setting Time
00835738
Pulse Response
Small Signal Inverting
00835706
Small Signal Non-Inverting
00835707
Large Signal Inverting
00835708
Large Signal Non-Inverting
00835709
TL082
7 www.national.com
Pulse Response (Continued)
Current Limit (RL = 100Ω)
00835710
Application Hints
These devices are op amps with an internally trimmed input
offset voltage and JFET input devices (BI-FET II). These
JFETs have large reverse breakdown voltages from gate to
source and drain eliminating the need for clamps across the
inputs. Therefore, large differential input voltages can easily
be accommodated without a large increase in input current.
The maximum differential input voltage is independent of the
supply voltages. However, neither of the input voltages
should be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a destroyed
unit.
Exceeding the negative common-mode limit on either input
will cause a reversal of the phase to the output and force the
amplifier output to the corresponding high or low state. Exceeding
the negative common-mode limit on both inputs will
force the amplifier output to a high state. In neither case
does a latch occur since raising the input back within the
common-mode range again puts the input stage and thus
the amplifier in a normal operating mode.
Exceeding the positive common-mode limit on a single input
will not change the phase of the output; however, if both
inputs exceed the limit, the output of the amplifier will be
forced to a high state.
The amplifiers will operate with a common-mode input voltage
equal to the positive supply; however, the gain bandwidth
and slew rate may be decreased in this condition.
When the negative common-mode voltage swings to within
3V of the negative supply, an increase in input offset voltage
may occur.
Each amplifier is individually biased by a zener reference
which allows normal circuit operation on ±6V power supplies.
Supply voltages less than these may result in lower
gain bandwidth and slew rate.
The amplifiers will drive a 2 kΩ load resistance to ±10V over
the full temperature range of 0°C to +70°C. If the amplifier is
forced to drive heavier load currents, however, an increase
in input offset voltage may occur on the negative voltage
swing and finally reach an active current limit on both positive
and negative swings.
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
Because these amplifiers are JFET rather than MOSFET
input op amps they do not require special handling.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to
an input should be placed with the body close to the input to
minimize “pick-up” and maximize the frequency of the feedback
pole by minimizing the capacitance from the input to
ground.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to AC
ground set the frequency of the pole. In many instances the
frequency of this pole is much greater than the expected 3
dB frequency of the closed loop gain and consequently there
is negligible effect on stability margin. However, if the feedback
pole is less than approximately 6 times the expected 3
dB frequency a lead capacitor should be placed from the
output to the input of the op amp. The value of the added
capacitor should be such that the RC time constant of this
capacitor and the resistance it parallels is greater than or
equal to the original feedback pole time constant.
TL082
www.national.com 8
Detailed Schematic
00835711
Typical Applications
Three-Band Active Tone Control
00835712
TL082
9 www.national.com
Typical Applications (Continued)
00835713
• All potentiometers are linear taper
• Use the LF347 Quad for stereo applications
Note 8: All controls flat.
Note 9: Bass and treble boost, mid flat.
Note 10: Bass and treble cut, mid flat.
Note 11: Mid boost, bass and treble flat.
Note 12: Mid cut, bass and treble flat.
Improved CMRR Instrumentation Amplifier
00835714
C and are separate isolated grounds
Matching of R2’s, R4’s and R5’s control CMRR
With AVT = 1400, resistor matching = 0.01%: CMRR = 136 dB
• Very high input impedance
• Super high CMRR
TL082
www.national.com 10
Typical Applications (Continued)
Fourth Order Low Pass Butterworth Filter
00835715
Fourth Order High Pass Butterworth Filter
00835716
TL082
11 www.national.com
Typical Applications (Continued)
Ohms to Volts Converter
00835717
TL082
www.national.com 12
Physical Dimensions inches (millimeters)
unless otherwise noted
Order Number TL082CM
NS Package M08A
Order Number TL082CP
NS Package N08E
TL082
13 www.national.com
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship
Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned
Substances’’ as defined in CSP-9-111S2.
National Semiconductor
Americas Customer
Support Center
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
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Europe Customer Support Center
Fax: +49 (0) 180-530 85 86
Email: europe.support@nsc.com
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English Tel: +44 (0) 870 24 0 2171
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Asia Pacific Customer
Support Center
Email: ap.support@nsc.com
National Semiconductor
Japan Customer Support Center
Fax: 81-3-5639-7507
Email: jpn.feedback@nsc.com
Tel: 81-3-5639-7560
www.national.com TL082 Wide Bandwidth Dual JFET Input Operational Amplifier
UDG-02157
VIN
VOUT
5
13
12
16
15
1
2
3
4
6 11
7
8
14
10
9
+
-
KFF
RT
BP5
SGND
VIN
BPN10
SW
BP10
SYNC
ILIM
TPS40060PWP
SS/SD
VFB
COMP
HDRV
LDRV
PGND
8
TPS40060
TPS40061
www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013
WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER
Check for Samples: TPS40060, TPS40061
1FEATURES APPLICATIONS
2• Operating Input Voltage 10 V to 55 V • Networking Equipment
• Input Voltage Feed-Forward Compensation • Telecom Equipment
• < 1% Internal 0.7-V Reference • Base Stations
• Programmable Fixed-Frequency, Up to 1-MHz • Servers
Voltage Mode Controller
• Internal Gate Drive Outputs for High-Side P- DESCRIPTION
Channel and Synchronous N-Channel The TPS40060 and TPS40061 are high-voltage, wide
MOSFETs input (10 V to 55 V) synchronous, step-down
• 16-Pin PowerPAD™ Package (θ converters. JC = 2°C/W)
• Thermal Shutdown This family of devices offers design flexibility with a
variety of user programmable functions, including;
• Externally Synchronizable soft-start, UVLO, operating frequency, voltage feed-
• Programmable High-Side Sense Short Circuit forward, high-side current limit, and loop
Protection compensation. These devices are also
• Programmable Closed-Loop Soft-Start synchronizable to an external supply.
• TPS40060 Source Only/TPS40061 Source/Sink The TPS40060 and TPS40061 incorporate MOSFET
gate drivers for external P-channel high-side and Nchannel
synchronous rectifier (SR) MOSFETs. Gate
drive logic incorporates anti-cross conduction circuitry
to prevent simultaneous high-side and synchronous
rectifier conduction.
SIMPLIFIED APPLICATION DIAGRAM
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2002–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
THERMAL
PAD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
KFF
RT
BP5
SYNC
SGND
SS/SD
VFB
COMP
ILIM
VIN
HDRV
BPN10
SW
BP10
LDRV
PGND
PWP PACKAGE (1)(2)
(TOP VIEW)
TPS40060
TPS40061
SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
TA LOAD CURRENT PACKAGE(1) PART NUMBER
SOURCE(2) Plastic HTSSOP (PWP) TPS40060PWP
–40°C to 85°C
SOURCE/SIN(2) Plastic HTSSOP (PWP) TPS40061PWP
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40060PWPR). See the Application
Information of the data sheet for PowerPAD drawing and layout information.
(2) See Application Information section.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS40060
TPS40061
VIN 60 V
VFB, SS/SD, SYNC –0.3 V to 6 V
VIN Input voltage range SW –0.3 V to 60 V or VIN+5 V (whichever is less)
SW. transient < 50 ns –2.5 V
VOUT Output voltage range COMP, RT, KFF, SS –0.3 V to 6 V
IIN Input current KFF 5 mA
IOUT Output current RT 200 μA
TJ Operating junction temperature range –40°C to 125°C
Tstg Storage temperature –55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
VIN Input voltage 10 55 V
TA Operating free-air temperature –40 85 °C
(1) For more information on the PWP package, refer to TI Technical Brief (SLMA002).
(2) PowerPAD™ heat slug must be connected to SGND (Pin 5), or electrically isolated from all other pins.
2 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: TPS40060 TPS40061
TPS40060
TPS40061
www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS
TA = –40°C to 85°C, VIN = 24 Vdc, RT = 165 kΩ, IKFF = 113 μA, fSW = 300 kHz, all parameters at zero power dissipation (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
VIN Input voltage range, VIN 10 55 V
OPERATING CURRENT
IDD Quiescent current Output drivers not switching 1.5 2.5 mA
5-V REFERENCE
VBP5 Input voltage 4.5 5.0 5.5 V
OSCILLATOR/RAMP GENERATOR(1)
fOSC Frequency 270 300 330 kHz
VRAMP PWM ramp voltage(2) 2
VIH High-level input voltage, SYNC 2 V
VIL Low-level input voltage, SYNC 0.8
ISYNC Input current, SYNC 5 10 μA
Pulse width, SYNC Pulse amplitude = 5 V 50 ns
VRT RT voltage 2.32 2.50 2.68 V
Maximum duty cycle VFB = 0 V, 100 kHz ≤ fSW≤ 1 MHz 85% 98%
Minimum duty cycle VFB ≥ 0.75 V 0%
VKFF Feed-forward voltage 3.35 3.50 3.65 V
IKFF Feed-forward current operating range(2) 20 1100 μA
SS/SD (SOFT START)
ISS Soft-start source current 1.5 2.3 2.9 μA
VSS Soft-start clamp voltage 3.1 3.7 4.0 V
tDSCH Discharge time CSS = 220 pF 1.6 2.2 2.9
μs
tSS Soft-start time CSS = 220 pF, 0 V ≤ VSS ≤ 1.6 V 120 155 235
SS/SD (SHUTDOWN)
VSD Shutdown threshold voltage 90 130 160
VEN Device action threshold voltage 170 210 260 mV
Hysteresis 80
10-V REFERENCE
VBP10 Input voltage 9.0 9.7 10.7 V
ERROR AMPLIFIER
TA = 25°C 0.698 0.700 0.704
VFB Feedback regulation voltage 0°C ≤ TA ≤ 85°C 0.690 0.700 0.707 V
0.690 0.700 0.715
GBW Gain bandwidth 3 5 MHz
AVOL Open loop gain 60 80 dB
IOH High-level output source current VCOMP = 2.0 V, VFB = 0 V 1.5 4.0
mA
IOL Low-level output sink current VCOMP = 2.0 V, VFB = 1 V 2.5 4.0
IBIAS Input bias current VFB = 0.7 V 100 300 nA
VOH High-level output voltage IOH = 0.5 mA, VFB = 0 V 3.25 3.45 3.60
V
VOL Low-level output voltage IOL = 0.5 mA, VFB = 1 V 0.050 0.215 0.350
(1) KFF current (IKFF) increases with SYNC frequency (fSYNC) and decreases with maximum duty cycle (DMAX).
(2) Ensured by design. Not production tested.
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: TPS40060 TPS40061
TPS40060
TPS40061
SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TA = –40°C to 85°C, VIN = 24 Vdc, RT = 165 kΩ, IKFF = 113 μA, fSW = 300 kHz, all parameters at zero power dissipation (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT LIMIT
TA = 25°C 8.8 10.0 11.4
ISINK Current limit sink current 0°C ≤ TA ≤ 85°C 8.3 11.9 μA
-40°C ≤ TA ≤ 0°C 7.5 11.5
VILIM = 23.7 V, VSW = (VILIM – 0.5 V) 330 500
tDELAY Propagation delay to output
VILIM = 23.7 V, VSW = (VILIM – 2 V) 275 375 ns
tON Switch leading-edge blanking pulse time(3) 100
tOFF Off time during a fault 7 cycles
VOS Overcurrent comparator offset voltage -200 -60 50 mV
OUTPUT DRIVER
tHFALL High-side driver fall time(3) CHDRV = 2200 pF, (VIN – VBPN10) 48 96
tHRISE High-side driver rise time(3) CHDRV = 2200 pF, (VIN – VBPN10) 36 72
ns
tLFALL Low-side driver fall time(3) CLDRV = 2200 pF, BP10 24 48
tLRISE Low-side driver rise time(3) CLDRV = 2200 pF, BP10 48 96
VOH High-level ouput voltage, HDRV IHDRV = 0.1 A , (VIN – VHDRV) 1.0 1.4
VOL Low-level ouput voltage, HDRV IHDRV = 0.1 A , (VHDRV – VBPN10) 0.75
V
VOH High-level ouput voltage, LDRV ILDRV = 0.1 A, (VBP10 – VLDRV) 1.0 1.5
VOL Low-level ouput voltage, LDRV ILDRV = 0.1 A 0.5
Minimum controllable pulse width 100 150 ns
BPN10 REGULATOR
VBPN1 Output voltage Outputs off –7.5 –8.5 –9.5 V
0
RECTIFIER ZERO CURRENT COMPARATOR (TPS40060 ONLY)
VSW Switch voltage LDRV output OFF –6 0 6 mV
SW NODE
ILEAK Leakage current(3) 1 μA
THERMAL SHUTDOWN
Shutdown temperature(3) 165
TSD °C
Hysteresis(3) 25
UNDERVOLTAGE LOCKOUT
VUVLO Undervoltage lockout threshold voltage, BP10 RKFF = 10 kΩ 6.25 6.5 7.5
Undervoltage lockout hysteresis 0.4 V
VKFF KFF programmable threshold voltage RKFF = 82.5 kΩ 9 10 11
(3) Ensured by design. Not production tested.
4 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: TPS40060 TPS40061
TPS40060
TPS40061
www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013
Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
5-V reference. BP5 3 O This pin should be bypassed to ground with a 0.1-μF ceramic capacitor. This pin may be used with an external DC load of 1 mA or less.
BP10 11 O 10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-μF ceramic capacitor. This pin may be used with an external DC load of 1 mA or less.
BPN10 13 O Negative 8-V reference with respect to VIN. This voltage is used to provide gate drive for the high side P-channel MOSFET. This pin should be bypassed to VIN with a 0.1-μF capacitor
Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the
COMP 8 I VFB pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to
improve large signal transient response.
HDRV 14 O Floating gate drive for the high-side P-channel MOSFET. This pin switches from VIN (MOSFET off) to BPN10 (MOSFET on).
Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a
ILIM 16 I voltage drop across an external resistor connected from this pin to VIN. The voltage on this pin is compared to the
voltage drop (VIN -SW) across the high side MOSFET during conduction.
KFF 1 I A resistor is connected from this pin to VIN to program the amount of voltage feed-forward. The current fed into this pin is internally divided and used to control the slope of the PWM ramp.
LDRV 10 I Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground (MOSFET off).
PGND 9 Power ground reference for the device. There should be a low-impedance connection from this point to the source of the power MOSFET.
RT 2 I A resistor is connected from this pin to ground to set the internal oscillator ramp charging current and switching frequency.
SGND 5 Signal ground reference for the device.
Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The
capacitor is charged with an internal current source of 2.3 μA. The resulting voltage ramp on the SS pin is used as
a second non-inverting input to the error amplifier. The output voltage begins to rise when VSS/SD is approximately
SS/SD 6 I 0.85 V. The output continues to rise and reaches regulation when VSS/SD is approximately 1.55 V. The controller is
considered shut down when VSS/SD is 125 mV or less. All internal circuitry is inactive. The internal circuitry is
enabled when VSS/SD is 210 mV or greater. When VSS/SD is less than approximately 0.85 V, the outputs cease
switching and the output voltage (VOUT) decays while the internal circuitry remains active.
SW 12 I This pin is connected to the switched node of the converter and used for overcurrent sensing. This pin is used for zero current sensing in the TPS40060.
SYNC 4 I Synchronization input for the device. This pin can be used to synchronize the oscillator to an external master frequency.
VFB 7 I Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference voltage, 0.7 V.
VIN 15 I Supply voltage for the device.
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: TPS40060 TPS40061
1
2
7
+
+
6
Ramp Generator
Clock
Oscillator
14
10
13
12
9
15 11
8
4
5
BP10
BP10
07VREF
7
7
16
3−bit up/down
Fault Counter
7
7
7
07VREF
1V5REF
3V5REF
Reference
Voltages
7
Fault
7
Restart
CLK
7
CLK
BP5 7
3 BP5 7
7
Restart
+
7 07VREF
7
7
Fault
CL
S Q
R Q
7
CLK
CL
SW
7 SW
S Q
R Q
7
HDRV
LDRV
PGND
BPN10
VIN BP10
SYNC
RT
KFF
BP5
VFB
SS/SD
COMP
ILIM
SGND
Zero Current Detector
(TPS40060 Only)
10−V Regulator
7
1V5REF
VIN
7
7 HDRV
7
HDRV
7
BPN10
7
+
0.85 V
+
N-Channel
Driver
P-Channel
Driver
UDG−02160
TPS40060
TPS40061
SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com
SIMPLIFIED BLOCK DIAGRAM
6 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: TPS40060 TPS40061
UDG-02131
RAMP
COMP
SW
VIN
VIN
SW
COMP
RAMP
VPEAK
VVALLEY
T2
tON1 > tON2 and d1 > d2
t tON2 ON1
d
tON
T
T1
RT 1
fSW17.8210623 k
TPS40060
TPS40061
www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013
APPLICATION INFORMATION
The TPS40060/61 family of parts allows the user to optimize the PWM controller to the specific application.
The TPS40061 is the controller of choice for synchronous buck designs which will include most applications. It
has two quadrant operation and will source or sink output current. This provides the best transient response.
The TPS40060 operates in one quadrant and sources output current only, allowing for paralleling of converters
and ensures that one converter does not sink current from another converter. This controller also emulates a
standard buck converter at light loads where the inductor current goes discontinuous. At continuous output
inductor currents the controller operates as a synchronous buck converter to optimize efficiency.
SW NODE RESISTOR
The SW node of the converter will be negative during the dead time when both the upper and lower MOSFETs
are off. The magnitude of this negative voltage is dependent on the lower MOSFET body diode and the output
current which flows during this dead time. This negative voltage could affect the operation of the controller,
especially at low input voltages.
Therefore, a 10-Ω resistor must be placed between the lower MOSFET drain and pin 12 (SW) of the controller as
shown in Figure 14 as RSW.
SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)
The TPS40060 and TPS40061 have independent clock oscillator and ramp generator circuits. The clock
oscillator serves as the master clock to the ramp generator circuit. The switching frequency, fSW in kHz, of the
clock oscillator is set by a single resistor (RT) to ground. The clock frequency is related to RT, in kΩ by
Equation 1 and the relationship is charted in Figure 2.
(1)
PROGRAMMING THE RAMP GENERATOR CIRCUIT
The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides
voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp
magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations since
the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 1).
Figure 1. Voltage Feed-Forward Effect on PWM Duty Cycle
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: TPS40060 TPS40061
RKFF VIN (min)3.565.27RT1502 ()
100
0
200
300
400
500
600
400 600 800 1000
700
200
800
FEED-FORWARD IMPEDANCE
vs
SWITCHING FREQUENCY
RKFF - Feed-Forward Impedance - kW
fSW - Switching Frequency - kHz
VIN = 25 V
VIN = 15 V
VIN = 9 V
RT - Timing Resistance - kW
fSW - Switching Frequency - kHz
TIMING RESISTANCE
vs
SWITCHING FREQUENCY
0
100
0
200 400 600 800 1000
200
300
400
500
600
RKFF VIN (min)3.565.27RT1502 ()
TPS40060
TPS40061
SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com
The PWM ramp must be faster than the master clock frequency or the PWM is prevented from starting. The
PWM ramp time is programmed via a single resistor (RKFF) pulled up to VIN. RKFF is related to RT, and the
minimum input voltage, VIN(min) through the following:
where:
• VIN is the desired start-up (UVLO) input voltage
• RT is the timing resistor in kΩ (2)
See the section on UVLO operation for further description.
The curve showing the feedforward impedance required for a given switching frequency, fSW, at various input
voltages is shown in Figure 3.
For low input voltage and high duty cycle applications, the voltage feed-forward may limit the duty cycle
prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and
regulates the output voltages. For more information on large duty cycle operation, refer to Application Note
(SLUA310).
Figure 2. Figure 3.
UVLO OPERATION
The TPS40060 and TPS40061 use both fixed and variable (user programmable) UVLO protection. The fixed
UVLO monitors the BP10 and BP5 bypass voltages. The UVLO circuit holds the soft-start low until the BP5 and
BP10 voltage rails have exceeded their thresholds and the input voltage has exceed the user programmable
undervoltage threshold.
The TPS40060 and TPS40061 use the feed-forward pin, KFF, as a user programmable low-line UVLO detection.
This variable low-line UVLO threshold compares the PWM ramp duration to the oscillator clock period. An
undervoltage condition exists if the device receives a clock pulse before the ramp has reached 90% of its full
amplitude. The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF
pin. The KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF
resistor can be referenced to the oscillator frequency as described in Equation 3:
8 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: TPS40060 TPS40061
10 15
0.5
0
1.0
1.5
2.0
2.5
3.0
20 25 30 35 40 45 50 45
VUVLO - Output Voltage - V
VUVLO - Undervoltage Lockout Threshold - V
UNDERVOLTAGE LOCKOUT
vs
HYSTERESIS
UDG-02132
Clock
PWM RAMP
PowerGood
VIN
UVLO Threshold
1 2 3 4 5 6 7 1 2 1 2 3 4 5 6 7
TPS40060
TPS40061
www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013
where:
• VIN is the desired start-up (UVLO) input voltage
• RT is the timing resistor in kΩ (3)
The variable UVLO function utilizes a 3-bit full adder to prevent spurious shut-downs or turn-ons due to spikes or
fast line transients. When the adder reaches a total of seven counts in which the ramp duration is shorter the
clock cycle a powergood signal is asserted, a soft-start initiated, and the upper and lower MOSFETs are turned
off.
Once the soft-start is initiated, the UVLO circuit must see a total count of seven cycles in which the ramp
duration is longer than the clock cycle before an undervoltage condition is declared (See Figure 4).
Figure 4. Undervoltage Lockout Operation
Figure 5.
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: TPS40060 TPS40061
CSS
2.3 A
0.7 V
tSTART (Farads)
tSTART 2LCO (seconds)
TPS40060
TPS40061
SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com
The impedance of the input voltage can cause the input voltage, at the TPS4006x, to sag when the converter
starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents
nuisance shutdowns at the UVLO point.
With RT chosen to select the operating frequency and RKFF chosen to select the start-up voltage, the amount of
hysteresis voltage is shown in Figure 5.
PROGRAMMING SOFT START
TPS4006x uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start is
programmed by charging an external capacitor (CSS) via an internally generated current source. The voltage on
CSS minus 0.85 V, is fed into a separate non-inverting input to the error amplifier (in addition to FB and 0.7-V
VREF). The loop is closed on the lower of the (VCSS – 0.85 V) voltage or the internal reference voltage (0.7-V
VREF). Once the (VCSS – 0.85 V) voltage rises above the internal reference voltage, regulation is based on the
internal reference. To ensure a controlled ramp-up of the output voltage the soft-start time should be greater than
the L-CO time constant as described in Equation 4.
(4)
There is a direct correlation between tSTART and the input current required during start-up. The faster tSTART, the
higher the input current required during start-up. This relationship is describe in more detail in the section titled,
Programming the Current Limit, which follows. The soft-start capacitance, CSS, is described in Equation 5.
For applications in which the VIN supply ramps up slowly, (typically between 50 ms and 100 ms) it may be
necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO
tripping. The soft-start time should be longer than the time that the VINsupply transitions between 6 V and 7 V.
(5)
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Product Folder Links: TPS40060 TPS40061
RILIM
IOCRDS(on)[max]
ISINK
VOS
ISINK
()
( ) ( ) O O
LIM LOAD
START
C V
I I A
t
é ´ ù
= ê ú +
ë û
TPS40060
TPS40061
www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013
PROGRAMMING CURRENT LIMIT
This device uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection
scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the
MOSFET when the gate is driven low. The MOSFET voltage is compared to the voltage dropped across a
resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across
the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated.
The MOSFET remains off until the next switching cycle is initiated.
The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and
decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a restart is
issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this
period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the PWM
is re-enabled. If the fault has been removed the output starts up normally. If the output is still present the counter
counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 7 for typical overcurrent
protection waveforms.
The minimum current limit setpoint (ILIM) depends on tSTART, CO, VO, and the load current at start-up (ILOAD).
(6)
The current limit programming resistor (RILIM) is calculated using Equation 7. Care must be taken in choosing the
values used for VOS and ISINK in the equation. In order to ensure the output current at the overcurrent level, the
minimum value of ISINK and the maximum value of VOS must be used.
where:
• ISINK is the current into the ILIM pin and is nominally 8.3 μA, minimum
• IOC is the overcurrent setpoint which is the DC output current plus one-half of the peak inductor current
• VOS is the overcurrent comparator offset and is 50 mV maximum (7)
BP5, BP10 AND BPN10 INTERNAL VOLTAGE REGULATOR
Start-up characteristics of the BP5, BP10 and BPN10 regulators are shown in Figure 7. Slight variations in the
BP5 occurs dependent upon the switching frequency. Variation in the BPN10 and BP10 regulation characteristics
is also based on the load presented by switching the external MOSFETs.
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: TPS40060 TPS40061
VBPx - Output Voltage - V
VIN - Input Voltage - V
INTERNAL REGULATOR OUTPUT VOLTAGE
vs
INPUT VOLTAGE
2 4 6 8 10 12
6
8
10
12
2
4
0
BP10
BP5
BPN10
UDG-02136
HDRV
CLOCK
VVIN-VSW
SS
7 CURRENT LIMIT TRIPS
(HDRV CYCLE TERMINATED BY CURRENT LIMIT TRIP)
7 SOFT-START CYCLES
VILIM
tBLANKING
TPS40060
TPS40061
SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com
Figure 6. Typical Current Limit Protection Waveforms
Figure 7.
CALCULATING THE BPN10 AND BP10V BYPASS CAPACITOR
The BPN10 capacitance provides energy for the high-side driver. The BPN10 capacitor should be a good quality,
high-frequency capacitor. The size of the bypass capacitor depends on the total gate charge of the high-side
MOSFET and the amount of droop allowed on the bypass capacitor. The BPN10 capacitance is described in
Equation 8.
12 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: TPS40060 TPS40061
L
VINVOVO
VINIfSW
(H)
KFF ( IN(min) ) ( T(dummy) ) R = V - 3.5V ´ 65.27 ´R +1502 W
RT(dummy) 1
fSYNC17.8210623 k
CBP10V
QgSR
V
(F)
CBPN10
Qg
V
(F)
TPS40060
TPS40061
www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013
(8)
The 10-V reference pin, BP10V needs to provide energy for the synchronous MOSFET gate drive via the BP10V
capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in Equation 9.
(9)
SYNCHRONIZING TO AN EXTERNAL SUPPLY
The TPS4006x can be synchronized to an external clock through the SYNC pin. The SW node rises on the
falling edge of the SYNC signal. The synchronization frequency should be in the range of 20% to 30% higher
than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock
generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS4006x to freely run at the
frequency programmed by RT.
Internally, the SYNC pin has a pull-down current between 5 μA and 10 μA. In order to synchronize the device to
an external clock signal, the SYNC pin has to be overdriven from the external clock circuit. Normal logic gates or
an external MOSFET with a pull-up resistor of 10 kΩ is adequate.
Internally there is a delay of between approximately 50 ns and 100 ns from the time the SYNC pin is pulled low
and the HDRV signal goes low to turn on the upper MOSFET. Additionally, there is some delay as the MOSFET
gate charges to turn on the upper MOSFET, typically between 20 ns and 50 ns.
The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM
ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically
this is of concern under low-line conditions only. In any case, RKFF needs to be adjusted for the higher switching
frequency. In order to specify the correct value for RKFF at the synchronizing frequency, calculate a 'dummy'
value for RT that would cause the oscillator to run at the synchronizing frequency. Do not use this value of RT in
the design.
where:
• fSYNC is the synchronous frequency in kHz (10)
Use the value of RT(dummy) to calculate the value for RKFF.
where:
• RT(dummy) is in kΩ (11)
This value of RKFF ensures that UVLO is not engaged when operating at the synchronization frequency.
SELECTING THE INDUCTOR VALUE
The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current
at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but is
physically larger for the same load current. Too small an inductance results in larger ripple currents and a greater
number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good
compromise is to select the inductance value such that the converter doesn't enter discontinuous mode until the
load approximated somewhere between 10% and 30% of the rated output. The inductance value is described in
Equation 12.
where:
• VO is the output voltage
• ΔI is the peak-to-peak inductor current (12)
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPS40060 TPS40061
CO
LIOH
2
IOL
2
Vf
2
Vi
2
(F)
V2
Vf
2
Vi
2
Volts2
EC 12
CV2 (J)
I2 IOH
2
IOL
2 (Amperes)2
EL 12
LI2 (J)
V I ESR 1
8COfSW VPP
TPS40060
TPS40061
SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com
CALCULATING THE OUTPUT CAPACITANCE
The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any
output voltage deviation requirement during a load transient.
The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst case output
ripple is described in Equation 13.
(13)
The output ripple voltage is typically between 90% and 95% due to the ESR component.
The output capacitance requirement typically increases in the presence of a load transient requirement. During a
step load, the output capacitance must provide energy to the load (light to heavy load step) or absorb excess
inductor energy (heavy-to-light load step) while maintaining the output voltage within acceptable limits. The
amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the
inductor.
Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the
inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in
Equation 14 and Equation 15.
(14)
where:
where:
• IOH is the output current under heavy load conditions
• IOL is the output current under light load conditions (15)
Energy in the capacitor is given by the following equation:
(16)
where:
where:
• Vf is the final peak capacitor voltage
• Vi is the initial capacitor voltage (17)
By substituting Equation 15 into Equation 14, substituting Equation 17 into Equation 16, setting Equation 14
equal to Equation 16 and solving for CO yields the following equation.
(18)
Loop Compensation
Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS40060 and
TPS40061 use voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must
be included. The generic modulator gain is described in Figure 8.
14 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: TPS40060 TPS40061
fC
fSW
4
(Hertz)
BIAS
O
0.7 R1
R
V 0.7
´
= W
-
fZ 1
2ESRCO
(Hz)
fLC
1
2LCO
(Hz)
( )
( )
IN min IN(min)
MOD MOD dB
RAMP RAMP
V V
A or A 20 log
V V
æ ö æ ö
= ç ÷ = ´ ç ÷
ç ÷ ç ÷
è ø è ø
D
VO
VIN
VC
VS
or
VO
VC
VIN
VS
TPS40060
TPS40061
www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013
Duty cycle, D, varies from 0 to 1 as the control voltage, VC, varies from the minimum ramp voltage to the
maximum ramp voltage, VS. Also, for a synchronous buck converter, D = VO / VIN. To get the control voltage to
output voltage modulator gain in terms of the input voltage and ramp voltage,
(19)
With the voltage feedforward function, the ramp slope is proportional to the input voltage. Therefore, the
moderator DC gain is independent of the change of input voltage. For the TPS40060 and TPS40061 the
modulator dc gain is shown in Equation 20, with VIN(min) as the minimum input voltage required to cause the ramp
excursion to reach the maximum ramp amplitude of VRAMP.
(20)
Calculate the Poles and Zeros
For a buck converter using voltage mode control there is a double pole due to the output L-CO. The double pole
is located at the frequency calculated in Equation 21.
(21)
There is also a zero created by the output capacitance, CO, and its associated ESR. The ESR zero is located at
the frequency calculated in Equation 22.
(22)
Calculate the value of RBIAS to set the output voltage, VO.
(23)
The maximum crossover frequency (0 dB loop gain) is set by Equation 24.
(24)
Typically, fC is selected to be close to the midpoint between the L-CO double pole and the ESR zero. At this
frequency, the control to output gain has a –2 slope (-40 dB/decade), while the Type III topology has a +1 slope
(20 dB/decade), resulting in an overall closed loop –1 slope (–20 dB/decade). Figure 9 shows the modulator
gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated.
A Type III topology, shown in Figure 10, has two zero-pole pairs in addition to a pole at the origin. The gain and
phase boost of a Type III topology is shown in Figure 11. The two zeros are used to compensate the L-CO
double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide
controlled gain roll-off. In many cases the second pole can be eliminated and the amplifier's gain roll-off used to
roll-off the overall gain at higher frequencies.
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS40060 TPS40061
fC 1
2R1C2G
(Hertz)
fP1 1
2R2C2
(Hz) fP2 1
2R3C3
(Hz)
fZ1 1
2R2C1
(Hz) fZ2 1
2R1C3
(Hz)
RBIAS
UDG−02189
+
R1
R3
C3
C2
(optional)
C1 R2
7
8
VREF
COMP
VFB
VOUT
GAIN
180°
−90°
−270°
PHASE
+ 1
− 1
− 1
0 dB
MODULATOR GAIN
vs
SWITCHING FREQUENCY
ModulatorGain - dB
fSW - Switching Frequency - Hz
100 1 k 10 k 100 k
ESR Zero, + 1
LC Filter, - 2
AMOD = VIN(min) / VRAMP
Resultant, - 1 VC
PWM MODULATOR RELATIONSHIPS
VS
D = VC / VS
TPS40060
TPS40061
SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com
Figure 8. Figure 9.
Figure 10. Type III Compensation of Configuration Figure 11. Type III Compensation Gain and Phase
The poles and zeros for a type III network are described in Equation 25.
(25)
The value of R1 is somewhat arbitrary, but influences other component values. A value between 50kΩ and
100kΩ usually yields reasonable values.
The unity gain frequency is described in Equation 26.
where
• G is the reciprocal of the modulator gain at fC (26)
16 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: TPS40060 TPS40061
PSW(fsw) VINIOUTtSWfSW (Watts)
IRMS IOd AmperesRMS
PCOND IRMS
2
RDS(on)1TCRTJ25OC (W)
R2(MIN)
VC (max)
ISOURCE (min)
()
3.45 V
2.0 mA 1.725 k
AMOD(f) AMODfLC
fC
2
and G
1
AMOD(f)
TPS40060
TPS40061
www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013
The modulator gain as a function of frequency at fC, is described in Equation 27.
(27)
Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too
small. The error amplifier has a finite output source and sink current which must be considered when sizing R2.
Too small a value does not allow the output to swing over its full range.
(28)
dv/dt INDUCED TURN-ON
MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (VDS) applications. The turn-on is caused
by the capacitor divider that is formed by CGD and CGS. High dv/dt conditions and drain-to-source voltage, on the
MOSFET causes current flow through CGD and causes the gate-to-source voltage to rise. If the gate-to-source
voltage rises above the MOSFET threshold voltage, the MOSFET turns on, resulting in large shoot-through
currents. Therefore the SR MOSFET should be chosen so that the CGD capacitance is smaller than the CGS
capacitance. A 2-Ω to 5-Ω resistor in the upper MOSFET gate lead shapes the turn-on and dv/dt of the SW node
and helps reduce the induced turn-on.
HIGH-SIDE MOSFET POWER DISSIPATION
The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The
conduction losses are a function of the IRMS current through the MOSFET and the RDS(on) of the MOSFET. The
high-side MOSFET conduction losses are defined by Equation 29.
where:
• TCR is the temperature coefficient of the MOSFET RDS(on) (29)
The TCR varies depending on MOSFET technology and manufacturer but is typically ranges between 3500
ppm/°C and 1000 ppm/°C.
The IRMS current for the high side MOSFET is described in Equation 30.
(30)
The switching losses for the high-side MOSFET are described in Equation 31.
where:
• IO is the DC output current
• tSW is the switching rise time, typically < 20 ns
• fSW is the switching frequency (31)
Typical switching waveforms are shown in Figure 12.
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPS40060 TPS40061
PSR PDCPRRPCOND (W)
PRR 0.5QRRVINfSW (W)
PDC 2IOVFtDELAYfSW (W)
IRMS IO1d ARMS
PT PCONDPSW(fsw) (W)
PT
TJTA
JA
(W)
UDG-02179
DI
ANTI-CROSS
CONDUCTION
SYNCHRONOUS
RECTIFIER ON
BODY DIODE
CONDUCTION
BODY DIODE
CONDUCTION
HIGH SIDE ON
ID1
ID2
IO
SW
0
d 1-d
TPS40060
TPS40061
SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com
Figure 12. Inductor Current and SW Node Waveforms
The maximum allowable power dissipation in the MOSFET is determined by the following equation.
(32)
where:
(33)
and ΘJA is the package thermal impedance.
SYNCHRONOUS RECTIFIER MOSFET POWER DISSIPATION
The power dissipated in the synchronous rectifier MOSFET is comprised of three components: RDS(on) conduction
losses, body diode conduction losses, and reverse recovery losses. RDS(on) conduction losses can be found
using Equation 29 and the RMS current through the synchronous rectifier MOSFET is described in Equation 34.
(34)
The body-diode conduction losses are due to forward conduction of the body diode during the anti-cross
conduction delay time. The body diode conduction losses are described by Equation 35.
where:
• VF is the body diode forward voltage
• tDELAY is the delay time just before the SW node rises (35)
The 2-multiplier is used because the body-diode conducts twice during each cycle (once on the rising edge and
once on the falling edge)
The reverse recovery losses are due to the time it takes for the body diode to recovery from a forward bias to a
reverse blocking state. The reverse recovery losses are described in Equation 36.
where:
• QRR is the reverse recovery charge of the body diode (36)
The total synchronous rectifier MOSFET power dissipation is described in Equation 37.
(37)
18 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: TPS40060 TPS40061
( )
( )
( ) ( )
J A
Q
JA IN
SW
g
T T
I
V
f Hz
2 Q
æ é - ù ö
ç ê ú - ÷ ç êë q ´ úû ÷ = è ø
´
PT 2QgfSWIQVIN (W)
PT 2PD
VDR
IQVIN (W)
PD = Qg ´ VDR ´ fSW (W / driver)
TPS40060
TPS40061
www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013
TPS40060/TPS40061 POWER DISSIPATION
The power dissipation in the TPS40060 and TPS40061 is largely dependent on the MOSFET driver currents and
the input voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver
power (neglecting external gate resistance, (refer to the second reference in the REFERENCES section) can be
calculated from Equation 38.
(38)
And the total power dissipation in the device, assuming MOSFETs with similar gate charges for both the highside
and synchronous rectifier is described in Equation 39.
(39)
or
where:
• IQ is the quiescent operating current (neglecting drivers) (40)
The maximum power capability of the device's PowerPad package is dependent on the layout as well as air flow.
The thermal impedance from junction to air, assuming 2 oz. copper trace and thermal pad with solder and no air
flow.
ΘJA = 36.51°C/W
The maximum allowable package power dissipation is related to ambient temperature by Equation 36.
Substituting Equation 32 into Equation 40 and solving for fSW yields the maximum operating frequency for the
TPS40060 and TPS40061. The result is:
(41)
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
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TPS40060
TPS40061
SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com
LAYOUT CONSIDERATIONS
THE PowerPAD™ PACKAGE
The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. For
maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the
package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP
(PWP) package the dimensions of the circuit board pad are 5 mm x 3.4 mm. The dimensions of the package pad
are shown in Figure 13.
Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently
small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is
needed to prevent wicking the solder away from the interface between the package body and the solder-tinned
area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is
plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not
plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a
diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked
through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD Thermally
Enhanced Package (see REFERENCES section) for more information on the PowerPAD package.
Figure 13. PowerPAD Dimensions
MOSFET PACKAGING
MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions. In
general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance (θJA)
and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends on
proper layout and thermal management. The θJAspecified in the MOSFET data sheet refers to a given copper
area and thickness. In most cases, a thermal impedance of 40°C/W requires one square inch of 2-ounce copper
on a G-10/FR-4 board. Lower thermal impedances can be achieved at the expense of board area. Please refer
to the selected MOSFET's data sheet for more information regarding proper mounting.
GROUNDING AND CIRCUIT LAYOUT CONSIDERATIONS
The device provides separate signal ground (SGND) and power ground (PGND) pins. It is important that circuit
grounds are properly separated. Each ground should consist of a plane to minimize its impedance if possible.
The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor
(BP10), and the input capacitor should be connected to PGND plane at the input capacitor.
Sensitive nodes such as the FB resistor divider, RT, and ILIM should be connected to the SGND plane. The
SGND plane should only make a single point connection to the PGND plane.
20 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
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TPS40060
TPS40061
www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013
Component placement should ensure that bypass capacitors (BP10, BP5, and BPN10) are located as close as
possible to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not
be located near high dv/dt nodes such as HDRV, LDRV, BPN10, and the switch node (SW).
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: TPS40060 TPS40061
PSW(fsw) VINIOtSWfSW 55 V5 A20 ns130 kHz 0.715 W
PCOND 1.220.12(10.007(15025)) 0.324 W
IRMS IOd 50.0588 1.2 A
I IO20.2 520.2 2.0 A
fSW
0.0588
400 ns 147 kHz
1
TSW
fSW
VO(min)
VIN(max)
TON
VO(min)
VIN(max)
tON
TSW
or
dMIN
VO(min)
VIN(max)
0.0588 dMAX
VO(max)
VIN(min)
0.187
TPS40060
TPS40061
SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com
DESIGN EXAMPLE
• Input voltage: 18 VDC to 55 VDC
• Output voltage: 3.3 V ±2%
• Output current: 5 A (maximum, steady-state), 7 A (surge, 10-ms duration, 10% duty cycle maximum)
• Output ripple: 33 mVP-P at 5 A
• Output load response: 0.3 V => 10% to 90% step load change
• Operating temperature: –40°C to 85°C
• fSW = 130 kHz
1. Calculate maximum and minimum duty cycles
(42)
2. Select switching frequency
The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit
comparator. In order to maintain current limit capability, the on time of the upper MOSFET, tON, must be greater
than 330 ns (see Electrical Characteristics table). Therefore
(43)
(44)
Using 400 ns to provide margin,
(45)
Since the oscillator can vary by 10%, decrease fSW, by 10%
fSW = 0.9 × 147 kHz = 130 kHz
and therefore choose a frequency of 130 kHz.
3. Select ΔI
In this case ΔI is chosen so that the converter enters discontinuous mode at 20% of nominal load.
(46)
4. Calculate the high-side MOSFET power losses
Power losses in the high-side MOSFET (Si9407AGY) at 55-VIN where switching losses dominate can be
calculated from Equation 46 through Equation 49.
(47)
substituting Equation 47 into Equation 29 yields
(48)
and from Equation 31, the switching losses can be determined.
(49)
The MOSFET junction temperature can be found by substituting Equation 33 into Equation 32
22 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: TPS40060 TPS40061
RT 1
fSW17.82 E0623 k 408 k, use 412 k
(55 3.3) 3.3
L 11.9 H
55 2 130 kHZ
- ´
= = m
´ ´
J SR JA A ( ) T = P ´ q + T = 0.644 ´ 40 + 85 = 111°C
SR RR COND DC P = P ´P ´P = 0.107 + 0.485 + 0.052 = 0.644 W
PRR 0.5QRRVINfSW 0.530 nC55 V130 kHz 0.107 W
DC O FD DELAY SW P = 2´I ´ V ´ t ´ f = 2´ 5 A ´ 0.8 V ´ 50 ns ´130 kHZ = 0.052 W
( ( )) 2
COND P = 4.85 ´ 0.011´ 1+ 0.007 150 - 25 = 0.485 W
IRMS IO1d 510.0588 4.85 ARMS
TJ PCONDPSWJATA (0.3240.715)4085 127OC
TPS40060
TPS40061
www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013
(50)
5. Calculate synchronous rectifier losses
The synchronous rectifier MOSFET has two loss components, conduction, and diode reverse recovery losses.
The conduction losses are due to IRMS losses as well as body diode conduction losses during the dead time
associated with the anti-cross conduction delay.
The IRMS current through the synchronous rectifier from Equation 51
(51)
The synchronous MOSFET conduction loss from Equation 29 is:
(52)
The body diode conduction loss from Equation 35 is:
(53)
The body diode reverse recovery loss from Equation 36 is:
(54)
The total power dissipated in the synchronous rectifier MOSFET from Equation 37 is:
(55)
The junction temperature of the synchronous rectifier at 85°C is:
(56)
In typical applications, paralleling the synchronous rectifier MOSFET with a Schottky rectifier increases the
overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode
conduction and reverse recovery periods.
6. Calculate the Inductor Value
The inductor value is calculated from Equation 12.
(57)
A standard inductor value of 10-μH is chosen. A Coev DXM1306-10RO or Panasonic ETQPF102HFA could be
used.
7. Setting the switching frequency
The clock frequency is set with a resistor (RT) from the RT pin to ground. The value of RT can be derived from
following Equation 58, with fSW in kHz.
(58)
8. Programming the Ramp Generator Circuit
The PWM ramp is programmed through a resistor (RKFF) from the KFF pin to VIN. The ramp generator also
controls the input UVLO voltage. For an undervoltage level of 14.4V (20% below the 18 VIN(min)), RKFF is
calculated in Equation 59.
RKFF = (80%xVIN(min) – 3.5)(65.27 ×RT + 1502) Ω = 309 kΩ, use 301 kΩ (59)
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: TPS40060 TPS40061
fZ 1
20.012180 F
74 kHz
fLC
1
2 10 H180 F 3.7 kHz
AMOD(dB) = 20 ´log(9) = 19 dB
MOD
18
A 9
2
= =
RILIM 100.14
ISINK
VOS
ISINK
100.14
8.3 A
(50 mV)
8.3 A 175 k 174 k
ILIM
180 F3.3
1 m 7.0 7.6 A
CSS
2.3 A
0.7 V
1 ms 3.28 nF 3300 pF
33 mV 2.0ESR
1
8180 F130 kHz
33 mV 2.0ESR
1
8127 F130 kHz
CO
10 H5212
3.323.02 127 F
TPS40060
TPS40061
SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com
9. Calculating the Output Capacitance (CO)
In this example. the output capacitance is determined by the load response requirement of ΔV = 0.3 V for a 1 A
to 5 A step load. CO can be calculated using Equation 18.
(60)
Using Equation 13 calculate the ESR required to meet the output ripple requirements.
(61)
ESR = 8.9 mΩ
In order to get the required ESR, the capacitance needs to be greater than the 127-μF calculated. For example,
a single Panasonic SP capacitor, 180-μF with ESR of 12 mΩ can be used. Re-calculating the ESR required with
the new value of 180-μF is shown in Equation 62.
(62)
ESR = 11.1 mΩ
10. Calculate the Soft-Start Capacitor (CSS)
This design requires a soft-start time (tSTART) of 1 ms. CSS is calculated in Equation 63.
(63)
11. Calculate the Current Limit Resistor (RILIM)
The current limit set point depends on tSTART, VO, CO and ILOAD at start up as shown in Equation 7.
(64)
Set ILIM for 10.0 A minimum, then from Equation 7
(65)
12. Calculate Loop Compensation Values
Calculate the DC modulator gain (AMOD) from Equation 20.
(66)
(67)
Calculate the output poles and zeros from Equation 21 and Equation 22 of the L-C filter.
(68)
and
(69)
Select the close-loop 0 dB crossover frequency, fC. For this example fC = 10 kHz.
Select the double zero location for the Type III compensation network at the output filter double pole at 3.7 kHz.
Select the double pole location for the Type III compensation network at the output capacitor ESR zero at 73.7
kHz.
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CBP10V
QgSR
V
57 nC
0.5 114 nF
CBPN10
Qg
V
30 nC
0.5 60 nF
RBIAS 0.7 VR1
VO0.7 V
0.7 V100k
3.3 V0.7 V
26.9 k, choose 26.7 k
Z1
1 1
f C1 4301pF, choose 3900 pF
2 R2 C1 2 10 k 3.7 kHz
= \ = =
p´ ´ p´ W´
P1
1 1
f R2 9.82 k , choose 10 k
2 R2 C2 2 220 pF 73.7 kHz
= \ = = W W
p´ ´ p´ ´
C
1 1
f C2 196 pF, choose 220 pF
2 R1 C2 G 2 100 k 0.81 10 kHz
= \ = =
p´ ´ ´ p´ W´ ´
P2
1 1
f R3 4.59 k , choose 4.64 k
2 R3 C3 2 470 pF 73.7 kHz
= \ = = W W
p´ ´ p´ ´
fZ2 1
2R1C3
C3 1
2100 k3.7 kHz
430 pF, choose 470 pF
MOD(f )
1 1
G 0.81
A 1.23
= = =
2 2
LC
MOD(f ) MOD
C
f 3.7 kHz
A A 9 1.23
f 10 kHz
æ ö æ ö
= ´ ç ÷ = ´ ç ÷ =
è ø è ø
TPS40060
TPS40061
www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013
The amplifier gain at the crossover frequency of 10 kHz is determined by the reciprocal of the modulator gain
AMOD at the crossover frequency from Equation 27.
(70)
And also from Equation 27.
(71)
Choose R1 = 100 kΩ
The poles and zeros for a Type III network are described in Equation 25 and Equation 26.
(72)
(73)
(74)
(75)
(76)
Calculate the value of RBIAS from Equation 23 with R1 = 100 kΩ.
(77)
CALCULATING THE BPN10 AND BP10V BYPASS CAPACITANCE
The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount
of droop allowed on the bypass capacitor. The BPN10 capacitance, allowing for a 0.5-V droop on the BPN10 pin
from Equation 8 is shown in Equation 78.
(78)
and the BP10V capacitance from Equation 9 is shown in Equation 79.
(79)
For this application, a 0.1-μF capacitor was used for the BPN10V and a 1.0-μF was used for the BP10V bypass
capacitor. Figure 14 shows component selection for the 18-V through 55-V to 3.3-V at 5-A dc-to-dc converter
specified in the design example.
GATE DRIVE CONFIGURATION
Due to the possibility of dv/dt induced turn-on from the fast MOSFET switching times, high VDS voltage and low
gate threshold voltage of the Si4470, the design includes a 2-Ω in the gate lead of the upper MOSFET. The
resistor can be used to shape the low-to-high transition of the Switch node and reduce the tendency of dv/dtinduced
turn on.
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: TPS40060 TPS40061
5
13
12
16
15
1
2
3
KFF
RT
BP5
SGND
VIN
BPN10
SW
BP10
4
SYNC
11
ILIM
TPS40060PWP
6 SS/SD
7 VFB
8 COMP
HDRV 14
LDRV 10
PGND 9
+
−
+
−
PGND
RILIM
174 kΩ
0.1 μF
2 Ω
10 μH
Si4470
1.0 μF
Si9407
CO
180 μF
RT 412 kΩ
RKFF
301 kΩ
UDG−02161
0.1 μF
CSS
3300 pF
C1 3900 pF
R2
10 kΩ
R1
R3 100kΩ
4.64 kΩ
C2
220 pF
C3
470 pF
RSW
10 Ω
30BQ060
RBIAS
26.7 kΩ
VOUT
VIN
TPS40060
TPS40061
SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com
Figure 14. Design Example, 48 V to 3.3 V at 5 A dc-to-dc Converter
REFERENCES
1. Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas
Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM-1400 Topic 2.
2. PowerPAD Thermally Enhanced Package Texas Instruments, Semiconductor Group, Technical Brief: TI
Literature No. SLMA002
26 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: TPS40060 TPS40061
TPS40060
TPS40061
www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013
REVISION HISTORY
Changes from Revision E (June 2006) to Revision F Page
• Changed reference to Figure 13, PowerPad Dimensions, to Figure 14, Design Example, 48 V to 3.3 V at 5 A dc-todc
Converter ......................................................................................................................................................................... 7
• Changed both (CSS – 0.85 V) voltages to (VCSS – 0.85 V) in Programming Soft Start ....................................................... 10
• Changed turn-on (IL) to start-up (ILOAD) in the third paragraph of Programming Current Limit section. ............................. 11
• Changed first instance of BPN10 to BP10 in respective section title. ................................................................................ 11
• Added high-side before MOSFET in the Calculating the BP10 and BP10V Bypass Capacitor section ............................. 12
• Changed HDRV signal goes high to ...goes low in the Synchronizing to an External Supply section ............................... 13
• Added equation definition for fSYNC to Equation 10 ............................................................................................................. 13
• Deleted k from KΩ at the end of equation Equation 11 ...................................................................................................... 13
• Added (dummy) to RT in Equation 11 definition ................................................................................................................. 13
• Changed sequence of equation substitutions from: Equation 14 into Equation 13, Equation 16 into Equation 15,
Equation 13 equal to Equation 15, to: Equation 15 into Equation 14, Equation 17 into Equation 16, Equation 14
equal to Equation 16 ........................................................................................................................................................... 14
• Added generic before modulator gain in first paragraph of the Loop Compensation section ............................................ 14
• Deleted with VIN being the minimum input voltage required to cause the ramp excursion to cover the entire switching
period. from first paragraph of the Loop Compensation section ........................................................................................ 14
• Deleted previous Equation 19, which was AMOD = VIN / VS or AMOD(db) = 20 × log (VIN / VS ) ............................................. 14
• Changed figure reference for modulator gain in the Loop Compensation from Figure 6 (Typical Current Limit
Protection Waveforms) to Figure 8 (PWM MODULATOR RELATIONSHIPS) ................................................................... 14
• Added moderator DC gain and new Equation 20 to Loop Compensation section ............................................................. 15
• Changed VOUT to VOin sentence before and in Equation 23 .............................................................................................. 15
• Changed calculated in to set by in sentence before Equation 24 ...................................................................................... 15
• Changed VIN / VS to VIN(min) / VRAMP in the Modulator Gain vs Switching Frequency graph ............................................... 15
• Changed the TCR minimum value from 0.0035 to 3500 and the maximum from 0.010 to 10000 in the second
paragraph of the High-Side MOSFET Power Dissipation section ...................................................................................... 17
• Changed VDD to VIN in Equation 41 .................................................................................................................................... 19
• Changed PowerPAD Dimensions to include x and y axis values ....................................................................................... 20
• Added high-side MOSFET to step four title ........................................................................................................................ 22
• Changed reference to substituting Equation 30 to Equation 47 ......................................................................................... 22
• Deleted IRMS
2 × RDS(ON) from synchronous MOSFET conduction equation ........................................................................ 23
• Changed synchronous MOSFET conduction equation equals value from 0.10 to 0.485 ................................................... 23
• Changed body diode conduction equation values: 100 ns to 50 ns and 0.104 W to 0.052 W ........................................... 23
• Changed power dissipation equation values: 0.1 to 0.485, 0.104 to 0.052, 0.311 W to 0.644 W ..................................... 23
• Changed junction temperature equation values: (0.311) to 0.644, 97°C to 111°C ............................................................ 23
• Changed Step 6 reference to Equation 11 to Equation 12 ................................................................................................. 23
• Changed inductor value equation in Step 6: replaced value of 48 with 55 and 11.8 with 11.9 .......................................... 23
• Changed RKFF equation values in Step 8:133.7 to 309 kΩ, 133 to 301 kΩ ........................................................................ 23
• Added 80%x before VIN(min) in RKFF equation in Step 8 ....................................................................................................... 23
• Changed first ESR value in Step 9 from 12.7 to 8.9 mΩ .................................................................................................... 24
• Changed second ESR value in Step 9 from 13.8 to 11.1 mΩ ............................................................................................ 24
• Changed DC modulator gain values in both equations: 10 to 18, 5 to 9; (5.0) to 9, 14 to 19 dB ...................................... 24
• Changed AMOD crossover frequency equation values: 5 to 9, 0.68 to 1.23 ..................................................................... 25
• Changed gain (G) equation values: 0.68 to 1.23, 1.46 to 0.81 .......................................................................................... 25
• Changed poles and zeros equation values: Equation 73, 73.3 to 73.7 kHZ, 4.62 to 4.59 kΩ; Equation 74, 3.29 to
0.81, 1.46 to 10 kHZ, 109 to 196 pF, 100 to 220 pF; Equation 75, 100 to 200 pF, 73.3 to 73.7 kHz, 21.7 to 9.82 kΩ,
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 27
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SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com
21.5 to 10 kΩ; Equation 76, 21.5 to 10 kΩ, 2000 to 4301 pF, 1800 to 3900 pF ................................................................ 25
• Changed Design Example graphic to include new values from equation: 133 to 301 kΩ, 1800 to 3900 pF, 21.5 to 10
kΩ, 100 to 220 pF. Si9470 to Si9407 ................................................................................................................................. 25
• Added link references to hard-coded references throughout document ............................................................................. 26
28 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
TPS40060PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40060
TPS40060PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40060
TPS40060PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40060
TPS40060PWPRG4 ACTIVE HTSSOP PWP 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40060
TPS40061PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40061
TPS40061PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40061
TPS40061PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40061
TPS40061PWPRG4 ACTIVE HTSSOP PWP 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40061
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
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in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TPS40060PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS40061PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS40060PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0
TPS40061PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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Copyright © 2013, Texas Instruments Incorporated
TAS1020B
USB Streaming Controller
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLES025B
January 2002–Revised May 2011
TAS1020B
SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com
Contents
1 Introduction ........................................................................................................................ 9
1.1 Features ...................................................................................................................... 9
1.2 Description ................................................................................................................. 10
1.3 Functional Block Diagram ................................................................................................ 11
1.4 Ordering Information ...................................................................................................... 11
1.5 Terminal Assignments—Normal Mode ................................................................................. 12
1.6 Terminal Assignments—External MCU Mode ......................................................................... 12
1.7 Terminal Functions ........................................................................................................ 13
1.8 Device Operation Modes ................................................................................................. 15
1.9 Terminal Assignments for Codec Port Interface Modes .............................................................. 15
2 Detailed Description .......................................................................................................... 16
2.1 Architectural Overview .................................................................................................... 16
2.1.1 Oscillator and PLL .............................................................................................. 16
2.1.2 Clock Generator and Sequencer Logic ...................................................................... 16
2.1.3 Adaptive Clock Generator (ACG) ............................................................................. 16
2.1.4 USB Transceiver ................................................................................................ 16
2.1.5 USB Serial Interface Engine (SIE) ........................................................................... 16
2.1.6 USB Buffer Manager (UBM) .................................................................................. 17
2.1.7 USB Frame Timer .............................................................................................. 17
2.1.8 USB Suspend and Resume Logic ............................................................................ 17
2.1.9 MCU Core ....................................................................................................... 17
2.1.10 MCU Memory ................................................................................................... 17
2.1.11 USB Endpoint Configuration Blocks and Buffer Space .................................................... 17
2.1.12 DMA Controller .................................................................................................. 17
2.1.13 Codec Port Interface ........................................................................................... 18
2.1.14 I2C Interface ..................................................................................................... 18
2.1.15 General-Purpose IO Ports (GPIO) ........................................................................... 18
2.1.16 Interrupt Logic ................................................................................................... 18
2.1.17 Reset Logic ...................................................................................................... 18
2.2 Device Operation .......................................................................................................... 19
2.2.1 Clock Generation ............................................................................................... 19
2.2.2 Boot Process .................................................................................................... 19
2.2.2.1 EEPROM Boot Process ........................................................................... 19
2.2.2.2 Host Boot Process ................................................................................. 19
2.2.2.3 EEPROM Data Organization ..................................................................... 20
2.2.2.4 I2C Serial EEPROM ................................................................................ 21
2.2.2.5 DFU Upgrade Process ............................................................................ 22
2.2.2.6 Download Error Recovery ........................................................................ 22
2.2.2.7 ROM Support Functions .......................................................................... 22
2.2.3 USB Enumeration .............................................................................................. 23
2.2.4 TAS1020B USB Reset Logic .................................................................................. 23
2.2.5 USB Suspend and Resume Modes .......................................................................... 24
2.2.5.1 USB Suspend Mode ............................................................................... 24
2.2.5.2 USB Resume Mode ................................................................................ 25
2.2.5.3 USB Remote Wake-Up Mode .................................................................... 25
2 Contents Copyright © 2002–2011, Texas Instruments Incorporated
TAS1020B
www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011
2.2.6 Adaptive Clock Generator (ACG) ............................................................................. 26
2.2.6.1 Programmable Frequency Synthesizer ......................................................... 27
2.2.6.2 Capture Counter and Register ................................................................... 28
2.2.7 USB Transfers .................................................................................................. 29
2.2.7.1 Control Transfers ................................................................................... 29
2.2.7.2 Interrupt Transfers ................................................................................. 31
2.2.7.3 Bulk Transfers ...................................................................................... 32
2.2.7.4 Isochronous Transfers ............................................................................. 35
2.2.8 Microcontroller Unit ............................................................................................. 39
2.2.9 External MCU Mode Operation ............................................................................... 39
2.2.10 Interrupt Logic ................................................................................................... 39
2.2.11 General-Purpose I/O (GPIO) Ports ........................................................................... 45
2.2.11.1 Port 3 GPIO Bits ................................................................................... 47
2.2.11.2 Port 1 GPIO Bits ................................................................................... 48
2.2.11.3 Pullup Macro ........................................................................................ 48
2.2.12 DMA Controller .................................................................................................. 49
2.2.13 Codec Port Interface ........................................................................................... 49
2.2.13.1 General-Purpose Mode of Operation ............................................................ 50
2.2.13.2 Audio Codec (AC) '97 1.0 Mode of Operation ................................................. 57
2.2.13.3 Audio Codec (AC) '97 2.0 Mode of Operation ................................................. 58
2.2.13.4 Inter-IC Sound (I2S) Modes of Operation ....................................................... 59
2.2.13.5 AIC Mode of Operation ............................................................................ 61
2.2.13.6 Bulk Mode ........................................................................................... 61
2.2.14 I2C Interface ..................................................................................................... 62
2.2.14.1 Data Transfers ...................................................................................... 62
2.2.14.2 Single Byte Write ................................................................................... 63
2.2.14.3 Multiple Byte Write ................................................................................. 64
2.2.14.4 Single Byte Read ................................................................................... 64
2.2.14.5 Multiple Byte Read ................................................................................. 65
3 Electrical Specifications ..................................................................................................... 66
3.1 Absolute Maximum Ratings .............................................................................................. 66
3.2 Dissipation Ratings ........................................................................................................ 66
3.3 Recommended Operating Conditions .................................................................................. 66
3.4 Electrical Characteristics ................................................................................................. 66
3.5 Timing Characteristics .................................................................................................... 67
3.6 Clock and Control Signals ................................................................................................ 67
3.7 USB Signals When Sourced by TAS1020B ............................................................................ 67
3.8 Codec Port Interface Signals (AC ’97 Modes) ......................................................................... 68
3.9 Codec Port Interface Signals (I2S Modes) ............................................................................. 69
3.10 Codec Port Interface Signals (General-Purpose Mode) .............................................................. 69
3.11 I2C Interface Signals ...................................................................................................... 70
4 Application Information ...................................................................................................... 71
5 8K ROM ............................................................................................................................ 72
5.1 ROM Errata ................................................................................................................. 72
6 MCU Memory and Memory-Mapped Registers ....................................................................... 73
6.1 MCU Memory Space ...................................................................................................... 73
6.2 Internal Data Memory ..................................................................................................... 73
Copyright © 2002–2011, Texas Instruments Incorporated Contents 3
TAS1020B
SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com
6.3 External MCU Mode Memory Space .................................................................................... 75
6.4 USB Endpoint Configuration Blocks and Data Buffer Space ........................................................ 76
6.4.1 USB Endpoint Configuration Blocks ......................................................................... 76
6.4.2 Data Buffer Space .............................................................................................. 76
6.4.3 USB OUT Endpoint Configuration Bytes .................................................................... 80
6.4.3.1 USB OUT Endpoint - Y Buffer Data Count Byte (OEPDCNTYx) ............................ 80
6.4.3.2 USB OUT Endpoint - Y Buffer Base Address Byte (OEPBBAYx) ........................... 80
6.4.3.3 USB OUT Endpoint - X Buffer Data Count Byte (OEPDCNTXx) ............................ 81
6.4.3.4 USB OUT Endpoint - X and Y Buffer Size Byte (OEPBSIZx) ................................ 81
6.4.3.5 USB OUT Endpoint - X Buffer Base Address Byte (OEPBBAXx) ........................... 81
6.4.3.6 USB OUT Endpoint - Configuration Byte (OEPCNFx) ........................................ 82
6.4.4 USB IN Endpoint Configuration Bytes ....................................................................... 83
6.4.4.1 USB IN Endpoint - Y Buffer Data Count Byte (IEPDCNTYx) ................................ 83
6.4.4.2 USB IN Endpoint - Y Buffer Base Address Byte (IEPBBAYx) ............................... 84
6.4.4.3 USB IN Endpoint - X Buffer Data Count Byte (IEPDCNTXx) ................................ 84
6.4.4.4 USB IN Endpoint - X and Y Buffer Size Byte (IEPBSIZx) .................................... 84
6.4.4.5 USB IN Endpoint - X Buffer Base Address Byte (IEPBBAXx) ............................... 85
6.4.4.6 USB IN Endpoint - Configuration Byte (IEPCNFx) ............................................ 85
6.4.5 USB Control Endpoint Setup Stage Data Packet Buffer .................................................. 86
6.5 Memory-Mapped Registers .............................................................................................. 87
6.5.1 USB Registers .................................................................................................. 89
6.5.1.1 USB Function Address Register (USBFADR - Address FFFFh) ............................ 89
6.5.1.2 USB Status Register (USBSTA - Address FFFEh) ............................................ 90
6.5.1.3 USB Interrupt Mask Register (USBIMSK - Address FFFDh) ................................. 91
6.5.1.4 USB Control Register (USBCTL - Address FFFCh) ........................................... 91
6.5.1.5 USB Frame Number Register (Low Byte) (USBFNL - Address FFFBh) .................... 92
6.5.1.6 USB Frame Number Register (High Byte) (USBFNH - Address FFFAh) ................... 92
6.5.2 DMA Registers .................................................................................................. 92
6.5.2.1 DMA Time Slot Assignment Register (Low Byte) (DMATSL1 - Address FFF0h) (DMATSL0
- Address FFEAh) .................................................................................. 92
6.5.2.2 DMA Time Slot Assignment Register (High Byte) (DMATSH1 - Address FFEFh)
(DMATSH0 - Address FFE9h) ................................................................... 93
6.5.2.3 DMA Control Register (DMACTL1 - Address FFEEh) (DMACTL0 - Address FFE8h) .... 93
6.5.2.4 DMA Current Buffer Content Register (Low-Byte) (DMABCNT1L - Address FFF3h)
(DMABCNT0L- Address FFEBh) ................................................................. 93
6.5.2.5 DMA Current Buffer Content Register (High Byte) (DMABCNT1H - Address FFF4h)
(DMABCNT0H - Address FFECh) ............................................................... 94
6.5.2.6 DMA Bulk Packet Count Register (Low Byte) (DMABPCT0 - Address FFF2h) ........... 94
6.5.2.7 DMA Bulk Packet Count Register (High-byte) (DMABPCT1 - Address FFF1h) ........... 94
6.5.2.8 UBM Write Pointer (Low Byte) (Ch0WrPtrL - Address FFBCh) (Ch1WrPtrL - Address
FFB8h) .............................................................................................. 94
6.5.2.9 UBM Write Pointer (High Byte) (Ch0WrPtrH - Address FFBBh) (Ch1WrPtrH - Address
FFB7h) .............................................................................................. 95
6.5.2.10 DMA Read Pointer (Low Byte) (Ch0RdPtrL - Address FFBAh) (Ch1RdPtrL - Address
FFB6h) .............................................................................................. 95
6.5.2.11 DMA Read Pointer (High Byte) (Ch0RdPtrH - Address FFB9h) (Ch1RdPtrH - Address
FFB5h) .............................................................................................. 95
6.5.3 Adaptive Clock Generator Registers ......................................................................... 96
6.5.3.1 Adaptive Clock Generator1 Frequency Register (Byte 0) (ACG1FRQ0 - Address FFE7h)
4 Contents Copyright © 2002–2011, Texas Instruments Incorporated
TAS1020B
www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011
........................................................................................................ 96
6.5.3.2 Adaptive Clock Generator1 Frequency Register (Byte 1) (ACG1FRQ1 - Address FFE6h)
........................................................................................................ 96
6.5.3.3 Adaptive Clock Generator1 Frequency Register (Byte 2) (ACG1FRQ2 - Address FFE5h)
........................................................................................................ 96
6.5.3.4 Adaptive Clock Generator MCLK Capture Register (Low Byte) (ACGCAPL - Address
FFE4h) .............................................................................................. 97
6.5.3.5 Adaptive Clock Generator MCLK Capture Register (High Byte) (ACGCAPH - Address
FFE3h) .............................................................................................. 97
6.5.3.6 Adaptive Clock Generator2 Frequency Register (Byte 0) (ACG2FRQ0 - Address FFF9h)
........................................................................................................ 97
6.5.3.7 Adaptive Clock Generator2 Frequency Register (Byte 1) (ACG2FRQ1 - Address FFF8h)
........................................................................................................ 97
6.5.3.8 Adaptive Clock Generator2 Frequency Register (Byte 2) (ACG2FRQ2 - Address FFF7h)
........................................................................................................ 98
6.5.3.9 Adaptive Clock Generator2 Divider Control Register (ACG2DCTL - Address FFF6h) ... 98
6.5.3.10 Adaptive Clock Generator1 Divider Control Register (ACG1DCTL - Address FFE2h) ... 98
6.5.3.11 Adaptive Clock Generator Control Register (ACGCTL - Address FFE1h) ................. 99
6.5.4 Codec Port Interface Registers .............................................................................. 100
6.5.4.1 Codec Port Interface Configuration Register 1 (CPTCNF1 - Address FFE0h) ........... 100
6.5.4.2 Codec Port Interface Configuration Register 2 (CPTCNF2 - Address FFDFh) .......... 101
6.5.4.3 Codec Port Interface Configuration Register 3 (CPTCNF3 - Address FFDEh) .......... 102
6.5.4.4 Codec Port Interface Configuration Register 4 (CPTCNF4 - Address FFDDh) .......... 103
6.5.4.5 Codec Port Interface Control and Status Register (CPTCTL - Address FFDCh) ........ 104
6.5.4.6 Codec Port Interface Address Register (CPTADR - Address FFDBh) .................... 105
6.5.4.7 Codec Port Interface Data Register (Low Byte) (CPTDATL - Address FFDAh) ......... 105
6.5.4.8 Codec Port Interface Data Register (High Byte) (CPTDATH - Address FFD9h) ......... 105
6.5.4.9 Codec Port Interface Valid Time Slots Register (Low Byte) (CPTVSLL - Address FFD8h)
....................................................................................................... 106
6.5.4.10 Codec Port Interface Valid Time Slots Register (High Byte) (CPTVSLH - Address FFD7h)
....................................................................................................... 106
6.5.4.11 Codec Port Receive Interface Configuration Register 2 (CPTRXCNF2 - Address FFD6h)
....................................................................................................... 107
6.5.4.12 Codec Port Receive Interface Configuration Register 3 (CPTRXCNF3 - Address FFD5h)
....................................................................................................... 108
6.5.4.13 Codec Port Receive Interface Configuration Register 4 (CPTRXCNF4 - Address FFD4h)
....................................................................................................... 109
6.5.5 P3 Mask Register ............................................................................................. 109
6.5.5.1 P3 Mask Register (P3MSK - Address FFCAh) ............................................... 109
6.5.6 I2C Interface Registers ....................................................................................... 110
6.5.6.1 I2C Interface Address Register (I2CADR - Address FFC3h) ............................... 110
6.5.6.2 I2C Interface Receive Data Register (I2CDATI - Address FFC2h) ......................... 110
6.5.6.3 I2C Interface Transmit Data Register (I2CDATO - Address FFC1h) ....................... 110
6.5.6.4 I2C Interface Control and Status Register (I2CCTL - Address FFC0h) ................... 111
6.5.7 Miscellaneous Registers ..................................................................................... 112
6.5.7.1 USB OUT endpoint Interrupt Register (OEPINT - Address FFB4h) ....................... 112
6.5.7.2 USB IN endpoint Interrupt Register (IEPINT - Address FFB3h) ........................... 112
6.5.7.3 Interrupt Vector Register (VECINT - Address FFB2h) ....................................... 113
6.5.7.4 Global Control Register (GLOBCTL - Address FFB1h) ..................................... 114
6.5.7.5 Memory Configuration Register (MEMCFG - Address FFB0h) ............................. 114
Copyright © 2002–2011, Texas Instruments Incorporated Contents 5
TAS1020B
SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com
List of Figures
2-1 Adaptive Clock Generator Block Diagram .................................................................................... 27
2-2 TAS1020B Interrupt, Reset, Suspend, and Resume Logic ................................................................. 41
2-3 Activation of Setup Stage Transaction Overwrite Interrupt ................................................................. 43
2-4 GPIO Port 1 and Port 3 Functionality.......................................................................................... 46
2-5 Pull-Up Logic Symbol............................................................................................................ 48
2-6 Codec Port Interface Parameters − AC '97 1.0 .............................................................................. 53
2-7 Codec Port Interface Parameters − AIC ...................................................................................... 54
2-8 Codec Port Interface Parameters – I2S........................................................................................ 57
2-9 Byte Reversal Example ......................................................................................................... 57
2-10 Connection of the TAS1020B to an AC '97 Codec .......................................................................... 58
2-11 Connection of the TAS1020B to Multiple AC '97 Codecs................................................................... 59
2-12 Bit Transfer on the I2C Bus ..................................................................................................... 62
2-13 I2C START and STOP Conditions ............................................................................................. 63
2-14 TAS1020B Acknowledge on the I2C Bus...................................................................................... 63
2-15 Single Byte Write Transfer ...................................................................................................... 64
2-16 Multiple Byte Write Transfer .................................................................................................... 64
2-17 Single Byte Read Transfer ...................................................................................................... 64
2-18 Multiple Byte Read Transfer .................................................................................................... 65
3-1 External Interrupt Timing Waveform ........................................................................................... 67
3-2 USB Differential Driver Timing Waveform..................................................................................... 67
3-3 BIT_CLK and SYNC Timing Waveforms...................................................................................... 68
3-4 SYNC, SD_IN, and SD_OUT Timing Waveforms............................................................................ 68
3-5 I2S Mode Timing Waveforms ................................................................................................... 69
3-6 General-Purpose Mode Timing Waveforms .................................................................................. 69
3-7 SCL and SDA Timing Waveforms.............................................................................................. 70
3-8 Start and Stop Conditions Timing Waveforms................................................................................ 70
3-9 Acknowledge Timing Waveform................................................................................................ 70
4-1 Typical TAS1020B Device Connections....................................................................................... 71
6-1 Boot Loader Mode Memory Map............................................................................................... 75
6-2 Normal Operating Mode Memory Map ........................................................................................ 75
6-3 USB Endpoint Configuration Blocks and Buffer Space Memory Map..................................................... 77
6 List of Figures Copyright © 2002–2011, Texas Instruments Incorporated
TAS1020B
www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011
List of Tables
1-1 Terminal Functions—Normal Mode ........................................................................................... 13
1-2 Terminal Functions—External MCU Mode ................................................................................... 14
1-3 Operating Mode After Reset .................................................................................................... 15
1-4 Terminal Assignments for Codec Port Interface Modes..................................................................... 15
2-1 EEPROM Header ................................................................................................................ 21
2-2 AGC Control Registers .......................................................................................................... 27
2-3 ACG Frequency Registers ...................................................................................................... 28
2-4 Electrical Characteristics of Pullup Resistors................................................................................. 48
2-5 Terminal Assignments for Codec Port Interface General-Purpose Mode................................................. 50
2-6 Terminal Assignments for Codec Port Interface AC '97 1.0 Mode 2 ...................................................... 57
2-7 Terminal Assignments for Codec Port Interface AC '97 2.0 Mode 3 ...................................................... 58
2-8 Terminal Assignments for Codec Port Interface I2S Mode 4 and Mode 5 ................................................ 59
2-9 SLOT Assignments for Codec Port Interface I2S Mode 4................................................................... 60
2-10 SLOT Assignments for Codec Port Interface I2S Mode 5................................................................... 60
2-11 Terminal Assignments for Codec Port Interface AIC Mode 1 .............................................................. 61
6-1 USB Endpoint Configuration Blocks Address Map .......................................................................... 77
6-2 USB Control Endpoint Setup Data Packet Buffer Address Map ........................................................... 86
6-3 Memory-Mapped Registers Address Map .................................................................................... 87
Copyright © 2002–2011, Texas Instruments Incorporated List of Tables 7
TAS1020B
SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com
8 List of Tables Copyright © 2002–2011, Texas Instruments Incorporated
TAS1020B
www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011
USB Streaming Controller
Check for Samples: TAS1020B
1 Introduction
1.1 Features
1
• Universal Serial Bus (USB) • DMA Controller
– USB specification version 1.1 compatible – Two DMA channels to support streaming
– USB audio class specification 1.0 compatible USB audio data to/from the codec port
– Integrated USB transceiver interface
– Supports 12 Mb/s data rate (full speed) – Each channel can support a single USB
– Supports suspend/resume and remote isochronous endpoint
wake-up – In the I2S mode the device can support
– Supports control, interrupt, bulk, and DAC/ADCs at different sampling frequencies
isochronous data transfer type – A circular programmable FIFO used for
– Supports up to a total of seven IN endpoints isochronous audio data streaming
and seven OUT endpoints in addition to the • Codec Port Interface
control endpoint – Configurable to support AC '97 1.x, AC '97
– Data transfer type, data buffer size, single or 2.x, AIC, or I2S serial interface formats
double buffering is programmable for each – I2S modes can support a combination of one
endpoint stereo DAC and/or two stereo ADCs
– On-chip adaptive clock generator (ACG) – Can be configured as a general-purpose
supports asynchronous, synchronous and serial interface
adaptive synchronization modes for – Can support bulk data transfer using DMA
isochronous endpoints for higher throughput
– To support synchronization for streaming • I2C Interface
USB audio data, the ACG can be used to – Master only interface
generate the master clock for the codec – Does not support a multimaster bus
• Micro-Controller Unit (MCU) environment
– Standard 8052 8-bit core – Programmable to 100 kb/s or 400 kb/s data
– 8K bytes of program memory ROM that transfer speeds
contains a boot loader program and a library – Supports wait states to accommodate slow
of commonly used USB functions slaves
– 6016 bytes of program memory RAM which • General Characteristics
is loaded by the boot loader program – High performance 48-pin TQFP Package
– 256 bytes of internal data memory RAM – On-chip phase-locked loop (PLL) with
– Two GPIO ports internal oscillator is used to generate
– MCU handles all USB control, interrupt, and internal clocks from a 6 MHz crystal input
bulk endpoint transfers – Reset output available which is asserted for
both system and USB reset
– External MCU mode supports application
firmware development
– 8K ROM with boot loader program and
commonly used USB functions library
– 3.3 V core and I/O buffers
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2002–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TAS1020B
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1.2 Description
The TAS1020B integrated circuit (IC) is a universal serial bus (USB) peripheral interface device designed
specifically for applications that require isochronous data streaming. Applications include digital speakers,
which require the streaming of digital audio data between the host PC and the speaker system via the
USB connection. The TAS1020B device is fully compatible with the USB Specification Version 1.1 and the
USB Audio Class 1.0 Specification.
The TAS1020B uses a standard 8052 microcontroller unit (MCU) core with on-chip memory. The MCU
memory includes 8K bytes of program memory ROM that contains a boot loader program. At initialization,
the boot loader program downloads the application program code to a 6,016-byte RAM from either the
host PC or a nonvolatile memory on the printed-circuit board (PCB). The MCU handles all USB control,
interrupt and bulk endpoint transactions. DMA channels are provided to handle isochronous endpoint
transactions.
The USB interface includes an integrated transceiver that supports 12 Mb/s (full speed) data transfers. In
addition to the USB control endpoint, support is provided for up to seven IN endpoints and seven OUT
endpoints. The USB endpoints are fully configurable by the MCU application code using a set of endpoint
configuration blocks that reside in on-chip RAM. All USB data transfer types are supported.
The TAS1020B device also includes a codec port interface (C-Port) that can be configured to support
several industry standard serial interface protocols. These protocols include the audio codec (AC) '97
Revision 1.X, the AC '97 Revision 2.X and several inter-IC sound (I2S) modes.
A direct memory access (DMA) controller with two channels is provided for streaming the USB
isochronous data packets to/from the codec port interface. Each DMA channel can support one USB
isochronous endpoint.
An on-chip phase lock loop (PLL) and adaptive clock generator (ACG) provide support for the USB
synchronization modes, which include asynchronous, synchronous and adaptive.
Other on-chip MCU peripherals include an inter-IC control (I2C) serial interface, and two 8-bit
general-purpose input/output (GPIO) ports.
The TAS1020B device is implemented in a 3.3-V 0.25 μm CMOS technology.
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8052 Core
I2C
Control
8K ROM
6016 Byte RAM
USB Serial
OSC
PLL
ACG
Suspend
/Resume
Logic
I2C Bus
C−Port
Port−3 Port−1
USB
SOF
6 MHz
Interface
Engine
CODEC
Interface
1520
Byte
SRAM
UBM DMA
Global
Control/Status
Registers
TQFP
Texas Instruments
Package Type
Peripheral Device
Audio Solutions
48 pins PFB
T AS 1020B PFB
TAS1020B
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1.3 Functional Block Diagram
1.4 Ordering Information
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2 3
P1.1
P1.0
NC
DVDD
NC
P3.5
P3.4
P3.3
DVSS
P3.2/XINT
P3.1
P3.0
24
23
22
21
20
19
18
17
16
15
14
13
4
37
38
39
40
41
42
43
44
45
46
47
48
CSCLK
CDATO
MCLKO1
MCLKO2
RESET
VREN
SDA
SCL
AVSS
XTALO
XTALI
PLLFILI
5 6 7 8
P1.5
P1.4
P1.3
36 35 34 33 32 31 30
CDATI
CSYNC
CRESET
CSCHNE
DV
TEST
EXTEN
RSTO
MCLKI
PUR
DP
DM
MRESET
29 28 27 26
9 10 11 12
25
1
P1.2
P1.7
P1.6
DD
PLLFILO
AV
DVSS
DVDD
DD
DVSS
TAS1020B
2 3
MCUAD1
MCUAD0
MCURD
DVDD
MCUWR
MCUINTO
MCUALE
MCUA10
DVSS
XINT
MCUA9
MCUA8
24
23
22
21
20
19
18
17
16
15
14
13
4
37
38
39
40
41
42
43
44
45
46
47
48
CSCLK
CDATO
MCLKO1
MCLKO2
RESET
VREN
SDA
SCL
AVSS
XTALO
XTALI
PLLFILI
5 6 7 8
MCUAD4
MCUAD3
36 35 34 33 32 31 30
CDATI
CSYNC
CRESET
DV
TEST
EXTEN
RSTO
MCLKI
PUR
DP
DM
MRESET
29 28 27 26
9 10 11 12
25
1
MCUAD2
DD
PLLFILO
AV
DVSS
DVDD
DD
DVSS
TAS1020B
MCUAD5
MCUAD6
MCUAD7
CSCHNE
TAS1020B
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1.5 Terminal Assignments—Normal Mode
PFB PACKAGE (Normal Mode)
(TOP VIEW)
1.6 Terminal Assignments—External MCU Mode
PFB PACKAGE (External Mode)
(TOP VIEW)
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1.7 Terminal Functions
Table 1-1. Terminal Functions—Normal Mode
TERMINAL
I/O DESCRIPTION
NAME PIN TYPE NO.
AVDD Power 2 3.3-V analog supply voltage
AVSS Power 45 Analog ground
CSCLK CMOS 37 I/O Codec port interface serial clock: CSCLK is the serial clock for the codec port interface
used to clock the CSYNC, CDATO, CDATI, CRESET, AND CSCHNE signals.
CSYNC CMOS 35 I/O Codec port interface frame sync: CSYNC is the frame synchronization signal for the
codec port interface.
CDATO CMOS 38 O Codec port interface serial data out
CDATI CMOS 36 I Codec port interface serial data in
CRESET CMOS 34 O Codec port interface reset output (see Table 1-4 for alternate uses)
CSCHNE CMOS 32 I/O Codec port interface secondary channel enable (see Table 1-4 for alternate uses)
DP CMOS 6 I/O USB differential pair data signal plus. DP is the positive signal of the bidirectional USB
differential pair used to connect the TAS1020B device to the universal serial bus.
DM CMOS 7 I/O USB differential pair data signal minus. DM is the negative signal of the bidirectional
USB differential pair used to connect the TAS1020B device to the universal serial bus.
DVDD Power 8, 21, 33 3.3-V digital supply voltage
DVSS Power 4, 16, 28 Digital ground
EXTEN CMOS 11 I External MCU mode enable: Input used to enable the device for the external MCU
mode
MCLKI CMOS 3 I Master clock input. An input that can be used as the master clock for the codec port
interface or the source for MCLKO2.
MCLKO1 CMOS 39 O Master clock output 1: The output of the ACG that can be used as the master clock for
the codec port interface and the codec.
MCLKO2 CMOS 40 O Master clock output 2: An output that can be used as the master clock for the codec
port interface and the codec used in I2S modes for receive. This clock signal can also
be used as a miscellaneous clock.
MRESET CMOS 9 I Master reset: An active low asynchronous reset for the device that resets all logic to
the default state
NC 20,22 Not used
P1.[0:7] CMOS 23, 24, 25, I/O General-purpose I/O port [bits 0 through 7]: A bidirectional 8-bit I/O port with an internal
26, 27, 29, 100-μA active pullup
30, 31
P3.[0:5] CMOS 13, 14, 15, I/O General-purpose I/O port [bits 0 through 5]: A bidirectional I/O port with an internal
17, 18, 19 100-μA active pullup
PLLFILI CMOS 48 I PLL loop filter input: Input to on-chip PLL from external filter components
PLLFILO CMOS 1 O PLL loop filter output: Output from on-chip PLL to external filter components
PUR CMOS 5 O USB data signal plus pullup resistor connect. PUR is used to connect the pullup
resistor on the DP signal from a high-impedance state to 3.3 V. When the DP signal is
connected to 3.3-V the host PC detects the connection of the TAS1020B device to the
universal serial bus.
RESET CMOS 41 O General-purpose active-low output which is memory mapped
RSTO CMOS 12 O Reset output: An output that is active while the master reset input or the USB reset is
active
SCL CMOS 44 O I2C interface serial clock
SDA CMOS 43 I/O I2C interface serial data
TEST CMOS 10 I Test mode enable: Factory test mode
VREN CMOS 42 O General-purpose active-low output which is memory mapped
XINT CMOS 15 I External interrupt: An active low input used by external circuitry to interrupt the on-chip
8052 MCU
XTALI CMOS 47 I Crystal input: Input to the on-chip oscillator from an external 6-MHz crystal
XTALO CMOS 46 O Crystal Output: Output from the on-chip oscillator to an external 6-MHz crystal
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Table 1-2. Terminal Functions—External MCU Mode
TERMINAL
I/O DESCRIPTION
NAME PIN TYPE NO.
AVDD Power 2 - 3.3-V Analog supply voltage
AVSS Power 45 - Analog ground
CSCLK CMOS 37 I/O Codec port interface serial clock: CSCLK is the serial clock for the codec port interface
used to clock the CSYNC, CDATO, CDATI, CRESET AND CSCHNE signals.
CSYNC CMOS 35 I/O Codec port interface frame sync: CSYNC is the frame synchronization signal for the
codec port interface.
CDATO CMOS 38 O Codec port interface serial data output
CDATI CMOS 36 I Codec port interface serial data input
CRESET CMOS 34 O Codec port interface reset output (see Table 1-4 for alternate uses)
CSCHNE CMOS 32 I/O Codec port interface secondary channel enable (see Table 1-4 for alternate uses)
DP CMOS 6 I/O USB differential pair data signal plus: DP is the positive signal of the bidirectional USB
differential pair used to connect the TAS1020B device to the universal serial bus.
DM CMOS 7 I/O USB differential pair data signal minus. DM is the negative signal of the bidirectional
USB differential pair used to connect the TAS1020B device to the universal serial bus.
DVDD Power 8, 21, 33 - 3.3-V Digital supply voltage
DVSS Power 4, 16, 28 - Digital ground
EXTEN CMOS 11 I External MCU mode enable: Input used to enable the device for the external MCU
mode. This signal uses a 3.3 V TTL/LVCMOS input buffer.
MCLKI CMOS 3 I Master clock input: An input that can be used as the master clock for the codec port
interface or the source for MCLKO2.
MCLKO1 CMOS 39 O Master clock output 1: The output of the ACG that can be used as the master clock for
the codec port interface and the codec.
MCLKO2 CMOS 40 O Master clock output 2: An output that can be used as the master clock for the codec
port interface and the codec. This clock signal can also be used as a miscellaneous
clock.
MRESET CMOS 9 I Master reset: An active low asynchronous reset for the device that resets all logic to
the default state.
MCUAD [0:7] CMOS 23, 24, 25, I/O MCU multiplexed address/data: Multiplexed address bits[0:7]/data bits[0:7] for external
26, 27, 29, MCU access to the TAS1020B external data memory space.
30, 31
MCUA [8:10] CMOS 13, 14, 17 I/O MCU address bus: Multiplexed address bus bits[8:10] for external MCU access to the
TAS1020B external data memory space.
MCUALE CMOS 18 I MCU address latch enable: Address latch enable for external MCU access to the
TAS1020B external data memory space.
MCUINTO CMOS 19 O MCU interrupt output: Interrupt output to be used for external MCU INTO input signal.
All internal TAS1020B interrupt sources are read together to generate this output
signal.
MCUWR CMOS 20 I MCU write strobe: Write strobe for external MCU write access to the TAS1020B
external data memory space.
MCURD CMOS 22 I MCU read strobe: Read strobe for external MCU read access to the TAS1020B
external data memory space.
PLLFILI CMOS 48 I PLL loop filter input: Input to on-chip PLL from external filter components.
PLLFILO CMOS 1 O PLL loop filter output: Output to on-chip PLL from external filter components.
PUR CMOS 5 O USB data signal plus pullup resistor connect. PUR is used to connect the pullup
resistor on the DP signal to 3.3V from a high-impedance state. When the DP signal is
connected in a 3.3-V state, the host PC should detect the connection of the TAS1020B
device to the universal serial bus.
RESET CMOS 41 O General-purpose active-low output which is memory mapped
RSTO CMOS 12 O Reset output: An output that is active while the master reset input or the USB reset is
active.
SCL CMOS 44 O I2C interface serial clock
SDA CMOS 43 I/O I2C interface serial data input/output
TEST CMOS 10 I Test mode enable: Factory text mode
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Table 1-2. Terminal Functions—External MCU Mode (continued)
TERMINAL
I/O DESCRIPTION
NAME PIN TYPE NO.
VREN CMOS 42 O General-purpose active-low output which is memory mapped.
XINT CMOS 15 I External interrupt: An active low input used by external circuitry to interrupt the on-chip
8052 MCU.
XTALI CMOS 47 I Crystal input: Input to the on-chip oscillator from an external 6-MHz crystal.
XTALO CMOS 46 O Crystal output: Output from the on-chip oscillator to an external 6-MHz crystal.
1.8 Device Operation Modes
The EXTEN and TEST pins define the mode that the TAS1020B is in after reset.
Table 1-3. Operating Mode After Reset
MODE EXTEN TEST
Normal mode - internal MCU 0 0
External MCU mode 1 0
Factory test 0 1
Factory test 1 1
1.9 Terminal Assignments for Codec Port Interface Modes
The codec port interface has five modes of operation that support AC '97, I2S, and AIC codecs. There is
also a general-purpose mode that is not specific to a serial interface. The mode is programmed by writing
to the mode select field of the codec port interface configuration register 1 (CPTCNF1). The codec port
interface terminals CSYNC, CSCLK, CDATO, CDATI, CRESET, and CSCHNE take on functionality
appropriate to the mode programmed as shown in the following table.
Table 1-4. Terminal Assignments for Codec Port Interface Modes(1) (2) (3)
TERMINAL GP AIC AC '97 v1.x AC '97 v2.x I2S I2S
NO. NAME Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5
35 CSYNC CSYNC I/O FS O SYNC O SYNC O LRCK O LRCK1 O
37 CSCLK CSCLK I/O SCLK O BIT_CLK I BIT_CLK I SCLK O SCLK1 O
38 CDATO CDATO O DOUT O SD_OUT O SD_OUT O SDOUT1 O SDOUT1 O
36 CDATI CDATI I DIN I SD_IN I SD_IN1 I SDIN1 I SDIN2 I
34 CRESET CRESET O RESET O RESET O RESET O CRESET O SCLK2 O
32 CSCHNE NC O FC O NC O SD_IN2 I SDIN2 I LRCK2 O
(1) Signal names and I/O direction are with respect to the TAS1020B device. The signal names used for the TAS1020B terminals for the
various codec port interface modes reflect the nomenclature used by the codec devices.
(2) NC indicates no connection for the terminal in a particular mode. The TAS1020B device drives the signal as an output for these cases.
(3) The CSYNC and CSCLK signals can be programmed as either an input or an output in the general-purpose mode.
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2 Detailed Description
2.1 Architectural Overview
2.1.1 Oscillator and PLL
Using an external 6-MHz crystal, the TAS1020B derives the fundamental 48-MHz internal clock signal
using an on-chip oscillator and PLL. Using the PLL output, the other required clock signals are generated
by the clock generator and adaptive clock generator.
2.1.2 Clock Generator and Sequencer Logic
Utilizing the 48-MHz output from the PLL, the clock generator logic generates all internal clock signals,
except for the codec port interface master clock (MCLK) and serial clock (CSCLK) signals. The TAS1020B
internal clocks include the 48-MHz clock, a 24-MHz clock, and a 12-MHz clock. A 12 MHz USB clock is
also generated. The USB clock is the same as the internal 12-MHz clock when the TAS1020B is
transmitting data, but is derived from the data when the TAS1020B is receiving data. To derive the USB
clock when receiving USB data, the TAS1020B utilizes an internal digital PLL (DPLL) driven from the
48-MHz clock.
The sequencer logic controls the access to the SRAM used for the USB endpoint configuration blocks and
the USB endpoint buffer space. The SRAM can be accessed by the MCU, the USB buffer manager
(UBM), or the DMA channels. The sequencer controls the access to the memory using a round-robin fixed
priority arbitration scheme. This means that the sequencer logic generates grant signals for the MCU,
UBM, and DMA channels at a predetermined fixed frequency.
2.1.3 Adaptive Clock Generator (ACG)
The adaptive clock generator is used to generate a master clock output signal (MCLKO) to be used by the
codec port interface and the codec device. To synchronize data sent to or received from the codec to the
USB frame rate, the MCLKO signal generated by the adaptive clock generator must be used. The
synchronization of the MCLKO signal to the USB frame rate is achieved by the ACG, which, in turn, is
controlled by a soft PLL, implemented in the MCU. One of the tasks performed by the ACG is to maintain
count of the number of MCLKO clocks between USB Start of Frame (SOF) events. This count is
monitored by the soft PLL in the MCU. Based on this count, the soft PLL outputs corrections to the ACG
to adjust MCLKO to obtain the correct number of MCLKO clocks between USB SOF events.
MCLKI, the master clock input, can also be selected to source the clocks used by the codec port interface.
When MCLKI is selected, it is used to derive the TAS1020B-sourced versions of the clocks CSCLK and
CSYNC. In this scenario, the codec device would also use the same master clock signal (MCLKI).
2.1.4 USB Transceiver
The TAS1020B provides an integrated transceiver for the USB port. The transceiver includes a differential
output driver, a differential input receiver, and two single ended input buffers. The transceiver connects to
the USB DP and DM signal terminals.
2.1.5 USB Serial Interface Engine (SIE)
The serial interface engine logic manages the USB packet protocol for packets being received and
transmitted by the TAS1020B. For packets being received, the SIE decodes the packet identifier field
(PID) to determine the type of packet being received and to ensure the PID is valid. The SIE then
calculates the cycle redundancy check (CRC) of the received token and data packets and compares the
value to the CRC contained in the packet to verify that the packet was not corrupted during transmission.
For transmitted token and data packets, the SIE generates the CRC that is transmitted with the packet.
The SIE also generates the synchronization field (SYNC) and the correct PID for all transmitted packets.
Another major function of the SIE is the serial-to-parallel conversion of received data packets and the
parallel-to-serial conversion of transmitted data packets.
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2.1.6 USB Buffer Manager (UBM)
The USB buffer manager provides the control logic that interfaces the SIE to the USB endpoint buffers.
One of the major functions of the UBM is to decode the USB function address to determine if the host PC
is addressing the TAS1020B device USB peripheral function. In addition, the endpoint address field and
direction signal are decoded to determine which particular USB endpoint is being addressed. Based on
the direction of the USB transaction and the endpoint number, the UBM will either write or read the data
packet to or from the appropriate USB endpoint data buffer.
2.1.7 USB Frame Timer
The USB frame timer logic receives the start of frame (SOF) packet from the host PC each USB frame.
Each frame, the logic stores the 11-bit frame number value from the SOF packet in a register and asserts
the internal SOF signal. The frame number register can be read by the MCU and the value can be used
as a time stamp. For USB frames in which the SOF packet is corrupted or not received, the frame timer
logic will generate a pseudo start of frame (PSOF) signal and increment the frame number register.
2.1.8 USB Suspend and Resume Logic
The USB suspend and resume logic detects suspend and resume conditions on the USB. This logic also
provides the internal signals used to control the TAS1020B device when these conditions occur. The
capability to resume operation from a suspend condition with a locally generated remote wake-up event is
also provided.
2.1.9 MCU Core
The TAS1020B uses an 8-bit microcontroller core that is based on the industry standard 8052. The MCU
is software compatible with the 8052, 8032, 80C52, 80C53, and 87C52 MCUs. The 8052 MCU is the
processing core of the TAS1020B and handles all USB control, interrupt and bulk endpoint transfers. Bulk
out end-point transfers can also be handled by one of the two DMA channels.
2.1.10 MCU Memory
In accordance with the industry standard 8052, the TAS1020B MCU memory is organized into program
memory, external data memory and internal data memory. A boot ROM program is used to download the
application code to a 6K byte RAM that is mapped to the program memory space. The external data
memory includes the USB endpoint configuration blocks, USB data buffers, and memory mapped
registers. The total external data memory space available is 1.5K bytes. A total of 256 bytes are provided
for the internal data memory.
2.1.11 USB Endpoint Configuration Blocks and Buffer Space
The USB endpoint configuration blocks are used by the MCU to configure and operate the required USB
endpoints for a particular application. In addition to the control end-point, the TAS1020B supports a total of
seven IN endpoints and seven OUT endpoints. A set of six bytes is provided for each endpoint to specify
the endpoint type, buffer address, buffer size, and data packet byte count.
The USB endpoint buffer configuration blocks and buffer space provided totals 1440 bytes. The buffer
space to be used by a particular endpoint is fully configurable by the MCU for a particular application.
Therefore, the MCU can configure each buffer based on the total number of endpoints to be used, the
maximum packet size to be used for each endpoint, and the selection of single or double buffering.
2.1.12 DMA Controller
Two DMA channels are provided to support the streaming of data for USB isochronous IN endpoints,
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isochronous OUT endpoints, and bulk OUT endpoints. Each DMA channel can support one USB
isochronous IN endpoint, or one isochronous OUT endpoint, or one bulk OUT endpoint. The DMA
channels are used to stream data between the USB endpoint data buffers and the codec port interface.
The USB endpoint number and direction can be programmed for each DMA channel. Also, the codec port
interface time slots to be serviced by each DMA channel can be programmed.
2.1.13 Codec Port Interface
The TAS1020B provides a configurable full duplex bidirectional serial interface that can be used to
connect to a codec or other external device types for streaming USB isochronous data. The interface can
be configured to support several different industry standard protocols, including AC '97 1.x, AC '97 2.x,
AIC, and I2S. The TAS1020B also has a general-purpose mode to support other protocols.
2.1.14 I2C Interface
The I2C interface logic provides a two-wire serial interface that the 8052 MCU can use to access other
ICs. The TAS1020B is an I2C master device only and supports single byte or multiple byte read and write
operations. The interface can be programmed to operate at either 100 kbps or 400 kbps. In addition, the
protocol supports 8-bit or 16-bit addressing for accessing the I2C slave device memory locations. The
TAS1020B supports I2C wait states. This means slaves can assert wait state on the I2C bus by pulling the
SCL line low.
2.1.15 General-Purpose IO Ports (GPIO)
The TAS1020B provides two general-purpose IO ports that are controlled by the internal 8052 MCU. The
two ports are port 1 and port 3. Port 1 provides true GPIO capability. Each bit of port 1 can be
independently used as either an input or output, and consists of an output buffer, an input buffer, and a
pullup resistor(4). Some of the bits of port 3 also provide true GPIO capability, but, in addition, some of the
bits of port 3 also provide alternate input and output uses. An example of this is P3.2, which is used as the
external interrupt (XINT) input to the TAS1020B. A detailed description of the alternate uses of some of
the port 3 bits is presented in Section 2.2.11.
The pullup resistors for port 1 and port 3 can be disabled by bits P1PUDIS and P3PUDIS respectively in
the on-chip register GLOBCTL. In addition, any port 3 pin can be used to wake up the host PC from a
low-power suspend mode.
2.1.16 Interrupt Logic
The interrupt logic monitors the various conditions that can cause an interrupt and asserts the interrupt 0
(INTO) input on the 8052 MCU core accordingly. All of the TAS1020B internal interrupt sources and the
external interrupt (XINT) input are ORed together to generate the INT0 signal. An interrupt vector register
is used by the MCU to identify the interrupt source.
2.1.17 Reset Logic
An external master reset (MRESET) input signal that is asynchronous to the internal clocks can be used to
reset the TAS1020B logic. In addition to this master reset, the TAS1020B logic can also be reset by a
USB reset from the host PC if bit FRSTE in the on-chip register USBCTL is set to 1. The TAS1020B also
provides a reset output (RSTO) signal that can be used by external devices. This signal is asserted when
either a master reset occurs or when a USB reset occurs and FRSTE is set to 1.
(4) The pullup resistors are not implemented as true resistors, but rather as switchable current sources (see Section 2.2.11.3).
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2.2 Device Operation
The operation of the TAS1020B is explained in the following sections. For additional information on USB,
refer to the Universal Serial Bus Specification, Version 1.1.
2.2.1 Clock Generation
The TAS1020B requires an external 6-MHz crystal with load capacitors and PLL loop filter components to
derive all the clocks needed for both USB and codec operation. Figure 4-1 shows the connection of these
components to the TAS1020B. Figure 4-1 also shows a ground shield residing on the top layer of the PCB
and underneath the crystal and its load capacitors and the PLL components. The PLL is an analog PLL,
and noise pickup in these components can translate to phase jitter at the output of the PLL, which in turn
can translate to distortion at the codec. A ground shield is recommended to attenuate the digital noise
components on the board as seen at the PLL.
The AVSS and AVDD pins on the TAS1020B are used exclusively to power the analog PLL. To maintain
isolation from the digital noise residing on a board, AVSS should be a separate ground plane that connects
to the primary ground plane (DGND) at a single point via a ferrite bead. The ferrite bead should exhibit
around 9 Ω of impedance at 100 MHz. AVDD should also be distinct from DVDD. A recommended
architecture is to generate DVDD and AVDD from the same regulator line, with each derived from a RC filter
in series with the regulator output. It is finally recommended that the ground shield for the crystal and its
load capacitors and the PLL loop filter components be connected to AVSS at a single point via a ferrite
bead of the same type as above.
Using the low frequency 6-MHz crystal and generating the required higher frequency clocks internally in
the TAS1020B is a major advantage with regard to EMI.
2.2.2 Boot Process
The TAS1020B can boot from EEPROM or execute a host boot. Host boot will be used in the following
circumstances:
• No EEPROM is present.
• An EEPROM is present, but does not contain a valid header.
• An EEPROM is present, but is a device EEPROM (contains header information only).
2.2.2.1 EEPROM Boot Process
If the target device has an application EEPROM (an EEPROM that contains both header and application
data), and if the header portion of the EEPROM content is valid, the EEPROM application code is
downloaded to on-chip RAM. During the download process, the RAM is mapped to data space, and the
boot code that orchestrates the download is part of the on-chip firmware housed in on-chip ROM. Also,
while the application code is being downloaded, the TAS1020B remains disconnected from the USB bus.
When the download is complete, the firmware sets the ROM disable bit SDW. The setting of this bit maps
the RAM from data space to program space, starting address 0x0000. Having set bit SDW, the firmware
then branches to address 0x0000, which is the reset entry point for the application code. The application
code is now running.
The application code then switches on the PUR output. The PUR output pin is connected, through
external circuitry (see Figure 4-1), to the positive (DP) line of the differential USB bus. Switching PUR on
informs the host that a full speed (12 Mb/s) device is present on the bus. In the enumeration procedure
that follows, the application code reports its run-time device descriptor set. Following enumeration, the
device is actively running its application.
2.2.2.2 Host Boot Process
The DFU code in the TAS1020B fully adheres to the USB Device Class Specification for DFU 1.0. In
addition, the TAS1020B utilizes the communication protocols from the DFU specification to implement a
host boot capability for those applications that do not have an EEPROM resource. In such cases, the
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TAS1020B, at power-up, reports its DFU mode descriptor set rather than its run-time descriptor set and
directly enters what the DFU specification terms the DFU Program Mode. The host processor must be
cognizant of the fact that the device under enumeration does not have an EEPROM resource with valid
code, and is already in the DFU mode awaiting a download per the DFU protocol. All of this capability is
provided by the ROM-based code (firmware) that resides on the TAS1020B.
Specifically, the host boot process addresses three cases—an EPROM is not present, an EEPROM is
present but the data in the EEPROM is invalid, or an EEPROM is present but the EEPROM is a device
EEPROM (contains only header data). In all three of these cases, the TAS1020B firmware comes up in
the DFU Program Mode. A host boot ensues, but the final destination of the download depends on the
status of the onboard EEPROM.
a. If the firmware determines that no EEPROM is present (by noting, when addressing the EEPROM, the
absence of an acknowledge from the EEPROM), a Vendor ID of 0xFFFF and a Product ID of 0xFFFE
is reported during enumeration. The download that follows enumeration is written to the on-chip RAM.
The download from the host must include a header (see Section 2.2.2.3.1), and the header overwrite
bit in the header downloaded must be set to 0. (The header overwrite bit is used to instruct the
TAS1020B firmware as to whether or not the header portion of the download is to be written into the
EEPROM. Since, in this case, no EEPROM is present, this header overwrite bit must be set to 0). It is
noted that the host must have prior knowledge that the target will initialize in the DFU program mode
and will require a download of application code (and header) to RAM.
b. If the firmware determines that an EEPROM is present (acknowledges are received from the
EEPROM), but that the header data in the EEPROM is invalid, a Vendor ID of 0xFFFF and a Product
ID of 0xFFFE is reported during enumeration. The download that follows enumeration is written to
EEPROM. Since the EEPROM data was invalid, the host has to set the header overwrite bit in the
header portion of the download to a 1 to ensure that the header is written to the EEPROM. It is noted
that the host must have prior knowledge that the target does have an EEPROM, but that the data in
the EEPROM is invalid. This could be a situation such as the initial download of the application on a
production line.
c. If the firmware determines that an EEPROM is present, that the header data in the EEPROM is valid,
but that the header data in the EEPROM indicates that the EEPROM is a device EEPROM, the Vendor
ID and Product ID settings in the EEPROM-resident header is reported during enumeration. In
addition, the strings in the header, if applicable, are reported. The EEPROM download that follows
enumeration will be written to the on-chip RAM facility. In addition to downloading the application code
to RAM, an option also exists to download the header portion of the download image to the EEPROM.
If the host does not wish to overwrite the valid header data in the EEPROM, it must set the header
overwrite bit in its download header to a 0. It is noted that the host must have knowledge that the
target contains an EEPROM, and that the EEPROM is a device EEPROM.
2.2.2.3 EEPROM Data Organization
Two types of data can be stored in the EEPROM—header data, which contains USB device information,
and application code.
During boot, if no header or invalid header data is found in the EEPROM, paragraph (b) in Section 2.2.2.2
applies.
During boot, if a valid header is found in the EEPROM, and the header indicates that the Data Type is an
Application, then the application is loaded from the EEPROM and execution is passed to it.
During boot, if a valid header is found in the EEPROM, and the header indicates that the Data Type is a
Device, then paragraph (c) in Section 2.2.2.2 applies.
2.2.2.3.1 EEPROM Header
Table 2-1 shows the format and information contained it the header data. As seen from Table 2-1, the
header data begins at address 0x0000 in the EEPROM and precedes the application code.
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Table 2-1. EEPROM Header
OFFSET TYPE SIZE VALUE
0 headerChksum 1 Header check sum—derived by adding the header data, excluding the header checksum, in bytes, and retaining the lower byte of the sum as the checksum.
1 HeaderSize 1 Size, in units of bytes, of the header including strings if applied
2 Signature 2 Signature: 0x1234
4 VendorID 2 USB Vendor ID
6 ProductID 2 USB Product ID
8 ProductVersion 1 Product version
9 FirmwareVersion 1 Firmware version
USB attributes:
Bit 0: If set to 1, the header includes all three strings: language, manufacture, and product
strings, if set to 0, the header does not include any string. The strings, if present, must
10 UsbAttributes 1 conform to the USB string format per USB spec 1.0 or later. Bit 1 : Not used.
Bit 2: If set to 1, the device can be self powered, if set to 0, cannot be self powered.
Bit 3: If set to 1, the device can be bus powered, if set to 0, cannot be bus powered.
Bits 4 through 7: Reserved
11 MaxPower 1 Maximum power the device needs in units of 2 mA.
Device attributes:
Bit 0: If set to 1, the CPU clock is 24 MHz, if set to 0, the CPU clock is 12 MHz.
Bit 1: If set to 1, the download version of the header will be written into the EEPROM
(download target has to be EEPROM). If the header is not to be overwritten, or if the target is
12 Attributes 1 RAM, this bit must be cleared to 0.
Bit 2: Not used.
Bit 3: If set to 1, the EEPROM can support a 400 kHz I2C bus, if set to 0, the EEPROM cannot
support a 400-kHz I2C bus.
Bits 4 through 7: Reserved
13 WPageSize 1 Maximum I2C write page size, in units of bytes
This value defines if the device is an application EEPROM or a device EEPROM.0x01:
14 DataType 1 Application EEPROM—contains header and application code.0x02: Device EEPROM—contains only header.
All other values are invalid.
15 RpageSize 1 Maximum I2C read page size, in units of bytes. If the value is zero, the whole payLoadSize is read in one I2C read setup.
16 payLoadSize 2 Size, in units of bytes, of the application, if using EEPROM as an application EEPROM, otherwise the value is 0.
Language string in standard USB string format if applied. If this attribute is applied, the two
xxxx Language string 4 attributes that follow must also be applied. If this attribute is not applied, the following two
attributes cannot be applied.
xxxx Manufacture ... Manufacture string in standard USB string format if applied. string
xxxx Product string ... Product string in standard USB string format if applied.
xxxx Application Code ... Application code if applied
The header checksum is used by the firmware to detect the presence of a valid header in the EEPROM.
The header size field supports future updates of the header.
2.2.2.3.2 Application Code
Application code is stored as a binary image in the EEPROM following the header information. The binary
image must always be mapped to MCU program space starting at address 0x0000, and must be stored in
the EEPROM as a continuous linear block of data.
2.2.2.4 I2C Serial EEPROM
The TAS1020B accesses the EEPROM via an I2C serial bus. Thus the EEPROM must be an I2C serial
EEPROM. The ROM boot loader assumes the EEPROM device uses the full 7-bit I2C device address with
the upper four bits of the address (control code) set to 1010 and the three least significant bits (chip select
bits) set to 000.
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2.2.2.5 DFU Upgrade Process
DFU compliance provides a host the capability of upgrading application code currently residing in a
target's onboard EEPROM memory. The DFU upgrade process provided by the TAS1020B fully conforms
to the requirements specified in USB Device Class Specification For DFU 1.0.
The download must consist of both header and application code. The destination of the download must be
defined by the on-chip application code (as opposed to the application code being downloaded). Under
normal circumstances, the download destination would be EEPROM, but it is possible for the application
code to specify on-chip RAM as the download destination.
If the download destination is to be EEPROM, bit 1 of the Attribute field in the header data being
downloaded determines whether or not the header data in the download image is to be written to the
EEPROM. A bit value of 1 results in the header in the EEPROM being overwritten by the header content
in the download image. It is important to note that if the application code targets RAM as the download
destination, bit 1 in the Attribute field of the download image must be 0.
2.2.2.6 Download Error Recovery
Safeguards are incorporated on the TAS1020B ROM to allow recovery from a host download that does
not complete due to a loss of power. Before downloading the application code, the TAS1020B saves the
value of the Data Type field in the EEPROM header and modifies the Data Type field to indicate that a
download is in progress (0x03: Updating). After successful completion of the download, the TAS1020B
restores the saved value in the Data Type field. If the download is terminated prior to successful
completion, the Data Type field still indicates that a download is in progress. In the case of an
unsuccessful download the TAS1020B reboots as a DFU device in DFU Program mode and uses the
Vendor and Product ID from the EEPROM header as the vendor and product ID in its USB device
descriptor.
The download process consists of the following task flow.
1. Header portion of download is written to EEPROM, if applicable.
2. Header Data Type is retrieved and stored in RAM.
3. Header Data Type is overwritten with a value indicating that a download is in progress.
4. Application portion of download is written to EEPROM (or to RAM).
5. Header Data Type is overwritten with the previously recorded legal value.
If the download should terminate during the downloading of the header to EEPROM, the header
checksum results in the EEPROM being declared invalid on the next boot of the TAS1020B. If the
download should terminate during the downloading of the application code, the Data Type field indicates
that a download was in progress and the TAS1020B enters the DFU program mode on the next boot.
If the TAS1020B remains powered when a premature termination of a download occurs, the TAS1020B
remains in the DFU program mode. In this case, the host can again attempt a download; the TAS1020B
does not have to be rebooted.
2.2.2.7 ROM Support Functions
To conserve RAM memory resources on the TAS1020B, several USB-specific routines have been
included in the firmware resident in the on-chip ROM. The inclusion of these routines frees the application
code from having to implement USB-specific code.
The tasks provided by the ROM code include:
• A USB engine for handling USB control endpoint data transactions and states
• USB protocol handlers to support USB Chapter 9
• USB protocol handlers to support USB HID Class
• USB protocol handlers to support USB DFU Class
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• USB protocol handlers to support the common features of USB Audio Class commands
– Feature Unit:
• Set/get volume control
• Set/get mute control
• Set/get bass control
• Set/get treble control
– Mixer unit: set/get input/output gain control
– End point: set/get the audio streaming endpoint sampling frequency
– For unsupported case, the ROM code passes the requests to the application code for processing ().
See also Section 5.
2.2.3 USB Enumeration
USB enumeration is accomplished by interaction between the host PC and the TAS1020B. As described
in Section 2.2.2, the TAS1020B can identify itself as an application device by reporting its application
Vendor ID and Product ID, or it can identify itself as a DFU device by reporting a Vendor ID of 0xFFFF
and a Product ID of 0xFFFE. If the TAS1020B fails to detect the presence of an EEPROM, or if an
EEPROM is present but does not contain a valid header, the Vendor ID of 0xFFFF and Product ID of
0xFFFE are reported. If an EEPROM is present, but contains only valid header data, the Vendor ID and
Product ID settings in the EEPROM header are reported, but the TAS1020B firmware comes up as a DFU
device in the DFU program mode. If an EEPROM is present, and contains both a valid header and
application code, the TAS1020B comes up as an application specific device.
For all cases where the TAS1020B comes up in the DFU program mode, once application code has been
downloaded, the TAS1020B is reset by a host-issued USB reset. After this reset, the TAS1020B comes up
as an application device. When the TAS1020B comes up as an application device, the ROM-resident boot
loader retrieves the application code from the EEPROM, if the EEPROM is not a device EEPROM, and
then runs the application code. It is the application code that connects the TAS1020B to the USB. During
the enumeration that follows connection to the USB, the application code identifies the device as an
application specific device and the host loads the appropriate host driver(s).
The boot loader and application code both use the CONT, SDW and FRSTE bits to control the
enumeration process.
• The function connect (CONT) bit is set to a 1 by the MCU to connect the TAS1020B device to the
USB. When this bit is set to a 1, the USB DP line pullup resistor (PUR) output signal is enabled.
Enabling PUR pulls DP high via external circuitry (see Figure 4-1). (When the TAS1020B powers up,
this bit is cleared to a 0 and the PUR output is in the high-impedance state.) This bit is not affected by
subsequent USB resets.
• The shadow the boot ROM (SDW) bit is set to 1 by the MCU to switch the MCU memory configuration
from boot loader mode to normal operating mode. Once set to 1, this bit is not affected by subsequent
USB resets.
• The function reset enable (FRSTE) bit is set to a 1 by the MCU to enable the USB reset to reset all
internal logic including the MCU. However, the shadow the ROM (SDW) and the USB function connect
(CONT) bits are not reset. In addition, when the FRSTE bit is set, the reset output (RSTO) signal from
the TAS1020B device is active whenever a USB reset occurs. This bit, once set, is not affected by
subsequent USB resets.
2.2.4 TAS1020B USB Reset Logic
There are two mechanisms provided by the TAS1020B—an external reset MRESET and a USB reset.
The reset logic used in the TAS1020B is presented in Figure 2-2.
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MRESET is a global reset that results in all the TAS1020B logic and the 8052 MCU core being reset. This
input to the TAS1020B is typically used to implement a power-on reset at the application of power, but it
can also be used with reset pushbutton switches and external circuits to implement global resets at any
time. MRESET is an asynchronous reset that must be active for a minimum time period of one
microsecond.
The TAS1020B can also detect a USB reset condition. When this reset occurs, the TAS1020B responds
by setting the function reset (RSTR) bit in the USB status register (USBSTA). However, the extent to
which the internal logic is reset depends on the setting of the function reset enable bit (FRSTE) in the USB
control register (USBCTL).
If the MCU has set FRSTE to 1, incoming USB resets are treated as global resets, with all TAS1020B
logic and the 8052 MCU core being reset. However, the shadow the ROM (SDW) and the USB function
connect (CONT) bits are not reset. Also, if the USB reset results in a global reset being issued, an
interrupt to the 8052 MCU is not generated. But if the MCU has cleared FRSTE, incoming USB resets is
treated as interrupts to the MCU (via INT0) if the corresponding function reset bit RSTR in the USB
interrupt mask register USBMSK has been set by the MCU. If neither FRSTE or RSTR has been set by
the MCU, USB resets have no effect on the TAS1020B, other than resetting the USB serial interface
engine (SIE) and the USB buffer manager (UBM) in the TAS1020B.
Regardless of the status of FRSTE and bit RSTR in the USB interrupt mask register USBMSK, the
function reset bit RSTR in the USB status register USBSTA is always set whenever a USB reset condition
is detected. If the USB reset results in the generation of a global reset, the global reset clears the function
reset bit RSTR in USBSTA. If, instead, the USB reset results in an interrupt being generated, RSTR in
register USBSTA is cleared when the MCU writes to the interrupt vector register VECINT while in the USB
reset interrupt service routine (VECINT = 0x17).
The TAS1020B has two reset outputs—RSTO and CRESET. RSTO is activated every time MRESET is
active, and every time a USB reset occurs and bit FRSTE in the USB control register USBCTL is set.
CRESET is typically used as a codec reset. Although labeled a reset line, it has no direct relationship to
MRESET or detected USB resets. Instead, it is activated and deactivated when the on-chip 8052 MCU
core writes a 0 and a 1, respectively, to the CRST bit in the codec port interface control and status register
CPTCTL.
2.2.5 USB Suspend and Resume Modes
The TAS1020B can recognize a suspend state. Figure 2-2 shows the logical implementation of the
suspend and resume modes in the TAS1020B. The TAS1020B enters a suspend mode if a constant idle
state (j state) is observed on the USB bus for a period of 5 ms. USB compliance also requires that a
device enter a suspend state, drawing only suspend current from the bus, after no more than 10 ms of bus
inactivity, The TAS1020B supports this requirement by creating a suspend interrupt to the on-chip MCU
after a suspend condition has been present for 5 ms. Upon receiving this interrupt, the MCU firmware can
then take the steps necessary to assure that the device enters a suspend state within the next 5 ms.
There are two ways for the TAS1020B device to exit the suspend mode: 1) detection of USB resume
signaling and 2) proactively performing a local remote wake-up event.
2.2.5.1 USB Suspend Mode
When a suspend condition is detected on the USB, the suspend/resume logic sets the function suspend
request bit (SUSR) in the USB status register, resulting in the generation of the function suspend request
interrupt SUSR. To enter the low-power suspend state and disable all TAS1020B device clocks, the MCU
firmware, upon receiving the SUSR interrupt, must set the idle mode bit (IDL), which is bit 0 in the MCU
power control (PCON) register. Setting the IDL bit results in the TAS1020B suspending all internal clocks,
including the clocks to the MCU. The MCU thus suspends instruction execution while in the idle mode.
The MCU must not set the IDL bit while in the SUSR interrupt service routine (ISR), or while in any other
ISR. As described in Section 2.2.5.3, it is intended that the receipt of an INT0 interrupt at the MCU result
in exiting the suspend state. But if the MCU has suspended instruction execution while in an ISR,
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subsequent INT0 activity is not recognized, as the MCU is still servicing an interrupt. For this reason then,
it is necessary that IDL not be set while processing an ISR. (As described in Section 2.2.5.3, an external
wake-up event will resume clocks within the TAS1020B. But even if the clocks to the MCU resume, if the
MCU does not recognize INT0, the IDL bit remains set and thus the MCU core itself remains in the
suspend state).
The SUSR bit is cleared while in the SUSR ISR by writing to the interrupt vector register VECINT. While
servicing the SUSR ISR, the VECINT output is 0x16 - the USB function suspend interrupt vector. As
shown in Figure 2-2, the occurrence of a write to VECINT, while the USB function suspend interrupt vector
is being output, results in clearing bit SUSR of the USB status register. (The data written to VECINT is of
no consequence; the clearing action takes place upon decoding the write transaction to VECINT).
2.2.5.2 USB Resume Mode
When the TAS1020B is in a suspend state, any non-idle signaling on the USB is detected by the
suspend/resume logic and device operation resumes. When the resume signal is detected, the TAS1020B
clocks are enabled and the function resume request bit (RESR) is set, resulting in the generation of the
function resume request interrupt. The function resume request interrupt to the MCU automatically clears
the idle mode bit IDL in the PCON register, and as a result the MCU exits the suspend state and becomes
fully functional, with all internal clocks active. After the RETI from the ISR, the next instruction to be
executed is the one following the instruction that set the IDL bit. The RESR bit is cleared while in the
RESR ISR by writing to the interrupt vector register VECINT.
2.2.5.3 USB Remote Wake-Up Mode
The TAS1020B device has the capability to remotely wake up the USB by generating resume signaling
upstream, providing the host has granted permission to generate remote wake-ups via a SET_FEATURE
DEVICE_REMOTE_WAKEUP control transaction. If remote wakeup capability has been granted, the MCU
firmware, upon awakening from a suspend state, has to activate the remote wake-up request bit RWUP in
the USB control register USBCTL. Activation of RWUP consists of the MCU firmware writing a 1 followed
by a 0 to RWUP. This action creates a pulse, which results in the TAS1020B generating resume signaling
upstream by driving a k state (non-idle) onto the USB bus. The USB specification requires that remote
wake-up resume signaling not be generated until the suspend state has been active for at least 5 ms. In
addition, the specification requires that the remote wake-up resume signaling be generated for at least
1ms but for no more than 15 ms. The 5 ms requirement is met by not entering the suspend mode until an
idle state, or j state, is detected, uninterrupted, for 5 ms. The RWUP pulse results in driving a k state onto
the USB bus for 1 to 2 ms, and thus the 15 ms requirement is also met. Moreover, if an application wishes
to extend the duration of the k state on the USB bus, it need only extend the pulse width of RWUP. The
resulting duration of the resume signaling is the duration of the RWUP pulse plus 1 to 2 ms.
The condition that activates a remote wake-up is a transition from 1 to 0 on one of the P3 port bits whose
corresponding mask bit has been set to zero. (When in the suspend mode, the XINT input is treated as
port bit P3.2). As seen in Figure 2-2, the P3 mask register bits are gated with the P3 port input lines from
the I/O port cells. The gated P3 port bits are then all ORed together and the output is ANDed with the
suspend signal. The output of this logic drives the clock input of a flip-flop, and when the output of this
logic transitions from 0 to 1, the flip-flop is set to 1. The setting of this flip-flop to 1 results in the TAS1020B
exiting the suspend state and resuming all clocks, including those to the MCU core. The output of this
flip-flop is also gated with bit XINTEN in the global control register GLOBCTL, and the output of this gate
drives the INT0 interrupt logic. This means that a remote wake-up generates an INT0 interrupt to the MCU
only if bit XINTEN has been set. Therefore, before entering a suspend state, the firmware must set
XINTEN if remote wake-up capability is to be enabled.
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The wake-up interrupt is seen by the firmware as an XINT interrupt; that is, the interrupt vector register
VECINT has an output value of 0x1F. If the XINT pin is to be used as an event marker during normal
operation, and if one of the P3 port bits is to be used for a wake-up interrupt, the firmware must be able to
distinguish between a wake-up interrupt and a normal XINT interrupt. One technique would be to examine
the state of the IDL bit in the MCU power control register. If this bit is set, the interrupt event is a wake-up
interrupt; otherwise, the interrupt is a normal XINT interrupt. If an XINT event should occur during a
suspend mode, the event is ignored if the mask bit for P3.2 is set. (During a suspend mode the TAS1020B
clocks are disabled, and thus an incoming XINT interrupt event does not propagate through the
synchronization logic and activate the MCU INT0 input).
2.2.6 Adaptive Clock Generator (ACG)
The adaptive clock generator is used to generate two programmable master clock output signals (MCLKO
and MCLKO2) that can be used by the codec port interface and the codec device. Two separate and
programmable frequency synthesizers provide the two master clocks. This allows the TAS1020B to
support different record and playback rates for those devices that require separate master clocks to
implement different rates. For isochronous transactions, the ACG can also support USB asynchronous,
synchronous, and adaptive modes of operation. The ACG keeps count of the number of master clock
events between USB SOF time marks, and the DCNTX/Y field of the endpoint register IEPDCNTX/Y
keeps track of the number of samples received between USB SOF time marks. Synchronous isochronous
operation can be accomplished by adjusting one of the two frequency synthesizers until the correct
number of master clock events is obtained between USB SOF time marks. Similarly, monitoring the
number of samples received between USB SOF events can accommodate adaptive isochronous
operation. Here the frequency synthesizer is adjusted to obtain the proper codec output rate for the
number of samples received. The TAS1020B can also accommodate asynchronous isochronous
operation, and the input MCLKI is provided for this case. For asynchronous isochronous operation, the
external clock pin MCLKI is used to derive the data and sync signal to the codec. However, the external
clock that provides the input to pin MCLKI, instead of the master clock output (MCLKO or MCLKO2) from
the ACG, must also source the codec's MCLK.
A block diagram of the adaptive clock generator is shown in Figure 2-1. Each frequency synthesizer circuit
generates a programmable clock with a frequency range of 12-25 MHz, and each frequency synthesizer
output feeds a divide-by-M-circuit, which can be programmed to divide by 1 to 16. As a result, the
frequency range of each master clock is 750 kHz to 25 MHz. Also, the duty cycle of each master clock is
50% for all programmable frequencies (after a possible short, or "runt", initial cycle).
As indicated in Figure 2-1, multiplexers precede the master clocks MCLKO and MCLKO2. These
multiplexers provide the option of using the output of either frequency synthesizer (after division by the
divide-by-M circuit) or the MCLKI input (after division by the divide-by-I circuit) to source each master
clock. Each master clock is also assigned its own divide circuit to generate its associated CSCLK. The
C-port serial clock (CSCLK) is derived by setting the divide by B value in codec port interface configuration
register CPTNCF4 [2:0] and the C-port serial clock 2 (CSCLK2) is derived by setting the divide by B2
value in codec port receive interface configuration register 4 CPTRXCNF4 [2:0].
In addition, although not shown in Figure 2-1, each master clock is assigned its own CSYNC generator,
with the length and polarity of each CSYNC separately programmable.
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6 MHz PLL
Frequency
Synthesizer
Oscillator MCLK0
Divide
by M1
1
Frequency
Synthesizer
Divide
by M2
2
Divide
by I
4
4
3
ACG1DCTL[7:4]
ACG2DCTL[7:4]
ACG1DCTL[2:0]
ACGCTL[4]
ACGCTL[1]
ACGCTL[3]
ACGCTL[0]
16-Bit Counter
ACGCTL[6]
ACGCTL[7]
MCLK02
ACGCAPH
ACGCAPL
SOF
PSOF
MCLKI
Divide by B
CPTCNF4 [2:0]
CSCLK
Divide by B2
CPTRXCNF4 [2:0]
CSCLK2
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Figure 2-1. Adaptive Clock Generator Block Diagram
The ACG is controlled by the registers shown in Table 2-2. See Section 6.5.3 for details.
Table 2-2. AGC Control Registers
FUNCTIONAL REGISTER ACTUAL BYTE-WIDE REGISTERS
24-bit frequency register #1 ACG1FRQ2 ACG1FRQ1 ACG1FRQ0
16-bit capture register ACGCAPH ACGCAPL
8-bit synthesizer 1 divider control register ACG1DCTL
8-bit ACG control register ACGCTL
24-bit frequency register #2 ACG2FRQ2 ACG2FRQ1 ACG2FRQ0
8-bit synthesizer 2 divider control register ACG2DCTL
The main functional modules of the ACG are described in the following sections.
2.2.6.1 Programmable Frequency Synthesizer
The 24-bit ACG frequency register value is used to program the frequency synthesizer, and the value of
the frequency register can be updated by the MCU while the ACG is running. The high resolution of each
frequency value programmed allows the firmware to adjust the frequency value by +LSB or more to lock
onto the USB start-of-frame (SOF) signal and achieve a synchronous mode of operation, a necessity for
streaming audio applications. The 24-bit frequency register value is updated and used by the frequency
synthesizer only when MCU writes to the ACGFRQ0 register. The proper way to update a frequency value
then is to write the least significant byte (ACGFRQ0) last.
The frequency resolution of the output master clock depends on the actual frequency being output. In
general, the frequency resolution decreases with increasing output frequencies. The clock frequency of
the MCLKO output signal is calculated by using the formula:
For N ≥ 24 and N < 50, Frequency Synthesizer output frequency = 600/N MHz
For N = 50, frequency = 12 MHz
Where N is the value in the 24-bit frequency register (ACGFRQ). The value of N can range from 24 to 50.
The six most significant bits of the 24-bit frequency register are used to represent the integer portion of N,
and the remaining 18 bits of the frequency register are used to represent the fractional portion of N. An
example is shown below.
Alternatively, with ACGnFRQ considered to be a 24-bit unsigned value:
ACGnFRQ = [600 000 000 / output (Hz)] × 218
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Where output (Hz) is the output of Frequency Synthesizer n.
Example Frequency Register Calculation
Suppose the desired MCLKO frequency is 24.576 MHz. Using the above formula, N = 24.4140625
decimal. To determine the binary value to be written to the ACGFRQ register, separately convert the
integer value (24) to 6-bit binary and the fractional value (4140625) to 18-bit binary. As a result, the 24-bit
binary value is 011000.011010100000000000.
The corresponding values to program into the ACGFRQ registers are:
ACGFRQ2 = 01100001b = 61h
ACGFRQ1 = 10101000b = A8h
ACGFRQ0 = 00000000b = 00h
Keep in mind that writing to register ACGFRQ0 loads the frequency synthesizer with the new 24-bit value
in registers ACGFRQ2, ACGFRQ1, and ACGFRQ0.
Example Frequency Resolution Calculation
To illustrate the frequency resolution capabilities of the ACG, the next possible higher and lower
frequencies for MCLKO can be calculated.
To get the next possible higher frequency of MCLKO (24.57600384 MHz), decrease the value of N by 1
LSB. Thus, N = 011000.01 – 10100111 –11111111 binary.
To get the next possible lower frequency of MCLKO (24.57599600 MHz), increase the value of N by 1
LSB. Thus, N = 011000.01 – 10101000 – 00000001 binary.
For this example with a nominal MCLKO frequency of 24.576 MHz, the frequency resolution is
approximately 4 Hz.
Table 2-3 lists typically used frequencies and the corresponding ACG frequency register values.
Table 2-3. ACG Frequency Registers
SYNTHESIZED CLOCK ACG1FRQ2/ ACG1FRQ1/ ACG1FRQ0/ OUTPUT ACG2FRQ2 ACG2FRQ1 ACG2FRQ0
25 MHz 0x60 0 0
24.576 MHz 0x61 0×A8 0x0F
22.579 MHz 0x6A 0x4B 0x20
18.432 MHz 0x82 0x35 0x55
16.934 MHz 0x8D 0xBA 0x09
16.384 MHz 0x92 0x7C 0x00
12.288 MHz 0xC3 0x50 0x00
12 MHz 0xC8 0 0
2.2.6.2 Capture Counter and Register
The capture counter and register circuit consists of a 16-bit free running counter which runs at the capture
clock frequency. The capture clock source can be selected by programming bits MCLK01S0 and
MCLK01S1 in the ACGCTL register. The options are the divided output of frequency synthesizer no. 1, the
divided output of frequency synthesizer no. 2, or the divided input clock MCLKI. At each USB
start-of-frame (SOF) event or pseudo-start-of-frame (PSOF) event, the capture counter value is stored into
the 16-bit capture register. This value is valid until the next SOF or PSOF signal occurs (~1 ms). The MCU
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can read the 16-bit capture register value by reading the ACGCAPH and ACGCAPL registers. Because
the counter is a free running counter, and because the count range of the counter extends over several
frames before rolling over and beginning the count anew, the capture count values obtained are correlated
over several SOF cycles. This attribute is useful should a case ever arise when the MCU fails to read the
capture counter after a SOF event, and thus skips an SOF cycle.
As shown in Figure 2-1, there is only one capture counter and register, and its capture clock frequency is
always the clock selection for MCLKO. This means that MCLKO2 cannot be synchronized to the incoming
USB data stream. However, MCLKO2 is intended to support record capability for those cases where
record and playback are conducted at different master clock frequencies. Synchronization to the USB bus
for record is handled by the handshaking protocol established between the assigned DMA channel and
the USB buffer manager (UBM) (see Section 2.2.7.4.1, heading Circular Buffer Operation for Isochronous
IN Transactions for more detail). Thus it is not necessary that MCLKO2 itself be synchronized to the USB
bus.
2.2.7 USB Transfers
The TAS1020B device supports all USB data transfer types: control, bulk, interrupt, and isochronous. In
accordance with the USB specification, endpoint zero is reserved for the control endpoint and is
bidirectional. In addition to the control endpoint, the TAS1020B is capable of supporting up to 7 IN
endpoints and 7 OUT endpoints. These additional endpoints can be configured as bulk, interrupt, or
isochronous endpoints.
2.2.7.1 Control Transfers
Control transfers are used for configuration, command, and status communication between the host PC
and the TAS1020B device. Control transfers to the TAS1020B device use IN endpoint 0 and OUT
endpoint 0. The three types of control transfers are control write, control write with no data stage, and
control reads.
2.2.7.1.1 Control Write Transfer (Out Transfer)
The host PC uses a control write transfer to write data to the USB function. A control write transfer always
consists of a setup stage transaction and an IN status stage, and can optionally contain one or more data
stage transactions between the setup and status transactions. If the data to be transferred can be
contained in the two byte value field of the setup transaction data packet, no data stage transaction is
required. If the control information requires the transfer of more than two bytes of data, a control write
transfer with data stage transactions will be required. The steps followed for a control write transfer are:
Initialization Stage
1. MCU initializes IN endpoint 0 and OUT endpoint 0 by programming the appropriate USB endpoint
configuration blocks. This entails programming the buffer size and buffer base address, selecting the
buffer mode, enabling the endpoint interrupt, initializing the TOGGLE bit, enabling the endpoint, and
clearing the NACK bit for both IN endpoint 0 and OUT endpoint 0.
Setup Stage Transaction
1. The host PC sends a setup token followed by the setup data packet addressed to OUT endpoint 0. If
the data is received without an error, the USB Buffer Manager (UBM) writes the data to the setup data
packet buffer, sets the setup stage transaction (SETUP) bit to a 1 in the USB status register, returns
an ACK handshake to the host PC, and asserts the setup stage transaction interrupt. Note that as long
as the setup stage transaction (SETUP) bit is set to a 1, the UBM returns a NACK handshake for any
data stage or status stage transactions regardless of the endpoint 0 NACK or STALL bit values.
2. The MCU services the interrupt, reads the setup data packet from the buffer, and decodes the
command. If the command is not supported or valid, the MCU should set the STALL bit in the OUT
endpoint 0 configuration byte and the IN endpoint 0 configuration byte before clearing the setup stage
transaction (SETUP) bit. This causes the device to return a STALL handshake for any data stage or
status stage transactions. If the command decoded is supported, the MCU clears the interrupt, which
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automatically clears the setup stage transaction bit. The MCU also sets the TOGGLE bit in the OUT
endpoint 0 configuration byte to a 1. For control write transfers, the PID used by the host for the first
OUT data packet is a DATA1 PID and the TOGGLE bit must match.
Optional Data Stage Transaction
1. The host PC sends an out token packet followed by a data packet addressed to OUT endpoint 0. If the
data packet is received without errors the UBM writes the data to the endpoint buffer, updates the data
count value, toggles the TOGGLE bit, sets the NACK bit to a 1, returns an ACK handshake to the host
PC, and asserts the endpoint interrupt.
2. The MCU services the interrupt and reads the data packet from the buffer. To read the data packet,
the MCU first must obtain the data count value. After reading the data packet, the MCU must clear the
interrupt and clear the NACK bit to allow the reception of the next data packet from the host PC.
3. If the NACK bit is set to 1 when the in token packet is received, the UBM simply returns a NAK
handshake to the host PC. If the STALL bit is set to 1 when the in token packet is received, the UBM
simply returns a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data
packet is received, then no handshake is returned to the host PC.
Status Stage Transaction
1. For IN endpoint 0, the MCU clears the data count value to zero, sets the TOGGLE bit to 1, and clears
the NACK bit to 0 to enable the data packet to be sent to the host PC. Note that for a status stage
transaction a null data packet with a DATA1 PID is sent to the host PC.
2. The host PC sends an IN token packet addressed to IN endpoint 0. After receiving the IN token, the
UBM transmits the null data packet to the host PC. If the data packet is received without errors by the
host PC, an ACK handshake is returned. Upon receiving the ACK handshake, the UBM toggles the
TOGGLE bit, sets the NACK bit to 1, and asserts the endpoint interrupt.
3. If the NACK bit is set to 1 when the IN token packet is received, the UBM simply returns a NAK
handshake to the host PC. If the STALL bit is set to 1 when the IN token packet is received, the UBM
simply returns a STALL handshake to the host PC. If no handshake packet is received from the host
PC then the UBM prepares to retransmit the same data packet again.
2.2.7.1.2 Control Read Transfer (In Transfer)
The host PC uses a control read transfer to read data from the USB function. A control read transfer
consists of a setup stage transaction, at least one in data stage transaction, and an out status stage
transaction.
The steps followed for a control read transfer are:
Initialization Stage
1. MCU initializes IN endpoint 0 and OUT endpoint 0 by programming the appropriate USB endpoint
configuration blocks. This entails programming the buffer size and buffer base address, selecting the
buffer mode, enabling the endpoint interrupt, initializing the TOGGLE bit, enabling the endpoint, and
clearing the NACK bit for both IN endpoint 0 and OUT endpoint 0.
Setup Stage Transaction
1. The host PC sends a setup token followed by the setup data packet addressed to OUT endpoint 0. If
the data is received without an error, the UBM writes the data to the setup data packet buffer, sets the
setup stage transaction (SETUP) bit to a 1 in the USB status register, returns an ACK handshake to
the host PC, and asserts the setup stage transaction interrupt. Note that as long as the setup stage
transaction (SETUP) bit is set to a 1, the UBM returns a NACK handshake for any data stage or status
stage transactions regardless of the endpoint 0 NACK or STALL bit values.
2. The MCU services the interrupt, reads the setup data packet from the buffer, and decodes the
command. If the command is not supported or is not valid, the MCU sets the STALL bit in the OUT
endpoint 0 configuration byte and the IN endpoint 0 configuration byte before clearing the setup stage
transaction (SETUP) bit. This causes the device to return a STALL handshake for any data stage or
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status stage transactions. If the command decoded is valid and is supported, the MCU clears the
interrupt, which automatically clears the setup stage transaction bit. The MCU also sets the TOGGLE
bit in the IN endpoint 0 configuration byte to a 1. For control read transfers, the PID used by the host
for the first IN data packet is a DATA1 PID.
Data Stage Transaction
1. The data packet to be sent to the host PC is written to the IN endpoint 0 buffer by the MCU. The MCU
also updates the data count value then clears the IN endpoint 0 NACK bit to a 0 to enable the data
packet to be sent to the host PC.
2. The host PC sends an IN token packet addressed to IN endpoint 0. After receiving the IN token, the
UBM transmits the data packet to the host PC. If the data packet is received without an error by the
host PC, then an ACK handshake is returned. The UBM then toggles the TOGGLE bit, sets the NACK
bit to 1, and asserts the endpoint interrupt.
3. The MCU services the interrupt and prepares to send the next data packet to the host PC.
4. If the NACK bit is set to 1 when the IN token packet is received, the UBM simply returns a NAK
handshake to the host PC. If the STALL bit is set to 1 when the IN token packet is received, the UBM
simply returns a STALL handshake to the host PC. If no handshake packet is received from the host
PC, then the UBM prepares to retransmit the same data packet again.
5. MCU continues to send data packets until all data has been sent to the host PC.
Status Stage Transaction
1. For OUT endpoint 0, the MCU sets the TOGGLE bit to 1, then clears the NACK bit to a 0 to enable a
data packet to be sent by the host PC. Note that for a status stage transaction a null data packet with
the DATA1 PID is sent by the host PC.
2. The host PC sends an OUT token packet and the null data packet to OUT endpoint 0. If the data
packet is received without an error the UBM updates the data count value, toggles to the TOGGLE bit,
sets the NACK bit to a 1, returns an ACK handshake to the host PC, and asserts the endpoint
interrupt.
3. The MCU services the interrupt. If the status transaction completed successfully, then the MCU clears
the interrupt and clears the NACK bit.
4. If the NACK bit is set to 1 when the OUT token packet is received, the UBM simply returns a NAK
handshake to the host PC. If the STALL bit is set to 1 when the OUT token packet is received, the
UBM simply returns a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the
data packet is received, no handshake is returned to the host PC.
2.2.7.2 Interrupt Transfers
The TAS1020B supports interrupt data transfers both to and from the host PC. Devices that need to send
or receive a small amount of data with a specified service period should use the interrupt transfer type. IN
endpoints 1 through 7 and OUT endpoints 1 through 7 can all be configured as interrupt endpoints.
2.2.7.2.1 Interrupt Out Transaction
The steps followed for an interrupt out transaction are:
1. MCU initializes one of the OUT endpoints as an out interrupt endpoint by programming the appropriate
USB endpoint configuration block. This entails programming the buffer size and buffer base address,
selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the
endpoint, and clearing the NACK bit.
2. The host PC sends an OUT token packet followed by a data packet addressed to the OUT endpoint. If
the data is received without an error then the UBM writes the data to the endpoint buffer, updates the
data count value, toggles the toggle bit, sets the NACK bit to a 1, returns an ACK handshake to the
host PC, and asserts the endpoint interrupt.
3. The MCU services the interrupt and reads the data packet from the buffer. To read the data packet,
the MCU must first obtain the data count value. After reading the data packet, the MCU clears the
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interrupt and clears the NACK bit to allow the reception of the next data packet from the host PC.
4. If the NACK bit is set to a 1 when the data packet is received, the UBM simply returns a NACK
handshake to the host PC. If the STALL bit is set to 1 when the data packet is received, the UBM
simply returns a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data
packet is received, no handshake is returned to the host PC.
NOTE
In double buffer mode for interrupt out transactions, the UBM selects between the X and Y
buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM writes the data
packet to the X buffer. If the toggle bit is a 1, the UBM writes the data packet to the Y buffer.
When a data packet is received, the MCU determines which buffer contains the data packet
by reading the toggle bit. However, when using double buffer mode, the possibility exists for
data packets to be received and written to both the X and Y buffer before the MCU responds
to the endpoint interrupt. In this case, simply use the toggle bit to determine which buffer
contains the data packet does not work. Hence, in double buffer mode, the MCU reads the X
buffer NACK bit, the Y buffer NACK bit, and the toggle bit to determine the status of the
buffers.
2.2.7.2.2 Interrupt In Transaction
The steps followed for an interrupt in transaction are:
1. MCU initializes one of the IN endpoints as an in interrupt endpoint by programming the appropriate
USB endpoint configuration block. This entails programming the buffer size and buffer base address,
selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the
endpoint, and setting the NACK bit.
2. The data packet to be sent to the host PC is written to the buffer by the MCU. The MCU also updates
the data count value and clears the NACK bit to 0 to enable the data packet to be sent to the host PC.
3. The host PC sends an IN token packet addressed to the IN endpoint. After receiving the IN token, the
UBM transmits the data packet to the host PC. If the data packet is received without errors by the host
PC, an ACK handshake is returned. The UBM then toggles the toggle bit, sets the NACK bit to a 1,
and asserts the endpoint interrupt.
4. The MCU services the interrupt and prepares to send the next data packet to the host PC.
5. If the NACK bit is set to a 1 when the in token packet is received, the UBM simply returns a NACK
handshake to the host PC. If the STALL bit is set to a 1 when the IN token packet is received, the UBM
simply returns a STALL handshake to the host PC. If no handshake packet is received from the host
PC, then the UBM prepares to retransmit the same data packet.
NOTE
In double buffer mode for interrupt IN transactions, the UBM selects between the X and Y
buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM reads the data
packet from the X buffer. If the toggle bit is 1, the UBM reads the data packet from the Y
buffer.
2.2.7.3 Bulk Transfers
The TAS1020B supports bulk data transfers both to and from the host PC. Devices that need to send or
receive a large amount of non time-critical data should use the bulk transfer type. IN endpoints 1 through
7 and OUT endpoints 1 through 7 can be configured as bulk endpoints. TAS1020B supports single and
double buffering for bulk transfers.
2.2.7.3.1 Bulk Out Transaction Using MCU
The steps for a bulk out transaction are as follows:
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1. MCU initializes one of the OUT endpoints as an OUT bulk endpoint by programming the appropriate
USB endpoint configuration block. This entails programming the buffer size and buffer base address,
selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the
endpoint, and clearing the NACK bit.
2. The host PC sends an OUT token packet followed by a data packet addressed to the OUT endpoint. If
the data is received without an error, the UBM writes the data to the endpoint buffer, updates the data
count value, toggles the toggle bit, sets the NACK bit to a 1, returns an ACK handshake to the host
PC, and asserts the endpoint interrupt.
3. The MCU services the interrupt and reads the data packet from the buffer. To read the data packet,
the MCU must first retrieve the data count value. After reading the data packet, the MCU clears the
interrupt and clears the NACK bit to allow the reception of the next data packet from the host PC.
4. If the NACK bit is set to 1 when the data packet is received, the UBM simply returns a NACK
handshake to the host PC. If the STALL bit is set to 1 when the data packet is received, the UBM
simply returns a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data
packet is received, no handshake is returned to the host PC.
NOTE
In double buffer mode for bulk OUT transactions, the UBM selects between the X and Y
buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM writes the data
packet to the X buffer. If the toggle bit is a 1, the UBM writes the data packet to the Y buffer.
When a data packet is received, the MCU determines which buffer contains the data packet
by reading the toggle bit. However, when using double buffer mode, data packets may be
received and written to both the X and Y buffer before the MCU responds to the endpoint
interrupt. In this case, simply using the toggle bit to determine which buffer contains the data
packet does not work. Hence, in double buffer mode, the MCU reads the X buffer NACK bit,
the Y buffer NACK bit, and the toggle bit to determine the status of the buffers.
2.2.7.3.2 Bulk In Transaction Using MCU
The steps followed for a bulk in transaction are:
1. MCU initializes one of the IN endpoints as an IN bulk endpoint by programming the appropriate USB
endpoint configuration block. This entails programming the buffer size and buffer base address,
selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the
endpoint and setting the NACK bit.
2. The data packet to be sent to the host PC is written to the buffer by the MCU. The MCU also updates
the data count value then clears the NACK bit to a 0 to enable the data packet to be sent to the host
PC.
3. The host PC sends an IN token packet addressed to the IN endpoint. After receiving the IN token, the
UBM transmits the data packet to the host PC. If the data packet is received without errors by the host
PC, an ACK handshake is returned. The UBM then toggles the toggle bit, sets the NACK bit to a 1,
and asserts the endpoint interrupt.
4. The MCU services the interrupt and prepares to send the next data packet to the host PC.
5. If the NACK bit is set to 1 when the in token packet is received, the UBM simply returns a NAK
handshake to the host PC. If the STALL bit is set to 1 when the IN token packet is received, the UBM
simply returns a STALL handshake to the host PC. If no handshake packet is received from the host
PC, the UBM prepares to retransmit the same data packet again.
NOTE
In double buffer mode for bulk IN transactions, the UBM selects between the X and Y buffer
based on the value of the toggle bit. If the toggle bit is a 0, the UBM reads the data packet
from the X buffer. If the toggle bit is a 1, the UBM reads the data packet from the Y buffer.
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2.2.7.3.3 Bulk Out Transaction Through DMA
This transaction is used by mass storage class USB applications to move bulk data to an external device
via the TAS1020B DMA resources. The difference between MCU-supported bulk transactions and
DMA-supported bulk transactions lies in how the data in the assigned out endpoint buffer is distributed to
its final destination. Two modes of DMA operation are possible. One mode is a software handshake mode
utilizing synchronization communication between the MCU, the USB Buffer Manager (UBM), and an
external device. The second mode is a direct exchange mode that bypasses communication with the MCU
and directly outputs USB packets to an external device via the DMA resources. Higher bandwidth
transactions can be achieved in the direct exchange mode.
In both modes, the on-chip C-port is used to output the received bulk data to an external device. To
implement DMA-supported transactions, the C-port must be programmed to operate in either a
general-purpose (GP) mode or an Audio Codec '97 (AC97) mode. When in the general-purpose mode,
SYNC is disabled when there is no valid data in the buffer to be output; in the AC97 mode, the time slot
valid bits in the tag field are disabled when there is no valid data in the buffer to be output.
Software Handshake Using MCU, UBM, and External Device
Bulk data has the lowest priority of all transfers on the USB bus. But when there is little other activity on
the USB bus, bulk transfers can achieve significant transfer rates. Bulk transfer rates then can fluctuate
greatly, and for this reason it is sometimes necessary to monitor the transfer rate of bulk transfers in order
to throttle back the transfer rate when the rate exceeds the bandwidth of the target device. The software
handshake mode is provided to enable the implementation of just such a throttling of data.
The following steps explain the operation of the software handshake mode.
1. The MCU initializes one of the OUT endpoints as a bulk OUT endpoint by programming the
appropriate USB endpoint configuration block. This entails programming the buffer size and buffer
base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit,
enabling the endpoint, and clearing the NACK bit.
2. To configure a given DMA channel to process a given endpoint in a software handshake mode, the
MCU must
– Enable the handshake mode by setting the HSKEN bit in the DMA channel control register
(DMACTL0 and DMACTL1) to 1. In this same register the MCU must also program the USB
endpoint direction and endpoint number fields.
– Program the DMA current buffer content register (DMABPCT0 and DMABPCT1) with the number of
bulk out packets to be handled by the DMA process without MCU intervention once the MCU has
invoked the DMA process.
– Program the DMA channel time slot assignment register (DMATSH0 and DMATSH1) with the time
slot assignments to be supported by the DMA channel and the number of bytes to be transferred
for each supported time slot.
3. The MCU must also appropriately configure the C-port. (See Section 2.2.7.4 for more detail on
initializing the C-port). Note that if the C-port is placed in mode 0 (general-purpose mode) the CPTBLK
bit in the codec port interface configuration register 4 must be set to 1 to assure that SYNC is disabled
when there is no valid data in the buffer to be output.
4. Data is now ready to be received. The UBM, after receiving the bulk out packet and placing it in the
appropriate buffer, toggles the toggle bit if the double-buffer mode is set, sets the NACK bit to 1, stores
the packet data count in the data count register, and issues an interrupt to the MCU.
5. If the external device indicates that it is ready to receive data, the MCU enables the DMA process by
setting the DMAEN bit the DMA channel control register (DMACTL0 and DMACTL1). (Handshaking
between the MCU and external device will have to have taken place earlier to determine the status of
the external device).
6. Once enabled, the DMA engine proceeds to transfer the contents of the buffer(s) to the C-port for
transmittal to the external device. Data availability in the buffer(s) is determined by examining the
NACK flags - which are set to 1 when data has been received. For the double buffer case, the buffer to
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be used to retrieve data for the C-port is determined by not only examining the NACK flags but also by
monitoring the state of the toggle bit. The NACK bit is cleared by the DMA logic (as opposed to the
MCU) each time an entire buffer content has been transferred to the C-port via DMA.
7. If the number of bulk out packets to be handled by the DMA process without MCU intervention is
greater than one (the number can be as high as 64K packets), multiple buffer writes take place before
the DMA process completes. Every time a data packet is written to a given buffer, the UBM generates
the MCU endpoint interrupt. If the MCU wishes to remain autonomous to the DMA process, the MCU
must mask off the MCU endpoint interrupt (by clearing the OEPIE bit in the USB out configuration
register OEPCNFx) before enabling the DMA process.
8. When the DMA process completes, the DMA channel disables itself and issues a DMA0 or a DMA1
interrupt to the MCU. Upon receiving the interrupt, the MCU knows that DMABPCT packets have been
sent out to the C-port. The MCU then enables the appropriate endpoint interrupt (if it had been
previously masked off). The process is now complete.
Direct Exchange Mode
This mode offers the highest bandwidth for bulk OUT transactions. The process is almost identical to the
software handshake mode, the only difference being that the Direct Exchange mode, once enabled, runs
continuously until disabled; whereas the Software handshake mode only remains active for the processing
of DMABPCT packets. The Direct Exchange mode is selected by clearing the bit HSKEN in the DMA
channel control register (DMACTL0 and DMACTL1). When the MCU enables the DMA process, after
appropriately setting up the endpoint configuration registers, the C-port configuration registers, and the
DMA channel, the DMA process remains active until disabled by the MCU. While the DMA channel is
active, received packets continue to be retrieved from the appropriate endpoint buffer and transferred to
the C-port for transmission to the external device.
2.2.7.3.4 Bulk In Transaction Using DMA
The TAS1020B does not support BULK IN using the DMA resources.
2.2.7.4 Isochronous Transfers
The TAS1020B supports isochronous data transfers both to and from the host PC. Devices that need to
send or receive data at a constant rate must use the isochronous transfer type rate if the bandwidth of the
data exceeds the USB bandwidth allotted to interrupt type transactions. IN endpoints 1 through 7 and OUT
endpoints 1 through 7 can all be configured as isochronous endpoints.
Isochronous transfers must include the use of a DMA channel; MCU-supported isochronous transfers are
not allowed. Since the TAS1020B has only two DMA channels, at any point in time only two isochronous
transactions can be concurrently supported by the TAS1020B.
To setup an isochronous IN or an isochronous OUT transaction, the MCU must initialize the appropriate
IN or OUT USB endpoint configuration block. For isochronous transactions, this entails programming the
buffer size and buffer base address, enabling the endpoint interrupt, setting the ISO bit (to flag that the
endpoint is an isochronous endpoint), clearing the NACK bit, and enabling the endpoint. When the ISO bit
is set, the hardware configures the buffer to be a single circular buffer (see Section 2.2.7.4.1), using the
endpoint buffer size register I/OEPBSIZx and buffer base address register I/O EPBBAXx. The size of the
circular buffer is the size specified in I/OEPSIZx. (This is not to be confused with the same value in
I/OEPSIZx yielding two buffers of that size when the double buffer mode is selected for control, interrupt,
and bulk transactions.)
The TAS1020B DMA engine has two DMA channels. Each channel can be assigned to any IN or OUT
endpoint that has been configured as an isochronous endpoint. (As previously discussed, DMA channels
can also be assigned to bulk out endpoints). If an isochronous OUT endpoint receives data, the DMA
channel assigned to the endpoint will retrieve the data from the endpoint buffer and transfer it to the C-port
for outputting to the external device. If a DMA channel is assigned to an isochronous IN endpoint, the
DMA channel transfers external device data received on the C-port to the IN endpoint buffer.
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Each DMA channel can only implement data flow between endpoint buffers and the C-port. The
configuration of each DMA channel includes a 14-bit field that defines which of the up to 14 time slots in
the C-port audio frame the DMA channel supports. Both DMA channels could thus service OUT endpoints,
or IN endpoints, with each DMA channel supporting different time slots in the audio frame.
Each DMA channel also provides a current buffer count register (DMABCNT0/1). For isochronous OUT
transactions, the count in the register represents the number of bytes being transferred from the OUT
endpoint buffer to the C-port during the current USB frame. A new count is derived at each USB SOF
event, and is the value of the write pointer address setting minus the read pointer address setting at the
time of the USB SOF event. The MCU can read the content of this register.
The steps required to service DMA-supported isochronous transfers are:
1. The MCU initializes an IN or OUT USB endpoint configuration block. This entails programming the
buffer size and buffer base address, setting the ISO bit, setting the number of bytes per isochronous
channel, clearing the NACK bit, and enabling the endpoint. Because the endpoint is configured as an
isochronous endpoint, the buffer configuration parameters are used to implement a circular buffer
rather than one or two linear buffers, and the size specified is the size of the single circular buffer.
2. The MCU configures the selected DMA channel. This entails:
– Programming registers DMATSH0/1 and DMATSL0/1, which consists of assigning the time slots to
be used and the number of bytes to be transferred per time slot.
– Programming register DMACTL0/1, which consists of setting the USB endpoint direction, selecting
the endpoint number, and setting the DMA channel enable bit DMAEN.
3. The MCU configures the C-port. This entails:
– Programming register CPTCNF1, which consists of setting the number of time slots per audio frame
and selecting the C-port interface mode (general purpose mode, AIC mode, etc.).
– Programming register CPTCNF2, which consists of setting the length of time slot 0 (number of
CSCLK serial clock cycles), setting the length of the remaining time slots (which are all the same in
length), and setting the number of data bits per time slot.
– Programming register CPTCNF3, which consists of:
– Setting the state of DDLY. A 1 programs a one CSCLK clock delay on the data output and data
input signals with reference to the leading edge of CSYNC. A 0 removes the delay.
– Setting the state of TRSEN. A 1 sets the C-port output to the high-impedance state for those
time slots that have no valid data.
– Setting the state of CSCLKP. A 1 programs the C-port to be CSCLK falling edge active (CDATO
and CSYNC transition on falling edge of CSCLK and DATI is sampled on rising edge of
CSCLK). A 0 results in activity on the opposite edges of CSCLK.
– Setting the state of CSYNCP. A 1 programs CSYNC to be active high. A 0 programs CSYNC to
be active low.
– Setting the state of CSYNCL. A 1 programs the length of CSYNC to be the same number of
CSCLK cycles as time slot 0. A 0 programs CSYNC to be one CSCLK cycle in length.
– Setting the state of BYOR. A 1 results in the DMA reversing the byte order in moving data
to/from the endpoint buffer.
– Setting the state of CSCLKD. A 1 sets the CSCLK port as an input port (TAS1020B receives
CSCLK). A 0 sets the CSCLK port as an output port (TAS1020B sources CSCLK).
– Setting the state of CSYNCD. A 1 sets the CSYNC port as an input port (TAS1020B receives
CSYNC). A 0 sets the CSYNC port as an output port (TAS1020B sources CSYNC).
– Programming register CPTCNF4, which consists of:
– Specifying the 4-Bit field ATSL. This field defines which time slot is to be used for secondary
communication (command/status) address and data.
– Setting the state of CPTBLK. When DMA is to be used to transport USB bulk transfers to
external devices via the C-port, the C-port must be placed in either a general-purpose mode or
an AC '97 mode, and CPTBLK must be set to one. When the C-port is placed in the
general-purpose mode, a state of 1 for CPTBLK results in CSYNC only being present when
valid data is present in the current frame. When the C-port is placed in the AC '97 mode, a state
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of 1 for CPTBLK results in CSYNC always being present, but the tag bits in time slot 0 being set
to indicate the presence or absence of data. When CPTBLK is set to 0, CSYNC and CSCLK are
free running once the C-port is enabled.
– Specifying the 3-Bit field DIVB. This defines the divide ratio of MCLK to CSCLK.
– Programming bits 4-7 of register CPTCTL to enable or disable the C-port transmit and receive
interrupts. Bits 1-2 of register CPTCTL are used to select between primary and secondary codecs
when using two codecs in the AC '97 mode. Bit 0 of register CPTCTL (CRST), when cleared to 0, is
used to issue resets to external devices via the CRESET output pin.
NOTE
C-port registers CPTADR, CPTDATL, and CPTDATH are accessed during run time
operation to set the address, the data, and the mode (receive (status) or command (write))
for secondary communications. Registers CPTVSLL and CPTVSLH are only used when the
AC '97 mode is selected and are used to specify which time slots in the audio frame contain
valid data. Registers CPTRXCNF2, CPTRXCNF3, and CPTRXCNF4 must be initialized
when the C-port is used in the I2S mode (mode 5) to support an ADC and a DAC running at
different frequencies.
2.2.7.4.1 Circular Memory Buffer Implementation
A significant feature of DMA-supported isochronous transfers is the circular memory structure used to
buffer the incoming data. In most applications, the C-port timing is derived from the USB frame rate using
a soft-PLL provided in the TAS1020B firmware. However, the USB frame rate can vary within specified
boundaries, and the output phase of the PLL can lag (or lead) the input during such variations. If a linear
ping pong buffer implementation is used, tolerance must be built into switching between buffers to
accommodate all possible magnitudes of variation in the relative timing between the input and output time
references. A circular buffer topology greatly simplifies the implementation of the buffer as the need for
decision points on when to switch buffers is eliminated.
The circular buffer implementation used in TAS1020B utilizes the same endpoint start (I/OEPBBAXx) and
size (I/OEPBSIZx) assignment used by the linear buffer implementation, and the size of the circular buffer
is the size specified in I/OEPBSIZx. The circular buffer implementation does require the use of two
additional registers - a read pointer and a write pointer. These two registers are controlled by hardware,
but are made available to the MCU for debug purposes.
Circular Buffer Operation for Isochronous OUT Transactions
The operation of the circular buffer for isochronous OUT transactions is as follows.
• Initially, the read and write pointers are set in hardware to the OUT endpoint start address.
• As the first packet of isochronous data addressed to the endpoint is received, the UBM stores the data
into the circular buffer and updates the value of the write pointer by a count of one for each byte
written into the buffer.
• As soon as the DMA channel detects that the read and write pointers are not the same value (data is
available), the DMA channel could begin immediately retrieving data and outputting it to the C-port.
However, the DMA channel waits until the next USB SOF is received.
• Once the DMA channel has waited until the next SOF is received, the buffer contains a full packet of
data. Upon receiving SOF, the DMA channel further waits until the start of the next C-port frame and
then begins transferring the buffered data to the C-port, updating the read pointer by one count for
each byte of data transferred. At the C-port the data is output to the external device in accordance with
the timing requirements of the external device (8 frames for 8 kHz audio sampling, 48 frames for 48
kHz audio sampling, etc.). The DMA channel continues to retrieve data from the buffer and output it to
the C-port, update the read pointer, and check the value of the write pointer. Should the
DMA-controlled read pointer value ever equal the value of the UBM-controlled write pointer, the
process goes on hold and awaits the next USB SOF, where the process again resumes.
When the UBM completes writing a packet of data into the endpoint buffer, it loads the data count
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value of that packer (number of data samples, not bytes) into field DCNTX/Y of register
OEPDCNTX/Yx. The register chosen, OEPDCNTX or OEPDCNTY, is determined by the LSB of the
frame count register USBFNL. An LSB value of 1 chooses OEPDCNTY; a value of 0 chooses
OEPDCNTX. This count value does not play a role in implementing the data flow for isochronous out
transactions, but is provided for and can be accessed by the MCU. As is discussed in the next section,
the counts do play a role in implementing the data flow for isochronous in transactions.
• The streaming of audio data via the DMA channel continues indefinitely until the DMA engine is halted
by the MCU.
Circular Buffer Operation for Isochronous IN Transactions
For isochronous out transactions, the handshake implemented between the USB bus and the output
device ensures that at each USB SOF event, the output has access to a complete USB frame of data. For
isochronous in transactions, the mirror condition must be true: the handshake implemented between the
USB bus and the input device must ensure that at each USB SOF event, the UBM has access to one or
more complete frames of device data. Isochronous out transactions also ensure, by definition, that a
complete USB frame of data is transmitted between USB SOF events. But the mirror condition here is not
true, there may not be an integer number of device frames received between USB SOF events.
If, at each USB SOF event, the UBM is to have access to one or more complete frames of data from the
input device, the latest codec frame available to the UBM has to have completed prior to the USB SOF
event. But it is not known when the last input device frame to complete prior to the USB SOF event
occurs. Thus a timing mark must be set up to mark the worse case arrival time of the last complete input
device frame prior to the USB SOF event. The slowest sampling rate supported for an input device is set
at 8 kHz (8 kHz audio sampling). At 8 kHz, a frame arrives from the input device every 0.125 milliseconds,
which is 1500 12 MHz USB clock periods. Thus a time mark can be set to occur 1500 clock periods
before the next USB SOF event. When this time mark occurs, the DMA completes the current input device
frame, if a frame is currently being received, and then sets a handshake flag. The DMA also updates the
content of register IEPDCNTX/Y with the total number of samples collected since the previous handshake
flag was set. When the USB SOF event occurs, the UBM looks at the flag to see if data is available. If
data is available, the UBM refers to the count in the register to determine how much data is to be output
on the next isochronous in transaction.
To accommodate variations in the number of clocks at the output of the soft PLL, with respect to the
incoming 12-MHz USB data rate, the time mark count is actually set to 1511, rather than 1500. The extra
11 clock periods assures that the last frame prior to the USB SOF event will have completed. The flag
used is the NACK bit in the IEPDCNTX/Y register, and the data count is the 7-bit DCNTX/Y field in the
same register. For isochronous in transactions, the register chosen, IEPDCNTX or IEPDCNTY, is also
determined by the LSB of the frame count register USBFNL. But in the case of isochronous in
transactions, an LSB value of 1 chooses IEPDCNTX and a value of 0 chooses IEPDCNTY. The selection
logic for isochronous in transactions then is the reverse of that used for isochronous out transactions.
The operation of the circular buffer for isochronous in transactions is as follows.
• Initially, the read and write pointers are set in hardware to the IN endpoint start address. At the same
time the NACK flags in the IEPDCNTX and IEPDCNTY registers are set to logic 1 and the DCNTX and
DCNTY counts are cleared.
• As the input device frames are received, they are stored in the circular buffer by the DMA engine. As
each byte is stored in the buffer, the DMA engine updates the write pointer by one count, and also
keeps count of the number of samples being stored.
• When the time mark occurs, marking that there are 1511 USB clock periods remaining until the next
USB SOF event occurs, the DMA engine awaits the completion of the current incoming input device
frame (if one is currently being received). When the incoming input device frame completes, the DMA
engine sets the NACK flag in IEPDCNTX/Y to logic 0 and loads the number of samples received into
the DCNTX/Y field of IEPDCNTX/Y.
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• At this time, the DMA engine zeroes its running count of data samples and awaits the next input device
frame. For the DMA engine, the process repeats, and at the next time mark, the DMA engine sets the
NACK flag in IEPDCNTX/Y to logic 0 and loads the number of samples received into the DCNTX/Y
field of IEPDCNTXY.
• At the same time that the DMA engine reinitializes itself to receive the next input device frame, the
UBM has noted the clearing of the NACK flag in IEPDCNTX/Y. When this occurs, the UBM knows that
one or more complete frames reside in the circular buffer, starting at the address pointed to by the
read buffer, and that the integer number of frames comprise a total of DCNTX/Y samples. When the
USB SOF event occurs, the UBM is thus prepared and can respond to the USB isochronous in
transaction when it occurs. As the UBM retrieves data during the isochronous in transaction, it updates
the read pointer by one count for each byte retrieved. When DCNTX/Y samples have been output, the
NACK bit in IEPDCNTX/Y is set back to logic 1 and the isochronous transaction is terminated. The
UBM now awaits the clearing of the NACK bit in IEPDCNTX/Y and the occurrence of the next USB
SOF event, at which time the process repeats. The UBM now continues to alternate (ping pong)
between the data count and NACK flag value in register IEPDCNTX and the data count and NACK flag
value in register IEPDCNTY until the DMA process is terminated by the MCU.
• If an isochronous in token is received when there is no new data to be output (the NACK flag bits in
both IEPDCNTX and IEPDCNTY registers are at logic 1), the UBM will respond to the isochronous in
request with a NULL packet.
2.2.8 Microcontroller Unit
The TAS1020B chip contains an 8-bit microcontroller core for control and supervisory functions. The
microcontroller core used is based on the industry standard 8052. It is software compatible (including
instruction execution times) with the industry standard 8052AH and 8052BH discrete devices, having all
their core features plus the additional features corresponding to standard 8052 / 8032 / 80C52BH /
80C32BH / 87C52 parts - except the ONCE mode and program lock are not supported.
The MCU core has three 16-bit timer/counter units and a full-duplex serial port (UART). The timer/counter
units and the UART are made available via the port 3 bits; thus some of the port 3 bits have dual
functionality assignments in accordance with the 80C51 family of microcontrollers (see Section 2.2.11 for
more detail on the dual functionality of port 3).
2.2.9 External MCU Mode Operation
An external MCU mode of operation is provided for firmware development using an in-circuit emulator
(ICE). The external MCU mode is selected by setting pin EXTEN on the TAS1020B high. When the
external MCU mode is selected, the internal 8052 MCU core of the TAS1020B is disabled. Also in the
external MCU mode, the GPIO ports are used for the external MCU data, address, and control signals.
See Section 1.7, Terminal Functions - External MCU Mode, for details. When in the external mode of
operation, the external MCU or ICE is able to access the memory mapped IO registers, the USB
configuration blocks and the USB buffer space in the TAS1020B.
Texas Instruments has developed a TAS1020B evaluation module (EVM) to allow customers to develop
application firmware and to evaluate device performance. The EVM board provides a 40-pin dip socket for
an ICE and headers to allow expansion of the system in a variety of ways.
2.2.10 Interrupt Logic
The 8052 MCU core used in the TAS1020B supports the five standard 8052 MCU interrupt sources.
These five standard MCU interrupt sources are timer 0, timer 1, serial port, external 1 (INT1), and external
0 (INT0).The timer 0, timer 1, and serial port interrupts are MCU-internal interrupts, but INT0 and INT1 are
external to the MCU core. Figure 2-2 shows the associated interrupt circuitry external to the MCU core,
but within the TAS1020B chip. INT0 is input into the MCU core via port 3 bit P3.2, and INT1 is input into
the MCU core via port 3 bit P3.3. P3.3 can also be configured, under firmware control, to serve as a
general-purpose IO (GPIO) port bit. But the input side of P3.2 must be dedicated to servicing the INT0
function, as all additional interrupt sources from within the TAS1020B device are ORed together to
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generate the INT0 signal into port 3, bit P3.2. The other interrupt sources are: the eight USB IN endpoints,
the eight USB OUT endpoints, USB function reset, USB function suspend, USB function resume, USB
start-of-frame, USB pseudo start-of-frame, USB setup stage transaction, USB setup stage transaction
over-write, codec port interface transmit data register empty, codec port interface receive data register full,
I2C interface transmit data register empty, I2C interface receive data register full, DMA channel 0, DMA
channel 1, and the external interrupt XINT.
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DP
DM
USB Bus
Suspend
Counter
En clk
Decode
> 5 ms
Reset
Reset
Counter
clk
Decode
> 2.5 us
En
Interrupt Vector Reg
(VECINT)
Logic
Interrupts
Decode
/XINT Int
WE D[0:7] NX2 NX1
MCU write to Interrupt
Vector Register ”clears”
current vector to next
vector, or to 24h if no
other interrupt pending
RST
IDL
Power Control
Register (PCON)
USB Interrupt Mask Register
(USBMSK)
Internal Interrupts
(After Masks Applied)
Must be programmed to be
low level triggered (ITO bit
in MCU’s TCON control
register = 0), as multiple
internal TAS1020B events
can occur concurrently . The
internal hardware assures that
each interrupt remains low until
the MCU signals that the interrupt
has been serviced.
Function Suspend
Request Interrupt
Function Resume
Request Interrupt
P3MSK7 P3MSK2 P3MSK0
P3.7−IN
P3.6−IN
P3.5−IN
P3.4−IN
P3.3−IN
P3.1−IN
P3.0−IN
P3.7−IN
P3.2−IN
P3.0−IN
USB Reset Interrupt
Suspend
FRSTE
USB Control Register
(USBCTL)
XINTEN
7 6 5 0
Global Control Register
(GLOBCTL)
RESR
0 4 5 6 7
Cl Cl Cl
Decode
Resume Int
Decode
Suspend Int
Decode USB
Reset Int
USB Status
Register (USBSTA)
0 4 5 6 7
0 3 4 5 7
8052 MCU
CORE
CRST
0 1 7
Suspend
Global Reset
Codec Port Interface Control
and Status Register (CPTCTL)
Clear USB Serial Interface Engine (SIE)
and USB Buffer Manager (UBM)
7 1 0
PLL
SubSystem
Turn
Off
Turn
On
D
Q
CL
’1’
P3 Mask Register
(P3MSK)
7 6 3 2 1 0
Synchronized
XINT
Remote ”Wake−Up Interrupt
Suspend
TAS1020B
Clocks
Q
D
Q
D
Q
D
Q
D
24 MHz Clk
Q
D
CL
24 MHz Clk
Set Set Set
Q
D
48 MHz
Clk
MRESET
RSTO
CRESET
XINT
(P3.2−IN)
SUSR RSTR
RESR SUSR RSTR
TAS1020B
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Figure 2-2. TAS1020B Interrupt, Reset, Suspend, and Resume Logic
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The events that trigger the interrupt sources are:
• USB OUT endpoint interrupts: these interrupts are issued by the USB Buffer Manager (UBM)
whenever a complete data packet has been received and stored in an endpoint buffer. Each endpoint
is assigned a dedicated OUT endpoint interrupt. For isochronous transactions, however, OUT endpoint
interrupts are not issued. The firmware must clear OUT endpoint interrupts by writing to the interrupt
vector register.
• USB IN endpoint interrupts: these interrupts are issued by the USB buffer manager (UBM) whenever it
receives an ACK handshake packet from the host PC indicating that a data packet sent by the UBM
was received without error. Each endpoint is assigned a dedicated IN endpoint interrupt. For
isochronous transactions, however, IN endpoint interrupts are not issued. The firmware must clear IN
endpoint interrupts by writing to the interrupt vector register.
• USB function reset interrupt: whenever the host PC issues a USB reset, the bit RSTR in the USB
status register USBSTA is set. The setting of this bit causes all of the USB-related logic blocks in the
TAS1020B to be reset. If the function reset enable (FRSTE) bit in the USB control register USBCTL is
set, the setting of bit RSTR in the USB status register results in a global reset being issued - which
resets the MCU core and activates the reset output RSTO. If bit FRSTE is not set, the setting of bit
RSTR results in the USB function reset interrupt being issued. If a global reset is issued, it clears the
USB status register USBSTA, and thus clears bit RSTR. If a USB function reset interrupt is issued, the
interrupt and bit RSTR must be cleared in firmware by writing to the interrupt vector register.
• USB function suspend interrupt: whenever the host PC keeps the USB bus in the idle or j state for
more than 5 ms, bit SUSR in the USB status register USBSTA is set. This, in turn, results in the
activation of the USB function suspend interrupt. The interrupt and bit SUSR must be cleared in
firmware by writing to the interrupt vector register.
• USB function resume interrupt: whenever a suspend state is active and the host PC resumes activity
on the USB bus, bit RESR in the USB status register USBSTA is set. This, in turn, results in the
activation of the USB function resume interrupt. The interrupt and bit RESR must be cleared in
firmware by writing to the interrupt vector register.
• USB start-of-frame interrupt: whenever the TAS1020B detects the reception of a start-of-frame (SOF)
packet from the host PC, bit SOF in the USB status register USBSTA is set. This, in turn, results in the
activation of the USB start-of-frame interrupt. The interrupt and bit SOF must be cleared in firmware by
writing to the interrupt vector register.
• USB pseudo start-of-frame interrupt: the TAS1020B employs a counter that runs between USB
start-of-frame events, and is cleared upon every reception of a USB SOF event. This counter is
included in the TAS1020B to generate pseudo start-of-frame interrupt in case the SOF packet on the
USB bus is corrupted. This is done to maintain synchronization to the USB bus and maintain the
fidelity any on going streaming audio application. If this count ever reaches a value representative of a
time span longer than the 1 ms period of a USB frame, a USB SOF was not received. In such an
event, bit PSOF in the USB status register USBSTA is set. This, in turn, results in the activation of the
USB pseudo start-of-frame interrupt. The interrupt and bit PSOF must be cleared in firmware by writing
to the interrupt vector register.
• USB setup stage transaction interrupt: whenever a control transaction is initiated by the host PC, and
the setup data packet following the setup token packet is received without error, bit SETUP in the USB
status register USBSTA is set. This, in turn, results in the activation of the USB setup stage transaction
interrupt. The interrupt and bit SETUP must be cleared in firmware by writing to the interrupt vector
register.
• USB setup stage transaction overwrite interrupt: the USB 1.1 specification states that should a setup
transaction be received before a previously initiated control transaction is complete, the current control
transaction must be aborted and the new transaction processed. The USB setup stage transaction
interrupt addresses this requirement. The timing conditions under which this interrupt is issued are
shown in Figure 2-3.
In Figure 2-3, the host has sent two control transactions. Having received the setup data packet of the
first transaction without error, the SETUP bit in the USB status register USBSTA is set and the USB
setup stage transaction interrupt issued. While the MCU core is still processing the USB setup stage
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SETUP
TOKEN PACKET
SETUP
DATA PACKET
ACK
PACKET
CONTROL TRANSACTION #1 CONTROL TRANSACTION #2
MCU CORE PROCESSING INTERRUPT
USB Setup Stage
Transaction Overwrite Interrupt
USB Setup Stage
Transaction Interrupt
USB Bus Traffic
SETUP Bit In
USB Status Register
STPOW Bit In
USB Status Register
SETUP
TOKEN PACKET
SETUP
DATA PACKET
ACK
PACKET
TAS1020B
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transaction interrupt (as indicated by the set state of the SETUP bit, which the MCU does not clear
until exiting the USB setup stage transaction interrupt service routine), the host issues another control
transaction. Issuing another USB setup stage transaction interrupt would not be of value, as the MCU
is still in the USB setup stage transaction interrupt service routine processing the first control
transaction. Thus the USB setup stage transaction overwrite interrupt is used to indicate that a second
control transaction has been received while still processing the first control transaction. If a setup data
packet is received without error while the SETUP bit is set, the STPOW bit in the USB status register
USBSTA is set and the USB setup stage transaction overwrite interrupt is issued. The interrupt and
STPOW bit must be cleared in firmware by writing to the interrupt vector register.
Figure 2-3. Activation of Setup Stage Transaction Overwrite Interrupt
• Codec port interface transmit data register empty interrupt: codec port modes AC '97 and AIC, and the
general-purpose codec port mode, all support secondary communication. Both secondary read and
secondary write modes are supported. For the write mode (R/W bit in the codec port interface address
register CPTADR cleared to logic 0), command/status can be sent to the codec port by the MCU for
transmission to the codec. The codec hardware inserts the data into the proper time slot in the codec
frame and transmit the data. The MCU writes the command/status data to the codec port interface data
register CPTDATL (and register CPTDATH for 16-bit data). The data written by the MCU is not output
until the address is written to the codec port interface address register CPTADR. Upon writing the
address to CPTADR (and clearing bit R/W), the codec clears the transmit data register empty bit TXE
in the codec port interface control and status register CPTCTL to logic 0. The clearing of this bit flags
the hardware that new command/status data has been output. When the command/status data is taken
by the codec, bit TXE is set to 1, and the codec port interface transmit data register empty interrupt is
issued. The firmware must clear this interrupt by writing to the interrupt vector register, but this action
does not clear the TXE bit.
• Codec port interface receive data register full interrupt: codec port modes AC '97 and AIC, and the
general-purpose codec port mode, all support secondary communication. Both secondary read and
secondary write modes are supported. For the read mode (R/W bit in the codec port interface address
register CPTADR set to logic 1), command/status data received by the codec can be retrieved by the
MCU. Upon receiving secondary command/status data, the codec hardware transfers the data to the
codec port interface data register CPTDATL (and CPTDATH if 16-bit data is being transferred), sets
the receive data register full bit RXF in codec port interface control and status register CPTCTL to logic
1, and issues the codec port interface receive data register full interrupt. When the MCU reads the
command/status data, RXF is cleared to 0. The firmware must clear this interrupt by writing to the
interrupt vector register, but this action does not clear bit RXF. (Note that all secondary
command/status receive transactions take two codec frames to complete. First the MCU writes the
address of the command/status data to be read to CPTADR and sets the R/W bit in register CPTADR
to logic 1. On the next codec frame, the address is sent to the codec. On the following codec frame,
the requested data is output by the codec and received at the TAS1020B codec port.)
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• I2C interface transmit data register empty interrupt: whenever the MCU writes to the I2C interface
transmit data register I2CDATO, it results in the hardware clearing the transmit data register empty bit
TXE in the I2C interface control and status register I2CCTL. When the data byte is output onto the I2C
bus, the hardware sets TXE back to logic 1 and the I2C interface transmit data register empty interrupt
is issued. The firmware must clear this interrupt by writing to the interrupt vector register, but this action
does not clear the TXE bit.
• I2C interface receive data register full interrupt: whenever the I2C interface receive data register
I2CDATI receives a byte of data off the I2C bus, the hardware sets the receive data register full bit RXF
in the I2C interface control and status register I2CCTL and issues the I2C interface receive data
register full interrupt. The firmware must clear this interrupt by writing to the interrupt vector register,
but this action does not clear the RXF bit. The RXF bit in the I2C interface control and status register
I2CCTL is cleared whenever the MCU reads the contents of the I2C interface receive data register
I2CDATI.
• External interrupt XINT: this interrupt is provided to give a user the ability to issue interrupts from
external sources. XINT is logic 0 active. The interrupt is sampled by synchronization logic internal to
the TAS1020B, as shown in Figure 2-2.
As Figure 2-2 shows, XINT must be remain in an active-low state for at least one period of the 24 MHz
clock to assure that the interrupt is recognized. Also, XINT must transition to an inactive state (logic 1)
and then transition back to the active state (logic 0) if another XINT interrupt is to be recognized. If
XINT remains in the active low state, it does not result in issuing multiple XINT interrupts. The firmware
must clear this interrupt by writing to the interrupt vector register.
• DMA channel 0 interrupt: this interrupt becomes active only during bulk OUT transactions utilizing DMA
channel 0 when the software handshake mode is selected (see Section 2.2.7.3.3). In this mode of
operation the programmable variable DMABPCT - registers DMABPCT0 and DMABPCT1 - instructs
DMA channel 0 as to how many bulk OUT packets it must handle before ceasing operation and issuing
the DMA channel 0 interrupt. The firmware must clear this interrupt by writing to the interrupt vector
register.
• DMA channel 1 interrupt: this interrupt is identical in operation to the DMA channel 0 interrupt. Note
that the same count variable DMABPCT is used for both DMA interrupts. In fact, as described in
Section 2.2.12, only one of the two DMA channels can be active when supporting a bulk OUT
transaction. - thus the need for only one count variable DMABPCT.
The interrupts for the USB IN endpoints and USB OUT endpoints can be masked. An interrupt for a
particular endpoint occurs at the end of a successful transaction to that endpoint. A status bit for each IN
and OUT endpoint also exists. However, these status bits are read only, and therefore, these bits are
intended to be used for diagnostic purposes only. After a successful transaction to an endpoint, both the
interrupt and status bit for an endpoint are asserted until the interrupt is cleared by the MCU.
The USB function reset, USB function suspend, USB function resume, USB start-of-frame, USB pseudo
start-of- frame, USB setup stage transaction, and USB setup stage transaction over-write interrupts can all
be masked. A status bit for each of these interrupts also exists. Refer to the USB interrupt mask register
and the USB status register for more details. Note that the status bits for these interrupts are read only.
For these interrupts, both the interrupt and status bit are asserted until the interrupt is cleared by the MCU.
The codec port interface transmit data register empty, codec port interface receive data register full, I2C
interface transmit data register empty, and I2C interface receive data register full interrupts can all be
masked. A status bit for each of these interrupts also exists. Note that the status bits for these interrupts
are read only. However, for these interrupts, the status bits are not cleared automatically when the
interrupt is cleared by the MCU. Refer to the codec port interface control and status register CPTCTL and
the I2C interface control and status register I2CCTL for more details.
The external interrupt input (XINT) is logically ORed with the on-chip interrupt sources. An enable bit
exists for this interrupt in the global control register GLOBCTL. This interrupt does not have a status bit.
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2.2.11 General-Purpose I/O (GPIO) Ports
Figure 2-4 shows the architecture of the MCU port bits in the TAS1020B. There are two GPIO ports visible
to external devices - port 1 and port 3. In examining the functionality of these ports two interfaces must be
examined - the I/O driver interface provided at the I/O pads of the TAS1020B and the interface provided at
the M8052 MCU core.
At each I/O pad servicing the GPIO ports, the individual data input (DI) and data output (DO) lines into the
pads are combined into one bidirectional external line. Each I/O pad is also assigned a separate enable
line EN. When EN is a logic 0 the output driver is enabled, and when EN is a logic 1 the input buffer is
enabled. This implementation means that as an output the GPIO pin actively sinks current in the logic 0
state, but drives the logic 1 state through the 100-μa pullup. However, to obtain an acceptable rise time
when the output transitions from a logic 0 to a logic 1, the EN signal remains active for two clock periods
after the output data transitions from a logic 0 to a logic 1. For two clock periods then the output buffer
actively drives the logic 1 output level before yielding to the 100 μa pullup. This implementation also
means that to use a GPIO pin as an input, the DO line for that pin must be set to a logic 1 and the
external source driving the pin must be able of sinking the 100 μa pullup when driving a logic 0. (Some
port 3 bits also require that the alternate output data source be at logic 1 to use the pin as a GPIO input).
The TAS1020B global control register has two bits - P1PUDIS and P3PUDIS - that control the enabling
and disabling of the 100 μa pullups for port 1 and port 3 respectively. If firmware disables the 100-μA
pullups in one of the ports - by setting P1PUDIS or P3PUDIS to logic 1 - then when a port bit is configured
as an output, a logic 1 output will transition to a high-impedance state after the two clock delay period has
expired. At power-up, and after a global reset, all GPIO pins are configured as input ports with all 100-μA
pullups enabled(1).
The MCU core implements each GPIO bit using three signals - DI, DO, and EN. For both port 1 and port
3, EN is derived from DO by ANDing DO with a two clock delayed version of DO. This provides a
two-clock delay in transitioning EN from a logic 0 to a logic 1 after DO transitions from a logic 0 to a logic
1. It is this circuitry that results in the output buffer in the I/O pad actively driving a logic 1 output for two
clock periods before yielding to the 100-μA pullup or transitioning to a high-impedance state.
(1) At power-up, GPIO pins P3.0 and P3.1 can initialize as inputs, outputs driven high, or outputs driven low. After MRESET is high and
clocks start, P3.0 and P3.1 become inputs. The user's firmware application can then reprogram them as desired. This behavior occurs
only at power-up.
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Mode 0
Tx Data
Send
Tx Clk
Rx Data
Tx Clk (mode 0)
UART
MCUDO Q
MCU
Data Out
Alternate
ADO Data Out
MCU Read
MCU
Bus
MCU
MCUDI Data In
ADI
Alternate
Data In
EN
DO
DI
P3.0
EN
DO
DI
ADO
MCUDO
MCUDI
ADI
P3.1
EN
DO
DI
ADO
MCUDO
MCUDI
ADI
P3.2
EN
DO
DI
ADO
MCUDO
MCUDI
ADI
P3.3
EN
DO
DI
ADO
MCUDO
MCUDI
ADI
P3.4
EN
DO
DI
ADO
MCUDO
MCUDI
ADI
P3.5
EN
DO
DI
ADO
MCUDO
MCUDI
ADI
P3.6
EN
DO
DI
ADO
MCUDO
MCUDI
ADI
P3.7
Timer Logic
Timer 0 Event Clk
Timer 1 Event Clk
Timer 1 Gate
Q
P1.3
Q
P1.4
Q
P1.5
Q
P1.6
Q
P1.7
Q
P1.2
Q
P1.1
Q
P1.0
EN
EN
EN
EN
EN
EN
EN
EN
DO
DI
DO
DI
DO
DI
DO
DI
DO
DI
DO
DI
DO
DI
DO
DI
I/O
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
100 ua
P3.1
UART Tx Data
(Mode 0)
TAS1020B
Interrupt
Logic
On−Chip
Interrupts
P1PUDIS
0
GLOBCTL Reg
Mux
TAS1020B
Read Pulse
Mux
TAS1020B
Write Pulse
Not
Used
Not
Used
EXTEN
I/O
Drivers
M8052 MCU CORE
TAS1020B
P3.0
100 ua
100 ua
100 ua
100 ua
100 ua
100 ua
100 ua
100 ua
100 ua
100 ua
100 ua
100 ua
100 ua
100 ua
100 ua
Q
D Q
D
MCU Clk
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
D Q D Q
MCU Clk
UART Rx Data
Delay
Timer 2 Event Clk
Timer 2 Ext. Trigger
P3.2 (output only) / XINT
UART Tx Data
(Mode 0)
UART Tx Clk
(Mode 0)
P3.3 / INT1 / Timer 1
Gate
P3.4 / Timer 0 Event
P3.5 / Timer 1 Event
WR (output only, internal MCU mode only)
WRD (input only, external MCU mode
only)
RD (output only, internal MCU mode only)
RRD (input only, external MCU mode only)
Not Used
Not Used
INT0
Not Used
INT1
Not Used
Not Used
WR
Not Used
RD
Not Used
MCU Read
VREN
RESET
MCU Read
MCU Read
MCU Read
MCU Read
MCU Read
MCU Read
MCU Read
VREN Reset P3PUDIS
7 6 5 4 3 2 1
Tx Data (Mode 0)
Tx Data (Mode 0)
TAS1020B
SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com
Figure 2-4. GPIO Port 1 and Port 3 Functionality
Also, as shown in Figure 2-4, both ports can service logical units internal to the MCU core, as well as
service the memory-mapped discrete input and output lines assigned to each port.
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2.2.11.1 Port 3 GPIO Bits
As illustrated in Figure 2-4, alternative inputs on port 3 are routed directly from the DI input at the MCU
core interface to their destination within the MCU core. It is also noted that when the port bit is used as an
alternative input, the value of the input can still be read by the MCU. If the port bit is to be used as a
general-purpose input, the firmware must make the proper settings so that the alternative logic unit that
receives the general-purpose input does not erroneously respond to the input.
Each alternative output on port 3 is ANDed with the memory-mapped latch (Special Function Register -
SFR) assigned to that port bit, and the result is DO. This means that if the alternate output is to be used,
the latch must be set to logic 1. Similarly, if the latch is to be the source for DO, the alternate output must
be logic 1. (The MCU core assures that if the logical unit supplying the alternate output is not used, its
default state is logic 1).
2.2.11.1.1 UART Alternative Functions
Port 3 GPIO bits P3.0 and P3.1, in addition to being able to serve as general-purpose I/O bits, can also
serve to implement UART functionality. The UART implemented offers four modes of operation. In mode
0, UART output data is output on port bit P3.0 and the transmit clock (MCU clock/12) is output on port bit
P3.1. In modes 1, 2, and 3 UART receive data is input on P3.0 and UART transmit data is output on P3.1.
Modes 1, 2, and 3 are then full duplex modes; serial data can be transmitted and received simultaneously.
In all four UART modes, transmission is initiated by any instruction that accesses the MCU-core register
SBUF. If this register is not written to, the alternate output lines for P3.0 and P3.1 are at their default logic
1 state. P3.0 and P3.1 can then be used as general-purpose outputs if no instructions access register
SBUF.
The REN bit in the MCU serial port control register SCON enables UART reception if set to logic 1. If REN
is cleared to logic 0, using P3.0 as a general-purpose input does not result in erroneous behavior in the
UART logic block. P3.1 has no alternative input function, and thus it can be used as a general-purpose
input if the latch assigned to that bit is set to logic 1 and no instructions access register SBUF. (P3.0 also
requires that its latch be set to logic 1 and that no instructions access register SBUF if it is to be used as a
general-purpose input).
2.2.11.1.2 External Interrupts XINT and INT1
The MCU core provides ports for two external interrupts (external to the MCU core) - INT0 and INT1. INT0
is an alternate input for port 3 bit P3.2 and INT1 is an alternate input for port 3 bit P3.3. As seen from both
Figure 2-2 and Figure 2-4, INT0 is used to service all TAS1020B internal interrupts as well as the external
interrupt XINT. INT1 only services GPIO pin P3.3, and thus can be used as a dedicated interrupt line.
Because INT0 services all internal interrupts, the input DI for P3.2 must be dedicated to its alternative
input function INT0. Thus P3.2 cannot be used as a general-purpose input. However, if the external
interrupt XINT is not required, P3.2 can be used as a general-purpose output.
Port 3 bit P3.3 can be used as a general-purpose output, a general-purpose input, or as INT1. This bit can
also serve as a gate for timer 1 (see Section 2.2.11.1.3).
2.2.11.1.3 Timer Alternative Functions
The MCU core has three 16-bit timer/counter registers: timer 0, timer 1, and timer 2. In the timer mode,
the timer/counter register is incremented every MCU machine cycle (MCU clock/12). In the counter mode,
the timer/counter register is incremented in response to a falling edge (logic 1 to logic 0 transition) at its
assigned port bit input - P3.4 for timer 0, P3.5 for timer 1, and P1.0 for timer 2. To qualify as an event
clock in the counter mode, the external source must hold each logic state - logic 1 and logic 0 - for a
period of time greater than 12 MCU clock periods. This means that the maximum count rate in the counter
mode is MCU clock/24.
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Timer 1 can be gated on and off under external control to facilitate pulse width measurements. The
external control is brought in on port 3 bit P3.3, which is the same input that sources the alternate input
function INT1. Thus P3.3 can be thought of as having two alternate input functions.
The MCU core also provides gating for timer 0 via P3.2. However, the input DI for P3.2 must be dedicated
to INT0 so that the internal TAS1020B interrupts can be serviced. As a result, gated timing is not allowed
on timer 0.
In addition to the external event clock on port 1 bit P1.0, timer 2 has an external trigger input on port 1 bit
P1.1 which can be used to either capture the value in the counter when in the counter mode or reload the
timer when in the timer mode.
If the C/NT bit in the appropriate MCU special function register (SFR) for a given timer is cleared to enable
a timer function, or if the timer/counter interrupt is masked off by clearing the appropriate ET bit in the
MCU interrupt enable register IE, the corresponding port bit input providing the external event clock can
be used as a general-purpose input. For the external trigger input for timer 2, it is necessary to clear bit
EXEN2 in the MCU timer/counter 2 control register T2CON if this input is to be used as a general-purpose
input.
2.2.11.1.4 MCU Read/Write Pulse Alternate Function
The TAS1020B provides the capability of replacing the internal MCU core with an in-circuit emulator (ICE)
for firmware development. When in the external MCU mode of operation (EXTEN = 1), port 3 bits P3.7
and P3.6 respectively are used to input the ICE-generated memory read and write pulses so that the ICE
can access the memory-mapped resources internal to the TAS1020B (but not those resources internal to
the MCU core itself). When in the internal MCU mode, P3.6 and P3.7 output the external memory write
and read pulses respectively from the MCU core, and can be used as troubleshooting aids. P3.6 and P3.7
cannot be used as GPIO resources.
2.2.11.2 Port 1 GPIO Bits
Port 1 has two bits that have alternate input functionality - P1.0 and P1.1. The alternate function serviced
by these inputs is timer 2. P1.0 provides the external event clock for timer 2 and P1.1 provides the
external trigger. These alternate functions and the conditions under which these two bits can be used as
GPIO bits are discussed in Section 2.2.11.1.3.
Port 1 provides no alternate output functionality.
2.2.11.3 Pullup Macro
Figure 2-5 shows the equivalent circuit of the pullup "resistor" of the TAS1020B. For use with 3.3-V I/Os
only.
Figure 2-5. Pull-Up Logic Symbol
Table 2-4. Electrical Characteristics of Pullup Resistors(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IO Output current VO = 0 V –35.98 –90.67 –197.38 μA
FI Input loading factor TAP 1.65 pF
FI Input loading factor PWRDN 2.50 SL
Cpd Equivalent power dissipation capacitance 0.04 pF
(1) When PWRDN = H, the current source is turned off.
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2.2.12 DMA Controller
The TAS1020B provides two DMA channels for transferring data between the USB endpoint buffers and
the codec port interface. The DMA channels are provided to support the streaming of data for USB
isochronous or bulk OUT endpoints only. Each DMA channel can be programmed to service one
isochronous endpoint. The endpoint number and direction are programmable using the DMA channel
control register provided for each DMA channel.
For the two AC '97 modes supported by the TAS1020B, one DMA channel can be assigned to support
bulk OUT transactions and the second DMA channel assigned to support isochronous IN transactions. An
example would be downloading an AC3 file for storage via a bulk OUT transaction while, at the same
time, supporting an isochronous recording session. For all formats and protocols other than AC '97,
however, if a DMA channel is assigned to support bulk OUT transactions, it can be the only DMA channel
active. If, for example, DMA channel 0 is assigned to support bulk OUT transactions in the General
Purpose mode, then DMA channel 1 cannot be assigned to support bulk OUT or isochronous
transactions.
Section 2.2.7.3.3 provides more detail on DMA-supported bulk OUT transactions.
The codec port interface time slots to be serviced by a particular DMA channel must also be programmed.
For example, an AC '97 mode stereo speaker application uses time slots 3 and 4 for audio playback.
Therefore, the DMA channel used to move the audio data to the codec port interface must set time slot
assignment bits 3 and 4 to a 1. Each DMA channel is capable of being programmed to transfer data for
time slots 0 through 13 using the two DMA channel time slot assignment registers provided for each DMA
channel.
The number of bytes to be transferred for each time slot is also programmable. The number of bytes used
must be set based on the desired audio data format.
2.2.13 Codec Port Interface
The codec port interface is a configurable serial interface used to transfer data between the TAS1020B IC
and a codec device. The serial protocol and formats supported include AC '97 1.0, AC '97 2.0, and several
I2S modes. In addition, a general-purpose mode is provided that can be configured to various user defined
serial interface formats. Configuration of the interface is accomplished using the four codec port interface
configuration registers: CPTCNF1, CPTCNF2, CPTCNF3, and CPTCNF4. In I2S mode 5, CPTRXCNF2,
CPTRXCNF3, and CPTRXCNF4 are used to configure the C-port in the receive direction. See
Section 6.5.4 for more details on these registers.
The serial interface is a time division multiplexed (TDM) time slot based scheme. The basic format of the
serial interface is determined by setting the number of time slots per codec frame and the number of serial
clock cycles (or bits) per time slot. The interface in all modes is bidirectional and full duplex. For all modes
except the I2S modes, command/status data as well as audio data can be transferred via the serial
interface. Transfer of the audio data packets between the USB endpoint data buffers and the codec port
interface is controlled by the DMA channels. The source and/or the destination of the command/status
address and data values is controlled by the MCU.
The features of the codec port interface that can be configured are:
• The mode of operation
• The number of time slots per codec frame
• The number of serial clock cycles for slot 0
• The number of serial clock cycles for all slots other than slot 0
• The number of data bits per audio data time slot
• The time slots to be used for command/status address and data
• The serial clock (CSCLK) frequency in relation to the codec master clock (MCLK) frequency
• The source of the serial clock signal (internally generated or an input from the codec device)
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• The source of the codec master clock signal used to generate the internal serial clock signal (internally
generated by the ACG or an input to the TAS1020B device)
• The polarity, duration, and direction of the codec frame sync signal
• The relationship between the codec frame sync signal and the serial clock signal
• The relationship between the codec frame sync signal and the serial data signals
• The relationship between the serial clock signal and the serial data signals
• The use of zero padding or a high-impedance state for unused time slots and/or bits
• The byte ordering to be used
2.2.13.1 General-Purpose Mode of Operation
In the general-purpose mode the codec port interface can be configured to various user-defined serial
interface formats using the pin assignments shown in Table 2-5. This mode gives the user flexibility to
configure the TAS1020B to connect to various codecs and DSPs that do not use a standard serial
interface format.
Table 2-5. Terminal Assignments for Codec Port
Interface General-Purpose Mode
TERMINAL
GENERAL-PURPOSE MODE 0
NO. NAME
35 CSYNC CSYNC I/O
37 CSCLK CSCLK I/O
38 CDATO CDATA0 O
36 CDATI CDATA1 I
34 CRESET CRESET O
32 CSCHNE NC O
Serial bus protocols AC '97, AIC, and I2S are specific settings of the programmable parameters offered in
the general-purpose mode. The general-purpose mode then can be thought of as the primary mode of the
codec interface port, with all other modes being special cases of the general-purpose mode.
Figure 2-6, Figure 2-7, and Figure 2-8 show three general-purpose mode codec configuration examples.
Figure 2-6 gives the settings required to implement AC '97 1.0, Figure 2-7 gives the settings required to
implement AIC, and Figure 2-8 gives the settings required to implement I2S. In all three cases the
parameters that define these modes are included in the figures. It should be noted the MODE bits in
codec port interface configuration register 1 (CPTCNF1) can be used to specifically select either AC '97
1.0, AIC, or I2S. However, when using the specific mode selections, the firmware still must set all
parameters in the codec port interface configuration registers. The MODE bits are used simply to
implement mode-specific behavior not covered by the programmable parameters. An example of this
would be setting, when in one of the two AC '97 modes, those time slot tag bits in the time slot 0 tag word
that correspond to the time slots that have valid data.
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2.2.13.1.1 Parameter Assignments - AC '97 1.0
In Figure 2-6, the codec port interface is configured for 13 time slots. The word size for time slot 0 is 16
bits, whereas the word size for all other time slots is 20 bits. Time slots 1 and 2 are used for secondary
communication, and, in the example of figure 2-5, time slots 3, 4, 6, 7, 8, and 9 have valid audio data. The
sync line CSYNC is programmed to be logic 1 active for the duration of time slot 0. CSYNC and CDATO
are programmed to transition on the rising edge of CSCLK, which means that CDATI will be sampled on
the falling edge of CSCLK. For the example of Figure 2-6, each audio data word is only 16 bits in length,
and the 4 LSBs of the 20-bit data word slot are set to logic 0. Byte order reversal (BYOR) is not set, so the
byte ordering of the data as received is preserved - both from the USB bus (OUT transactions) and from
the external codec (IN transactions). To conform with AC '97 timing requirements, it is necessary that both
transmit and receive data be delayed by one CSCLK clock period with respect to the rising edge of
CSYNC. This is accomplished by setting DDLY to logic 1. Lastly, DIVB is programmed to set CSCLK to
MSCLK/2. This allows MSCLK to be set at 24.576 MHz and source the oscillator input XTRL_IN on AC '97
compliant codecs.
Figure 2-6 also points out that time slot assignments in AC '97 modes need not be the same for input data
frames and output data frames. For output data frames (CDATO), the settings in bit fields VTSL(3:7) and
VTSL(8:12) define which time slots have valid data. For input data frames (CDATI) the valid time slots are
determined from the settings of the time slot valid tag bits in the 16-bit tag word received in time slot 0.
The hardware uses these bit settings to extract the valid data from the input data frame and output it, via a
DMA channel, to an endpoint buffer resource.
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0
Tag
Rdy
CSYNC
CSCLK
CDATO
0
DDLY = 1
CSCLK
CDATO D15
0
CSCLKP = 0
CSYNCP = 1
CSYNCL = 1
Time Slot 0 Length = TSL0L = 10b (16 CSCLK Periods)
Time Slot Length = TSLL = 011b (20 CSCLK Periods)
Data Bits Per Time Slot = BPTSL = 001b (16)
Number Of Time Slots = NTSL = 01100b (13)
Mode = MODE = 010b (AC’97 1.0 Mode)
BYOR = 0
Cmd Time Slot = ATSL = 0001b
VTSL(3:7) = 11011b VTSL(8:12) = 11000b
CSYNC
CDATI
CDATO
Tag
TRSEN = 0
MCLKO (XTL_IN)
CSCLK
DIVB = 001b
Status Addr
Cmd Addr
1
Status Data
Cmd Data
2
PCM Left
PCM Left
3
PCM Rt
PCM Rt
4
0 . . . 0
5
PCM Mike
PCM Cen
6
PCM L Surr
7
PCM R Surr
8
LFE
9
0 . . . 0
10
0 . . . 0
11
0 . . . 0
12
TS1
1
TS2
2
TS12
12
0
13
ID1
14
ID0
15
D14
1
D13
2
D0
15
0
16
0
17
0
18
0
19
TAS1020B
SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com
Figure 2-6. Codec Port Interface Parameters − AC '97 1.0
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2.2.13.1.2 Parameter Assignments - AIC
Figure 2-7 shows the parametric settings for the AIC mode. In Figure 2-7, the codec port interface is
configured for 16 time slots. The word size for all time slots, including time slot 0, is 16 bits. Time slot 0 is
the only active audio time slot and time slot 8 is assigned to handle secondary communications. The sync
line CSYNC is programmed to be logic 1 active for one CSCLK period. DDLY is set to logic 1, and thus
transmit data (CDATO) and receive data (CDATI) are both delayed by one CSCLK period with respect to
the rising edge of CSYNC. CSYNC and CDATO are programmed to transition on the rising edge of
CSCLK, and consequently CDATI is sampled on the falling edge of CSCLK. Byte order reversal (BYOR) is
not set, so the byte ordering of the data as received is preserved - both from the USB bus (OUT
transactions) and from the external codec (IN transactions). The 3-state enable (TRSEN) is set, and thus
CDATO goes to a high-impedance state during the outputting of non-valid time slots. Lastly, CSCLK is set
to MSCLK/8. (This parameter selection is not part of the AIC standard.)
AIC requires both input (CDATI) and output (CDATO) audio data reside in time slot 0 and secondary
communication information reside in time slot 8. Thus, unlike AC '97, AIC does not require the use of the
valid time slot tag bits VTSL as there is no tag word needed to identify which time slots are valid. A unique
feature of AIC is the generation of a second CSYNC frame sync pulse within a given frame if a secondary
transaction is taking place. If the MCU has not output data requesting a secondary transaction, the second
frame sync pulse shown in Figure 2-7 is not generated. Thus without secondary communication there are
256 CSCLK periods between frame sync pulses, and with secondary communication there are 128
CSCLK periods between frame sync pulses.
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D15
Data Bits / Time Slot = BPTSL = 001b (16)
Time Slot 0 Length = TSL0L = 10b (16)
CSYNCL = 0, CSYNCP = 1
CSCLKP = 0
DDLY = 1
BYOR = 0
Time Slot 0 Time Slot 1 Time Slot 7 Time Slot 8 Time Slot 9 Time Slot 14 Time Slot 15
FC
CSYNC
DAC Data Register W. Data
CDATO /Register R. Addr
ADC Data
Register Read
CDATI Data
CSCLK
CSYNC
CDATO
or
CDATI
MCLKO
CSCLK
DIVB = 111b
1
NOTE: DA = Device Address
FC
Number of Time Slots = NTSL = 01111b (16)
TRSEN = 1
Cmd Time Slot = ATSL = 1000b (8)
Mode = MODE = 001b (AIC Mode)
D14 D13 D12 D2 D1 D0 DA2
Data Bits / Time Slot = BPTSL = 001b (16)
Time Slot Length = TSLL = 001b (16)
CSYNCL = 0, CSYNCP = 1
CSCLKP = 0
DDLY = 1
CSCLK
CSYNC
CDATO
or
CDATI
FC
DA1 DA0 RW D2 D1 D0
2 3 4 5 6 7 8
TAS1020B
SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com
Figure 2-7. Codec Port Interface Parameters − AIC
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2.2.13.1.3 Parameter Assignments - I2S
Figure 2-8 shows the parameter settings for I2S. I2S only uses two time slots. Time slot 0 is used for left
channel audio data and time slot 1 is used for right channel audio data. Secondary communication is not
allowed in I2S. The sync line CSYNC is programmed to be logic 0 active for the duration of time slot 0.
CSYNC and CDATO are programmed to transition on the falling edge of CSCLK, which means that
CDATI will be sampled on the rising edge of CSCLK. DDLY is set to logic 1, and thus transmit data
(CDATO) and receive data (CDATI) are both delayed one CSCLK period with respect to the falling edge of
CSYNC.
The time slot length for both time slots is programmed to be 32 bits. I2S does allow the use of different
word size lengths, and a word size length of 24 bits is selected for the example in Figure 2-8. Byte order
reversal (BYOR) is not set, so the byte ordering of the data as received is preserved.
CSCLK is set to MSCLK/4, which is a common ratio for I2S. For example, if 48 kHz audio sampling is
used, CSCLK would be 64 × 48 kHz = 3.072 MHz. MCLK then would be 4 × 3.072 MHz 12.288 MHz,
which is a standard master clock frequency used by I2S codecs for 48-kHz audio data.
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0
Time Slot 0 Time Slot 1 Time Slot 0
CSYNC
CSCLK
CDATO
or
CADTI
DDLY = 1
CSYNCL = 1, CSYNCP = 0
CSCLKP = 1
BYOR = 0
TSL0L = 11b (32 CSCLK Periods)
TSLL = 101b (32 CSCLK Periods)
BPTSL = 100b (24)
NTSL = 00001b (2)
MCLKO
CSCLK
DIVB = 011b
0 L23 L22 L21 L20 L1 L0 0 0 0 0 0 0 R23 R22 R21 R20 0R1 R0 0 0 0 0 0 0 L23 L22
Mode = MODE = 100b or 101b (I2S)
TAS1020B
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Figure 2-8. Codec Port Interface Parameters – I2S
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2.2.13.1.4 Byte Reversal Ordering
For all data transactions managed under DMA control, the TAS1020B provides an option to reverse the
ordering of the bytes within a data word as received. Byte order reversal, if selected, applies to both DMA
channels. If, for example, one DMA channel is used to output audio to a codec and the second DMA
channel is used to retrieve record data from a codec, byte reversal is applied to both audio streams.
When re-ordering the bytes within an audio data word, both time slot length (TSLL/TSL0L) and data bits
per time slot (BPTSL) must be taken into account. As an example consider Figure 2-9. In Figure 2-9 (a)
20-bit data in a 3-byte word is received either over the USB bus (OUT transaction) or from a codec (IN
transaction). The byte order of the data as received is little endian, where the least significant byte is
placed in the right-most byte position of the word. If BYOR = 1, byte reversal will be performed to yield an
output that is big endian in byte order, where the least significant byte is placed in the left-most byte
position of the word. However, in examining the byte-order reversed data in Figure 2-9 (b), it is noted that
the two nibbles of the most significant byte are switched to prevent a gap in the serial data when output.
The TAS1020B automatically performs this nibble reversal based on BPTSL being one nibble less than
the time slot in length.
a. Audio Word Received by TAS1020B
24 0
0 0 0 0 B19 B16 B15 B9 B8 B7 B1 B0
b. Received Audio Word After Byte Reversal
24 0
B7 B1 B0 B15 B9 B8 B19 B16 0 0 0 0
Figure 2-9. Byte Reversal Example
2.2.13.2 Audio Codec (AC) '97 1.0 Mode of Operation
In AC '97 1.0 mode, the codec port interface can be configured as an AC link serial interface to the AC '97
codec device. Refer to the audio codec '97 specification revision 2.2 for additional information. The AC link
serial interface is a time division multiplexed (TDM) slot based serial interface that is used to transfer both
audio data and command/status data between the TAS1020B IC and the codec device. NO TAG shows
the structure of the codec port interface signals for AC '97 1.0.
Table 2-6. Terminal Assignments for Codec Port
Interface AC '97 1.0 Mode 2
TERMINAL
AC '97 VERSION 1.0 MODE 2
NO. NAME
35 CSYNC SYNC O
37 CSCLK BIT_CLK I
38 CDATO SDATA_OUT O
36 CDATI SDATA_IN I
34 CRESET RESET O
32 CSCHNE NC O
In this mode, the codec port interface is configured as a bidirectional full duplex serial interface with a
fixed rate of 48 kHz. Each 48-kHz frame is divided into 13 time slots, with the use of each time slot
predefined by the audio codec AC '97 specification. Each time slot is 20 serial clock cycles in length
except for time slot 0, which is only 16 serial clock cycles. The serial clock, which is referred to as the
BIT_CLK for AC '97 modes, is set to 12.288 MHz. Based on the length of each slot, there is a total of 256
serial clock cycles per frame at a frequency of 12.288 MHz. As a result the frame frequency is 48 kHz. For
the AC '97 modes, the BIT_CLK is input to the TAS1020B device from the codec. The BIT_CLK is
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MCLKO1
CSYNC
CSCLK
CDATO
CDATI
CRESET
CSCHNE
AC97CLK
SYNC
BIT_CLK
SD_IN
SD_OUT
CRESET
TAS1020B AC’97 IC
TAS1020B
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generated by the codec from the master clock (MCLK) input. The codec MCLK input, which can be
generated by the TAS1020B device, must be a frequency of 24.576 MHz. The start of each 48-kHz frame
is synchronized to the rising edge of the SYNC signal, which is an output of the TAS1020B device. The
SYNC signal is driven high each frame for the duration of slot 0. See Figure 2-10 for details on connecting
the TAS1020B to a codec device in this mode.
Figure 2-10. Connection of the TAS1020B to an AC '97 Codec
The AC link protocol defines slot 0 as a special slot called the tag slot and defines slots 1 through 12 as
data slots. Slot 1 and slot 2 are used to transfer command and status information between the TAS1020B
device and the codec. Slot 1 and slot 2 of the outgoing serial data stream are defined as the command
address and command data slots, respectively. These slots are used for writing to the control registers in
the codec. Slot 1 and slot 2 of the incoming serial data stream are defined as the status address and
status data slots, respectively. These slots are used for reading from the control registers in the codec.
Unused or reserved time slots and unused bit locations within a valid time slot are filled with zeros. Since
each data time slot is 20 bits in length, the protocol supports 8-bit, 16-bit, 18-bit, or 20-bit data transfers.
2.2.13.3 Audio Codec (AC) '97 2.0 Mode of Operation
The basic serial protocol for the AC '97 2.0 mode is the same as the AC '97 1.0 mode. The AC '97 2.0
mode, however, offers some additional features. In this mode, the TAS1020B provides support for multiple
codec devices and also on-demand sampling.
Table 2-7. Terminal Assignments for Codec Port
Interface AC '97 2.0 Mode 3
TERMINAL
AC '97 VERSION 2.0 MODE 3
NO. NAME
35 CSYNC SYNC O
37 CSCLK BIT_CLK I
38 CDATO SDATA_OUT O
36 CDATI SDATA_IN I
34 CRESET RESET O
32 CSCHNE SD_IN2 I
The TAS1020B can connect directly to two AC '97 codecs. The interconnect for two codecs is shown in
Figure 2-11. As noted in Figure 2-11, the support for two codecs only requires the use of one additional
pin—CSCHNE (codec port interface secondary channel enable)—and this additional pin allows record
transactions to consist of data from two codecs. The two serial data lines from the two codecs to the
TAS1020B are ORed together inside the TAS1020B to form one final serial digital data stream. This
means that the data output from each codec must reside in different time slots. This also explains why
CSCHNE must be grounded when not used, as a floating input could result in unpredictable behavior and
corrupt the serial data coming in on the other input pin, SDATA_IN1.
AC '97 mode 2.0 also supports on-demand sampling. On-demand sampling is a codec-to-controller
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Secondary
MCLKO
CSCHNE
CRESET
CDATI
CDATO
CSCLK
CSYNC
AC97CLK
CRESET
SDATA_OUT
SDATA_IN
BIT_CLK
SYNC
AC97CLK
CRESET
SDATA_OUT
SDATA_IN
BIT_CLK
SYNC
AC ’97 IC
TAS1020B
AC97 or MC97
Primary
Serial Input Data
TAS1020B
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signaling protocol that is used to accommodate audio sampling rates that differ from the 48-kHz AC-link
serial frame rate. An example would be streaming 44.1 kHz audio across the AC-link. The signaling
protocol is implemented using the data request flags SLOTREQ[0-9] residing in SLOT1[2-11] of slot 1 of
the AC '97 input frame. An active request (bit request flag = 0) results in data being sent to the codec on
the next AC-link frame.
The TAS1020B does not support on-demand sampling when used with two codecs. Only one codec using
on-demand sampling can be supported by the TAS1020B.
Figure 2-11. Connection of the TAS1020B to Multiple AC '97 Codecs
2.2.13.4 Inter-IC Sound (I2S) Modes of Operation
The TAS1020B offers two I2S modes of operation, codec port interface mode 4 and codec port interface
mode 5. The difference in the I2S modes is the number of serial data outputs and/or serial data inputs
supported. For codec port interface mode 4, there is one serial data output (SDOUT1) and two serial data
inputs (SDIN1, SDIN2). Hence, mode 4 can be used to connect the TAS1020B device to a codec with one
stereo DAC and two ADCs. For codec port interface mode 5, one serial data output (SDOUT1) and one
serial data input (SDIN2) are supported, but these data streams can be completely independent as each is
assigned its separate sync pulse and bit clock. Mode 5 then can service applications that require different
sampling rates for record and playback. Table 2-8 shows the TAS1020B codec terminal assignments and
the respective signal names for each of the I2S modes. Figure 2-8 shows the signal waveforms for I2S.
Table 2-8. Terminal Assignments for Codec Port
Interface I2S Mode 4 and Mode 5
TERMINAL I2S I2S
NO. NAME MODE 4 MODE 5
35 CSYNC LRCK O LRCK1 O
37 CSCLK SCLK O SCLK1 O
38 CDATO SDOUT1 O SDOUT1 O
36 CDATI SDIN1 I SDIN2 I
34 CRESET CRESET O SCLK2 O
32 CSCHNE SDIN2 I LRCK2 O
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In all I2S modes, the codec port interface is configured as a bidirectional full duplex serial interface with
two time slots per frame. The frame sync signal is the left/right clock (LRCK) signal. Time slot 0 is used for
the left channel audio data, and time slot 1 is used for the right channel audio data. Both time slots must
be set to 32 serial clock (SCLK) cycles in length giving an SCLK-to-LRCK ratio of 64. The serial clock
frequency is based on the audio sample rate. For example, when using an audio sample rate (FS) of 48
kHz, the SCLK frequency must be set to 3.072 MHz (64×FS). (Note that the terms codec frame sync,
audio sample rate (FS), and LRCK all refer to the same signal.)
The LRCK signal has a 50% duty cycle. The LRCK signal is low for the left channel time slot and is high
for the right channel time slot. In addition, the LRCK signal is synchronous to the falling edge of the SCLK.
Serial data is shifted out on the falling edge of SCLK and shifted in on the rising edge of SCLK. Both for
the left channel and the right channel, there is a one-SCLK cycle delay from the edge of LRCK before the
most significant bit of the data is shifted out.
For the I2S modes of the codec port interface, there is a 24-bit transmit and 24-bit receive shift register for
each SDOUT and SDIN signal, respectively. As a result, the interface can actually support 16-bit, 18-bit,
20-bit or 24-bit transfers. The interface pads the unused bits automatically with zeros.
The I2S protocol does not provide for command/status data transfers. Therefore, when using the
TAS1020B device with a codec that uses an I2S serial interface for audio data transfers, the TAS1020B
I2C serial interface can be used for codec command/status data transfers.
2.2.13.4.1 Mapping DMA Time Slots to Codec Port Interface Time Slots for I2S Modes
The I2S serial data format uses two time slots (left channel—slot 0, and right channel—slot 1) for each
serial data output or input. Because two serial data streams are input into the TAS1020B in I2S mode 4
operation, and since each input stream has its own unique slot 0 and slot 1 assignments associated with
its data, the TAS1020B must contend with two slots arriving during time slot 0 and two slots arriving during
time slot 1. Mapping is then required to transpose these multiple time slot occurrences to single, unique
slot assignments for the DMA channel. Table 2-9 shows the mapping of the codec port interface time slots
for each input to their corresponding DMA time slot assignments.
As an example, suppose that codec port interface mode 4 is to be used with one serial data output and
two serial data inputs. The DMA channel assigned to support the serial data output must have time slot
assignment bits 0 and 1 set to 1. The DMA channel assigned to support the two serial data inputs must
have time slot assignment bits 0, 1, 2, and 3 set to 1.
Table 2-9. SLOT Assignments for Codec Port Interface I2S Mode 4
CODEC PORT INTERFACE DMA CHANNEL(S)
SERIAL DATA TIME SLOT NUMBER TIME SLOT NUMBER
LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL
SDOUT1 0 1 0 1
SDIN1 0 1 0 2
SDIN2 0 1 1 3
Table 2-10. SLOT Assignments for Codec Port Interface I2S Mode 5
CODEC PORT INTERFACE DMA CHANNEL(S)
SERIAL DATA TIME SLOT NUMBER TIME SLOT NUMBER
LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL
SDOUT1 0 1 0 1
SDIN2 0 1 0 1
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2.2.13.5 AIC Mode of Operation
AIC - audio interface circuit - is a standard adopted by Texas Instruments for interfacing digitized analog
data to a TI DSP. The bus is specifically tailored to be compatible with the serial ports supplied with most
TI DSP offerings. In later DSP offerings, these ports are referred to as McBSP ports.
The AIC standard has four serial interface modes - pulse mode, SPI mode 0, SPI mode 1, and frame
mode. The TAS1020B only supports the pulse mode of operation. (The pulse mode is so named because
of the one CSCLK period duration of the sync signal). Three options exist for the pulse mode - master
(frame sync is sourced by the codec), slave (frame sync is sourced by the TAS1020B), and
continuous-transfer master (data is transmitted and received continuously, and frame sync is sourced by
the codec). The TAS1020B directly supports the master and slave options. The continuous-transfer
master mode option does not allow secondary communication. The AIC standard covers this case by
specifying the use of a second data stream, synchronous with CSCLK, to directly program the internal
registers of the codec. The TAS1020B has no means of outputting such a second data stream. The
TAS1020B then can only support the continuous-transfer master mode option by the use of external logic,
whereby the CDATO line can be multiplexed between the AIC data terminal and the direct configuration
serial input terminal. Such a solution for implementing the continuous-transfer master mode option does
introduce the restriction that audio data and control data cannot be transmitted concurrently.
The AIC standard provides two options for requesting secondary communication - asserting an active-high
logic level on a separate line (FC) or setting the LSB of the 16-bit data word high. The latter option is only
available when the audio consists of 15-bit data words. The TAS1020B only supports the FC option. When
the codec port interface is set to the AIC mode, the TAS1020B CSCHNE pin (pin 32) sources FC.
Figure 2-7 shows the parameter settings for the AIC master or slave mode, and Section 2.2.13.1.2
provides detail on these settings. Table 2-11 shows the TAS1020B codec terminal assignments and the
respective signal names for the AIC mode of operation.
Table 2-11. Terminal Assignments for Codec Port
Interface AIC Mode 1
TERMINAL
AIC
NO. NAME
35 CSYNC FS O
37 CSCLK SCLK O
38 CDATO DOUT O
36 CDATI DIN I
34 CRESET RESET O
32 CSCHNE FC O
2.2.13.6 Bulk Mode
The TAS1020B supports bulk OUT data transactions through the codec port using one of the two
available DMA channels, but the codec port needs to be configured in AC '97 or general-purpose mode to
support bulk OUT transactions. AC '97 and the general-purpose mode are the only two modes of
operation that support bulk OUT transactions, as these are the only two modes that have mechanisms in
place to distinguish when valid data is or is not being output. AC '97 uses tag bits to indicate whether or
not data is valid in any given time slot. In the general-purpose mode, no sync pulse is output if no valid
data is available to be output. (In both AC '97 and the general-purpose mode, CPTBLK must be set to
logic 1 if tag bits or the sync pulse, respectively, are to indicate the presence of valid data). See
Section 2.2.7.3.3 for more detail on bulk OUT transactions using one of the two DMA channels.
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Data Line Stable:
Data Valid
Change of Data
Allowed
SDA
SCL
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2.2.14 I2C Interface
The TAS1020B has a bidirectional two-wire serial interface that can be used to access other ICs. This
serial interface is compatible with the I2C (Inter IC) bus protocol and supports both 100-kbps and 400-kbps
data transfer rates. The TAS1020B does not support all provisions of theI2C specification. The TAS1020B
can only serve as a master device on the I2C bus, but as a master device, the TAS1020B does not
support a multimaster bus environment (no bus arbitration), but can recognize wait state insertions on the
bus. The I2C interface on the TAS1020B is provided to allow access to I2C slave devices, including
EEPROMs and codecs. For example, if the application program code is stored in an EEPROM on the
PCB, then the MCU downloads the code from the EEPROM to the TAS1020B on-chip RAM using the I2C
interface. Another example is the control of a codec device that uses an I2S interface for audio data
transfers and an I2C interface for control register read/write access.
2.2.14.1 Data Transfers
The two-wire serial interface uses the serial clock signal, SCL, and the serial data signal, SDA. As stated
above, the TAS1020B is a master only device, and therefore, the SCL signal is an output only. The SDA
signal is a bidirectional signal that uses an open-drain output to allow the TAS1020B to be wire-ORed with
other devices that use open-drain or open-collector outputs.
All read and write data transfers on the serial bus are initiated by the TAS1020B. The TAS1020B is also
responsible for generating the clock signal used for all data transfers. The data is transferred on the bus
serially one bit at a time. However, the protocol requires that the address and data be transferred in byte
(8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the
bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with
the master device driving a start condition on the bus and ends with the master device driving a stop
condition on the bus.
The timing relationship between the SCL and SDA signals for each bit transferred on the bus is shown in
Figure 2-12. As shown, the SDA signal must be stable while the SCL signal is high, which also means that
the SDA signal can only change states while the SCL signal is low.
Figure 2-12. Bit Transfer on the I2C Bus
The timing relationship between the SCL and SDA signals for the start and stop conditions is shown in
Figure 2-13. As shown, the start condition is defined as a high-to-low transition of the SDA signal while the
SCL signal is high. Also as shown, the stop condition is defined as a low-to-high transition of the SDA
signal while the SCL signal is high.
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SDA
SCL
S
Start Condition
P
Stop Condition
S
Start Condition
MSB
Acknowledge
Not Acknowledge
9
Clock Pulse For
Acknowledge
1 2 8
Data Output By
Slave Device
Data Output By
TAS1020B
SDA
SDA
}
}
SCL
TAS1020B
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Figure 2-13. I2C START and STOP Conditions
When the TAS1020B is the device receiving data information, the TAS1020B acknowledges each byte
received by driving the SDA signal low during the acknowledge SCL period. During the acknowledge SCL
period, the slave device must stop driving the SDA signal. If the TAS1020B is unable to receive a byte, the
SDA signal is not driven low and is pulled high external to the TAS1020B device. Also, if the TAS1020B
has received the last byte of data, it signals an end of transmission to the slave device by issuing a not
acknowledge, rather than an acknowledge, following reception of the last byte. A high during the SCL
period indicates a not-acknowledge to the slave device. The acknowledge timing is shown in Figure 2-14.
Read and write data transfers by the TAS1020B device can be done using single byte or multiple byte
data transfers. Therefore, the actual transfer type used depends on the protocol required by the I2C slave
device being accessed.
Figure 2-14. TAS1020B Acknowledge on the I2C Bus
2.2.14.2 Single Byte Write
As shown is Figure 2-15, a single byte data write transfer begins with the master device transmitting a
start condition followed by the I2C device address and the read/write bit. The read/write bit determines the
direction of the data transfer. For a write data transfer, the read/write bit must be a 0. After receiving the
correct I2C device address and the read/write bit, the I2C slave device responds with an acknowledge bit.
Next, the TAS1020B transmits the address byte or bytes corresponding to the I2C slave device internal
memory address being accessed. After receiving the address byte, the I2C slave device again responds
with an acknowledge bit. Next, the TAS1020B device transmits the data byte to be written to the memory
address being accessed. After receiving the data byte, the I2C slave device again responds with an
acknowledge bit. Finally, the TAS1020B device transmits a stop condition to complete the single byte data
write transfer.
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A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Start Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I2C Device Address and
Read/Write Bit
Memory or Register Address Data Byte
SDA
D7 D6 D1 D0 ACK
Stop
Condition
Acknowledge
I2C Device Address and
Read/Write Bit
Memory or Register Address Last Data Byte
A6 A5 A1 A0 R/W ACK A7 A5 A1 A0 ACK D7 D6 D1 D0 ACK
Start Condition Acknowledge Acknowledge Acknowledge
SDA
First Data Byte
A6 A4 A3
Other
Data Bytes
A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I2C Device Address and
Read/Write Bit
Memory or Register Address Data Byte
SDA D7 D6 D1 D0 ACK
I2C Device Address and
Read/Write Bit
Repeat Start Condition
Not
Acknowledge
A1 A1 R/W
TAS1020B
SLES025B–JANUARY 2002–REVISED MAY 2011 www.ti.com
Figure 2-15. Single Byte Write Transfer
2.2.14.3 Multiple Byte Write
A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data
bytes are transmitted by the TAS1020B device to the I2C slave device as shown in Figure 2-16. After
receiving each data byte, the I2C slave device responds with an acknowledge bit.
Figure 2-16. Multiple Byte Write Transfer
2.2.14.4 Single Byte Read
As shown in Figure 2-17, a single byte data read transfer begins with the TAS1020B device transmitting a
start condition followed by the I2C device address and the read/write bit. For the data read transfer, both a
write followed by a read are actually performed. Initially, a write is performed to transfer the address byte
or bytes of the internal memory address to be read. As a result, the read/write bit must be a 0. After
receiving the I2C device address and the read/write bit, the I2C slave device responds with an
acknowledge bit. Also, after sending the internal memory address byte or bytes, the TAS1020B device
transmits another start condition followed by the I2C slave device address and the read/write bit again.
This time the read/write bit is a 1 indicating a read transfer. After receiving the I2C device address and the
read/write bit the I2C slave again responds with an acknowledge bit. Next, the I2C slave device transmits
the data byte from the memory address being read. After receiving the data byte, the TAS1020B device
transmits a not-acknowledge followed by a stop condition to complete the single byte data read transfer.
Figure 2-17. Single Byte Read Transfer
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A6 A0 ACK
Acknowledge
I2C Device Address and
Read/Write Bit
A6 A0 R/W ACK A4 A0 ACK R/W D7 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
Last Data Byte
SDA D7 D6 D1 D0 ACK
First Data Byte
Repeat Start
Condition
Not
Acknowledge
I2C Device Address and
Read/Write Bit
Memory or Register Address Other
Data Bytes
A7 A6 A7
TAS1020B
www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011
2.2.14.5 Multiple Byte Read
A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data
bytes are transmitted by the I2C slave device to the TAS1020B device as shown in Figure 2-18. Except for
the last data byte, the TAS1020B device responds with an acknowledge bit after receiving each data byte.
Figure 2-18. Multiple Byte Read Transfer
Copyright © 2002–2011, Texas Instruments Incorporated Detailed Description 65
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3 Electrical Specifications
3.1 Absolute Maximum Ratings(1)
over operating temperature range (unless otherwise noted)
DVDD Supply voltage range −0.5 to 3.6 V
VI Input voltage range 3.3-V TTL/LVCMOS −0.5 V to DVDD + 0.5 V
Continuous power dissipation See Section 3.2
TOp Operating free air temperature range 0°C to 70°C
TStg Storage temperature range
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3.2 Dissipation Ratings
PACKAGE TA ≤ 25°C DERATING FACTOR TA = 70°C POWER RATING ABOVE TA = 25°C POWER RATING
TQFP 0.923 W 10.256 mW/°C 0.461 W
3.3 Recommended Operating Conditions
MIN NOM MAX UNIT
DVDD Digital supply voltage 3 3.3 3.6 V
AVDD Analog supply voltage 3 3.3 3.6 V
VIH High-level input voltage CMOS inputs 0.7 DVDD V
VIL Low-level input voltage CMOS inputs 0 0.2 DVDD V
VI Input voltage CMOS inputs 0 DVDD V
VO Output voltage CMOS inputs 0 DVDD V
3.4 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage, GPIO port bits P3 [0-7] IOH = - 4 mA DVDD-0.5 V
VOL Low-level output voltage, GPIO port bits P3 [0-7] IOL = 4 mA 0.5 V
VOH High-level output voltage, GPIO port bits P1 [0-7] IOH = - 8 mA DVDD-0.5 V
VOL Low-level output voltage, GPIO port bits P1 [0-7] IOL = 8 mA 0.5 V
IOZ High-impedance output current ± 20 μA
Pullup disabled VI = VIL - 20
IIL Low-level input current μA
Enabled -100
Pullup disabled VI = VIH 20
IIH High-level input current μA
Enabled 20
CPU clock 12 MHz 45.9
mA
Digital supply voltage DVDD (3.3 V) CPU clock 24 MHz 50.9
IDD Suspend(1) 196 μA
Normal 14.7 mA
Analog supply voltage AVDD (3.3 V)
Suspend 24 nA
(1) In this 196 μA measurement, the bulk of suspend current (190 μA) is delivered to the USB cable through PUR pin. The remaining 6 μA
is consumed by the device. As described in section 7.2.3 of USB 1.1 specification, When computing suspend current, the current from
VBus through the pullup and pulldown resistors must be included.
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tw(L)
XINT
tr , tf
90%
10%
VO(CRS)
VOH
VOL
DM
DP
TAS1020B
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3.5 Timing Characteristics
3.6 Clock and Control Signals
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Internal 0.75 25
fMCLKO1 Clock frequency, MCLKO1 CL = 50 pF(1) MHz
MCLKI 0.625 25
Internal 0.75 25
fMCLKO2 Clock frequency, MCLKO2 CL = 50 pF(1) MHz
MCLKI 0.625 25
fMCLKI Clock frequency, MCLKI See (1) 5 25 MHz
tw(L) Pulse duration, XINT low CL = 50 pF 0.2 10 μs
(1) Worst case duty cycle is 45/55.
Figure 3-1. External Interrupt Timing Waveform
3.7 USB Signals When Sourced by TAS1020B
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
tr Transition rise time for DP or DM 4 20 ns
tf Transition fall time for DP or DM 4 20 ns
tRFM Rise/fall time matching (tr / tf) × 100 90% 110%
VO(CRS) Voltage output signal crossover 1.3 2 V
Figure 3-2. USB Differential Driver Timing Waveform
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tw1(H) tw1(L)
tcyc1
tw2(H) tw2(L)
tcyc2
BIT_CLK
SYNC
tsu th
BIT_CLK
tpd1
SYNC, SD_OUT
SD_IN
TAS1020B
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3.8 Codec Port Interface Signals (AC ’97 Modes)
TA = 25°C, DVDD = 3.3 V, AVDD = 3.3 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fBIT_CLK Frequency, BIT_CLK See (1) 12.288 MHz
tcyc1 Cycle time, BIT_CLK See (1) 81.4 ns
tw1(H) Pulse duration, BIT_CLK high See (1) 36 40.7 45 ns
tw1(L) Pulse duration, BIT_CLK low See (1) 36 40.7 45 ns
fSYNC Frequency, SYNC CL = 50 pF 48 kHz
tcyc2 Cycle time, SYNC CL = 50 pF 20.8 μs
tw2(H) Pulse duration, SYNC high CL = 50 pF 1.3 μs
tw2(L) Pulse duration, SYNC low CL = 50 pF 19.5 μs
tpd1 Propagation delay time, BIT_CLK rising edge to SYNC, SD_OUT CL = 50 pF 15 ns
tsu Setup time, SD_IN to BIT_CLK falling edge 10 ns
th Hold time, SD_IN from BIT_CLK falling edge 10 ns
(1) Worst case duty cycle is 45/55.
Figure 3-3. BIT_CLK and SYNC Timing Waveforms
Figure 3-4. SYNC, SD_IN, and SD_OUT Timing Waveforms
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tsu th
SCLK
LRCLK, SD_OUT
SD_IN
tpd
tcyc
tsu th
CSCLK
CSYNC, CDATO,
CSCHNE, CRESET
CDATI
tpd
tcyc
TAS1020B
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3.9 Codec Port Interface Signals (I2S Modes)
over recommended operating conditions (unless otherwise noted)
TEST CONDITIONS MIN MAX UNIT
fSCLK Frequency, SCLK CL = 50 pF (32)FS (64)FS MHz
tcyc Cycle time, SCLK CL = 50 pF(1) 1/(64)FS 1/(32)FS ns
tpd Propagation delay, SCLK falling edge to LRCLK and SDOUT CL = 50 pF 15 ns
tsu Setup time, SDIN to SCLK rising edge 10 ns
th Hold time, SDIN from SCLK rising edge 10 ns
(1) Worst case duty cycle is 45/55.
Figure 3-5. I2S Mode Timing Waveforms
3.10 Codec Port Interface Signals (General-Purpose Mode)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
fCSCLK Frequency, CSCLK CL = 50 pF 0.125 25 MHz
tcyc Cycle time, CSCLK CL = 50 pF(1) 0.040 8 μs
tpd Propagation delay, CSCLK to CSYNC, CDATO, CSCHNE and CRESET CL = 50 pF 15 ns
tsu Setup time, CDATI to CSCLK 10 ns
th Hold time, CDATI from CSCLK 10 ns
(1) The timing waveforms in Figure 3-6 show the CSYNC, CDATO, CSCHNE, and CRESET signals generated with the rising edge of the
clock and the CDATI signal sampled with the falling edge of the clock. The edge of the clock used is programmable. However, the
timing characteristics are the same regardless of which edge of the clock is used.
Figure 3-6. General-Purpose Mode Timing Waveforms
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tw(H) tw(L) tr tf
tsu1 tpd1
SCL
SDA
tsu2 th2 tsu3 tbuf
SCL
SDA
Start Condition Stop Condition
SCL 1 2 8 9
SDA OUT
SDA IN
TAS1020B
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3.11 I2C Interface Signals
over recommended operating conditions (unless otherwise noted)
STANDARD FAST MODE PARAMETER MODE UNIT
MIN MAX MIN MAX
fSCL Frequency, SCL 0 100 0 400 kHz
tw(H) Pulse duration, SCL high 4 0.6 μs
tw(L) Pulse duration, SCL low 4.7 1.3 μs
tr Rise time, SCL and SDA 1000 300 ns
tf Fall time, SCL and SDA 300 300 ns
tsu1 Setup time, SDA to SCL 250 100 ns
tpd1 Propagation delay, SCL to SDA (5-kΩ pullup resistor) 300 500 300 500 ns
tbuf Bus free time between stop and start condition 4.7 1.3 μs
tsu2 Setup time, SCL to start condition 4.7 0.6 μs
th2 Hold time, start condition to SCL 4 0.6 μs
tsu3 Setup time, SCL to stop condition 4 0.6 μs
CL Load capacitance for each bus line 400 400 pF
Figure 3-7. SCL and SDA Timing Waveforms
Figure 3-8. Start and Stop Conditions Timing Waveforms
Figure 3-9. Acknowledge Timing Waveform
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24C64
33
28
2
3
4
5
6
7
8
P1.4
P1.3
32
31
30
CDATI
CSYNC
TEST
EXTEN
MCLKI
PUR
DP
DM
27
26
29
9
10
11
12 25
1
P1.2
PLLFILO
DVSS
DVSS
TAS1020B
P1.5
P1.6
P1.7
CSCHNE
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
PLLFILI
XTALI
XTALO
SCL
SDA
MCLKO2
MCLKO1
CDATO
P1.1 CSCLK
P1.0
NC
DVDD
NC
P3.5
P3.4
P3.3
P3.1
P3.0
3.3 VD
3.3 VD
1 μF
3.3 VD
10 k!
VCC
WP
SCL
SDA GND
A2
3.09 k!
1000 pF
100 pF
AGND
3.3 VA
27 pF
XTAL
6 MHz
27 pF
AGND
MCLKO
A1
A0
DGND
DGND
3.3 VD
2 k!
Top Layer Ground Shield
Ferrite Bead
9 ! at 100 MHz
20 k! +
C1
C5
35
36
34
C3
C2
2 k!
C4
Voltage
Regulator
+
10 μF
16 V
C1
0.1 μF
C2
0.1 μF
DGND
C3
0.1 μF
C4
0.1 μF
3.3 VD (To TAS1020B Device Only)
1.0 !
1 μF
16 V
+
C5
0.1 μF
AGND
3.3 VA (To TAS1020B Device Only)
3.3 V
DGND
1.0 !
CRESET
MRESET
RSTO
P3.2/XINT
RESET
VREN
DVDD
AVDD
DVDD
DVSS AVSS
USB_CONN
27.4 W
27.4 W
15 kW
1.5 kW
PN2222A
(see Note E)
Data–
Data+
VCC
GND
VCC
TAS1020B
www.ti.com SLES025B–JANUARY 2002–REVISED MAY 2011
4 Application Information
A. If MCLKI and CSCHNE are not used, they must be connected to DGND.
B. Capacitors C1, C2, C3, C4, and C5 are as shown to indicate they must be mounted as close to the pins as possible.
C. NC on pins 20 and 22 means they must be left unconnected when running in normal mode.
D. Crystal load capacitors are shown as 27 pF, but recommendations of crystal manufactures should be followed.
E. Q1 and associated circuitry is required for USB back-voltage certification test.
Figure 4-1. Typical TAS1020B Device Connections
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5 8K ROM
The 8K ROM is mask-programmed as part of the TAS1020B manufacturing process. The ROM program
provides the boot behavior as discussed in Section 2.2.2. It also provides support functions for the user's
application. Source for the ROM image is provided in the TAS1020B Firmware Development Kit
(http://focus.ti.com/docs/toolsw/folders/print/tas1020fdk.html).
5.1 ROM Errata
It is not possible for an application that uses the ROM support functions to stall an invalid control
transaction that has a data stage.
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6 MCU Memory and Memory-Mapped Registers
This section describes the TAS1020B MCU memory configurations and operation. In general, the MCU
memory operation is the same as the industry standard 8052 MCU.
6.1 MCU Memory Space
The TAS1020B MCU memory is organized into three individual spaces: program memory, external data
memory, and internal data memory. All memory resources reside within the TAS1020B; the terms internal
and external refer to memory resources internal to and external to the MCU core residing in the
TAS1020B. The total address range for the program memory and the external data memory spaces is 64K
bytes each. The total address range for the internal data memory is 256 bytes.
The actual mapping of physical memory resources into these three individual spaces is dependent on
which operating mode is active, boot loader mode or normal mode. The operating mode is determined by
the setting of the SDW bit in the MCU memory configuration register. At power turnon, or after a master
reset, the SDW bit is reset and the boot loader mode is active. In this mode, and 8K ROM resource within
the TAS1020B is mapped to program space beginning at address 0000h. This same 8K ROM is also
mapped to program space beginning at address 8000h. The TAS1020B uses the 8K boot ROM as the
program memory when in the boot loader mode. The boot ROM program code downloads the application
program code from a nonvolatile memory (EEPROM) on the peripheral PCB, and writes the code to a 6K
RAM resource internal to the TAS1020B. In the boot loader mode, this 6K RAM resource is mapped to the
external data memory space starting at address 0000h. (If a valid EEPROM resource is not available, the
TAS1020B initializes in the DFU program mode and requires a download of application code to
RAM—see Section 2.2.2.2). After downloading the application program code to the 6K RAM resource, the
boot ROM enables the normal operating mode by setting the ROM disable (SDW) bit to enable program
code execution from the 6K RAM instead of the boot ROM. In the normal operating mode, the boot ROM
is still mapped to program memory space starting at address 8000h, but the 6K RAM resource is now
mapped to program memory space beginning at address 0000h. Also, in the normal operating mode, the
RAM resource becomes a read-only memory resource that cannot be written to. Refer to Figure 6-1 and
Figure 6-2 for details.
In the normal operating mode, the external data memory space contains the data buffers for the USB
endpoints, the configuration blocks for the USB endpoints, the setup data packet buffer for the USB
control endpoint, and memory-mapped registers. The data buffers for the USB endpoints, the
configuration blocks for the USB endpoints and the setup data packet buffer for the USB control endpoints
are all implemented in RAM, and this RAM resource is separate from the 6K RAM resource used to house
the application code. The memory-mapped registers used for control and status registers are implemented
in hardware with flip-flops. The data buffers for the USB endpoints total 1304 bytes, the configuration
blocks for the USB endpoints total 128 bytes, the setup packet buffer for the USB control endpoint is 8
bytes, and the memory-mapped-register space is 80 bytes. The total external data memory space used for
these blocks of memory then is 1520 bytes.
6.2 Internal Data Memory
The internal data memory space is a total of 256 bytes of RAM, which includes the 128 bytes of special
function registers (SFR) space. The internal data memory space is mapped in accordance with the
industry standard 8052 MCU. The internal data memory space is mapped from 00h to FFh with the SFRs
mapped from 80h to FFh. The lower 128 bytes are accessible with both direct and indirect addressing.
However, the upper 128 bytes, which is the SFR space, is only accessible with direct addressing. Note
that the internal data memory space is separate and distinct from the external data memory space, and
although both spaces begin at address 0000h, there is no overlap.
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Program Memory
FFFFh
24K − Reserved
A000h
9FFFh
Boot ROM (8K)
24K − Reserved
2000h
1FFFh
Boot ROM (8K)
(Boot loader and library
0000h of USB functions)
External Data Memory
FFFFh
Memory Mapped Registers
(80 Bytes)
FFB0h
FFAFh
USB End-Point Configuration
Blocks and Buffer Space
(1440 Bytes)
FA10h
FA0Fh
58,000 Bytes − Reserved
1780h
177Fh
Code RAM
(6016 Bytes)
(Read/Write)
(Loaded from EEPROM
0000h by boot loader)
8000h
7FFFh
TAS1020B
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Figure 6-1. Boot Loader Mode Memory Map
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Program Memory
FFFFh
24K − Reserved
A000h
9FFFh
Boot ROM (8K)
26752 Bytes
0000h
External Data Memory
FFFFh
Memory Mapped Registers
(80 Bytes)
FFB0h
FFAFh
USB End-Point Configuration
Blocks and Buffer Space
(1440 Bytes)
FA10h
FA0Fh
64016 Bytes − Reserved
1780h
177Fh
Code RAM
(6016 Bytes)
0000h
8000h
7FFFh
(Read/Write)
TAS1020B
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Figure 6-2. Normal Operating Mode Memory Map
6.3 External MCU Mode Memory Space
When using an external MCU for firmware development, only the USB configuration blocks, the USB
buffer space, and the memory-mapped registers are accessible by the external MCU. See Section 6.4 for
details. In this mode, only address lines A0 to A10 are input to the TAS1020B device from the external
MCU. Therefore, the USB buffer space and the memory-mapped registers in the external data memory
space are not fully decoded since all sixteen address lines are not available. Hence, the USB buffer space
and the memory-mapped registers are actually accessible at any 2K boundary within the total 64K
external data memory space of the external MCU. As a result, when using the TAS1020B in the external
MCU mode, nothing can be mapped to the external data memory space of the external MCU except the
USB buffer space and the memory-mapped registers of the TAS1020B device.
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6.4 USB Endpoint Configuration Blocks and Data Buffer Space
6.4.1 USB Endpoint Configuration Blocks
The USB endpoint configuration space contains 16 8-byte blocks that define configuration, buffer location,
buffer size, and data count for the 16 (8 input and 8 output) USB endpoints. The MCU, UBM, and DMA all
have access to these configuration blocks.
Each of the 16 endpoints in the TAS1020B can be configured as a USB pipe endpoint by initializing the
block configuration register assigned to each endpoint. The location of the endpoint X and Y data buffers
for each endpoint is set by the value programmed into the X and Y buffer base address registers. Base
addresses are octet (8-byte) aligned. The size of the X and Y buffers is set by initializing the buffer size
register. The size of the X and Y buffers must be greater than or equal to the USB packet size associated
with the endpoint. For Isochronous endpoints, the buffer size defines the size of the single circular buffer.
For IN transactions, the X and Y data count registers assigned to each endpoint are set by the USB buffer
manager (UBM) to register the size of the new data packet just received. For OUT transactions, the X and
Y data count registers assigned to each endpoint are set by the DMA logic or the MCU to register the size
of the data packet to be output. For control, interrupt, and bulk transactions, the data count is the number
of samples per transaction.
6.4.2 Data Buffer Space
The endpoint data buffer space (1304 bytes) provides rate buffering between the data traffic on the USB
bus and data traffic to and from the codecs attached to the TAS1020B. Buffers are defined in this space
by base address pointers and size descriptors in the USB endpoint configuration blocks. The MCU also
has access to this space.
In order to conserve RAM memory resources on the TAS1020B, several USB-specific routines have been
included in the firmware resident in the on-chip ROM. These ROM support functions are detailed in
Section 2.2.2.7. To provide temporary variable storage for these ROM support functions, locations FA10h
through FA63h (84 bytes) of the 1304 bytes of data buffer space are reserved for use by the ROM support
functions. This then leaves 1220 bytes for the endpoint buffer memories, which service applications up to
6 channels, 48 kHz sampling rate with 16 bits per sample or 4 channels, 48-kHz sampling rate with 24 bits
per sample. (If the ROM support functions are not used, the entire block of 1304 bytes can be assigned to
endpoint buffer memories.)
The values entered into the X and Y buffer base address registers are offset addresses. The lower
memory address (or Base address) of a given X (Y) buffer is determined by adding the value in the base
address register (multiplied by 8) to the base address of the block of memory assigned to the X and Y
buffers. For the TAS1020B, this base address is FA10h. However, the base address of the TUSB3200
members of the family of USB streaming audio controllers, of which the TAS1020B is also a member, is
F800h. To maintain software compatibility between family members, the value entered into the base
address register for the TAS1020B (as well as the other family members) must be the offset from the base
address F800h. For example, assume the X buffer for IN endpoint 3 is to be established starting at
address FA60h. For the TAS1020B, the offset of this address from the FA10h base address of the block
of memory assigned to the X and Y buffers is 50h. Nevertheless, the value entered into the X buffer base
address for IN endpoint 3 must be 4Ch, because F800h + 8 × 4Ch = FA60h.
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External Data Memory
Memory Mapped Registers
(80 Bytes)
Endpoint Configuration Blocks
(128 Bytes)
Setup Data Packet Buffer
(8 Bytes) (see Note A)
Endpoint Data Buffers
(1220 Bytes)
FFFFh
FFB0h
FFAFh
FF30h
FF2Fh
FF28h
FF27h
FA10h
DMA Access
DMA Access
MCU Access
UBM Access
FA64h
FA63h ROM Support
(84 Bytes)
TAS1020B
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A. See Section 6.4.5.
Figure 6-3. USB Endpoint Configuration Blocks and Buffer Space Memory Map
Table 6-1. USB Endpoint Configuration Blocks Address Map
ADDRESS MNEMONIC NAME
FFAFh OEPDCNTY0 OUT endpoint 0 - Y buffer data count byte
FFAEh Reserved Reserved for future use
FFADh OEPBBAY0 OUT endpoint 0 - Y buffer base address byte
FFACh Reserved Reserved for future use
FFABh OEPDCNTX0 OUT endpoint 0 - X buffer data count byte
FFAAh OEPBSIZ0 OUT endpoint 0 - X and Y buffer size byte
FFA9h OEPBBAX0 OUT endpoint 0 - X buffer base address byte
FFA8h OEPCNF0 OUT endpoint 0 - configuration byte
FFA7h OEPDCNTY1 OUT endpoint 1 - Y buffer data count byte
FFA6h Reserved Reserved for future use
FFA5h OEPBBAY1 OUT endpoint 1 - Y buffer base address byte
FFA4h Reserved Reserved for future use
FFA3h OEPDCNTX1 OUT endpoint 1 - X buffer data count byte
FFA2h OEPBSIZ1 OUT endpoint 1 - X and Y buffer size byte
FFA1h OEPBBAX1 OUT endpoint 1 - X buffer base address byte
FFA0h OEPCNF1 OUT endpoint 1 - configuration byte
FF9Fh OEPDCNTY2 OUT endpoint 2 - Y buffer data count byte
FF9Eh Reserved Reserved for future use
FF9Dh OEPBBAY2 OUT endpoint 2 - Y buffer base address byte
FF9Ch Reserved Reserved for future use
FF9Bh OEPDCNTX2 OUT endpoint 2 - X buffer data count byte
FF9Ah OEPBSIZ2 OUT endpoint 2 - X and Y buffer size byte
FF99h OEPBBAX2 OUT endpoint 2 - X buffer base address byte
FF98h OEPCNF2 OUT endpoint 2 - configuration byte
FF97h OEPDCNTY3 OUT endpoint 3 - Y buffer data count byte
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Table 6-1. USB Endpoint Configuration Blocks Address Map (continued)
ADDRESS MNEMONIC NAME
FF96h Reserved Reserved for future use
FF95h OEPBBAY3 OUT endpoint 3 - Y buffer base address byte
FF94h Reserved Reserved for future use
FF93h OEPDCNTX3 OUT endpoint 3 - X buffer data count byte
FF92h OEPBSIZ3 OUT endpoint 3 - X and Y buffer size byte
FF91h OEPBBAX3 OUT endpoint 3 - X buffer base address byte
FF90h OEPCNF3 OUT endpoint 3 - configuration byte
FF8Fh OEPDCNTY4 OUT endpoint 4 - Y buffer data count byte
FF8Eh Reserved Reserved for future use
FF8Dh OEPBBAY4 OUT endpoint 4 - Y buffer base address byte
FF8Ch Reserved Reserved for future use
FF8Bh OEPDCNTX4 OUT endpoint 4 - X buffer data count byte
FF8Ah OEPBSIZ4 OUT endpoint 4 - X and Y buffer size byte
FF89h OEPBBAX4 OUT endpoint 4 - X buffer base address byte
FF88h OEPCNF4 OUT endpoint 4 - configuration byte
FF87h OEPDCNTY5 OUT endpoint 5 - Y buffer data count byte
FF86h Reserved Reserved for future use
FF85h OEPBBAY5 OUT endpoint 5 - Y buffer base address byte
FF84h Reserved Reserved for future use
FF83h OEPDCNTX5 OUT endpoint 5 - X buffer data count byte
FF82h OEPBSIZ5 OUT endpoint 5 - X and Y buffer size byte
FF81h OEPBBAX5 OUT endpoint 5 - X Buffer Base Address Byte
FF80h OEPCNF5 OUT endpoint 5 - configuration byte
FF7Fh OEPDCNTY6 OUT endpoint 6 - Y buffer data count byte
FF7Eh Reserved Reserved for future use
FF7Dh OEPBBAY6 OUT endpoint 6 - Y buffer base address byte
FF7Ch Reserved Reserved for future use
FF7Bh OEPDCNTX6 OUT endpoint 6 - X buffer data count byte
FF7Ah OEPBSIZ6 OUT endpoint 6 - X and Y buffer size byte
FF79h OEPBBAX6 OUT endpoint 6 - X buffer base address byte
FF78h OEPCNF6 OUT endpoint 6 - configuration byte
FF77h OEPDCNTY7 OUT endpoint 7 - Y buffer data count byte
FF76h Reserved Reserved for future use
FF75h OEPBBAY7 OUT endpoint 7 - Y buffer base address byte
FF74h Reserved Reserved for future use
FF73h OEPDCNTX7 OUT endpoint 7 - X buffer data count byte
FF72h OEPBSIZ7 OUT endpoint 7 - X and Y buffer size byte
FF71h OEPBBAX7 OUT endpoint 7 - X buffer base address byte
FF70h OEPCNF7 OUT endpoint 7 - configuration byte
FF6Fh IEPDCNTY0 IN endpoint 0 - Y buffer data count byte
FF6Eh Reserved Reserved for future use
FF6Dh IEPBBAY0 IN endpoint 0 - Y buffer base address byte
FF6Ch Reserved Reserved for future use
FF6Bh IEPDCNTX0 IN endpoint 0 - X buffer data count byte
FF6Ah IEPBSIZ0 IN endpoint 0 - X and Y buffer size byte
FF69h IEPBBAX0 IN endpoint 0 - X buffer base address byte
FF68h IEPCNF0 IN endpoint 0 - configuration byte
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Table 6-1. USB Endpoint Configuration Blocks Address Map (continued)
ADDRESS MNEMONIC NAME
FF67h IEPDCNTY1 IN endpoint 1 - Y buffer data count byte
FF66h Reserved Reserved for future use
FF65h IEPBBAY1 IN endpoint 1 - Y buffer base address byte
FF64h Reserved Reserved for future use
FF63h IEPDCNTX1 IN endpoint 1 - X buffer data count byte
FF62h IEPBSIZ1 IN endpoint 1 - X and Y buffer size byte
FF61h IEPBBAX1 IN endpoint 1 - X buffer base address byte
FF60h IEPCNF1 IN endpoint 1 - configuration byte
FF5Fh IEPDCNTY2 IN endpoint 2 - Y buffer data count byte
FF5Eh Reserved Reserved for future use
FF5Dh IEPBBAY2 IN endpoint 2 - Y buffer base address byte
FF5Ch Reserved Reserved for future use
FF5Bh IEPDCNTX2 IN endpoint 2 - X buffer data count byte
FF5Ah IEPBSIZ2 IN endpoint 2 - X and Y buffer size byte
FF59h IEPBBAX2 IN endpoint 2 - X buffer base address byte
FF58h IEPCNF2 IN endpoint 2 - configuration byte
FF57h IEPDCNTY3 IN endpoint 3 - Y buffer data count byte
FF56h Reserved Reserved for future use
FF55h IEPBBAY3 IN endpoint 3 - Y buffer base address byte
FF54h Reserved Reserved for future use
FF53h IEPDCNTX3 IN endpoint 3 - X buffer data count byte
FF52h IEPBSIZ3 IN endpoint 3 - X and Y buffer size byte
FF51h IEPBBAX3 IN endpoint 3 - X buffer base address byte
FF50h IEPCNF3 IN endpoint 3 - configuration byte
FF4Fh IEPDCNTY4 IN endpoint 4 - Y buffer data count byte
FF4Eh Reserved Reserved for future use
FF4Dh IEPBBAY4 IN endpoint 4 - Y buffer base address byte
FF4Ch Reserved Reserved for future use
FF4Bh IEPDCNTX4 IN endpoint 4 - X buffer data count byte
FF4Ah IEPBSIZ4 IN endpoint 4 - X and Y buffer size byte
FF49h IEPBBAX4 IN endpoint 4 - X buffer base address byte
FF48h IEPCNF4 IN endpoint 4 - configuration byte
FF47h IEPDCNTY5 IN endpoint 5 - Y buffer data count byte
FF46h Reserved Reserved for future use
FF45h IEPBBAY5 IN endpoint 5 - Y buffer base address byte
FF44h Reserved Reserved for future use
FF43h IEPDCNTX5 IN endpoint 5 - X buffer data count byte
FF42h IEPBSIZ5 IN endpoint 5 - X and Y buffer size byte
FF41h IEPBBAX5 IN endpoint 5 - X buffer base address byte
FF40h IEPCNF5 IN endpoint 5 - configuration byte
FF3Fh IEPDCNTY6 IN endpoint 6 - Y buffer data count byte
FF3Eh Reserved Reserved for future use
FF3Dh IEPBBAY6 IN endpoint 6 - Y buffer base address byte
FF3Ch Reserved Reserved for future use
FF3Bh IEPDCNTX6 IN endpoint 6 - X buffer data count byte
FF3Ah IEPBSIZ6 IN endpoint 6 - X and Y buffer size byte
FF39h IEPBBAX6 IN endpoint 6 - X buffer base address byte
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Table 6-1. USB Endpoint Configuration Blocks Address Map (continued)
ADDRESS MNEMONIC NAME
FF38h IEPCNF6 IN endpoint 6 - configuration byte
FF37h IEPDCNTY7 IN endpoint 7 - Y buffer data count byte
FF36h Reserved Reserved for future use
FF35h IEPBBAY7 IN endpoint 7 - Y buffer base address byte
FF34h Reserved Reserved for future use
FF33h IEPDCNTX7 IN endpoint 7 - X buffer data count byte
FF32h IEPBSIZ7 IN endpoint 7 - X and Y buffer size byte
FF31h IEPBBAX7 IN endpoint 7 - X buffer base address byte
FF30h IEPCNF7 IN endpoint 7 - configuration byte
6.4.3 USB OUT Endpoint Configuration Bytes
This section describes the individual bytes in the USB endpoint configuration blocks for the OUT
endpoints. A set of 8 bytes is used for the control and operation of each USB OUT endpoint. In addition to
the USB control endpoint, the TAS1020B supports up to a total of seven OUT endpoints.
6.4.3.1 USB OUT Endpoint - Y Buffer Data Count Byte (OEPDCNTYx)
The USB OUT endpoint Y buffer data count byte contains the 7-bit value used to specify the amount of
data received in a data packet from the host PC. The no acknowledge status bit is also contained in this
byte.
Bit 7 6 5 4 3 2 1 0
Mnemonic NACK DCNTY6 DCNTY5 DCNTY4 DCNTY3 DCNTY2 DCNTY1 DCNTY0
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
The no acknowledge status bit is set to a 1 by the UBM at the end of a successful
USB OUT transaction to this endpoint to indicate that the USB endpoint Y buffer
contains a valid data packet and that the Y buffer data count value is valid. For
control, interrupt, or bulk endpoints, when this bit is set to a 1, all subsequent
transactions to the endpoint result in a NACK handshake response to the host PC.
7 NACK No acknowledge Also for control, interrupt, and bulk endpoints to enable this endpoint to receive
another data packet from the host PC, this bit must be cleared to a 0 by the MCU. For
isochronous endpoints, a NACK handshake response to the host PC is not allowed.
Therefore, the UBM ignores this bit in reference to receiving the next data packet.
However, the MCU or DMA must clear this bit before reading the data packet from the
buffer.
The Y buffer data count value is set by the UBM when a new data packet is written to
the Y buffer for the OUT endpoint. The 7-bit value is set to the number of bytes in the
data packet for control, interrupt or bulk endpoint transfers and is set to the number of
6:0 DCNTY(6:0) Y Buffer data count samples in the data packet for isochronous endpoint transfers. To determine the
number of samples in the data packet for isochronous transfers, the bytes per sample
value in the configuration byte is used. The data count value is read by the MCU or
DMA to obtain the data packet size.
6.4.3.2 USB OUT Endpoint - Y Buffer Base Address Byte (OEPBBAYx)
The USB OUT endpoint Y buffer base address byte contains the 8-bit value used to specify the base
memory location for the Y data buffer for a particular USB OUT endpoint.
Bit 7 6 5 4 3 2 1 0
Mnemonic BBAY10 BBAY9 BBAY8 BBAY7 BBAY6 BBAY5 BBAY4 BBAY3
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
The Y buffer base address value is set by the MCU to program the base address
7:0 BBAY(10:3) Y Buffer base address location in memory to be used for the Y data buffer. A total of 11 bits is used to specify the base address location. This byte specifies the most significant 8 bits of the
address. All 0s are used by the hardware for the three least significant bits.
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6.4.3.3 USB OUT Endpoint - X Buffer Data Count Byte (OEPDCNTXx)
The USB OUT endpoint X buffer data count byte contains the 7-bit value used to specify the amount of
data received in a data packet from the host PC. The no acknowledge status bit is also contained in this
byte.
Bit 7 6 5 4 3 2 1 0
Mnemonic NACK DCNTX6 DCNTX5 DCNTX4 DCNTX3 DCNTX2 DCNTX1 DCNTX0
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
The no acknowledge status bit is set to a 1 by the UBM at the end of a successful
USB OUT transaction to this endpoint to indicate that the USB endpoint X buffer
contains a valid data packet and that the X buffer data count value is valid. For
control, interrupt, or bulk endpoints, when this bit is set to a 1, all subsequent
transactions to the endpoint result in a NACK handshake response to the host PC.
7 NACK No acknowledge Also for control, interrupt, and bulk endpoints to enable this endpoint to receive
another data packet from the host PC, this bit must be cleared to a 0 by the MCU. For
isochronous endpoints, a NACK handshake response to the host PC is not allowed.
Therefore, the UBM ignores this bit in reference to receiving the next data packet.
However, the MCU or DMA must clear this bit before reading the data packet from the
buffer.
The X buffer data count value is set by the UBM when a new data packet is written to
the X buffer for the OUT endpoint. The 7-bit value is set to the number of bytes in the
data packet for control, interrupt, or bulk endpoint transfers and is set to the number of
6:0 DCNTX(6:0) X Buffer data count samples in the data packet for isochronous endpoint transfers. To determine the
number of samples in the data packet for isochronous transfers, the bytes per sample
value in the configuration byte is used. The data count value is read by the MCU or
DMA to obtain the data packet size.
6.4.3.4 USB OUT Endpoint - X and Y Buffer Size Byte (OEPBSIZx)
The USB OUT endpoint X and Y buffer size byte contains the 8-bit value used to specify the size of the
two data buffers to be used for this endpoint.
Bit 7 6 5 4 3 2 1 0
Mnemonic BSIZ7 BSIZ6 BSIZ5 BSIZ4 BSIZ3 BSIZ2 BSIZ1 BSIZ0
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
For control, interrupt, and bulk transactions, the X and Y buffer size value is set by the
MCU to program the size of the X and Y data packet buffers. Both buffers are
7:0 BSIZ(7:0) Buffer size programmed to the same size based on this value. This value is in 8-byte units. For example, a value of 18h results in the size of the X and Y buffers each being set to
192 bytes. For isochronous transactions, the buffer size sets the size of the single
circular buffer.
6.4.3.5 USB OUT Endpoint - X Buffer Base Address Byte (OEPBBAXx)
The USB OUT endpoint X buffer base address byte contains the 8-bit value used to specify the base
memory location for the X data buffer for a particular USB OUT endpoint.
Bit 7 6 5 4 3 2 1 0
Mnemonic BBAX10 BBAX9 BBAX8 BBAX7 BBAX6 BBAX5 BBAX4 BBAX3
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
The X buffer base address value is set by the MCU to program the base address
7:0 BBAX(10:3) X Buffer base address location in memory to be used for the X data buffer. A total of 11 bits is used to specify the base address location. This byte specifies the most significant 8 bits of the
address. All 0s are used by the hardware for the three least significant bits.
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6.4.3.6 USB OUT Endpoint - Configuration Byte (OEPCNFx)
The USB OUT endpoint configuration byte contains the various bits used to configure and control the
endpoint. Note that the bits in this byte take on different functionality based on the type of endpoint
defined. The control, interrupt, and bulk endpoints function differently than the isochronous endpoints.
6.4.3.6.1 USB OUT Endpoint Configuration Byte Settings—Control, interrupt, or Bulk Transactions
This section defines the functionality of the bits in the USB OUT endpoint configuration byte for control,
interrupt, and bulk endpoints.
Bit 7 6 5 4 3 2 1 0
Mnemonic OEPEN ISO TOGGLE DBUF STALL OEPIE — —
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
7 OEPEN Endpoint enable The endpoint enable bit is set to 1 by the MCU to enable the OUT endpoint.
The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a
6 ISO Isochronous endpoint particular OUT endpoint for isochronous transactions. This bit must be cleared to a 0 by the MCU to use a particular OUT endpoint for control, interrupt, or bulk
transactions.
The toggle bit is controlled by the UBM and is toggled at the end of a successful out
5 TOGGLE Toggle data stage transaction if a valid data packet is received and the data packet PID
matches the expected PID.
The double buffer mode bit is set to 1 by the MCU to enable the use of both the X and
4 DBUF Double buffer mode Y data packet buffers for USB transactions to a particular OUT endpoint. This bit must be cleared to a 0 by the MCU to use the single buffer mode. In the single buffer mode,
only the X buffer is used.
The stall bit is set to 1 by the MCU to stall endpoint transactions. When this bit is set,
the hardware automatically returns a stall handshake to the host PC for any
transaction received for the endpoint. An exception is the control endpoint setup stage
transaction, which must always received. This requirement allows a
3 STALL Stall Clear_Feature_Stall request to be received from the host PC. Control endpoint data and status stage transactions however can be stalled. The stall bit is cleared to a 0 by
the MCU if a Clear_Feature_Stall request or a USB reset is received from the host
PC. For a control write transaction, if the amount of data received is greater than
expected, the UBM sets the stall bit to a 1 to stall the endpoint. When the stall bit is
set to a 1 by the UBM, the USB OUT endpoint 0 interrupt is generated.
2 OEPIE Interrupt enable The interrupt enable bit is set to a 1 by the MCU to enable the OUT endpoint interrupt. See Section 6.5.7.1 for details on the OUT endpoint interrupts.
1:0 — Reserved Reserved for future use
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6.4.3.6.2 USB OUT Endpoint Configuration Byte Settings—Isochronous Transactions
This section defines the functionality of the bits in the USB OUT endpoint configuration byte for
isochronous endpoints.
Bit 7 6 5 4 3 2 1 0
Mnemonic OEPEN ISO OVF BPS4 BPS3 BPS2 BPS1 BPS0
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
7 OEPEN Endpoint enable The endpoint enable bit is set to a 1 by the MCU to enable the OUT endpoint.
The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a
6 ISO Isochronous endpoint particular OUT endpoint for isochronous transactions. This bit must be cleared to a 0 by the MCU for a particular OUT endpoint to be used for control, interrupt, or bulk
transactions.
The overflow bit is set to a 1 by the UBM to indicate a buffer overflow condition has
5 OVF Overflow occurred. This bit is used for diagnostic purposes only and is not used for normal
operation. This bit can only be cleared to a 0 by the MCU.
The bytes per sample bits are used to define the number of bytes per isochronous
data sample. In other words, the total number of bytes in an entire audio codec frame.
4:0 BPS(4:0) Bytes per sample For example, a PCM 16-bit stereo audio data sample consists of 4 bytes. There are two bytes of left channel data and two bytes of right channel data. For a four channel
system using 16-bit data, the total number of bytes is 8, which is the isochronous data
sample size.00h = 1 byte, 01h = 2 bytes, …, 1Fh = 32 bytes
6.4.4 USB IN Endpoint Configuration Bytes
This section describes the individual bytes in the USB endpoint configuration blocks for the IN endpoints.
A set of 8 bytes is used for the control and operation of each USB IN endpoint. In addition to the USB
control endpoint, the TAS1020B supports up to a total of seven IN endpoints.
6.4.4.1 USB IN Endpoint - Y Buffer Data Count Byte (IEPDCNTYx)
The USB IN endpoint Y buffer data count byte contains the 7-bit value used to specify the amount of data
to be transmitted in a data packet to the host PC. The no acknowledge status bit is also contained in this
byte.
Bit 7 6 5 4 3 2 1 0
Mnemonic NACK DCNTY6 DCNTY5 DCNTY4 DCNTY3 DCNTY2 DCNTY1 DCNTY0
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
The no acknowledge status bit is set to a 1 by the UBM at the end of a successful
USB IN transaction to this endpoint to indicate that the USB endpoint Y buffer is
empty. For control, interrupt, or bulk endpoints, when this bit is set to a 1, all
subsequent transactions to the endpoint result in a NACK handshake response to the
7 NACK No acknowledge host PC. Also for control, interrupt, and bulk endpoints to enable this endpoint to transmit another data packet to the Host PC, this bit must be cleared to a 0 by the
MCU. For isochronous endpoints, a NACK handshake response to the host PC is not
allowed. Therefore, the UBM ignores this bit in reference to sending the next data
packet. However, the MCU or DMA must clear this bit after writing a data packet to the
buffer.
The Y buffer data count value is set by the MCU or DMA when a new data packet is
written to the Y buffer for the IN endpoint. The 7-bit value is set to the number of bytes
6:0 DCNTY(6:0) Y Buffer data count in the data packet for control, interrupt, or bulk endpoint transfers and is set to the number of samples in the data packet for isochronous endpoint transfers. To
determine the number of samples in the data packet for isochronous transfers, the
bytes per sample value in the configuration byte is used.
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6.4.4.2 USB IN Endpoint - Y Buffer Base Address Byte (IEPBBAYx)
The USB IN endpoint Y buffer base address byte contains the 8-bit value used to specify the base
memory location for the Y data buffer for a particular USB IN endpoint.
Bit 7 6 5 4 3 2 1 0
Mnemonic BBAY10 BBAY9 BBAY8 BBAY7 BBAY6 BBAY5 BBAY4 BBAY3
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
The Y buffer base address value is set by the MCU to program the base address
7:0 BBAY(10:3) Y Buffer base address location in memory to be used for the Y data buffer. A total of 11 bits is used to specify the base address location. This byte specifies the most significant 8 bits of the
address. All 0s are used by the hardware for the three least significant bits.
6.4.4.3 USB IN Endpoint - X Buffer Data Count Byte (IEPDCNTXx)
The USB IN endpoint X buffer data count byte contains the 7-bit value used to specify the amount of data
received in a data packet from the host PC. The no acknowledge status bit is also contained in this byte.
Bit 7 6 5 4 3 2 1 0
Mnemonic NACK DCNTX6 DCNTX5 DCNTX4 DCNTX3 DCNTX2 DCNTX1 DCNTX0
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
The no acknowledge status bit is set to a 1 by the UBM at the end of a successful
USB IN transaction to this endpoint to indicate that the USB endpoint X buffer is
empty. For control, interrupt, or bulk endpoints, when this bit is set to a 1, all
subsequent transactions to the endpoint result in a NACK handshake response to the
7 NACK No acknowledge host PC. Also for control, interrupt, and bulk endpoints to enable this endpoint to transmit another data packet to the host PC, this bit must be cleared to a 0 by the
MCU. For isochronous endpoints, a NACK handshake response to the host PC is not
allowed. Therefore, the UBM ignores this bit in reference to sending the next data
packet. However, the MCU or DMA must clear this bit after writing a data packet to the
buffer.
The X buffer data count value is set by the MCU or DMA when a new data packet is
written to the X buffer for the IN endpoint. The 7-bit value is set to the number of bytes
6:0 DCNTX(6:0) X Buffer data count in the data packet for control, interrupt, or bulk endpoint transfers and is set to the number of samples in the data packet for isochronous endpoint transfers. To
determine the number of samples in the data packet for isochronous transfers, the
bytes per sample value in the configuration byte is used.
6.4.4.4 USB IN Endpoint - X and Y Buffer Size Byte (IEPBSIZx)
The USB IN endpoint X and Y buffer size byte contains the 8-bit value used to specify the size of the two
data buffers to be used for this endpoint.
Bit 7 6 5 4 3 2 1 0
Mnemonic BSIZ7 BSIZ6 BSIZ5 BSIZ4 BSIZ3 BSIZ2 BSIZ1 BSIZ0
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
For control, interrupt, and bulk transactions, the X and Y buffer size value is set by the
MCU to program the size of the X and Y data packet buffers. Both buffers are
7 BSIZ(7:0) Buffer size programmed to the same size based on this value. This value should be in 8 byte units. For example, a value of 18h results in the size of the X and Y buffers each
being set to 192 bytes. For isochronous transactions, the buffer size sets the size of
the single circular buffer.
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6.4.4.5 USB IN Endpoint - X Buffer Base Address Byte (IEPBBAXx)
The USB IN endpoint X buffer base address byte contains the 8-bit value used to specify the base
memory location for the X data buffer for a particular USB IN endpoint.
Bit 7 6 5 4 3 2 1 0
Mnemonic BBAX10 BBAX9 BBAX8 BBAX7 BBAX6 BBAX5 BBAX4 BBAX3
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
The X buffer base address value is set by the MCU to program the base address
7:0 BBAX(10:3) X Buffer base address location in memory to be used for the X data buffer. A total of 11 bits is used to specify the base address location. This byte specifies the most significant 8 bits of the
address. All 0s are used by the hardware for the three least significant bits.
6.4.4.6 USB IN Endpoint - Configuration Byte (IEPCNFx)
The USB IN endpoint configuration byte contains the various bits used to configure and control the
endpoint. Note that the bits in this byte take on different functionality based on the type of endpoint
defined. Basically, the control, interrupt and bulk endpoints function differently than the isochronous
endpoints.
6.4.4.6.1 USB IN Endpoint Configuration Byte Settings - Control, Interrupt or Bulk Transactions
This section defines the functionality of the bits in the USB IN endpoint configuration byte for control,
interrupt, and bulk endpoints.
Bit 7 6 5 4 3 2 1 0
Mnemonic IEPEN ISO TOGGLE DBUF STALL IEPIE — —
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
7 IEPEN Endpoint enable The endpoint enable bit is set to a 1 by the MCU to enable the IN endpoint. This bit does not affect the reception of the control endpoint setup stage transaction.
The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a
6 ISO Isochronous endpoint particular IN endpoint for isochronous transactions. This bit must be cleared to a 0 by
the MCU to use a particular IN endpoint for control, interrupt, or bulk transactions.
The toggle bit is controlled by the UBM and is toggled at the end of a successful in
5 TOGGLE Toggle data stage transaction if a valid data packet is transmitted. If this bit is a 0, a DATA0 PID is transmitted in the data packet to the host PC. If this bit is a 1, a DATA1 PID is
transmitted in the data packet.
The double buffer mode bit is set to a 1 by the MCU to enable the use of both the X
4 DBUF Double buffer mode and Y data packet buffers for USB transactions to a particular IN endpoint. This bit must be cleared to a 0 by the MCU to use the single buffer mode. In the single buffer
mode, only the X buffer is used.
The stall bit is set to a 1 by the MCU to stall endpoint transactions. When this bit is
3 STALL Stall set, the hardware automatically returns a stall handshake to the host PC for any
transaction received for the endpoint.
2 IEPIE Interrupt enable The interrupt enable bit is set to a 1 by the MCU to enable the IN endpoint interrupt. See Section 6.5.7.2 for details on the IN endpoint interrupts.
1:0 — Reserved Reserved for future use.
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6.4.4.6.2 USB IN Endpoint Configuration Byte Settings - Isochronous Transactions
This section defines the functionality of the bits in the USB IN endpoint configuration byte for isochronous
endpoints.
Bit 7 6 5 4 3 2 1 0
Mnemonic IEPEN ISO OVF BPS4 BPS3 BPS2 BPS1 BPS0
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
7 IEPEN Endpoint enable The endpoint enable bit is set to a 1 by the MCU to enable the IN endpoint.
The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a
6 ISO Isochronous endpoint particular IN endpoint for isochronous transactions. This bit must be cleared to a 0 by the MCU for a particular IN endpoint to be used for control, interrupt, or bulk
transactions.
The overflow bit is set to a 1 by the UBM to indicate a buffer overflow condition has
5 OVF Overflow occurred. This bit is used for diagnostic purposes only and is not used for normal
operation. This bit can only be cleared to a 0 by the MCU.
The bytes per sample bits are used to define the number of bytes per isochronous
data sample. In other words, the total number of bytes in an entire audio codec frame.
4:0 BPS(4:0) Bytes per sample For example, a PCM 16-bit stereo audio data sample consists of 4 bytes. There are two bytes of left channel data and two bytes of right channel data. For a four channel
system using 16-bit data, the total number of bytes is 8, which is the isochronous data
sample size. 00h = 1 byte, 01h = 2 bytes, …, 1Fh = 32 bytes
6.4.5 USB Control Endpoint Setup Stage Data Packet Buffer
The USB control endpoint setup stage data packet buffer is the buffer space used to store the 8-byte data
packet received from the host PC during a control endpoint transfer setup stage transaction. Refer to
Chapter 9 of the USB Specification for details on the data packet.
Table 6-2. USB Control Endpoint Setup Data Packet
Buffer Address Map
ADDRESS NAME
FF2Fh wLength - Number of bytes to transfer in the data stage
FF2Eh wLength - Number of bytes to transfer in the data stage
FF2Dh wIndex - Index or offset value
FF2Ch wIndex - Index or offset value
FF2Bh wValue - Value of a parameter specific to the request
FF2Ah wValue - Value of a parameter specific to the request
FF29h bRequest - Specifies the particular request
FF28h bmRequestType - Identifies the characteristics of the request
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6.5 Memory-Mapped Registers
The TAS1020B device provides a set of control and status registers to be used by the MCU to control the
overall operation of the device. This section describes the memory-mapped registers.
Table 6-3. Memory-Mapped Registers Address Map
ADDRESS MNEMONIC NAME SECTION
FFFFh USBFADR USB function address register Section 6.5.1.1
FFFEh USBSTA USB status register Section 6.5.1.2
FFFDh USBIMSK USB interrupt mask register Section 6.5.1.3
FFFCh USBCTL USB control register Section 6.5.1.4
FFFBh USBFNL USB frame number register (low-byte) Section 6.5.1.5
FFFAh USBFNH USB frame number register (high-byte) Section 6.5.1.6
FFF9h ACG2FRQ0 Adaptive clock generator2 frequency register (Byte 0) Section 6.5.3.6
FFF8h ACG2FRQ1 Adaptive clock generator2 frequency register (Byte 1) Section 6.5.3.7
FFF7h ACG2FRQ2 Adaptive clock generator2 frequency register (Byte 2) Section 6.5.3.8
FFF6h ACG2DCTL Adaptive clock generator2 divider control register Section 6.5.3.9
FFF5h Reserved Reserved for future use
FFF4h DMABCNT1H DMA buffer content register (high-byte) (channel 1) Section 6.5.2.5
FFF3h DMABCNT1L DMA buffer content register (low-byte) (channel 1) Section 6.5.2.4
FFF2h DMABPCT0 DMA bulk packet count register (low-byte) Section 6.5.2.6
FFF1h DMABPCT1 DMA bulk packet count register (high-byte) Section 6.5.2.7
FFF0h DMATSL1 DMA time slot assignment register (low-byte) (channel 1) Section 6.5.2.1
FFEFh DMATSH1 DMA time slot assignment register (high-byte) (channel 1) Section 6.5.2.1
FFEEh DMACTL1 DMA control register (channel 1) Section 6.5.2.3
FFEDh Reserved Reserved for future use
FFECh DMABCNT0H DMA current buffer content register (high-byte) (channel 0) Section 6.5.2.5
FFEBh DMABCNT0L DMA current buffer content register (low-byte) (channel 0) Section 6.5.2.4
FFEAh DMATSL0 DMA time slot assignment register (low-byte) (channel 0) Section 6.5.2.1
FFE9h DMATSH0 DMA time slot assignment register (high-byte) (channel 0) Section 6.5.2.2
FFE8h DMACTL0 DMA control register (channel 0) Section 6.5.2.3
FFE7h ACG1FRQ0 Adaptive clock generator1 frequency register (byte 0) Section 6.5.3.1
FFE6h ACG1FRQ1 Adaptive clock generator1 frequency register (byte 1) Section 6.5.3.2
FFE5h ACG1FRQ2 Adaptive clock generator1 frequency register (byte 2) Section 6.5.3.3
FFE4h ACGCAPL Adaptive clock generator1 MCLK capture register (low byte) Section 6.5.3.4
FFE3h ACGCAPH Adaptive clock generator1 MCLK capture register (high byte) Section 6.5.3.5
FFE2h ACG1DCTL Adaptive clock generator1 divider control register Section 6.5.3.10
FFE1h ACGCTL Adaptive clock generator control register Section 6.5.3.11
FFE0h CPTCNF1 Codec port interface configuration register 1 Section 6.5.4.1
FFDFh CPTCNF2 Codec port interface configuration register 2 Section 6.5.4.2
FFDEh CPTCNF3 Codec port interface configuration register 3 Section 6.5.4.3
FFDDh CPTCNF4 Codec port interface configuration register 4 Section 6.5.4.4
FFDCh CPTCTL Codec port interface control and status register Section 6.5.4.5
FFDBh CPTADR Codec port interface address register Section 6.5.4.6
FFDAh CPTDATL Codec port interface data register (low-byte) Section 6.5.4.7
FFD9h CPTDATH Codec port interface data register (high-byte) Section 6.5.4.8
FFD8h CPTVSLL Codec port interface valid slots register (low-byte) Section 6.5.4.9
FFD7h CPTVSLH Codec port interface valid slots register (high-byte) Section 6.5.4.10
FFD6h CPTRXCNF2 Codec port receive interface configuration register 2 Section 6.5.4.11
FFD5h CPTRXCNF3 Codec port receive interface configuration register 3 Section 6.5.4.12
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Table 6-3. Memory-Mapped Registers Address Map (continued)
ADDRESS MNEMONIC NAME SECTION
FFD4h CPTRXCNF4 Codec port receive interface configuration register 4 Section 6.5.4.13
FFD3h Reserved Reserved for future use
FFD2h Reserved Reserved for future use
FFD1h Reserved Reserved for future use
FFD0h Reserved Reserved for future use
FFCFh Reserved Reserved for future use
FFCEh Reserved Reserved for future use
FFCDh Reserved Reserved for future use
FFCCh Reserved Reserved for future use
FFCBh Reserved Reserved for future use
FFCAh P3MSK Mask register for P3 Section 6.5.5.1
FFC9h Reserved Reserved for future use
FFC8h Reserved Reserved for future use
FFC7h Reserved Reserved for future use
FFC6h Reserved Reserved for future use
FFC5h Reserved Reserved for future use
FFC4h Reserved Reserved for future use
FFC3h I2CADR I2C interface address register Section 6.5.6.1
FFC2h I2CDATI I2C interface receive data register Section 6.5.6.2
FFC1h I2CDATO I2C interface transmit data register Section 6.5.6.3
FFC0h I2CCTL I2C interface control and status register Section 6.5.6.4
FFBFh Reserved Reserved for future use
FFBEh Reserved Reserved for future use
FFBDh Reserved Reserved for future use
FFBCh Ch0WrPtrL UBM write pointer (low-byte) (8 bits) Section 6.5.2.8
FFBBh Ch0WrPtrH UBM write pointer (high-byte) (3 bits) Section 6.5.2.9
FFBAh Ch0RdPtrL DMA read pointer (low-byte) (8 bits) Section 6.5.2.10
FFB9h Ch0RdPtrH DMA read pointer (high-byte) (3 bits) Section 6.5.2.11
FFB8h Ch1WrPtrL UBM write pointer (low-byte) (8 bits) Section 6.5.2.8
FFB7h Ch1WrPtrH UBM write pointer (high-byte) (3 bits) Section 6.5.2.9
FFB6h Ch1RdPtrL DMA read pointer (low-byte) (8 bits) Section 6.5.2.10
FFB5h Ch1RdPtrH DMA read pointer (high-byte) (3 bits) Section 6.5.2.11
FFB4h OEPINT USB OUT endpoint interrupt register Section 6.5.7.1
FFB3h IEPINT USB IN endpoint interrupt register Section 6.5.7.2
FFB2h VECINT Interrupt vector register Section 6.5.7.3
FFB1h GLOBCTL Global control register Section 6.5.7.4
FFB0h MEMCFG Memory configuration register Section 6.5.7.5
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6.5.1 USB Registers
This section describes the memory-mapped registers used for control and operation of the USB functions.
This section consists of six registers used for USB functions.
6.5.1.1 USB Function Address Register (USBFADR - Address FFFFh)
The USB function address register contains the current setting of the USB device address assigned to the
function by the host. After power-on reset or USB reset, the default address is 00h. During enumeration of
the function by the host, the MCU should load the assigned address to this register when a USB
Set_Address request is received by the control endpoint.
Bit 7 6 5 4 3 2 1 0
Mnemonic — FA6 FA5 FA4 FA3 FA2 FA1 FA0
Type R R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7 — Reserved Reserved for future use
6:0 FA(6:0) Function address The function address bit values are set by the MCU to program the USB device address assigned by the host PC.
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6.5.1.2 USB Status Register (USBSTA - Address FFFEh)
The USB status register contains various status bits used for USB operations.
Bit 7 6 5 4 3 2 1 0
Mnemonic RSTR SUSR RESR SOF PSOF SETUP — STPOW
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The function reset bit is set to a 1 by hardware in response to the host PC initiating a
USB reset to the function. When a USB reset occurs, all of the USB logic blocks,
including the SIE, UBM, frame timer, and suspend/resume are automatically reset.
The function reset enable (FRSTE) control bit in the USB control register, when set,
7 RSTR Function reset enables the USB reset to reset all remaining TAS1020B logic, except the shadow the
ROM (SDW) and the USB function connect (CONT) bits. Also, when the FRSTE
control bit is set to a 1, the reset output (RSTO) signal from the TAS1020B device is
also active when a USB reset occurs. This bit is read only and is cleared when the
MCU writes to the interrupt vector register.
The function suspend bit is set to a 1 by hardware when a USB suspend condition is
6 SUSR Function suspend detected by the suspend/resume logic. See Section 2.2.5 for details on the USB suspend and resume operation. This bit is read only and is cleared when the MCU
writes to the interrupt vector register.
The function resume bit is set to a 1 by hardware when a USB resume condition is
5 RESR Function resume detected by the suspend/resume logic. See Section 2.2.5 for details on the USB suspend and resume operation. This bit is read only and is cleared when the MCU
writes to the interrupt vector register.
The start-of-frame bit is set to a 1 by hardware when a new USB frame starts. This bit
is set when the SOF packet from the host PC is detected, even if the TAS1020B
4 SOF Start-of-frame frame timer is not locked to the host PC frame timer. This bit is read only and is
cleared when the MCU writes to the interrupt vector register. The nominal SOF rate is
1 ms.
The pseudo start-of-frame bit is set to a 1 by hardware when a USB pseudo SOF
occurs. The pseudo SOF is an artificial SOF signal that is generated when the
3 PSOF Pseudo start-of-frame TAS1020B frame timer is not locked to the host PC frame timer. This bit is read only
and is cleared when the MCU writes to the interrupt vector register. The nominal
pseudo SOF rate is 1 ms.
The setup stage transaction bit is set to a 1 by hardware when a successful control
endpoint setup stage transaction is completed. Upon completion of the setup stage
2 SETUP Setup stage transaction transaction, the USB control endpoint setup stage data packet buffer should contain a
new setup stage data packet. This bit is read-only and is cleared when the MCU
writes to the interrupt vector register.
1 — Reserved Reserved for future use
The setup stage transaction over-write bit is set to a 1 by hardware when the data in
Setup stage transaction the USB control endpoint setup data packet buffer is over-written. This scenario 0 STPOW over-write occurs when the host PC prematurely terminates a USB control transfer by simply starting a new control transfer with a new setup stage transaction. This bit is read-only
and is cleared when the MCU writes to the interrupt vector register.
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6.5.1.3 USB Interrupt Mask Register (USBIMSK - Address FFFDh)
The USB interrupt mask register contains the interrupt mask bits used to enable or disable the generation
of interrupts based on the corresponding status bits.
Bit 7 6 5 4 3 2 1 0
Mnemonic RSTR SUSR RESR SOF PSOF SETUP — STPOW
Type R/W R/W R/W R/W R/W R/W R R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7 RSTR Function reset The function reset interrupt mask bit is set to a 1 by the MCU to enable the USB function reset interrupt.
6 SUSR Function suspend The function suspend interrupt mask bit is set to a 1 by the MCU to enable the USB function suspend interrupt.
5 RESR Function resume The function resume interrupt mask bit is set to a 1 by the MCU to enable the USB function resume interrupt.
4 SOF Start-of-frame The start-of-frame interrupt mask bit is set to a 1 by the MCU to enable the USB start-of-frame interrupt.
3 PSOF Pseudo start-of-frame The pseudo start-of-frame interrupt mask bit is set to a 1 by the MCU to enable the USB pseudo start-of-frame interrupt.
2 SETUP Setup stage transaction The setup stage transaction interrupt mask bit is set to a 1 by the MCU to enable the USB setup stage transaction interrupt.
1 — Reserved Reserved for future use
0 STPOW Setup stage transaction The setup stage transaction over-write interrupt mask bit is set to a 1 by the MCU to over-write enable the USB setup stage transaction over-write interrupt.
6.5.1.4 USB Control Register (USBCTL - Address FFFCh)
The USB control register contains various control bits used for USB operations.
Bit 7 6 5 4 3 2 1 0
Mnemonic CONT FEN RWUP FRSTE — — — SDW_OK
Type R/W R/W R/W R/W R R R R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The function connect bit is set to 1 by the MCU to connect the TAS1020B device to
the USB. As a result of connecting to the USB, the host PC should enumerate the
7 CONT Function connect function. When this bit is set, the USB data plus pullup resistor (PUR) output signal is enabled, which connects the pullup on the PCB to the TAS1020B 3.3-V supply
voltage. When this bit is cleared to 0, the PUR output is in the high-impedance state.
This bit is not affected by a USB reset.
The function enable bit is set to 1 by the MCU to enable the TAS1020B device to
6 FEN Function enable respond to USB transactions. If this bit is cleared to 0, the UBM ignores all USB
transactions. This bit is cleared by a USB reset.
The remote wake-up bit is set to 1 by the MCU to request the suspend/resume logic to
5 RWUP Remote wake-up generate resume signaling upstream on the USB. This bit is used to exit a USB low-power suspend state when a remote wake-up event occurs. After initiating the
resume signaling by setting this bit, the MCU should clear this bit within 2.5 μs.
The function reset enable bit is set to 1 by the MCU to enable the USB reset to reset
all internal logic including the MCU. However, the shadow the ROM (SDW) and the
4 FRSTE Function reset enable USB function connect (CONT) bits will not be reset. When this bit is set, the reset
output (RSTO) signal from the TAS1020B device is also active when a USB reset
occurs. This bit is not affected by USB reset.
3 — Reserved Reserved for future use.
2 — Reserved Reserved for future use.
1 — Reserved Reserved for future use.
This bit is used as a confirmation bit to prevent a user from spuriously clearing the
0 SDW_OK SDW bit confirm SDW bit in the MEMCFG register. This bit must be set to 1 before clearing the SDW
bit to switch from normal mode to boot mode. This bit is not affected by USB reset.
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6.5.1.5 USB Frame Number Register (Low Byte) (USBFNL - Address FFFBh)
The USB frame number register (low byte) contains the least significant byte of the 11-bit frame number
value received from the host PC in the start-of-frame packet.
Bit 7 6 5 4 3 2 1 0
Mnemonic FN7 FN6 FN5 FN4 FN3 FN2 FN1 FN0
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The frame number bit values are updated by hardware each USB frame with the
frame number field value received in the USB start-of-frame packet. The frame
7:0 FN(7:0) Frame number number can be used as a time stamp by the USB function. If the TAS1020B frame
timer is not locked to the host PC frame timer, then the frame number is incremented
from the previous value when a pseudo start-of-frame occurs.
6.5.1.6 USB Frame Number Register (High Byte) (USBFNH - Address FFFAh)
The USB frame number register (high byte) contains the most significant 3 bits of the 11-bit frame number
value received from the host PC in the start-of-frame packet.
Bit 7 6 5 4 3 2 1 0
Mnemonic — — — — — FN10 FN9 FN8
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:3 — Reserved Reserved for future use.
The frame number bit values are updated by hardware each USB frame with the
frame number field value received in the USB start-of-frame packet. The frame
2:0 FN(10:8) Frame number number can be used as a time stamp by the USB function. If the TAS1020B frame
timer is not locked to the host PC frame timer, then the frame number is incremented
from the previous value when a pseudo start-of-frame occurs.
6.5.2 DMA Registers
This section describes the memory-mapped registers used for the two DMA channels. Each DMA channel
has a set of three registers.
6.5.2.1 DMA Time Slot Assignment Register (Low Byte) (DMATSL1 - Address FFF0h) (DMATSL0 -
Address FFEAh)
Bit 7 6 5 4 3 2 1 0
Mnemonic TSL7 TSL6 TSL5 TSL4 TSL3 TSL2 TSL1 TSL0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:0 TSL(7:0) Time slot assignment The DMA time slot assignment bits are set to 1 by the MCU to define the codec port interface time slots supported by this DMA channel.
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6.5.2.2 DMA Time Slot Assignment Register (High Byte) (DMATSH1 - Address FFEFh) (DMATSH0 -
Address FFE9h)
Bit 7 6 5 4 3 2 1 0
Mnemonic BPTS1 BPTS0 TSL13 TSL12 TSL11 TSL10 TSL9 TSL8
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The bytes per time slot bits are used to define the number of bytes to be transferred
for each time slot supported by this DMA channel.
7:6 BPTS(1:0) Bytes per time slot 00b = 1 byte 01b = 2 bytes
10b = 3 bytes
11b = 4 bytes
5:0 TSL(13:8) Time slot assignment The DMA time slot assignment bits are set to 1 by the MCU to define the codec port interface time slots supported by this DMA channel.
6.5.2.3 DMA Control Register (DMACTL1 - Address FFEEh) (DMACTL0 - Address FFE8h)
Bit 7 6 5 4 3 2 1 0
Mnemonic DMAEN HSKEN — — EPDIR EPNUM2 EPNUM1 EPNUM0
Type R/W R/W R R R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The DMA enable bit is set to a 1 by the MCU to enable this DMA channel. Before
7 DMAEN DMA enable enabling the DMA channel, all other DMA channel configuration bits must be set to the
desired value.
This bit is relevant for BULK data transfer in the OUT direction through DMA. MCU
must set this bit to a 1 to enable the handshake mode for the data transfer. If MCU
sets this bit, MCU has to enable DMA for each received BULK OUT packet. DMA,
6 HSKEN Handshake enable once enabled, transfers the BULK OUT packet to the C-port, disables itself and
generates an interrupt to the MCU. If MCU clears this bit, DMA handles the BULK
OUT data transfer to the C-port without MCU intervention. For more details, see
Section 2.2.7.3.3.
5 — Reserved Reserved for future use
4 — Reserved Reserved for future use
The USB endpoint direction bit controls the direction of data transfer by this DMA
3 EPDIR USB endpoint direction channel. The MCU should set this bit to a 1 to configure this DMA channel to be used for a USB IN endpoint. The MCU must clear this bit to a 0 to configure this DMA
channel to be used for a USB OUT endpoint.
The USB endpoint number bits are set by the MCU to define the USB endpoint
number supported by this DMA channel. Keep in mind that endpoint 0 is always used
for the control endpoint, which is serviced by the MCU and not a DMA channel.
2:0 EPNUM(2:0) USB endpoint number 001b = Endpoint 1 010b = Endpoint 2
⋮
111b = Endpoint 7
000b = Illegal
6.5.2.4 DMA Current Buffer Content Register (Low-Byte) (DMABCNT1L - Address FFF3h) (DMABCNT0LAddress
FFEBh)
Bit 7 6 5 4 3 2 1 0
Mnemonic Size 7 Size 6 Size 5 Size 4 Size 3 Size 2 Size 1 Size 0
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
This register shows the buffer content (bytes) for an ISO OUT endpoint. This register
7:0 Size(7:0) Buffer content is updated every SOF and is stable for the following USB frame, during which the
MCU can read it to implement USB audio synchronization.
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6.5.2.5 DMA Current Buffer Content Register (High Byte) (DMABCNT1H - Address FFF4h) (DMABCNT0H
- Address FFECh)
Bit 7 6 5 4 3 2 1 0
Mnemonic Size 15 Size 14 Size 13 Size 12 Size 11 Size 10 Size 9 Size 8
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
This register shows the buffer content (bytes) for an ISO OUT endpoint. This register
7:0 Size(15:8) Buffer content is updated every SOF and is stable for the following USB frame, during which the
MCU can read it to implement USB audio synchronization.
6.5.2.6 DMA Bulk Packet Count Register (Low Byte) (DMABPCT0 - Address FFF2h)
Bit 7 6 5 4 3 2 1 0
Mnemonic PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
This register shows the number of BULK OUT packets DMA has to handle in
7:0 PCNT (7:0) Bulk packet count handshake mode. MCU writes to this register before enabling the DMA to program the DMA to handle up to 64K BULK packets without MCU intervention. MCU can read this
register anytime.
6.5.2.7 DMA Bulk Packet Count Register (High-byte) (DMABPCT1 - Address FFF1h)
Bit 7 6 5 4 3 2 1 0
Mnemonic PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
This register shows the number of BULK OUT packets DMA has to handle in
7:0 PCNT (15:8) Bulk packet count handshake mode. MCU writes to this register before enabling the DMA to program the DMA to handle up to 64K BULK packets without MCU intervention. MCU can read this
register anytime.
6.5.2.8 UBM Write Pointer (Low Byte) (Ch0WrPtrL - Address FFBCh) (Ch1WrPtrL - Address FFB8h)
Bit 7 6 5 4 3 2 1 0
Mnemonic WRPTR7 WRPTR6 WRPTR5 WRPTR4 WRPTR3 WRPTR2 WRPTR1 WRPTR0
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
This register contains 8 LSB bits of 11-bit UBM write pointer of the isochronous OUT
7:0 WRPTR(7:0) UBM write pointer endpoint buffer. MCU can read this register anytime. This 11-bit UBM write pointer WRPTR can be used in conjunction with the corresponding 11-bit CHn DMA RDPTR
to estimate the amount of data in the isochronous OUT endpoint buffer.
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6.5.2.9 UBM Write Pointer (High Byte) (Ch0WrPtrH - Address FFBBh) (Ch1WrPtrH - Address FFB7h)
Bit 7 6 5 4 3 2 1 0
Mnemonic — — — — — WRPTR10 WRPTR9 WRPTR8
Type — — — — — R R R
Default — — — — — 0 0 0
BIT MNEMONIC NAME DESCRIPTION
This register contains 3 MSB bits of 11-bit UBM write pointer of the isochronous OUT
2:0 WRPTR(10:8) UBM write pointer endpoint buffer. MCU can read this register anytime. This 11-bit UBM write pointer WRPTR can be used in conjunction with the corresponding 11-bit CHn DMA RDPTR
to estimate the amount of data in the isochronous OUT endpoint buffer.
7:3 — Reserved Reserved for future use
6.5.2.10 DMA Read Pointer (Low Byte) (Ch0RdPtrL - Address FFBAh) (Ch1RdPtrL - Address FFB6h)
Bit 7 6 5 4 3 2 1 0
Mnemonic RDPTR7 RDPTR6 RDPTR5 RDPTR4 RDPTR3 RDPTR2 RDPTR1 RDPTR0
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
This register contains 8 LSB bits of 11-bit DMA channel n (n can be 0 or 1) read
pointer of the Isochronous OUT endpoint buffer. MCU can read this register anytime.
7:0 RDPTR(7:0) DMA read pointer This 11-bit CHn DMA read pointer RDPTR can be used in conjunction with the
corresponding 11-bit UBM write pointer WRPTR to estimate the amount of data in the
isochronous OUT endpoint buffer.
6.5.2.11 DMA Read Pointer (High Byte) (Ch0RdPtrH - Address FFB9h) (Ch1RdPtrH - Address FFB5h)
Bit 7 6 5 4 3 2 1 0
Mnemonic — — — — — WRPTR10 WRPTR9 WRPTR8
Type — — — — — R R R
Default — — — — — 0 0 0
BIT MNEMONIC NAME DESCRIPTION
This register contains 3 MSB bits of 11-bit channel n (n can be 0 or 1) read pointer of
the Isochronous OUT endpoint buffer. MCU can read this register anytime. This 11-bit
2:0 RDPTR(10:8) DMA read pointer CHn DMA RDPTR can be used in conjunction with the corresponding 11-bit UBM
write pointer WRPTR to estimate the amount of data in the isochronous OUT endpoint
buffer.
7:3 — Reserved Reserved for future use
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6.5.3 Adaptive Clock Generator Registers
This section describes the memory-mapped registers used for two adaptive clock generators for their
controls and operations.
6.5.3.1 Adaptive Clock Generator1 Frequency Register (Byte 0) (ACG1FRQ0 - Address FFE7h)
The adaptive clock generator frequency register (byte 0) contains the least significant byte of the 24-bit
ACG frequency value. The adaptive clock generator frequency registers, ACG1FRQ0, ACG1FRQ1, and
ACG1FRQ2, contain the 24-bit value used to program the ACG1 frequency synthesizer. The 24-bit value
of these three registers can be used to determine the codec master clock output (MCLKO) signal
frequency. The output of the ACG2 frequency synthesizer can also be used to source MCLK0. See
Section 2.2.6 for the operation details of the adaptive clock generator including instructions for
programming the 24-bit ACG frequency value.
Bit 7 6 5 4 3 2 1 0
Mnemonic FRQ7 FRQ6 FRQ5 FRQ4 FRQ3 FRQ2 FRQ1 FRQ0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:0 FRQ(7:0) ACG frequency The ACG frequency bit values are set by the MCU to program the ACG1 frequency synthesizer.
6.5.3.2 Adaptive Clock Generator1 Frequency Register (Byte 1) (ACG1FRQ1 - Address FFE6h)
The adaptive clock generator frequency register (byte 1) contains the middle byte of the 24-bit ACG 1
frequency value.
Bit 7 6 5 4 3 2 1 0
Mnemonic FRQ15 FRQ14 FRQ13 FRQ12 FRQ11 FRQ10 FRQ9 FRQ8
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:0 FRQ(15:8) ACG frequency The ACG frequency bit values are set by the MCU to program the ACG1 frequency synthesizer.
6.5.3.3 Adaptive Clock Generator1 Frequency Register (Byte 2) (ACG1FRQ2 - Address FFE5h)
The adaptive clock generator frequency register (byte 2) contains the most significant byte of the 24-bit
ACG frequency value.
Bit 7 6 5 4 3 2 1 0
Mnemonic FRQ23 FRQ22 FRQ21 FRQ20 FRQ19 FRQ18 FRQ17 FRQ16
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:0 FRQ(23:16) ACG frequency The ACG frequency bit values are set by the MCU to program the ACG1 frequency synthesizer.
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6.5.3.4 Adaptive Clock Generator MCLK Capture Register (Low Byte) (ACGCAPL - Address FFE4h)
The adaptive clock generator MCLK capture register (low byte) contains the least significant byte of the
16-bit codec master clock (MCLK) signal cycle count that is captured each time a USB start of frame
(SOF) occurs. The value of a16-bit free running counter, which is clocked with the MCLK signal, is
captured at the beginning of each USB frame. The source of the MCLK signal used to clock the 16-bit
timer can be selected to be either the MCLKO signal or the MCLKO2 signal. See Section 2.2.6 for the
operation details of the adaptive clock generator.
Bit 7 6 5 4 3 2 1 0
Mnemonic CAP7 CAP6 CAP5 CAP4 CAP3 CAP2 CAP1 CAP0
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:0 CAP(7:0) ACG MCLK capture The ACG MCLK capture bit values are updated by hardware each time a USB start of frame occurs. This register contains the least significant byte of the 16-bit value.
6.5.3.5 Adaptive Clock Generator MCLK Capture Register (High Byte) (ACGCAPH - Address FFE3h)
The adaptive clock generator MCLK capture register (high byte) contains the most significant byte of the
16-bit codec master clock (MCLK) signal cycle count that is captured each time a USB start of frame
(SOF) occurs.
Bit 7 6 5 4 3 2 1 0
Mnemonic CAP15 CAP14 CAP13 CAP12 CAP11 CAP10 CAP9 CAP8
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:0 CAP(15:8) ACG MCLK capture The ACG MCLK capture bit values are updated by hardware each time a USB start of frame occurs. This register contains the most significant byte of the 16-bit value.
6.5.3.6 Adaptive Clock Generator2 Frequency Register (Byte 0) (ACG2FRQ0 - Address FFF9h)
The adaptive clock generator control registers ACG2FRQ0, ACG2FRQ1, and ACG2FRQ2, contain the
24-bit value used to program the ACG2 frequency synthesizer.
Bit 7 6 5 4 3 2 1 0
Mnemonic FRQ7 FRQ6 FRQ5 FRQ4 FRQ3 FRQ2 FRQ1 FRQ0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:0 FRQ(7:0) ACQ2 frequency The ACG2 frequency bit values are set by the MCU to program the ACG2 frequency synthesizer.
6.5.3.7 Adaptive Clock Generator2 Frequency Register (Byte 1) (ACG2FRQ1 - Address FFF8h)
Bit 7 6 5 4 3 2 1 0
Mnemonic FRQ15 FRQ14 FRQ13 FRQ12 FRQ11 FRQ10 FRQ9 FRQ8
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:0 FRQ(15:8) ACQ2 frequency The ACG2 frequency bit values are set by the MCU to program the ACG2 frequency synthesizer.
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6.5.3.8 Adaptive Clock Generator2 Frequency Register (Byte 2) (ACG2FRQ2 - Address FFF7h)
Bit 7 6 5 4 3 2 1 0
Mnemonic FRQ23 FRQ22 FRQ21 FRQ20 FRQ19 FRQ18 FRQ17 FRQ16
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:0 FRQ(23:16) ACQ2 frequency The ACG2 frequency bit values are set by the MCU to program the ACG2 frequency synthesizer.
6.5.3.9 Adaptive Clock Generator2 Divider Control Register (ACG2DCTL - Address FFF6h)
Bit 7 6 5 4 3 2 1 0
Mnemonic DIVM3 DIVM2 DIVM1 DIVM0 - - - -
Type R/W R/W R/W R/W R R R R
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The divide by M control bits are set by the MCU to program the ACG2 frequency
divider.
7:4 DIVM(3:0) Divide by M value 0000b = divide by 1 0001b = divide by 2
⋮
1111b = divide by 16
3:0 - Reserved Reserved for future use
6.5.3.10 Adaptive Clock Generator1 Divider Control Register (ACG1DCTL - Address FFE2h)
Bit 7 6 5 4 3 2 1 0
Mnemonic DIVM3 DIVM2 DIVM1 DIVM0 - DIVI2 DIVI1 DIVI0
Type R/W R/W R/W R/W R R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The divide by M control bits are set by the MCU to program the ACG1 frequency
divider.
7:4 DIVM(3:0) Divide by M value 0000b = divide by 1 0001b = divide by 2
⋮
1111b = divide by 16
3 - Reserved Reserved for future use
The divide by I control bits are set by the MCU to program the MCLKI divider.
000b = divide by 1
2:0 DIVI(2:0) Divide by I value 001b = divide by 2
⋮
111b = divide by 8
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6.5.3.11 Adaptive Clock Generator Control Register (ACGCTL - Address FFE1h)
Bit 7 6 5 4 3 2 1 0
Mnemonic MCLKO2EN MCLKO1EN - MCLKO1S1 MCLKO1S0 DIVEN MCLKO2S1 MCLKO2S0
Type R/W R/W R R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
This bit is set to 1 by the MCU to enable the MCLKO2 signal to be an output from the
7 MCLKO2EN MCLKO2 output enable TAS1020B device. If the MCLKO2 signal is not being used, then the MCU can clear
this bit to 0 to set the output to logic 0.
This bit is set to 1 by the MCU to enable the MCLKO1 signal to be an output from the
6 MCLKO1EN MCLKO1 output enable TAS1020B device. If the MCLKO1 signal is not being used, then the MCU can clear
this bit to 0 to set the output to logic 0.
5 - Reserved Reserved for future use
This bit in conjunction with MCLKO1S0, selects the source for MCLKO1. See the ACG
block diagram (Figure 2-1).
MCLKO1S1 MCLKO1S0 MCLKO1
4 MCLKO1S1 MCLKO1 clock select 0 0 acg_clk (after ÷M)
x 1 mclki (after ÷I)
1 0 acg2_clk(after ÷M)
3 MCLKO1S0 MCLKO1 clock select See the description above.
2 DIVEN Divider enable The divider enable bit is set to 1 by the MCU to enable the divide-by-I and divide-by-M circuits.
This bit in conjunction with MCLKO2S0, selects the MCLKO2. See the ACG block
diagram (Figure 2-1).
MCLKO2S1 MCLKO2S0 MCLKO2
1 MCLKO2S1 MCLKO2 clock select 0 0 acg_clk (after ÷M)
x 1 mclki (after ÷I)
1 0 acg2_clk(after ÷M)
0 MCLKO2S0 MCLKO2 clock select See the description above.
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6.5.4 Codec Port Interface Registers
This section describes the memory-mapped registers used for the codec port interface control and
operation. The codec port interface has a set of ten registers. Note that the four codec port interface
configuration registers can only be written to by the MCU if the codec port enable bit (CPTEN) in the
global control register is a 0 - the codec port is disabled.
6.5.4.1 Codec Port Interface Configuration Register 1 (CPTCNF1 - Address FFE0h)
The codec port interface configuration register 1 is used to store various control bits for the codec port
interface operation.
Bit 7 6 5 4 3 2 1 0
Mnemonic NTSL4 NTSL3 NTSL2 NTSL1 NTSL0 MODE2 MODE1 MODE0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The number of time slots bits are set by the MCU to program the number of time slots
per audio frame.
7:3 NTSL(4:0) Number of time slots 00000b = Illegal 00001b = 2 time slots per frame
⋮
01101 = 14 time slots per frame
The mode select bits are set by the MCU to program the codec port interface mode of
operation. In addition to selecting the desired mode of operation, the MCU must also
program the other configuration registers to obtain the correct serial interface format.
000b = mode 0 - General-purpose mode
001b = mode 1 - AIC mode
2:0 MODE(2:0) Mode select 010b = mode 2 - AC ’97 1.x mode
011b = mode 3 - AC ’97 2.x mode
100b = mode 4 - I2S mode - 1 OUT and 2 IN at same frequency
101b = mode 5 - I2S mode - 1 OUT and 1 IN at different frequencies
110b = Reserved
111b = Reserved
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6.5.4.2 Codec Port Interface Configuration Register 2 (CPTCNF2 - Address FFDFh)
The codec port interface configuration register 2 is used to store various control bits for the codec port
interface operation.
Bit 7 6 5 4 3 2 1 0
Mnemonic TSL0L1 TSL0L0 BPTSL2 BPTSL1 BPTSL0 TSLL2 TSLL1 TSLL0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The time slot 0 Length bits are set by the MCU to program the number of serial clock
(CSCLK) cycles for time slot 0.
7:6 TSL0L(1:0) Time slot 0 length 00b = CSCLK cycles for time slot 0 same as other time slots 01b = 8 CSCLK cycles for time slot 0
10b = 16 CSCLK cycles for time slot 0
11b = 32 CSCLK cycles for time slot 0
The data bits per time slot bits are set by the MCU to program the number of data bits
per audio time slot. Note that this value in not used for the secondary communication
address and data time slots.
000b = 8 data bits per time slot
001b = 16 data bits per time slot
5:3 BPTSL(2:0) Data bits per time slot 010b = 18 data bits per time slot
011b = 20 data bits per time slot
100b = 24 data bits per time slot
101b = 32 data bits per time slot
110b = reserved
111b = reserved
The time slot length bits are set by the MCU to program the number of serial clock
(CSCLK) cycles for all time slots except time slot 0.
000b = 8 CSCLK cycles per time slot
001b = 16 CSCLK cycles per time slot
2:0 TSLL(2:0) Time slot length 010b = 18 CSCLK cycles per time slot 011b = 20 CSCLK cycles per time slot
100b = 24 CSCLK cycles per time slot
101b = 32 CSCLK cycles per time slot
110b = reserved
111b = reserved
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6.5.4.3 Codec Port Interface Configuration Register 3 (CPTCNF3 - Address FFDEh)
The codec port interface configuration register 3 is used to store various control bits for the codec port
interface operation.
Bit 7 6 5 4 3 2 1 0
Mnemonic DDLY TRSEN CSCLKP CSYNCP CSYNCL BYOR CSCLKD CSYNCD
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 1 1 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The data delay bit is set to a 1 by the MCU to program a one CSCLK cycle delay of
7 DDLY Data delay the serial data output and input signals in reference to the leading edge of the CSYNC
signal. The MCU must clear this bit to a 0 for no delay between these signals.
The 3-state enable bit is set to a 1 by the MCU to program the hardware to set the
serial data output signal to the high-impedance state for the time slots during the
6 TRSEN 3-State enable audio frame that are not valid. The MCU must clear this bit to a 0 to program the
hardware to use zero-padding for the serial data output signal for time slots during the
audio frame that are not valid.
The CSCLK polarity bit is used by the MCU to program the clock edge used for the
codec port interface frame sync (CSYNC) output signal, codec port interface serial
data output (CDATO) signal and codec port interface serial data Input (CDATI) signal.
When this bit is set to a 1, the CSYNC signal is generated with the negative edge of
the codec port interface serial clock (CSCLK) signal. Also, when this bit is set to a 1,
5 CSCLKP CSCLK polarity the CDATO signal is generated with the negative edge of the CSCLK signal and the
CDATI signal is sampled with the positive edge of the CSCLK signal. When this bit is
cleared to a 0, the CSYNC signal is generated with the positive edge of the CSCLK
signal. Also, when this bit is cleared to a 0, the CDATO signal is generated with the
positive edge of the CSCLK signal and the CDATI signal is sampled with the negative
edge of the CSCLK signal.
The CSYNC polarity bit is set to a 1 by the MCU to program the polarity of the codec
4 CSYNCP CSYNC polarity port interface frame sync (CSYNC) output signal to be active high. The MCU must clear this bit to a 0 to program the polarity of the CSYNC output signal to be active
low.
The CSYNC length bit is set to a 1 by the MCU to program the length of the codec
3 CSYNCL CSYNC length port interface frame sync (CSYNC) output signal to be the same number of CSCLK cycles as time slot 0. The MCU must clear this bit to a 0 to program the length of the
CSYNC output signal to be one CSCLK cycle.
The byte order bit is used by the MCU to program the byte order for the data moved
by the DMA between the USB endpoint buffer and the codec port interface. When this
2 BYOR Byte order bit is set to a 1, the byte order of each audio sample is reversed when the data is
moved to/from the USB endpoint buffer. When this bit is cleared to a 0, the byte order
of the each audio sample is unchanged.
The CSCLK direction bit is set to a 1 by the MCU to program the direction of the
codec port interface serial clock (CSCLK) signal as an input to the TAS1020B device.
The MCU must clear this bit to a 0 to program the direction of the CSCLK signal as an
1 CSCLKD CSCLK direction output from the TAS1020B device.
This bit can optionally be set to 1 to select 'Input' only when General Purpose Mode 1
has been selected.
The CSYNC direction bit is set to a 1 by the MCU to program the direction of the
codec port interface frame sync (CSYNC) signal as an input to the TAS1020B device.
The MCU must clear this bit to a 0 to program the direction of the CSYNC signal as an
0 CSYNCD CSYNC direction output from the TAS1020B device.
This bit can optionally be set to 1 to select 'Input' only when General Purpose Mode 1
has been selected.
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6.5.4.4 Codec Port Interface Configuration Register 4 (CPTCNF4 - Address FFDDh)
The codec port interface configuration register 4 is used to store various control bits for the codec port
interface operation.
Bit 7 6 5 4 3 2 1 0
Mnemonic ATSL3 ATSL2 ATSL1 ATSL0 CPTBLK DIVB2 DIVB1 DIVB0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The command/status address/data time slot bits are set by the MCU to program the
time slots to be used for the secondary communication address and data values. For
the AC ’97 modes of operation, this value must be set to 0001b which results in time
slot 1 being used for the address and time slot 2 being used for the data. For the AIC
Command/status and general-purpose modes of operation, the same time slot is used for both address 7:4 ATSL(3:0) address/data time slot and data. For the AIC mode of operation this value must be set to 0111b which results in time slot 7 being used for both the address and data.
0000b = time slot 0
0001b = time slot 1
⋮
1111b = time slot 15
This bit is used when C-port is in Mode 0. If this bit is cleared to 0, the C-port
3 CptBlk C-port bulk mode sync/clocks are free running once C-port is enabled. If this bit is set to 1, DMA controls the C-port sync/clocks. The sync/clocks are active only when valid data is present in a
codec frame.
The divide by B control bits are set by the MCU to program the divide ratio used to
derive CSCLK from MCLKO.
000b = CSCLK output disabled
001b = divide by 2
2:0 DIVB(2:0) Divide by B value 010b = divide by 3 011b = divide by 4
100b = divide by 5
101b = divide by 6
110b = divide by 7
111b = divide by 8
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6.5.4.5 Codec Port Interface Control and Status Register (CPTCTL - Address FFDCh)
The codec port interface control and status register contains various control and status bits used for the
codec port interface operation.
Bit 7 6 5 4 3 2 1 0
Mnemonic RXF RXIE TXE TXIE — CID1 CID0 CRST
Type R R/W R R/W R R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The receive data register full bit is set to a 1 by hardware when a new data value has
been received into the receive data register from the codec device. This bit is read
7 RXF Receive data register full only and is cleared to a 0 by hardware when the MCU reads the new value from the receive data register. Note that when the MCU writes to the interrupt vector register,
the codec port interface receive data register full interrupt is cleared but this status bit
is not cleared at that time.
6 RXIE Receive interrupt enable The receive interrupt enable bit is set to a 1 by the MCU to enable the C-port receive data register full interrupt.
The transmit data register empty bit is set to a 1 by hardware when the data value in
the transmit data register has been sent to the codec device. This bit is read only and
5 TXE Transmit data register is cleared to a 0 by hardware when a new data byte is written to the transmit data empty register by the MCU. Note that when the MCU writes to the interrupt vector register,
the codec port interface transmit data register empty interrupt is cleared but this status
bit is not cleared at that time.
4 TXIE Transmit interrupt The transmit interrupt enable bit is set to a 1 by the MCU to enable the codec port enable interface transmit data register empty interrupt.
3 — Reserved Reserved for future use
The codec ID bits are used by the MCU to select between the primary codec device
and the secondary codec device for secondary communication in the AC ’97 modes of
2:1 CID(1:0) Codec ID operation. When the bits are cleared to 00, the primary codec device is selected. When the bits are set to 01, 10 or 11, the secondary codec device is selected. Note
that when only a primary codec device is connected to the TAS1020B, the bits remain
cleared to 00.
The codec reset bit is used by the MCU to control the codec port interface reset
(CRESET) output signal from the TAS1020B device. When this bit is set to a 1, the
CRESET signal is a high. When this bit is cleared to a 0, the CRESET signal is active
0 CRST Codec reset low. At power up this bit is cleared to a 0, which means the CRESET output signal is
active low and remains active low until the MCU sets this bit to a 1. In I2S mode 5, this
signal is not available because the CRESET pin becomes SCLK2, which is used to
input data from a codec.
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6.5.4.6 Codec Port Interface Address Register (CPTADR - Address FFDBh)
The codec port interface address register contains the read/write control bit and address bits used for
secondary communication between the TAS1020B MCU and the codec device. For write transactions to
the codec, the 8-bit value in this register is sent to the codec in the designated time slot and appropriate
bit locations. Note that for the different modes of operation, the number of address bits and the bit location
of the read/write bit is different. For example, the AC ’97 modes require 7 address bits and the bit location
of the read/write bit to be the most significant bit. The AIC mode only requires 4 address bits and the bit
location of the read/write bit to be bit 13 of the 16-bits in the time slot. The MCU must load the read/write
and address bits to the correct bit locations within this register for the different modes of operation. Shown
below are the read/write control bit and address bits for the AC ’97 mode of operation.
Bit 7 6 5 4 3 2 1 0
Mnemonic R/W A6 A5 A4 A3 A2 A1 A0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The command/status read/write control bit value is set by the MCU to program the
7 R/W Command/status type of secondary communication transaction to be done. This bit must be set to a 1 read/write control by the MCU for a read transaction and cleared to a 0 by the MCU for a write
transaction.
The command/status address value is set by the MCU to program the codec device
6:0 A(6:0) Command/status control/status register address to be accessed during the read or write transaction. address The command/status address value is updated by hardware with the control/status
register address value received from the codec device for read transactions.
6.5.4.7 Codec Port Interface Data Register (Low Byte) (CPTDATL - Address FFDAh)
The codec port interface data register (low byte) contains the least significant byte of the 16-bit command
or status data value used for secondary communication between the TAS1020B MCU and the codec
device. Note that for general-purpose mode or AIC mode only an 8-bit data value is used for secondary
communication.
Bit 7 6 5 4 3 2 1 0
Mnemonic D7 D6 D5 D4 D3 D2 D1 D0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The command/status data value is set by the MCU with the command data to be
7:0 D(7:0) Command/status data transmitted to the codec device for write transactions. The command/status data value is updated by hardware with the status data received from the codec device for read
transactions.
6.5.4.8 Codec Port Interface Data Register (High Byte) (CPTDATH - Address FFD9h)
The codec port interface data register (high byte) contains the most significant byte of the 16-bit command
or status data value used for secondary communication between the TAS1020B MCU and the codec
device. This register is not used for general-purpose mode or AIC mode since these modes only support
an 8-bit data value for secondary communication.
Bit 7 6 5 4 3 2 1 0
Mnemonic D15 D14 D13 D12 D11 D10 D9 D8
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The command/status data value is set by the MCU with the command data to be
7:0 D(15:8) Command/status data transmitted to the codec device for write transactions. The command/status data value is updated by hardware with the status data received from the codec device for read
transactions.
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6.5.4.9 Codec Port Interface Valid Time Slots Register (Low Byte) (CPTVSLL - Address FFD8h)
The codec port interface valid time slots register (low byte) contains the control bits used to specify which
time slots in the audio frame contain valid data. This register is only used in the AC ’97 modes of
operation.
Bit 7 6 5 4 3 2 1 0
Mnemonic VTSL8 VTSL9 VTSL10 VTSL11 VTSL12 — — —
Type R/W R/W R/W R/W R/W R R R
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The valid time slot bits are set to a 1 by the MCU to define which time slots in the
7:3 VTSL(8:12) Valid time slot audio frame contain valid data. The MCU must clear to a 0 the bits corresponding to time slots that do not contain valid data. Note that bits 7 to 3 of this register
correspond to time slots 8 to 12.
2:0 — Reserved Reserved for future use
6.5.4.10 Codec Port Interface Valid Time Slots Register (High Byte) (CPTVSLH - Address FFD7h)
The codec port interface valid time slots register (high byte) contains the control bits used to specify which
time slots in the audio frame contain valid data. In addition the valid frame, primary codec ready and
secondary codec ready bits are contained in this register. This register is only used in the AC ’97 modes
of operation.
Bit 7 6 5 4 3 2 1 0
Mnemonic VF PCRDY SCRDY VTSL3 VTSL4 VTSL5 VTSL6 VTSL7
Type R/W R R R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The valid frame bit is set to a 1 by the MCU to indicate that the current audio frame
7 VF Valid frame contains at least one time slot with valid data. The MCU must clear this bit to a 0 to
indicate that the current audio frame does not contain any time slots with valid data.
The primary codec ready bit is updated by hardware each audio frame based on the
6 PCRDY Primary codec ready value of bit 15 in time slot 0 of the incoming serial data from the primary codec. This
bit is set to a 1 to indicate the primary codec is ready for operation.
The secondary codec ready bit is updated by hardware each audio frame based on
5 SCRDY Secondary codec ready the value of bit 15 in time slot 0 of the incoming serial data from the secondary codec. This bit is set to a 1 to indicate the secondary codec is ready for operation. Note that
this bit is only used if a secondary codec is connected to the TAS1020B device.
The valid time slot bits are set to a 1 by the MCU to define which time slots in the
4:0 VTSL(3:7) Valid time slot audio frame contain valid data. The MCU must clear to a 0 the bits corresponding to time slots that do not contain valid data. Note that bits 4 to 0 of this register
correspond to time slots 3 to 7.
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6.5.4.11 Codec Port Receive Interface Configuration Register 2 (CPTRXCNF2 - Address FFD6h)
The codec port receive interface configuration register2 is only used in I2S Mode 5.
Bit 7 6 5 4 3 2 1 0
Mnemonic - - BPTSL2 BPTSL1 BPTSL0 TSLL2 TSLL1 TSLL0
Type R R R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:6 — Reserved Reserved for future use
The data bits per time slot bits are set by the MCU to program the number of data bits
per audio time slot. Note that this value in not used for the secondary communication
address and data time slots.
000b = 8 data bits per time slot
001b = 16 data bits per time slot
5:3 BPTSL(2:0) Data bits per time slot. 010b = 18 data bits per time slot
011b = 20 data bits per time slot
100b = 24 data bits per time slot
101b = 32 data bits per time slot
110b = reserved
111b = reserved
The time slot length bits are set by the MCU to program the number of serial clock
(SCLK2) cycles for all time slots.
000b = 8 SCLK2 cycles per time slot
001b = 16 SCLK2 cycles per time slot
2:0 TSLL(2:0) Time slot length 010b = 18 SCLK2 cycles per time slot 011b = 20 SCLK2 cycles per time slot
100b = 24 SCLK2 cycles per time slot
101b = 32 SCLK2 cycles per time slot
110b = reserved
111b= reserved
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6.5.4.12 Codec Port Receive Interface Configuration Register 3 (CPTRXCNF3 - Address FFD5h)
The codec port receive interface configuration register3 is only used in I2S Mode 5.
Bit 7 6 5 4 3 2 1 0
Mnemonic DDLY TRSEN CSCLKP CSYNCP CSYNCL BYOR CSCLKD CSYNCD
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 1 1 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The data delay bit is set to 1 by the MCU to program a one SCLK2 cycle delay of the
7 DDLY Data delay serial data output and input signals in reference to the leading edge of the LRCK2
signal. The MCU must clear this bit to a 0 for no delay between these signals.
The 3-state enable bit is set to a 1 by the MCU to program the hardware to set the
serial data output signal to the high-impedance state for time slots during the audio
6 TRSEN 3-state enable frame that are not valid. The MCU must clear this bit to a 0 to program the hardware
to use zero-padding for the serial data output signal for time slots during the audio
frame that are not valid.
The CSCLKP polarity bit is used by the MCU to program the clock edge used for the
codec port interface frame sync (LRCK2) output signal and codec port interface serial
data input (CDAT1) signal. When this bit is set to a 1, the LRCK2 signal is generated
5 CSCLKP CSCLK polarity with the negative edge of the codec port interface serial clock (SCLK2) signal. Also, when this bit is set a 1, the CDATI signal is sampled with the positive edge of the
SCLK2 signal. When this bit is cleared to 0, the LRCK2 signal is generated with the
positive edge of SCLK2 and the CDATI signal is sampled with the negative edge of
the SCLK2 signal.
The CSYNCP polarity bit is set to a 1 by the MCU to program the polarity of the codec
4 CSYNCP CSYNC polarity port interface frame sync (LRCK2) output signal to be active high. The MCU must
clear this bit to a 0 to program the polarity of the LRCK2 output signal to be active low.
The CSYNCL polarity bit is set to a 1 by the MCU to program the length of the codec
3 CSYNCL CSYNC length port interface frame sync (LRCK2) output signal to be the same number of SCLK2 cycles as time slot 0. The MCU must clear this bit to a 0 to program the length of the
LRCK2 output signal to be one SCLK2 cycle.
The byte order bit is used by the MCU to program the byte order for the data moved
by the DMA between the USB endpoint buffer and the codec port interface. When this
2 BYOR Byte order bit is set to a 1, the byte order of each audio sample is reversed when the data is
moved to/from the USB endpoint buffer. When this bit is cleared to a 0, the byte order
of the each audio sample is unchanged.
The SCLK2 direction bit is set to a 1 by the MCU to program the direction of the codec
1 CSCLKD CSCLK direction port interface serial clock (SCLK2) signal as an input of the TAS1020B device. The MCU must clear this bit to a 0 to program the direction of the CSCLK signal as an
output from the TAS1020B device.
The SCLK2 direction bit is set to a 1 by the MCU to program the direction of the codec
0 CSYNCD CSYNC direction port interface frame sync (LRCK2) signal as an input of the TAS1020B device. The MCU must clear this bit to a 0 to program the direction of the LRCK2 signal as an
output from the TAS1020B device.
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6.5.4.13 Codec Port Receive Interface Configuration Register 4 (CPTRXCNF4 - Address FFD4h)
The codec port receive interface configuration register 4 is only used in I2S Mode 5.
Bit 7 6 5 4 3 2 1 0
Mnemonic - - - - - DIVB22 DIVB21 DIVB20
Type R R R R R R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:3 — Reserved Reserved for future use
The divide by B2 control bits are set by the MCU to program the divide ratio used to
derive SCLK2 from MCLKO2.
000b = SCLK2 output disabled
001b = divide by 2
2:0 DIVB2(2:0) Divide by B2 value 010b = divide by 3 011b = divide by 4
100b = divide by 5
101b = divide by 6
110b = divide by 7
111b = divide by 8
6.5.5 P3 Mask Register
Mask register for P3 to enable the wake-up function for these pins when the device is in low-power mode.
6.5.5.1 P3 Mask Register (P3MSK - Address FFCAh)
Bit 7 6 5 4 3 2 1 0
Mnemonic P3MSK7 P3MSK6 P3MSK5 P3MSK4 P3MSK3 P3MSK2 P3MSK1 P3MSK0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:0 P3MSK(7:0) 0 = Unmasked 1 = Masked
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6.5.6 I2C Interface Registers
This section describes the memory-mapped registers used for the I2C Interface control and operation. The
I2C interface has a set of four registers. See Section 2.2.14 for the operation details of the I2C interface.
6.5.6.1 I2C Interface Address Register (I2CADR - Address FFC3h)
The I2C interface address register contains the 7-bit I2C slave device address and the read/write
transaction control bit.
Bit 7 6 5 4 3 2 1 0
Mnemonic A6 A5 A4 A3 A2 A1 A0 RW
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The address bit values are set by the MCU to program the 7-bit I2C slave address of
the device to be accessed. Each I2 7:1 A(6:0) Address C slave device must have a unique address on the I2C bus. This address is used to identify the device on the bus to be accessed and is
not the internal memory address to be accessed within the device.
The read/write control bit value is set by the MCU to program the type of I2C
0 RW Read/write control transaction to be done. This bit must be set to a 1 by the MCU for a read transaction
and cleared to a 0 by the MCU for a write transaction.
6.5.6.2 I2C Interface Receive Data Register (I2CDATI - Address FFC2h)
The I2C interface receive data register contains the most recent data byte received from the slave device.
Bit 7 6 5 4 3 2 1 0
Mnemonic RXD7 RXD6 RXD5 RDXD4 RXD3 RXD2 RXD1 RXD0
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:0 RXD(7:0) Receive data The receive data byte value is updated by hardware for each data byte received from the I2C slave device.
6.5.6.3 I2C Interface Transmit Data Register (I2CDATO - Address FFC1h)
The I2C interface transmit data register contains the next address or data byte to be transmitted to the
slave device in accordance with the protocol. Note that for both read and write transactions, the internal
register or memory address of the slave device being accessed must be transmitted to the slave device.
Bit 7 6 5 4 3 2 1 0
Mnemonic TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0
Type W W W W W W W W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7:0 TXD(7:0) Transmit data The transmit data byte value is set by the MCU for each address or data byte to be transmitted to the I2C slave device.
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6.5.6.4 I2C Interface Control and Status Register (I2CCTL - Address FFC0h)
The I2C interface control and status register contains various control and status bits used for the I2C
interface operation.
Bit 7 6 5 4 3 2 1 0
Mnemonic RXF RXIE ERR FRQ TXE TXIE STPRD STPWR
Type R R/W R/W R/W R R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The receive data register full bit is set to a 1 by hardware when a new data byte has
been received into the receive data register from the slave device. This bit is read only
7 RXF Receive data register full and is cleared to a 0 by hardware when the MCU reads the new byte from the receive data register. Note that when the MCU writes to the interrupt vector register, the I2C
receive data register full interrupt is cleared but this status bit is not cleared at that
time.
6 RXIE Receive interrupt enable The receive interrupt enable bit is set to a 1 by the MCU to enable the I2C receive data register full interrupt.
5 ERR Error condition The error condition bit is set to a 1 by hardware when the slave device does not respond. This bit is read/write and can only be cleared by the MCU.
The frequency select bit is used by the MCU to program the I2C serial clock (SCL)
4 FRQ Frequency select output signal frequency. A value of 0 sets the SCL frequency to 100 kHz and a value
of 1 sets the SCL frequency to 400 kHz.
The transmit data register empty bit is set to a 1 by hardware when the data byte in
the transmit data register has been sent to the slave device. This bit is read only and
3 TXE Transmit data register is cleared to a 0 by hardware when a new data byte is written to the transmit data empty register by the MCU. Note that when the MCU writes to the interrupt vector register,
the I2C transmit data register empty interrupt is cleared but this status bit is not
cleared at that time.
2 TXIE Transmit interrupt The transmit interrupt enable bit is set to a 1 by the MCU to enable the I2C transmit enable data register empty interrupt.
The stop read transaction bit is set to a 1 by the MCU to enable the hardware to
1 STPRD Stop - read transaction generate a stop condition on the I2C bus after the next data byte from the slave device is received into the receive data register. The MCU must clear this bit to a 0 after the
read transaction has concluded.
The stop write transaction bit is set to a 1 by the MCU to enable the hardware to
0 STPWR Stop - write transaction generate a stop condition on the I2C bus after the data byte in the transmit data register is sent to the slave device. The MCU must clear this bit to a 0 after the write
transaction has concluded.
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6.5.7 Miscellaneous Registers
This section describes the memory-mapped registers used for the control and operation of miscellaneous
functions in the TAS1020B device. The registers include the USB OUT endpoint interrupt register, the
USB IN endpoint interrupt register, the interrupt vector register, the global control register, and the
memory configuration register.
6.5.7.1 USB OUT endpoint Interrupt Register (OEPINT - Address FFB4h)
The USB OUT endpoint interrupt register contains the interrupt pending status bits for the USB OUT
endpoints. These bits do not apply to the USB isochronous endpoints. Also, these bits are read only by
the MCU and are used for diagnostic purposes only.
Bit 7 6 5 4 3 2 1 0
Mnemonic OEPI7 OEPI6 OEPI5 OEPI4 OEPI3 OEPI2 OEPI1 OEPI0
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The OUT endpoint interrupt status bit for a particular USB OUT endpoint is set to a 1
by the UBM when a successful completion of a transaction occurs to that OUT
7:0 OEPI(7:0) OUT endpoint interrupt endpoint. When a bit is set, an interrupt to the MCU is generated and the
corresponding interrupt vector results. The status bit is cleared when the MCU writes
to the interrupt vector register. These bits do not apply to isochronous OUT endpoints.
6.5.7.2 USB IN endpoint Interrupt Register (IEPINT - Address FFB3h)
The USB IN endpoint interrupt register contains the interrupt pending status bits for the USB IN endpoints.
These bits do not apply to the USB isochronous endpoints. Also, these bits are read only by the MCU and
are used for diagnostic purposes only.
Bit 7 6 5 4 3 2 1 0
Mnemonic IEPI7 IEPI6 IEPI5 IEPI4 IEPI3 IEPI2 IEPI1 IEPI0
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The IN endpoint interrupt status bit for a particular USB IN endpoint is set to a 1 by the
UBM when a successful completion of a transaction occurs to that IN endpoint. When
7:0 IEPI(7:0) IN endpoint interrupt a bit is set, an interrupt to the MCU is generated and the corresponding interrupt
vector results. The status bit is cleared when the MCU writes to the interrupt vector
register. These bits do not apply to isochronous IN endpoints.
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6.5.7.3 Interrupt Vector Register (VECINT - Address FFB2h)
The interrupt vector register contains a 6-bit vector value that identifies the interrupt source for the INT0
input to the MCU. All of the TAS1020B internal interrupt sources and the external interrupt input to the
device are ORed together to generate the internal INT0 signal to the MCU. When there is not an interrupt
pending, the interrupt vector value is set to 24h. To clear any interrupt and update the interrupt vector
value to the next pending interrupt, the MCU should simply write any value to this register. The interrupt
priority is fixed in order, ranging from vector value 1Fh with the highest priority to vector value 00h with the
lowest priority. An exception to this priority is the control endpoint EP0 which has top priority.
Bit 7 6 5 4 3 2 1 0
Mnemonic — — IVEC5 IVEC4 IVEC3 IVEC2 IVEC1 IVEC0
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
7 — Reserved Reserved for future use
6 — Reserved Reserved for future use
00h = USB OUT endpoint 0 10h = USB setup stage transaction
01h = USB OUT endpoint 1 over-write
02h = USB OUT endpoint 2 11h = Reserved
03h = USB OUT endpoint 3 12h = USB setup stage transaction
04h = USB OUT endpoint 4 13h = USB pseudo start-of-frame
05h = USB OUT endpoint 5 14h = USB start-of-frame
06h = USB OUT endpoint 6 15h = USB function resume
07h = USB OUT endpoint 7 16h = USB function suspend
5:0 IVEC(5:0) Interrupt vector 08h = USB IN endpoint 0 17h = USB function reset
09h = USB IN endpoint 1 18h = C-port receive data register full
0Ah = USB IN endpoint 2 19h = C-port transmit data register empty
0Bh = USB IN endpoint 3 1Ah = Reserved
0Ch = USB IN endpoint 4 1Bh = Reserved
0Dh = USB IN endpoint 5 1Ch = I2C receive data register full
0Eh = USB IN endpoint 6 1Dh = I2C transmit data register empty
0Fh = USB IN endpoint 7 1Eh = Reserved1Fh = External interrupt
input
20h = DMA Ch.0 interrupt 24h = No interrupt pending
21h = DMA Ch.1 interrupt 25h - 3Fh = Reserved
22h - 23h = Reserved
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6.5.7.4 Global Control Register (GLOBCTL - Address FFB1h)
The global control register contains various global control bits for the TAS1020B device.
Bit 7 6 5 4 3 2 1 0
Mnemonic MCUCLK XINTEN P1PUDIS VREN RESET LPWR P3PUDIS CPTEN
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
BIT MNEMONIC NAME DESCRIPTION
The MCU clock select bit is used by the MCU to program the clock frequency to be
used for the MCU operation.
7 MCUCLK MCU clock select 0b = 12 MHz 1b = 24 MHz
POR (Power On Reset) value is 0 (12 MHz). Setting this bit to 1 will change MCU
clock frequency to 24 MHz. But, once set, this bit can only be cleared by master reset.
6 XINTEN External interrupt enable The external interrupt enable bit is set to a 1 by the MCU to enable the use of the external interrupt input to the TAS1020B device.
5 P1PUDIS Pullup resistor disable If set to 1, disables on-chip pullup resistors on P1 GPIO pins.
4 VREN VREN Memory-mapped GPIO pin
3 RESET RESET Memory-mapped GPIO pin
The low power mode disable bit is used by the MCU to put the TAS1020B into a
2 LPWR Low power mode semi-low power state. When this bit is cleared to a 0, all USB functional blocks are
powered down. For normal operation, the MCU must set this bit to a 1.
1 P3PUDIS Pullup resistor disable If set to 1, disables on-chip pullup resistors on P3 GPIO pins.
The codec port enable bit is set to a 1 by the MCU to enable the operation of the
0 CPTEN Codec port enable codec port interface. Note that the codec port interface configuration registers must be
fully programmed before this bit is set by the MCU.
6.5.7.5 Memory Configuration Register (MEMCFG - Address FFB0h)
The memory configuration register contains various bits pertaining to the memory configuration of the
TAS1020B device.
Bit 7 6 5 4 3 2 1 0
Mnemonic MEMTYP CODESZ1 CODESZ0 REV3 REV2 REV1 REV0 SDW
Type R R R R R R R R/W
Default 1 0 1 0 0 0 1 0
BIT MNEMONIC NAME DESCRIPTION
The code memory type bit identifies if the type of memory used for the application
7 MEMTYP Code memory type program code space is ROM or RAM. For the TAS1020B, an 8K byte RAM is used
and this bit is tied to 1.
The code space size bits identify the size of the application program code memory
space. For the TAS1020B, an 8K byte RAM is used and these bits are tied to 01b.
6:5 CODESZ(1:0) Code space size 00b = 4K bytes 01b = 8K bytes
10b = 16K bytes
11b = 32K bytes
The IC revision bits identify the revision of the IC.
0000b = Rev. -
4:1 REV(3:0) IC revision 0001b = Rev. A
⋮
1111b = Rev. F
The shadow the boot ROM bit is set to a 1 by the MCU to switch the MCU memory
0 SDW Shadow the boot ROM configuration from boot loader mode to normal operating mode. This must occur after completion of the download of the application program code by the boot ROM.
See the SDW protection bit in USBCTL register.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing
Pins Package Qty Eco Plan (2) Lead/
Ball Finish
MSL Peak Temp (3) Samples
(Requires Login)
TAS1020BPFB NRND TQFP PFB 48 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TAS1020BPFBG4 NRND TQFP PFB 48 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TAS1020BPFBR NRND TQFP PFB 48 1000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TAS1020BPFBRG4 NRND TQFP PFB 48 1000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TAS1020BPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS1020BPFBR TQFP PFB 48 1000 336.6 336.6 31.8
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 2
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Copyright © 2012, Texas Instruments Incorporated
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1
2-V to 5.5-V VCC Operation
Support Mixed-Mode Voltage Operation on
All Ports
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
Individual Switch Controls
Extremely Low Input Current
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
These triple 2-channel CMOS analog
multiplexers/demultiplexers are designed for 2-V
to 5.5-V VCC operation.
The ’LV4053A devices handle both analog and
digital signals. Each channel permits signals with
amplitudes up to 5.5 V (peak) to be transmitted in
either direction.
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and
digital-to-analog conversion systems.
ORDERING INFORMATION
TA PACKAGE† ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N Tube of 25 SN74LV4053AN SN74LV4053AN
QFN − RGY Reel of 1000 SN74LV4053ARGYR LW053A
SOIC D
Tube of 40 SN74LV4053AD
− LV4053A
Reel of 2500 SN74LV4053ADR
40°C to 85°C
SOP − NS Reel of 2000 SN74LV4053ANSR 74LV4053A
−SSOP − DB Reel of 2000 SN74LV4053ADBR LW053A
Tube of 90 SN74LV4053APW
TSSOP − PW Reel of 2000 SN74LV4053APWR LW053A
Reel of 250 SN74LV4053APWT
TVSOP − DGV Reel of 2000 SN74LV4053ADGVR LW053A
55°C to 125°C
CDIP − J Tube of 25 SNJ54LV4053AJ SNJ54LV4053AJ
−CFP − W Tube of 150 SNJ54LV4053AW SNJ54LV4053AW
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
UNLESS OTHERWISE NOTED this document contains PRODUCTION Copyright © 2005, Texas Instruments Incorporated
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Y1
2Y0
3Y1
3-COM
3Y0
INH
GND
GND
VCC
2-COM
1-COM
1Y1
1Y0
A
B
C
SN54LV4053A . . . J OR W PACKAGE
SN74LV4053A . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
SN74LV4053A . . . RGY PACKAGE
(TOP VIEW)
1 16
8 9
2
3
4
5
6
7
15
14
13
12
11
10
2-COM
1-COM
1Y1
1Y0
A
B
2Y0
3Y1
3-COM
3Y0
INH
GND
2Y1
C V
GND
CC
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
ON CHANNELS
INH C B A
L L L L 1Y0, 2Y0, 3Y0
L L L H 1Y1, 2Y0, 3Y0
L L H L 1Y0, 2Y1, 3Y0
L L H H 1Y1, 2Y1, 3Y0
L H L L 1Y0, 2Y0, 3Y1
L H L H 1Y1, 2Y0, 3Y1
L H H L 1Y0, 2Y1, 3Y1
L H H H 1Y1, 2Y1, 3Y1
H X X X None
logic diagram (positive logic)
1Y0
1Y1
2Y0
2Y1
3Y0
1-COM
INH
B
A
3-COM
3Y1
2-COM
C
11
10
9
6
15
14
12
13
2
1
5
3
4
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, VIO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
I/O diode current, IIOK (VIO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Switch through current, IT (VIO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 5)
SN54LV4053A SN74LV4053A
UNIT
MIN MAX MIN MAX
VCC Supply voltage 2‡ 5.5 2‡ 5.5 V
VCC = 2 V 1.5 1.5
V High level input voltage control inputs
VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7
VIH High-voltage, V
VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7
VCC = 2 V 0.5 0.5
V Low level input voltage control inputs
VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3
VIL Low-voltage, V
VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3
VI Control input voltage 0 5.5 0 5.5 V
VIO Input/output voltage 0 VCC 0 VCC V
VCC = 2.3 V to 2.7 V 200 200
Δt/Δv Input transition rise or fall rate VCC = 3 V to 3.6 V 100 100 ns/V
VCC = 4.5 V to 5.5 V 20 20
TA Operating free-air temperature −55 125 −40 85 °C
‡ With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals
be transmitted at these low supply voltages.
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST
V
TA = 25°C SN54LV4053A SN74LV4053A
UNIT
CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX
IT = 2 mA, 2.3 V 41 180 225 225
ron
On-state
T ,
VI = VCC or GND,
VINH = VIL
on 3 V 30 150 190 190 Ω switch resistance
(see Figure 1) 4.5 V 23 75 100 100
IT = 2 mA,
2.3 V 139 500 600 600
ron(p) Peak on-state resistance
on VI = VCC to GND, 3 V 63 180 225 225 Ω
VINH = VIL 4.5 V 35 100 125 125
Difference in
IT = 2 mA,
2.3 V 2 30 40 40
Δron
on-state resistance
on VI = VCC to GND,
3 V 1.6 20 30 30 Ω
between switches
VINH = VIL 4.5 V 1.3 15 20 20
II Control input current VI = 5.5 V or GND
0 to
5.5 V ±0.1 ±1 ±1 μA
IS(off)
Off-state
switch leakage current
VI = VCC and
VO = GND, or
VI = GND and
VO = VCC,
VINH = VIH
(see Figure 2)
5.5 V ±0.1 ±1 ±1 μA
IS(on)
On-state
switch leakage current
VI = VCC or GND,
VINH = VIH
(see Figure 3)
5.5 V ±0.1 ±1 ±1 μA
ICC Supply current VI = VCC or GND 5.5 V 20 20 μA
CIC Control input capacitance 2 pF
CIS
Common
terminal capacitance
8.2 pF
COS
Switch
terminal capacitance
5.6 pF
CF Feedthrough capacitance 0.5 pF
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER
FROM
TO
TEST
TA = 25°C SN54LV4053A SN74LV4053A
UNIT
(INPUT)
(OUTPUT)
CONDITIONS MIN TYP MAX MIN MAX MIN MAX
tPLH
tPHL
Propagation
delay time
COM or Yn Yn or COM CL = 15 pF
(see Figure 4)
2.5 10 16 16 ns
tPZH
tPZL
Enable
delay time
INH COM or Yn CL = 15 pF
(see Figure 5)
7.6 18 23 23 ns
tPHZ
tPLZ
Disable
delay time
INH COM or Yn CL = 15 pF
(see Figure 5)
7.7 18 23 23 ns
tPLH
tPHL
Propagation
delay time
COM or Yn Yn or COM CL = 50 pF
(see Figure 4)
4.4 12 18 18 ns
tPZH
tPZL
Enable
delay time
INH COM or Yn CL = 50 pF
(see Figure 5)
8.8 28 35 35 ns
tPHZ
tPLZ
Disable
delay time
INH COM or Yn CL = 50 pF
(see Figure 5)
11.7 28 35 35 ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
FROM
TO
TEST
TA = 25°C SN54LV4053A SN74LV4053A
UNIT
(INPUT)
(OUTPUT)
CONDITIONS MIN TYP MAX MIN MAX MIN MAX
tPLH
tPHL
Propagation
delay time
COM or Yn Yn or COM CL = 15 pF
(see Figure 4)
1.6 6 10 10 ns
tPZH
tPZL
Enable
delay time
INH COM or Yn CL = 15 pF
(see Figure 5)
5.3 12 15 15 ns
tPHZ
tPLZ
Disable
delay time
INH COM or Yn CL = 15 pF
(see Figure 5)
6.1 12 15 15 ns
tPLH
tPHL
Propagation
delay time
COM or Yn Yn or COM CL = 50 pF
(see Figure 4)
2.9 9 12 12 ns
tPZH
tPZL
Enable
delay time
INH COM or Yn CL = 50 pF
(see Figure 5)
6.1 20 25 25 ns
tPHZ
tPLZ
Disable
delay time
INH COM or Yn CL = 50 pF
(see Figure 5)
8.9 20 25 25 ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted)
PARAMETER
FROM
TO
TEST
TA = 25°C SN54LV4053A SN74LV4053A
UNIT
(INPUT)
(OUTPUT)
CONDITIONS MIN TYP MAX MIN MAX MIN MAX
tPLH
tPHL
Propagation
delay time
COM or Yn Yn or COM CL = 15 pF
(see Figure 4)
0.9 4 7 7 ns
tPZH
tPZL
Enable delay
time
INH COM or Yn CL = 15 pF
(see Figure 5)
3.8 8 10 10 ns
tPHZ
tPLZ
Disable
delay time
INH COM or Yn CL = 15 pF
(see Figure 5)
4.6 8 10 10 ns
tPLH
tPHL
Propagation
delay time
COM or Yn Yn or COM CL = 50 pF
(see Figure 4)
1.8 6 8 8 ns
tPZH
tPZL
Enable delay
time
INH COM or Yn CL = 50 pF
(see Figure 5)
4.3 14 18 18 ns
tPHZ
tPLZ
Disable
delay time
INH COM or Yn CL = 50 pF
(see Figure 5)
6.3 14 18 18 ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
analog switch characteristics
PARAMETER
FROM
TO
TEST CONDITIONS V
TA = 25°C
UNIT
(INPUT)
(OUTPUT) VCC TYP
CL = 50 pF, 2.3 V 30
Frequency response
COM or Yn Yn or COM
L p ,
RL = 600 Ω,
fi = 1 MHz (sine wave)
3 V 35 MHz
(switch on)
fin (see Note 6 and Figure 6) 4.5 V 50
CL = 50 pF, 2.3 V −45
Crosstalk
COM or Yn Yn or COM
p ,
RL = 600 Ω,
fin = 1 MHz (sine wave)
3 V −45 dB (between any switches) (see Note 7 and Figure 7) 4.5 V −45
CL = 50 pF, 2.3 V 20
Crosstalk
(control input to signal output) INH COM or Yn
p ,
RL = 600 Ω,
fin = 1 MHz (square wave)
3 V 35 mV (see Figure 8) 4.5 V 65
CL = 50 pF, 2.3 V −45
Feedthrough attenuation
COM or Yn Yn or COM
p ,
RL = 600 Ω,
fin = 1 MHz
3 V −45 dB (switch off) (see Note 7 and Figure 9) 4.5 V −45
CL = 50 pF,
RL = 10 kΩ
VI = 2 Vp-p 2.3 V 0.1
Sine-wave distortion COM or Yn Yn or COM
kΩ,
fin = 1 kHz
( i )
VI = 2.5 Vp-p 3 V 0.1 %
sine wave)
(see Figure 10) VI = 4 Vp-p 4.5 V 0.1
NOTES: 6. Adjust fin voltage to obtain 0-dBm output. Increase fin frequency until dB meter reads −3 dB.
7. Adjust fin voltage to obtain 0-dBm input.
operating characteristics, VCC = 3.3 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance CL = 50 pF, f = 10 MHz 5.3 pF
PARAMETER MEASUREMENT INFORMATION
VCC
VI = VCC or GND
VINH = VIL
2 mA
VO
ron
VI – VO
2 10–3
VI − VO
VCC
GND
(ON)
V
Figure 1. On-State Resistance Test Circuit
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
PARAMETER MEASUREMENT INFORMATION
VINH = VIH
VI VO
Condition 1: VI = 0, VO = VCC
Condition 2: VI = VCC, VO = 0
A
VCC
VCC
GND
(OFF)
Figure 2. Off-State Switch Leakage-Current Test Circuit
VCC
VINH = VIL
VI Open
VCC
GND
A (ON)
VI = VCC or GND
Figure 3. On-State Switch Leakage-Current Test Circuit
VCC
VINH = VIL
Input Output
50 Ω CL
VCC
GND
(ON)
Figure 4. Propagation Delay Time, Signal Input to Signal Output
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
CL
VCC
VO
TEST CIRCUIT
VOLTAGE WAVEFORMS
1 kΩ
S1 S2
tPLZ/tPZL
tPHZ/tPZH
GND
VCC
TEST S1 S2
VCC
GND
VINH
50 Ω
50%
VOL + 0.3 V
tPZH
tPHZ
50%
50%
50%
tPZL
50%
VCC
VO 50%
0 V
VOL
VINH
(tPZL, tPZH)
(tPLZ, tPHZ)
VCC
VO
0 V
VOL
VINH
VCC
0 V
VOH
VCC
0 V
≈0 V
VOH VOH − 0.3 V
≈0 V
≈VCC
≈VCC
GND
VCC
VI
tPLZ
Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output
VO
RL CL
VCC
50 Ω
fin
VINH = GND
0.1 μF
VCC
GND
(ON)
NOTE A: fin is a sine wave.
VCC/2
Figure 6. Frequency Response (Switch On)
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9
PARAMETER MEASUREMENT INFORMATION
VO1
RL CL
VCC
50 Ω
fin
VCC/2
VINH = GND
0.1 μF
VO2
VCC
VCC/2
VINH = VCC
600 Ω
VCC
GND
(ON)
VCC
GND
(OFF)
600 Ω RL CL
fin
Figure 7. Crosstalk Between Any Two Switches
VO
VCC
VCC
GND
RL CL
VCC/2 VCC/2
50 Ω
VINH
600 Ω
Figure 8. Crosstalk Between Control Input and Switch Output
VO
RL CL
VCC
VCC/2
VINH = VCC
0.1 μF
fin
VCC/2
50 Ω 600 Ω
VCC
GND
(OFF)
Figure 9. Feedthrough Attenuation (Switch Off)
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VO
RL CL
VCC
VCC/2
VINH = GND
10 μF
fin
VCC
GND
(ON)
600 Ω
10 μF
Figure 10. Sine-Wave Distortion
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LV4053AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV4053A
SN74LV4053ADBR ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A
SN74LV4053ADE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV4053A
SN74LV4053ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV4053A
SN74LV4053ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A
SN74LV4053ADGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A
SN74LV4053ADR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 LV4053A
SN74LV4053ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV4053A
SN74LV4053AN ACTIVE PDIP N 16 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -40 to 85 SN74LV4053AN
SN74LV4053ANE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -40 to 85 SN74LV4053AN
SN74LV4053ANSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 74LV4053A
SN74LV4053APW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A
SN74LV4053APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A
SN74LV4053APWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 LW053A
SN74LV4053APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A
SN74LV4053APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A
SN74LV4053APWT ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 LW053A
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LV4053ARGYR ACTIVE VQFN RGY 16 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LW053A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV4053A :
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
Addendum-Page 3
• Automotive: SN74LV4053A-Q1
• Enhanced Product: SN74LV4053A-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
SN74LV4053ADBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LV4053ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74LV4053ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74LV4053ADR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
SN74LV4053ADRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74LV4053ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LV4053APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV4053APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV4053APWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV4053APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV4053ARGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Apr-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LV4053ADBR SSOP DB 16 2000 367.0 367.0 38.0
SN74LV4053ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0
SN74LV4053ADR SOIC D 16 2500 333.2 345.9 28.6
SN74LV4053ADR SOIC D 16 2500 364.0 364.0 27.0
SN74LV4053ADRG4 SOIC D 16 2500 333.2 345.9 28.6
SN74LV4053ANSR SO NS 16 2000 367.0 367.0 38.0
SN74LV4053APWR TSSOP PW 16 2000 364.0 364.0 27.0
SN74LV4053APWR TSSOP PW 16 2000 367.0 367.0 35.0
SN74LV4053APWRG4 TSSOP PW 16 2000 367.0 367.0 35.0
SN74LV4053APWT TSSOP PW 16 250 367.0 367.0 35.0
SN74LV4053ARGYR VQFN RGY 16 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Apr-2014
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
1 12
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
16 24 38
4,90
3,70 5,10
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
0,40 0,07 M
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
7,90 9,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
16 20
6,50 6,50
14
0,05 MIN
5,90 5,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 0,15 M
0°–8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
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No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
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Interface interface.ti.com Medical www.ti.com/medical
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Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
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Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
ULINKpro Debug and Trace Unit
The Keil ULINKpro Debug and Trace Unit connects your PC's USB port to your target system (via a JTAG, Cortex Debug, or Cortex Debug+ETM connector). It allows you to program, debug, and analyze your applications using its unique streaming trace technology.
ULINKpro, together with MDK-ARM, provides extended on-the-fly debug capabilities for Cortex-M devices. You are able to control the processor, set breakpoints, and read/write memory contents, all while the processor is running at full speed. High-Speed data and instruction trace are streamed directly to your PC enabling you to analyze detailed program behaviour.
Features
Supports ARM7, ARM9, Cortex-M0, Cortex-M1, Cortex-M3, and Cortex-M4 devices
JTAG support for ARM7, ARM9, and Cortex-M
Serial Wire Debug (SWD) support for Cortex-M
Serial Wire Viewer (SWV) Data and Event Trace for Cortex-M up to 100Mbit/s (Manchester mode)
Instruction Trace (ETM) for Cortex-M3 and Cortex-M4 up to 800Mbit/s
Unique Streaming Trace direct to your PC, provides unlimited trace buffer
JTAG Clock Speed up to 50MHz
Supports Cortex-M devices running at up to 200MHz
High-Speed Memory Read/Write up to 1MBytes/sec
Seamless integration with the Keil μVision IDE & Debugger
Wide target voltage range: 1.2V - 3.3V, 5V tolerant
Support for 5V only devices using optional 5V Adapter
Optional Isolation Adapter provides electrical isolation from the target system
USB 2.0 High-Speed connection
USB powered (no power supply required)
Target Connectors
10-pin (0.05") - Cortex Debug Connector
20-pin (0.10") - ARM Standard JTAG Connector
20-pin (0.05") - Cortex Debug+ETM Connector
The unique streaming trace capabilities of ULINKpro delivers sophisticated analysis features such as:
Complete Code Coverage information about your program's execution ensures thorough application testing and verification
Performance Analysis using the Execution Profiler and Performance Analyzer enable you to identify program bottlenecks, optimize your application, and to isolate problems
Streaming instruction trace requires the target device to have ETM (Embedded Trace Macrocell)
www.element14.com
www.farnell.com
www.newark.com
Page <1>
V1.0
30/07/13
Raspberry PI Heat Sink Kit
The Farnell Raspberry PI heat sink kit will ensure your Raspberry PI remains cool with no need for Fans. They will also help extend the life of your Raspberry PI and thereby reduce hardware failures.
The heat sink kit comprises of 3 high quality Pressfin heat sinks which are designed to fit the 3 main heat sources on the Raspberry PI. Included in the kit is a 30mm × 30mm piece of thermal adhesive tape to securely fix the heat sinks in place and to ensure a good thermal transfer bond.
Dimensions : Millimetres
Important Notice : This data sheet and its contents (the “Information”) belong to the members of the Premier Farnell group of companies (the “Group”) or are licensed to it. No licence is granted for the use of it other than for information purposes in connection with the products to which it relates. No licence of any intellectual property rights is granted. The Information is subject to change without notice and replaces all data sheets previously supplied. The Information supplied is believed to be accurate but the Group assumes no responsibility for its accuracy or completeness, any error in or omission from it or for any use made of it. Users of this data sheet should check for themselves the Information and the suitability of the products for their purpose and not make any
assumptions based on information included or omitted. Liability for loss or damage resulting from any reliance on the Information or use of it (including liability resulting from negligence or where the Group was aware of the possibility of such loss or damage arising) is excluded. This will not operate to limit or restrict the Group’s liability for death or personal injury resulting from its negligence. Multicomp is the registered trademark of the Group. © Premier Farnell plc 2012.
Part Number Table
Description
Part Number
Raspberry PI Heat Sink Kit
2319947
Raspberry Pi Power Supply
UK version
Features:
Built specifically for use with Raspberry Pi
Class II design 5vdc 1A output via Micro USB
Energy efficienct to ErP stage 2
ĞƐĐƌŝƉƟŽŶ͗
This 5vdc 1A UK Micro USB power supply is manufactured specifically
for use with the Raspberry Pi device. It offers a highly efficient output
ŵĞĞƟŶŐ ůĂƚĞƐƚ ƌW ƐƚĂŐĞ Ϯ ƌĞƋƵŝƌĞŵĞŶƚƐ ĂŶĚ ŝƐ ƐĂĨĞƚLJ ĂƉƉƌŽǀ ĞĚ͘ dŚŝƐ
unit has a fixed UK pin and a 1.8 metre output cable and features
ƐŚŽƌƚ ĐŝƌĐƵŝƚ ĂŶĚ Žǀ Ğƌ ĐƵƌƌĞŶƚ ƉƌŽƚĞĐƟŽŶ ĂƐ ƐƚĂŶĚĂƌĚ͘ dŚŝƐ ZĂƐƉďĞƌƌLJ
Pi power supply has M.T.B.F of 50K hours at 25 degrees C.
Part Number PW03060
Output 5vdc 1A maximum
Current Min. 0.01A
WŽǁ Ğƌ ;ǁ ĂƩ ƐͿ 5W
Line Reg +/-5% at rated load
dŽƚĂů K ƵƚƉƵƚ ZĞŐƵůĂƟŽŶ +/-5 % at 0—100% load
Ripple & Noise (mV p-p) 200mV P-P
WƌŽƚĞĐƟŽŶƐ Over Current and Short Circuit
Case Size 54 x 50 x 42mm
Weight (approx.) 70g
DC Cord 1.8 Metres
DC Plug Micro USB
Rated Input Voltage 100-240Vac
Full Input Voltage Range 90-264Vac
Rated Frequency 50-60Hz
Full Frequency Range 47-63Hz
Efficiency 68.17%
Leakage Current shall not exceed 0.25mA
Input Power 7.72W max
Input Current (RMS Max.) 0.18A max
Hi-Pot Spec 3000Vac 10mA 1 min. (I.P. to O.P.)
E Ž ůŽĂĚ ƉŽǁ Ğƌ ĐŽŶƐƵŵƉƟŽŶ 0.3W max
K ƉĞƌĂƟŶŐ dĞŵƉĞƌĂƚƵƌĞ 0 to 40 degrees C
Storage Temperature -20 to 80 degrees C
K ƉĞƌĂƟŶŐ , ƵŵŝĚŝƚLJ 10% to 90%
Safety Approvals BS EN60950-1 / CE marked
EMC Standards EN55022:2006+A1:2007
/ EN6100-3-2 / EN6100-3-3
Pb-free Yes RoHS Compliant
MTBF 50K Hours at 25 degrees C
See mechanical drawing and DC cable drawing on page 2.
Full spec sheet on this PSU is available on request. Premier Farnell Ltd accepts
ŶŽ ƌĞƐƉŽŶƐŝďŝůŝƚLJ ĨŽƌ ƚLJƉŽŐƌĂƉŚŝĐĂů ĞƌƌŽƌƐ ŝŶ ƚŚĞ ƉƌŽĚƵĐƟŽŶ ŽĨ ƚŚŝƐ ůĞĂŇĞƚ͘
WƌŽĚƵĐƚ ƐƉĞĐŝĮ ĐĂƟŽŶƐ ĂƌĞ ƐƵďũĞĐƚ ƚŽ ĐŚĂŶŐĞ ǁ ŝƚŚŽƵƚ ŶŽƟĐĞ
Raspberry Pi Power Supply
UK version
Mechanical drawing:
Output connector
Keyboard, Mouse and Cable Bundles for the
Raspberry Pi
Kit Contents:
HDMI Bundle DVI Bundle
RPI-CABLE+ACC/HDMI RPI-CABLE+ACC/DVI
Mini QWERTY Keyboard
Optical USB Mouse
3.5mm Stereo Jack Plug Cable – 2m
Stereo Phono (RCA) to 3.5mm Stereo Jack Plug Cable – 1.8m
Cat5e Patch Cable, RJ45 Plug to RJ45 Plug – 3m
High Speed HDMI Cable – 2m HDMI to DVI Cable – 2m
LM3S6952 Microcontroller
DATA SHEET
DS-LM3S6952-1972 Copyright © 2007 Luminary Micro, Inc.
PRELIMINARY
Legal Disclaimers and Trademark Information
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO
LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR
USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS.
Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office
or your distributor to obtain the latest specifications before placing your product order.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these
for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Copyright © 2007 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of
Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks and Cortex is a trademark
of ARM Limited. Other names and brands may be claimed as the property of others.
Luminary Micro, Inc.
108 Wild Basin, Suite 350
Austin, TX 78746
Main: +1-512-279-8800
Fax: +1-512-279-8879
http://www.luminarymicro.com
2 November 30, 2007
Preliminary
Table of Contents
About This Document .................................................................................................................... 20
Audience .............................................................................................................................................. 20
About This Manual ................................................................................................................................ 20
Related Documents ............................................................................................................................... 20
Documentation Conventions .................................................................................................................. 20
1 Architectural Overview ...................................................................................................... 22
1.1 Product Features ...................................................................................................................... 22
1.2 Target Applications .................................................................................................................... 28
1.3 High-Level Block Diagram ......................................................................................................... 29
1.4 Functional Overview .................................................................................................................. 29
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 30
1.4.2 Motor Control Peripherals .......................................................................................................... 30
1.4.3 Analog Peripherals .................................................................................................................... 31
1.4.4 Serial Communications Peripherals ............................................................................................ 32
1.4.5 System Peripherals ................................................................................................................... 33
1.4.6 Memory Peripherals .................................................................................................................. 34
1.4.7 Additional Features ................................................................................................................... 35
1.4.8 Hardware Details ...................................................................................................................... 35
2 ARM Cortex-M3 Processor Core ...................................................................................... 37
2.1 Block Diagram .......................................................................................................................... 38
2.2 Functional Description ............................................................................................................... 38
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 38
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 39
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 39
2.2.4 ROM Table ............................................................................................................................... 39
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 39
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 39
3 Memory Map ....................................................................................................................... 43
4 Interrupts ............................................................................................................................ 45
5 JTAG Interface .................................................................................................................... 48
5.1 Block Diagram .......................................................................................................................... 49
5.2 Functional Description ............................................................................................................... 49
5.2.1 JTAG Interface Pins .................................................................................................................. 50
5.2.2 JTAG TAP Controller ................................................................................................................. 51
5.2.3 Shift Registers .......................................................................................................................... 52
5.2.4 Operational Considerations ........................................................................................................ 52
5.3 Initialization and Configuration ................................................................................................... 55
5.4 Register Descriptions ................................................................................................................ 55
5.4.1 Instruction Register (IR) ............................................................................................................. 55
5.4.2 Data Registers .......................................................................................................................... 57
6 System Control ................................................................................................................... 59
6.1 Functional Description ............................................................................................................... 59
6.1.1 Device Identification .................................................................................................................. 59
6.1.2 Reset Control ............................................................................................................................ 59
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Preliminary
LM3S6952 Microcontroller
6.1.3 Power Control ........................................................................................................................... 62
6.1.4 Clock Control ............................................................................................................................ 62
6.1.5 System Control ......................................................................................................................... 64
6.2 Initialization and Configuration ................................................................................................... 65
6.3 Register Map ............................................................................................................................ 65
6.4 Register Descriptions ................................................................................................................ 66
7 Hibernation Module .......................................................................................................... 120
7.1 Block Diagram ........................................................................................................................ 121
7.2 Functional Description ............................................................................................................. 121
7.2.1 Register Access Timing ........................................................................................................... 121
7.2.2 Clock Source .......................................................................................................................... 122
7.2.3 Battery Management ............................................................................................................... 122
7.2.4 Real-Time Clock ...................................................................................................................... 122
7.2.5 Non-Volatile Memory ............................................................................................................... 123
7.2.6 Power Control ......................................................................................................................... 123
7.2.7 Interrupts and Status ............................................................................................................... 123
7.3 Initialization and Configuration ................................................................................................. 124
7.3.1 Initialization ............................................................................................................................. 124
7.3.2 RTC Match Functionality (No Hibernation) ................................................................................ 124
7.3.3 RTC Match/Wake-Up from Hibernation ..................................................................................... 124
7.3.4 External Wake-Up from Hibernation .......................................................................................... 125
7.3.5 RTC/External Wake-Up from Hibernation .................................................................................. 125
7.4 Register Map .......................................................................................................................... 125
7.5 Register Descriptions .............................................................................................................. 126
8 Internal Memory ............................................................................................................... 139
8.1 Block Diagram ........................................................................................................................ 139
8.2 Functional Description ............................................................................................................. 139
8.2.1 SRAM Memory ........................................................................................................................ 139
8.2.2 Flash Memory ......................................................................................................................... 140
8.3 Flash Memory Initialization and Configuration ........................................................................... 141
8.3.1 Flash Programming ................................................................................................................. 141
8.3.2 Nonvolatile Register Programming ........................................................................................... 142
8.4 Register Map .......................................................................................................................... 142
8.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 143
8.6 Flash Register Descriptions (System Control Offset) .................................................................. 150
9 General-Purpose Input/Outputs (GPIOs) ....................................................................... 163
9.1 Functional Description ............................................................................................................. 163
9.1.1 Data Control ........................................................................................................................... 164
9.1.2 Interrupt Control ...................................................................................................................... 165
9.1.3 Mode Control .......................................................................................................................... 166
9.1.4 Commit Control ....................................................................................................................... 166
9.1.5 Pad Control ............................................................................................................................. 166
9.1.6 Identification ........................................................................................................................... 166
9.2 Initialization and Configuration ................................................................................................. 166
9.3 Register Map .......................................................................................................................... 168
9.4 Register Descriptions .............................................................................................................. 169
4 November 30, 2007
Preliminary
Table of Contents
10 General-Purpose Timers ................................................................................................. 204
10.1 Block Diagram ........................................................................................................................ 204
10.2 Functional Description ............................................................................................................. 205
10.2.1 GPTM Reset Conditions .......................................................................................................... 205
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 206
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 207
10.3 Initialization and Configuration ................................................................................................. 211
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 211
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 212
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 212
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 213
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 213
10.3.6 16-Bit PWM Mode ................................................................................................................... 214
10.4 Register Map .......................................................................................................................... 214
10.5 Register Descriptions .............................................................................................................. 215
11 Watchdog Timer ............................................................................................................... 240
11.1 Block Diagram ........................................................................................................................ 240
11.2 Functional Description ............................................................................................................. 240
11.3 Initialization and Configuration ................................................................................................. 241
11.4 Register Map .......................................................................................................................... 241
11.5 Register Descriptions .............................................................................................................. 242
12 Analog-to-Digital Converter (ADC) ................................................................................. 263
12.1 Block Diagram ........................................................................................................................ 264
12.2 Functional Description ............................................................................................................. 264
12.2.1 Sample Sequencers ................................................................................................................ 264
12.2.2 Module Control ........................................................................................................................ 265
12.2.3 Hardware Sample Averaging Circuit ......................................................................................... 266
12.2.4 Analog-to-Digital Converter ...................................................................................................... 266
12.2.5 Test Modes ............................................................................................................................. 266
12.2.6 Internal Temperature Sensor .................................................................................................... 266
12.3 Initialization and Configuration ................................................................................................. 267
12.3.1 Module Initialization ................................................................................................................. 267
12.3.2 Sample Sequencer Configuration ............................................................................................. 267
12.4 Register Map .......................................................................................................................... 268
12.5 Register Descriptions .............................................................................................................. 269
13 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 296
13.1 Block Diagram ........................................................................................................................ 297
13.2 Functional Description ............................................................................................................. 297
13.2.1 Transmit/Receive Logic ........................................................................................................... 297
13.2.2 Baud-Rate Generation ............................................................................................................. 298
13.2.3 Data Transmission .................................................................................................................. 299
13.2.4 Serial IR (SIR) ......................................................................................................................... 299
13.2.5 FIFO Operation ....................................................................................................................... 300
13.2.6 Interrupts ................................................................................................................................ 300
13.2.7 Loopback Operation ................................................................................................................ 301
13.2.8 IrDA SIR block ........................................................................................................................ 301
13.3 Initialization and Configuration ................................................................................................. 301
13.4 Register Map .......................................................................................................................... 302
November 30, 2007 5
Preliminary
LM3S6952 Microcontroller
13.5 Register Descriptions .............................................................................................................. 303
14 Synchronous Serial Interface (SSI) ................................................................................ 337
14.1 Block Diagram ........................................................................................................................ 337
14.2 Functional Description ............................................................................................................. 337
14.2.1 Bit Rate Generation ................................................................................................................. 338
14.2.2 FIFO Operation ....................................................................................................................... 338
14.2.3 Interrupts ................................................................................................................................ 338
14.2.4 Frame Formats ....................................................................................................................... 339
14.3 Initialization and Configuration ................................................................................................. 346
14.4 Register Map .......................................................................................................................... 347
14.5 Register Descriptions .............................................................................................................. 348
15 Inter-Integrated Circuit (I2C) Interface ............................................................................ 374
15.1 Block Diagram ........................................................................................................................ 374
15.2 Functional Description ............................................................................................................. 374
15.2.1 I2C Bus Functional Overview .................................................................................................... 375
15.2.2 Available Speed Modes ........................................................................................................... 377
15.2.3 Interrupts ................................................................................................................................ 378
15.2.4 Loopback Operation ................................................................................................................ 378
15.2.5 Command Sequence Flow Charts ............................................................................................ 379
15.3 Initialization and Configuration ................................................................................................. 385
15.4 I2C Register Map ..................................................................................................................... 386
15.5 Register Descriptions (I2C Master) ........................................................................................... 387
15.6 Register Descriptions (I2C Slave) ............................................................................................. 400
16 Ethernet Controller .......................................................................................................... 409
16.1 Block Diagram ........................................................................................................................ 410
16.2 Functional Description ............................................................................................................. 410
16.2.1 Internal MII Operation .............................................................................................................. 410
16.2.2 PHY Configuration/Operation ................................................................................................... 411
16.2.3 MAC Configuration/Operation .................................................................................................. 412
16.2.4 Interrupts ................................................................................................................................ 414
16.3 Initialization and Configuration ................................................................................................. 415
16.4 Ethernet Register Map ............................................................................................................. 415
16.5 Ethernet MAC Register Descriptions ......................................................................................... 417
16.6 MII Management Register Descriptions ..................................................................................... 434
17 Analog Comparators ....................................................................................................... 453
17.1 Block Diagram ........................................................................................................................ 454
17.2 Functional Description ............................................................................................................. 454
17.2.1 Internal Reference Programming .............................................................................................. 456
17.3 Initialization and Configuration ................................................................................................. 457
17.4 Register Map .......................................................................................................................... 457
17.5 Register Descriptions .............................................................................................................. 458
18 Pulse Width Modulator (PWM) ........................................................................................ 466
18.1 Block Diagram ........................................................................................................................ 466
18.2 Functional Description ............................................................................................................. 466
18.2.1 PWM Timer ............................................................................................................................. 466
18.2.2 PWM Comparators .................................................................................................................. 467
18.2.3 PWM Signal Generator ............................................................................................................ 468
6 November 30, 2007
Preliminary
Table of Contents
18.2.4 Dead-Band Generator ............................................................................................................. 469
18.2.5 Interrupt/ADC-Trigger Selector ................................................................................................. 469
18.2.6 Synchronization Methods ......................................................................................................... 469
18.2.7 Fault Conditions ...................................................................................................................... 470
18.2.8 Output Control Block ............................................................................................................... 470
18.3 Initialization and Configuration ................................................................................................. 470
18.4 Register Map .......................................................................................................................... 471
18.5 Register Descriptions .............................................................................................................. 472
19 Quadrature Encoder Interface (QEI) ............................................................................... 501
19.1 Block Diagram ........................................................................................................................ 501
19.2 Functional Description ............................................................................................................. 502
19.3 Initialization and Configuration ................................................................................................. 504
19.4 Register Map .......................................................................................................................... 504
19.5 Register Descriptions .............................................................................................................. 505
20 Pin Diagram ...................................................................................................................... 518
21 Signal Tables .................................................................................................................... 519
22 Operating Characteristics ............................................................................................... 533
23 Electrical Characteristics ................................................................................................ 534
23.1 DC Characteristics .................................................................................................................. 534
23.1.1 Maximum Ratings ................................................................................................................... 534
23.1.2 Recommended DC Operating Conditions .................................................................................. 534
23.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 535
23.1.4 Power Specifications ............................................................................................................... 535
23.1.5 Flash Memory Characteristics .................................................................................................. 537
23.2 AC Characteristics ................................................................................................................... 537
23.2.1 Load Conditions ...................................................................................................................... 537
23.2.2 Clocks .................................................................................................................................... 537
23.2.3 Analog-to-Digital Converter ...................................................................................................... 538
23.2.4 Analog Comparator ................................................................................................................. 539
23.2.5 I2C ......................................................................................................................................... 539
23.2.6 Ethernet Controller .................................................................................................................. 540
23.2.7 Hibernation Module ................................................................................................................. 543
23.2.8 Synchronous Serial Interface (SSI) ........................................................................................... 543
23.2.9 JTAG and Boundary Scan ........................................................................................................ 545
23.2.10 General-Purpose I/O ............................................................................................................... 546
23.2.11 Reset ..................................................................................................................................... 547
24 Package Information ........................................................................................................ 549
A Serial Flash Loader .......................................................................................................... 551
A.1 Serial Flash Loader ................................................................................................................. 551
A.2 Interfaces ............................................................................................................................... 551
A.2.1 UART ..................................................................................................................................... 551
A.2.2 SSI ......................................................................................................................................... 551
A.3 Packet Handling ...................................................................................................................... 552
A.3.1 Packet Format ........................................................................................................................ 552
A.3.2 Sending Packets ..................................................................................................................... 552
A.3.3 Receiving Packets ................................................................................................................... 552
November 30, 2007 7
Preliminary
LM3S6952 Microcontroller
A.4 Commands ............................................................................................................................. 553
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 553
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 553
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 553
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 554
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 554
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 554
B Register Quick Reference ............................................................................................... 556
C Ordering and Contact Information ................................................................................. 575
C.1 Ordering Information ................................................................................................................ 575
C.2 Kits ......................................................................................................................................... 575
C.3 Company Information .............................................................................................................. 575
C.4 Support Information ................................................................................................................. 576
8 November 30, 2007
Preliminary
Table of Contents
List of Figures
Figure 1-1. Stellaris® 6000 Series High-Level Block Diagram ............................................................... 29
Figure 2-1. CPU Block Diagram ......................................................................................................... 38
Figure 2-2. TPIU Block Diagram ........................................................................................................ 39
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 49
Figure 5-2. Test Access Port State Machine ....................................................................................... 52
Figure 5-3. IDCODE Register Format ................................................................................................. 57
Figure 5-4. BYPASS Register Format ................................................................................................ 58
Figure 5-5. Boundary Scan Register Format ....................................................................................... 58
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 60
Figure 7-1. Hibernation Module Block Diagram ................................................................................. 121
Figure 8-1. Flash Block Diagram ...................................................................................................... 139
Figure 9-1. GPIO Port Block Diagram ............................................................................................... 164
Figure 9-2. GPIODATA Write Example ............................................................................................. 165
Figure 9-3. GPIODATA Read Example ............................................................................................. 165
Figure 10-1. GPTM Module Block Diagram ........................................................................................ 205
Figure 10-2. 16-Bit Input Edge Count Mode Example .......................................................................... 209
Figure 10-3. 16-Bit Input Edge Time Mode Example ........................................................................... 210
Figure 10-4. 16-Bit PWM Mode Example ............................................................................................ 211
Figure 11-1. WDT Module Block Diagram .......................................................................................... 240
Figure 12-1. ADC Module Block Diagram ........................................................................................... 264
Figure 12-2. Internal Temperature Sensor Characteristic ..................................................................... 267
Figure 13-1. UART Module Block Diagram ......................................................................................... 297
Figure 13-2. UART Character Frame ................................................................................................. 298
Figure 13-3. IrDA Data Modulation ..................................................................................................... 300
Figure 14-1. SSI Module Block Diagram ............................................................................................. 337
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 339
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 340
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 341
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 341
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 342
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 343
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 343
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 344
Figure 14-10. MICROWIRE Frame Format (Single Frame) .................................................................... 345
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 346
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 346
Figure 15-1. I2C Block Diagram ......................................................................................................... 374
Figure 15-2. I2C Bus Configuration .................................................................................................... 375
Figure 15-3. START and STOP Conditions ......................................................................................... 375
Figure 15-4. Complete Data Transfer with a 7-Bit Address ................................................................... 376
Figure 15-5. R/S Bit in First Byte ........................................................................................................ 376
Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 376
Figure 15-7. Master Single SEND ...................................................................................................... 379
Figure 15-8. Master Single RECEIVE ................................................................................................. 380
Figure 15-9. Master Burst SEND ....................................................................................................... 381
November 30, 2007 9
Preliminary
LM3S6952 Microcontroller
Figure 15-10. Master Burst RECEIVE .................................................................................................. 382
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 383
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 384
Figure 15-13. Slave Command Sequence ............................................................................................ 385
Figure 16-1. Ethernet Controller Block Diagram .................................................................................. 410
Figure 16-2. Ethernet Controller ......................................................................................................... 410
Figure 16-3. Ethernet Frame ............................................................................................................. 412
Figure 17-1. Analog Comparator Module Block Diagram ..................................................................... 454
Figure 17-2. Structure of Comparator Unit .......................................................................................... 455
Figure 17-3. Comparator Internal Reference Structure ........................................................................ 456
Figure 18-1. PWM Module Block Diagram .......................................................................................... 466
Figure 18-2. PWM Count-Down Mode ................................................................................................ 467
Figure 18-3. PWM Count-Up/Down Mode .......................................................................................... 468
Figure 18-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 468
Figure 18-5. PWM Dead-Band Generator ........................................................................................... 469
Figure 19-1. QEI Block Diagram ........................................................................................................ 501
Figure 19-2. Quadrature Encoder and Velocity Predivider Operation .................................................... 503
Figure 20-1. Pin Connection Diagram ................................................................................................ 518
Figure 23-1. Load Conditions ............................................................................................................ 537
Figure 23-2. I2C Timing ..................................................................................................................... 540
Figure 23-3. External XTLP Oscillator Characteristics ......................................................................... 542
Figure 23-4. Hibernation Module Timing ............................................................................................. 543
Figure 23-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 544
Figure 23-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 544
Figure 23-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 545
Figure 23-8. JTAG Test Clock Input Timing ......................................................................................... 546
Figure 23-9. JTAG Test Access Port (TAP) Timing .............................................................................. 546
Figure 23-10. JTAG TRST Timing ........................................................................................................ 546
Figure 23-11. External Reset Timing (RST) .......................................................................................... 547
Figure 23-12. Power-On Reset Timing ................................................................................................. 548
Figure 23-13. Brown-Out Reset Timing ................................................................................................ 548
Figure 23-14. Software Reset Timing ................................................................................................... 548
Figure 23-15. Watchdog Reset Timing ................................................................................................. 548
Figure 24-1. 100-Pin LQFP Package .................................................................................................. 549
10 November 30, 2007
Preliminary
Table of Contents
List of Tables
Table 1. Documentation Conventions ............................................................................................ 20
Table 3-1. Memory Map ................................................................................................................... 43
Table 4-1. Exception Types .............................................................................................................. 45
Table 4-2. Interrupts ........................................................................................................................ 46
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 50
Table 5-2. JTAG Instruction Register Commands ............................................................................... 55
Table 6-1. System Control Register Map ........................................................................................... 65
Table 7-1. Hibernation Module Register Map ................................................................................... 125
Table 8-1. Flash Protection Policy Combinations ............................................................................. 141
Table 8-2. Flash Resident Registers ............................................................................................... 142
Table 8-3. Flash Register Map ........................................................................................................ 142
Table 9-1. GPIO Pad Configuration Examples ................................................................................. 167
Table 9-2. GPIO Interrupt Configuration Example ............................................................................ 167
Table 9-3. GPIO Register Map ....................................................................................................... 168
Table 10-1. Available CCP Pins ........................................................................................................ 205
Table 10-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 208
Table 10-3. Timers Register Map ...................................................................................................... 214
Table 11-1. Watchdog Timer Register Map ........................................................................................ 241
Table 12-1. Samples and FIFO Depth of Sequencers ........................................................................ 264
Table 12-2. ADC Register Map ......................................................................................................... 268
Table 13-1. UART Register Map ....................................................................................................... 302
Table 14-1. SSI Register Map .......................................................................................................... 347
Table 15-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 377
Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 386
Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 391
Table 16-1. TX & RX FIFO Organization ........................................................................................... 413
Table 16-2. Ethernet Register Map ................................................................................................... 416
Table 17-1. Comparator 0 Operating Modes ..................................................................................... 455
Table 17-2. Comparator 1 Operating Modes ..................................................................................... 455
Table 17-3. Comparator 2 Operating Modes ...................................................................................... 456
Table 17-4. Internal Reference Voltage and ACREFCTL Field Values ................................................. 456
Table 17-5. Analog Comparators Register Map ................................................................................. 458
Table 18-1. PWM Register Map ........................................................................................................ 471
Table 19-1. QEI Register Map .......................................................................................................... 504
Table 21-1. Signals by Pin Number ................................................................................................... 519
Table 21-2. Signals by Signal Name ................................................................................................. 523
Table 21-3. Signals by Function, Except for GPIO ............................................................................. 527
Table 21-4. GPIO Pins and Alternate Functions ................................................................................. 531
Table 22-1. Temperature Characteristics ........................................................................................... 533
Table 22-2. Thermal Characteristics ................................................................................................. 533
Table 23-1. Maximum Ratings .......................................................................................................... 534
Table 23-2. Recommended DC Operating Conditions ........................................................................ 534
Table 23-3. LDO Regulator Characteristics ....................................................................................... 535
Table 23-4. Detailed Power Specifications ........................................................................................ 536
Table 23-5. Flash Memory Characteristics ........................................................................................ 537
Table 23-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 537
November 30, 2007 11
Preliminary
LM3S6952 Microcontroller
Table 23-7. Clock Characteristics ..................................................................................................... 537
Table 23-8. Crystal Characteristics ................................................................................................... 538
Table 23-9. ADC Characteristics ....................................................................................................... 538
Table 23-10. Analog Comparator Characteristics ................................................................................. 539
Table 23-11. Analog Comparator Voltage Reference Characteristics .................................................... 539
Table 23-12. I2C Characteristics ......................................................................................................... 539
Table 23-13. 100BASE-TX Transmitter Characteristics ........................................................................ 540
Table 23-14. 100BASE-TX Transmitter Characteristics (informative) ..................................................... 540
Table 23-15. 100BASE-TX Receiver Characteristics ............................................................................ 540
Table 23-16. 10BASE-T Transmitter Characteristics ............................................................................ 540
Table 23-17. 10BASE-T Transmitter Characteristics (informative) ......................................................... 541
Table 23-18. 10BASE-T Receiver Characteristics ................................................................................ 541
Table 23-19. Isolation Transformers ................................................................................................... 541
Table 23-20. Ethernet Reference Crystal ............................................................................................ 542
Table 23-21. External XTLP Oscillator Characteristics ......................................................................... 542
Table 23-22. Hibernation Module Characteristics ................................................................................. 543
Table 23-23. SSI Characteristics ........................................................................................................ 543
Table 23-24. JTAG Characteristics ..................................................................................................... 545
Table 23-25. GPIO Characteristics ..................................................................................................... 547
Table 23-26. Reset Characteristics ..................................................................................................... 547
Table C-1. Part Ordering Information ............................................................................................... 575
12 November 30, 2007
Preliminary
Table of Contents
List of Registers
System Control .............................................................................................................................. 59
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 67
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 69
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 70
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 71
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 72
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 73
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 74
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 75
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 79
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 80
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 82
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 83
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 85
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 86
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 88
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 90
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 92
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 94
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 96
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 98
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 100
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 103
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 106
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 109
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 111
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 113
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 115
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 116
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 118
Hibernation Module ..................................................................................................................... 120
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 127
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 128
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 129
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 130
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 131
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 133
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 134
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 135
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 136
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 137
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 138
Internal Memory ........................................................................................................................... 139
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 144
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 145
November 30, 2007 13
Preliminary
LM3S6952 Microcontroller
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 146
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 148
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 149
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 150
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 151
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 152
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 153
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 154
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 155
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 156
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 157
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 158
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 159
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 160
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 161
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 162
General-Purpose Input/Outputs (GPIOs) ................................................................................... 163
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 170
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 171
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 172
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 173
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 174
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 175
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 176
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 177
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 178
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 179
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 181
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 182
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 183
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 184
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 185
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 186
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 187
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 188
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 189
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 190
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 192
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 193
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 194
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 195
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 196
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 197
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 198
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 199
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 200
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 201
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 202
14 November 30, 2007
Preliminary
Table of Contents
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 203
General-Purpose Timers ............................................................................................................. 204
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 216
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 217
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 219
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 221
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 224
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 226
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 227
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 228
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 230
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 231
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 232
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 233
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 234
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 235
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 236
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 237
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 238
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 239
Watchdog Timer ........................................................................................................................... 240
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 243
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 244
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 245
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 246
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 247
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 248
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 249
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 250
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 251
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 252
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 253
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 254
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 255
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 256
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 257
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 258
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 259
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 260
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 261
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 262
Analog-to-Digital Converter (ADC) ............................................................................................. 263
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 270
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 271
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 272
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 273
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 274
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 275
November 30, 2007 15
Preliminary
LM3S6952 Microcontroller
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 278
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 279
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 280
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 281
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 282
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 284
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 287
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 287
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 287
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 287
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 288
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 288
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 288
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 288
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 289
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 289
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 290
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 290
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 292
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 293
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 294
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 296
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 304
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 306
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 308
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 310
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 311
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 312
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 313
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 315
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 317
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 319
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 321
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 322
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 323
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 325
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 326
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 327
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 328
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 329
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 330
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 331
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 332
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 333
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 334
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 335
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 336
16 November 30, 2007
Preliminary
Table of Contents
Synchronous Serial Interface (SSI) ............................................................................................ 337
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 349
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 351
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 353
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 354
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 356
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 357
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 359
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 360
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 361
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 362
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 363
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 364
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 365
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 366
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 367
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 368
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 369
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 370
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 371
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 372
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 373
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 374
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 388
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 389
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 393
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 394
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 395
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 396
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 397
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 398
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 399
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 401
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 402
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 404
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 405
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 406
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 407
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 408
Ethernet Controller ...................................................................................................................... 409
Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 418
Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 420
Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 421
Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 422
Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 423
Register 6: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 424
Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 426
November 30, 2007 17
Preliminary
LM3S6952 Microcontroller
Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 427
Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 428
Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 429
Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 430
Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 431
Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 432
Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 433
Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 434
Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 435
Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 437
Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 439
Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 440
Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 441
Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 443
Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 444
Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 445
Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address
0x11 .............................................................................................................................. 447
Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 449
Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 450
Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 451
Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 452
Analog Comparators ................................................................................................................... 453
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 459
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 460
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 461
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 462
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 463
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 463
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60 ....................................................... 463
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 464
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 464
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64 ...................................................... 464
Pulse Width Modulator (PWM) .................................................................................................... 466
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 473
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 474
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 475
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 476
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 477
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 478
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 479
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 480
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 481
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 482
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 482
18 November 30, 2007
Preliminary
Table of Contents
Register 12: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 484
Register 13: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 484
Register 14: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 486
Register 15: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 486
Register 16: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 487
Register 17: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 487
Register 18: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 488
Register 19: PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 488
Register 20: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 489
Register 21: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 489
Register 22: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 490
Register 23: PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 490
Register 24: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 491
Register 25: PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 491
Register 26: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 492
Register 27: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 492
Register 28: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 495
Register 29: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 495
Register 30: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 498
Register 31: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 498
Register 32: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 499
Register 33: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 499
Register 34: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 500
Register 35: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 500
Quadrature Encoder Interface (QEI) .......................................................................................... 501
Register 1: QEI Control (QEICTL), offset 0x000 ................................................................................ 506
Register 2: QEI Status (QEISTAT), offset 0x004 ................................................................................ 508
Register 3: QEI Position (QEIPOS), offset 0x008 .............................................................................. 509
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... 510
Register 5: QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... 511
Register 6: QEI Timer (QEITIME), offset 0x014 ................................................................................. 512
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ............................................................. 513
Register 8: QEI Velocity (QEISPEED), offset 0x01C .......................................................................... 514
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................... 515
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............................................................. 516
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ..................................................... 517
November 30, 2007 19
Preliminary
LM3S6952 Microcontroller
About This Document
This data sheet provides reference information for the LM3S6952 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■ ARM® Cortex™-M3 Technical Reference Manual
■ ARM® CoreSight Technical Reference Manual
■ ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 20.
Table 1. Documentation Conventions
Notation Meaning
General Register Notation
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
REGISTER
bit A single bit in a register.
bit field Two or more consecutive and related bits.
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 43.
offset 0xnnn
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Register N
20 November 30, 2007
Preliminary
About This Document
Notation Meaning
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
reserved
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
yy:xx
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Register Bit/Field
Types
RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO Software can read this field. Always write the chip reset value.
R/W Software can read or write this field.
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1C
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
W1C
WO Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field This value in the register bit diagram shows the bit/field value after any reset, unless noted.
Reset Value
0 Bit cleared to 0 on chip reset.
1 Bit set to 1 on chip reset.
- Nondeterministic.
Pin/Signal Notation
[ ] Pin alternate function; a pin defaults to the signal without the brackets.
pin Refers to the physical connection on the package.
signal Refers to the electrical signal encoding of a pin.
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
assert a signal
deassert a signal Change the value of the signal from the logically True state to the logically False state.
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
SIGNAL
Numbers
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
X
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
0x
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1 Architectural Overview
The Luminary Micro Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The Stellaris® family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris® LM3S1000 series extends the Stellaris® family with larger on-chip
memories, enhanced power management, and expanded I/O and control capabilities. The Stellaris®
LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris
family with Bosch CAN networking technology, the golden standard in short-haul industrial networks.
The Stellaris® LM3S2000 series also marks the first integration of CAN capabilities with the
revolutionary Cortex-M3 core. The Stellaris® LM3S6000 series combines both a 10/100 Ethernet
Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated
connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC
and PHY available in an ARM architecture MCU. The Stellaris® LM3S8000 series combines Bosch
Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and
Physical (PHY) layer.
The LM3S6952 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S6952 microcontroller features
a Battery-backed Hibernation module to efficiently power down the LM3S6952 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S6952 microcontroller perfectly for
battery applications.
In addition, the LM3S6952 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S6952 microcontroller is code-compatible
to all members of the extensive Stellaris® family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
1.1 Product Features
The LM3S6952 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
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– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 34 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
– 256 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 64 KB single-cycle SRAM
■ General-Purpose Timers
– Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
• To trigger analog-to-digital conversions
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
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• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
• ADC event trigger
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ 10/100 Ethernet Controller
– Conforms to the IEEE 802.3-2002 Specification
– Full- and half-duplex for both 100 Mbps and 10 Mbps operation
– Integrated 10/100 Mbps Transceiver (PHY)
– Automatic MDI/MDI-X cross-over correction
– Programmable MAC address
– Power-saving and power-down modes
■ Synchronous Serial Interface (SSI)
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– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Three fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator with fractional divider
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ ADC
– Single- and differential-input configurations
– Three 10-bit channels (inputs) when used as single-ended inputs
– Sample rate of 500 thousand samples/second
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Each sequence triggered by software or internal event (timers, analog comparators, PWM
or GPIO)
– On-chip temperature sensor
■ Analog Comparators
– Three independent integrated analog comparators
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– Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
– Compare external pin input to external pin input or to internal programmable voltage reference
■ I2C
– Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
– Interrupt generation
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ PWM
– Two PWM generator blocks, each with one 16-bit counter, two comparators, a PWM generator,
and a dead-band generator
– One 16-bit counter
• Runs in Down or Up/Down mode
• Output frequency controlled by a 16-bit load value
• Load value updates can be synchronized
• Produces output signals at zero and load value
– Two PWM comparators
• Comparator value updates can be synchronized
• Produces output signals on match
– PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
• Produces two independent PWM signals
– Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge
• Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
• PWM output enable of each PWM signal
• Optional output inversion of each PWM signal (polarity control)
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• Optional fault handling for each PWM signal
• Synchronization of timers in the PWM generator blocks
• Synchronization of timer/comparator updates across the PWM generator blocks
• Interrupt status summary of the PWM generator blocks
– Can initiate an ADC sample sequence
■ QEI
– Hardware position integrator tracks the encoder position
– Velocity capture using built-in timer
– Interrupt generation on index pulse, velocity-timer expiration, direction change, and quadrature
error detection
■ GPIOs
– 6-43 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
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– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial-range 100-pin RoHS-compliant LQFP package
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
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1.3 High-Level Block Diagram
Figure 1-1 on page 29 represents the full set of features in the Stellaris® 6000 series of devices;
not all features may be available on the LM3S6952 microcontroller.
Figure 1-1. Stellaris® 6000 Series High-Level Block Diagram
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S6952 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 575.
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1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 37)
All members of the Stellaris® product family, including the LM3S6952 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 37 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S6952 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 34 interrupts.
“Interrupts” on page 45 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S6952 controller features Pulse Width Modulation (PWM) outputs
and the Quadrature Encoder Interface (QEI).
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
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wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
On the LM3S6952, PWM motion control functionality can be achieved through:
■ Dedicated, flexible motion control hardware using the PWM pins
■ The motion control features of the general-purpose timers using the CCP pins
PWM Pins (see page 466)
The LM3S6952 PWM module consists of two PWM generator blocks and a control block. Each
PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a
PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control
block determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. The output of the PWM
generation blocks are managed by the output control block before being passed to the device pins.
CCP Pins (see page 210)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.2.2 QEI (see page 501)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
The Stellaris quadrature encoder with index (QEI) module interprets the code produced by a
quadrature encoder wheel to integrate position over time and determine direction of rotation. In
addition, it can capture a running estimate of the velocity of the encoder wheel.
1.4.3 Analog Peripherals
To handle analog signals, the LM3S6952 microcontroller offers an Analog-to-Digital Converter
(ADC).
For support of analog signals, the LM3S6952 microcontroller offers three analog comparators.
1.4.3.1 ADC (see page 263)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The LM3S6952 ADC module features 10-bit conversion resolution and supports three input channels,
plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up
to eight analog input sources without controller intervention. Each sample sequence provides flexible
programming with fully configurable input source, trigger events, interrupt generation, and sequence
priority.
1.4.3.2 Analog Comparators (see page 453)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
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The LM3S6952 microcontroller provides three independent integrated analog comparators that can
be configured to drive an output or generate an interrupt or ADC event.
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
1.4.4 Serial Communications Peripherals
The LM3S6952 controller supports both asynchronous and synchronous serial communications
with:
■ Three fully programmable 16C550-type UARTs
■ One SSI module
■ One I2C module
■ Ethernet controller
1.4.4.1 UART (see page 296)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S6952 controller includes three fully programmable 16C550-type UARTs that support data
transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.4.2 SSI (see page 337)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S6952 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
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The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.4.3 I2C (see page 374)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL).
The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking
devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and
diagnostic purposes in product development and manufacture.
The LM3S6952 controller includes one I2C module that provides the ability to communicate to other
IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write
and read) data.
Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive,
Slave Transmit, and Slave Receive.
A Stellaris® I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error). The I2C slave generates
interrupts when data has been sent or requested by a master.
1.4.4.4 Ethernet Controller (see page 409)
Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet
has been standardized as IEEE 802.3. It defines a number of wiring and signaling standards for the
physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer,
and a common addressing format.
The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and
network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3
specifications and fully supports 10BASE-T and 100BASE-TX standards. In addition, the Ethernet
Controller supports automatic MDI/MDI-X cross-over correction.
1.4.5 System Peripherals
1.4.5.1 Programmable GPIOs (see page 163)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris® GPIO module is composed of seven physical GPIO blocks, each corresponding to
an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation
IP for Real-Time Microcontrollers specification) and supports 6-43 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page
519 for the signals available to each GPIO pin).
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The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines.
1.4.5.2 Three Programmable Timers (see page 204)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris® General-Purpose Timer Module (GPTM) contains three GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
Timers can also be used to trigger analog-to-digital (ADC) conversions.
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.5.3 Watchdog Timer (see page 240)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
The Stellaris® Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
1.4.6 Memory Peripherals
The LM3S6952 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.6.1 SRAM (see page 139)
The LM3S6952 static random access memory (SRAM) controller supports 64 KB SRAM. The internal
SRAM of the Stellaris® devices is located at offset 0x0000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
1.4.6.2 Flash (see page 140)
The LM3S6952 Flash controller supports 256 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
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1.4.7 Additional Features
1.4.7.1 Memory Map (see page 43)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S6952 controller can be found in “Memory Map” on page 43. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
1.4.7.2 JTAG TAP Controller (see page 48)
The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the
Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG
data registers can be used to test the interconnects of assembled printed circuit boards, obtain
manufacturing information on the components, and observe and/or control the inputs and outputs
of the controller during normal operation. The JTAG port provides a high degree of testability and
chip-level access at a low cost.
The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
1.4.7.3 System Control and Clocks (see page 59)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
1.4.7.4 Hibernation Module (see page 120)
The Hibernation module provides logic to switch power off to the main processor and peripherals,
and to wake on external or time-based events. The Hibernation module includes power-sequencing
logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt
signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used
for saving state during hibernation.
1.4.8 Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 518
■ “Signal Tables” on page 519
■ “Operating Characteristics” on page 533
■ “Electrical Characteristics” on page 534
November 30, 2007 35
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LM3S6952 Microcontroller
■ “Package Information” on page 549
36 November 30, 2007
Preliminary
Architectural Overview
2 ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that
meets the needs of minimal memory implementation, reduced pin count, and low power consumption,
while delivering outstanding computational performance and exceptional system response to
interrupts. Features include:
■ Compact core.
■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of
memory for microcontroller class applications.
■ Rapid application execution through Harvard architecture characterized by separate buses for
instruction and data.
■ Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.
■ Migration from the ARM7™ processor family for better performance and power efficiency.
■ Full-featured debug solution with a:
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
The Stellaris® family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motors.
For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference
Manual.
November 30, 2007 37
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LM3S6952 Microcontroller
2.1 Block Diagram
Figure 2-1. CPU Block Diagram
Private Peripheral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
Instrumentation
Trace Macrocell
Trace
Port
Interface
Unit
CM3 Core
Instructions Data
Flash
Patch and
Breakpoint
Memory
Protection
Unit
Adv. High-
Perf. Bus
Access Port
Nested
Vectored
Interrupt
Controller
Serial Wire JTAG
Debug Port
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
ROM
Table
Private
Peripheral
Bus
(external)
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex-M3
2.2 Functional Description
Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
This section describes the Stellaris® implementation.
Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 38. As
noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are
flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested
Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.
2.2.1 Serial Wire and JTAG Debug
Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the
ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris® devices.
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
38 November 30, 2007
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ARM Cortex-M3 Processor Core
2.2.2 Embedded Trace Macrocell (ETM)
ETM was not implemented in the Stellaris® devices. This means Chapters 15 and 16 of the ARM®
Cortex™-M3 Technical Reference Manual can be ignored.
2.2.3 Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer. The Stellaris® devices have implemented TPIU as shown in Figure 2-2 on page 39.
This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference
Manual, however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
ATB
Interface
Asynchronous FIFO
APB
Interface
Trace Out
(serializer)
Debug
ATB
Slave
Port
APB
Slave
Port
Serial Wire
Trace Port
(SWO)
2.2.4 ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
2.2.5 Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S6952 controller and supports the standard
ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for
protection regions, overlapping protection regions, access permissions, and exporting memory
attributes to the system.
2.2.6 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
■ Facilitates low-latency exception and interrupt handling
■ Controls power management
■ Implements system control registers
November 30, 2007 39
Preliminary
LM3S6952 Microcontroller
The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of
priority. The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge
of the stacked (nested) interrupts to enable tail-chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode
if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference
Manual). Any other user-mode access causes a bus fault.
All NVIC registers are accessible using byte, halfword, and word unless otherwise stated.
All NVIC registers and system debug registers are little endian regardless of the endianness state
of the processor.
2.2.6.1 Interrupts
The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts
and interrupt priorities. The LM3S6952 microcontroller supports 34 interrupts with eight priority
levels.
2.2.6.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
Functional Description
The timer consists of three registers:
■ A control and status counter to configure its clock, enable the counter, enable the SysTick
interrupt, and determine counter status.
■ The reload value for the counter, used to provide the counter's wrap value.
■ The current value of the counter.
A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris® devices.
When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value
in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks.
Writing a value of zero to the Reload Value register disables the counter on the next wrap. When
the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
40 November 30, 2007
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ARM Cortex-M3 Processor Core
Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write
does not trigger the SysTick exception logic. On a read, the current value is the value of the register
at the time the register is accessed.
If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect
to a reference clock. The reference clock can be the core clock or an external clock source.
SysTick Control and Status Register
Use the SysTick Control and Status Register to enable the SysTick features. The reset is
0x0000.0000.
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
31:17 reserved RO 0
Returns 1 if timer counted to 0 since last time this was read. Clears on read by
application. If read by the debugger using the DAP, this bit is cleared on read-only
if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the
COUNTFLAG bit is not changed by the debugger read.
16 COUNTFLAG R/W 0
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
15:3 reserved RO 0
0 = external reference clock. (Not implemented for Stellaris microcontrollers.)
1 = core clock.
If no reference clock is provided, it is held at 1 and so gives the same time as the
core clock. The core clock must be at least 2.5 times faster than the reference clock.
If it is not, the count values are unpredictable.
2 CLKSOURCE R/W 0
1 = counting down to 0 pends the SysTick handler.
0 = counting down to 0 does not pend the SysTick handler. Software can use the
COUNTFLAG to determine if ever counted to 0.
1 TICKINT R/W 0
1 = counter operates in a multi-shot way. That is, counter loads with the Reload
value and then begins counting down. On reaching 0, it sets the COUNTFLAG to
1 and optionally pends the SysTick handler, based on TICKINT. It then loads the
Reload value again, and begins counting.
0 = counter disabled.
0 ENABLE R/W 0
SysTick Reload Value Register
Use the SysTick Reload Value Register to specify the start value to load into the current value
register when the counter reaches 0. It can be any value between 1 and 0x00FF.FFFF. A start value
of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated
when counting from 1 to 0.
Therefore, as a multi-shot timer, repeated over and over, it fires every N+1 clock pulse, where N is
any value from 1 to 0x00FF.FFFF. So, if the tick interrupt is required every 100 clock pulses, 99
must be written into the RELOAD. If a new value is written on each tick interrupt, so treated as single
shot, then the actual count down must be written. For example, if a tick is next required after 400
clock pulses, 400 must be written into the RELOAD.
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a read-modify-write
operation.
31:24 reserved RO 0
November 30, 2007 41
Preliminary
LM3S6952 Microcontroller
Bit/Field Name Type Reset Description
23:0 RELOAD W1C - Value to load into the SysTick Current Value Register when the counter reaches 0.
SysTick Current Value Register
Use the SysTick Current Value Register to find the current value in the register.
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
31:24 reserved RO 0
Current value at the time the register is accessed. No read-modify-write protection is
provided, so change with care.
This register is write-clear. Writing to it with any value clears the register to 0. Clearing
this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
23:0 CURRENT W1C -
SysTick Calibration Value Register
The SysTick Calibration Value register is not implemented.
42 November 30, 2007
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ARM Cortex-M3 Processor Core
3 Memory Map
The memory map for the LM3S6952 controller is provided in Table 3-1 on page 43.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Important: In Table 3-1 on page 43, addresses not listed are reserved.
Table 3-1. Memory Mapa
For details on
registers, see
page ...
Start End Description
Memory
0x0000.0000 0x0003.FFFF On-chip flash b 143
0x2000.0000 0x2000.FFFF Bit-banded on-chip SRAMc 143
0x2010.0000 0x21FF.FFFF Reserved non-bit-banded SRAM space -
0x2200.0000 0x23FF.FFFF Bit-band alias of 0x2000.0000 through 0x200F.FFFF 139
0x2400.0000 0x3FFF.FFFF Reserved non-bit-banded SRAM space -
FiRM Peripherals
0x4000.0000 0x4000.0FFF Watchdog timer 242
0x4000.4000 0x4000.4FFF GPIO Port A 169
0x4000.5000 0x4000.5FFF GPIO Port B 169
0x4000.6000 0x4000.6FFF GPIO Port C 169
0x4000.7000 0x4000.7FFF GPIO Port D 169
0x4000.8000 0x4000.8FFF SSI0 348
0x4000.C000 0x4000.CFFF UART0 303
0x4000.D000 0x4000.DFFF UART1 303
0x4000.E000 0x4000.EFFF UART2 303
Peripherals
0x4002.0000 0x4002.07FF I2C Master 0 387
0x4002.0800 0x4002.0FFF I2C Slave 0 400
0x4002.4000 0x4002.4FFF GPIO Port E 169
0x4002.5000 0x4002.5FFF GPIO Port F 169
0x4002.6000 0x4002.6FFF GPIO Port G 169
0x4002.8000 0x4002.8FFF PWM 472
0x4002.C000 0x4002.CFFF QEI0 505
0x4003.0000 0x4003.0FFF Timer0 215
0x4003.1000 0x4003.1FFF Timer1 215
0x4003.2000 0x4003.2FFF Timer2 215
0x4003.8000 0x4003.8FFF ADC 269
0x4003.C000 0x4003.CFFF Analog Comparators 453
0x4004.8000 0x4004.8FFF Ethernet Controller 417
0x400F.C000 0x400F.CFFF Hibernation Module 126
November 30, 2007 43
Preliminary
LM3S6952 Microcontroller
For details on
registers, see
page ...
Start End Description
0x400F.D000 0x400F.DFFF Flash control 143
0x400F.E000 0x400F.EFFF System control 66
0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF -
Private Peripheral Bus
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM)
0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT)
0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB)
0xE000.3000 0xE000.DFFF Reserved
0xE000.E000 0xE000.EFFF Nested Vectored Interrupt Controller (NVIC)
0xE000.F000 0xE003.FFFF Reserved
0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU)
0xE004.1000 0xE004.1FFF Reserved -
0xE004.2000 0xE00F.FFFF Reserved -
0xE010.0000 0xFFFF.FFFF Reserved for vendor peripherals -
a. All reserved space returns a bus fault when read or written.
b. The unavailable flash will bus fault throughout this range.
c. The unavailable SRAM will bus fault throughout this range.
44 November 30, 2007
Preliminary
Memory Map
4 Interrupts
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions. All exceptions are handled in Handler Mode. The processor state is
automatically stored to the stack on an exception, and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which
enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back
interrupts to be performed without the overhead of state saving and restoration.
Table 4-1 on page 45 lists all the exceptions. Software can set eight priority levels on seven of these
exceptions (system handlers) as well as on 34 interrupts (listed in Table 4-2 on page 46).
Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts
are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt
Priority registers. You can also group priorities by splitting priority levels into pre-emption priorities
and subpriorities. All the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt
Controller” in the ARM® Cortex™-M3 Technical Reference Manual.
Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and
a Hard Fault. Note that 0 is the default priority for all the settable priorities.
If you assign the same priority level to two or more interrupts, their hardware priority (the lower the
position number) determines the order in which the processor activates them. For example, if both
GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority.
See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM®
Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts.
Note: In Table 4-2 on page 46 interrupts not listed are reserved.
Table 4-1. Exception Types
Exception Type Position Prioritya Description
- 0 - Stack top is loaded from first entry of vector table on reset.
Invoked on power up and warm reset. On first instruction, drops to lowest
priority (and then is called the base level of activation). This is
asynchronous.
Reset 1 -3 (highest)
Cannot be stopped or preempted by any exception but reset. This is
asynchronous.
An NMI is only producible by software, using the NVIC Interrupt Control
State register.
Non-Maskable 2 -2
Interrupt (NMI)
All classes of Fault, when the fault cannot activate due to priority or the
configurable fault handler has been disabled. This is synchronous.
Hard Fault 3 -1
MPU mismatch, including access violation and no match. This is
synchronous.
The priority of this exception can be changed.
Memory Management 4 settable
Pre-fetch fault, memory access fault, and other address/memory related
faults. This is synchronous when precise and asynchronous when
imprecise.
You can enable or disable this fault.
Bus Fault 5 settable
Usage fault, such as undefined instruction executed or illegal state
transition attempt. This is synchronous.
Usage Fault 6 settable
- 7-10 - Reserved.
SVCall 11 settable System service call with SVC instruction. This is synchronous.
November 30, 2007 45
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LM3S6952 Microcontroller
Exception Type Position Prioritya Description
Debug monitor (when not halting). This is synchronous, but only active
when enabled. It does not activate if lower priority than the current
activation.
Debug Monitor 12 settable
- 13 - Reserved.
Pendable request for system service. This is asynchronous and only
pended by software.
PendSV 14 settable
SysTick 15 settable System tick timer has fired. This is asynchronous.
Asserted from outside the ARM Cortex-M3 core and fed through the NVIC
(prioritized). These are all asynchronous. Table 4-2 on page 46 lists the
interrupts on the LM3S6952 controller.
16 and settable
above
Interrupts
a. 0 is the default priority for all the settable priorities.
Table 4-2. Interrupts
Interrupt (Bit in Interrupt Registers) Description
0 GPIO Port A
1 GPIO Port B
2 GPIO Port C
3 GPIO Port D
4 GPIO Port E
5 UART0
6 UART1
7 SSI0
8 I2C0
9 PWM Fault
10 PWM Generator 0
11 PWM Generator 1
13 QEI0
14 ADC Sequence 0
15 ADC Sequence 1
16 ADC Sequence 2
17 ADC Sequence 3
18 Watchdog timer
19 Timer0 A
20 Timer0 B
21 Timer1 A
22 Timer1 B
23 Timer2 A
24 Timer2 B
25 Analog Comparator 0
26 Analog Comparator 1
27 Analog Comparator 2
28 System Control
29 Flash Control
30 GPIO Port F
46 November 30, 2007
Preliminary
Interrupts
Interrupt (Bit in Interrupt Registers) Description
31 GPIO Port G
33 UART2
42 Ethernet Controller
43 Hibernation Module
November 30, 2007 47
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LM3S6952 Microcontroller
5 JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
The JTAG module has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions:
– BYPASS instruction
– IDCODE instruction
– SAMPLE/PRELOAD instruction
– EXTEST instruction
– INTEST instruction
■ ARM additional instructions:
– APACC instruction
– DPACC instruction
– ABORT instruction
■ Integrated ARM Serial Wire Debug (SWD)
See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG
controller.
48 November 30, 2007
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JTAG Interface
5.1 Block Diagram
Figure 5-1. JTAG Module Block Diagram
Instruction Register (IR)
TAP Controller
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TRST
TCK
TMS
TDI
TDO
Cortex-M3
Debug
Port
5.2 Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 49. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and
TMS inputs. The current state of the TAP controller depends on the current value of TRST and the
sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when
the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel
load registers. The current state of the TAP controller also determines whether the Instruction
Register (IR) chain or one of the Data Register (DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 5-2 on page 55 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 545 for JTAG timing diagrams.
November 30, 2007 49
Preliminary
LM3S6952 Microcontroller
5.2.1 JTAG Interface Pins
The JTAG interface consists of five standard pins: TRST, TCK, TMS, TDI, and TDO. These pins and
their associated reset state are given in Table 5-1 on page 50. Detailed information on each pin
follows.
Table 5-1. JTAG Port Pins Reset State
Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value
TRST Input Enabled Disabled N/A N/A
TCK Input Enabled Disabled N/A N/A
TMS Input Enabled Disabled N/A N/A
TDI Input Enabled Disabled N/A N/A
TDO Output Enabled Disabled 2-mA driver High-Z
5.2.1.1 Test Reset Input (TRST)
The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP
controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the
Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters
the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction,
IDCODE.
By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled
on PB7/TRST; otherwise JTAG communication could be lost.
5.2.1.2 Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers
that are daisy-chained together can synchronously communicate serial test data between
components. During normal operation, TCK is driven by a free-running clock with a nominal 50%
duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK
is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction
and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no
clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down
resistors can be turned off to save internal power as long as the TCK pin is constantly being driven
by an external source.
5.2.1.3 Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered.
Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the
value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can
be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine
can be seen in its entirety in Figure 5-2 on page 52.
50 November 30, 2007
Preliminary
JTAG Interface
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost.
5.2.1.4 Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on
the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling
edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost.
5.2.1.5 Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the
pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states.
5.2.2 JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 5-2 on page 52. The TAP controller
state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR)
or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module
to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed
information on the function of the TAP controller and the operations that occur in each state, please
refer to IEEE Standard 1149.1.
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Figure 5-2. Test Access Port State Machine
Test Logic Reset
Run Test Idle Select DR Scan Select IR Scan
Capture DR Capture IR
Shift DR Shift IR
Exit 1 DR Exit 1 IR
Exit 2 DR Exit 2 IR
Pause DR Pause IR
Update DR Update IR
1 1 1
1 1
1
1 1
1 1
1 1
1 1
1 0 1 0
0 0
0 0
0 0
0 0
0 0
0 0
0
0
5.2.3 Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 55.
5.2.4 Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG pins
can be programmed to be GPIOs, board configuration and reset conditions on these pins must be
considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the
method for switching between these two operational modes is described below.
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5.2.4.1 GPIO Functionality
When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting
GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate
hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and
PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging
or board-level testing, this provides five more GPIOs for use in the design.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors,
and apply RST or power-cycle the part.
In addition, it is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 190) have been set to 1.
Recovering a "Locked" Device
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug sequence that can be used to recover the device. Performing
a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset
mass erases the flash memory. The sequence to recover the device is:
1. Assert and hold the RST signal.
2. Perform the JTAG-to-SWD switch sequence.
3. Perform the SWD-to-JTAG switch sequence.
4. Perform the JTAG-to-SWD switch sequence.
5. Perform the SWD-to-JTAG switch sequence.
6. Perform the JTAG-to-SWD switch sequence.
7. Perform the SWD-to-JTAG switch sequence.
8. Perform the JTAG-to-SWD switch sequence.
9. Perform the SWD-to-JTAG switch sequence.
10. Perform the JTAG-to-SWD switch sequence.
11. Perform the SWD-to-JTAG switch sequence.
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12. Release the RST signal.
The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug
(SWD)” on page 54. When performing switch sequences for the purpose of recovering the debug
capabilities of the device, only steps 1 and 2 of the switch sequence need to be performed.
5.2.4.2 ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller
in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the
following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test
Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run
Test Idle, Select DR, Select IR, and Test Logic Reset states.
Stepping through this sequences of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
probability of this sequence occurring during normal operation of the TAP controller, it should not
affect normal performance of the JTAG interface.
JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in SWD mode, before sending the switch sequence, the SWD goes into the line reset
state.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to JTAG mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
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2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C.
3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic
Reset state.
5.3 Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. This is done by enabling the five JTAG
pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register.
5.4 Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The registers
can be broken down into two main categories: Instruction Registers and Data Registers.
5.4.1 Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register
connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct
states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the
chain and updated, they are interpreted as the current instruction. The decode of the Instruction
Register bits is shown in Table 5-2 on page 55. A detailed explanation of each instruction, along
with its associated Data Register, follows.
Table 5-2. JTAG Instruction Register Commands
IR[3:0] Instruction Description
Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD
instruction onto the pads.
0000 EXTEST
Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD
instruction into the controller.
0001 INTEST
Captures the current I/O values and shifts the sampled values out of the Boundary Scan
Chain while new preload data is shifted in.
0010 SAMPLE / PRELOAD
1000 ABORT Shifts data into the ARM Debug Port Abort Register.
1010 DPACC Shifts data into and out of the ARM DP Access Register.
1011 APACC Shifts data into and out of the ARM AC Access Register.
Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE
chain and shifts it out.
1110 IDCODE
1111 BYPASS Connects TDI to TDO through a single Shift Register chain.
All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO.
5.4.1.1 EXTEST Instruction
The EXTEST instruction does not have an associated Data Register chain. The EXTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. This allows
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tests to be developed that drive known values out of the controller, which can be used to verify
connectivity.
5.4.1.2 INTEST Instruction
The INTEST instruction does not have an associated Data Register chain. The INTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. This allows tests
to be developed that drive known values into the controller, which can be used for testing. It is
important to note that although the RST input pin is on the Boundary Scan Data Register chain, it
is only observable.
5.4.1.3 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data
Register” on page 58 for more information.
5.4.1.4 ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. Please see the “ABORT Data Register” on page 58 for more
information.
5.4.1.5 DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. Please see “DPACC
Data Register” on page 58 for more information.
5.4.1.6 APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
Please see “APACC Data Register” on page 58 for more information.
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5.4.1.7 IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure their input and output data streams. IDCODE is the default instruction that is loaded into
the JTAG Instruction Register when a power-on-reset (POR) is asserted, TRST is asserted, or the
Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 57 for more
information.
5.4.1.8 BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 57 for
more information.
5.4.2 Data Registers
The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan,
APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed
in the following sections.
5.4.2.1 IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-3 on page 57. The standard requires that every JTAG-compliant device implement either
the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This allows auto configuration test tools to determine which instruction is the default instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly, and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x3BA00477. This value indicates an ARM Cortex-M3, Version 1
processor. This allows the debuggers to automatically configure themselves to work correctly with
the Cortex-M3 during debug.
Figure 5-3. IDCODE Register Format
5.4.2.2 BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-4 on page 58. The standard requires that every JTAG-compliant device implement either
the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This allows auto configuration test tools to determine which instruction is the default instruction.
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Figure 5-4. BYPASS Register Format
5.4.2.3 Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 58. Each GPIO
pin, in a counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data
Register. Each GPIO pin has three associated digital signals that are included in the chain. These
signals are input, output, and output enable, and are arranged in that order as can be seen in the
figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because
the reset pin is always an input, only the input signal is included in the Data Register chain.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.
Figure 5-5. Boundary Scan Register Format
O TDO TDI O IN
E UT
O O IN
U E
T
O O IN
E UT
O O IN
U E
T
I
N ... ...
GPIO PB6 GPIO m RST GPIO m+1 GPIO n
For detailed information on the order of the input, output, and output enable bits for each of the
GPIO ports, please refer to the Stellaris® Family Boundary Scan Description Language (BSDL) files,
downloadable from www.luminarymicro.com.
5.4.2.4 APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.5 DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.6 ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
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6 System Control
System control determines the overall operation of the device. It provides information about the
device, controls the clocking to the core and individual peripherals, and handles reset detection and
reporting.
6.1 Functional Description
The System Control module provides the following capabilities:
■ Device identification, see “Device Identification” on page 59
■ Local control, such as reset (see “Reset Control” on page 59), power (see “Power
Control” on page 62) and clock control (see “Clock Control” on page 62)
■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 64
6.1.1 Device Identification
Seven read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers.
6.1.2 Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
6.1.2.1 CMOD0 and CMOD1 Test-Mode Control Pins
Two pins, CMOD0 and CMOD1, are defined for use by Luminary Micro for testing the devices during
manufacture. They have no end-user function and should not be used. The CMOD pins should be
connected to ground.
6.1.2.2 Reset Sources
The controller has five sources of reset:
1. External reset input pin (RST) assertion, see “RST Pin Assertion” on page 59.
2. Power-on reset (POR), see “Power-On Reset (POR)” on page 60.
3. Internal brown-out (BOR) detector, see “Brown-Out Reset (BOR)” on page 60.
4. Software-initiated reset (with the software reset registers), see “Software Reset” on page 61.
5. A watchdog timer reset condition violation, see “Watchdog Timer Reset” on page 61.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator.
6.1.2.3 RST Pin Assertion
The external reset pin (RST) resets the controller. This resets the core and all the peripherals except
the JTAG TAP controller (see “JTAG Interface” on page 48). The external reset sequence is as
follows:
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1. The external reset pin (RST) is asserted and then de-asserted.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
A few clocks cycles from RST de-assertion to the start of the reset sequence is necessary for
synchronization.
The external reset timing is shown in Figure 23-11 on page 547.
6.1.2.4 Power-On Reset (POR)
The Power-On Reset (POR) circuit monitors the power supply voltage (VDD). The POR circuit
generates a reset signal to the internal logic when the power supply ramp reaches a threshold value
(VTH). If the application only uses the POR circuit, the RST input needs to be connected to the power
supply (VDD) through a pull-up resistor (1K to 10K Ω).
The device must be operating within the specified operating parameters at the point when the on-chip
power-on reset pulse is complete. The 3.3-V power supply to the device must reach 3.0 V within
10 msec of it crossing 2.0 V to guarantee proper operation. For applications that require the use of
an external reset to hold the device in reset longer than the internal POR, the RST input may be
used with the circuit as shown in Figure 6-1 on page 60.
Figure 6-1. External Circuitry to Extend Reset
R1
C1
R2
RST
Stellaris
D1
The R1 and C1 components define the power-on delay. The R2 resistor mitigates any leakage from
the RST input. The diode (D1) discharges C1 rapidly when the power supply is turned off.
The Power-On Reset sequence is as follows:
1. The controller waits for the later of external reset (RST) or internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing
is shown in Figure 23-12 on page 548.
Note: The power-on reset also resets the JTAG controller. An external reset does not.
6.1.2.5 Brown-Out Reset (BOR)
A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops
below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may
generate a controller interrupt or a system reset.
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Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset.
The brown-out reset is equivelent to an assertion of the external RST input and the reset is held
active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt
handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to
determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 23-13 on page 548.
6.1.2.6 Software Reset
Software can reset a specific peripheral or generate a reset to the entire system .
Peripherals can be individually reset by software via three registers that control reset signals to each
peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and
subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with
the encoding of the clock gating control for peripherals and on-chip functions (see “System
Control” on page 64). Note that all reset signals for all clocks of the specified unit are asserted as
a result of a software-initiated reset.
The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is deasserted and the controller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
The software-initiated system reset timing is shown in Figure 23-14 on page 548.
6.1.2.7 Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts
down to its zero state again before the first time-out interrupt is cleared, and the reset signal has
been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset
sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the controller loads from memory the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
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The watchdog reset timing is shown in Figure 23-15 on page 548.
6.1.3 Power Control
The Stellaris® microcontroller provides an integrated LDO regulator that may be used to provide
power to the majority of the controller's internal logic. The LDO regulator provides software a
mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V
to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ
field in the LDO Power Control (LDOPCTL) register.
Note: The use of the LDO is optional. The internal logic may be supplied by the on-chip LDO or
by an external regulator. If the LDO is used, the LDO output pin is connected to the VDD25
pins on the printed circuit board. The LDO requires decoupling capacitors on the printed
circuit board. If an external regulator is used, it is strongly recommended that the external
regulator supply the controller only and not be shared with other devices on the printed
circuit board.
6.1.4 Clock Control
System control determines the control of clocks in this part.
6.1.4.1 Fundamental Clock Sources
There are four clock sources for use in the device:
■ Internal Oscillator (IOSC): The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
Applications that do not depend on accurate clock sources may use this clock source to reduce
system cost. The internal oscillator is the clock source the device uses during and following POR.
If the main oscillator is required, software must enable the main oscillator following reset and
allow the main oscillator to stabilize before changing the clock reference.
■ Main Oscillator: The main oscillator provides a frequency-accurate clock source by one of two
means: an external single-ended clock source is connected to the OSC0 input pin, or an external
crystal is connected across the OSC0 input and OSC1 output pins. The crystal value allowed
depends on whether the main oscillator is used as the clock reference source to the PLL. If so,
the crystal must be one of the supported frequencies between 3.579545 MHz through 8.192
MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC
through the specified speed of the device. The supported crystals are listed in the XTAL bit in
the RCC register (see page 75).
■ Internal 30-kHz Oscillator: The internal 30-kHz oscillator is similar to the internal oscillator,
except that it provides an operational frequency of 30 kHz ± 30%. It is intended for use during
Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal
switching and also allows the main oscillator to be powered down.
■ External Real-Time Oscillator: The external real-time oscillator provides a low-frequency,
accurate clock reference. It is intended to provide the system with a real-time clock source. The
real-time oscillator is part of the Hibernation Module (“Hibernation Module” on page 120) and may
also provide an accurate source of Deep-Sleep or Hibernate mode power savings.
The internal system clock (sysclk), is derived from any of the four sources plus two others: the output
of the internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The frequency of the
PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive).
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The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options.
6.1.4.2 Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise,
the range of supported crystals is 1 to 8.192 MHz.
The XTAL bit in the RCC register (see page 75) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
6.1.4.3 PLL Frequency Configuration
The PLL is disabled by default during power-on reset and is enabled later by software if required.
Software configures the PLL input reference clock source, specifies the output divisor to set the
system clock frequency, and enables the PLL to drive the output.
If the main oscillator provides the clock reference to the PLL, the translation provided by hardware
and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG)
register (see page 79). The internal translation provides a translation within ± 1% of the targeted
PLL VCO frequency.
The Crystal Value field (XTAL) on page 75 describes the available crystal choices and default
programming of the PLLCFG register. The crystal number is written into the XTAL field of the
Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings
are translated and the internal PLL settings are updated.
6.1.4.4 PLL Modes
The PLL has two modes of operation: Normal and Power-Down
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 75 and page 80).
6.1.4.5 PLL Operation
If the PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
23-6 on page 537). During this time, the PLL is not usable as a clock reference.
The PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■ Change in the PLL from Power-Down to Normal mode.
A counter is defined to measure the TREADY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is set
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to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). . Hardware is provided to
keep the PLL from being used as a system clock until the TREADY condition is met after one of the
two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator)
before the RCC/RCC2 register is switched to use the PLL.
6.1.5 System Control
For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep
mode, respectively.
In Run mode, the processor executes code. In Sleep mode, the clock frequency of the active
peripherals is unchanged, but the processor is not clocked and therefore no longer executes code.
In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the
Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns
the device to Run mode from one of the sleep modes; the sleep modes are entered on request from
the code. Each mode is described in more detail below.
There are four levels of operation for the device defined as:
■ Run Mode. Run mode provides normal operation of the processor and all of the peripherals that
are currently enabled by the RCGCn registers. The system clock can be any of the available
clock sources including the PLL.
■ Sleep Mode. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for
Interrupt) instruction. Any properly configured interrupt event in the system will bring the
processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3
Technical Reference Manual for more details.
In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked.
Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
■ Deep-Sleep Mode. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in
the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any
properly configured interrupt event in the system will bring the processor back into Run mode.
See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual
for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up,
if necessary, and the main oscillator is powered down. If the PLL is running at the time of the
WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active
RCC/RCC2 register to be /16 or /64, respectively. When the Deep-Sleep exit event occurs,
hardware brings the system clock back to the source and frequency it had at the onset of
Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep
duration.
■ Hibernate Mode. In this mode, the power supplies are turned off to the main part of the device
and only the Hibernation module's circuitry is active. An external wake event or RTC event is
required to bring the device back to Run mode. The Cortex-M3 processor and peripherals outside
64 November 30, 2007
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of the Hibernation module see a normal "power on" sequence and the processor starts running
code. It can determine that it has been restarted from Hibernate mode by inspecting the
Hibernation module registers.
6.2 Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source (using the
main oscillator or internal oscillator) and allows for the new PLL configuration to be validated
before switching the system clock to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
6.3 Register Map
Table 6-1 on page 65 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use by Luminary Micro, Inc. Software should not modify any reserved memory
address.
Table 6-1. System Control Register Map
See
Offset Name Type Reset Description page
0x000 DID0 RO - Device Identification 0 67
0x004 DID1 RO - Device Identification 1 83
0x008 DC0 RO 0x00FF.007F Device Capabilities 0 85
0x010 DC1 RO 0x0011.32FF Device Capabilities 1 86
0x014 DC2 RO 0x0707.1117 Device Capabilities 2 88
0x018 DC3 RO 0x0F07.BFCF Device Capabilities 3 90
0x01C DC4 RO 0x5000.007F Device Capabilities 4 92
0x030 PBORCTL R/W 0x0000.7FFD Brown-Out Reset Control 69
0x034 LDOPCTL R/W 0x0000.0000 LDO Power Control 70
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See
Offset Name Type Reset Description page
0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 115
0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 116
0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 118
0x050 RIS RO 0x0000.0000 Raw Interrupt Status 71
0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 72
0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 73
0x05C RESC R/W - Reset Cause 74
0x060 RCC R/W 0x07AE.3AD1 Run-Mode Clock Configuration 75
0x064 PLLCFG RO - XTAL to PLL Translation 79
0x070 RCC2 R/W 0x0780.2800 Run-Mode Clock Configuration 2 80
0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 94
0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 100
0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 109
0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 96
0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 103
0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 111
0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 98
0x124 DCGC1 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 106
0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 113
0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 82
6.4 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
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Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the device.
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved VER reserved CLASS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJOR MINOR
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows:
Value Description
First revision of the DID0 register format, for Stellaris®
Fury-class devices .
0x1
30:28 VER RO 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:24 reserved RO 0x0
Device Class
The CLASS field value identifies the internal design from which all mask
sets are generated for all devices in a particular product line. The CLASS
field value is changed for new product lines, for changes in fab process
(for example, a remap or shrink), or any case where the MAJOR or MINOR
fields require differentiation from prior devices. The value of the CLASS
field is encoded as follows (all other encodings are reserved):
Value Description
0x0 Stellaris® Sandstorm-class devices.
0x1 Stellaris® Fury-class devices.
23:16 CLASS RO 0x1
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Bit/Field Name Type Reset Description
Major Revision
This field specifies the major revision number of the device. The major
revision reflects changes to base layers of the design. The major revision
number is indicated in the part number as a letter (A for first revision, B
for second, and so on). This field is encoded as follows:
Value Description
0x0 Revision A (initial device)
0x1 Revision B (first base layer revision)
0x2 Revision C (second base layer revision)
and so on.
15:8 MAJOR RO -
Minor Revision
This field specifies the minor revision number of the device. The minor
revision reflects changes to the metal layers of the design. The MINOR
field value is reset when the MAJOR field is changed. This field is numeric
and is encoded as follows:
Value Description
0x0 Initial device, or a major revision update.
0x1 First metal layer change.
0x2 Second metal layer change.
and so on.
7:0 MINOR RO -
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Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BORIOR reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x0
BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the controller. If set, a
reset is signaled. Otherwise, an interrupt is signaled.
1 BORIOR R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 3: LDO Power Control (LDOPCTL), offset 0x034
The VADJ field in this register adjusts the on-chip output voltage (VOUT).
LDO Power Control (LDOPCTL)
Base 0x400F.E000
Offset 0x034
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved VADJ
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0
LDO Output Voltage
This field sets the on-chip output voltage. The programming values for
the VADJ field are provided below.
Value VOUT (V)
0x00 2.50
0x01 2.45
0x02 2.40
0x03 2.35
0x04 2.30
0x05 2.25
0x06-0x3F Reserved
0x1B 2.75
0x1C 2.70
0x1D 2.65
0x1E 2.60
0x1F 2.55
5:0 VADJ R/W 0x0
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Register 4: Raw Interrupt Status (RIS), offset 0x050
Central location for system control raw interrupts. These are set and cleared by hardware.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLRIS reserved BORRIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Raw Interrupt Status
This bit is set when the PLL TREADY Timer asserts.
6 PLLLRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
Brown-Out Reset Raw Interrupt Status
This bit is the raw interrupt status for any brown-out conditions. If set,
a brown-out condition is currently active. This is an unregistered signal
from the brown-out detection circuit. An interrupt is reported if the BORIM
bit in the IMC register is set and the BORIOR bit in the PBORCTL register
is cleared.
1 BORRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 5: Interrupt Mask Control (IMC), offset 0x054
Central location for system control interrupt masks.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLIM reserved BORIM reserved
Type RO RO RO RO RO RO RO RO RO R/W RO RO RO RO R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Interrupt Mask
This bit specifies whether a current limit detection is promoted to a
controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS
is set; otherwise, an interrupt is not generated.
6 PLLLIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
Brown-Out Reset Interrupt Mask
This bit specifies whether a brown-out condition is promoted to a
controller interrupt. If set, an interrupt is generated if BORRIS is set;
otherwise, an interrupt is not generated.
1 BORIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
Central location for system control result of RIS AND IMC to generate an interrupt to the controller.
All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS
register (see page 71).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLMIS reserved BORMIS reserved
Type RO RO RO RO RO RO RO RO RO R/W1C RO RO RO RO R/W1C RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Masked Interrupt Status
This bit is set when the PLL TREADY timer asserts. The interrupt is cleared
by writing a 1 to this bit.
6 PLLLMIS R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
BOR Masked Interrupt Status
The BORMIS is simply the BORRIS ANDed with the mask value, BORIM.
1 BORMIS R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an external reset is the cause, and then
all the other bits in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved LDO SW WDT BOR POR EXT
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0
LDO Reset
When set, indicates the LDO circuit has lost regulation and has
generated a reset event.
5 LDO R/W -
Software Reset
When set, indicates a software reset is the cause of the reset event.
4 SW R/W -
Watchdog Timer Reset
When set, indicates a watchdog reset is the cause of the reset event.
3 WDT R/W -
Brown-Out Reset
When set, indicates a brown-out reset is the cause of the reset event.
2 BOR R/W -
Power-On Reset
When set, indicates a power-on reset is the cause of the reset event.
1 POR R/W -
External Reset
When set, indicates an external reset (RST assertion) is the cause of
the reset event.
0 EXT R/W -
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Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x07AE.3AD1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved ACG SYSDIV USESYSDIV reserved USEPWMDIV PWMDIV reserved
Type RO RO RO RO R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWRDN reserved BYPASS reserved XTAL OSCSRC reserved IOSCDIS MOSCDIS
Type RO RO R/W RO R/W RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W
Reset 0 0 1 1 1 0 1 0 1 1 0 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:28 reserved RO 0x0
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.
27 ACG R/W 0
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Bit/Field Name Type Reset Description
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
Value Divisor (BYPASS=1) Frequency (BYPASS=0)
0x0 reserved reserved
0x1 /2 reserved
0x2 /3 reserved
0x3 /4 50 MHz
0x4 /5 40 MHz
0x5 /6 33.33 MHz
0x6 /7 28.57 MHz
0x7 /8 25 MHz
0x8 /9 22.22 MHz
0x9 /10 20 MHz
0xA /11 18.18 MHz
0xB /12 16.67 MHz
0xC /13 15.38 MHz
0xD /14 14.29 MHz
0xE /15 13.33 MHz
0xF /16 12.5 MHz (default)
When reading the Run-Mode Clock Configuration (RCC) register (see
page 75), the SYSDIV value is MINSYSDIV if a lower divider was
requested and the PLL is being used. This lower value is allowed to
divide a non-PLL source.
26:23 SYSDIV R/W 0xF
Enable System Clock Divider
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
22 USESYSDIV R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
21 reserved RO 0
Enable PWM Clock Divisor
Use the PWM clock divider as the source for the PWM clock.
20 USEPWMDIV R/W 0
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Bit/Field Name Type Reset Description
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. This clock
is only power 2 divide and rising edge is synchronous without phase
shift from the system clock.
Value Divisor
0x0 /2
0x1 /4
0x2 /8
0x3 /16
0x4 /32
0x5 /64
0x6 /64
0x7 /64 (default)
19:17 PWMDIV R/W 0x7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16:14 reserved RO 0
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
13 PWRDN R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12 reserved RO 1
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
Note: The ADC must be clocked from the PLL or directly from a
14-MHz to 18-MHz clock source to operate properly. While
the ADC works in a 14-18 MHz range, to maintain a 1 M
sample/second rate, the ADC must be provided a 16-MHz
clock source.
11 BYPASS R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10 reserved RO 0
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Bit/Field Name Type Reset Description
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below.
Crystal Frequency (MHz)
Using the PLL
Crystal Frequency (MHz)
Not Using the PLL
Value
0x0 1.000 reserved
0x1 1.8432 reserved
0x2 2.000 reserved
0x3 2.4576 reserved
0x4 3.579545 MHz
0x5 3.6864 MHz
0x6 4 MHz
0x7 4.096 MHz
0x8 4.9152 MHz
0x9 5 MHz
0xA 5.12 MHz
0xB 6 MHz (reset value)
0xC 6.144 MHz
0xD 7.3728 MHz
0xE 8 MHz
0xF 8.192 MHz
9:6 XTAL R/W 0xB
Oscillator Source
Picks among the four input sources for the OSC. The values are:
Value Input Source
0x0 Main oscillator (default)
0x1 Internal oscillator (default)
0x2 Internal oscillator / 4 (this is necessary if used as input to PLL)
0x3 reserved
5:4 OSCSRC R/W 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0x0
Internal Oscillator Disable
0: Internal oscillator (IOSC) is enabled.
1: Internal oscillator is disabled.
1 IOSCDIS R/W 0
Main Oscillator Disable
0: Main oscillator is enabled.
1: Main oscillator is disabled (default).
0 MOSCDIS R/W 1
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Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 75).
The PLL frequency is calculated using the PLLCFG field values, as follows:
PLLFreq = OSCFreq * F / (R + 1)
XTAL to PLL Translation (PLLCFG)
Base 0x400F.E000
Offset 0x064
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved F R
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x0
PLL F Value
This field specifies the value supplied to the PLL’s F input.
13:5 F RO -
PLL R Value
This field specifies the value supplied to the PLL’s R input.
4:0 R RO -
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Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields when the USERCC2 bit is set. This allows
RCC2 to be used to extend the capabilities, while also providing a means to be backward-compatible
to previous parts. The fields within the RCC2 register occupy the same bit positions as they do
within the RCC register as LSB-justified.
The SYSDIV2 field is wider so that additional larger divisors are possible. This allows a lower system
clock frequency for improved Deep Sleep power consumption.
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x0780.2800
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USERCC2 reserved SYSDIV2 reserved
Type R/W RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWRDN2 reserved BYPASS2 reserved OSCSRC2 reserved
Type RO RO R/W RO R/W RO RO RO RO R/W R/W R/W RO RO RO RO
Reset 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Use RCC2
When set, overrides the RCC register fields.
31 USERCC2 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30:29 reserved RO 0x0
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
This field is wider than the RCC register SYSDIV field in order to provide
additional divisor values. This permits the system clock to be run at
much lower frequencies during Deep Sleep mode. For example, where
the RCC register SYSDIV encoding of 1111 provides /16, the RCC2
register SYSDIV2 encoding of 111111 provides /64.
28:23 SYSDIV2 R/W 0x0F
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:14 reserved RO 0x0
Power-Down PLL
When set, powers down the PLL.
13 PWRDN2 R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12 reserved RO 0
Bypass PLL
When set, bypasses the PLL for the clock source.
11 BYPASS2 R/W 1
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10:7 reserved RO 0x0
System Clock Source
Value Description
0x0 Main oscillator (MOSC)
0x1 Internal oscillator (IOSC)
0x2 Internal oscillator / 4
0x3 30 kHz internal oscillator
0x7 32 kHz external oscillator
6:4 OSCSRC2 R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0
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Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved DSDIVORIDE reserved
Type RO RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DSOSCSRC reserved
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:29 reserved RO 0x0
Divider Field Override
6-bit system divider field to override when Deep-Sleep occurs with PLL
running.
28:23 DSDIVORIDE R/W 0x0F
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:7 reserved RO 0x0
Clock Source
When set, forces IOSC to be clock source during Deep Sleep mode.
Value Name Description
0x0 NOORIDE No override to the oscillator clock source is done
0x1 IOSC Use internal 12 MHz oscillator as source
0x3 30kHz Use 30 kHz internal oscillator
0x7 32kHz Use 32 kHz external oscillator
6:4 DSOSCSRC R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0x0
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Register 12: Device Identification 1 (DID1), offset 0x004
This register identifies the device family, part number, temperature range, pin count, and package
type.
Device Identification 1 (DID1)
Base 0x400F.E000
Offset 0x004
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VER FAM PARTNO
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOUNT reserved TEMP PKG ROHS QUAL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 0 0 0 0 0 0 0 1 0 1 1 - -
Bit/Field Name Type Reset Description
DID1 Version
This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Value Description
First revision of the DID1 register format, indicating a Stellaris
Fury-class device.
0x1
31:28 VER RO 0x1
Family
This field provides the family identification of the device within the
Luminary Micro product portfolio. The value is encoded as follows (all
other encodings are reserved):
Value Description
Stellaris family of microcontollers, that is, all devices with
external part numbers starting with LM3S.
0x0
27:24 FAM RO 0x0
Part Number
This field provides the part number of the device within the family. The
value is encoded as follows (all other encodings are reserved):
Value Description
0x78 LM3S6952
23:16 PARTNO RO 0x78
Package Pin Count
This field specifies the number of pins on the device package. The value
is encoded as follows (all other encodings are reserved):
Value Description
0x2 100-pin package
15:13 PINCOUNT RO 0x2
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12:8 reserved RO 0
Temperature Range
This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x1 Industrial temperature range (-40°C to 85°C)
7:5 TEMP RO 0x1
Package Type
This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):
Value Description
0x1 LQFP package
4:3 PKG RO 0x1
RoHS-Compliance
This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.
2 ROHS RO 1
Qualification Status
This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x0 Engineering Sample (unqualified)
0x1 Pilot Production (unqualified)
0x2 Fully Qualified
1:0 QUAL RO -
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Register 13: Device Capabilities 0 (DC0), offset 0x008
This register is predefined by the part and can be used to verify features.
Device Capabilities 0 (DC0)
Base 0x400F.E000
Offset 0x008
Type RO, reset 0x00FF.007F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRAMSZ
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASHSZ
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
SRAM Size
Indicates the size of the on-chip SRAM memory.
Value Description
0x00FF 64 KB of SRAM
31:16 SRAMSZ RO 0x00FF
Flash Size
Indicates the size of the on-chip flash memory.
Value Description
0x007F 256 KB of Flash
15:0 FLASHSZ RO 0x007F
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Register 14: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: CANs, PWM,
ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the
maximum clock frequency and maximum ADC sample rate. The format of this register is consistent
with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control
register.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0011.32FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved PWM reserved ADC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MINSYSDIV MAXADCSPD MPU HIB TEMPSNS PLL WDT SWO SWD JTAG
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:21 reserved RO 0
PWM Module Present
When set, indicates that the PWM module is present.
20 PWM RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:17 reserved RO 0
ADC Module Present
When set, indicates that the ADC module is present.
16 ADC RO 1
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4.
15:12 MINSYSDIV RO 0x3
Max ADC Speed
Indicates the maximum rate at which the ADC samples data.
Value Description
0x2 500K samples/second
11:8 MAXADCSPD RO 0x2
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Bit/Field Name Type Reset Description
MPU Present
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the ARM Cortex-M3 Technical Reference Manual
for details on the MPU.
7 MPU RO 1
Hibernation Module Present
When set, indicates that the Hibernation module is present.
6 HIB RO 1
Temp Sensor Present
When set, indicates that the on-chip temperature sensor is present.
5 TEMPSNS RO 1
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
4 PLL RO 1
Watchdog Timer Present
When set, indicates that a watchdog timer is present.
3 WDT RO 1
SWO Trace Port Present
When set, indicates that the Serial Wire Output (SWO) trace port is
present.
2 SWO RO 1
SWD Present
When set, indicates that the Serial Wire Debugger (SWD) is present.
1 SWD RO 1
JTAG Present
When set, indicates that the JTAG debugger interface is present.
0 JTAG RO 1
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Register 15: Device Capabilities 2 (DC2), offset 0x014
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register
is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software
reset control register.
Device Capabilities 2 (DC2)
Base 0x400F.E000
Offset 0x014
Type RO, reset 0x0707.1117
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C0 reserved QEI0 reserved SSI0 reserved UART2 UART1 UART0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 1 0 0 0 1 0 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Present
When set, indicates that analog comparator 2 is present.
26 COMP2 RO 1
Analog Comparator 1 Present
When set, indicates that analog comparator 1 is present.
25 COMP1 RO 1
Analog Comparator 0 Present
When set, indicates that analog comparator 0 is present.
24 COMP0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
Timer 2 Present
When set, indicates that General-Purpose Timer module 2 is present.
18 TIMER2 RO 1
Timer 1 Present
When set, indicates that General-Purpose Timer module 1 is present.
17 TIMER1 RO 1
Timer 0 Present
When set, indicates that General-Purpose Timer module 0 is present.
16 TIMER0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
I2C Module 0 Present
When set, indicates that I2C module 0 is present.
12 I2C0 RO 1
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:9 reserved RO 0
QEI0 Present
When set, indicates that QEI module 0 is present.
8 QEI0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5 reserved RO 0
SSI0 Present
When set, indicates that SSI module 0 is present.
4 SSI0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
UART2 Present
When set, indicates that UART module 2 is present.
2 UART2 RO 1
UART1 Present
When set, indicates that UART module 1 is present.
1 UART1 RO 1
UART0 Present
When set, indicates that UART module 0 is present.
0 UART0 RO 1
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Register 16: Device Capabilities 3 (DC3), offset 0x018
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os.
Device Capabilities 3 (DC3)
Base 0x400F.E000
Offset 0x018
Type RO, reset 0x0F07.BFCF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved CCP3 CCP2 CCP1 CCP0 reserved ADC2 ADC1 ADC0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWMFAULT reserved C2PLUS C2MINUS C1O C1PLUS C1MINUS C0O C0PLUS C0MINUS reserved PWM3 PWM2 PWM1 PWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:28 reserved RO 0
CCP3 Pin Present
When set, indicates that Capture/Compare/PWM pin 3 is present.
27 CCP3 RO 1
CCP2 Pin Present
When set, indicates that Capture/Compare/PWM pin 2 is present.
26 CCP2 RO 1
CCP1 Pin Present
When set, indicates that Capture/Compare/PWM pin 1 is present.
25 CCP1 RO 1
CCP0 Pin Present
When set, indicates that Capture/Compare/PWM pin 0 is present.
24 CCP0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
ADC2 Pin Present
When set, indicates that ADC pin 2 is present.
18 ADC2 RO 1
ADC1 Pin Present
When set, indicates that ADC pin 1 is present.
17 ADC1 RO 1
ADC0 Pin Present
When set, indicates that ADC pin 0 is present.
16 ADC0 RO 1
PWM Fault Pin Present
When set, indicates that the PWM Fault pin is present.
15 PWMFAULT RO 1
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14 reserved RO 0
C2+ Pin Present
When set, indicates that the analog comparator 2 (+) input pin is present.
13 C2PLUS RO 1
C2- Pin Present
When set, indicates that the analog comparator 2 (-) input pin is present.
12 C2MINUS RO 1
C1o Pin Present
When set, indicates that the analog comparator 1 output pin is present.
11 C1O RO 1
C1+ Pin Present
When set, indicates that the analog comparator 1 (+) input pin is present.
10 C1PLUS RO 1
C1- Pin Present
When set, indicates that the analog comparator 1 (-) input pin is present.
9 C1MINUS RO 1
C0o Pin Present
When set, indicates that the analog comparator 0 output pin is present.
8 C0O RO 1
C0+ Pin Present
When set, indicates that the analog comparator 0 (+) input pin is present.
7 C0PLUS RO 1
C0- Pin Present
When set, indicates that the analog comparator 0 (-) input pin is present.
6 C0MINUS RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
PWM3 Pin Present
When set, indicates that the PWM pin 3 is present.
3 PWM3 RO 1
PWM2 Pin Present
When set, indicates that the PWM pin 2 is present.
2 PWM2 RO 1
PWM1 Pin Present
When set, indicates that the PWM pin 1 is present.
1 PWM1 RO 1
PWM0 Pin Present
When set, indicates that the PWM pin 0 is present.
0 PWM0 RO 1
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Register 17: Device Capabilities 4 (DC4), offset 0x01C
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Ethernet MAC
and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2,
and DCGC2 clock control registers and the SRCR2 software reset control register.
Device Capabilities 4 (DC4)
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x5000.007F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
Ethernet PHY0 Present
When set, indicates that Ethernet PHY module 0 is present.
30 EPHY0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
Ethernet MAC0 Present
When set, indicates that Ethernet MAC module 0 is present.
28 EMAC0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
GPIO Port G Present
When set, indicates that GPIO Port G is present.
6 GPIOG RO 1
GPIO Port F Present
When set, indicates that GPIO Port F is present.
5 GPIOF RO 1
GPIO Port E Present
When set, indicates that GPIO Port E is present.
4 GPIOE RO 1
GPIO Port D Present
When set, indicates that GPIO Port D is present.
3 GPIOD RO 1
GPIO Port C Present
When set, indicates that GPIO Port C is present.
2 GPIOC RO 1
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Bit/Field Name Type Reset Description
GPIO Port B Present
When set, indicates that GPIO Port B is present.
1 GPIOB RO 1
GPIO Port A Present
When set, indicates that GPIO Port A is present.
0 GPIOA RO 1
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Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 0 (RCGC0)
Base 0x400F.E000
Offset 0x100
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved PWM reserved ADC
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MAXADCSPD reserved HIB reserved WDT reserved
Type RO RO RO RO R/W R/W R/W R/W RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:21 reserved RO 0
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:17 reserved RO 0
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:12 reserved RO 0
94 November 30, 2007
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System Control
Bit/Field Name Type Reset Description
ADC Sample Speed
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:
Value Description
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second
11:8 MAXADCSPD R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.
6 HIB R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
November 30, 2007 95
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LM3S6952 Microcontroller
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved PWM reserved ADC
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MAXADCSPD reserved HIB reserved WDT reserved
Type RO RO RO RO R/W R/W R/W R/W RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:21 reserved RO 0
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:17 reserved RO 0
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:12 reserved RO 0
96 November 30, 2007
Preliminary
System Control
Bit/Field Name Type Reset Description
ADC Sample Speed
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:
Value Description
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second
11:8 MAXADCSPD R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.
6 HIB R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
November 30, 2007 97
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LM3S6952 Microcontroller
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved PWM reserved ADC
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MAXADCSPD reserved HIB reserved WDT reserved
Type RO RO RO RO R/W R/W R/W R/W RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:21 reserved RO 0
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:17 reserved RO 0
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:12 reserved RO 0
98 November 30, 2007
Preliminary
System Control
Bit/Field Name Type Reset Description
ADC Sample Speed
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:
Value Description
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second
11:8 MAXADCSPD R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.
6 HIB R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
November 30, 2007 99
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LM3S6952 Microcontroller
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 1 (RCGC1)
Base 0x400F.E000
Offset 0x104
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C0 reserved QEI0 reserved SSI0 reserved UART2 UART1 UART0
Type RO RO RO R/W RO RO RO R/W RO RO RO R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
26 COMP2 R/W 0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
25 COMP1 R/W 0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
100 November 30, 2007
Preliminary
System Control
Bit/Field Name Type Reset Description
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18 TIMER2 R/W 0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17 TIMER1 R/W 0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
12 I2C0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:9 reserved RO 0
QEI0 Clock Gating Control
This bit controls the clock gating for QEI module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
8 QEI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5 reserved RO 0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
2 UART2 R/W 0
November 30, 2007 101
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LM3S6952 Microcontroller
Bit/Field Name Type Reset Description
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
1 UART1 R/W 0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0 UART0 R/W 0
102 November 30, 2007
Preliminary
System Control
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 1 (SCGC1)
Base 0x400F.E000
Offset 0x114
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C0 reserved QEI0 reserved SSI0 reserved UART2 UART1 UART0
Type RO RO RO R/W RO RO RO R/W RO RO RO R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
26 COMP2 R/W 0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
25 COMP1 R/W 0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
November 30, 2007 103
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LM3S6952 Microcontroller
Bit/Field Name Type Reset Description
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18 TIMER2 R/W 0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17 TIMER1 R/W 0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
12 I2C0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:9 reserved RO 0
QEI0 Clock Gating Control
This bit controls the clock gating for QEI module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
8 QEI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5 reserved RO 0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
2 UART2 R/W 0
104 November 30, 2007
Preliminary
System Control
Bit/Field Name Type Reset Description
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
1 UART1 R/W 0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0 UART0 R/W 0
November 30, 2007 105
Preliminary
LM3S6952 Microcontroller
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C0 reserved QEI0 reserved SSI0 reserved UART2 UART1 UART0
Type RO RO RO R/W RO RO RO R/W RO RO RO R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
26 COMP2 R/W 0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
25 COMP1 R/W 0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
106 November 30, 2007
Preliminary
System Control
Bit/Field Name Type Reset Description
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18 TIMER2 R/W 0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17 TIMER1 R/W 0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
12 I2C0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:9 reserved RO 0
QEI0 Clock Gating Control
This bit controls the clock gating for QEI module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
8 QEI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5 reserved RO 0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
2 UART2 R/W 0
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Bit/Field Name Type Reset Description
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
1 UART1 R/W 0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0 UART0 R/W 0
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Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 2 (RCGC2)
Base 0x400F.E000
Offset 0x108
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
6 GPIOG R/W 0
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Bit/Field Name Type Reset Description
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 GPIOF R/W 0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 GPIOE R/W 0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3 GPIOD R/W 0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 GPIOC R/W 0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 GPIOB R/W 0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0 GPIOA R/W 0
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System Control
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset
0x118
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 2 (SCGC2)
Base 0x400F.E000
Offset 0x118
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
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Bit/Field Name Type Reset Description
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
6 GPIOG R/W 0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 GPIOF R/W 0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 GPIOE R/W 0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3 GPIOD R/W 0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 GPIOC R/W 0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 GPIOB R/W 0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0 GPIOA R/W 0
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System Control
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
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Bit/Field Name Type Reset Description
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
6 GPIOG R/W 0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 GPIOF R/W 0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 GPIOE R/W 0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3 GPIOD R/W 0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 GPIOC R/W 0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 GPIOB R/W 0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0 GPIOA R/W 0
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Register 27: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved PWM reserved ADC
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved HIB reserved WDT reserved
Type RO RO RO RO RO RO RO RO RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:21 reserved RO 0
PWM Reset Control
Reset control for PWM module.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:17 reserved RO 0
ADC0 Reset Control
Reset control for SAR ADC module 0.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:7 reserved RO 0
HIB Reset Control
Reset control for the Hibernation module.
6 HIB R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Reset Control
Reset control for Watchdog unit.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 28: Software Reset Control 1 (SRCR1), offset 0x044
Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C0 reserved QEI0 reserved SSI0 reserved UART2 UART1 UART0
Type RO RO RO R/W RO RO RO R/W RO RO RO R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comp 2 Reset Control
Reset control for analog comparator 2.
26 COMP2 R/W 0
Analog Comp 1 Reset Control
Reset control for analog comparator 1.
25 COMP1 R/W 0
Analog Comp 0 Reset Control
Reset control for analog comparator 0.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
Timer 2 Reset Control
Reset control for General-Purpose Timer module 2.
18 TIMER2 R/W 0
Timer 1 Reset Control
Reset control for General-Purpose Timer module 1.
17 TIMER1 R/W 0
Timer 0 Reset Control
Reset control for General-Purpose Timer module 0.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
I2C0 Reset Control
Reset control for I2C unit 0.
12 I2C0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:9 reserved RO 0
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Bit/Field Name Type Reset Description
QEI0 Reset Control
Reset control for QEI unit 0.
8 QEI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5 reserved RO 0
SSI0 Reset Control
Reset control for SSI unit 0.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
UART2 Reset Control
Reset control for UART unit 2.
2 UART2 R/W 0
UART1 Reset Control
Reset control for UART unit 1.
1 UART1 R/W 0
UART0 Reset Control
Reset control for UART unit 0.
0 UART0 R/W 0
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Register 29: Software Reset Control 2 (SRCR2), offset 0x048
Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register.
Software Reset Control 2 (SRCR2)
Base 0x400F.E000
Offset 0x048
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Reset Control
Reset control for Ethernet PHY unit 0.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Reset Control
Reset control for Ethernet MAC unit 0.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
Port G Reset Control
Reset control for GPIO Port G.
6 GPIOG R/W 0
Port F Reset Control
Reset control for GPIO Port F.
5 GPIOF R/W 0
Port E Reset Control
Reset control for GPIO Port E.
4 GPIOE R/W 0
Port D Reset Control
Reset control for GPIO Port D.
3 GPIOD R/W 0
Port C Reset Control
Reset control for GPIO Port C.
2 GPIOC R/W 0
Port B Reset Control
Reset control for GPIO Port B.
1 GPIOB R/W 0
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Bit/Field Name Type Reset Description
Port A Reset Control
Reset control for GPIO Port A.
0 GPIOA R/W 0
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7 Hibernation Module
The Hibernation Module manages removal and restoration of power to the rest of the microcontroller
to provide a means for reducing power consumption. When the processor and peripherals are idle,
power can be completely removed with only the Hibernation Module remaining powered. Power
can be restored based on an external signal, or at a certain time using the built-in real-time clock
(RTC). The Hibernation module can be independently supplied from a battery or an auxiliary power
supply.
The Hibernation module has the following features:
■ Power-switching logic to discrete external regulator
■ Dedicated pin for waking from an external signal
■ Low-battery detection, signaling, and interrupt generation
■ 32-bit real-time counter (RTC)
■ Two 32-bit RTC match registers for timed wake-up and interrupt generation
■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal
■ RTC predivider trim for making fine adjustments to the clock rate
■ 64 32-bit words of non-volatile memory
■ Programmable interrupts for RTC match, external wake, and low battery events
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Hibernation Module
7.1 Block Diagram
Figure 7-1. Hibernation Module Block Diagram
HIBIM
HIBRIS
HIBMIS
HIBIC
HIBRTCT
Pre-Divider
/128
XOSC0
XOSC1
HIBCTL.CLK32EN
HIBCTL.CLKSEL
HIBRTCC
HIBRTCLD
HIBRTCM0
HIBRTCM1
RTC
Interrupts
Power
Sequence
Logic
MATCH0/1
WAKE
Interrupts
to CPU
Low Battery
Detect
LOWBAT
VDD
VBAT
HIB
HIBCTL.LOWBATEN HIBCTL.PWRCUT
HIBCTL.EXTWEN
HIBCTL.RTCWEN
HIBCTL.VABORT
Non-Volatile
Memory
HIBDATA
7.2 Functional Description
The Hibernation module controls the power to the processor with an enable signal (HIB) that signals
an external voltage regulator to turn off. The Hibernation module power is determined dynamically.
The supply voltage of the Hibernation module is the larger of the main voltage source (VDD) or the
battery/auxilliary voltage source (VBAT). A voting circuit indicates the larger and an internal power
switch selects the appropriate voltage source. The Hibernation module also has a separate clock
source to maintain a real-time clock (RTC). Once in hibernation, the module signals an external
voltage regulator to turn back on the power when an external pin (WAKE) is asserted, or when the
internal RTC reaches a certain value. The Hibernation module can also detect when the battery
voltage is low, and optionally prevent hibernation when this occurs.
Power-up from a power cut to code execution is defined as the regulator turn-on time (specifed at
tHIB_TO_VDD maximum) plus the normal chip POR (see “Hibernation Module” on page 543).
7.2.1 Register Access Timing
Because the Hibernation module has an independent clocking domain, certain registers must be
written only with a timing gap between accesses. The delay time is tHIB_REG_WRITE, therefore software
must guarantee that a delay of tHIB_REG_WRITE is inserted between back-to-back writes to certain
Hibernation registers, or between a write followed by a read to those same registers. There is no
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restriction on timing for back-to-back reads from the Hibernation module. Refer to “Register
Descriptions” on page 126 for details about which registers are subject to this timing restriction.
7.2.2 Clock Source
The Hibernation module must be clocked by an external source, even if the RTC feature will not be
used. An external oscillator or crystal can be used for this purpose. To use a crystal, a 4.194304-MHz
crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to
produce the 32.768-kHz clock reference. To use a more precise clock source, a 32.768-kHz oscillator
can be connected to the XOSC0 pin.
The clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The type of clock
source is selected by setting the CLKSEL bit to 0 for a 4.194304-MHz clock source, and to 1 for a
32.768-kHz clock source. If the bit is set to 0, the input clock is divided by 128, resulting in a
32.768-kHz clock source. If a crystal is used for the clock source, the software must leave a delay
of tXOSC_SETTLE after setting the CLK32EN bit and before any other accesses to the Hibernation
module registers. The delay allows the crystal to power up and stabilize. If an oscillator is used for
the clock source, no delay is needed.
7.2.3 Battery Management
The Hibernation module can be independently powered by a battery or an auxiliary power source.
The module can monitor the voltage level of the battery and detect when the voltage becomes too
low. When this happens, an interrupt can be generated. The module can also be configured so that
it will not go into Hibernate mode if the battery voltage is too low.
Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher
voltage. Therefore, it is important to design the circuit to ensure that VDD is higher that VBAT under
nominal conditions or else the Hibernation module draws power from the battery even when VDD
is available.
The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN
bit of the HIBCTL register. In this configuration, the LOWBAT bit of the HIBRIS register will be set
when the battery level is low. If the VABORT bit is also set, then the module is prevented from entering
Hibernation mode when a low battery is detected. The module can also be configured to generate
an interrupt for the low-battery condition (see “Interrupts and Status” on page 123).
7.2.4 Real-Time Clock
The Hibernation module includes a 32-bit counter that increments once per second with a proper
clock source and configuration (see “Clock Source” on page 122). The 32.768-kHz clock signal is
fed into a predivider register which counts down the 32.768-kHz clock ticks to achieve a once per
second clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock
source by using the predivider trim register. This register has a nominal value of 0x7FFF, and is
used for one second out of every 64 seconds to divide the input clock. This allows the software to
make fine corrections to the clock rate by adjusting the predivider trim register up or down from
0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC
rate, and down from 0x7FFF in order to speed up the RTC rate.
The Hibernation module includes two 32-bit match registers that are compared to the value of the
RTC counter. The match registers can be used to wake the processor from hibernation mode, or
to generate an interrupt to the processor if it is not in hibernation.
The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be
set at any time by writing to the HIBRTCLD register. The predivider trim can be adjusted by reading
and writing the HIBRTCT register. The predivider uses this register once every 64 seconds to adjust
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the clock rate. The two match registers can be set by writing to the HIBRTCM0 and HIBRTCM1
registers. The RTC can be configured to generate interrupts by using the interrupt registers (see
“Interrupts and Status” on page 123).
7.2.5 Non-Volatile Memory
The Hibernation module contains 64 32-bit words of memory which are retained during hibernation.
This memory is powered from the battery or auxiliary power supply during hibernation. The processor
software can save state information in this memory prior to hibernation, and can then recover the
state upon waking. The non-volatile memory can be accessed through the HIBDATA registers.
7.2.6 Power Control
The Hibernation module controls power to the processor through the use of the HIB pin, which is
intended to be connected to the enable signal of the external regulator(s) providing 3.3 V and/or
2.5 V to the microcontroller. When the HIB signal is asserted by the Hibernation module, the external
regulator is turned off and no longer powers the microcontroller. The Hibernation module remains
powered from the VBAT supply, which could be a battery or an auxiliary power source. Hibernation
mode is initiated by the microcontroller setting the HIBREQ bit of the HIBCTL register. Prior to doing
this, a wake-up condition must be configured, either from the external WAKE pin, or by using an RTC
match.
The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN
bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Either
one or both of these bits can be set prior to going into hibernation. The WAKE pin includes a weak
internal pull-up. Note that both the HIB and WAKE pins use the Hibernation module's internal power
supply as the logic 1 reference.
When the Hibernation module wakes, the microcontroller will see a normal power-on reset. It can
detect that the power-on was due to a wake from hibernation by examining the raw interrupt status
register (see “Interrupts and Status” on page 123) and by looking for state data in the non-volatile
memory (see “Non-Volatile Memory” on page 123).
When the HIB signal deasserts, enabling the external regulator, the external regulator must reach
the operating voltage within tHIB_TO_VDD.
7.2.7 Interrupts and Status
The Hibernation module can generate interrupts when the following conditions occur:
■ Assertion of WAKE pin
■ RTC match
■ Low battery detected
All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate
module can only generate a single interrupt request to the controller at any given time. The software
interrupt handler can service multiple interrupt events by reading the HIBMIS register. Software can
also read the status of the Hibernation module at any time by reading the HIBRIS register which
shows all of the pending events. This register can be used at power-on to see if a wake condition
is pending, which indicates to the software that a hibernation wake occurred.
The events that can trigger an interrupt are configured by setting the appropriate bits in the HIBIM
register. Pending interrupts can be cleared by writing the corresponding bit in the HIBIC register.
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7.3 Initialization and Configuration
The Hibernation module can be configured in several different combinations. The following sections
show the recommended programming sequence for various scenarios. The examples below assume
that a 32.768-kHz oscillator is used, and thus always show bit 2 (CLKSEL) of the HIBCTL register
set to 1. If a 4.194304-MHz crystal is used instead, then the CLKSEL bit remains cleared. Because
the Hibernation module runs at 32 kHz and is asynchronous to the rest of the system, software must
allow a delay of tHIB_REG_WRITE after writes to certain registers (see “Register Access
Timing” on page 121). The registers that require a delay are denoted with a footnote in
Table 7-1 on page 125.
7.3.1 Initialization
The clock source must be enabled first, even if the RTC will not be used. If a 4.194304-MHz crystal
is used, perform the following steps:
1. Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128
input path.
2. Wait for a time of tXOSC_SETTLE for the crystal to power up and stabilize before performing any
other operations with the Hibernation module.
If a 32.678-kHz oscillator is used, then perform the following steps:
1. Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input.
2. No delay is necessary.
The above is only necessary when the entire system is initialized for the first time. If the processor
is powered due to a wake from hibernation, then the Hibernation module has already been powered
up and the above steps are not necessary. The software can detect that the Hibernation module
and clock are already powered by examining the CLK32EN bit of the HIBCTL register.
7.3.2 RTC Match Functionality (No Hibernation)
The following steps are needed to use the RTC match functionality of the Hibernation module:
1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the
HIBIM register at offset 0x014.
4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting.
7.3.3 RTC Match/Wake-Up from Hibernation
The following steps are needed to use the RTC match and wake-up functionality of the Hibernation
module:
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
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4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the
HIBCTL register at offset 0x010.
7.3.4 External Wake-Up from Hibernation
The following steps are needed to use the Hibernation module with the external WAKE pin as the
wake-up source for the microcontroller:
1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the
HIBCTL register at offset 0x010.
7.3.5 RTC/External Wake-Up from Hibernation
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F
to the HIBCTL register at offset 0x010.
7.4 Register Map
Table 7-1 on page 125 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000.
Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 121.
Table 7-1. Hibernation Module Register Map
See
Offset Name Type Reset Description page
0x000 HIBRTCC RO 0x0000.0000 Hibernation RTC Counter 127
0x004 HIBRTCM0 R/W 0xFFFF.FFFF Hibernation RTC Match 0 128
0x008 HIBRTCM1 R/W 0xFFFF.FFFF Hibernation RTC Match 1 129
0x00C HIBRTCLD R/W 0xFFFF.FFFF Hibernation RTC Load 130
0x010 HIBCTL R/W 0x0000.0000 Hibernation Control 131
0x014 HIBIM R/W 0x0000.0000 Hibernation Interrupt Mask 133
0x018 HIBRIS RO 0x0000.0000 Hibernation Raw Interrupt Status 134
0x01C HIBMIS RO 0x0000.0000 Hibernation Masked Interrupt Status 135
0x020 HIBIC R/W1C 0x0000.0000 Hibernation Interrupt Clear 136
0x024 HIBRTCT R/W 0x0000.7FFF Hibernation RTC Trim 137
0x030- HIBDATA R/W 0x0000.0000 Hibernation Data 138
0x12C
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7.5 Register Descriptions
The remainder of this section lists and describes the Hibernation module registers, in numerical
order by address offset.
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Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000
This register is the current 32-bit value of the RTC counter.
Hibernation RTC Counter (HIBRTCC)
Base 0x400F.C000
Offset 0x000
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
RTC Counter
A read returns the 32-bit counter value. This register is read-only. To
change the value, use the HIBRTCLD register.
31:0 RTCC RO 0x0000.0000
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Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004
This register is the 32-bit match 0 register for the RTC counter.
Hibernation RTC Match 0 (HIBRTCM0)
Base 0x400F.C000
Offset 0x004
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCM0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCM0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
RTC Match 0
A write loads the value into the RTC match register.
A read returns the current match value.
31:0 RTCM0 R/W 0xFFFF.FFFF
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Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008
This register is the 32-bit match 1 register for the RTC counter.
Hibernation RTC Match 1 (HIBRTCM1)
Base 0x400F.C000
Offset 0x008
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCM1
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCM1
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
RTC Match 1
A write loads the value into the RTC match register.
A read returns the current match value.
31:0 RTCM1 R/W 0xFFFF.FFFF
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Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C
This register is the 32-bit value loaded into the RTC counter.
Hibernation RTC Load (HIBRTCLD)
Base 0x400F.C000
Offset 0x00C
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCLD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCLD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
RTC Load
A write loads the current value into the RTC counter (RTCC).
A read returns the 32-bit load value.
31:0 RTCLD R/W 0xFFFF.FFFF
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Register 5: Hibernation Control (HIBCTL), offset 0x010
This register is the control register for the Hibernation module.
Hibernation Control (HIBCTL)
Base 0x400F.C000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBREQ RTCEN
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Power Cut Abort Enable
0: Power cut occurs during a low-battery alert
1: Power cut is aborted
7 VABORT R/W 0
32-kHz Oscillator Enable
0: Disabled
1: Enabled
This bit must be enabled to use the Hibernation module. If a crystal is
used, then software should wait 20 ms after setting this bit to allow the
crystal to power up and stabilize.
6 CLK32EN R/W 0
Low Battery Monitoring Enable
0: Disabled
1: Enabled
When set, low battery voltage detection is enabled.
5 LOWBATEN R/W 0
External WAKE Pin Enable
0: Disabled
1: Enabled
When set, an external event on the WAKE pin will re-power the device.
4 PINWEN R/W 0
RTC Wake-up Enable
0: Disabled
1: Enabled
When set, an RTC match event (RTCM0 or RTCM1) will re-power the
device based on the RTC counter value matching the corresponding
match register 0 or 1.
3 RTCWEN R/W 0
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Bit/Field Name Type Reset Description
Hibernation Module Clock Select
0: Use Divide by 128 output. Use this value for a 4-MHz crystal.
1: Use raw output. Use this value for a 32-kHz oscillator.
2 CLKSEL R/W 0
Hibernation Request
0: Disabled
1: Hibernation initiated
After a wake-up event, this bit is cleared by hardware.
1 HIBREQ R/W 0
RTC Timer Enable
0: Disabled
1: Enabled
0 RTCEN R/W 0
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Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014
This register is the interrupt mask register for the Hibernation module interrupt sources.
Hibernation Interrupt Mask (HIBIM)
Base 0x400F.C000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
External Wake-Up Interrupt Mask
0: Masked
1: Unmasked
3 EXTW R/W 0
Low Battery Voltage Interrupt Mask
0: Masked
1: Unmasked
2 LOWBAT R/W 0
RTC Alert1 Interrupt Mask
0: Masked
1: Unmasked
1 RTCALT1 R/W 0
RTC Alert0 Interrupt Mask
0: Masked
1: Unmasked
0 RTCALT0 R/W 0
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Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018
This register is the raw interrupt status for the Hibernation module interrupt sources.
Hibernation Raw Interrupt Status (HIBRIS)
Base 0x400F.C000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
3 EXTW RO 0 External Wake-Up Raw Interrupt Status
2 LOWBAT RO 0 Low Battery Voltage Raw Interrupt Status
1 RTCALT1 RO 0 RTC Alert1 Raw Interrupt Status
0 RTCALT0 RO 0 RTC Alert0 Raw Interrupt Status
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Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C
This register is the masked interrupt status for the Hibernation module interrupt sources.
Hibernation Masked Interrupt Status (HIBMIS)
Base 0x400F.C000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
3 EXTW RO 0 External Wake-Up Masked Interrupt Status
2 LOWBAT RO 0 Low Battery Voltage Masked Interrupt Status
1 RTCALT1 RO 0 RTC Alert1 Masked Interrupt Status
0 RTCALT0 RO 0 RTC Alert0 Masked Interrupt Status
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Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020
This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources.
Hibernation Interrupt Clear (HIBIC)
Base 0x400F.C000
Offset 0x020
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
External Wake-Up Masked Interrupt Clear
Reads return an indeterminate value.
3 EXTW R/W1C 0
Low Battery Voltage Masked Interrupt Clear
Reads return an indeterminate value.
2 LOWBAT R/W1C 0
RTC Alert1 Masked Interrupt Clear
Reads return an indeterminate value.
1 RTCALT1 R/W1C 0
RTC Alert0 Masked Interrupt Clear
Reads return an indeterminate value.
0 RTCALT0 R/W1C 0
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Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024
This register contains the value that is used to trim the RTC clock predivider. It represents the
computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock
cycles.
Hibernation RTC Trim (HIBRTCT)
Base 0x400F.C000
Offset 0x024
Type R/W, reset 0x0000.7FFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
RTC Trim Value
This value is loaded into the RTC predivider every 64 seconds. It is used
to adjust the RTC rate to account for drift and inaccuracy in the clock
source. The compensation is made by software by adjusting the default
value of 0x7FFF up or down.
15:0 TRIM R/W 0x7FFF
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Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C
This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the
system processor in order to store any non-volatile state data and will not lose power during a power
cut operation.
Hibernation Data (HIBDATA)
Base 0x400F.C000
Offset 0x030-0x12C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
31:0 RTD R/W 0x0000.0000 Hibernation Module NV Registers[63:0]
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8 Internal Memory
The LM3S6952 microcontroller comes with 64 KB of bit-banded SRAM and 256 KB of flash memory.
The flash controller provides a user-friendly interface, making flash programming a simple task.
Flash protection can be applied to the flash memory on a 2-KB block basis.
8.1 Block Diagram
Figure 8-1. Flash Block Diagram
Flash Control
FMA
FCMISC
FCIM
FCRIS
FMC
FMD
Flash Timing
USECRL
Flash Protection
FMPREn
FMPPEn
Flash Array
SRAM Array
Bridge
Cortex-M3
ICode
DCode
System Bus
APB
User Registers
USER_REG0
USER_REG1
USER_DBG
8.2 Functional Description
This section describes the functionality of both the flash and SRAM memories.
8.2.1 SRAM Memory
The internal SRAM of the Stellaris® devices is located at address 0x2000.0000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has
introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor,
certain regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
The bit-band alias is calculated by using the formula:
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bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3
Technical Reference Manual.
8.2.2 Flash Memory
The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be
programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB
blocks that can be individually protected. The protection allows blocks to be marked as read-only
or execute-only, providing different levels of code protection. Read-only blocks cannot be erased
or programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
See also “Serial Flash Loader” on page 551 for a preprogrammed flash-resident utility used to
download code to the flash memory of a device without the use of a debug interface.
8.2.2.1 Flash Memory Timing
The timing for the flash is automatically handled by the flash controller. However, in order to do so,
it must know the clock rate of the system in order to time its internal signals properly. The number
of clock cycles per microsecond must be provided to the flash controller for it to accomplish this
timing. It is software's responsibility to keep the flash controller updated with this information via the
USec Reload (USECRL) register.
On reset, the USECRL register is loaded with a value that configures the flash timing so that it works
with the maximum clock rate of the part. If software changes the system operating frequency, the
new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash
modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value
of 0x13 (20-1) must be written to the USECRL register.
8.2.2.2 Flash Memory Protection
The user is provided two forms of flash protection per 2-KB flash blocks in four pairs of 32-bit wide
registers. The protection policy for each form is controlled by individual bits (per policy per block)
in the FMPPEn and FMPREn registers.
■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed
(written) or erased. If cleared, the block may not be changed.
■ Flash Memory Protection Read Enable (FMPREn): If set, the block may be executed or read
by software or debuggers. If cleared, the block may only be executed. The contents of the memory
block are prohibited from being accessed as data and traversing the DCode bus.
The policies may be combined as shown in Table 8-1 on page 141.
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Table 8-1. Flash Protection Policy Combinations
FMPPEn FMPREn Protection
Execute-only protection. The block may only be executed and may not be written or erased. This mode
is used to protect code.
0 0
1 0 The block may be written, erased or executed, but not read. This combination is unlikely to be used.
Read-only protection. The block may be read or executed but may not be written or erased. This mode
is used to lock the block from further modification while allowing any read or execute access.
0 1
1 1 No protection. The block may be written, erased, executed or read.
An access that attempts to program or erase a PE-protected block is prohibited. A controller interrupt
may be optionally generated (by setting the AMASK bit in the FIM register) to alert software developers
of poorly behaving software during the development and debug phases.
An access that attempts to read an RE-protected block is prohibited. Such accesses return data
filled with all 0s. A controller interrupt may be optionally generated to alert software developers of
poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. This implements a policy of open access and programmability. The register bits may be
changed by writing the specific register bit. The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. Details on
programming these bits are discussed in “Nonvolatile Register Programming” on page 142.
8.3 Flash Memory Initialization and Configuration
8.3.1 Flash Programming
The Stellaris® devices provide a user-friendly interface for flash programming. All erase/program
operations are handled via three registers: FMA, FMD, and FMC.
8.3.1.1 To program a 32-bit word
1. Write source data to the FMD register.
2. Write the target address to the FMA register.
3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register.
4. Poll the FMC register until the WRITE bit is cleared.
8.3.1.2 To perform an erase of a 1-KB page
1. Write the page address to the FMA register.
2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register.
3. Poll the FMC register until the ERASE bit is cleared.
8.3.1.3 To perform a mass erase of the flash
1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register.
2. Poll the FMC register until the MERASE bit is cleared.
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8.3.2 Nonvolatile Register Programming
This section discusses how to update registers that are resident within the flash memory itself.
These registers exist in a separate space from the main flash array and are not affected by an
ERASE or MASS ERASE operation. These nonvolatile registers are updated by using the COMT bit
in the FMC register to activate a write operation. For the USER_DBG register, the data to be written
must be loaded into the FMD register before it is "committed". All other registers are R/W and can
have their operation tried before committing them to nonvolatile memory.
Important: These registers can only have bits changed from 1 to 0 by the user and there is no
mechanism for the user to erase them back to a 1 value.
In addition, the USER_REG0, USER_REG1, and USER_DBG use bit 31 (NW) of their respective
registers to indicate that they are available for user write. These three registers can only be written
once whereas the flash protection registers may be written multiple times. Table 8-2 on page 142
provides the FMA address required for commitment of each of the registers and the source of the
data to be written when the COMT bit of the FMC register is written with a value of 0xA442.0008.
After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to
complete.
Table 8-2. Flash Resident Registersa
Register to be Committed FMA Value Data Source
FMPRE0 0x0000.0000 FMPRE0
FMPRE1 0x0000.0002 FMPRE1
FMPRE2 0x0000.0004 FMPRE2
FMPRE3 0x0000.0008 FMPRE3
FMPPE0 0x0000.0001 FMPPE0
FMPPE1 0x0000.0003 FMPPE1
FMPPE2 0x0000.0005 FMPPE2
FMPPE3 0x0000.0007 FMPPE3
USER_REG0 0x8000.0000 USER_REG0
USER_REG1 0x8000.0001 USER_REG1
USER_DBG 0x7510.0000 FMD
a. Which FMPREn and FMPPEn registers are available depend on the flash size of your particular Stellaris® device.
8.4 Register Map
Table 8-3 on page 142 lists the Flash memory and control registers. The offset listed is a hexadecimal
increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers
are relative to the Flash control base address of 0x400F.D000. The FMPREn, FMPPEn, USECRL,
USER_DBG, and USER_REGn registers are relative to the System Control base address of
0x400F.E000.
Table 8-3. Flash Register Map
See
Offset Name Type Reset Description page
Flash Control Offset
0x000 FMA R/W 0x0000.0000 Flash Memory Address 144
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See
Offset Name Type Reset Description page
0x004 FMD R/W 0x0000.0000 Flash Memory Data 145
0x008 FMC R/W 0x0000.0000 Flash Memory Control 146
0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 148
0x010 FCIM R/W 0x0000.0000 Flash Controller Interrupt Mask 149
0x014 FCMISC R/W1C 0x0000.0000 Flash Controller Masked Interrupt Status and Clear 150
System Control Offset
0x130 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 152
0x200 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 152
0x134 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 153
0x400 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 153
0x140 USECRL R/W 0x31 USec Reload 151
0x1D0 USER_DBG R/W 0xFFFF.FFFE User Debug 154
0x1E0 USER_REG0 R/W 0xFFFF.FFFF User Register 0 155
0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 156
0x204 FMPRE1 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 1 157
0x208 FMPRE2 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 2 158
0x20C FMPRE3 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 3 159
0x404 FMPPE1 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 1 160
0x408 FMPPE2 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 2 161
0x40C FMPPE3 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 3 162
8.5 Flash Register Descriptions (Flash Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000.
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Register 1: Flash Memory Address (FMA), offset 0x000
During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations, this register contains a 1 KB-aligned address and specifies
which page is erased. Note that the alignment requirements must be met by software or the results
of the operation are unpredictable.
Flash Memory Address (FMA)
Base 0x400F.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved OFFSET
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:18 reserved RO 0x0
Address Offset
Address offset in flash where operation is performed, except for
nonvolatile registers (see “Nonvolatile Register Programming” on page
142 for details on values for this field).
17:0 OFFSET R/W 0x0
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Register 2: Flash Memory Data (FMD), offset 0x004
This register contains the data to be written during the programming cycle or read during the read
cycle. Note that the contents of this register are undefined for a read access of an execute-only
block. This register is not used during the erase cycles.
Flash Memory Data (FMD)
Base 0x400F.D000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Data Value
Data value for write operation.
31:0 DATA R/W 0x0
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Register 3: Flash Memory Control (FMC), offset 0x008
When this register is written, the flash controller initiates the appropriate access cycle for the location
specified by the Flash Memory Address (FMA) register (see page 144). If the access is a write
access, the data contained in the Flash Memory Data (FMD) register (see page 145) is written.
This is the final register written and initiates the memory operation. There are four control bits in the
lower byte of this register that, when set, initiate the memory operation. The most used of these
register bits are the ERASE and WRITE bits.
It is a programming error to write multiple control bits and the results of such an operation are
unpredictable.
Flash Memory Control (FMC)
Base 0x400F.D000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRKEY
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved COMT MERASE ERASE WRITE
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Flash Write Key
This field contains a write key, which is used to minimize the incidence
of accidental flash writes. The value 0xA442 must be written into this
field for a write to occur. Writes to the FMC register without this WRKEY
value are ignored. A read of this field returns the value 0.
31:16 WRKEY WO 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:4 reserved RO 0x0
Commit Register Value
Commit (write) of register value to nonvolatile storage. A write of 0 has
no effect on the state of this bit.
If read, the state of the previous commit access is provided. If the
previous commit access is complete, a 0 is returned; otherwise, if the
commit access is not complete, a 1 is returned.
This can take up to 50 μs.
3 COMT R/W 0
Mass Erase Flash Memory
If this bit is set, the flash main memory of the device is all erased. A
write of 0 has no effect on the state of this bit.
If read, the state of the previous mass erase access is provided. If the
previous mass erase access is complete, a 0 is returned; otherwise, if
the previous mass erase access is not complete, a 1 is returned.
This can take up to 250 ms.
2 MERASE R/W 0
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Bit/Field Name Type Reset Description
Erase a Page of Flash Memory
If this bit is set, the page of flash main memory as specified by the
contents of FMA is erased. A write of 0 has no effect on the state of this
bit.
If read, the state of the previous erase access is provided. If the previous
erase access is complete, a 0 is returned; otherwise, if the previous
erase access is not complete, a 1 is returned.
This can take up to 25 ms.
1 ERASE R/W 0
Write a Word into Flash Memory
If this bit is set, the data stored in FMD is written into the location as
specified by the contents of FMA. A write of 0 has no effect on the state
of this bit.
If read, the state of the previous write update is provided. If the previous
write access is complete, a 0 is returned; otherwise, if the write access
is not complete, a 1 is returned.
This can take up to 50 μs.
0 WRITE R/W 0
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Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled
if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Base 0x400F.D000
Offset 0x00C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PRIS ARIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Programming Raw Interrupt Status
This bit indicates the current state of the programming cycle. If set, the
programming cycle completed; if cleared, the programming cycle has
not completed. Programming cycles are either write or erase actions
generated through the Flash Memory Control (FMC) register bits (see
page 146).
1 PRIS RO 0
Access Raw Interrupt Status
This bit indicates if the flash was improperly accessed. If set, the program
tried to access the flash counter to the policy as set in the Flash Memory
Protection Read Enable (FMPREn) and Flash Memory Protection
Program Enable (FMPPEn) registers. Otherwise, no access has tried
to improperly access the flash.
0 ARIS RO 0
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Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the flash controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PMASK AMASK
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the controller. If set, a programming-generated interrupt is promoted
to the controller. Otherwise, interrupts are recorded but suppressed from
the controller.
1 PMASK R/W 0
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
controller. If set, an access-generated interrupt is promoted to the
controller. Otherwise, interrupts are recorded but suppressed from the
controller.
0 AMASK R/W 0
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Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PMISC AMISC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Programming Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because a
programming cycle completed and was not masked. This bit is cleared
by writing a 1. The PRIS bit in the FCRIS register (see page 148) is also
cleared when the PMISC bit is cleared.
1 PMISC R/W1C 0
Access Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because an improper
access was attempted and was not masked. This bit is cleared by writing
a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC
bit is cleared.
0 AMISC R/W1C 0
8.6 Flash Register Descriptions (System Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the System Control base address of
0x400F.E000.
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Register 7: USec Reload (USECRL), offset 0x140
Note: Offset is relative to System Control base address of 0x400F.E000
This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller.
The internal flash has specific minimum and maximum requirements on the length of time the high
voltage write pulse can be applied. It is required that this register contain the operating frequency
(in MHz -1) whenever the flash is being erased or programmed. The user is required to change this
value if the clocking conditions are changed for a flash erase/program operation.
USec Reload (USECRL)
Base 0x400F.E000
Offset 0x140
Type R/W, reset 0x31
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved USEC
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Microsecond Reload Value
MHz -1 of the controller clock when the flash is being erased or
programmed.
USEC should be set to 0x31 (50 MHz) whenever the flash is being erased
or programmed.
7:0 USEC R/W 0x31
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Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130
and 0x200
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 0 (FMPRE0)
Base 0x400F.D000
Offset 0x130 and 0x200
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset
0x134 and 0x400
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 0 (FMPPE0)
Base 0x400F.D000
Offset 0x134 and 0x400
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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Register 10: User Debug (USER_DBG), offset 0x1D0
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides a write-once mechanism to disable external debugger access to the device
in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory
and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0
disables any external debugger access to the device permanently, starting with the next power-up
cycle of the device. The NOTWRITTEN bit (bit 31) indicates that the register is available to be written
and is controlled through hardware to ensure that the register is only written once.
User Debug (USER_DBG)
Base 0x400F.E000
Offset 0x1D0
Type R/W, reset 0xFFFF.FFFE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NW DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA DBG1 DBG0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Bit/Field Name Type Reset Description
User Debug Not Written
Specifies that this 32-bit dword has not been written.
31 NW R/W 1
User Data
Contains the user data value. This field is initialized to all 1s and can
only be written once.
30:2 DATA R/W 0x1FFFFFFF
Debug Control 1
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
1 DBG1 R/W 1
Debug Control 0
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
0 DBG0 R/W 0
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Register 11: User Register 0 (USER_REG0), offset 0x1E0
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 0 (USER_REG0)
Base 0x400F.E000
Offset 0x1E0
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NW DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Not Written
Specifies that this 32-bit dword has not been written.
31 NW R/W 1
User Data
Contains the user data value. This field is initialized to all 1s and can
only be written once.
30:0 DATA R/W 0x7FFFFFFF
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Register 12: User Register 1 (USER_REG1), offset 0x1E4
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 1 (USER_REG1)
Base 0x400F.E000
Offset 0x1E4
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NW DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Not Written
Specifies that this 32-bit dword has not been written.
31 NW R/W 1
User Data
Contains the user data value. This field is initialized to all 1s and can
only be written once.
30:0 DATA R/W 0x7FFFFFFF
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Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 1 (FMPRE1)
Base 0x400F.E000
Offset 0x204
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 2 (FMPRE2)
Base 0x400F.E000
Offset 0x208
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 3 (FMPRE3)
Base 0x400F.E000
Offset 0x20C
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset
0x404
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 1 (FMPPE1)
Base 0x400F.E000
Offset 0x404
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset
0x408
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 2 (FMPPE2)
Base 0x400F.E000
Offset 0x408
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset
0x40C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 3 (FMPPE3)
Base 0x400F.E000
Offset 0x40C
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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9 General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, and Port G, ). The GPIO module is
FiRM-compliant and supports 6-43 programmable input/output pins, depending on the peripherals
being used.
The GPIO module has the following features:
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ 5-V-tolerant input/outputs
■ Bit masking in both read and write operations through address lines
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
9.1 Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
9-1 on page 164). The LM3S6952 microcontroller contains seven ports and thus seven of these
physical GPIO blocks.
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Figure 9-1. GPIO Port Block Diagram
Alternate Input
Alternate Output
Alternate Output Enable
Interrupt
GPIO Input
GPIO Output
GPIO Output Enable
Pad Output
Pad Output Enable
Package I/O Pin
GPIODATA
GPIODIR
Data
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
Interrupt
Control
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
Pad
Control
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
Identification Registers
GPIOAFSEL
Mode
Control
DEMUX MUX MUX
Digital
I/O Pad
Pad Input
GPIOLOCK
Commit
Control
GPIOCR
9.1.1 Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
9.1.1.1 Data Direction Operation
The GPIO Direction (GPIODIR) register (see page 171) is used to configure each individual pin as
an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and
the corresponding data register bit will capture and store the value on the GPIO port. When the data
direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit
will be driven out on the GPIO port.
9.1.1.2 Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 170) by using bits [9:2] of the address bus as a mask.
This allows software drivers to modify individual GPIO pins in a single instruction, without affecting
the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write
operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA
register covers 256 locations in the memory map.
During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA
register is altered. If it is cleared to 0, it is left unchanged.
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For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 9-2 on page 165, where u is data unchanged by the write.
Figure 9-2. GPIODATA Write Example
0 0 1 0 0 1 1 0 1 0
u u 1 u u 0 1 u
9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 1 1
7 6 5 4 3 2 1 0
GPIODATA
0xEB
0x098
ADDR[9:2]
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value.
For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 9-3 on page 165.
Figure 9-3. GPIODATA Read Example
0 0 1 1 0 0 0 1 0 0
0 0 1 1 0 0 0 0
9 8 7 6 5 4 3 2 1 0
1 0 1 1 1 1 1 0
7 6 5 4 3 2 1 0
Returned Value
GPIODATA
0x0C4
ADDR[9:2]
9.1.2 Interrupt Control
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source
holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:
■ GPIO Interrupt Sense (GPIOIS) register (see page 172)
■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 173)
■ GPIO Interrupt Event (GPIOIEV) register (see page 174)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 175).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 176 and page 177). As the name implies, the GPIOMIS register only shows interrupt
conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a
GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller.
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In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (GPIOIM is set to 1), not only is an interrupt for
PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer
Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated.
If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored
Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts
and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt
handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC
interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC
registers until the conversion is completed.
Interrupts are cleared by writing a 1 to the GPIO Interrupt Clear (GPIOICR) register (see page 178).
When programming the following interrupt control registers, the interrupts should be masked (GPIOIM
set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can
generate a spurious interrupt if the corresponding bits are enabled.
9.1.3 Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is enabled
via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179), the pin state is
controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO
mode, where the GPIODATA register is used to read/write the corresponding pins.
9.1.4 Commit Control
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 190) have been set to 1.
9.1.5 Pad Control
The pad control registers allow for GPIO pad configuration by software based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers.
9.1.6 Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
9.2 Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 9-1 on page 167
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 9-2 on page 167 shows how a rising edge interrupt would be configured for pin
2 of a GPIO port.
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Table 9-1. GPIO Pad Configuration Examples
Configuration GPIO Register Bit Valuea
AFSEL DIR ODR DEN PUR PDR DR2R DR4R DR8R SLR
Digital Input (GPIO) 0 0 0 1 ? ? X X X X
Digital Output (GPIO) 0 1 0 1 ? ? ? ? ? ?
Open Drain Input 0 0 1 1 X X X X X X
(GPIO)
Open Drain Output 0 1 1 1 X X ? ? ? ?
(GPIO)
Open Drain 1 X 1 1 X X ? ? ? ?
Input/Output (I2C)
Digital Input (Timer 1 X 0 1 ? ? X X X X
CCP)
Digital Input (QEI) 1 X 0 1 ? ? X X X X
Digital Output (PWM) 1 X 0 1 ? ? ? ? ? ?
Digital Output (Timer 1 X 0 1 ? ? ? ? ? ?
PWM)
Digital Input/Output 1 X 0 1 ? ? ? ? ? ?
(SSI)
Digital Input/Output 1 X 0 1 ? ? ? ? ? ?
(UART)
Analog Input 0 0 0 0 0 0 X X X X
(Comparator)
Digital Output 1 X 0 1 ? ? ? ? ? ?
(Comparator)
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
Table 9-2. GPIO Interrupt Configuration Example
Desired Pin 2 Bit Valuea
Interrupt
Event
Trigger
Register
7 6 5 4 3 2 1 0
0=edge X X X X X 0 X X
1=level
GPIOIS
0=single X X X X X 0 X X
edge
1=both
edges
GPIOIBE
0=Low level, X X X X X 1 X X
or negative
edge
1=High level,
or positive
edge
GPIOIEV
0=masked 0 0 0 0 0 1 0 0
1=not
masked
GPIOIM
a. X=Ignored (don’t care bit)
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9.3 Register Map
Table 9-3 on page 168 lists the GPIO registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that GPIO port’s base address:
■ GPIO Port A: 0x4000.4000
■ GPIO Port B: 0x4000.5000
■ GPIO Port C: 0x4000.6000
■ GPIO Port D: 0x4000.7000
■ GPIO Port E: 0x4002.4000
■ GPIO Port F: 0x4002.5000
■ GPIO Port G: 0x4002.6000
Important: The GPIO registers in this chapter are duplicated in each GPIO block, however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to those unconnected bits has no effect and reading those unconnected
bits returns no meaningful data.
Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are
0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and
PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default
reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
The default register type for the GPIOCR register is RO for all GPIO pins, with the exception
of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because of this, the register type for
GPIO Port B7 and GPIO Port C[3:0] is R/W.
The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the
exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port
is not accidentally programmed as a GPIO, these five pins default to non-commitable.
Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while
the default reset value of GPIOCR for Port C is 0x0000.00F0.
Table 9-3. GPIO Register Map
See
Offset Name Type Reset Description page
0x000 GPIODATA R/W 0x0000.0000 GPIO Data 170
0x400 GPIODIR R/W 0x0000.0000 GPIO Direction 171
0x404 GPIOIS R/W 0x0000.0000 GPIO Interrupt Sense 172
0x408 GPIOIBE R/W 0x0000.0000 GPIO Interrupt Both Edges 173
0x40C GPIOIEV R/W 0x0000.0000 GPIO Interrupt Event 174
0x410 GPIOIM R/W 0x0000.0000 GPIO Interrupt Mask 175
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See
Offset Name Type Reset Description page
0x414 GPIORIS RO 0x0000.0000 GPIO Raw Interrupt Status 176
0x418 GPIOMIS RO 0x0000.0000 GPIO Masked Interrupt Status 177
0x41C GPIOICR W1C 0x0000.0000 GPIO Interrupt Clear 178
0x420 GPIOAFSEL R/W - GPIO Alternate Function Select 179
0x500 GPIODR2R R/W 0x0000.00FF GPIO 2-mA Drive Select 181
0x504 GPIODR4R R/W 0x0000.0000 GPIO 4-mA Drive Select 182
0x508 GPIODR8R R/W 0x0000.0000 GPIO 8-mA Drive Select 183
0x50C GPIOODR R/W 0x0000.0000 GPIO Open Drain Select 184
0x510 GPIOPUR R/W - GPIO Pull-Up Select 185
0x514 GPIOPDR R/W 0x0000.0000 GPIO Pull-Down Select 186
0x518 GPIOSLR R/W 0x0000.0000 GPIO Slew Rate Control Select 187
0x51C GPIODEN R/W - GPIO Digital Enable 188
0x520 GPIOLOCK R/W 0x0000.0001 GPIO Lock 189
0x524 GPIOCR - - GPIO Commit 190
0xFD0 GPIOPeriphID4 RO 0x0000.0000 GPIO Peripheral Identification 4 192
0xFD4 GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 193
0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 194
0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 195
0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 196
0xFE4 GPIOPeriphID1 RO 0x0000.0000 GPIO Peripheral Identification 1 197
0xFE8 GPIOPeriphID2 RO 0x0000.0018 GPIO Peripheral Identification 2 198
0xFEC GPIOPeriphID3 RO 0x0000.0001 GPIO Peripheral Identification 3 199
0xFF0 GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 200
0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 201
0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 202
0xFFC GPIOPCellID3 RO 0x0000.00B1 GPIO PrimeCell Identification 3 203
9.4 Register Descriptions
The remainder of this section lists and describes the GPIO registers, in numerical order by address
offset.
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Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 171).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from
the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause
the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the
corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
GPIO Data (GPIODATA)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Data
This register is virtually mapped to 256 locations in the address space.
To facilitate the reading and writing of data to these registers by
independent drivers, the data read from and the data written to the
registers are masked by the eight address lines ipaddr[9:2]. Reads
from this register return its current state. Writes to this register only affect
bits that are not masked by ipaddr[9:2] and are configured as
outputs. See “Data Register Operation” on page 164 for examples of
reads and writes.
7:0 DATA R/W 0x00
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General-Purpose Input/Outputs (GPIOs)
Register 2: GPIO Direction (GPIODIR), offset 0x400
The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure
the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are
cleared by a reset, meaning all GPIO pins are inputs by default.
GPIO Direction (GPIODIR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x400
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DIR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Data Direction
The DIR values are defined as follows:
Value Description
0 Pins are inputs.
1 Pins are outputs.
7:0 DIR R/W 0x00
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Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the
corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits
are cleared by a reset.
GPIO Interrupt Sense (GPIOIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x404
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IS
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Sense
The IS values are defined as follows:
Value Description
0 Edge on corresponding pin is detected (edge-sensitive).
1 Level on corresponding pin is detected (level-sensitive).
7:0 IS R/W 0x00
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Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register (see page 172) is set to detect edges, bits set to High in GPIOIBE
configure the corresponding pin to detect both rising and falling edges, regardless of the
corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 174). Clearing a bit
configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.
GPIO Interrupt Both Edges (GPIOIBE)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x408
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IBE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Both Edges
The IBE values are defined as follows:
Value Description
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 174).
0
1 Both edges on the corresponding pin trigger an interrupt.
Note: Single edge is determined by the corresponding bit
in GPIOIEV.
7:0 IBE R/W 0x00
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Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C
The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the
corresponding pin to detect rising edges or high levels, depending on the corresponding bit value
in the GPIO Interrupt Sense (GPIOIS) register (see page 172). Clearing a bit configures the pin to
detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are
cleared by a reset.
GPIO Interrupt Event (GPIOIEV)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x40C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IEV
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Event
The IEV values are defined as follows:
Value Description
Falling edge or Low levels on corresponding pins trigger
interrupts.
0
Rising edge or High levels on corresponding pins trigger
interrupts.
1
7:0 IEV R/W 0x00
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Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding
pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables
interrupt triggering on that pin. All bits are cleared by a reset.
GPIO Interrupt Mask (GPIOIM)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x410
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IME
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Mask Enable
The IME values are defined as follows:
Value Description
0 Corresponding pin interrupt is masked.
1 Corresponding pin interrupt is not masked.
7:0 IME R/W 0x00
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Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the
status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the
requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask
(GPIOIM) register (see page 175). Bits read as zero indicate that corresponding input pins have not
initiated an interrupt. All bits are cleared by a reset.
GPIO Raw Interrupt Status (GPIORIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x414
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Raw Status
Reflects the status of interrupt trigger condition detection on pins (raw,
prior to masking).
The RIS values are defined as follows:
Value Description
0 Corresponding pin interrupt requirements not met.
1 Corresponding pin interrupt has met requirements.
7:0 RIS RO 0x00
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Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect
the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has
been generated, or the interrupt is masked.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (GPIOIM is set to 1), not only is an interrupt for
PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer
Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated.
If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored
Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts
and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt
handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC
interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC
registers until the conversion is completed.
GPIOMIS is the state of the interrupt after masking.
GPIO Masked Interrupt Status (GPIOMIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x418
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Masked Interrupt Status
Masked value of interrupt due to corresponding pin.
The MIS values are defined as follows:
Value Description
0 Corresponding GPIO line interrupt not active.
1 Corresponding GPIO line asserting interrupt.
7:0 MIS RO 0x00
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Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt edge detection logic register. Writing a 0 has no effect.
GPIO Interrupt Clear (GPIOICR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x41C
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IC
Type RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Clear
The IC values are defined as follows:
Value Description
0 Corresponding interrupt is unaffected.
1 Corresponding interrupt is cleared.
7:0 IC W1C 0x00
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General-Purpose Input/Outputs (GPIOs)
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register
selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore
no GPIO line is set to hardware control by default.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 190) have been set to 1.
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors,
and apply RST or power-cycle the part.
In addition, it is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
GPIO Alternate Function Select (GPIOAFSEL)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x420
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved AFSEL
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
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Bit/Field Name Type Reset Description
GPIO Alternate Function Select
The AFSEL values are defined as follows:
Value Description
0 Software control of corresponding GPIO line (GPIO mode).
Hardware control of corresponding GPIO line (alternate
hardware function).
1
Note: The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
7:0 AFSEL R/W -
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Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO
signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 2-mA Drive Select (GPIODR2R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x500
Type R/W, reset 0x0000.00FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DRV2
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad 2-mA Drive Enable
A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the
corresponding 2-mA enable bit. The change is effective on the second
clock cycle after the write.
7:0 DRV2 R/W 0xFF
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Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504
The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 4-mA Drive Select (GPIODR4R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x504
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DRV4
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad 4-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the
corresponding 4-mA enable bit. The change is effective on the second
clock cycle after the write.
7:0 DRV4 R/W 0x00
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Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R
register are automatically cleared by hardware.
GPIO 8-mA Drive Select (GPIODR8R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x508
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DRV8
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad 8-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the
corresponding 8-mA enable bit. The change is effective on the second
clock cycle after the write.
7:0 DRV8 R/W 0x00
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Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see
page 188). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R,
and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open
drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open drain output
when set to 1.
When using the I2C module, the GPIO Alternate Function Select (GPIOAFSEL) register bit for
PB2 and PB3 should be set to 1 (see examples in “Initialization and Configuration” on page 166).
GPIO Open Drain Select (GPIOODR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x50C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ODE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad Open Drain Enable
The ODE values are defined as follows:
Value Description
0 Open drain configuration is disabled.
1 Open drain configuration is enabled.
7:0 ODE R/W 0x00
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General-Purpose Input/Outputs (GPIOs)
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up
resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 186).
GPIO Pull-Up Select (GPIOPUR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x510
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PUE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Pad Weak Pull-Up Enable
A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n]
enables. The change is effective on the second clock cycle after the
write.
Note: The default reset value for the GPIOAFSEL, GPIOPUR, and
GPIODEN registers are 0x0000.0000 for all GPIO pins, with
the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
These five pins default to JTAG/SWD functionality. Because
of this, the default reset value of these registers for GPIO Port
B is 0x0000.0080 while the default reset value for Port C is
0x0000.000F.
7:0 PUE R/W -
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Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak
pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 185).
GPIO Pull-Down Select (GPIOPDR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x514
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PDE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Pad Weak Pull-Down Enable
A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n]
enables. The change is effective on the second clock cycle after the
write.
7:0 PDE R/W 0x00
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General-Purpose Input/Outputs (GPIOs)
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
The GPIOSLR register is the slew rate control register. Slew rate control is only available when
using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see
page 183).
GPIO Slew Rate Control Select (GPIOSLR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x518
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SRL
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Slew Rate Limit Enable (8-mA drive only)
The SRL values are defined as follows:
Value Description
0 Slew rate control disabled.
1 Slew rate control enabled.
7:0 SRL R/W 0x00
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Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
The GPIODEN register is the digital enable register. By default, with the exception of the GPIO
signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven
(tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not
allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or
alternate function), the corresponding GPIODEN bit must be set.
GPIO Digital Enable (GPIODEN)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x51C
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DEN
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Digital Enable
The DEN values are defined as follows:
Value Description
0 Digital functions disabled.
1 Digital functions enabled.
Note: The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
7:0 DEN R/W -
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General-Purpose Input/Outputs (GPIOs)
Register 19: GPIO Lock (GPIOLOCK), offset 0x520
The GPIOLOCK register enables write access to the GPIOCR register (see page 190). Writing
0x1ACCE551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value
to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns
the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses
are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses
are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000.
GPIO Lock (GPIOLOCK)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x520
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
GPIO Lock
A write of the value 0x1ACCE551 unlocks the GPIO Commit (GPIOCR)
register for write access. A write of any other value reapplies the lock,
preventing any register updates. A read of this register returns the
following values:
Value Description
0x0000.0001 locked
0x0000.0000 unlocked
31:0 LOCK R/W 0x0000.0001
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Register 20: GPIO Commit (GPIOCR), offset 0x524
The GPIOCR register is the commit register. The value of the GPIOCR register determines which
bits of the GPIOAFSEL register will be committed when a write to the GPIOAFSEL register is
performed. If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit
in the GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the
GPIOCR register is a one, the data being written to the corresponding bit of the GPIOAFSEL register
will be committed to the register and will reflect the new value.
The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked.
Writes to the GPIOCR register will be ignored if the GPIOLOCK register is locked.
Important: This register is designed to prevent accidental programming of the GPIOAFSEL registers
that control connectivity to the JTAG/SWD debug hardware. By initializing the bits of
the GPIOCR register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only
be converted to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR,
and GPIOAFSEL registers.
Because this protection is currently only implemented on the JTAG/SWD pins on PB7
and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0.
These bits are hardwired to 0x1, ensuring that it is always possible to commit new
values to the GPIOAFSEL register bits of these other pins.
GPIO Commit (GPIOCR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x524
Type -, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CR
Type RO RO RO RO RO RO RO RO - - - - - - - -
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
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General-Purpose Input/Outputs (GPIOs)
Bit/Field Name Type Reset Description
GPIO Commit
On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL
bit to be set to its alternate function.
Note: The default register type for the GPIOCR register is RO for
all GPIO pins, with the exception of the five JTAG/SWD pins
(PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because
of this, the register type for GPIO Port B7 and GPIO Port
C[3:0] is R/W.
The default reset value for the GPIOCR register is
0x0000.00FF for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the
JTAG port is not accidentally programmed as a GPIO, these
five pins default to non-commitable. Because of this, the
default reset value of GPIOCR for GPIO Port B is
0x0000.007F while the default reset value of GPIOCR for Port
C is 0x0000.00F0.
7:0 CR - -
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Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 4 (GPIOPeriphID4)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID4 RO 0x00 GPIO Peripheral ID Register[7:0]
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General-Purpose Input/Outputs (GPIOs)
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 5 (GPIOPeriphID5)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID5 RO 0x00 GPIO Peripheral ID Register[15:8]
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Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 6 (GPIOPeriphID6)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID6 RO 0x00 GPIO Peripheral ID Register[23:16]
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General-Purpose Input/Outputs (GPIOs)
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 7 (GPIOPeriphID7)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID7 RO 0x00 GPIO Peripheral ID Register[31:24]
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Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 0 (GPIOPeriphID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE0
Type RO, reset 0x0000.0061
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID0 RO 0x61
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General-Purpose Input/Outputs (GPIOs)
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 1 (GPIOPeriphID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID1 RO 0x00
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Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 2 (GPIOPeriphID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID2 RO 0x18
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General-Purpose Input/Outputs (GPIOs)
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 3 (GPIOPeriphID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID3 RO 0x01
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Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 0 (GPIOPCellID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
7:0 CID0 RO 0x0D
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Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 1 (GPIOPCellID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
7:0 CID1 RO 0xF0
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Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 2 (GPIOPCellID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
7:0 CID2 RO 0x05
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Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 3 (GPIOPCellID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
7:0 CID3 RO 0xB1
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10 General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris® General-Purpose Timer Module (GPTM) contains three GPTM blocks (Timer0, Timer1,
and Timer 2). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA and
TimerB) that can be configured to operate independently as timers or event counters, or configured
to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to
trigger analog-to-digital (ADC) conversions. The trigger signals from all of the general-purpose timers
are ORed together before reaching the ADC module, so only one timer should be used to trigger
ADC events.
Note: Timer2 is an internal timer and can only be used to generate internal interrupts or trigger
ADC events.
The General-Purpose Timer Module is one timing resource available on the Stellaris® microcontrollers.
Other timer resources include the System Timer (SysTick) (see “System Timer (SysTick)” on page 40)
and the PWM timer in the PWM module (see “PWM Timer” on page 466).
The following modes are supported:
■ 32-bit Timer modes
– Programmable one-shot timer
– Programmable periodic timer
– Real-Time Clock using 32.768-KHz input clock
– Software-controlled event stalling (excluding RTC mode)
■ 16-bit Timer modes
– General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only)
– Programmable one-shot timer
– Programmable periodic timer
– Software-controlled event stalling
■ 16-bit Input Capture modes
– Input edge count capture
– Input edge time capture
■ 16-bit PWM mode
– Simple PWM mode with software-programmable output inversion of the PWM signal
10.1 Block Diagram
Note: In Figure 10-1 on page 205, the specific CCP pins available depend on the Stellaris® device.
See Table 10-1 on page 205 for the available CCPs.
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Figure 10-1. GPTM Module Block Diagram
TA Comparator
TB Comparator
GPTMTBR
GPTMAR
Clock / Edge
Detect
RTC Divider
Clock / Edge
Detect
TimerA
Interrupt
TimerB
Interrupt
System
Clock
0x0000 (Down Counter Modes)
0x0000 (Down Counter Modes)
32 KHz or
Even CCP Pin
Odd CCP Pin
En
En
TimerA Control
GPTMTAPMR
GPTMTAILR
GPTMTAMATCHR
GPTMTAPR
GPTMTAMR
TimerB Control
GPTMTBPMR
GPTMTBILR
GPTMTBMATCHR
GPTMTBPR
GPTMTBMR
Interrupt / Config
GPTMCFG
GPTMRIS
GPTMICR
GPTMMIS
GPTMIMR
GPTMCTL
Table 10-1. Available CCP Pins
Timer 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin
Timer 0 TimerA CCP0 -
TimerB - CCP1
Timer 1 TimerA CCP2 -
TimerB - CCP3
Timer 2 TimerA - -
TimerB - -
10.2 Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit
load/initialization registers and their associated control functions. The exact functionality of each
GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 216),
the GPTM TimerA Mode (GPTMTAMR) register (see page 217), and the GPTM TimerB Mode
(GPTMTBMR) register (see page 219). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
10.2.1 GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters TimerA and TimerB are initialized to
0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
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(GPTMTAILR) register (see page 230) and the GPTM TimerB Interval Load (GPTMTBILR) register
(see page 231). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale
(GPTMTAPR) register (see page 234) and the GPTM TimerB Prescale (GPTMTBPR) register (see
page 235).
10.2.2 32-Bit Timer Operating Modes
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configuration.
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 230
■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 231
■ GPTM TimerA (GPTMTAR) register [15:0], see page 238
■ GPTM TimerB (GPTMTBR) register [15:0], see page 239
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
10.2.2.1 32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB
registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is
determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register
(see page 217), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register.
When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 221), the
timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the
timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to
be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If
configured as a periodic timer, it continues counting.
In addition to reloading the count value, the GPTM generates interrupts and output triggers when
it reaches the 0x0000000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status
(GPTMRIS) register (see page 226), and holds it until it is cleared by writing the GPTM Interrupt
Clear (GPTMICR) register (see page 228). If the time-out interrupt is enabled in the GPTM Interrupt
Mask (GPTIMR) register (see page 224), the GPTM also sets the TATOMIS bit in the GPTM Masked
Interrupt Status (GPTMMIS) register (see page 227).
The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000.0000
state, and deasserted on the following clock cycle. It is enabled by setting the TAOTE bit in GPTMCTL,
and can trigger SoC-level events such as ADC conversions.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
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If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal
is deasserted.
10.2.2.2 32-Bit Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is
loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA
Match (GPTMTAMATCHR) register (see page 232) by the controller.
The input clock on the CCP0, CCP2, or CCP4 pins is required to be 32.768 KHz in RTC mode. The
clock signal is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter.
When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its
preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until
either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs,
the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the
GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags
are cleared by writing the RTCCINT bit in GPTMICR.
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if
the RTCEN bit is set in GPTMCTL.
10.2.3 16-Bit Timer Operating Modes
The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration
(GPTMCFG) register (see page 216). This section describes each of the GPTM 16-bit modes of
operation. TimerA and TimerB have identical modes, so a single description is given using an n to
reference both.
10.2.3.1 16-Bit One-Shot/Periodic Timer Mode
In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with
an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The
selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR)
register.
When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from
its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from
GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops
counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it
continues counting.
In addition to reloading the count value, the timer generates interrupts and output triggers when it
reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it
until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR,
the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt.
The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000 state,
and deasserted on the following clock cycle. It is enabled by setting the TnOTE bit in the GPTMCTL
register, and can trigger SoC-level events such as ADC conversions.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
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If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal
is deasserted.
The following example shows a variety of configurations for a 16-bit free running timer while using
the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period).
Table 10-2. 16-Bit Timer With Prescaler Configurations
Prescale #Clock (T c)a Max Time Units
00000000 1 1.3107 mS
00000001 2 2.6214 mS
00000010 3 3.9321 mS
------------ -- -- --
11111100 254 332.9229 mS
11111110 255 334.2336 mS
11111111 256 335.5443 mS
a. Tc is the clock period.
10.2.3.2 16-Bit Input Edge Count Mode
In Edge Count mode, the timer is configured as a down-counter capable of capturing three types
of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit
of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined
by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match
(GPTMTnMATCHR) register is configured so that the difference between the value in the
GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that
must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count
matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the
GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded
using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in
the GPTMCTL register. Once the event count has been reached, all further events are ignored until
TnEN is re-enabled by software.
Figure 10-2 on page 209 shows how input edge count mode works. In this case, the timer start value
is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so that four
edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit after
the current count matches the value in the GPTMnMR register.
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Figure 10-2. 16-Bit Input Edge Count Mode Example
0x000A
0x0006
0x0007
0x0008
0x0009
Input Signal
Timer stops,
flags
asserted
Timer reload
Count on next cycle Ignored Ignored
10.2.3.3 16-Bit Input Edge Time Mode
Note: The prescaler is not available in 16-Bit Input Edge Time mode.
In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value
loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of both
rising and falling edges. The timer is placed into Edge Time mode by setting the TnCMR bit in the
GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT
fields of the GPTMCnTL register.
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture.
When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR
register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and
the CnEMIS bit, if the interrupt is not masked).
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the
GPTMnILR register.
Figure 10-3 on page 210 shows how input edge timing mode works. In the diagram, it is assumed
that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture
rising edge events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR
register, and is held there until another rising edge is detected (at which point the new count value
is loaded into GPTMTnR).
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Figure 10-3. 16-Bit Input Edge Time Mode Example
GPTMTnR=Y
Input Signal
Time
Count
GPTMTnR=X GPTMTnR=Z
Z
X
Y
0xFFFF
10.2.3.4 16-Bit PWM Mode
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled
with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR
field to 0x2.
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from
GPTMTnILR (and GPTMTnPR if using a prescaler) and continues counting until disabled by software
clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM
mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTM Timern Match
Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by
setting the TnPWML bit in the GPTMCTL register.
Figure 10-4 on page 211 shows how to generate an output PWM with a 1-ms period and a 66% duty
cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML
=1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is
GPTMnMR=0x411A.
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Figure 10-4. 16-Bit PWM Mode Example
Output
Signal
Time
Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR
0xC350
0x411A
TnPWML = 0
TnPWML = 1
TnEN set
10.3 Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0,
TIMER1, and TIMER2 bits in the RCGC1 register.
This section shows module initialization and configuration examples for each of the supported timer
modes.
10.3.1 32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0.
3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR).
5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
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7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
In One-Shot mode, the timer stops counting after step 7 on page 212. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
10.3.2 32-Bit Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on its CCP0, CCP2, or CCP4
pins. To enable the RTC feature, follow these steps:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1.
3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR).
4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired.
5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded
with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared.
10.3.3 16-Bit One-Shot/Periodic Timer Mode
A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4.
3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register:
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register
(GPTMTnPR).
5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR).
6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start
counting.
8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
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In One-Shot mode, the timer stops counting after step 8 on page 212. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
10.3.4 16-Bit Input Edge Count Mode
A timer is configured to Input Edge Count mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.
4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register.
7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.
9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM
Interrupt Clear (GPTMICR) register.
In Input Edge Count Mode, the timer stops after the desired number of edge events has been
detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 213
through step 9 on page 213.
10.3.5 16-Bit Input Edge Timing Mode
A timer is configured to Input Edge Timing mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3.
4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting.
8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM
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Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timern (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
10.3.6 16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field
of the GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.
7. If a prescaler is going to be used, configure the GPTM Timern Prescale (GPTMTnPR) register
and the GPTM Timern Prescale Match (GPTMTnPMR) register.
8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
10.4 Register Map
Table 10-3 on page 214 lists the GPTM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that timer’s base address:
■ Timer0: 0x4003.0000
■ Timer1: 0x4003.1000
■ Timer2: 0x4003.2000
Table 10-3. Timers Register Map
See
Offset Name Type Reset Description page
0x000 GPTMCFG R/W 0x0000.0000 GPTM Configuration 216
0x004 GPTMTAMR R/W 0x0000.0000 GPTM TimerA Mode 217
0x008 GPTMTBMR R/W 0x0000.0000 GPTM TimerB Mode 219
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See
Offset Name Type Reset Description page
0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 221
0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 224
0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 226
0x020 GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 227
0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 228
GPTM TimerA Interval Load 230
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
0x028 GPTMTAILR R/W
0x02C GPTMTBILR R/W 0x0000.FFFF GPTM TimerB Interval Load 231
GPTM TimerA Match 232
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
0x030 GPTMTAMATCHR R/W
0x034 GPTMTBMATCHR R/W 0x0000.FFFF GPTM TimerB Match 233
0x038 GPTMTAPR R/W 0x0000.0000 GPTM TimerA Prescale 234
0x03C GPTMTBPR R/W 0x0000.0000 GPTM TimerB Prescale 235
0x040 GPTMTAPMR R/W 0x0000.0000 GPTM TimerA Prescale Match 236
0x044 GPTMTBPMR R/W 0x0000.0000 GPTM TimerB Prescale Match 237
GPTM TimerA 238
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
0x048 GPTMTAR RO
0x04C GPTMTBR RO 0x0000.FFFF GPTM TimerB 239
10.5 Register Descriptions
The remainder of this section lists and describes the GPTM registers, in numerical order by address
offset.
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Register 1: GPTM Configuration (GPTMCFG), offset 0x000
This register configures the global operation of the GPTM module. The value written to this register
determines whether the GPTM is in 32- or 16-bit mode.
GPTM Configuration (GPTMCFG)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPTMCFG
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
GPTM Configuration
The GPTMCFG values are defined as follows:
Value Description
0x0 32-bit timer configuration.
0x1 32-bit real-time clock (RTC) counter configuration.
0x2 Reserved.
0x3 Reserved.
16-bit timer configuration, function is controlled by bits 1:0 of
GPTMTAMR and GPTMTBMR.
0x4-0x7
2:0 GPTMCFG R/W 0x0
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Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.
GPTM TimerA Mode (GPTMTAMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TAAMS TACMR TAMR
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
GPTM TimerA Alternate Mode Select
The TAAMS values are defined as follows:
Value Description
0 Capture mode is enabled.
1 PWM mode is enabled.
Note: To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.
3 TAAMS R/W 0
GPTM TimerA Capture Mode
The TACMR values are defined as follows:
Value Description
0 Edge-Count mode.
1 Edge-Time mode.
2 TACMR R/W 0
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Bit/Field Name Type Reset Description
GPTM TimerA Mode
The TAMR values are defined as follows:
Value Description
0x0 Reserved.
0x1 One-Shot Timer mode.
0x2 Periodic Timer mode.
0x3 Capture mode.
The Timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register (16-or 32-bit).
In 16-bit timer configuration, TAMR controls the 16-bit timer modes for
TimerA.
In 32-bit timer configuration, this register controls the mode and the
contents of GPTMTBMR are ignored.
1:0 TAMR R/W 0x0
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Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to
0x2.
GPTM TimerB Mode (GPTMTBMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBAMS TBCMR TBMR
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
GPTM TimerB Alternate Mode Select
The TBAMS values are defined as follows:
Value Description
0 Capture mode is enabled.
1 PWM mode is enabled.
Note: To enable PWM mode, you must also clear the TBCMR
bit and set the TBMR field to 0x2.
3 TBAMS R/W 0
GPTM TimerB Capture Mode
The TBCMR values are defined as follows:
Value Description
0 Edge-Count mode.
1 Edge-Time mode.
2 TBCMR R/W 0
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Bit/Field Name Type Reset Description
GPTM TimerB Mode
The TBMR values are defined as follows:
Value Description
0x0 Reserved.
0x1 One-Shot Timer mode.
0x2 Periodic Timer mode.
0x3 Capture mode.
The timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
In 16-bit timer configuration, these bits control the 16-bit timer modes
for TimerB.
In 32-bit timer configuration, this register’s contents are ignored and
GPTMTAMR is used.
1:0 TBMR R/W 0x0
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Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBPWML TBOTE reserved TBEVENT TBSTALL TBEN reserved TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN
Type RO R/W R/W RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:15 reserved RO 0x00
GPTM TimerB PWM Output Level
The TBPWML values are defined as follows:
Value Description
0 Output is unaffected.
1 Output is inverted.
14 TBPWML R/W 0
GPTM TimerB Output Trigger Enable
The TBOTE values are defined as follows:
Value Description
0 The output TimerB trigger is disabled.
1 The output TimerB trigger is enabled.
13 TBOTE R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12 reserved RO 0
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Bit/Field Name Type Reset Description
GPTM TimerB Event Mode
The TBEVENT values are defined as follows:
Value Description
0x0 Positive edge.
0x1 Negative edge.
0x2 Reserved
0x3 Both edges.
11:10 TBEVENT R/W 0x0
GPTM TimerB Stall Enable
The TBSTALL values are defined as follows:
Value Description
0 TimerB stalling is disabled.
1 TimerB stalling is enabled.
9 TBSTALL R/W 0
GPTM TimerB Enable
The TBEN values are defined as follows:
Value Description
0 TimerB is disabled.
TimerB is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
8 TBEN R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
GPTM TimerA PWM Output Level
The TAPWML values are defined as follows:
Value Description
0 Output is unaffected.
1 Output is inverted.
6 TAPWML R/W 0
GPTM TimerA Output Trigger Enable
The TAOTE values are defined as follows:
Value Description
0 The output TimerA trigger is disabled.
1 The output TimerA trigger is enabled.
5 TAOTE R/W 0
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Bit/Field Name Type Reset Description
GPTM RTC Enable
The RTCEN values are defined as follows:
Value Description
0 RTC counting is disabled.
1 RTC counting is enabled.
4 RTCEN R/W 0
GPTM TimerA Event Mode
The TAEVENT values are defined as follows:
Value Description
0x0 Positive edge.
0x1 Negative edge.
0x2 Reserved
0x3 Both edges.
3:2 TAEVENT R/W 0x0
GPTM TimerA Stall Enable
The TASTALL values are defined as follows:
Value Description
0 TimerA stalling is disabled.
1 TimerA stalling is enabled.
1 TASTALL R/W 0
GPTM TimerA Enable
The TAEN values are defined as follows:
Value Description
0 TimerA is disabled.
TimerA is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
0 TAEN R/W 0
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Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables
the interrupt, while writing a 0 disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x018
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBEIM CBMIM TBTOIM reserved RTCIM CAEIM CAMIM TATOIM
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Interrupt Mask
The CBEIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
10 CBEIM R/W 0
GPTM CaptureB Match Interrupt Mask
The CBMIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
9 CBMIM R/W 0
GPTM TimerB Time-Out Interrupt Mask
The TBTOIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
8 TBTOIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0
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Bit/Field Name Type Reset Description
GPTM RTC Interrupt Mask
The RTCIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
3 RTCIM R/W 0
GPTM CaptureA Event Interrupt Mask
The CAEIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
2 CAEIM R/W 0
GPTM CaptureA Match Interrupt Mask
The CAMIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
1 CAMIM R/W 0
GPTM TimerA Time-Out Interrupt Mask
The TATOIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
0 TATOIM R/W 0
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Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBERIS CBMRIS TBTORIS reserved RTCRIS CAERIS CAMRIS TATORIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
10 CBERIS RO 0
GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
9 CBMRIS RO 0
GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
8 TBTORIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x0
GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
3 RTCRIS RO 0
GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
2 CAERIS RO 0
GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
1 CAMRIS RO 0
GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
0 TATORIS RO 0
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Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x020
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBEMIS CBMMIS TBTOMIS reserved RTCMIS CAEMIS CAMMIS TATOMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Masked Interrupt
This is the CaptureB event interrupt status after masking.
10 CBEMIS RO 0
GPTM CaptureB Match Masked Interrupt
This is the CaptureB match interrupt status after masking.
9 CBMMIS RO 0
GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
8 TBTOMIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x0
GPTM RTC Masked Interrupt
This is the RTC event interrupt status after masking.
3 RTCMIS RO 0
GPTM CaptureA Event Masked Interrupt
This is the CaptureA event interrupt status after masking.
2 CAEMIS RO 0
GPTM CaptureA Match Masked Interrupt
This is the CaptureA match interrupt status after masking.
1 CAMMIS RO 0
GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
0 TATOMIS RO 0
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Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x024
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBECINT CBMCINT TBTOCINT reserved RTCCINT CAECINT CAMCINT TATOCINT
Type RO RO RO RO RO W1C W1C W1C RO RO RO RO W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Interrupt Clear
The CBECINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
10 CBECINT W1C 0
GPTM CaptureB Match Interrupt Clear
The CBMCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
9 CBMCINT W1C 0
GPTM TimerB Time-Out Interrupt Clear
The TBTOCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
8 TBTOCINT W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x0
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Bit/Field Name Type Reset Description
GPTM RTC Interrupt Clear
The RTCCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
3 RTCCINT W1C 0
GPTM CaptureA Event Interrupt Clear
The CAECINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
2 CAECINT W1C 0
GPTM CaptureA Match Raw Interrupt
This is the CaptureA match interrupt status after masking.
1 CAMCINT W1C 0
GPTM TimerA Time-Out Raw Interrupt
The TATOCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
0 TATOCINT W1C 0
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Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028
This register is used to load the starting count value into the timer. When GPTM is configured to
one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond
to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
GPTM TimerA Interval Load (GPTMTAILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x028
Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAILRH
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAILRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
GPTM TimerA Interval Load Register High
When configured for 32-bit mode via the GPTMCFG register, the GPTM
TimerB Interval Load (GPTMTBILR) register loads this value on a
write. A read returns the current value of GPTMTBILR.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBILR.
0xFFFF
(32-bit mode)
0x0000 (16-bit
mode)
31:16 TAILRH R/W
GPTM TimerA Interval Load Register Low
For both 16- and 32-bit modes, writing this field loads the counter for
TimerA. A read returns the current value of GPTMTAILR.
15:0 TAILRL R/W 0xFFFF
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General-Purpose Timers
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C
This register is used to load the starting count value into TimerB. When the GPTM is configured to
a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes.
GPTM TimerB Interval Load (GPTMTBILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBILRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
GPTM TimerB Interval Load Register
When the GPTM is not configured as a 32-bit timer, a write to this field
updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads
return the current value of GPTMTBILR.
15:0 TBILRL R/W 0xFFFF
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LM3S6952 Microcontroller
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerA Match (GPTMTAMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x030
Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMRH
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
GPTM TimerA Match Register High
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the upper half of
GPTMTAR, to determine match events.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBMATCHR.
0xFFFF
(32-bit mode)
0x0000 (16-bit
mode)
31:16 TAMRH R/W
GPTM TimerA Match Register Low
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the lower half of
GPTMTAR, to determine match events.
When configured for PWM mode, this value along with GPTMTAILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTAILR
minus this value.
15:0 TAMRL R/W 0xFFFF
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General-Purpose Timers
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerB Match (GPTMTBMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x034
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBMRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
GPTM TimerB Match Register Low
When configured for PWM mode, this value along with GPTMTBILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTBILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTBILR
minus this value.
15:0 TBMRL R/W 0xFFFF
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LM3S6952 Microcontroller
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerA Prescale (GPTMTAPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TAPSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerA Prescale
The register loads this value on a write. A read returns the current value
of the register.
Refer to Table 10-2 on page 208 for more details and an example.
7:0 TAPSR R/W 0x00
234 November 30, 2007
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General-Purpose Timers
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerB Prescale (GPTMTBPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x03C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBPSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerB Prescale
The register loads this value on a write. A read returns the current value
of this register.
Refer to Table 10-2 on page 208 for more details and an example.
7:0 TBPSR R/W 0x00
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Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040
This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerA Prescale Match (GPTMTAPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x040
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TAPSMR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerA Prescale Match
This value is used alongside GPTMTAMATCHR to detect timer match
events while using a prescaler.
7:0 TAPSMR R/W 0x00
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General-Purpose Timers
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044
This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerB Prescale Match (GPTMTBPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x044
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBPSMR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerB Prescale Match
This value is used alongside GPTMTBMATCHR to detect timer match
events while using a prescaler.
7:0 TBPSMR R/W 0x00
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LM3S6952 Microcontroller
Register 17: GPTM TimerA (GPTMTAR), offset 0x048
This register shows the current value of the TimerA counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerA (GPTMTAR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x048
Type RO, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TARH
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TARL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
GPTM TimerA Register High
If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the
GPTMCFG is in a 16-bit mode, this is read as zero.
0xFFFF
(32-bit mode)
0x0000 (16-bit
mode)
31:16 TARH RO
GPTM TimerA Register Low
A read returns the current value of the GPTM TimerA Count Register,
except in Input Edge Count mode, when it returns the timestamp from
the last edge event.
15:0 TARL RO 0xFFFF
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General-Purpose Timers
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C
This register shows the current value of the TimerB counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerB (GPTMTBR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x04C
Type RO, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBRL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
GPTM TimerB
A read returns the current value of the GPTM TimerB Count Register,
except in Input Edge Count mode, when it returns the timestamp from
the last edge event.
15:0 TBRL RO 0xFFFF
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LM3S6952 Microcontroller
11 Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
The Stellaris® Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, a locking register, and user-enabled stalling.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
11.1 Block Diagram
Figure 11-1. WDT Module Block Diagram
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
WDTRIS
WDTMIS
WDTLOCK
WDTTEST
WDTLOAD
WDTVALUE
Comparator
32-Bit Down
Counter
0x00000000
Interrupt
System Clock
Identification Registers
WDTPCellID0 WDTPeriphID0 WDTPeriphID4
WDTPCellID1 WDTPeriphID1 WDTPeriphID5
WDTPCellID2 WDTPeriphID2 WDTPeriphID6
WDTPCellID3 WDTPeriphID3 WDTPeriphID7
11.2 Functional Description
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the
240 November 30, 2007
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Watchdog Timer
Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written,
which prevents the timer configuration from being inadvertently altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) register.
The Watchdog module interrupt and reset generation can be enabled or disabled as required. When
the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its
last state.
11.3 Initialization and Configuration
To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register.
The Watchdog Timer is configured using the following sequence:
1. Load the WDTLOAD register with the desired timer load value.
2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.
3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register.
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write
a value of 0x1ACC.E551.
11.4 Register Map
Table 11-1 on page 241 lists the Watchdog registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000.
Table 11-1. Watchdog Timer Register Map
See
Offset Name Type Reset Description page
0x000 WDTLOAD R/W 0xFFFF.FFFF Watchdog Load 243
0x004 WDTVALUE RO 0xFFFF.FFFF Watchdog Value 244
0x008 WDTCTL R/W 0x0000.0000 Watchdog Control 245
0x00C WDTICR WO - Watchdog Interrupt Clear 246
0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 247
0x014 WDTMIS RO 0x0000.0000 Watchdog Masked Interrupt Status 248
0x418 WDTTEST R/W 0x0000.0000 Watchdog Test 249
0xC00 WDTLOCK R/W 0x0000.0000 Watchdog Lock 250
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LM3S6952 Microcontroller
See
Offset Name Type Reset Description page
0xFD0 WDTPeriphID4 RO 0x0000.0000 Watchdog Peripheral Identification 4 251
0xFD4 WDTPeriphID5 RO 0x0000.0000 Watchdog Peripheral Identification 5 252
0xFD8 WDTPeriphID6 RO 0x0000.0000 Watchdog Peripheral Identification 6 253
0xFDC WDTPeriphID7 RO 0x0000.0000 Watchdog Peripheral Identification 7 254
0xFE0 WDTPeriphID0 RO 0x0000.0005 Watchdog Peripheral Identification 0 255
0xFE4 WDTPeriphID1 RO 0x0000.0018 Watchdog Peripheral Identification 1 256
0xFE8 WDTPeriphID2 RO 0x0000.0018 Watchdog Peripheral Identification 2 257
0xFEC WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 258
0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 259
0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 260
0xFF8 WDTPCellID2 RO 0x0000.0005 Watchdog PrimeCell Identification 2 261
0xFFC WDTPCellID3 RO 0x0000.00B1 Watchdog PrimeCell Identification 3 262
11.5 Register Descriptions
The remainder of this section lists and describes the WDT registers, in numerical order by address
offset.
242 November 30, 2007
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Watchdog Timer
Register 1: Watchdog Load (WDTLOAD), offset 0x000
This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the
value is immediately loaded and the counter restarts counting down from the new value. If the
WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated.
Watchdog Load (WDTLOAD)
Base 0x4000.0000
Offset 0x000
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTLoad
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTLoad
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
31:0 WDTLoad R/W 0xFFFF.FFFF Watchdog Load Value
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LM3S6952 Microcontroller
Register 2: Watchdog Value (WDTVALUE), offset 0x004
This register contains the current count value of the timer.
Watchdog Value (WDTVALUE)
Base 0x4000.0000
Offset 0x004
Type RO, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTValue
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTValue
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Watchdog Value
Current value of the 32-bit down counter.
31:0 WDTValue RO 0xFFFF.FFFF
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Watchdog Timer
Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.
Watchdog Control (WDTCTL)
Base 0x4000.0000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RESEN INTEN
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Watchdog Reset Enable
The RESEN values are defined as follows:
Value Description
0 Disabled.
1 Enable the Watchdog module reset output.
1 RESEN R/W 0
Watchdog Interrupt Enable
The INTEN values are defined as follows:
Value Description
Interrupt event disabled (once this bit is set, it can only be
cleared by a hardware reset).
0
1 Interrupt event enabled. Once enabled, all writes are ignored.
0 INTEN R/W 0
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Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C
This register is the interrupt clear register. A write of any value to this register clears the Watchdog
interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is
indeterminate.
Watchdog Interrupt Clear (WDTICR)
Base 0x4000.0000
Offset 0x00C
Type WO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTIntClr
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTIntClr
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
31:0 WDTIntClr WO - Watchdog Interrupt Clear
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Watchdog Timer
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010
This register is the raw interrupt status register. Watchdog interrupt events can be monitored via
this register if the controller interrupt is masked.
Watchdog Raw Interrupt Status (WDTRIS)
Base 0x4000.0000
Offset 0x010
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WDTRIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Watchdog Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of WDTINTR.
0 WDTRIS RO 0
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Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.
Watchdog Masked Interrupt Status (WDTMIS)
Base 0x4000.0000
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WDTMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Watchdog Masked Interrupt Status
Gives the masked interrupt state (after masking) of the WDTINTR
interrupt.
0 WDTMIS RO 0
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Watchdog Timer
Register 7: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
Watchdog Test (WDTTEST)
Base 0x4000.0000
Offset 0x418
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved STALL reserved
Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:9 reserved RO 0x00
Watchdog Stall Enable
When set to 1, if the Stellaris® microcontroller is stopped with a
debugger, the watchdog timer stops counting. Once the microcontroller
is restarted, the watchdog timer resumes counting.
8 STALL R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0 reserved RO 0x00
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Register 8: Watchdog Lock (WDTLOCK), offset 0xC00
Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing
any other value to the WDTLOCK register re-enables the locked state for register writes to all the
other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value
written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns
0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)).
Watchdog Lock (WDTLOCK)
Base 0x4000.0000
Offset 0xC00
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTLock
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTLock
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Watchdog Lock
A write of the value 0x1ACC.E551 unlocks the watchdog registers for
write access. A write of any other value reapplies the lock, preventing
any register updates.
A read of this register returns the following values:
Value Description
0x0000.0001 Locked
0x0000.0000 Unlocked
31:0 WDTLock R/W 0x0000
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Watchdog Timer
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 4 (WDTPeriphID4)
Base 0x4000.0000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID4 RO 0x00 WDT Peripheral ID Register[7:0]
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Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset
0xFD4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 5 (WDTPeriphID5)
Base 0x4000.0000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID5 RO 0x00 WDT Peripheral ID Register[15:8]
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Watchdog Timer
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset
0xFD8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 6 (WDTPeriphID6)
Base 0x4000.0000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID6 RO 0x00 WDT Peripheral ID Register[23:16]
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Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset
0xFDC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 7 (WDTPeriphID7)
Base 0x4000.0000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID7 RO 0x00 WDT Peripheral ID Register[31:24]
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Watchdog Timer
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset
0xFE0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 0 (WDTPeriphID0)
Base 0x4000.0000
Offset 0xFE0
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID0 RO 0x05 Watchdog Peripheral ID Register[7:0]
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Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset
0xFE4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 1 (WDTPeriphID1)
Base 0x4000.0000
Offset 0xFE4
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID1 RO 0x18 Watchdog Peripheral ID Register[15:8]
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Watchdog Timer
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset
0xFE8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 2 (WDTPeriphID2)
Base 0x4000.0000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID2 RO 0x18 Watchdog Peripheral ID Register[23:16]
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Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset
0xFEC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 3 (WDTPeriphID3)
Base 0x4000.0000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID3 RO 0x01 Watchdog Peripheral ID Register[31:24]
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Watchdog Timer
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 0 (WDTPCellID0)
Base 0x4000.0000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID0 RO 0x0D Watchdog PrimeCell ID Register[7:0]
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Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 1 (WDTPCellID1)
Base 0x4000.0000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID1 RO 0xF0 Watchdog PrimeCell ID Register[15:8]
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Watchdog Timer
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 2 (WDTPCellID2)
Base 0x4000.0000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID2 RO 0x05 Watchdog PrimeCell ID Register[23:16]
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Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 3 (WDTPCellID3)
Base 0x4000.0000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID3 RO 0xB1 Watchdog PrimeCell ID Register[31:24]
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Watchdog Timer
12 Analog-to-Digital Converter (ADC)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The Stellaris® ADC module features 10-bit conversion resolution and supports three input channels,
plus an internal temperature sensor. The ADC module contains a programmable sequencer which
allows for the sampling of multiple analog input sources without controller intervention. Each sample
sequence provides flexible programming with fully configurable input source, trigger events, interrupt
generation, and sequence priority.
The Stellaris® ADC provides the following features:
■ Three analog input channels
■ Single-ended and differential-input configurations
■ Internal temperature sensor
■ Sample rate of 500 thousand samples/second
■ Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
■ Flexible trigger control
– Controller (software)
– Timers
– Analog Comparators
– PWM
– GPIO
■ Hardware averaging of up to 64 samples for improved accuracy
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12.1 Block Diagram
Figure 12-1. ADC Module Block Diagram
Analog-to-Digital
Converter
ADCSSFIFO0
ADCSSFIFO1
ADCSSFIFO2
ADCSSFIFO3
FIFO Block
ADCSSFSTAT0
ADCSSCTL0
ADCSSMUX0
Sample
Sequencer 0
ADCSSFSTAT1
ADCSSCTL1
ADCSSMUX1
Sample
Sequencer 1
ADCSSFSTAT2
ADCSSCTL2
ADCSSMUX2
Sample
Sequencer 2
ADCSSFSTAT3
ADCSSCTL3
ADCSSMUX3
Sample
Sequencer 3
ADCUSTAT
ADCOSTAT
ADCACTSS
Control/Status
ADCSSPRI
ADCISC
ADCRIS
ADCIM
Interrupt Control
SS0 Interrupt
Analog Inputs
SS1 Interrupt
SS2 Interrupt
SS3 Interrupt
ADCEMUX
ADCPSSI
Trigger Events
SS0
SS1
SS2
SS3
Comparator
GPIO (PB4)
Timer
PWM
Comparator
GPIO (PB4)
Timer
PWM
Comparator
GPIO (PB4)
Timer
PWM
Comparator
GPIO (PB4)
Timer
PWM
Hardware Averager
ADCSAC
12.2 Functional Description
The Stellaris® ADC collects sample data by using a programmable sequence-based approach
instead of the traditional single or double-sampling approach found on many ADC modules. Each
sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the
ADC to collect data from multiple input sources without having to be re-configured or serviced by
the controller. The programming of each sample in the sample sequence includes parameters such
as the input source and mode (differential versus single-ended input), interrupt generation on sample
completion, and the indicator for the last sample in the sequence.
12.2.1 Sample Sequencers
The sampling control and data capture is handled by the Sample Sequencers. All of the sequencers
are identical in implementation except for the number of samples that can be captured and the depth
of the FIFO. Table 12-1 on page 264 shows the maximum number of samples that each Sequencer
can capture and its corresponding FIFO depth. In this implementation, each FIFO entry is a 32-bit
word, with the lower 10 bits containing the conversion result.
Table 12-1. Samples and FIFO Depth of Sequencers
Sequencer Number of Samples Depth of FIFO
SS3 1 1
SS2 4 4
SS1 4 4
SS0 8 8
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Analog-to-Digital Converter (ADC)
For a given sample sequence, each sample is defined by two 4-bit nibbles in the ADC Sample
Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control
(ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn
nibbles select the input pin, while the ADCSSCTLn nibbles contain the sample control bits
corresponding to parameters such as temperature sensor selection, interrupt enable, end of
sequence, and differential input mode. Sample Sequencers are enabled by setting the respective
ASENn bit in the ADC Active Sample Sequencer (ADCACTSS) register, but can be configured
before being enabled.
When configuring a sample sequence, multiple uses of the same input pin within the same sequence
is allowed. In the ADCSSCTLn register, the Interrupt Enable (IE) bits can be set for any
combination of samples, allowing interrupts to be generated after every sample in the sequence if
necessary. Also, the END bit can be set at any point within a sample sequence. For example, if
Sequencer 0 is used, the END bit can be set in the nibble associated with the fifth sample, allowing
Sequencer 0 to complete execution of the sample sequence after the fifth sample.
After a sample sequence completes execution, the result data can be retrieved from the ADC
Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers
that read a single address to "pop" result data. For software debug purposes, the positions of the
FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn)
registers along with FULL and EMPTY status flags. Overflow and underflow conditions are monitored
using the ADCOSTAT and ADCUSTAT registers.
12.2.2 Module Control
Outside of the Sample Sequencers, the remainder of the control logic is responsible for tasks such
as interrupt generation, sequence prioritization, and trigger configuration.
Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider
is configured automatically by hardware when the system XTAL is selected. The automatic clock
divider configuration targets 16.667 MHz operation for all Stellaris® devices.
12.2.2.1 Interrupts
The Sample Sequencers dictate the events that cause interrupts, but they don't have control over
whether the interrupt is actually sent to the interrupt controller. The ADC module's interrupt signal
is controlled by the state of the MASK bits in the ADC Interrupt Mask (ADCIM) register. Interrupt
status can be viewed at two locations: the ADC Raw Interrupt Status (ADCRIS) register, which
shows the raw status of a Sample Sequencer's interrupt signal, and the ADC Interrupt Status and
Clear (ADCISC) register, which shows the logical AND of the ADCRIS register’s INR bit and the
ADCIM register’s MASK bits. Interrupts are cleared by writing a 1 to the corresponding IN bit in
ADCISC.
12.2.2.2 Prioritization
When sampling events (triggers) happen concurrently, they are prioritized for processing by the
values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in
the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active Sample
Sequencer units with the same priority do not provide consistent results, so software must ensure
that all active Sample Sequencer units have a unique priority value.
12.2.2.3 Sampling Events
Sample triggering for each Sample Sequencer is defined in the ADC Event Multiplexer Select
(ADCEMUX) register. The external peripheral triggering sources vary by Stellaris® family member,
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but all devices share the "Controller" and "Always" triggers. Software can initiate sampling by setting
the CH bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register.
When using the "Always" trigger, care must be taken. If a sequence's priority is too high, it is possible
to starve other lower priority sequences.
12.2.3 Hardware Sample Averaging Circuit
Higher precision results can be generated using the hardware averaging circuit, however, the
improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged
to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the
number of samples in the averaging calculation. For example, if the averaging circuit is configured
to average 16 samples, the throughput is decreased by a factor of 16.
By default the averaging circuit is off and all data from the converter passes through to the sequencer
FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC)
register (see page 281). There is a single averaging circuit and all input channels receive the same
amount of averaging whether they are single-ended or differential.
12.2.4 Analog-to-Digital Converter
The converter itself generates a 10-bit output value for selected analog input. Special analog pads
are used to minimize the distortion on the input.
12.2.5 Test Modes
There is a user-available test mode that allows for loopback operation within the digital portion of
the ADC module. This can be useful for debugging software without having to provide actual analog
stimulus. This mode is available through the ADC Test Mode Loopback (ADCTMLB) register (see
page 294).
12.2.6 Internal Temperature Sensor
The internal temperature sensor provides an analog temperature reading as well as a reference
voltage. The voltage at the output terminal SENSO is given by the following equation:
SENSO = 2.7 - ((T + 55) / 75)
This relation is shown in Figure 12-2 on page 267.
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Figure 12-2. Internal Temperature Sensor Characteristic
12.3 Initialization and Configuration
In order for the ADC module to be used, the PLL must be enabled and using a supported crystal
frequency (see the RCC register). Using unsupported frequencies can cause faulty operation in the
ADC module.
12.3.1 Module Initialization
Initialization of the ADC module is a simple process with very few steps. The main steps include
enabling the clock to the ADC and reconfiguring the Sample Sequencer priorities (if needed).
The initialization sequence for the ADC is as follows:
1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC1 register (see page 100).
2. If required by the application, reconfigure the Sample Sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority, and Sample
Sequencer 3 as the lowest priority.
12.3.2 Sample Sequencer Configuration
Configuration of the Sample Sequencers is slightly more complex than the module initialization
since each sample sequence is completely programmable.
The configuration for each Sample Sequencer should be as follows:
1. Ensure that the Sample Sequencer is disabled by writing a 0 to the corresponding ASEN bit in
the ADCACTSS register. Programming of the Sample Sequencers is allowed without having
them enabled. Disabling the Sequencer during programming prevents erroneous execution if
a trigger event were to occur during the configuration process.
2. Configure the trigger event for the Sample Sequencer in the ADCEMUX register.
3. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn register.
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4. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register.
6. Enable the Sample Sequencer logic by writing a 1 to the corresponding ASEN bit in the
ADCACTSS register.
12.4 Register Map
Table 12-2 on page 268 lists the ADC registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the ADC base address of 0x4003.8000.
Table 12-2. ADC Register Map
See
Offset Name Type Reset Description page
0x000 ADCACTSS R/W 0x0000.0000 ADC Active Sample Sequencer 270
0x004 ADCRIS RO 0x0000.0000 ADC Raw Interrupt Status 271
0x008 ADCIM R/W 0x0000.0000 ADC Interrupt Mask 272
0x00C ADCISC R/W1C 0x0000.0000 ADC Interrupt Status and Clear 273
0x010 ADCOSTAT R/W1C 0x0000.0000 ADC Overflow Status 274
0x014 ADCEMUX R/W 0x0000.0000 ADC Event Multiplexer Select 275
0x018 ADCUSTAT R/W1C 0x0000.0000 ADC Underflow Status 278
0x020 ADCSSPRI R/W 0x0000.3210 ADC Sample Sequencer Priority 279
0x028 ADCPSSI WO - ADC Processor Sample Sequence Initiate 280
0x030 ADCSAC R/W 0x0000.0000 ADC Sample Averaging Control 281
0x040 ADCSSMUX0 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 0 282
0x044 ADCSSCTL0 R/W 0x0000.0000 ADC Sample Sequence Control 0 284
0x048 ADCSSFIFO0 RO 0x0000.0000 ADC Sample Sequence Result FIFO 0 287
0x04C ADCSSFSTAT0 RO 0x0000.0100 ADC Sample Sequence FIFO 0 Status 288
0x060 ADCSSMUX1 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 1 289
0x064 ADCSSCTL1 R/W 0x0000.0000 ADC Sample Sequence Control 1 290
0x068 ADCSSFIFO1 RO 0x0000.0000 ADC Sample Sequence Result FIFO 1 287
0x06C ADCSSFSTAT1 RO 0x0000.0100 ADC Sample Sequence FIFO 1 Status 288
0x080 ADCSSMUX2 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 2 289
0x084 ADCSSCTL2 R/W 0x0000.0000 ADC Sample Sequence Control 2 290
0x088 ADCSSFIFO2 RO 0x0000.0000 ADC Sample Sequence Result FIFO 2 287
0x08C ADCSSFSTAT2 RO 0x0000.0100 ADC Sample Sequence FIFO 2 Status 288
0x0A0 ADCSSMUX3 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 3 292
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Analog-to-Digital Converter (ADC)
See
Offset Name Type Reset Description page
0x0A4 ADCSSCTL3 R/W 0x0000.0002 ADC Sample Sequence Control 3 293
0x0A8 ADCSSFIFO3 RO 0x0000.0000 ADC Sample Sequence Result FIFO 3 287
0x0AC ADCSSFSTAT3 RO 0x0000.0100 ADC Sample Sequence FIFO 3 Status 288
0x100 ADCTMLB R/W 0x0000.0000 ADC Test Mode Loopback 294
12.5 Register Descriptions
The remainder of this section lists and describes the ADC registers, in numerical order by address
offset.
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Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000
This register controls the activation of the Sample Sequencers. Each Sample Sequencer can be
enabled/disabled independently.
ADC Active Sample Sequencer (ADCACTSS)
Base 0x4003.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ASEN3 ASEN2 ASEN1 ASEN0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
ADC SS3 Enable
Specifies whether Sample Sequencer 3 is enabled. If set, the sample
sequence logic for Sequencer 3 is active. Otherwise, the Sequencer is
inactive.
3 ASEN3 R/W 0
ADC SS2 Enable
Specifies whether Sample Sequencer 2 is enabled. If set, the sample
sequence logic for Sequencer 2 is active. Otherwise, the Sequencer is
inactive.
2 ASEN2 R/W 0
ADC SS1 Enable
Specifies whether Sample Sequencer 1 is enabled. If set, the sample
sequence logic for Sequencer 1 is active. Otherwise, the Sequencer is
inactive.
1 ASEN1 R/W 0
ADC SS0 Enable
Specifies whether Sample Sequencer 0 is enabled. If set, the sample
sequence logic for Sequencer 0 is active. Otherwise, the Sequencer is
inactive.
0 ASEN0 R/W 0
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Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each Sample Sequencer. These bits
may be polled by software to look for interrupt conditions without having to generate controller
interrupts.
ADC Raw Interrupt Status (ADCRIS)
Base 0x4003.8000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved INR3 INR2 INR1 INR0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SS3 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL3 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN3 bit.
3 INR3 RO 0
SS2 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL2 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN2 bit.
2 INR2 RO 0
SS1 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL1 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN1 bit.
1 INR1 RO 0
SS0 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL0 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN0 bit.
0 INR0 RO 0
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Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the Sample Sequencer raw interrupt signals are promoted to controller
interrupts. The raw interrupt signal for each Sample Sequencer can be masked independently.
ADC Interrupt Mask (ADCIM)
Base 0x4003.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MASK3 MASK2 MASK1 MASK0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SS3 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 3
(ADCRIS register INR3 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
3 MASK3 R/W 0
SS2 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 2
(ADCRIS register INR2 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
2 MASK2 R/W 0
SS1 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 1
(ADCRIS register INR1 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
1 MASK1 R/W 0
SS0 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 0
(ADCRIS register INR0 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
0 MASK0 R/W 0
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Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C
This register provides the mechanism for clearing interrupt conditions, and shows the status of
controller interrupts generated by the Sample Sequencers. When read, each bit field is the logical
AND of the respective INR and MASK bits. Interrupts are cleared by writing a 1 to the corresponding
bit position. If software is polling the ADCRIS instead of generating interrupts, the INR bits are still
cleared via the ADCISC register, even if the IN bit is not set.
ADC Interrupt Status and Clear (ADCISC)
Base 0x4003.8000
Offset 0x00C
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN3 IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SS3 Interrupt Status and Clear
This bit is set by hardware when the MASK3 and INR3 bits are both 1,
providing a level-based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR3 bit.
3 IN3 R/W1C 0
SS2 Interrupt Status and Clear
This bit is set by hardware when the MASK2 and INR2 bits are both 1,
providing a level based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR2 bit.
2 IN2 R/W1C 0
SS1 Interrupt Status and Clear
This bit is set by hardware when the MASK1 and INR1 bits are both 1,
providing a level based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR1 bit.
1 IN1 R/W1C 0
SS0 Interrupt Status and Clear
This bit is set by hardware when the MASK0 and INR0 bits are both 1,
providing a level based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR0 bit.
0 IN0 R/W1C 0
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Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010
This register indicates overflow conditions in the Sample Sequencer FIFOs. Once the overflow
condition has been handled by software, the condition can be cleared by writing a 1 to the
corresponding bit position.
ADC Overflow Status (ADCOSTAT)
Base 0x4003.8000
Offset 0x010
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OV3 OV2 OV1 OV0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SS3 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 3 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
3 OV3 R/W1C 0
SS2 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 2 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
2 OV2 R/W1C 0
SS1 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 1 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
1 OV1 R/W1C 0
SS0 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 0 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
0 OV0 R/W1C 0
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Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014
The ADCEMUX selects the event (trigger) that initiates sampling for each Sample Sequencer. Each
Sample Sequencer can be configured with a unique trigger source.
ADC Event Multiplexer Select (ADCEMUX)
Base 0x4003.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM3 EM2 EM1 EM0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
SS3 Trigger Select
This field selects the trigger source for Sample Sequencer 3.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
0x6 PWM0
0x7 PWM1
0x8 PWM2
0x9-0xE reserved
0xF Always (continuously sample)
15:12 EM3 R/W 0x00
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Bit/Field Name Type Reset Description
SS2 Trigger Select
This field selects the trigger source for Sample Sequencer 2.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
0x6 PWM0
0x7 PWM1
0x8 PWM2
0x9-0xE reserved
0xF Always (continuously sample)
11:8 EM2 R/W 0x00
SS1 Trigger Select
This field selects the trigger source for Sample Sequencer 1.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
0x6 PWM0
0x7 PWM1
0x8 PWM2
0x9-0xE reserved
0xF Always (continuously sample)
7:4 EM1 R/W 0x00
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Bit/Field Name Type Reset Description
SS0 Trigger Select
This field selects the trigger source for Sample Sequencer 0.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
0x6 PWM0
0x7 PWM1
0x8 PWM2
0x9-0xE reserved
0xF Always (continuously sample)
3:0 EM0 R/W 0x00
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Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018
This register indicates underflow conditions in the Sample Sequencer FIFOs. The corresponding
underflow condition can be cleared by writing a 1 to the relevant bit position.
ADC Underflow Status (ADCUSTAT)
Base 0x4003.8000
Offset 0x018
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved UV3 UV2 UV1 UV0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SS3 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 3 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
3 UV3 R/W1C 0
SS2 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 2 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
2 UV2 R/W1C 0
SS1 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 1 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
1 UV1 R/W1C 0
SS0 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 0 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
0 UV0 R/W1C 0
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Analog-to-Digital Converter (ADC)
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020
This register sets the priority for each of the Sample Sequencers. Out of reset, Sequencer 0 has
the highest priority, and sample sequence 3 has the lowest priority. When reconfiguring sequence
priorities, each sequence must have a unique priority or the ADC behavior is inconsistent.
ADC Sample Sequencer Priority (ADCSSPRI)
Base 0x4003.8000
Offset 0x020
Type R/W, reset 0x0000.3210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SS3 reserved SS2 reserved SS1 reserved SS0
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x00
SS3 Priority
The SS3 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 3. A priority encoding of 0 is highest
and 3 is lowest. The priorities assigned to the Sequencers must be
uniquely mapped. ADC behavior is not consistent if two or more fields
are equal.
13:12 SS3 R/W 0x3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0x0
SS2 Priority
The SS2 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 2.
9:8 SS2 R/W 0x2
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0x0
SS1 Priority
The SS1 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 1.
5:4 SS1 R/W 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0x0
SS0 Priority
The SS0 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 0.
1:0 SS0 R/W 0x0
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Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028
This register provides a mechanism for application software to initiate sampling in the Sample
Sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.
ADC Processor Sample Sequence Initiate (ADCPSSI)
Base 0x4003.8000
Offset 0x028
Type WO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SS3 SS2 SS1 SS0
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved WO -
SS3 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 3, assuming the Sequencer is enabled in the ADCACTSS
register.
3 SS3 WO -
SS2 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 2, assuming the Sequencer is enabled in the ADCACTSS
register.
2 SS2 WO -
SS1 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 1, assuming the Sequencer is enabled in the ADCACTSS
register.
1 SS1 WO -
SS0 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 0, assuming the Sequencer is enabled in the ADCACTSS
register.
0 SS0 WO -
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Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030
This register controls the amount of hardware averaging applied to conversion results. The final
conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified
ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6,
then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An
AVG = 7 provides unpredictable results.
ADC Sample Averaging Control (ADCSAC)
Base 0x4003.8000
Offset 0x030
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved AVG
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Hardware Averaging Control
Specifies the amount of hardware averaging that will be applied to ADC
samples. The AVG field can be any value between 0 and 6. Entering a
value of 7 creates unpredictable results.
Value Description
0x0 No hardware oversampling
0x1 2x hardware oversampling
0x2 4x hardware oversampling
0x3 8x hardware oversampling
0x4 16x hardware oversampling
0x5 32x hardware oversampling
0x6 64x hardware oversampling
0x7 Reserved
2:0 AVG R/W 0x0
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Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0),
offset 0x040
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 0.
This register is 32-bits wide and contains information for eight possible samples.
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0)
Base 0x4003.8000
Offset 0x040
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved MUX7 reserved MUX6 reserved MUX5 reserved MUX4
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:30 reserved RO 0
8th Sample Input Select
The MUX7 field is used during the eighth sample of a sequence executed
with the Sample Sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion. The value set here indicates
the corresponding pin, for example, a value of 1 indicates the input is
ADC1.
29:28 MUX7 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:26 reserved RO 0
7th Sample Input Select
The MUX6 field is used during the seventh sample of a sequence
executed with the Sample Sequencer and specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
25:24 MUX6 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:22 reserved RO 0
6th Sample Input Select
The MUX5 field is used during the sixth sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
21:20 MUX5 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:18 reserved RO 0
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Bit/Field Name Type Reset Description
5th Sample Input Select
The MUX4 field is used during the fifth sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
17:16 MUX4 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:14 reserved RO 0
4th Sample Input Select
The MUX3 field is used during the fourth sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
13:12 MUX3 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0
3rd Sample Input Select
The MUX2 field is used during the third sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
9:8 MUX2 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0
2nd Sample Input Select
The MUX1 field is used during the second sample of a sequence
executed with the Sample Sequencer and specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
5:4 MUX1 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
1st Sample Input Select
The MUX0 field is used during the first sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
1:0 MUX0 R/W 0
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Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 0. When configuring a sample sequence, the END bit must be set at some point,
whether it be after the first sample, last sample, or any sample in between.
This register is 32-bits wide and contains information for eight possible samples.
ADC Sample Sequence Control 0 (ADCSSCTL0)
Base 0x4003.8000
Offset 0x044
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
8th Sample Temp Sensor Select
The TS7 bit is used during the eighth sample of the sample sequence
and specifies the input source of the sample. If set, the temperature
sensor is read. Otherwise, the input pin specified by the ADCSSMUX
register is read.
31 TS7 R/W 0
8th Sample Interrupt Enable
The IE7 bit is used during the eighth sample of the sample sequence
and specifies whether the raw interrupt signal (INR0 bit) is asserted at
the end of the sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to a controller-level interrupt.
When this bit is set, the raw interrupt is asserted, otherwise it is not. It
is legal to have multiple samples within a sequence generate interrupts.
30 IE7 R/W 0
8th Sample is End of Sequence
The END7 bit indicates that this is the last sample of the sequence. It is
possible to end the sequence on any sample position. Samples defined
after the sample containing a set END are not requested for conversion
even though the fields may be non-zero. It is required that software write
the END bit somewhere within the sequence. (Sample Sequencer 3,
which only has a single sample in the sequence, is hardwired to have
the END0 bit set.)
Setting this bit indicates that this sample is the last in the sequence.
29 END7 R/W 0
8th Sample Diff Input Select
The D7 bit indicates that the analog input is to be differentially sampled.
The corresponding ADCSSMUXx nibble must be set to the pair number
"i", where the paired inputs are "2i and 2i+1". The temperature sensor
does not have a differential option. When set, the analog inputs are
differentially sampled.
28 D7 R/W 0
7th Sample Temp Sensor Select
Same definition as TS7 but used during the seventh sample.
27 TS6 R/W 0
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Bit/Field Name Type Reset Description
7th Sample Interrupt Enable
Same definition as IE7 but used during the seventh sample.
26 IE6 R/W 0
7th Sample is End of Sequence
Same definition as END7 but used during the seventh sample.
25 END6 R/W 0
7th Sample Diff Input Select
Same definition as D7 but used during the seventh sample.
24 D6 R/W 0
6th Sample Temp Sensor Select
Same definition as TS7 but used during the sixth sample.
23 TS5 R/W 0
6th Sample Interrupt Enable
Same definition as IE7 but used during the sixth sample.
22 IE5 R/W 0
6th Sample is End of Sequence
Same definition as END7 but used during the sixth sample.
21 END5 R/W 0
6th Sample Diff Input Select
Same definition as D7 but used during the sixth sample.
20 D5 R/W 0
5th Sample Temp Sensor Select
Same definition as TS7 but used during the fifth sample.
19 TS4 R/W 0
5th Sample Interrupt Enable
Same definition as IE7 but used during the fifth sample.
18 IE4 R/W 0
5th Sample is End of Sequence
Same definition as END7 but used during the fifth sample.
17 END4 R/W 0
5th Sample Diff Input Select
Same definition as D7 but used during the fifth sample.
16 D4 R/W 0
4th Sample Temp Sensor Select
Same definition as TS7 but used during the fourth sample.
15 TS3 R/W 0
4th Sample Interrupt Enable
Same definition as IE7 but used during the fourth sample.
14 IE3 R/W 0
4th Sample is End of Sequence
Same definition as END7 but used during the fourth sample.
13 END3 R/W 0
4th Sample Diff Input Select
Same definition as D7 but used during the fourth sample.
12 D3 R/W 0
3rd Sample Temp Sensor Select
Same definition as TS7 but used during the third sample.
11 TS2 R/W 0
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Bit/Field Name Type Reset Description
3rd Sample Interrupt Enable
Same definition as IE7 but used during the third sample.
10 IE2 R/W 0
3rd Sample is End of Sequence
Same definition as END7 but used during the third sample.
9 END2 R/W 0
3rd Sample Diff Input Select
Same definition as D7 but used during the third sample.
8 D2 R/W 0
2nd Sample Temp Sensor Select
Same definition as TS7 but used during the second sample.
7 TS1 R/W 0
2nd Sample Interrupt Enable
Same definition as IE7 but used during the second sample.
6 IE1 R/W 0
2nd Sample is End of Sequence
Same definition as END7 but used during the second sample.
5 END1 R/W 0
2nd Sample Diff Input Select
Same definition as D7 but used during the second sample.
4 D1 R/W 0
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
3 TS0 R/W 0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
2 IE0 R/W 0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
1 END0 R/W 0
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0 D0 R/W 0
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Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset
0x0A8
This register contains the conversion results for samples collected with the Sample Sequencer (the
ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1,
ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return
conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the
FIFO is not properly handled by software, overflow and underflow conditions are registered in the
ADCOSTAT and ADCUSTAT registers.
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0)
Base 0x4003.8000
Offset 0x048
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0x00
9:0 DATA RO 0x00 Conversion Result Data
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Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset
0x04C
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset
0x06C
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset
0x08C
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset
0x0AC
This register provides a window into the Sample Sequencer, providing full/empty status information
as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty
FIFO. The ADCSSFSTAT0 register provides status on FIF0, ADCSSFSTAT1 on FIFO1,
ADCSSFSTAT2 on FIFO2, and ADCSSFSTAT3 on FIFO3.
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0)
Base 0x4003.8000
Offset 0x04C
Type RO, reset 0x0000.0100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved FULL reserved EMPTY HPTR TPTR
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:13 reserved RO 0x00
FIFO Full
When set, indicates that the FIFO is currently full.
12 FULL RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:9 reserved RO 0x00
FIFO Empty
When set, indicates that the FIFO is currently empty.
8 EMPTY RO 1
FIFO Head Pointer
This field contains the current "head" pointer index for the FIFO, that is,
the next entry to be written.
7:4 HPTR RO 0x00
FIFO Tail Pointer
This field contains the current "tail" pointer index for the FIFO, that is,
the next entry to be read.
3:0 TPTR RO 0x00
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Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1),
offset 0x060
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2),
offset 0x080
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 1 or 2. These registers are 16-bits wide and contain information for four possible
samples. See the ADCSSMUX0 register on page 282 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1)
Base 0x4003.8000
Offset 0x060
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x00
13:12 MUX3 R/W 0 4th Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0
9:8 MUX2 R/W 0 3rd Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0
5:4 MUX1 R/W 0 2nd Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
1:0 MUX0 R/W 0 1st Sample Input Select
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Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084
These registers contain the configuration information for each sample for a sequence executed with
Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set at some
point, whether it be after the first sample, last sample, or any sample in between. This register is
16-bits wide and contains information for four possible samples. See the ADCSSCTL0 register on
page 284 for detailed bit descriptions.
ADC Sample Sequence Control 1 (ADCSSCTL1)
Base 0x4003.8000
Offset 0x064
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
4th Sample Temp Sensor Select
Same definition as TS7 but used during the fourth sample.
15 TS3 R/W 0
4th Sample Interrupt Enable
Same definition as IE7 but used during the fourth sample.
14 IE3 R/W 0
4th Sample is End of Sequence
Same definition as END7 but used during the fourth sample.
13 END3 R/W 0
4th Sample Diff Input Select
Same definition as D7 but used during the fourth sample.
12 D3 R/W 0
3rd Sample Temp Sensor Select
Same definition as TS7 but used during the third sample.
11 TS2 R/W 0
3rd Sample Interrupt Enable
Same definition as IE7 but used during the third sample.
10 IE2 R/W 0
3rd Sample is End of Sequence
Same definition as END7 but used during the third sample.
9 END2 R/W 0
3rd Sample Diff Input Select
Same definition as D7 but used during the third sample.
8 D2 R/W 0
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Bit/Field Name Type Reset Description
2nd Sample Temp Sensor Select
Same definition as TS7 but used during the second sample.
7 TS1 R/W 0
2nd Sample Interrupt Enable
Same definition as IE7 but used during the second sample.
6 IE1 R/W 0
2nd Sample is End of Sequence
Same definition as END7 but used during the second sample.
5 END1 R/W 0
2nd Sample Diff Input Select
Same definition as D7 but used during the second sample.
4 D1 R/W 0
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
3 TS0 R/W 0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
2 IE0 R/W 0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
1 END0 R/W 0
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0 D0 R/W 0
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Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3),
offset 0x0A0
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 3. This register is 4-bits wide and contains information for one possible sample.
See the ADCSSMUX0 register on page 282 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3)
Base 0x4003.8000
Offset 0x0A0
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MUX0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
1:0 MUX0 R/W 0 1st Sample Input Select
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Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 3. The END bit is always set since there is only one sample in this sequencer.
This register is 4-bits wide and contains information for one possible sample. See the ADCSSCTL0
register on page 284 for detailed bit descriptions.
ADC Sample Sequence Control 3 (ADCSSCTL3)
Base 0x4003.8000
Offset 0x0A4
Type R/W, reset 0x0000.0002
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TS0 IE0 END0 D0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
3 TS0 R/W 0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
2 IE0 R/W 0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
1 END0 R/W 1
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0 D0 R/W 0
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Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100
This register provides loopback operation within the digital logic of the ADC, which can be useful in
debugging software without having to provide actual analog stimulus. This test mode is entered by
writing a value of 0x0000.0001 to this register. When data is read from the FIFO in loopback mode,
the read-only portion of this register is returned.
Read-Only Register
ADC Test Mode Loopback (ADCTMLB)
Base 0x4003.8000
Offset 0x100
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CNT CONT DIFF TS MUX
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0x00
Continuous Sample Counter
Continuous sample counter that is initialized to 0 and counts each
sample as it processed. This helps provide a unique value for the data
received.
9:6 CNT RO 0x0
Continuation Sample Indicator
When set, indicates that this is a continuation sample. For example, if
two sequencers were to run back-to-back, this indicates that the
controller kept continuously sampling at full rate.
5 CONT RO 0
Differential Sample Indicator
When set, indicates that this is a differential sample.
4 DIFF RO 0
Temp Sensor Sample Indicator
When set, indicates that this is a temperature sensor sample.
3 TS RO 0
Analog Input Indicator
Indicates which analog input is to be sampled.
2:0 MUX RO 0x0
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Write-Only Register
ADC Test Mode Loopback (ADCTMLB)
Base 0x4003.8000
Offset 0x100
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved LB
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Loopback Mode Enable
When set, forces a loopback within the digital block to provide information
on input and unique numbering.
The 10-bit loopback data is defined as shown in the read for bits 9:0
above.
0 LB WO 0
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13 Universal Asynchronous Receivers/Transmitters
(UARTs)
The Stellaris® Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable,
16C550-type serial interface characteristics. The LM3S6952 controller is equipped with three UART
modules.
Each UART has the following features:
■ Separate transmit and receive FIFOs
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Programmable baud-rate generator allowing rates up to 3.125 Mbps
■ Standard asynchronous communication bits for start, stop, and parity
■ False start bit detection
■ Line-break generation and detection
■ Fully programmable serial interface characteristics:
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing:
– Programmable use of IrDA Serial InfraRed (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
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13.1 Block Diagram
Figure 13-1. UART Module Block Diagram
Receiver
Transmitter
System Clock
Control / Status
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
UARTILPR
Interrupt Control
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
Baud Rate
Generator
UARTIBRD
UARTFBRD
Identification
Registers
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UART PeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
UARTDR
TXFIFO
16x8
...
RXFIFO
16x8
...
Interrupt
UnTx
UnRx
13.2 Functional Description
Each Stellaris® UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 315). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected
to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
13.2.1 Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
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bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 13-2 on page 298 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 13-2. UART Character Frame
1
0 5-8 data bits
LSB MSB
Parity bit
if enabled
1-2
stop bits
UnTX
n
Start
13.2.2 Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 311) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 312). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.):
BRD = BRDI + BRDF = SysClk / (16 * Baud Rate)
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register)
can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and
adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as
Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error
detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 313), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
■ UARTIBRD write, UARTFBRD write, and UARTLCRH write
■ UARTFBRD write, UARTIBRD write, and UARTLCRH write
■ UARTIBRD write and UARTLCRH write
■ UARTFBRD write and UARTLCRH write
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13.2.3 Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 308) is asserted as soon as
data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has
been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 (described in “Transmit/Receive Logic” on page 297).
The start bit is valid if UnRx is still low on the eighth cycle of Baud16, otherwise a false start bit is
detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR)
register (see page 306). If the start bit was valid, successive data bits are sampled on every 16th
cycle of Baud16 (that is, one bit period later) according to the programmed length of the data
characters. The parity bit is then checked if parity mode was enabled. Data length and parity are
defined in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When
a full word is received, the data is stored in the receive FIFO, with any error bits associated with
that word.
13.2.4 Serial IR (SIR)
The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream, and half-duplex
serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to
provide a digital encoded output, and decoded input to the UART. The UART signal pins can be
connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block
has two modes of operation:
■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the
selected baud rate bit period on the output pin, while logic one levels are transmitted as a static
LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light
for each zero. On the reception side, the incoming light pulses energize the photo transistor base
of the receiver, pulling its output LOW. This drives the UART input pin LOW.
■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the
period of the internally generated IrLPBaud16 signal (1.63 μs, assuming a nominal 1.8432 MHz
frequency) by changing the appropriate bit in the UARTCR register.
Figure 13-3 on page 300 shows the UART transmit and receive signals, with and without IrDA
modulation.
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Figure 13-3. IrDA Data Modulation
0 1 0 1 0 0 1 1 0 1
Data bits
0 1 0 1 0 0 1 1 0 1
Start Data bits
bit
Start Stop
Bit period Bit period
3
16
UnTx
UnTx with IrDA
UnRx with IrDA
UnRx
Stop
bit
In both normal and low-power IrDA modes:
■ During transmission, the UART data bit is used as the base for encoding
■ During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay
between transmission and reception. This delay must be generated by software because it is not
automatically supported by the UART. The delay is required because the infrared receiver electronics
might become biased, or even saturated from the optical power coupled from the adjacent transmitter
LED. This delay is known as latency, or receiver setup time.
13.2.5 FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 304). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data
in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 313).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 308) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the
UARTRSR register shows overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 317). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For
example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt
after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the
½ mark.
13.2.6 Interrupts
The UART can generate interrupts when the following conditions are observed:
■ Overrun Error
■ Break Error
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■ Parity Error
■ Framing Error
■ Receive Timeout
■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)
■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 322).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM ) register (see page 319) by setting the corresponding IM bit to 1. If interrupts are
not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 321).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 323).
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data
is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO
becomes empty through reading all the data (or by reading the holding register), or when a 1 is
written to the corresponding bit in the UARTICR register.
13.2.7 Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 315). In loopback mode,
data transmitted on UnTx is received on the UnRx input.
13.2.8 IrDA SIR block
The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the
SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR
transceiver.
The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same
time. Transmission must be stopped before data can be received. The IrDA SIR physical layer
specifies a minimum 10-ms delay between transmission and reception.
13.3 Initialization and Configuration
To use the UARTs, the peripheral clock must be enabled by setting the UART0, UART1, or UART2
bits in the RCGC1 register.
This section discusses the steps that are required for using a UART module. For this example, the
system clock is assumed to be 20 MHz and the desired UART configuration is:
■ 115200 baud rate
■ Data length of 8 bits
■ One stop bit
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■ No parity
■ FIFOs disabled
■ No interrupts
The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the
UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the
equation described in “Baud-Rate Generation” on page 298, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 311) should be set to 10.
The value to be loaded into the UARTFBRD register (see page 312) is calculated by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Enable the UART by setting the UARTEN bit in the UARTCTL register.
13.4 Register Map
Table 13-1 on page 302 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■ UART0: 0x4000.C000
■ UART1: 0x4000.D000
■ UART2: 0x4000.E000
Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 315)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 13-1. UART Register Map
See
Offset Name Type Reset Description page
0x000 UARTDR R/W 0x0000.0000 UART Data 304
0x004 UARTRSR/UARTECR R/W 0x0000.0000 UART Receive Status/Error Clear 306
0x018 UARTFR RO 0x0000.0090 UART Flag 308
0x020 UARTILPR R/W 0x0000.0000 UART IrDA Low-Power Register 310
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See
Offset Name Type Reset Description page
0x024 UARTIBRD R/W 0x0000.0000 UART Integer Baud-Rate Divisor 311
0x028 UARTFBRD R/W 0x0000.0000 UART Fractional Baud-Rate Divisor 312
0x02C UARTLCRH R/W 0x0000.0000 UART Line Control 313
0x030 UARTCTL R/W 0x0000.0300 UART Control 315
0x034 UARTIFLS R/W 0x0000.0012 UART Interrupt FIFO Level Select 317
0x038 UARTIM R/W 0x0000.0000 UART Interrupt Mask 319
0x03C UARTRIS RO 0x0000.000F UART Raw Interrupt Status 321
0x040 UARTMIS RO 0x0000.0000 UART Masked Interrupt Status 322
0x044 UARTICR W1C 0x0000.0000 UART Interrupt Clear 323
0xFD0 UARTPeriphID4 RO 0x0000.0000 UART Peripheral Identification 4 325
0xFD4 UARTPeriphID5 RO 0x0000.0000 UART Peripheral Identification 5 326
0xFD8 UARTPeriphID6 RO 0x0000.0000 UART Peripheral Identification 6 327
0xFDC UARTPeriphID7 RO 0x0000.0000 UART Peripheral Identification 7 328
0xFE0 UARTPeriphID0 RO 0x0000.0011 UART Peripheral Identification 0 329
0xFE4 UARTPeriphID1 RO 0x0000.0000 UART Peripheral Identification 1 330
0xFE8 UARTPeriphID2 RO 0x0000.0018 UART Peripheral Identification 2 331
0xFEC UARTPeriphID3 RO 0x0000.0001 UART Peripheral Identification 3 332
0xFF0 UARTPCellID0 RO 0x0000.000D UART PrimeCell Identification 0 333
0xFF4 UARTPCellID1 RO 0x0000.00F0 UART PrimeCell Identification 1 334
0xFF8 UARTPCellID2 RO 0x0000.0005 UART PrimeCell Identification 2 335
0xFFC UARTPCellID3 RO 0x0000.00B1 UART PrimeCell Identification 3 336
13.5 Register Descriptions
The remainder of this section lists and describes the UART registers, in numerical order by address
offset.
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Register 1: UART Data (UARTDR), offset 0x000
This register is the data register (the interface to the FIFOs).
When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs
are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.
UART Data (UARTDR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OE BE PE FE DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0
UART Overrun Error
The OE values are defined as follows:
Value Description
0 There has been no data loss due to a FIFO overrun.
New data was received when the FIFO was full, resulting in
data loss.
1
11 OE RO 0
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the receive data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state) and the next valid start bit is received.
10 BE RO 0
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Bit/Field Name Type Reset Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
9 PE RO 0
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
8 FE RO 0
Data Transmitted or Received
When written, the data that is to be transmitted via the UART. When
read, the data that was received by the UART.
7:0 DATA R/W 0
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Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset
0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared to 0 on reset.
Read-Only Receive Status (UARTRSR) Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OE BE PE FE
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0
UART Overrun Error
When this bit is set to 1, data is received and the FIFO is already full.
This bit is cleared to 0 by a write to UARTECR.
The FIFO contents remain valid since no further data is written when
the FIFO is full, only the contents of the shift register are overwritten.
The CPU must now read the data in order to empty the FIFO.
3 OE RO 0
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the received data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
2 BE RO 0
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Bit/Field Name Type Reset Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
1 PE RO 0
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
0 FE RO 0
Write-Only Error Clear (UARTECR) Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x004
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved WO 0
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
7:0 DATA WO 0
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Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.
UART Flag (UARTFR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x018
Type RO, reset 0x0000.0090
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXFE RXFF TXFF RXFE BUSY reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding
register is empty.
If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO
is empty.
7 TXFE RO 1
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is full.
If the FIFO is enabled, this bit is set when the receive FIFO is full.
6 RXFF RO 0
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding register
is full.
If the FIFO is enabled, this bit is set when the transmit FIFO is full.
5 TXFF RO 0
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Bit/Field Name Type Reset Description
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is empty.
If the FIFO is enabled, this bit is set when the receive FIFO is empty.
4 RXFE RO 1
UART Busy
When this bit is 1, the UART is busy transmitting data. This bit remains
set until the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
3 BUSY RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor
value used to generate the IrLPBaud16 signal by dividing down the system clock (SysClk). All the
bits are cleared to 0 when reset.
The IrLPBaud16 internal signal is generated by dividing down the UARTCLK signal according to
the low-power divisor value written to UARTILPR. The low-power divisor value is calculated as
follows:
ILPDVSR = SysClk / FIrLPBaud16
where FIrLPBaud16 is nominally 1.8432 MHz.
IrLPBaud16 is an internal signal used for SIR pulse generation when low-power mode is used.
You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power
pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency
of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that
pulses greater than 1.4 μs are accepted as valid pulses.
Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
UART IrDA Low-Power Register (UARTILPR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ILPDVSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
IrDA Low-Power Divisor
This is an 8-bit low-power divisor value.
7:0 ILPDVSR R/W 0x00
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Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 298
for configuration details.
UART Integer Baud-Rate Divisor (UARTIBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x024
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVINT
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0
15:0 DIVINT R/W 0x0000 Integer Baud-Rate Divisor
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Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 298
for configuration details.
UART Fractional Baud-Rate Divisor (UARTFBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x028
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DIVFRAC
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
5:0 DIVFRAC R/W 0x000 Fractional Baud-Rate Divisor
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Register 7: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
UART Line Control (UARTLCRH)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x02C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SPS WLEN FEN STP2 EPS PEN BRK
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
7 SPS R/W 0
UART Word Length
The bits indicate the number of data bits transmitted or received in a
frame as follows:
Value Description
0x3 8 bits
0x2 7 bits
0x1 6 bits
0x0 5 bits (default)
6:5 WLEN R/W 0
UART Enable FIFOs
If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO
mode).
When cleared to 0, FIFOs are disabled (Character mode). The FIFOs
become 1-byte-deep holding registers.
4 FEN R/W 0
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Bit/Field Name Type Reset Description
UART Two Stop Bits Select
If this bit is set to 1, two stop bits are transmitted at the end of a frame.
The receive logic does not check for two stop bits being received.
3 STP2 R/W 0
UART Even Parity Select
If this bit is set to 1, even parity generation and checking is performed
during transmission and reception, which checks for an even number
of 1s in data and parity bits.
When cleared to 0, then odd parity is performed, which checks for an
odd number of 1s.
This bit has no effect when parity is disabled by the PEN bit.
2 EPS R/W 0
UART Parity Enable
If this bit is set to 1, parity checking and generation is enabled; otherwise,
parity is disabled and no parity bit is added to the data frame.
1 PEN R/W 0
UART Send Break
If this bit is set to 1, a Low level is continually output on the UnTX output,
after completing transmission of the current character. For the proper
execution of the break command, the software must set this bit for at
least two frames (character periods). For normal use, this bit must be
cleared to 0.
0 BRK R/W 0
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are written.
If the UART is disabled during a transmit or receive operation, the current transaction is completed
prior to the UART stopping.
UART Control (UARTCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x030
Type R/W, reset 0x0000.0300
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RXE TXE LBE reserved SIRLP SIREN UARTEN
Type RO RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0
UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled. When
the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note: To enable reception, the UARTEN bit must also be set.
9 RXE R/W 1
UART Transmit Enable
If this bit is set to 1, the transmit section of the UART is enabled. When
the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note: To enable transmission, the UARTEN bit must also be set.
8 TXE R/W 1
UART Loop Back Enable
If this bit is set to 1, the UnTX path is fed through the UnRX path.
7 LBE R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:3 reserved RO 0
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Bit/Field Name Type Reset Description
UART SIR Low Power Mode
This bit selects the IrDA encoding mode. If this bit is cleared to 0,
low-level bits are transmitted as an active High pulse with a width of
3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted
with a pulse width which is 3 times the period of the IrLPBaud16 input
signal, regardless of the selected bit rate. Setting this bit uses less power,
but might reduce transmission distances. See page 310 for more
information.
2 SIRLP R/W 0
UART SIR Enable
If this bit is set to 1, the IrDA SIR block is enabled, and the UART will
transmit and receive data using SIR protocol.
1 SIREN R/W 0
UART Enable
If this bit is set to 1, the UART is enabled. When the UART is disabled
in the middle of transmission or reception, it completes the current
character before stopping.
0 UARTEN R/W 0
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Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.
UART Interrupt FIFO Level Select (UARTIFLS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x034
Type R/W, reset 0x0000.0012
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RXIFLSEL TXIFLSEL
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
Value Description
0x0 RX FIFO ≥ 1/8 full
0x1 RX FIFO ≥ ¼ full
0x2 RX FIFO ≥ ½ full (default)
0x3 RX FIFO ≥ ¾ full
0x4 RX FIFO ≥ 7/8 full
0x5-0x7 Reserved
5:3 RXIFLSEL R/W 0x2
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Bit/Field Name Type Reset Description
UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
Value Description
0x0 TX FIFO ≤ 1/8 full
0x1 TX FIFO ≤ ¼ full
0x2 TX FIFO ≤ ½ full (default)
0x3 TX FIFO ≤ ¾ full
0x4 TX FIFO ≤ 7/8 full
0x5-0x7 Reserved
2:0 TXIFLSEL R/W 0x2
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Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to
a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a
0 prevents the raw interrupt signal from being sent to the interrupt controller.
UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OEIM BEIM PEIM FEIM RTIM TXIM RXIM reserved
Type RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
UART Overrun Error Interrupt Mask
On a read, the current mask for the OEIM interrupt is returned.
Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller.
10 OEIM R/W 0
UART Break Error Interrupt Mask
On a read, the current mask for the BEIM interrupt is returned.
Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller.
9 BEIM R/W 0
UART Parity Error Interrupt Mask
On a read, the current mask for the PEIM interrupt is returned.
Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller.
8 PEIM R/W 0
UART Framing Error Interrupt Mask
On a read, the current mask for the FEIM interrupt is returned.
Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller.
7 FEIM R/W 0
UART Receive Time-Out Interrupt Mask
On a read, the current mask for the RTIM interrupt is returned.
Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller.
6 RTIM R/W 0
UART Transmit Interrupt Mask
On a read, the current mask for the TXIM interrupt is returned.
Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller.
5 TXIM R/W 0
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Bit/Field Name Type Reset Description
UART Receive Interrupt Mask
On a read, the current mask for the RXIM interrupt is returned.
Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller.
4 RXIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0x00
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Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x03C
Type RO, reset 0x0000.000F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
UART Overrun Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
10 OERIS RO 0
UART Break Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
9 BERIS RO 0
UART Parity Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
8 PERIS RO 0
UART Framing Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
7 FERIS RO 0
UART Receive Time-Out Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
6 RTRIS RO 0
UART Transmit Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
5 TXRIS RO 0
UART Receive Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
4 RXRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0xF
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Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x040
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
UART Overrun Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
10 OEMIS RO 0
UART Break Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
9 BEMIS RO 0
UART Parity Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
8 PEMIS RO 0
UART Framing Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
7 FEMIS RO 0
UART Receive Time-Out Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
6 RTMIS RO 0
UART Transmit Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
5 TXMIS RO 0
UART Receive Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
4 RXMIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0
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Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x044
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OEIC BEIC PEIC FEIC RTIC TXIC RXIC reserved
Type RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
Overrun Error Interrupt Clear
The OEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
10 OEIC W1C 0
Break Error Interrupt Clear
The BEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
9 BEIC W1C 0
Parity Error Interrupt Clear
The PEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
8 PEIC W1C 0
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Bit/Field Name Type Reset Description
Framing Error Interrupt Clear
The FEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
7 FEIC W1C 0
Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
6 RTIC W1C 0
Transmit Interrupt Clear
The TXIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
5 TXIC W1C 0
Receive Interrupt Clear
The RXIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
4 RXIC W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0x00
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 4 (UARTPeriphID4)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID4 RO 0x0000
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Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 5 (UARTPeriphID5)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID5 RO 0x0000
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Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 6 (UARTPeriphID6)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID6 RO 0x0000
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Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 7 (UARTPeriphID7)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID7 RO 0x0000
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 0 (UARTPeriphID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE0
Type RO, reset 0x0000.0011
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID0 RO 0x11
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Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 1 (UARTPeriphID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID1 RO 0x00
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Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 2 (UARTPeriphID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID2 RO 0x18
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Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 3 (UARTPeriphID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID3 RO 0x01
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 0 (UARTPCellID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
7:0 CID0 RO 0x0D
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Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 1 (UARTPCellID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
7:0 CID1 RO 0xF0
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Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 2 (UARTPCellID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
7:0 CID2 RO 0x05
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Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 3 (UARTPCellID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
7:0 CID3 RO 0xB1
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14 Synchronous Serial Interface (SSI)
The Stellaris® Synchronous Serial Interface (SSI) is a master or slave interface for synchronous
serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas
Instruments synchronous serial interfaces.
The Stellaris® SSI module has the following features:
■ Master or slave operation
■ Programmable clock bit rate and prescale
■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
14.1 Block Diagram
Figure 14-1. SSI Module Block Diagram
Transmit/
Receive
Logic
Clock
Prescaler
SSICPSR
Control / Status
SSICR0
SSICR1
SSISR
Interrupt Control
SSIIM
SSIMIS
SSIRIS
SSIICR
SSIDR
TxFIFO
8 x 16
...
RxFIFO
8 x 16
...
System Clock
SSITx
SSIRx
SSIClk
SSIFss
Interrupt
Identification Registers
SSIPCellID0 SSIPeriphID0 SSIPeriphID4
SSIPCellID1 SSIPeriphID1 SSIPeriphID5
SSIPCellID2 SSIPeriphID2 SSIPeriphID6
SSIPCellID3 SSIPeriphID3 SSIPeriphID7
14.2 Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
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internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes.
14.2.1 Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the 50-MHz input clock. The clock is first divided by
an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 356). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 349).
The frequency of the output clock SSIClk is defined by:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
Note that although the SSIClk transmit clock can theoretically be 25 MHz, the module may not be
able to operate at that speed. For master mode, the system clock must be at least two times faster
than the SSIClk. For slave mode, the system clock must be at least 12 times faster than the SSIClk.
See “Synchronous Serial Interface (SSI)” on page 543 to view SSI timing parameters.
14.2.2 FIFO Operation
14.2.2.1 Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 353), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
14.2.2.2 Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
14.2.3 Interrupts
The SSI can generate interrupts when the following conditions are observed:
■ Transmit FIFO service
■ Receive FIFO service
■ Receive FIFO time-out
■ Receive FIFO overrun
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
can only generate a single interrupt request to the controller at any given time. You can mask each
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of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask
(SSIIM) register (see page 357). Setting the appropriate mask bit to 1 enables the interrupt.
Provision of the individual outputs, as well as a combined interrupt output, allows use of either a
global interrupt service routine, or modular device drivers to handle interrupts. The transmit and
receive dynamic dataflow interrupts have been separated from the status interrupts so that data
can be read or written in response to the FIFO trigger levels. The status of the individual interrupt
sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status
(SSIMIS) registers (see page 359 and page 360, respectively).
14.2.4 Frame Formats
Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. There are three basic frame types that can be selected:
■ Texas Instruments synchronous serial
■ Freescale SPI
■ MICROWIRE
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and
latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique, which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
14.2.4.1 Texas Instruments Synchronous Serial Frame Format
Figure 14-2 on page 339 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer)
SSIClk
4 to 16 bits
SSIFss
SSITx/SSIRx MSB LSB
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In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is
pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data
is shifted onto the SSIRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSIClk after the LSB has been latched.
Figure 14-3 on page 340 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer)
MSB LSB
4 to 16 bits
SSIClk
SSIFss
SSITx/SSIRx
14.2.4.2 Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk
pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not
being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition
before the first data capture edge. When the SPH phase control bit is Low, data is captured on the
first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition.
14.2.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 14-4 on page 341 and Figure 14-5 on page 341.
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Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
4 to 16 bits
SSIClk
SSIFss
SSIRx Q
SSITx
MSB
MSB
LSB
LSB
Note: Q is undefined.
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx LSB
SSITx MSB LSB
4 to 16 bits
LSB MSB
MSB
MSB
LSB
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto
the SSIRx input line of the master. The master SSITx output pad is enabled.
One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the
master and slave data have been set, the SSIClk master clock pin goes High after one further half
SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
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14.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
14-6 on page 342, which covers both single and continuous transfers.
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1
4 to 16 bits
SSIClk
SSIFss
SSIRx
SSITx
Q
MSB
Q MSB
LSB
LSB
Note: Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After
a further one half SSIClk period, both master and slave valid data is enabled onto their respective
transmission lines. At the same time, the SSIClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned
to its idle High state one SSIClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
14.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 14-7 on page 343 and Figure 14-8 on page 343.
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Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
4 to 16 bits
SSIClk
SSIFss
SSIRx
SSITx
MSB Q
MSB LSB
LSB
Note: Q is undefined.
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSITx/SSIRx MSB LSB
4 to 16 bits
LSB MSB
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low, which causes slave data to be immediately
transferred onto the SSIRx line of the master. The master SSITx output pad is enabled.
One half period later, valid master data is transferred to the SSITx line. Now that both the master
and slave data have been set, the SSIClk master clock pin becomes Low after one further half
SSIClk period. This means that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss
line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
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14.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
14-9 on page 344, which covers both single and continuous transfers.
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1
4 to 16 bits
SSIClk
SSIFss
SSIRx
SSITx
Q Q
MSB
MSB
LSB
LSB
Note: Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled.
After a further one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until
the final bit of the last word has been captured, and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
14.2.4.7 MICROWIRE Frame Format
Figure 14-10 on page 345 shows the MICROWIRE frame format, again for a single frame. Figure
14-11 on page 346 shows the same format when back-to-back frames are transmitted.
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Figure 14-10. MICROWIRE Frame Format (Single Frame)
SSIClk
SSIFss
SSIRx MSB LSB
4 to 16 bits
output data
0
SSITx MSB LSB
8-bit control
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
full-duplex, using a master-slave message passing technique. Each serial transmission begins with
an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss
causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the
SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains
tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of
each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a
one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven
onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising
edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one
clock period after the last bit has been latched in the receive serial shifter, which causes the data
to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk
after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer.
However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs
back-to-back. The control byte of the next frame follows directly after the LSB of the received data
from the current frame. Each of the received values is transferred from the receive shifter on the
falling edge of SSIClk, after the LSB of the frame has been latched into the SSI.
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Figure 14-11. MICROWIRE Frame Format (Continuous Transfer)
8-bit control
SSIClk
SSIFss
SSIRx MSB LSB
4 to 16 bits
output data
0
SSITx LSB MSB LSB
MSB
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
Figure 14-12 on page 346 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
SSIClk
SSIFss
SSIRx
First RX data to be
sampled by SSI slave
tSetup=(2*tSSIClk)
tHold=tSSIClk
14.3 Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the clock prescale divisor by writing the SSICPSR register.
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4. Write the SSICR0 register with the following configuration:
■ Serial clock rate (SCR)
■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
■ The data size (DSS)
5. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
■ Master operation
■ Freescale SPI mode (SPO=1, SPH=1)
■ 1 Mbps bit rate
■ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is disabled.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
14.4 Register Map
Table 14-1 on page 347 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■ SSI0: 0x4000.8000
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 14-1. SSI Register Map
See
Offset Name Type Reset Description page
0x000 SSICR0 R/W 0x0000.0000 SSI Control 0 349
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See
Offset Name Type Reset Description page
0x004 SSICR1 R/W 0x0000.0000 SSI Control 1 351
0x008 SSIDR R/W 0x0000.0000 SSI Data 353
0x00C SSISR RO 0x0000.0003 SSI Status 354
0x010 SSICPSR R/W 0x0000.0000 SSI Clock Prescale 356
0x014 SSIIM R/W 0x0000.0000 SSI Interrupt Mask 357
0x018 SSIRIS RO 0x0000.0008 SSI Raw Interrupt Status 359
0x01C SSIMIS RO 0x0000.0000 SSI Masked Interrupt Status 360
0x020 SSIICR W1C 0x0000.0000 SSI Interrupt Clear 361
0xFD0 SSIPeriphID4 RO 0x0000.0000 SSI Peripheral Identification 4 362
0xFD4 SSIPeriphID5 RO 0x0000.0000 SSI Peripheral Identification 5 363
0xFD8 SSIPeriphID6 RO 0x0000.0000 SSI Peripheral Identification 6 364
0xFDC SSIPeriphID7 RO 0x0000.0000 SSI Peripheral Identification 7 365
0xFE0 SSIPeriphID0 RO 0x0000.0022 SSI Peripheral Identification 0 366
0xFE4 SSIPeriphID1 RO 0x0000.0000 SSI Peripheral Identification 1 367
0xFE8 SSIPeriphID2 RO 0x0000.0018 SSI Peripheral Identification 2 368
0xFEC SSIPeriphID3 RO 0x0000.0001 SSI Peripheral Identification 3 369
0xFF0 SSIPCellID0 RO 0x0000.000D SSI PrimeCell Identification 0 370
0xFF4 SSIPCellID1 RO 0x0000.00F0 SSI PrimeCell Identification 1 371
0xFF8 SSIPCellID2 RO 0x0000.0005 SSI PrimeCell Identification 2 372
0xFFC SSIPCellID3 RO 0x0000.00B1 SSI PrimeCell Identification 3 373
14.5 Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
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Register 1: SSI Control 0 (SSICR0), offset 0x000
SSICR0 is control register 0 and contains bit fields that control various functions within the SSI
module. Functionality such as protocol mode, clock rate, and data size are configured in this register.
SSI Control 0 (SSICR0)
SSI0 base: 0x4000.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCR SPH SPO FRF DSS
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
SSI Serial Clock Rate
The value SCR is used to generate the transmit and receive bit rate of
the SSI. The bit rate is:
BR=FSSIClk/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
15:8 SCR R/W 0x0000
SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. It has the most impact on the first bit transmitted by
either allowing or not allowing a clock transition before the first data
capture edge.
When the SPH bit is 0, data is captured on the first clock edge transition.
If SPH is 1, data is captured on the second clock edge transition.
7 SPH R/W 0
SSI Serial Clock Polarity
This bit is only applicable to the Freescale SPI Format.
When the SPO bit is 0, it produces a steady state Low value on the
SSIClk pin. If SPO is 1, a steady state High value is placed on the
SSIClk pin when data is not being transferred.
6 SPO R/W 0
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Bit/Field Name Type Reset Description
SSI Frame Format Select
The FRF values are defined as follows:
Value Frame Format
0x0 Freescale SPI Frame Format
0x1 Texas Intruments Synchronous Serial Frame Format
0x2 MICROWIRE Frame Format
0x3 Reserved
5:4 FRF R/W 0x0
SSI Data Size Select
The DSS values are defined as follows:
Value Data Size
0x0-0x2 Reserved
0x3 4-bit data
0x4 5-bit data
0x5 6-bit data
0x6 7-bit data
0x7 8-bit data
0x8 9-bit data
0x9 10-bit data
0xA 11-bit data
0xB 12-bit data
0xC 13-bit data
0xD 14-bit data
0xE 15-bit data
0xF 16-bit data
3:0 DSS R/W 0x00
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Register 2: SSI Control 1 (SSICR1), offset 0x004
SSICR1 is control register 1 and contains bit fields that control various functions within the SSI
module. Master and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SOD MS SSE LBM
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In multiple-slave
systems, it is possible for the SSI master to broadcast a message to all
slaves in the system while ensuring that only one slave drives data onto
the serial output line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD bit can be
configured so that the SSI slave does not drive the SSITx pin.
The SOD values are defined as follows:
Value Description
0 SSI can drive SSITx output in Slave Output mode.
1 SSI must not drive the SSITx output in Slave mode.
3 SOD R/W 0
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
SSI is disabled (SSE=0).
The MS values are defined as follows:
Value Description
0 Device configured as a master.
1 Device configured as a slave.
2 MS R/W 0
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Bit/Field Name Type Reset Description
SSI Synchronous Serial Port Enable
Setting this bit enables SSI operation.
The SSE values are defined as follows:
Value Description
0 SSI operation disabled.
1 SSI operation enabled.
Note: This bit must be set to 0 before any control registers
are reprogrammed.
1 SSE R/W 0
SSI Loopback Mode
Setting this bit enables Loopback Test mode.
The LBM values are defined as follows:
Value Description
0 Normal serial port operation enabled.
Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.
1
0 LBM R/W 0
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Register 3: SSI Data (SSIDR), offset 0x008
SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO
(pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI
receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed
to by the current FIFO write pointer).
When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written
to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is
loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed
bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
SSI0 base: 0x4000.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.
15:0 DATA R/W 0x0000
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Register 4: SSI Status (SSISR), offset 0x00C
SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
Offset 0x00C
Type RO, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BSY RFF RNE TNF TFE
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 reserved RO 0x00
SSI Busy Bit
The BSY values are defined as follows:
Value Description
0 SSI is idle.
SSI is currently transmitting and/or receiving a frame, or the
transmit FIFO is not empty.
1
4 BSY RO 0
SSI Receive FIFO Full
The RFF values are defined as follows:
Value Description
0 Receive FIFO is not full.
1 Receive FIFO is full.
3 RFF RO 0
SSI Receive FIFO Not Empty
The RNE values are defined as follows:
Value Description
0 Receive FIFO is empty.
1 Receive FIFO is not empty.
2 RNE RO 0
SSI Transmit FIFO Not Full
The TNF values are defined as follows:
Value Description
0 Transmit FIFO is full.
1 Transmit FIFO is not full.
1 TNF RO 1
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Bit/Field Name Type Reset Description
SSI Transmit FIFO Empty
The TFE values are defined as follows:
Value Description
0 Transmit FIFO is not empty.
1 Transmit FIFO is empty.
0 TFE R0 1
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Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
SSICPSR is the clock prescale register and specifies the division factor by which the system clock
must be internally divided before further use.
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CPSDVSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254, depending on the
frequency of SSIClk. The LSB always returns 0 on reads.
7:0 CPSDVSR R/W 0x00
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Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding
mask.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXIM RXIM RTIM RORIM
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SSI Transmit FIFO Interrupt Mask
The TXIM values are defined as follows:
Value Description
0 TX FIFO half-full or less condition interrupt is masked.
1 TX FIFO half-full or less condition interrupt is not masked.
3 TXIM R/W 0
SSI Receive FIFO Interrupt Mask
The RXIM values are defined as follows:
Value Description
0 RX FIFO half-full or more condition interrupt is masked.
1 RX FIFO half-full or more condition interrupt is not masked.
2 RXIM R/W 0
SSI Receive Time-Out Interrupt Mask
The RTIM values are defined as follows:
Value Description
0 RX FIFO time-out interrupt is masked.
1 RX FIFO time-out interrupt is not masked.
1 RTIM R/W 0
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Bit/Field Name Type Reset Description
SSI Receive Overrun Interrupt Mask
The RORIM values are defined as follows:
Value Description
0 RX FIFO overrun interrupt is masked.
1 RX FIFO overrun interrupt is not masked.
0 RORIM R/W 0
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Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
Offset 0x018
Type RO, reset 0x0000.0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXRIS RXRIS RTRIS RORRIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SSI Transmit FIFO Raw Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
3 TXRIS RO 1
SSI Receive FIFO Raw Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
2 RXRIS RO 0
SSI Receive Time-Out Raw Interrupt Status
Indicates that the receive time-out has occurred, when set.
1 RTRIS RO 0
SSI Receive Overrun Raw Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
0 RORRIS RO 0
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Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXMIS RXMIS RTMIS RORMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0
SSI Transmit FIFO Masked Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
3 TXMIS RO 0
SSI Receive FIFO Masked Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
2 RXMIS RO 0
SSI Receive Time-Out Masked Interrupt Status
Indicates that the receive time-out has occurred, when set.
1 RTMIS RO 0
SSI Receive Overrun Masked Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
0 RORMIS RO 0
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Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
Offset 0x020
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RTIC RORIC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
SSI Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
0 No effect on interrupt.
1 Clears interrupt.
1 RTIC W1C 0
SSI Receive Overrun Interrupt Clear
The RORIC values are defined as follows:
Value Description
0 No effect on interrupt.
1 Clears interrupt.
0 RORIC W1C 0
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Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 4 (SSIPeriphID4)
SSI0 base: 0x4000.8000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID4 RO 0x00
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Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 5 (SSIPeriphID5)
SSI0 base: 0x4000.8000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID5 RO 0x00
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Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 6 (SSIPeriphID6)
SSI0 base: 0x4000.8000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID6 RO 0x00
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Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 7 (SSIPeriphID7)
SSI0 base: 0x4000.8000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID7 RO 0x00
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Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 0 (SSIPeriphID0)
SSI0 base: 0x4000.8000
Offset 0xFE0
Type RO, reset 0x0000.0022
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID0 RO 0x22
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Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 1 (SSIPeriphID1)
SSI0 base: 0x4000.8000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID1 RO 0x00
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Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 2 (SSIPeriphID2)
SSI0 base: 0x4000.8000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID2 RO 0x18
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Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 3 (SSIPeriphID3)
SSI0 base: 0x4000.8000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID3 RO 0x01
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Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 0 (SSIPCellID0)
SSI0 base: 0x4000.8000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
7:0 CID0 RO 0x0D
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Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 1 (SSIPCellID1)
SSI0 base: 0x4000.8000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
7:0 CID1 RO 0xF0
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Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 2 (SSIPCellID2)
SSI0 base: 0x4000.8000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
7:0 CID2 RO 0x05
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Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 3 (SSIPCellID3)
SSI0 base: 0x4000.8000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
7:0 CID3 RO 0xB1
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15 Inter-Integrated Circuit (I2C) Interface
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C
bus may also be used for system testing and diagnostic purposes in product development and
manufacture. The LM3S6952 microcontroller includes one I2C module, providing the ability to interact
(both send and receive) with other I2C devices on the bus.
Devices on the I2C bus can be designated as either a master or a slave. The Stellaris® I2C module
supports both sending and receiving data as either a master or a slave, and also supports the
simultaneous operation as both a master and a slave. There are a total of four I2C modes: Master
Transmit, Master Receive, Slave Transmit, and Slave Receive. The Stellaris® I2C module can
operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
Both the I2C master and slave can generate interrupts; the I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error) and the I2C slave generates
interrupts when data has been sent or requested by a master.
15.1 Block Diagram
Figure 15-1. I2C Block Diagram
I2C I/O Select
I2C Master Core
Interrupt
I2C Slave Core
I2CSCL
I2CSDA
I2CSDA
I2CSCL
I2CSDA
I2CSCL
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIM
I2CSRIS
I2CSMIS
I2CMMIS I2CSICR
I2C Control
15.2 Functional Description
The I2C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I2C bus configuration is shown in Figure 15-2 on page 375.
See “I2C” on page 539 for I2C timing diagrams.
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Figure 15-2. I2C Bus Configuration
RPUP
StellarisTM
I2CSCL I2CSDA
RPUP
3rd Party Device
with I2C Interface
SCL SDA
I2C Bus
SCL
SDA
3rd Party Device
with I2C Interface
SCL SDA
15.2.1 I2C Bus Functional Overview
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris®
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are high.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 375) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
15.2.1.1 START and STOP Conditions
The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP.
A high-to-low transition on the SDA line while the SCL is high is defined as a START condition, and
a low-to-high transition on the SDA line while SCL is high is defined as a STOP condition. The bus
is considered busy after a START condition and free after a STOP condition. See Figure
15-3 on page 375.
Figure 15-3. START and STOP Conditions
START
condition
SDA
SCL
STOP
condition
SDA
SCL
15.2.1.2 Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 15-4 on page 376. After the START condition, a
slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction
bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates
a request for data (receive). A data transfer is always terminated by a STOP condition generated
by the master, however, a master can initiate communications with another device on the bus by
generating a repeated START condition and addressing another slave without first generating a
STOP condition. Various combinations of receive/send formats are then possible within a single
transfer.
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Figure 15-4. Complete Data Transfer with a 7-Bit Address
Slave address Data
SDA MSB LSB R/S ACK MSB LSB ACK
SCL 1 2 7 8 9 1 2 7 8 9
The first seven bits of the first byte make up the slave address (see Figure 15-5 on page 376). The
eighth bit determines the direction of the message. A zero in the R/S position of the first byte means
that the master will write (send) data to the selected slave, and a one in this position means that
the master will receive data from the slave.
Figure 15-5. R/S Bit in First Byte
R/S
LSB
Slave address
MSB
15.2.1.3 Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is low (see Figure 15-6 on page 376).
Figure 15-6. Data Validity During Bit Transfer on the I2C Bus
Change
of data
allowed
Dataline
stable
SDA
SCL
15.2.1.4 Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data
validity requirements described in “Data Validity” on page 376.
When a slave receiver does not acknowledge the slave address, SDA must be left high by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Since the master controls the number of bytes in the transfer, it signals the end
of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave
transmitter must then release SDA to allow the master to generate the STOP or a repeated START
condition.
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15.2.1.5 Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is high. During arbitration, the first of the
competing master devices to place a '1' (high) on SDA while another master transmits a '0' (low)
will switch off its data output stage and retire until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
15.2.2 Available Speed Modes
The I2C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP.
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see
page 394).
The I2C clock period is calculated as follows:
SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/T = 333 Khz
Table 15-1 on page 377 gives examples of timer period, system clock, and speed mode (Standard
or Fast).
Table 15-1. Examples of I2C Master Timer Period versus Speed Mode
System Clock Timer Period Standard Mode Timer Period Fast Mode
4 Mhz 0x01 100 Kbps - -
6 Mhz 0x02 100 Kbps - -
12.5 Mhz 0x06 89 Kbps 0x01 312 Kbps
16.7 Mhz 0x08 93 Kbps 0x02 278 Kbps
20 Mhz 0x09 100 Kbps 0x02 333 Kbps
25 Mhz 0x0C 96.2 Kbps 0x03 312 Kbps
33Mhz 0x10 97.1 Kbps 0x04 330 Kbps
40Mhz 0x13 100 Kbps 0x04 400 Kbps
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System Clock Timer Period Standard Mode Timer Period Fast Mode
50Mhz 0x18 100 Kbps 0x06 357 Kbps
15.2.3 Interrupts
The I2C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master transaction error
■ Slave transaction received
■ Slave transaction requested
There is a separate interrupt signal for the I2C master and I2C modules. While both modules can
generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
15.2.3.1 I2C Master Interrupts
The I2C master module generates an interrupt when a transaction completes (either transmit or
receive), or when an error occurs during a transaction. To enable the I2C master interrupt, software
must write a '1' to the I2C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition
is met, software must check the ERROR bit in the I2C Master Control/Status (I2CMCS) register to
verify that an error didn't occur during the last transaction. An error condition is asserted if the last
transaction wasn't acknowledge by the slave or if the master was forced to give up ownership of
the bus due to a lost arbitration round with another master. If an error is not detected, the application
can proceed with the transfer. The interrupt is cleared by writing a '1' to the I2C Master Interrupt
Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Master Raw Interrupt Status (I2CMRIS) register.
15.2.3.2 I2C Slave Interrupts
The slave module generates interrupts as it receives requests from an I2C master. To enable the
I2C slave interrupt, write a '1' to the I2C Slave Interrupt Mask (I2CSIMR) register. Software
determines whether the module should write (transmit) or read (receive) data from the I2C Slave
Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status
(I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received,
the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a '1' to the I2C Slave
Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Slave Raw Interrupt Status (I2CSRIS) register.
15.2.4 Loopback Operation
The I2C modules can be placed into an internal loopback mode for diagnostic or debug work. This
is accomplished by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In
loopback mode, the SDA and SCL signals from the master and slave modules are tied together.
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15.2.5 Command Sequence Flow Charts
This section details the steps required to perform the various I2C transfer types in both master and
slave mode.
15.2.5.1 I2C Master Command Sequences
The figures that follow show the command sequences available for the I2C master.
Figure 15-7. Master Single SEND
Idle
Write Slave
Address to
I2CMSA
Write data to
I2CMDR
Read I2CMCS
Sequence
may be
omitted in a
Single Master
system
BUSBSY bit=0? NO
Write ---0-111 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
Error Service
Idle
YES
NO
NO
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Figure 15-8. Master Single RECEIVE
Idle
Write Slave
Address to
I2CMSA
Read I2CMCS
Sequence may be
omitted in a Single
Master system
BUSBSY bit=0? NO
Write ---00111 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
Error Service
Idle
NO
NO
Read data from
I2CMDR
YES
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Figure 15-9. Master Burst SEND
Idle
Write Slave
Address to
I2CMSA
Write data to
I2CMDR
Read I2CMCS
BUSBSY bit=0?
YES
Write ---0-011 to
I2CMCS
NO
Read I2CMCS
BUSY bit=0?
YES
ERROR bit=0?
YES
Write data to ARBLST bit=1?
I2CMDR
Write ---0-100 to
Index=n? I2CMCS
NO
Error Service
Idle
YES
Write ---0-001 to
I2CMCS
Write ---0-101 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
NO
Idle
YES
Error Service NO
NO
NO
NO
Sequence
may be
omitted in a
Single Master
system
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Figure 15-10. Master Burst RECEIVE
Idle
Write Slave
Address to
I2CMSA
Read I2CMCS
BUSBSY bit=0? NO
Write ---01011 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0? NO
ERROR bit=0?
YES
ARBLST bit=1?
Write ---0-100 to
I2CMCS
NO
Error Service
YES
Idle
Read data from
I2CMDR
Index=m-1?
Write ---00101 to
I2CMCS
YES
Idle
Read data from
Error Service I2CMDR
ERROR bit=0?
YES
Write ---01001 to
I2CMCS
Read I2CMCS
BUSY bit=0? NO
YES
Sequence
may be
omitted in a
Single Master
system
NO
NO
NO
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Figure 15-11. Master Burst RECEIVE after Burst SEND
Idle
Master operates in
Master Transmit mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---01011 to
I2CMCS
Master operates in
Master Receive mode
Idle
Repeated START
condition is generated
with changing data
direction
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Figure 15-12. Master Burst SEND after Burst RECEIVE
Idle
Master operates in
Master Receive mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---0-011 to
I2CMCS
Master operates in
Master Transmit mode
Idle
Repeated START
condition is generated
with changing data
direction
15.2.5.2 I2C Slave Command Sequences
Figure 15-13 on page 385 presents the command sequence available for the I2C slave.
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Figure 15-13. Slave Command Sequence
Idle
Write OWN Slave
Address to
I2CSOAR
Write -------1 to
I2CSCSR
Read I2CSCSR
RREQ bit=1?
Read data from
I2CSDR
YES
TREQ bit=1? NO
Write data to
I2CSDR
YES
NO
FBR is
also valid
15.3 Initialization and Configuration
The following example shows how to configure the I2C module to send a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation.
4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020.
5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:
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TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1;
TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
6. Specify the slave address of the master and that the next operation will be a Send by writing
the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired
data.
8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with
a value of 0x0000.0007 (STOP, START, RUN).
9. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
15.4 I2C Register Map
Table 15-2 on page 386 lists the I2C registers. All addresses given are relative to the I2C base
addresses for the master and slave:
■ I2C Master 0: 0x4002.0000
■ I2C Slave 0: 0x4002.0800
Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map
See
Offset Name Type Reset Description page
I2C Master
0x000 I2CMSA R/W 0x0000.0000 I2C Master Slave Address 388
0x004 I2CMCS R/W 0x0000.0000 I2C Master Control/Status 389
0x008 I2CMDR R/W 0x0000.0000 I2C Master Data 393
0x00C I2CMTPR R/W 0x0000.0001 I2C Master Timer Period 394
0x010 I2CMIMR R/W 0x0000.0000 I2C Master Interrupt Mask 395
0x014 I2CMRIS RO 0x0000.0000 I2C Master Raw Interrupt Status 396
0x018 I2CMMIS RO 0x0000.0000 I2C Master Masked Interrupt Status 397
0x01C I2CMICR WO 0x0000.0000 I2C Master Interrupt Clear 398
0x020 I2CMCR R/W 0x0000.0000 I2C Master Configuration 399
I2C Slave
0x000 I2CSOAR R/W 0x0000.0000 I2C Slave Own Address 401
0x004 I2CSCSR RO 0x0000.0000 I2C Slave Control/Status 402
0x008 I2CSDR R/W 0x0000.0000 I2C Slave Data 404
0x00C I2CSIMR R/W 0x0000.0000 I2C Slave Interrupt Mask 405
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See
Offset Name Type Reset Description page
0x010 I2CSRIS RO 0x0000.0000 I2C Slave Raw Interrupt Status 406
0x014 I2CSMIS RO 0x0000.0000 I2C Slave Masked Interrupt Status 407
0x018 I2CSICR WO 0x0000.0000 I2C Slave Interrupt Clear 408
15.5 Register Descriptions (I2C Master)
The remainder of this section lists and describes the I2C master registers, in numerical order by
address offset. See also “Register Descriptions (I2C Slave)” on page 400.
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Register 1: I2C Master Slave Address (I2CMSA), offset 0x000
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Send (Low).
I2C Master Slave Address (I2CMSA)
I2C Master 0 base: 0x4002.0000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SA R/S
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
I2C Slave Address
This field specifies bits A6 through A0 of the slave address.
7:1 SA R/W 0
Receive/Send
The R/S bit specifies if the next operation is a Receive (High) or Send
(Low).
Value Description
0 Send.
1 Receive.
0 R/S R/W 0
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Register 2: I2C Master Control/Status (I2CMCS), offset 0x004
This register accesses four control bits when written, and accesses seven status bits when read.
The status register consists of seven bits, which when read determine the state of the I2C bus
controller.
The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes
the generation of the START, or REPEATED START condition.
The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst.
To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with
the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1),
STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed
(or aborted due an error), the interrupt pin becomes active and the data may be read from the
I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set
normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after
each byte. This bit must be reset when the I2C bus controller requires no further data to be sent
from the slave transmitter.
Read-Only Status Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x00
Bus Busy
This bit specifies the state of the I2C bus. If set, the bus is busy;
otherwise, the bus is idle. The bit changes based on the START and
STOP conditions.
6 BUSBSY RO 0
I2C Idle
This bit specifies the I2C controller state. If set, the controller is idle;
otherwise the controller is not idle.
5 IDLE RO 0
Arbitration Lost
This bit specifies the result of bus arbitration. If set, the controller lost
arbitration; otherwise, the controller won arbitration.
4 ARBLST RO 0
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Bit/Field Name Type Reset Description
Acknowledge Data
This bit specifies the result of the last data operation. If set, the
transmitted data was not acknowledged; otherwise, the data was
acknowledged.
3 DATACK RO 0
Acknowledge Address
This bit specifies the result of the last address operation. If set, the
transmitted address was not acknowledged; otherwise, the address was
acknowledged.
2 ADRACK RO 0
Error
This bit specifies the result of the last bus operation. If set, an error
occurred on the last operation; otherwise, no error was detected. The
error can be from the slave address not being acknowledged, the
transmit data not being acknowledged, or because the controller lost
arbitration.
1 ERROR RO 0
I2C Busy
This bit specifies the state of the controller. If set, the controller is busy;
otherwise, the controller is idle. When the BUSY bit is set, the other status
bits are not valid.
0 BUSY RO 0
Write-Only Control Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
Offset 0x004
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ACK STOP START RUN
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved WO 0x00
Data Acknowledge Enable
When set, causes received data byte to be acknowledged automatically
by the master. See field decoding in Table 15-3 on page 391.
3 ACK WO 0
Generate STOP
When set, causes the generation of the STOP condition. See field
decoding in Table 15-3 on page 391.
2 STOP WO 0
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Bit/Field Name Type Reset Description
Generate START
When set, causes the generation of a START or repeated START
condition. See field decoding in Table 15-3 on page 391.
1 START WO 0
I2C Master Enable
When set, allows the master to send or receive data. See field decoding
in Table 15-3 on page 391.
0 RUN WO 0
Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3)
Current I2CMSA[0] I2CMCS[3:0] Description
State R/S ACK STOP START RUN
START condition followed by SEND (master goes to the
Master Transmit state).
Idle 0 Xa 0 1 1
START condition followed by a SEND and STOP
condition (master remains in Idle state).
0 X 1 1 1
START condition followed by RECEIVE operation with
negative ACK (master goes to the Master Receive state).
1 0 0 1 1
START condition followed by RECEIVE and STOP
condition (master remains in Idle state).
1 0 1 1 1
START condition followed by RECEIVE (master goes to
the Master Receive state).
1 1 0 1 1
1 1 1 1 1 Illegal.
All other combinations not listed are non-operations. NOP.
SEND operation (master remains in Master Transmit
state).
Master X X 0 0 1
Transmit
X X 1 0 0 STOP condition (master goes to Idle state).
SEND followed by STOP condition (master goes to Idle
state).
X X 1 0 1
Repeated START condition followed by a SEND (master
remains in Master Transmit state).
0 X 0 1 1
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
0 X 1 1 1
Repeated START condition followed by a RECEIVE
operation with a negative ACK (master goes to Master
Receive state).
1 0 0 1 1
Repeated START condition followed by a SEND and
STOP condition (master goes to Idle state).
1 0 1 1 1
Repeated START condition followed by RECEIVE (master
goes to Master Receive state).
1 1 0 1 1
1 1 1 1 1 Illegal.
All other combinations not listed are non-operations. NOP.
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Current I2CMSA[0] I2CMCS[3:0] Description
State R/S ACK STOP START RUN
RECEIVE operation with negative ACK (master remains
in Master Receive state).
Master X 0 0 0 1
Receive
X X 1 0 0 STOP condition (master goes to Idle state).b
RECEIVE followed by STOP condition (master goes to
Idle state).
X 0 1 0 1
RECEIVE operation (master remains in Master Receive
state).
X 1 0 0 1
X 1 1 0 1 Illegal.
Repeated START condition followed by RECEIVE
operation with a negative ACK (master remains in Master
Receive state).
1 0 0 1 1
Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
1 0 1 1 1
Repeated START condition followed by RECEIVE (master
remains in Master Receive state).
1 1 0 1 1
Repeated START condition followed by SEND (master
goes to Master Transmit state).
0 X 0 1 1
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
0 X 1 1 1
All other combinations not listed are non-operations. NOP.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.
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Inter-Integrated Circuit (I2C) Interface
Register 3: I2C Master Data (I2CMDR), offset 0x008
This register contains the data to be transmitted when in the Master Transmit state, and the data
received when in the Master Receive state.
I2C Master Data (I2CMDR)
I2C Master 0 base: 0x4002.0000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Data Transferred
Data transferred during transaction.
7:0 DATA R/W 0x00
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Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C
This register specifies the period of the SCL clock.
I2C Master Timer Period (I2CMTPR)
I2C Master 0 base: 0x4002.0000
Offset 0x00C
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TPR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SCL Clock Period
This field specifies the period of the SCL clock.
SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD
where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the Timer Period register value (range of 1 to 255).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
7:0 TPR R/W 0x1
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Inter-Integrated Circuit (I2C) Interface
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C Master 0 base: 0x4002.0000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IM
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Interrupt Mask
This bit controls whether a raw interrupt is promoted to a controller
interrupt. If set, the interrupt is not masked and the interrupt is promoted;
otherwise, the interrupt is masked.
0 IM R/W 0
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Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014
This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
I2C Master 0 base: 0x4002.0000
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Raw Interrupt Status
This bit specifies the raw interrupt state (prior to masking) of the I2C
master block. If set, an interrupt is pending; otherwise, an interrupt is
not pending.
0 RIS RO 0
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Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018
This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
I2C Master 0 base: 0x4002.0000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Masked Interrupt Status
This bit specifies the raw interrupt state (after masking) of the I2C master
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.
0 MIS RO 0
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Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C
This register clears the raw interrupt.
I2C Master Interrupt Clear (I2CMICR)
I2C Master 0 base: 0x4002.0000
Offset 0x01C
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Interrupt Clear
This bit controls the clearing of the raw interrupt. A write of 1 clears the
interrupt; otherwise, a write of 0 has no affect on the interrupt state. A
read of this register returns no meaningful data.
0 IC WO 0
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Inter-Integrated Circuit (I2C) Interface
Register 9: I2C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
I2C Master Configuration (I2CMCR)
I2C Master 0 base: 0x4002.0000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SFE MFE reserved LPBK
Type RO RO RO RO RO RO RO RO RO RO R/W R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
I2C Slave Function Enable
This bit specifies whether the interface may operate in Slave mode. If
set, Slave mode is enabled; otherwise, Slave mode is disabled.
5 SFE R/W 0
I2C Master Function Enable
This bit specifies whether the interface may operate in Master mode. If
set, Master mode is enabled; otherwise, Master mode is disabled and
the interface clock is disabled.
4 MFE R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:1 reserved RO 0x00
I2C Loopback
This bit specifies whether the interface is operating normally or in
Loopback mode. If set, the device is put in a test mode loopback
configuration; otherwise, the device operates normally.
0 LPBK R/W 0
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15.6 Register Descriptions (I2C Slave)
The remainder of this section lists and describes the I2C slave registers, in numerical order by
address offset. See also “Register Descriptions (I2C Master)” on page 387.
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Inter-Integrated Circuit (I2C) Interface
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000
This register consists of seven address bits that identify the Stellaris® I2C device on the I2C bus.
I2C Slave Own Address (I2CSOAR)
I2C Slave 0 base: 0x4002.0800
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OAR
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x00
I2C Slave Own Address
This field specifies bits A6 through A0 of the slave address.
6:0 OAR R/W 0x00
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Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004
This register accesses one control bit when written, and three status bits when read.
The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First
Byte Received (FBR) bit is set only after the Stellaris® device detects its own slave address
and receives the first data byte from the I2C master. The Receive Request (RREQ) bit indicates
that the Stellaris® I2C device has received a data byte from an I2C master. Read one data byte from
the I2C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit
indicates that the Stellaris® I2C device is addressed as a Slave Transmitter. Write one data byte
into the I2C Slave Data (I2CSDR) register to clear the TREQ bit.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
Stellaris® I2C slave operation.
Read-Only Status Register
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved FBR TREQ RREQ
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
First Byte Received
Indicates that the first byte following the slave’s own address is received.
This bit is only valid when the RREQ bit is set, and is automatically cleared
when data has been read from the I2CSDR register.
Note: This bit is not used for slave transmit operations.
2 FBR RO 0
Transmit Request
This bit specifies the state of the I2C slave with regards to outstanding
transmit requests. If set, the I2C unit has been addressed as a slave
transmitter and uses clock stretching to delay the master until data has
been written to the I2CSDR register. Otherwise, there is no outstanding
transmit request.
1 TREQ RO 0
Receive Request
This bit specifies the status of the I2C slave with regards to outstanding
receive requests. If set, the I2C unit has outstanding receive data from
the I2C master and uses clock stretching to delay the master until the
data has been read from the I2CSDR register. Otherwise, no receive
data is outstanding.
0 RREQ RO 0
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Inter-Integrated Circuit (I2C) Interface
Write-Only Control Register
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
Offset 0x004
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Device Active
Value Description
0 Disables the I2C slave operation.
1 Enables the I2C slave operation.
0 DA WO 0
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Register 12: I2C Slave Data (I2CSDR), offset 0x008
This register contains the data to be transmitted when in the Slave Transmit state, and the data
received when in the Slave Receive state.
I2C Slave Data (I2CSDR)
I2C Slave 0 base: 0x4002.0800
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Data for Transfer
This field contains the data for transfer during a slave receive or transmit
operation.
7:0 DATA R/W 0x0
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Inter-Integrated Circuit (I2C) Interface
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C Slave 0 base: 0x4002.0800
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IM
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Interrupt Mask
This bit controls whether a raw interrupt is promoted to a controller
interrupt. If set, the interrupt is not masked and the interrupt is promoted;
otherwise, the interrupt is masked.
0 IM R/W 0
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Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010
This register specifies whether an interrupt is pending.
I2C Slave Raw Interrupt Status (I2CSRIS)
I2C Slave 0 base: 0x4002.0800
Offset 0x010
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Raw Interrupt Status
This bit specifies the raw interrupt state (prior to masking) of the I2C
slave block. If set, an interrupt is pending; otherwise, an interrupt is not
pending.
0 RIS RO 0
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Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C Slave 0 base: 0x4002.0800
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Masked Interrupt Status
This bit specifies the raw interrupt state (after masking) of the I2C slave
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.
0 MIS RO 0
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Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018
This register clears the raw interrupt.
I2C Slave Interrupt Clear (I2CSICR)
I2C Slave 0 base: 0x4002.0800
Offset 0x018
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Clear Interrupt
This bit controls the clearing of the raw interrupt. A write of 1 clears the
interrupt; otherwise a write of 0 has no affect on the interrupt state. A
read of this register returns no meaningful data.
0 IC WO 0
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Inter-Integrated Circuit (I2C) Interface
16 Ethernet Controller
The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and
network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3
specifications and fully supports 10BASE-T and 100BASE-TX standards.
The Ethernet Controller module has the following features:
■ Conforms to the IEEE 802.3-2002 specification
– 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer
interface to the line
– 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler
– Full-featured auto-negotiation
■ Multiple operational modes
– Full- and half-duplex 100 Mbps
– Full- and half-duplex 10 Mbps
– Power-saving and power-down modes
■ Highly configurable
– Programmable MAC address
– LED activity selection
– Promiscuous mode support
– CRC error-rejection control
– User-configurable interrupts
■ Physical media manipulation
– Automatic MDI/MDI-X cross-over correction
– Register-programmable transmit amplitude
– Automatic polarity correction and 10BASE-T signal reception
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16.1 Block Diagram
Figure 16-1. Ethernet Controller Block Diagram
MACISR
MACIACK
MACIMR
Interrupt
Control
MACRCR
MACNPR
Receive
Control
MACTCR
MACITHR
MACTRR
Transmit
Control
Transmit
FIFO
Receive
FIFO
MACIAR0
MACIAR1
Individual
Address
MACMDTX
MACMCR
MACMDVR
MACMAR
MACMDRX
MII
Control
MACDR
Data
Access
TXOP
TXON
RXIP
RXIN
XTLP
XTLN
MDIX
Clock
Reference
Transmit
Encoding
Pulse
Shaping
Receive
Decoding
Clock
Recovery
Auto
Negotiation
Carrier
Sense
MR3
MR0
MR1
MR2
MR4
Media Independent Interface
Management Register Set
MR5
MR18
MR6
MR16
MR17
MR19
MR23
MR24
Collision
Detect System Clock
Interrupt
16.2 Functional Description
As shown in Figure 16-2 on page 410, the Ethernet Controller is functionally divided into two layers
or modules: the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These
correspond to the OSI model layers 2 and 1. The primary interface to the Ethernet Controller is a
simple bus interface to the MAC layer. The MAC layer provides transmit and receive processing for
Ethernet frames. The MAC layer also provides the interface to the PHY module via an internal Media
Independent Interface (MII).
Figure 16-2. Ethernet Controller
Cortex M3
Media Access
Controller
MAC
(Layer 2)
Physical
Layer Entity
PHY
(Layer 1)
Magnetics RJ45
Ethernet Controller
16.2.1 Internal MII Operation
For the MII management interface to function properly, the MDIO signal must be connected through
a 10k Ω pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor will prevent
management transactions on this internal MII to function. Note that it is possible for data transmission
across the MII to still function since the PHY layer will auto-negotiate the link parameters by default.
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For the MII management interface to function properly, the internal clock must be divided down from
the system clock to a frequency no greater than 2.5 MHz. The MACMDV register contains the divider
used for scaling down the system clock. See page 430 for more details about the use of this register.
16.2.2 PHY Configuration/Operation
The Physical Layer (PHY) in the Ethernet Controller includes integrated ENDECs,
scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions.
The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an
adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery.
The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX
applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The
Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external
filter is required.
16.2.2.1 Clock Selection
The PHY has an on-chip crystal oscillator which can also be driven by an external oscillator. In this
mode of operation, a 25-MHz crystal should be connected between the XTALPPHY and XTALNPHY
pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY pin. In this
mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground.
16.2.2.2 Auto-Negotiation
The PHY supports the auto-negotiation functions of Clause 28 of the IEEE 802.3 standard for 10/100
Mbps operation over copper wiring. This function can be enabled via register settings. The
auto-negotiation function defaults to On and the ANEGEN bit in the MR0 register is High after reset.
Software can disable the auto-negotiation function by writing to the ANEGEN bit. The contents of the
MR4 register are sent to the PHY’s link partner during auto-negotiation via fast-link pulse coding.
Once auto-negotiation is complete, the DPLX and RATE bits in the MR18 register reflect the actual
speed and duplex that was chosen. If auto-negotiation fails to establish a link for any reason, the
ANEGF bit in the MR18 register reflects this and auto-negotiation restarts from the beginning. Writing
a 1 to the RANEG bit in the MR0 register also causes auto-negotiation to restart.
16.2.2.3 Polarity Correction
The PHY is capable of either automatic or manual polarity reversal for 10BASE-T and auto-negotiation
functions. Bits 4 and 5 (RVSPOL and APOL) in the MR16 register control this feature. The default is
automatic mode, where APOL is Low and RVSPOL indicates if the detection circuitry has inverted
the input signal. To enter manual mode, APOL should be set High and RVSPOL then controls the
signal polarity.
16.2.2.4 MDI/MDI-X Configuration
The PHY supports the automatic MDI/MDI-X configuration as defined in IEEE 802.3-2002
specification. This eliminates the need for cross-over cables when connecting to another device,
such as a hub. The algorithm is controlled via settings in the MR24 register. Refer to page 452 for
additional details about these settings.
16.2.2.5 LED Indicators
The PHY supports two LED signals that can be used to indicate various states of operation of the
Ethernet Controller. These signals are mapped to the LED0 and LED1 pins. By default, these pins
are configured as GPIO signals (PF3 and PF2). For the PHY layer to drive these signals, they must
be reconfigured to their hardware function. See “General-Purpose Input/Outputs (GPIOs)” on page
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163 for additional details. The function of these pins is programmable via the PHY layer MR23 register.
Refer to page 451 for additonal details on how to program these LED functions.
16.2.3 MAC Configuration/Operation
16.2.3.1 Ethernet Frame Format
Ethernet data is carried by Ethernet frames. The basic frame format is shown in Figure
16-3 on page 412.
Figure 16-3. Ethernet Frame
Preamble SFD Destination Address Source Address Length/
Type Data FCS
7
Bytes
6
Bytes
6
Bytes
2
Bytes
1
Byte
4
Bytes
46 - 1500
Bytes
The seven fields of the frame are transmitted from left to right. The bits within the frame are
transmitted from least to most significant bit.
■ Preamble
The Preamble field is used by the physical layer signaling circuitry to synchronize with the received
frame’s timing. The preamble is 7 octets long.
■ Start Frame Delimiter (SFD)
The SFD field follows the preamble pattern and indicates the start of the frame. Its value is
1010.1011.
■ Destination Address (DA)
This field specifies destination addresses for which the frame is intended. The LSB of the DA
determines whether the address is an individual (0), or group/multicast (1) address.
■ Source Address (SA)
The source address field identifies the station from which the frame was initiated.
■ Length/Type Field
The meaning of this field depends on its numeric value. The first of two octets is most significant.
This field can be interpreted as length or type code. The maximum length of the data field is
1500 octets. If the value of the Length/Type field is less than or equal to 1500 decimal, it indicates
the number of MAC client data octets. If the value of this field is greater than or equal to 1536
decimal, then it is type interpretation. The meaning of the Length/Type field when the value is
between 1500 and 1536 decimal is unspecified by the standard. The MAC module assumes
type interpretation if the value of the Length/Type field is greater than 1500 decimal.
■ Data
The data field is a sequence of 0 to 1500 octets. Full data transparency is provided so any values
can appear in this field. A minimum frame size is required to properly meet the IEEE standard.
If necessary, the data field is extended by appending extra bits (a pad). The pad field can have
a size of 0 to 46 octets. The sum of the data and pad lengths must be a minimum of 46 octets.
The MAC module automatically inserts pads if required, though it can be disabled by a register
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write. For the MAC module core, data sent/received can be larger than 1500 bytes, and no Frame
Too Long error is reported. Instead, a FIFO Overrun error is reported when the frame received
is too large to fit into the Ethernet Controller’s RAM.
■ Frame Check Sequence (FCS)
The frame check sequence carries the cyclic redundancy check (CRC) value. The value of this
field is computed over destination address, source address, length/type, data, and pad fields
using the CRC-32 algorithm. The MAC module computes the FCS value one nibble at a time.
For transmitted frames, this field is automatically inserted by the MAC layer, unless disabled by
the CRC bit in the MACTCTL register. For received frames, this field is automatically checked.
If the FCS does not pass, the frame will not be placed in the RX FIFO, unless the FCS check is
disabled by the BADCRC bit in the MACRCTL register.
16.2.3.2 MAC Layer FIFOs
For Ethernet frame transmission, a 2 KB TX FIFO is provided that can be used to store a single
frame. While the IEEE 802.3 specification limits the size of an Ethernet frame's payload section to
1500 Bytes, the Ethernet Controller places no such limit. The full buffer can be used, for a payload
of up to 2032 bytes.
For Ethernet frame reception, a 2-KB RX FIFO is provided that can be used to store multiple frames,
up to a maximum of 31 frames. If a frame is received and there is insufficient space in the RX FIFO,
an overflow error will be indicated.
For details regarding the TX and RX FIFO layout, refer to Table 16-1 on page 413. Please note the
following difference between TX and RX FIFO layout. For the TX FIFO, the Data Length field in the
first FIFO word refers to the Ethernet frame data payload, as shown in the 5th to nth FIFO positions.
For the RX FIFO, the Frame Length field is the total length of the received Ethernet frame, including
the FCS and Frame Length bytes. Also note that if FCS generation is disabled with the CRC bit in
the MACTCTL register, the last word in the FIFO must be the FCS bytes for the frame that has been
written to the FIFO.
Also note that if the length of the data payload section is not a multiple of 4, the FCS field will overlap
words in the FIFO. However, for the RX FIFO, the beginning of the next frame will always be on a
word boundary.
Table 16-1. TX & RX FIFO Organization
FIFO Word Read/Write Word Bit Fields TX FIFO (Write) RX FIFO (Read)
Sequence
1st 7:0 Data Length LSB Frame Length LSB
15:8 Data Length MSB Frame Length MSB
23:16 DA oct 1
31:24 DA oct 2
2nd 7:0 DA oct 3
15:8 DA oct 4
23:16 DA oct 5
31:24 DA oct 6
3rd 7:0 SA oct 1
15:8 SA oct 2
23:16 SA oct 3
31:24 SA oct 4
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FIFO Word Read/Write Word Bit Fields TX FIFO (Write) RX FIFO (Read)
Sequence
4th 7:0 SA oct 5
15:8 SA oct 6
23:16 Len/Type MSB
31:24 Len/Type LSB
5th to nth 7:0 data oct n
15:8 data oct n+1
23:16 data oct n+2
31:24 data oct n+3
FCS 1 (if the CRC bit in FCS 1
MACCTL is 0)
last 7:0
FCS 2 (if the CRC bit in FCS 2
MACCTL is 0)
15:8
FCS 3 (if the CRC bit in FCS 3
MACCTL is 0)
23:16
FCS 4 (if the CRC bit in FCS 4
MACCTL is 0)
31:24
16.2.3.3 Ethernet Transmission Options
The Ethernet Controller can automatically generate and insert the Frame Check Sequence (FCS)
at the end of the transmit frame. This is controlled by the CRC bit in the MACTCTL register. For test
purposes, in order to generate a frame with an invalid CRC, this feature can be disabled.
The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46
bytes. The Ethernet Controller can be configured to automatically pad the data section if the payload
data section loaded into the FIFO is less than the minimum 46 bytes. This feature is controlled by
the PADEN bit in the MACTCTL register.
At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation
by using the DUPLEX bit in the MACTCTL register.
16.2.3.4 Ethernet Reception Options
Using the BADCRC bit in the MACRCTL register, the Ethernet Controller can be configured to reject
incoming Ethernet frames with an invalid FCS field.
The Ethernet receiver can also be configured for Promiscuous and Multicast modes using the PRMS
and AMUL fields in the MACRCTL register. If these modes are not enabled, only Ethernet frames
with a broadcast address, or frames matching the MAC address programmed into the MACIA0 and
MACIA1 register will be placed into the RX FIFO.
16.2.4 Interrupts
The Ethernet Controller can generate an interrupt for one or more of the following conditions:
■ A frame has been received into an empty RX FIFO
■ A frame transmission error has occurred
■ A frame has been transmitted successfully
■ A frame has been received with no room in the RX FIFO (overrun)
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■ A frame has been received with one or more error conditions (for example, FCS failed)
■ An MII management transaction between the MAC and PHY layers has completed
■ One or more of the following PHY layer conditions occurs:
– Auto-Negotiate Complete
– Remote Fault
– Link Status Change
– Link Partner Acknowledge
– Parallel Detect Fault
– Page Received
– Receive Error
– Jabber Event Detected
16.3 Initialization and Configuration
To use the Ethernet Controller, the peripheral must be enabled by setting the EPHY0 and EMAC0
bits in the RCGC2 register. The following steps can then be used to configure the Ethernet Controller
for basic operation.
1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming
a 20-MHz system clock, the MACDIV value would be 4.
2. Program the MACIA0 and MACIA1 register for address filtering.
3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation
using a value of 0x16.
4. Program the MACRCTL register to reject frames with bad FCS using a value of 0x08.
5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and
MACRCTL registers.
6. To transmit a frame, write the frame into the TX FIFO using the MACDATA register. Then set
the NEWTX bit in the MACTR register to initiate the transmit process. When the NEWTX bit has
been cleared, the TX FIFO will be available for the next transmit frame.
7. To receive a frame, wait for the NPR field in the MACNP register to be non-zero. Then begin
reading the frame from the RX FIFO by using the MACDATA register. When the frame (including
the FCS field) has been read, the NPR field should decrement by one. When there are no more
frames in the RX FIFO, the NPR field will read 0.
16.4 Ethernet Register Map
Table 16-2 on page 416 lists the Ethernet MAC registers. All addresses given are relative to the
Ethernet MAC base address of 0x4004.8000.
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The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY.
The registers are collectively known as the MII Management registers and are detailed in Section
22.2.4 of the IEEE 802.3 specification. Table 16-2 on page 416 also lists these MII Management
registers. All addresses given are absolute and are written directly to the REGADR field of the
MACMCTL register. The format of registers 0 to 15 are defined by the IEEE specification and are
common to all PHY implementations. The only variance allowed is for features that may or may not
be supported by a specific PHY. Registers 16 to 31 are vendor-specific registers, used to support
features that are specific to a vendors PHY implementation. Vendor-specific registers not listed are
reserved.
Table 16-2. Ethernet Register Map
See
Offset Name Type Reset Description page
Ethernet MAC
0x000 MACRIS RO 0x0000.0000 Ethernet MAC Raw Interrupt Status 418
0x000 MACIACK W1C 0x0000.0000 Ethernet MAC Interrupt Acknowledge 420
0x004 MACIM R/W 0x0000.007F Ethernet MAC Interrupt Mask 421
0x008 MACRCTL R/W 0x0000.0008 Ethernet MAC Receive Control 422
0x00C MACTCTL R/W 0x0000.0000 Ethernet MAC Transmit Control 423
0x010 MACDATA R/W 0x0000.0000 Ethernet MAC Data 424
0x014 MACIA0 R/W 0x0000.0000 Ethernet MAC Individual Address 0 426
0x018 MACIA1 R/W 0x0000.0000 Ethernet MAC Individual Address 1 427
0x01C MACTHR R/W 0x0000.003F Ethernet MAC Threshold 428
0x020 MACMCTL R/W 0x0000.0000 Ethernet MAC Management Control 429
0x024 MACMDV R/W 0x0000.0080 Ethernet MAC Management Divider 430
0x02C MACMTXD R/W 0x0000.0000 Ethernet MAC Management Transmit Data 431
0x030 MACMRXD R/W 0x0000.0000 Ethernet MAC Management Receive Data 432
0x034 MACNP RO 0x0000.0000 Ethernet MAC Number of Packets 433
0x038 MACTR R/W 0x0000.0000 Ethernet MAC Transmission Request 434
MII Management
- MR0 R/W 0x3100 Ethernet PHY Management Register 0 – Control 435
- MR1 RO 0x7849 Ethernet PHY Management Register 1 – Status 437
Ethernet PHY Management Register 2 – PHY Identifier 439
- MR2 RO 0x000E 1
Ethernet PHY Management Register 3 – PHY Identifier 440
- MR3 RO 0x7237 2
Ethernet PHYManagement Register 4 – Auto-Negotiation 441
- MR4 R/W 0x01E1 Advertisement
Ethernet PHYManagement Register 5 – Auto-Negotiation 443
- MR5 RO 0x0000 Link Partner Base Page Ability
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See
Offset Name Type Reset Description page
Ethernet PHYManagement Register 6 – Auto-Negotiation 444
- MR6 RO 0x0000 Expansion
Ethernet PHY Management Register 16 – 445
- MR16 R/W 0x0140 Vendor-Specific
Ethernet PHY Management Register 17 – Interrupt 447
- MR17 R/W 0x0000 Control/Status
- MR18 RO 0x0000 Ethernet PHY Management Register 18 – Diagnostic 449
Ethernet PHY Management Register 19 – Transceiver 450
- MR19 R/W 0x4000 Control
Ethernet PHY Management Register 23 – LED 451
- MR23 R/W 0x0010 Configuration
Ethernet PHY Management Register 24 –MDI/MDIX 452
- MR24 R/W 0x00C0 Control
16.5 Ethernet MAC Register Descriptions
The remainder of this section lists and describes the Ethernet MAC registers, in numerical order by
address offset. Also see “MII Management Register Descriptions” on page 434.
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Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000
The MACRIS register is the interrupt status register. On a read, this register gives the current status
value of the corresponding interrupt prior to masking.
Ethernet MAC Raw Interrupt Status (MACRIS)
Base 0x4004.8000
Offset 0x000
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PHYINT MDINT RXER FOV TXEMP TXER RXINT
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x0
PHY Interrupt
When set, indicates that an enabled interrupt in the PHY layer has
occured. MR17 in the PHY must be read to determine the specific PHY
event that triggered this interrupt.
6 PHYINT RO 0x0
MII Transaction Complete
When set, indicates that a transaction (read or write) on the MII interface
has completed successfully.
5 MDINT RO 0x0
Receive Error
This bit indicates that an error was encountered on the receiver. The
possible errors that can cause this interrupt bit to be set are:
■ A receive error occurs during the reception of a frame (100 Mb/s
only).
■ The frame is not an integer number of bytes (dribble bits) due to an
alignment error.
■ The CRC of the frame does not pass the FCS check.
■ The length/type field is inconsistent with the frame data size when
interpreted as a length field.
4 RXER RO 0x0
FIFO Overrrun
When set, indicates that an overrun was encountered on the receive
FIFO.
3 FOV RO 0x0
Transmit FIFO Empty
When set, indicates that the packet was transmitted and that the TX
FIFO is empty.
2 TXEMP RO 0x0
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Bit/Field Name Type Reset Description
Transmit Error
When set, indicates that an error was encountered on the transmitter.
The possible errors that can cause this interrupt bit to be set are:
■ The data length field stored in the TX FIFO exceeds 2032. The
frame is not sent when this error occurs.
■ The retransmission attempts during the backoff process have
exceeded the maximum limit of 16.
1 TXER RO 0x0
Packet Received
When set, indicates that at least one packet has been received and is
stored in the receiver FIFO.
0 RXINT RO 0x0
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Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000
A write of a 1 to any bit position of this register clears the corresponding interrupt bit in the Ethernet
MAC Raw Interrupt Status (MACRIS) register.
Ethernet MAC Interrupt Acknowledge (MACIACK)
Base 0x4004.8000
Offset 0x000
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PHYINT MDINT RXER FOV TXEMP TXER RXINT
Type RO RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x0
Clear PHY Interrupt
A write of a 1 clears the PHYINT interrupt read from the MACRIS
register.
6 PHYINT W1C 0x0
Clear MII Transaction Complete
A write of a 1 clears the MDINT interrupt read from the MACRIS register.
5 MDINT W1C 0x0
Clear Receive Error
A write of a 1 clears the RXER interrupt read from the MACRIS register.
4 RXER W1C 0x0
Clear FIFO Overrun
A write of a 1 clears the FOV interrupt read from the MACRIS register.
3 FOV W1C 0x0
Clear Transmit FIFO Empty
A write of a 1 clears the TXEMP interrupt read from the MACRIS register.
2 TXEMP W1C 0x0
Clear Transmit Error
A write of a 1 clears the TXER interrupt read from the MACRIS register
and resets the TX FIFO write pointer.
1 TXER W1C 0x0
Clear Packet Received
A write of a 1 clears the RXINT interrupt read from the MACRIS register.
0 RXINT W1C 0x0
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Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004
This register allows software to enable/disable Ethernet MAC interrupts. Writing a 0 disables the
interrupt, while writing a 1 enables it.
Ethernet MAC Interrupt Mask (MACIM)
Base 0x4004.8000
Offset 0x004
Type R/W, reset 0x0000.007F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PHYINTM MDINTM RXERM FOVM TXEMPM TXERM RXINTM
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x0
Mask PHY Interrupt
This bit masks the PHYINT bit in the MACRIS register from being
asserted.
6 PHYINTM R/W 1
Mask MII Transaction Complete
This bit masks the MDINT bit in the MACRIS register from being
asserted.
5 MDINTM R/W 1
Mask Receive Error
This bit masks the RXER bit in the MACRIS register from being asserted.
4 RXERM R/W 1
Mask FIFO Overrrun
This bit masks the FOV bit in the MACRIS register from being asserted.
3 FOVM R/W 1
Mask Transmit FIFO Empty
This bit masks the TXEMP bit in the MACRIS register from being
asserted.
2 TXEMPM R/W 1
Mask Transmit Error
This bit masks the TXER bit in the MACRIS register from being asserted.
1 TXERM R/W 1
Mask Packet Received
This bit masks the RXINT bit in the MACRIS register from being
asserted.
0 RXINTM R/W 1
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Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008
This register enables software to configure the receive module and control the types of frames that
are received from the physical medium. It is important to note that when the receive module is
enabled, all valid frames with a broadcast address of FF-FF-FF-FF-FF-FF in the Destination Address
field will be received and stored in the RX FIFO, even if the AMUL bit is not set.
Ethernet MAC Receive Control (MACRCTL)
Base 0x4004.8000
Offset 0x008
Type R/W, reset 0x0000.0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RSTFIFO BADCRC PRMS AMUL RXEN
Type RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 reserved RO 0x0
Clear Receive FIFO
When set, clears the receive FIFO. This should be done when software
initialization is performed.
It is recommended that the receiver be disabled (RXEN = 0), and then
the reset initiated (RSTFIFO = 1). This sequence will flush and reset the
RX FIFO.
4 RSTFIFO R/W 0x0
Enable Reject Bad CRC
The BADCRC bit enables the rejection of frames with an incorrectly
calculated CRC.
3 BADCRC R/W 0x1
Enable Promiscuous Mode
The PRMS bit enables Promiscuous mode, which accepts all valid frames,
regardless of the Destination Address.
2 PRMS R/W 0x0
Enable Multicast Frames
The AMUL bit enables the reception of multicast frames from the physical
medium.
1 AMUL R/W 0x0
Enable Receiver
The RXEN bit enables the Ethernet receiver. When this bit is Low, the
receiver is disabled and all frames on the physical medium are ignored.
0 RXEN R/W 0x0
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Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C
This register enables software to configure the transmit module, and control frames are placed onto
the physical medium.
Ethernet MAC Transmit Control (MACTCTL)
Base 0x4004.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DUPLEX reserved CRC PADEN TXEN
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 reserved RO 0x0
Enable Duplex Mode
When set, enables Duplex mode, allowing simultaneous transmission
and reception.
4 DUPLEX R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0x0
Enable CRC Generation
When set, enables the automatic generation of the CRC and the
placement at the end of the packet. If this bit is not set, the frames placed
in the TX FIFO will be sent exactly as they are written into the FIFO.
2 CRC R/W 0x0
Enable Packet Padding
When set, enables the automatic padding of packets that do not meet
the minimum frame size.
1 PADEN R/W 0x0
Enable Transmitter
When set, enables the transmitter. When this bit is 0, the transmitter is
disabled.
0 TXEN R/W 0x0
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Register 6: Ethernet MAC Data (MACDATA), offset 0x010
This register enables software to access the TX and RX FIFOs.
Reads from this register return the data stored in the RX FIFO from the location indicated by the
read pointer.
Writes to this register store the data in the TX FIFO at the location indicated by the write pointer.
The write pointer is then auto-incremented to the next TX FIFO location.
There is no mechanism for randomly accessing bytes in either the RX or TX FIFOs. Data must be
read from the RX FIFO sequentially and stored in a buffer for further processing. Once a read has
been performed, the data in the FIFO cannot be re-read. Data must be written to the TX FIFO
sequentially. If an error is made in placing the frame into the TX FIFO, the write pointer can be reset
to the start of the TX FIFO by writing the TXER bit of the MACIACK register and then the data
re-written.
Read-Only Register
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDATA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Receive FIFO Data
The RXDATA bits represent the next four bytes of data stored in the RX
FIFO.
31:0 RXDATA RO 0x0
Write-Only Register
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDATA
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit/Field Name Type Reset Description
Transmit FIFO Data
The TXDATA bits represent the next four bytes of data to place in the
TX FIFO for transmission.
31:0 TXDATA WO 0x0
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Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014
This register enables software to program the first four bytes of the hardware MAC address of the
Network Interface Card (NIC). (The last two bytes are in MACIA1). The 6-byte IAR is compared
against the incoming Destination Address fields to determine whether the frame should be received.
Ethernet MAC Individual Address 0 (MACIA0)
Base 0x4004.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MACOCT4 MACOCT3
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACOCT2 MACOCT1
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
MAC Address Octet 4
The MACOCT4 bits represent the fourth octet of the MAC address used
to uniquely identify each Ethernet Controller.
31:24 MACOCT4 R/W 0x0
MAC Address Octet 3
The MACOCT3 bits represent the third octet of the MAC address used
to uniquely identify each Ethernet Controller.
23:16 MACOCT3 R/W 0x0
MAC Address Octet 2
The MACOCT2 bits represent the second octet of the MAC address used
to uniquely identify each Ethernet Controller.
15:8 MACOCT2 R/W 0x0
MAC Address Octet 1
The MACOCT1 bits represent the first octet of the MAC address used to
uniquely identify each Ethernet Controller.
7:0 MACOCT1 R/W 0x0
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Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018
This register enables software to program the last two bytes of the hardware MAC address of the
Network Interface Card (NIC). (The first four bytes are in MACIA0). The 6-byte IAR is compared
against the incoming Destination Address fields to determine whether the frame should be received.
Ethernet MAC Individual Address 1 (MACIA1)
Base 0x4004.8000
Offset 0x018
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACOCT6 MACOCT5
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0
MAC Address Octet 6
The MACOCT6 bits represent the sixth octet of the MAC address used
to uniquely identify each Ethernet Controller.
15:8 MACOCT6 R/W 0x0
MAC Address Octet 5
The MACOCT5 bits represent the fifth octet of the MAC address used to
uniquely identify each Ethernet Controller.
7:0 MACOCT5 R/W 0x0
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Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C
This register enables software to set the threshold level at which the transmission of the frame
begins. If the THRESH bits are set to 0x3F, which is the reset value, transmission does not start until
the NEWTX bit is set in the MACTR register. This effectively disables the early transmission feature.
Writing the THRESH bits to any value besides all 1s enables the early transmission feature. Once
the byte count of data in the TX FIFO reaches this level, transmission of the frame begins. When
THRESH is set to all 0s, transmission of the frame begins after 4 bytes (a single write) are stored in
the TX FIFO. Each increment of the THRESH bit field waits for an additional 32 bytes of data (eight
writes) to be stored in the TX FIFO. Therefore, a value of 0x01 would wait for 36 bytes of data to
be written while a value of 0x02 would wait for 68 bytes to be written. In general, early transmission
starts when:
Number of Bytes >= 4 (THRESH x 8 + 1)
Reaching the threshold level has the same effect as setting the NEWTX bit in the MACTR register.
Transmission of the frame begins and then the number of bytes indicated by the Data Length field
is sent out on the physical medium. Because under-run checking is not performed, it is possible
that the tail pointer may reach and pass the write pointer in the TX FIFO. This causes indeterminate
values to be written to the physical medium rather than the end of the frame. Therefore, sufficient
bus bandwidth for writing to the TX FIFO must be guaranteed by the software.
If a frame smaller than the threshold level needs to be sent, the NEWTX bit in the MACTR register
must be set with an explicit write. This initiates the transmission of the frame even though the
threshold limit has not been reached.
If the threshold level is set too small, it is possible for the transmitter to underrun. If this occurs, the
transmit frame is aborted, and a transmit error occurs.
Ethernet MAC Threshold (MACTHR)
Base 0x4004.8000
Offset 0x01C
Type R/W, reset 0x0000.003F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved THRESH
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x0
Threshold Value
The THRESH bits represent the early transmit threshold. Once the amount
of data in the TX FIFO exceeds this value, transmission of the packet
begins.
5:0 THRESH R/W 0x3F
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Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020
This register enables software to control the transfer of data to and from the MII Management
registers in the Ethernet PHY. The address, name, type, reset configuration, and functional description
of each of these registers can be found in Table 16-2 on page 416 and in “MII Management Register
Descriptions” on page 434.
In order to initiate a read transaction from the MII Management registers, the WRITE bit must be
written with a 0 during the same cycle that the START bit is written with a 1.
In order to initiate a write transaction to the MII Management registers, the WRITE bit must be written
with a 1 during the same cycle that the START bit is written with a 1.
Ethernet MAC Management Control (MACMCTL)
Base 0x4004.8000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved REGADR reserved WRITE START
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0
MII Register Address
The REGADR bit field represents the MII Management register address
for the next MII management interface transaction.
7:3 REGADR R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2 reserved RO 0x0
MII Register Transaction Type
The WRITE bit represents the operation of the next MII management
interface transaction. If WRITE is set, the next operation will be a write;
otherwise, it will be a read.
1 WRITE R/W 0x0
MII Register Transaction Enable
The START bit represents the initiation of the next MII management
interface transaction. When a 1 is written to this bit, the MII register
located at REGADR will be read (WRITE=0) or written (WRITE=1).
0 START R/W 0x0
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Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024
This register enables software to set the clock divider for the Management Data Clock (MDC). This
clock is used to synchronize read and write transactions between the system and the MII Management
registers. The frequency of the MDC clock can be calculated from the following formula:
Fmdc = Fipclk / (2 * (MACMDVR + 1 ))
The clock divider must be written with a value that ensures that the MDC clock will not exceed a
frequency of 2.5 MHz.
Ethernet MAC Management Divider (MACMDV)
Base 0x4004.8000
Offset 0x024
Type R/W, reset 0x0000.0080
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DIV
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0
Clock Divider
The DIV bits are used to set the clock divider for the MDC clock used
to transmit data between the MAC and PHY over the serial MII interface.
7:0 DIV R/W 0x80
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Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset
0x02C
This register holds the next value to be written to the MII Management registers.
Ethernet MAC Management Transmit Data (MACMTXD)
Base 0x4004.8000
Offset 0x02C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDTX
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0
MII Register Transmit Data
The MDTX bits represent the data that will be written in the next MII
management transaction.
15:0 MDTX R/W 0x0
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Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset
0x030
This register holds the last value read from the MII Management registers.
Ethernet MAC Management Receive Data (MACMRXD)
Base 0x4004.8000
Offset 0x030
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDRX
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0
MII Register Receive Data
The MDRX bits represent the data that was read in the previous MII
management transaction.
15:0 MDRX R/W 0x0
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Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034
This register holds the number of frames that are currently in the RX FIFO. When NPR is 0, there
are no frames in the RX FIFO and the RXINT bit is not set. When NPR is any other value, there is
at least one frame in the RX FIFO and the RXINT bit in the MACRIS register is set.
Ethernet MAC Number of Packets (MACNP)
Base 0x4004.8000
Offset 0x034
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved NPR
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x0
Number of Packets in Receive FIFO
The NPR bits represent the number of packets stored in the RX FIFO.
While the NPR field is greater than 0, the RXINT interrupt in the MACRIS
register will be asserted.
5:0 NPR RO 0x0
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Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038
This register enables software to initiate the transmission of the frame currently located in the TX
FIFO to the physical medium. Once the frame has been transmitted to the medium from the TX
FIFO or a transmission error has been encountered, the NEWTX bit is auto-cleared by the hardware.
Ethernet MAC Transmission Request (MACTR)
Base 0x4004.8000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved NEWTX
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x0
New Transmission
When set, the NEWTX bit initiates an Ethernet transmission once the
packet has been placed in the TX FIFO. This bit is cleared once the
transmission has been completed. If early transmission is being used
(see the MACTHR register), this bit does not need to be set.
0 NEWTX R/W 0x0
16.6 MII Management Register Descriptions
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY.
The registers are collectively known as the MII Management registers. All addresses given are
absolute. Addresses not listed are reserved. Also see “Ethernet MAC Register
Descriptions” on page 417.
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Register 16: Ethernet PHY Management Register 0 – Control (MR0), address
0x00
This register enables software to configure the operation of the PHY. The default settings of these
registers are designed to initialize the PHY to a normal operational mode without configuration.
Ethernet PHY Management Register 0 – Control (MR0)
Base 0x4004.8000
Address 0x00
Type R/W, reset 0x3100
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT reserved
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Reset Registers
When set, resets the registers to their default state and reinitializes
internal state machines. Once the reset operation has completed, this
bit is cleared by hardware.
15 RESET R/W 0
Loopback Mode
When set, enables the Loopback mode of operation. The receive circuitry
is isolated from the physical medium and transmissions are sent back
through the receive circuitry instead of the medium.
14 LOOPBK R/W 0
Speed Select
1: Enables the 100 Mb/s mode of operation (100BASE-TX).
0: Enables the 10 Mb/s mode of operation (10BASE-T).
13 SPEEDSL R/W 1
Auto-Negotiation Enable
When set, enables the Auto-Negotiation process.
12 ANEGEN R/W 1
Power Down
When set, places the PHY into a low-power consuming state.
11 PWRDN R/W 0
Isolate
When set, isolates transmit and receive data paths and ignores all
signaling on these buses.
10 ISO R/W 0
Restart Auto-Negotiation
When set, restarts the Auto-Negotiation process. Once the restart has
initiated, this bit is cleared by hardware.
9 RANEG R/W 0
Set Duplex Mode
1: Enables the Full-Duplex mode of operation. This bit can be set by
software in a manual configuration process or by the Auto-Negotiation
process.
0: Enables the Half-Duplex mode of operation.
8 DUPLEX R/W 1
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Bit/Field Name Type Reset Description
Collision Test
When set, enables the Collision Test mode of operation. The COLT bit
asserts after the initiation of a transmission and de-asserts once the
transmission is halted.
7 COLT R/W 0
6:0 reserved R/W 0x00 Write as 0, ignore on read.
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Register 17: Ethernet PHY Management Register 1 – Status (MR1), address
0x01
This register enables software to determine the capabilities of the PHY and perform its initialization
and operation appropriately.
Ethernet PHY Management Register 1 – Status (MR1)
Base 0x4004.8000
Address 0x01
Type RO, reset 0x7849
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved 100X_F 100X_H 10T_F 10T_H reserved MFPS ANEGC RFAULT ANEGA LINK JAB EXTD
Type RO RO RO RO RO RO RO RO RO RO RO RC RO RO RC RO
Reset 0 1 1 1 1 0 0 0 0 1 0 0 1 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15 reserved RO 0
100BASE-TX Full-Duplex Mode
When set, indicates that the PHY is capable of supporting 100BASE-TX
Full-Duplex mode.
14 100X_F RO 1
100BASE-TX Half-Duplex Mode
When set, indicates that the PHY is capable of supporting 100BASE-TX
Half-Duplex mode.
13 100X_H RO 1
10BASE-T Full-Duplex Mode
When set, indicates that the PHY is capable of 10BASE-T Full-Duplex
mode.
12 10T_F RO 1
10BASE-T Half-Duplex Mode
When set, indicates that the PHY is capable of supporting 10BASE-T
Half-Duplex mode.
11 10T_H RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10:7 reserved RO 0
Management Frames with Preamble Suppressed
When set, indicates that the Management Interface is capable of
receiving management frames with the preamble suppressed.
6 MFPS RO 1
Auto-Negotiation Complete
When set, indicates that the Auto-Negotiation process has been
completed and that the extended registers defined by the
Auto-Negotiation protocol are valid.
5 ANEGC RO 0
Remote Fault
When set, indicates that a remote fault condition has been detected.
This bit remains set until it is read, even if the condition no longer exists.
4 RFAULT RC 0
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Bit/Field Name Type Reset Description
Auto-Negotiation
When set, indicates that the PHY has the ability to perform
Auto-Negotiation.
3 ANEGA RO 1
Link Made
When set, indicates that a valid link has been established by the PHY.
2 LINK RO 0
Jabber Condition
When set, indicates that a jabber condition has been detected by the
PHY. This bit remains set until it is read, even if the jabber condition no
longer exists.
1 JAB RC 0
Extended Capabilities
When set, indicates that the PHY provides an extended set of capabilities
that can be accessed through the extended register set.
0 EXTD RO 1
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Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2),
address 0x02
This register, along with MR3, provides a 32-bit value indicating the manufacturer, model, and
revision information.
Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2)
Base 0x4004.8000
Address 0x02
Type RO, reset 0x000E
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUI[21:6]
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
Bit/Field Name Type Reset Description
Organizationally Unique Identifier[21:6]
This field, along with the OUI[5:0] field in MR3, makes up the
Organizationally Unique Identifier indicating the PHY manufacturer.
15:0 OUI[21:6] RO 0x000E
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Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3),
address 0x03
This register, along with MR2, provides a 32-bit value indicating the manufacturer, model, and
revision information.
Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3)
Base 0x4004.8000
Address 0x03
Type RO, reset 0x7237
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUI[5:0] MN RN
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1
Bit/Field Name Type Reset Description
Organizationally Unique Identifier[5:0]
This field, along with the OUI[21:6] field in MR2, makes up the
Organizationally Unique Identifier indicating the PHY manufacturer.
15:10 OUI[5:0] RO 0x1C
Model Number
The MN field represents the Model Number of the PHY.
9:4 MN RO 0x23
Revision Number
The RN field represents the Revision Number of the PHY.
3:0 RN RO 0x7
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Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation
Advertisement (MR4), address 0x04
This register provides the advertised abilities of the PHY used during Auto-Negotiation. Bits 8:5
represent the Technology Ability Field bits. This field can be overwritten by software to Auto-Negotiate
to an alternate common technology. Writing to this register has no effect until Auto-Negotiation is
re-initiated.
Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4)
Base 0x4004.8000
Address 0x04
Type R/W, reset 0x01E1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NP reserved RF reserved A3 A2 A1 A0 S[4:0]
Type RO RO R/W RO RO RO RO R/W R/W R/W R/W RO RO RO RO RO
Reset 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1
Bit/Field Name Type Reset Description
Next Page
When set, indicates the PHY is capable of Next Page exchanges to
provide more detailed information on the PHY’s capabilities.
15 NP RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14 reserved RO 0
Remote Fault
When set, indicates to the link partner that a Remote Fault condition
has been encountered.
13 RF R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12:9 reserved RO 0
Technology Ability Field[3]
When set, indicates that the PHY supports the 100Base-TX full-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated with the
RANEG bit in the MR0 register.
8 A3 R/W 1
Technology Ability Field[2]
When set, indicates that the PHY supports the 100Base-T half-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated.
7 A2 R/W 1
Technology Ability Field[1]
When set, indicates that the PHY supports the 10Base-T full-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated.
6 A1 R/W 1
Technology Ability Field[0]
When set, indicates that the PHY supports the 10Base-T half-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated.
5 A0 R/W 1
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Bit/Field Name Type Reset Description
Selector Field
The S[4:0] field encodes 32 possible messages for communicating
between PHYs. This field is hard-coded to 0x01, indicating that the
Stellaris® PHY is IEEE 802.3 compliant.
4:0 S[4:0] RO 0x01
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Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link
Partner Base Page Ability (MR5), address 0x05
This register provides the advertised abilities of the link partner’s PHY that are received and stored
during Auto-Negotiation.
Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5)
Base 0x4004.8000
Address 0x05
Type RO, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NP ACK RF A[7:0] S[4:0]
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Next Page
When set, indicates that the link partner’s PHY is capable of Next page
exchanges to provide more detailed information on the PHY’s
capabilities.
15 NP RO 0
Acknowledge
When set, indicates that the device has successfully received the link
partner’s advertised abilities during Auto-Negotiation.
14 ACK RO 0
Remote Fault
Used as a standard transport mechanism for transmitting simple fault
information.
13 RF RO 0
Technology Ability Field
The A[7:0] field encodes individual technologies that are supported
by the PHY. See the MR4 register.
12:5 A[7:0] RO 0x00
Selector Field
The S[4:0] field encodes possible messages for communicating
between PHYs.
Value Description
0x00 Reserved
0x01 IEEE Std 802.3
0x02 IEEE Std 802.9 ISLAN-16T
0x03 IEEE Std 802.5
0x04 IEEE Std 1394
0x05–0x1F Reserved
4:0 S[4:0] RO 0x00
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Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation
Expansion (MR6), address 0x06
This register enables software to determine the Auto-Negotiation and Next Page capabilities of the
PHY and the link partner after Auto-Negotiation.
Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6)
Base 0x4004.8000
Address 0x06
Type RO, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PDF LPNPA reserved PRX LPANEGA
Type RO RO RO RO RO RO RO RO RO RO RO RC RO RO RC RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:5 reserved RO 0x000
Parallel Detection Fault
When set, indicates that more than one technology has been detected
at link up. This bit is cleared when read.
4 PDF RC 0
Link Partner is Next Page Able
When set, indicates that the link partner is Next Page Able.
3 LPNPA RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2 reserved RO 0x000
New Page Received
When set, indicates that a New Page has been received from the link
partner and stored in the appropriate location. This bit remains set until
the register is read.
1 PRX RC 0
Link Partner is Auto-Negotiation Able
When set, indicates that the Link partner is Auto-Negotiation Able.
0 LPANEGA RO 0
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Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16),
address 0x10
This register enables software to configure the operation of vendor-specific modes of the PHY.
Ethernet PHY Management Register 16 – Vendor-Specific (MR16)
Base 0x4004.8000
Address 0x10
Type R/W, reset 0x0140
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPTR INPOL reserved TXHIM SQEI NL10 reserved APOL RVSPOL reserved PCSBP RXCC
Type R/W R/W RO R/W R/W R/W RO RO RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Repeater Mode
When set, enables the repeater mode of operation. In this mode,
full-duplex is not allowed and the Carrier Sense signal only responds
to receive activity. If the PHY is configured to 10Base-T mode, the SQE
test function is disabled.
15 RPTR R/W 0
Interrupt Polarity
1: Sets the polarity of the PHY interrupt to be active High.
0: Sets the polarity of the PHY interrupt to active Low.
Important: Because the Media Access Controller expects active
Low interrupts from the PHY, this bit must always be
written with a 0 to ensure proper operation.
14 INPOL R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13 reserved RO 0
Transmit High Impedance Mode
When set, enables the transmitter High Impedance mode. In this mode,
the TXOP and TXON transmitter pins are put into a high impedance state.
The RXIP and RXIN pins remain fully functional.
12 TXHIM R/W 0
SQE Inhibit Testing
When set, prohibits 10Base-T SQE testing.
When 0, the SQE testing is performed by generating a Collision pulse
following the completion of the transmission of a frame.
11 SQEI R/W 0
Natural Loopback Mode
When set, enables the 10Base-T Natural Loopback mode. This causes
the transmission data received by the PHY to be looped back onto the
receive data path when 10Base-T mode is enabled.
10 NL10 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9:6 reserved RO 0x05
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Bit/Field Name Type Reset Description
Auto-Polarity Disable
When set, disables the PHY’s auto-polarity function.
If this bit is 0, the PHY automatically inverts the received signal due to
a wrong polarity connection during Auto-Negotiation if the PHY is in
10Base-T mode.
5 APOL R/W 0
Receive Data Polarity
This bit indicates whether the receive data pulses are being inverted.
If the APOL bit is 0, then the RVSPOL bit is read-only and indicates
whether the auto-polarity circuitry is reversing the polarity. In this case,
a 1 in the RVSPOL bit indicates that the receive data is inverted while a
0 indicates that the receive data is not inverted.
If the APOL bit is 1, then the RVSPOL bit is writable and software can
force the receive data to be inverted. Setting RVSPOL to 1 forces the
receive data to be inverted while a 0 does not invert the receive data.
4 RVSPOL R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
PCS Bypass
When set, enables the bypass of the PCS and scrambling/descrambling
functions in 100Base-TX mode. This mode is only valid when
Auto-Negotiation is disabled and 100Base-T mode is enabled.
1 PCSBP R/W 0
Receive Clock Control
When set, enables the Receive Clock Control power saving mode if the
PHY is configured in 100Base-TX mode. This mode shuts down the
receive clock when no data is being received from the physical medium
to save power. This mode should not be used when PCSBP is enabled
and is automatically disabled when the LOOPBK bit in the MR0 register
is set.
0 RXCC R/W 0
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Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status
(MR17), address 0x11
This register provides the means for controlling and observing the events, which trigger a PHY
interrupt in the MACRIS register. This register can also be used in a polling mode via the MII Serial
Interface as a means to observe key events within the PHY via one register address. Bits 0 through
7 are status bits, which are each set to logic 1 based on an event. These bits are cleared after the
register is read. Bits 8 through 15 of this register, when set to logic 1, enable their corresponding
bit in the lower byte to signal a PHY interrupt in the MACRIS register.
Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17)
Base 0x4004.8000
Address 0x11
Type R/W, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JABBER_IE RXER_IE PRX_IE PDF_IE LPACK_IELSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INTRXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT ANEGCOMP_INT
Type R/W R/W R/W R/W R/W R/W R/W R/W RC RC RC RC RC RC RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Jabber Interrupt Enable
When set, enables system interrupts when a Jabber condition is detected
by the PHY.
15 JABBER_IE R/W 0
Receive Error Interrupt Enable
When set, enables system interrupts when a receive error is detected
by the PHY.
14 RXER_IE R/W 0
Page Received Interrupt Enable
When set, enables system interrupts when a new page is received by
the PHY.
13 PRX_IE R/W 0
Parallel Detection Fault Interrupt Enable
When set, enables system interrupts when a Parallel Detection Fault is
detected by the PHY.
12 PDF_IE R/W 0
LP Acknowledge Interrupt Enable
When set, enables system interrupts when FLP bursts are received with
the Acknowledge bit during Auto-Negotiation.
11 LPACK_IE R/W 0
Link Status Change Interrupt Enable
When set, enables system interrupts when the Link Status changes
from OK to FAIL.
10 LSCHG_IE R/W 0
Remote Fault Interrupt Enable
When set, enables system interrupts when a Remote Fault condition is
signaled by the link partner.
9 RFAULT_IE R/W 0
Auto-Negotiation Complete Interrupt Enable
When set, enables system interrupts when the Auto-Negotiation
sequence has completed successfully.
8 ANEGCOMP_IE R/W 0
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Bit/Field Name Type Reset Description
Jabber Event Interrupt
When set, indicates that a Jabber event has been detected by the
10Base-T circuitry.
7 JABBER_INT RC 0
Receive Error Interrupt
When set, indicates that a receive error has been detected by the PHY.
6 RXER_INT RC 0
Page Receive Interrupt
When set, indicates that a new page has been received from the link
partner during Auto-Negotiation.
5 PRX_INT RC 0
Parallel Detection Fault Interrupt
When set, indicates that a Parallel Detection Fault has been detected
by the PHY during the Auto-Negotiation process.
4 PDF_INT RC 0
LP Acknowledge Interrupt
When set, indicates that an FLP burst has been received with the
Acknowledge bit set during Auto-Negotiation.
3 LPACK_INT RC 0
Link Status Change Interrupt
When set, indicates that the link status has changed from OK to FAIL.
2 LSCHG_INT RC 0
Remote Fault Interrupt
When set, indicates that a Remote Fault condition has been signaled
by the link partner.
1 RFAULT_INT RC 0
Auto-Negotiation Complete Interrupt
When set, indicates that the Auto-Negotiation sequence has completed
successfully.
0 ANEGCOMP_INT RC 0
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Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18),
address 0x12
This register enables software to diagnose the results of the previous Auto-Negotiation.
Ethernet PHY Management Register 18 – Diagnostic (MR18)
Base 0x4004.8000
Address 0x12
Type RO, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ANEGF DPLX RATE RXSD RX_LOCK reserved
Type RO RO RO RC RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
Auto-Negotiation Failure
When set, indicates that no common technology was found during
Auto-Negotiation and has failed. This bit remains set until read.
12 ANEGF RC 0
Duplex Mode
When set, indicates that Full-Duplex was the highest common
denominator found during the Auto-Negotiation process. Otherwise,
Half-Duplex was the highest common denominator found.
11 DPLX RO 0
Rate
When set, indicates that 100Base-TX was the highest common
denominator found during the Auto-Negotiation process. Otherwise,
10Base-TX was the highest common denominator found.
10 RATE RO 0
Receive Detection
When set, indicates that receive signal detection has occurred (in
100Base-TX mode) or that Manchester-encoded data has been detected
(in 10Base-T mode).
9 RXSD RO 0
Receive PLL Lock
When set, indicates that the Receive PLL has locked onto the receive
signal for the selected speed of operation (10Base-T or 100Base-TX).
8 RX_LOCK RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0 reserved RO 00
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Register 26: Ethernet PHY Management Register 19 – Transceiver Control
(MR19), address 0x13
This register enables software to set the gain of the transmit output to compensate for transformer
loss.
Ethernet PHY Management Register 19 – Transceiver Control (MR19)
Base 0x4004.8000
Address 0x13
Type R/W, reset 0x4000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXO[1:0] reserved
Type R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Transmit Amplitude Selection
The TXO[1:0] field sets the transmit output amplitude to account for
transmit transformer insertion loss.
Value Description
0x0 Gain set for 0.0dB of insertion loss
0x1 Gain set for 0.4dB of insertion loss
0x2 Gain set for 0.8dB of insertion loss
0x3 Gain set for 1.2dB of insertion loss
15:14 TXO[1:0] R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13:0 reserved RO 0x0
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Register 27: Ethernet PHY Management Register 23 – LED Configuration
(MR23), address 0x17
This register enables software to select the source that will cause the LEDs to toggle.
Ethernet PHY Management Register 23 – LED Configuration (MR23)
Base 0x4004.8000
Address 0x17
Type R/W, reset 0x0010
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved LED1[3:0] LED0[3:0]
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8 reserved RO 0x0
LED1 Source
The LED1 field selects the source that will toggle the LED1 signal.
Value Description
0x0 Link OK
0x1 RX or TX Activity (Default LED1)
0x2 TX Activity
0x3 RX Activity
0x4 Collision
0x5 100BASE-TX mode
0x6 10BASE-T mode
0x7 Full-Duplex
0x8 Link OK & Blink=RX or TX Activity
7:4 LED1[3:0] R/W 1
LED0 Source
The LED0 field selects the source that will toggle the LED0 signal.
Value Description
0x0 Link OK (Default LED0)
0x1 RX or TX Activity
0x2 TX Activity
0x3 RX Activity
0x4 Collision
0x5 100BASE-TX mode
0x6 10BASE-T mode
0x7 Full-Duplex
0x8 Link OK & Blink=RX or TX Activity
3:0 LED0[3:0] R/W 0
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Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24),
address 0x18
This register enables software to control the behavior of the MDI/MDIX mux and its switching
capabilities.
Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24)
Base 0x4004.8000
Address 0x18
Type R/W, reset 0x00C0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PD_MODEAUTO_SW MDIX MDIX_CM MDIX_SD
Type RO RO RO RO RO RO RO RO R/W R/W R/W RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8 reserved RO 0x0
Parallel Detection Mode
When set, enables the Parallel Detection mode and allows auto-switching
to work when Auto-Negotiation is not enabled.
7 PD_MODE R/W 0
Auto-Switching Enable
When set, enables Auto-Switching of the MDI/MDIX mux.
6 AUTO_SW R/W 0
Auto-Switching Configuration
When set, indicates that the MDI/MDIX mux is in the crossover (MDIX)
configuration.
When 0, it indicates that the mux is in the pass-through (MDI)
configuration.
When the AUTO_SW bit is 1, the MDIX bit is read-only. When the
AUTO_SW bit is 0, the MDIX bit is read/write and can be configured
manually.
5 MDIX R/W 0
Auto-Switching Complete
When set, indicates that the auto-switching sequence has completed.
If 0, it indicates that the sequence has not completed or that
auto-switching is disabled.
4 MDIX_CM RO 0
Auto-Switching Seed
This field provides the initial seed for the switching algorithm. This seed
directly affects the number of attempts [5,4] respectively to write bits
[3:0].
A 0 sets the seed to 0x5.
3:0 MDIX_SD R/W 0
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17 Analog Comparators
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S6952 controller provides three independent integrated analog comparators that can be
configured to drive an output or generate an interrupt or ADC event.
Note: Not all comparators have the option to drive an output pin. See the Comparator Operating
Mode tables for more information.
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
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17.1 Block Diagram
Figure 17-1. Analog Comparator Module Block Diagram
interrupt
C2+
C2-
output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 2
ACSTAT2
ACCTL2
interrupt
C1-
C1+ output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 1
ACSTAT1
ACCTL1
C1o
Voltage
Ref
ACREFCTL
output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 0
ACSTAT0
ACCTL0
C0+
internal
bus
interrupt
C0-
C0o
trigger trigger
trigger trigger
trigger trigger
17.2 Functional Description
Important: It is recommended that the Digital-Input enable (the GPIODEN bit in the GPIO module)
for the analog input pin be disabled to prevent excessive current draw from the I/O
pads.
The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT.
VIN- < VIN+, VOUT = 1
VIN- > VIN+, VOUT = 0
As shown in Figure 17-2 on page 455, the input source for VIN- is an external input. In addition to
an external input, input sources for VIN+ can be the +ve input of comparator 0 or an internal reference.
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Analog Comparators
Figure 17-2. Structure of Comparator Unit
ACCTL ACSTAT
IntGen
2 TrigGen
1
0
CINV
output
-ve input
+ve input
interrupt
internal
bus
trigger
+ve input (alternate)
reference input
A comparator is configured through two status/control registers (ACCTL and ACSTAT ). The internal
reference is configured through one control register (ACREFCTL). Interrupt status and control is
configured through three registers (ACMIS, ACRIS, and ACINTEN). The operating modes of the
comparators are shown in the Comparator Operating Mode tables.
Typically, the comparator output is used internally to generate controller interrupts. It may also be
used to drive an external pin or generate an analog-to-digital converter (ADC) trigger.
Important: Certain register bit values must be set before using the analog comparators. The proper
pad configuration for the comparator input and output pins are described in the
Comparator Operating Mode tables.
Table 17-1. Comparator 0 Operating Modes
ACCNTL0 Comparator 0
ASRCP VIN- VIN+ Output Interrupt ADCTrigger
00 C0- C0+ C0o yes yes
01 C0- C0+ C0o yes yes
10 C0- Vref C0o yes yes
11 C0- reserved C0o yes yes
Table 17-2. Comparator 1 Operating Modes
ACCNTL1 Comparator 1
ASRCP VIN- VIN+ Output Interrupt ADCTrigger
00 C1- C1o/C1+ C1o/C1+ yes yes
01 C1- C0+ C1o/C1+ yes yes
10 C1- Vref C1o/C1+ yes yes
11 C1- reserved C1o/C1+ yes yes
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Table 17-3. Comparator 2 Operating Modes
ACCNTL2 Comparator 2
ASRCP VIN- VIN+ Output Interrupt ADCTrigger
00 C2- C2+ n/a yes yes
01 C2- C0+ n/a yes yes
10 C2- Vref n/a yes yes
11 C2- reserved n/a yes yes
17.2.1 Internal Reference Programming
The structure of the internal reference is shown in Figure 17-3 on page 456. This is controlled by a
single configuration register (ACREFCTL). Table 17-4 on page 456 shows the programming options
to develop specific internal reference values, to compare an external voltage against a particular
voltage generated internally.
Figure 17-3. Comparator Internal Reference Structure
8R R R
8R
R R
•••
•••
0
Decoder
15 14 1
AVDD
EN
internal
reference
VREF
RNG
Table 17-4. Internal Reference Voltage and ACREFCTL Field Values
ACREFCTL Register Output Reference Voltage Based on VREF Field Value
EN Bit Value RNG Bit Value
0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and VREF=0
for the least noisy ground reference.
EN=0 RNG=X
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ACREFCTL Register Output Reference Voltage Based on VREF Field Value
EN Bit Value RNG Bit Value
Total resistance in ladder is 32 R.
VREF AVDD
R V REF
RT
= × ----------------
VREF AVDD
(VREF + 8)
32
= × ------------------------------
VR EF = 0.825 + 0.103 VREF
The range of internal reference in this mode is 0.825-2.37 V.
EN=1 RNG=0
Total resistance in ladder is 24 R.
VREF AVDD
R V REF
RT
= × ----------------
VREF AVDD
(VREF)
24
= × --------------------
VREF = 0.1375 x VREF
The range of internal reference for this mode is 0.0-2.0625 V.
RNG=1
17.3 Initialization and Configuration
The following example shows how to configure an analog comparator to read back its output value
from an internal register.
1. Enable the analog comparator 0 clock by writing a value of 0x0010.0000 to the RCGC1 register
in the System Control module.
2. In the GPIO module, enable the GPIO port/pin associated with C0- as a GPIO input.
3. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the
value 0x0000.030C.
4. Configure comparator 0 to use the internal voltage reference and to not invert the output on the
C0o pin by writing the ACCTL0 register with the value of 0x0000.040C.
5. Delay for some time.
6. Read the comparator output value by reading the ACSTAT0 register’s OVAL value.
Change the level of the signal input on C0- to see the OVAL value change.
17.4 Register Map
Table 17-5 on page 458 lists the comparator registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Analog Comparator base address of 0x4003.C000.
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Table 17-5. Analog Comparators Register Map
See
Offset Name Type Reset Description page
0x00 ACMIS R/W1C 0x0000.0000 Analog Comparator Masked Interrupt Status 459
0x04 ACRIS RO 0x0000.0000 Analog Comparator Raw Interrupt Status 460
0x08 ACINTEN R/W 0x0000.0000 Analog Comparator Interrupt Enable 461
0x10 ACREFCTL R/W 0x0000.0000 Analog Comparator Reference Voltage Control 462
0x20 ACSTAT0 RO 0x0000.0000 Analog Comparator Status 0 463
0x24 ACCTL0 R/W 0x0000.0000 Analog Comparator Control 0 464
0x40 ACSTAT1 RO 0x0000.0000 Analog Comparator Status 1 463
0x44 ACCTL1 R/W 0x0000.0000 Analog Comparator Control 1 464
0x60 ACSTAT2 RO 0x0000.0000 Analog Comparator Status 2 463
0x64 ACCTL2 R/W 0x0000.0000 Analog Comparator Control 2 464
17.5 Register Descriptions
The remainder of this section lists and describes the Analog Comparator registers, in numerical
order by address offset.
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Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00
This register provides a summary of the interrupt status (masked) of the comparator.
Analog Comparator Masked Interrupt Status (ACMIS)
Base 0x4003.C000
Offset 0x00
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Comparator 2 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
2 IN2 R/W1C 0
Comparator 1 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
1 IN1 R/W1C 0
Comparator 0 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
0 IN0 R/W1C 0
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Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04
This register provides a summary of the interrupt status (raw) of the comparator.
Analog Comparator Raw Interrupt Status (ACRIS)
Base 0x4003.C000
Offset 0x04
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Comparator 2 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
2.
2 IN2 RO 0
Comparator 1 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
1.
1 IN1 RO 0
Comparator 0 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
0.
0 IN0 RO 0
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Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08
This register provides the interrupt enable for the comparator.
Analog Comparator Interrupt Enable (ACINTEN)
Base 0x4003.C000
Offset 0x08
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Comparator 2 Interrupt Enable
When set, enables the controller interrupt from the comparator 2 output
2 IN2 R/W 0
Comparator 1 Interrupt Enable
When set, enables the controller interrupt from the comparator 1 output.
1 IN1 R/W 0
Comparator 0 Interrupt Enable
When set, enables the controller interrupt from the comparator 0 output.
0 IN0 R/W 0
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Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset
0x10
This register specifies whether the resistor ladder is powered on as well as the range and tap.
Analog Comparator Reference Voltage Control (ACREFCTL)
Base 0x4003.C000
Offset 0x10
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EN RNG reserved VREF
Type RO RO RO RO RO RO R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0x00
Resistor Ladder Enable
The EN bit specifies whether the resistor ladder is powered on. If 0, the
resistor ladder is unpowered. If 1, the resistor ladder is connected to
the analog VDD.
This bit is reset to 0 so that the internal reference consumes the least
amount of power if not used and programmed.
9 EN R/W 0
Resistor Ladder Range
The RNG bit specifies the range of the resistor ladder. If 0, the resistor
ladder has a total resistance of 32 R. If 1, the resistor ladder has a total
resistance of 24 R.
8 RNG R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x00
Resistor Ladder Voltage Ref
The VREF bit field specifies the resistor ladder tap that is passed through
an analog multiplexer. The voltage corresponding to the tap position is
the internal reference voltage available for comparison. See Table
17-4 on page 456 for some output reference voltage examples.
3:0 VREF R/W 0x00
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Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60
These registers specify the current output value of the comparator.
Analog Comparator Status 0 (ACSTAT0)
Base 0x4003.C000
Offset 0x20
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OVAL reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Comparator Output Value
The OVAL bit specifies the current output value of the comparator.
1 OVAL RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64
These registers configure the comparator’s input and output.
Analog Comparator Control 0 (ACCTL0)
Base 0x4003.C000
Offset 0x24
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TOEN ASRCP reserved TSLVAL TSEN ISLVAL ISEN CINV reserved
Type RO RO RO RO R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Trigger Output Enable
The TOEN bit enables the ADC event transmission to the ADC. If 0, the
event is suppressed and not sent to the ADC. If 1, the event is
transmitted to the ADC.
11 TOEN R/W 0
Analog Source Positive
The ASRCP field specifies the source of input voltage to the VIN+ terminal
of the comparator. The encodings for this field are as follows:
Value Function
0x0 Pin value
0x1 Pin value of C0+
0x2 Internal voltage reference
0x3 Reserved
10:9 ASRCP R/W 0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8 reserved RO 0
Trigger Sense Level Value
The TSLVAL bit specifies the sense value of the input that generates
an ADC event if in Level Sense mode. If 0, an ADC event is generated
if the comparator output is Low. Otherwise, an ADC event is generated
if the comparator output is High.
7 TSLVAL R/W 0
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Bit/Field Name Type Reset Description
Trigger Sense
The TSEN field specifies the sense of the comparator output that
generates an ADC event. The sense conditioning is as follows:
Value Function
0x0 Level sense, see TSLVAL
0x1 Falling edge
0x2 Rising edge
0x3 Either edge
6:5 TSEN R/W 0x0
Interrupt Sense Level Value
The ISLVAL bit specifies the sense value of the input that generates
an interrupt if in Level Sense mode. If 0, an interrupt is generated if the
comparator output is Low. Otherwise, an interrupt is generated if the
comparator output is High.
4 ISLVAL R/W 0
Interrupt Sense
The ISEN field specifies the sense of the comparator output that
generates an interrupt. The sense conditioning is as follows:
Value Function
0x0 Level sense, see ISLVAL
0x1 Falling edge
0x2 Rising edge
0x3 Either edge
3:2 ISEN R/W 0x0
Comparator Output Invert
The CINV bit conditionally inverts the output of the comparator. If 0, the
output of the comparator is unchanged. If 1, the output of the comparator
is inverted prior to being processed by hardware.
1 CINV R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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18 Pulse Width Modulator (PWM)
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
The Stellaris® PWM module consists of two PWM generator blocks and a control block. Each PWM
generator block contains one timer (16-bit down or up/down counter), two PWM comparators, a
PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control
block determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals
(other than being based on the same timer and therefore having the same frequency) or a single
pair of complementary signals with dead-band delays inserted. The output of the PWM generation
blocks are managed by the output control block before being passed to the device pins.
The Stellaris® PWM module provides a great deal of flexibility. It can generate simple PWM signals,
such as those required by a simple charge pump. It can also generate paired PWM signals with
dead-band delays, such as those required by a half-H bridge driver.
18.1 Block Diagram
Figure 18-1 on page 466 provides a block diagram of a Stellaris® PWM module. The LM3S6952
controller contains two generator blocks (PWM0 and PWM1) and generates four independent PWM
signals or two paired PWM signals with dead-band delays inserted.
Figure 18-1. PWM Module Block Diagram
Interrupt and
Trigger Generate
PWMnINTEN
PWMnRIS
PWMnISC
PWM Clock
Interrupt
Dead-Band
Generator
PWMnDBCTL
PWMnDBRISE
PWMnDBFALL
PWM Output
Control
PWMENABLE
PWMINVERT
PWMFAULT
PWM
Generator
PWMnGENA
PWMnGENB
pwma
pwmb
Timer
PWMnLOAD
PWMnCOUNT
Comparator A
PWMnCMPA
Comparator B
PWMnCMPB
zero
load
dir
16
cmpA
cmpB
Fault
PWM Generator Block
18.2 Functional Description
18.2.1 PWM Timer
The timer in each PWM generator runs in one of two modes: Count-Down mode or Count-Up/Down
mode. In Count-Down mode, the timer counts from the load value to zero, goes back to the load
value, and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the
load value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode
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is used for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used
for generating center-aligned PWM signals.
The timers output three signals that are used in the PWM generation process: the direction signal
(this is always Low in Count-Down mode, but alternates between Low and High in Count-Up/Down
mode), a single-clock-cycle-width High pulse when the counter is zero, and a single-clock-cycle-width
High pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero
pulse is immediately followed by the load pulse.
18.2.2 PWM Comparators
There are two comparators in each PWM generator that monitor the value of the counter; when
either match the counter, they output a single-clock-cycle-width High pulse. When in Count-Up/Down
mode, these comparators match both when counting up and when counting down; they are therefore
qualified by the counter direction signal. These qualified pulses are used in the PWM generation
process. If either comparator match value is greater than the counter load value, then that comparator
never outputs a High pulse.
Figure 18-2 on page 467 shows the behavior of the counter and the relationship of these pulses
when the counter is in Count-Down mode. Figure 18-3 on page 468 shows the behavior of the counter
and the relationship of these pulses when the counter is in Count-Up/Down mode.
Figure 18-2. PWM Count-Down Mode
Load
Zero
CompB
CompA
Load
Zero
B
A
Dir
ADown
BDown
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Figure 18-3. PWM Count-Up/Down Mode
Load
Zero
CompB
CompA
Load
Zero
B
A
Dir
BUp
AUp ADown
BDown
18.2.3 PWM Signal Generator
The PWM generator takes these pulses (qualified by the direction signal), and generates two PWM
signals. In Count-Down mode, there are four events that can affect the PWM signal: zero, load,
match A down, and match B down. In Count-Up/Down mode, there are six events that can affect
the PWM signal: zero, load, match A down, match A up, match B down, and match B up. The match
A or match B events are ignored when they coincide with the zero or load events. If the match A
and match B events coincide, the first signal, PWMA, is generated based only on the match A event,
and the second signal, PWMB, is generated based only on the match B event.
For each event, the effect on each output PWM signal is programmable: it can be left alone (ignoring
the event), it can be toggled, it can be driven Low, or it can be driven High. These actions can be
used to generate a pair of PWM signals of various positions and duty cycles, which do or do not
overlap. Figure 18-4 on page 468 shows the use of Count-Up/Down mode to generate a pair of
center-aligned, overlapped PWM signals that have different duty cycles.
Figure 18-4. PWM Generation Example In Count-Up/Down Mode
Load
Zero
CompB
CompA
PWMB
PWMA
In this example, the first generator is set to drive High on match A up, drive Low on match A down,
and ignore the other four events. The second generator is set to drive High on match B up, drive
Low on match B down, and ignore the other four events. Changing the value of comparator A
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changes the duty cycle of the PWMA signal, and changing the value of comparator B changes the
duty cycle of the PWMB signal.
18.2.4 Dead-Band Generator
The two PWM signals produced by the PWM generator are passed to the dead-band generator. If
disabled, the PWM signals simply pass through unmodified. If enabled, the second PWM signal is
lost and two PWM signals are generated based on the first PWM signal. The first output PWM signal
is the input signal with the rising edge delayed by a programmable amount. The second output
PWM signal is the inversion of the input signal with a programmable delay added between the falling
edge of the input signal and the rising edge of this new signal.
This is therefore a pair of active High signals where one is always High, except for a programmable
amount of time at transitions where both are Low. These signals are therefore suitable for driving
a half-H bridge, with the dead-band delays preventing shoot-through current from damaging the
power electronics. Figure 18-5 on page 469 shows the effect of the dead-band generator on an input
PWM signal.
Figure 18-5. PWM Dead-Band Generator
Input
PWMA
PWMB
Rising Edge
Delay
Falling Edge
Delay
18.2.5 Interrupt/ADC-Trigger Selector
The PWM generator also takes the same four (or six) counter events and uses them to generate
an interrupt or an ADC trigger. Any of these events or a set of these events can be selected as a
source for an interrupt; when any of the selected events occur, an interrupt is generated. Additionally,
the same event, a different event, the same set of events, or a different set of events can be selected
as a source for an ADC trigger; when any of these selected events occur, an ADC trigger pulse is
generated. The selection of events allows the interrupt or ADC trigger to occur at a specific position
within the PWM signal. Note that interrupts and ADC triggers are based on the raw events; delays
in the PWM signal edges caused by the dead-band generator are not taken into account.
18.2.6 Synchronization Methods
There is a global reset capability that can synchronously reset any or all of the counters in the PWM
generators. If multiple PWM generators are configured with the same counter load value, this can
be used to guarantee that they also have the same count value (this does imply that the PWM
generators must be configured before they are synchronized). With this, more than two PWM signals
can be produced with a known relationship between the edges of those signals since the counters
always have the same values.
The counter load values and comparator match values of the PWM generator can be updated in
two ways. The first is immediate update mode, where a new value is used as soon as the counter
reaches zero. By waiting for the counter to reach zero, a guaranteed behavior is defined, and overly
short or overly long output PWM pulses are prevented.
The other update method is synchronous, where the new value is not used until a global synchronized
update signal is asserted, at which point the new value is used as soon as the counter reaches
zero. This second mode allows multiple items in multiple PWM generators to be updated
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simultaneously without odd effects during the update; everything runs from the old values until a
point at which they all run from the new values. The Update mode of the load and comparator match
values can be individually configured in each PWM generator block. It typically makes sense to use
the synchronous update mechanism across PWM generator blocks when the timers in those blocks
are synchronized, though this is not required in order for this mechanism to function properly.
18.2.7 Fault Conditions
There are two external conditions that affect the PWM block; the signal input on the Fault pin and
the stalling of the controller by a debugger. There are two mechanisms available to handle such
conditions: the output signals can be forced into an inactive state and/or the PWM timers can be
stopped.
Each output signal has a fault bit. If set, a fault input signal causes the corresponding output signal
to go into the inactive state. If the inactive state is a safe condition for the signal to be in for an
extended period of time, this keeps the output signal from driving the outside world in a dangerous
manner during the fault condition. A fault condition can also generate a controller interrupt.
Each PWM generator can also be configured to stop counting during a stall condition. The user can
select for the counters to run until they reach zero then stop, or to continue counting and reloading.
A stall condition does not generate a controller interrupt.
18.2.8 Output Control Block
With each PWM generator block producing two raw PWM signals, the output control block takes
care of the final conditioning of the PWM signals before they go to the pins. Via a single register,
the set of PWM signals that are actually enabled to the pins can be modified; this can be used, for
example, to perform commutation of a brushless DC motor with a single register write (and without
modifying the individual PWM generators, which are modified by the feedback control loop). Similarly,
fault control can disable any of the PWM signals as well. A final inversion can be applied to any of
the PWM signals, making them active Low instead of the default active High.
18.3 Initialization and Configuration
The following example shows how to initialize the PWM Generator 0 with a 25-KHz frequency, and
with a 25% duty cycle on the PWM0 pin and a 75% duty cycle on the PWM1 pin. This example assumes
the system clock is 20 MHz.
1. Enable the PWM clock by writing a value of 0x0010.0000 to the RCGC0 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register.
4. Configure the Run-Mode Clock Configuration (RCC) register in the System Control module
to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000).
5. Configure the PWM generator for countdown mode with immediate updates to the parameters.
■ Write the PWM0CTL register with a value of 0x0000.0000.
■ Write the PWM0GENA register with a value of 0x0000.008C.
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■ Write the PWM0GENB register with a value of 0x0000.080C.
6. Set the period. For a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM
clock source is 10 MHz; the system clock divided by 2. This translates to 400 clock ticks per
period. Use this value to set the PWM0LOAD register. In Count-Down mode, set the Load field
in the PWM0LOAD register to the requested period minus one.
■ Write the PWM0LOAD register with a value of 0x0000.018F.
7. Set the pulse width of the PWM0 pin for a 25% duty cycle.
■ Write the PWM0CMPA register with a value of 0x0000.012B.
8. Set the pulse width of the PWM1 pin for a 75% duty cycle.
■ Write the PWM0CMPB register with a value of 0x0000.0063.
9. Start the timers in PWM generator 0.
■ Write the PWM0CTL register with a value of 0x0000.0001.
10. Enable PWM outputs.
■ Write the PWMENABLE register with a value of 0x0000.0003.
18.4 Register Map
Table 18-1 on page 471 lists the PWM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the PWM base address of 0x4002.8000.
Table 18-1. PWM Register Map
See
Offset Name Type Reset Description page
0x000 PWMCTL R/W 0x0000.0000 PWM Master Control 473
0x004 PWMSYNC R/W 0x0000.0000 PWM Time Base Sync 474
0x008 PWMENABLE R/W 0x0000.0000 PWM Output Enable 475
0x00C PWMINVERT R/W 0x0000.0000 PWM Output Inversion 476
0x010 PWMFAULT R/W 0x0000.0000 PWM Output Fault 477
0x014 PWMINTEN R/W 0x0000.0000 PWM Interrupt Enable 478
0x018 PWMRIS RO 0x0000.0000 PWM Raw Interrupt Status 479
0x01C PWMISC R/W1C 0x0000.0000 PWM Interrupt Status and Clear 480
0x020 PWMSTATUS RO 0x0000.0000 PWM Status 481
0x040 PWM0CTL R/W 0x0000.0000 PWM0 Control 482
0x044 PWM0INTEN R/W 0x0000.0000 PWM0 Interrupt and Trigger Enable 484
0x048 PWM0RIS RO 0x0000.0000 PWM0 Raw Interrupt Status 486
0x04C PWM0ISC R/W1C 0x0000.0000 PWM0 Interrupt Status and Clear 487
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See
Offset Name Type Reset Description page
0x050 PWM0LOAD R/W 0x0000.0000 PWM0 Load 488
0x054 PWM0COUNT RO 0x0000.0000 PWM0 Counter 489
0x058 PWM0CMPA R/W 0x0000.0000 PWM0 Compare A 490
0x05C PWM0CMPB R/W 0x0000.0000 PWM0 Compare B 491
0x060 PWM0GENA R/W 0x0000.0000 PWM0 Generator A Control 492
0x064 PWM0GENB R/W 0x0000.0000 PWM0 Generator B Control 495
0x068 PWM0DBCTL R/W 0x0000.0000 PWM0 Dead-Band Control 498
0x06C PWM0DBRISE R/W 0x0000.0000 PWM0 Dead-Band Rising-Edge Delay 499
0x070 PWM0DBFALL R/W 0x0000.0000 PWM0 Dead-Band Falling-Edge-Delay 500
0x080 PWM1CTL R/W 0x0000.0000 PWM1 Control 482
0x084 PWM1INTEN R/W 0x0000.0000 PWM1 Interrupt and Trigger Enable 484
0x088 PWM1RIS RO 0x0000.0000 PWM1 Raw Interrupt Status 486
0x08C PWM1ISC R/W1C 0x0000.0000 PWM1 Interrupt Status and Clear 487
0x090 PWM1LOAD R/W 0x0000.0000 PWM1 Load 488
0x094 PWM1COUNT RO 0x0000.0000 PWM1 Counter 489
0x098 PWM1CMPA R/W 0x0000.0000 PWM1 Compare A 490
0x09C PWM1CMPB R/W 0x0000.0000 PWM1 Compare B 491
0x0A0 PWM1GENA R/W 0x0000.0000 PWM1 Generator A Control 492
0x0A4 PWM1GENB R/W 0x0000.0000 PWM1 Generator B Control 495
0x0A8 PWM1DBCTL R/W 0x0000.0000 PWM1 Dead-Band Control 498
0x0AC PWM1DBRISE R/W 0x0000.0000 PWM1 Dead-Band Rising-Edge Delay 499
0x0B0 PWM1DBFALL R/W 0x0000.0000 PWM1 Dead-Band Falling-Edge-Delay 500
18.5 Register Descriptions
The remainder of this section lists and describes the PWM registers, in numerical order by address
offset.
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Register 1: PWM Master Control (PWMCTL), offset 0x000
This register provides master control over the PWM generation blocks.
PWM Master Control (PWMCTL)
Base 0x4002.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GlobalSync1 GlobalSync0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Update PWM Generator 1
Same as GlobalSync0 but for PWM generator 1.
1 GlobalSync1 R/W 0
Update PWM Generator 0
Setting this bit causes any queued update to a load or comparator
register in PWM generator 0 to be applied the next time the
corresponding counter becomes zero. This bit automatically clears when
the updates have completed; it cannot be cleared by software.
0 GlobalSync0 R/W 0
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Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004
This register provides a method to perform synchronization of the counters in the PWM generation
blocks. Writing a bit in this register to 1 causes the specified counter to reset back to 0; writing
multiple bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred;
reading them back as zero indicates that the synchronization has completed.
PWM Time Base Sync (PWMSYNC)
Base 0x4002.8000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Sync1 Sync0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Reset Generator 1 Counter
Performs a reset of the PWM generator 1 counter.
1 Sync1 R/W 0
Reset Generator 0 Counter
Performs a reset of the PWM generator 0 counter.
0 Sync0 R/W 0
474 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Register 3: PWM Output Enable (PWMENABLE), offset 0x008
This register provides a master control of which generated PWM signals are output to device pins.
By disabling a PWM output, the generation process can continue (for example, when the time bases
are synchronized) without driving PWM signals to the pins. When bits in this register are set, the
corresponding PWM signal is passed through to the output stage, which is controlled by the
PWMINVERT register. When bits are not set, the PWM signal is replaced by a zero value which is
also passed to the output stage.
PWM Output Enable (PWMENABLE)
Base 0x4002.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWM3En PWM2En PWM1En PWM0En
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
PWM3 Output Enable
When set, allows the generated PWM3 signal to be passed to the device
pin.
3 PWM3En R/W 0
PWM2 Output Enable
When set, allows the generated PWM2 signal to be passed to the device
pin.
2 PWM2En R/W 0
PWM1 Output Enable
When set, allows the generated PWM1 signal to be passed to the device
pin.
1 PWM1En R/W 0
PWM0 Output Enable
When set, allows the generated PWM0 signal to be passed to the device
pin.
0 PWM0En R/W 0
November 30, 2007 475
Preliminary
LM3S6952 Microcontroller
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C
This register provides a master control of the polarity of the PWM signals on the device pins. The
PWM signals generated by the PWM generator are active High; they can optionally be made active
Low via this register. Disabled PWM channels are also passed through the output inverter (if so
configured) so that inactive channels maintain the correct polarity.
PWM Output Inversion (PWMINVERT)
Base 0x4002.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWM3Inv PWM2Inv PWM1Inv PWM0Inv
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
Invert PWM3 Signal
When set, the generated PWM3 signal is inverted.
3 PWM3Inv R/W 0
Invert PWM2 Signal
When set, the generated PWM2 signal is inverted.
2 PWM2Inv R/W 0
Invert PWM1 Signal
When set, the generated PWM1 signal is inverted.
1 PWM1Inv R/W 0
Invert PWM0 Signal
When set, the generated PWM0 signal is inverted.
0 PWM0Inv R/W 0
476 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Register 5: PWM Output Fault (PWMFAULT), offset 0x010
This register controls the behavior of the PWM outputs in the presence of fault conditions. Both the
fault input and debug events are considered fault conditions. On a fault condition, each PWM signal
can either be passed through unmodified or driven Low. For outputs that are configured for
pass-through, the debug event handling on the corresponding PWM generator also determines if
the PWM signal continues to be generated.
Fault condition control happens before the output inverter, so PWM signals driven Low on fault are
inverted if the channel is configured for inversion (therefore, the pin is driven High on a fault condition).
PWM Output Fault (PWMFAULT)
Base 0x4002.8000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Fault3 Fault2 Fault1 Fault0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
PWM3 Driven Low on Fault
When set, the PWM3 output signal is driven Low on a fault condition.
3 Fault3 R/W 0
PWM2 Driven Low on Fault
When set, the PWM2 output signal is driven Low on a fault condition.
2 Fault2 R/W 0
PWM1 Driven Low on Fault
When set, the PWM1 output signal is driven Low on a fault condition.
1 Fault1 R/W 0
PWM0 Driven Low on Fault
When set, the PWM0 output signal is driven Low on a fault condition.
0 Fault0 R/W 0
November 30, 2007 477
Preliminary
LM3S6952 Microcontroller
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014
This register controls the global interrupt generation capabilities of the PWM module. The events
that can cause an interrupt are the fault input and the individual interrupts from the PWM generators.
PWM Interrupt Enable (PWMINTEN)
Base 0x4002.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved IntFault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntPWM1 IntPWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:17 reserved RO 0x00
Fault Interrupt Enable
When 1, an interrupt occurs when the fault input is asserted.
16 IntFault R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:2 reserved RO 0x00
PWM1 Interrupt Enable
When 1, an interrupt occurs when the PWM generator 1 block asserts
an interrupt.
1 IntPWM1 R/W 0
PWM0 Interrupt Enable
When 1, an interrupt occurs when the PWM generator 0 block asserts
an interrupt.
0 IntPWM0 R/W 0
478 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller. The fault interrupt is latched on detection;
it must be cleared through the PWM Interrupt Status and Clear (PWMISC) register (see page 480).
The PWM generator interrupts simply reflect the status of the PWM generators; they are cleared
via the interrupt status register in the PWM generator blocks. Bits set to 1 indicate the events that
are active; a zero bit indicates that the event in question is not active.
PWM Raw Interrupt Status (PWMRIS)
Base 0x4002.8000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved IntFault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntPWM1 IntPWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:17 reserved RO 0x00
Fault Interrupt Asserted
Indicates that the fault input has been asserted.
16 IntFault RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:2 reserved RO 0x00
PWM1 Interrupt Asserted
Indicates that the PWM generator 1 block is asserting its interrupt.
1 IntPWM1 RO 0
PWM0 Interrupt Asserted
Indicates that the PWM generator 0 block is asserting its interrupt.
0 IntPWM0 RO 0
November 30, 2007 479
Preliminary
LM3S6952 Microcontroller
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C
This register provides a summary of the interrupt status of the individual PWM generator blocks. A
bit set to 1 indicates that the corresponding generator block is asserting an interrupt. The individual
interrupt status registers in each block must be consulted to determine the reason for the interrupt,
and used to clear the interrupt. For the fault interrupt, a write of 1 to that bit position clears the latched
interrupt status.
PWM Interrupt Status and Clear (PWMISC)
Base 0x4002.8000
Offset 0x01C
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved IntFault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntPWM1 IntPWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:17 reserved RO 0x00
Fault Interrupt Asserted
Indicates if the fault input is asserting an interrupt.
16 IntFault R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:2 reserved RO 0x00
PWM1 Interrupt Status
Indicates if the PWM generator 1 block is asserting an interrupt.
1 IntPWM1 RO 0
PWM0 Interrupt Status
Indicates if the PWM generator 0 block is asserting an interrupt.
0 IntPWM0 RO 0
480 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Register 9: PWM Status (PWMSTATUS), offset 0x020
This register provides the status of the Fault input signal.
PWM Status (PWMSTATUS)
Base 0x4002.8000
Offset 0x020
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Fault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Fault Interrupt Status
When set to 1, indicates the fault input is asserted.
0 Fault RO 0
November 30, 2007 481
Preliminary
LM3S6952 Microcontroller
Register 10: PWM0 Control (PWM0CTL), offset 0x040
Register 11: PWM1 Control (PWM1CTL), offset 0x080
These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator
0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable
mode are all controlled via these registers. The blocks produce the PWM signals, which can be
either two independent PWM signals (from the same counter), or a paired set of PWM signals with
dead-band delays added.
The PWM0 block produces the PWM0 and PWM1 outputs, and the PWM1 block produces the
PWM2 and PWM3 outputs.
PWM0 Control (PWM0CTL)
Base 0x4002.8000
Offset 0x040
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CmpBUpdCmpAUpd LoadUpd Debug Mode Enable
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
Comparator B Update Mode
Same as CmpAUpd but for the comparator B register.
5 CmpBUpd R/W 0
Comparator A Update Mode
The Update mode for the comparator A register. If 0, updates to the
register are reflected to the comparator the next time the counter is 0.
If 1, updates to the register are delayed until the next time the counter
is 0 after a synchronous update has been requested through the PWM
Master Control (PWMCTL) register (see page 473).
4 CmpAUpd R/W 0
Load Register Update Mode
The Update mode for the load register. If 0, updates to the register are
reflected to the counter the next time the counter is 0. If 1, updates to
the register are delayed until the next time the counter is 0 after a
synchronous update has been requested through the PWM Master
Control (PWMCTL) register.
3 LoadUpd R/W 0
Debug Mode
The behavior of the counter in Debug mode. If 0, the counter stops
running when it next reaches 0, and continues running again when no
longer in Debug mode. If 1, the counter always runs.
2 Debug R/W 0
482 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Bit/Field Name Type Reset Description
Counter Mode
The mode for the counter. If 0, the counter counts down from the load
value to 0 and then wraps back to the load value (Count-Down mode).
If 1, the counter counts up from 0 to the load value, back down to 0, and
then repeats (Count-Up/Down mode).
1 Mode R/W 0
PWM Block Enable
Master enable for the PWM generation block. If 0, the entire block is
disabled and not clocked. If 1, the block is enabled and produces PWM
signals.
0 Enable R/W 0
November 30, 2007 483
Preliminary
LM3S6952 Microcontroller
Register 12: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044
Register 13: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084
These registers control the interrupt and ADC trigger generation capabilities of the PWM generators
(PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an
interrupt or an ADC trigger are:
■ The counter being equal to the load register
■ The counter being equal to zero
■ The counter being equal to the comparator A register while counting up
■ The counter being equal to the comparator A register while counting down
■ The counter being equal to the comparator B register while counting up
■ The counter being equal to the comparator B register while counting down
Any combination of these events can generate either an interruptor an ADC trigger, though no
determination can be made as to the actual event that caused an ADC trigger if more than one is
specified.
PWM0 Interrupt and Trigger Enable (PWM0INTEN)
Base 0x4002.8000
Offset 0x044
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero reserved IntCmpBDIntCmpBUIntCmpADIntCmpAU IntCntLoad IntCntZero
Type RO RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x00
Trigger for Counter=Comparator B Down
When 1, a trigger pulse is output when the counter matches the
comparator B value and the counter is counting down.
13 TrCmpBD R/W 0
Trigger for Counter=Comparator B Up
When 1, a trigger pulse is output when the counter matches the
comparator B value and the counter is counting up.
12 TrCmpBU R/W 0
Trigger for Counter=Comparator A Down
When 1, a trigger pulse is output when the counter matches the
comparator A value and the counter is counting down.
11 TrCmpAD R/W 0
484 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Bit/Field Name Type Reset Description
Trigger for Counter=Comparator A Up
When 1, a trigger pulse is output when the counter matches the
comparator A value and the counter is counting up.
10 TrCmpAU R/W 0
Trigger for Counter=Load
When 1, a trigger pulse is output when the counter matches the
PWMnLOAD register.
9 TrCntLoad R/W 0
Trigger for Counter=0
When 1, a trigger pulse is output when the counter is 0.
8 TrCntZero R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0x0
Interrupt for Counter=Comparator B Down
When 1, an interrupt occurs when the counter matches the comparator B
value and the counter is counting down.
5 IntCmpBD R/W 0
Interrupt for Counter=Comparator B Up
When 1, an interrupt occurs when the counter matches the comparator B
value and the counter is counting up.
4 IntCmpBU R/W 0
Interrupt for Counter=Comparator A Down
When 1, an interrupt occurs when the counter matches the comparator A
value and the counter is counting down.
3 IntCmpAD R/W 0
Interrupt for Counter=Comparator A Up
When 1, an interrupt occurs when the counter matches the comparator A
value and the counter is counting up.
2 IntCmpAU R/W 0
Interrupt for Counter=Load
When 1, an interrupt occurs when the counter matches the PWMnLOAD
register.
1 IntCntLoad R/W 0
Interrupt for Counter=0
When 1, an interrupt occurs when the counter is 0.
0 IntCntZero R/W 0
November 30, 2007 485
Preliminary
LM3S6952 Microcontroller
Register 14: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048
Register 15: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088
These registers provide the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0
block, and so on). Bits set to 1 indicate the latched events that have occurred; a 0 bit indicates that
the event in question has not occurred.
PWM0 Raw Interrupt Status (PWM0RIS)
Base 0x4002.8000
Offset 0x048
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntCmpBDIntCmpBUIntCmpADIntCmpAU IntCntLoad IntCntZero
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
Comparator B Down Interrupt Status
Indicates that the counter has matched the comparator B value while
counting down.
5 IntCmpBD RO 0
Comparator B Up Interrupt Status
Indicates that the counter has matched the comparator B value while
counting up.
4 IntCmpBU RO 0
Comparator A Down Interrupt Status
Indicates that the counter has matched the comparator A value while
counting down.
3 IntCmpAD RO 0
Comparator A Up Interrupt Status
Indicates that the counter has matched the comparator A value while
counting up.
2 IntCmpAU RO 0
Counter=Load Interrupt Status
Indicates that the counter has matched the PWMnLOAD register.
1 IntCntLoad RO 0
Counter=0 Interrupt Status
Indicates that the counter has matched 0.
0 IntCntZero RO 0
486 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Register 16: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
Register 17: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C
These registers provide the current set of interrupt sources that are asserted to the controller
(PWM0ISC controls the PWM generator 0 block, and so on). Bits set to 1 indicate the latched events
that have occurred; a 0 bit indicates that the event in question has not occurred. These are R/W1C
registers; writing a 1 to a bit position clears the corresponding interrupt reason.
PWM0 Interrupt Status and Clear (PWM0ISC)
Base 0x4002.8000
Offset 0x04C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntCmpBDIntCmpBUIntCmpADIntCmpAU IntCntLoad IntCntZero
Type RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
Comparator B Down Interrupt
Indicates that the counter has matched the comparator B value while
counting down.
5 IntCmpBD R/W1C 0
Comparator B Up Interrupt
Indicates that the counter has matched the comparator B value while
counting up.
4 IntCmpBU R/W1C 0
Comparator A Down Interrupt
Indicates that the counter has matched the comparator A value while
counting down.
3 IntCmpAD R/W1C 0
Comparator A Up Interrupt
Indicates that the counter has matched the comparator A value while
counting up.
2 IntCmpAU R/W1C 0
Counter=Load Interrupt
Indicates that the counter has matched the PWMnLOAD register.
1 IntCntLoad R/W1C 0
Counter=0 Interrupt
Indicates that the counter has matched 0.
0 IntCntZero R/W1C 0
November 30, 2007 487
Preliminary
LM3S6952 Microcontroller
Register 18: PWM0 Load (PWM0LOAD), offset 0x050
Register 19: PWM1 Load (PWM1LOAD), offset 0x090
These registers contain the load value for the PWM counter (PWM0LOAD controls the PWM
generator 0 block, and so on). Based on the counter mode, either this value is loaded into the counter
after it reaches zero, or it is the limit of up-counting after which the counter decrements back to zero.
If the Load Value Update mode is immediate, this value is used the next time the counter reaches
zero; if the mode is synchronous, it is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 473).
If this register is re-written before the actual update occurs, the previous value is never used and is
lost.
PWM0 Load (PWM0LOAD)
Base 0x4002.8000
Offset 0x050
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Load
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Counter Load Value
The counter load value.
15:0 Load R/W 0
488 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Register 20: PWM0 Counter (PWM0COUNT), offset 0x054
Register 21: PWM1 Counter (PWM1COUNT), offset 0x094
These registers contain the current value of the PWM counter (PWM0COUNT is the value of the
PWM generator 0 block, and so on). When this value matches the load register, a pulse is output;
this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers, see
page 492 and page 495) or drive an interrupt or ADC trigger (via the PWMnINTEN register, see
page 484). A pulse with the same capabilities is generated when this value is zero.
PWM0 Counter (PWM0COUNT)
Base 0x4002.8000
Offset 0x054
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Count
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Counter Value
The current value of the counter.
15:0 Count RO 0x00
November 30, 2007 489
Preliminary
LM3S6952 Microcontroller
Register 22: PWM0 Compare A (PWM0CMPA), offset 0x058
Register 23: PWM1 Compare A (PWM1CMPA), offset 0x098
These registers contain a value to be compared against the counter (PWM0CMPA controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this
can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an
interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than
the PWMnLOAD register (see page 488), then no pulse is ever output.
If the comparator A update mode is immediate (based on the CmpAUpd bit in the PWMnCTL register),
then this 16-bit CompA value is used the next time the counter reaches zero. If the update mode is
synchronous, it is used the next time the counter reaches zero after a synchronous update has been
requested through the PWM Master Control (PWMCTL) register (see page 473). If this register is
rewritten before the actual update occurs, the previous value is never used and is lost.
PWM0 Compare A (PWM0CMPA)
Base 0x4002.8000
Offset 0x058
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CompA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Comparator A Value
The value to be compared against the counter.
15:0 CompA R/W 0x00
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Register 24: PWM0 Compare B (PWM0CMPB), offset 0x05C
Register 25: PWM1 Compare B (PWM1CMPB), offset 0x09C
These registers contain a value to be compared against the counter (PWM0CMPB controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this
can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an
interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than
the PWMnLOAD register, then no pulse is ever output.
IF the comparator B update mode is immediate (based on the CmpBUpd bit in the PWMnCTL
register), then this 16-bit CompB value is used the next time the counter reaches zero. If the update
mode is synchronous, it is used the next time the counter reaches zero after a synchronous update
has been requested through the PWM Master Control (PWMCTL) register (see page 473). If this
register is rewritten before the actual update occurs, the previous value is never used and is lost.
PWM0 Compare B (PWM0CMPB)
Base 0x4002.8000
Offset 0x05C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CompB
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Comparator B Value
The value to be compared against the counter.
15:0 CompB R/W 0x00
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Register 26: PWM0 Generator A Control (PWM0GENA), offset 0x060
Register 27: PWM1 Generator A Control (PWM1GENA), offset 0x0A0
These registers control the generation of the PWMnA signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENA controls the PWM generator 0 block, and so on). When the counter is running in
Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six
occur. These events provide great flexibility in the positioning and duty cycle of the PWM signal that
is produced.
The PWM0GENA register controls generation of the PWM0A signal; PWM1GENA, the PWM1A signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare A action is taken and the compare B action is ignored.
PWM0 Generator A Control (PWM0GENA)
Base 0x4002.8000
Offset 0x060
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Action for Comparator B Down
The action to be taken when the counter matches comparator B while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
11:10 ActCmpBD R/W 0x0
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Bit/Field Name Type Reset Description
Action for Comparator B Up
The action to be taken when the counter matches comparator B while
counting up. Occurs only when the Mode bit in the PWMnCTL register
(see page 482) is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
9:8 ActCmpBU R/W 0x0
Action for Comparator A Down
The action to be taken when the counter matches comparator A while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
7:6 ActCmpAD R/W 0x0
Action for Comparator A Up
The action to be taken when the counter matches comparator A while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
5:4 ActCmpAU R/W 0x0
Action for Counter=Load
The action to be taken when the counter matches the load value.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
3:2 ActLoad R/W 0x0
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Bit/Field Name Type Reset Description
Action for Counter=0
The action to be taken when the counter is zero.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
1:0 ActZero R/W 0x0
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Register 28: PWM0 Generator B Control (PWM0GENB), offset 0x064
Register 29: PWM1 Generator B Control (PWM1GENB), offset 0x0A4
These registers control the generation of the PWMnB signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENB controls the PWM generator 0 block, and so on). When the counter is running in
Down mode, only four of these events occur; when running in Up/Down mode, all six occur. These
events provide great flexibility in the positioning and duty cycle of the PWM signal that is produced.
The PWM0GENB register controls generation of the PWM0B signal; PWM1GENB, the PWM1B signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare B action is taken and the compare A action is ignored.
PWM0 Generator B Control (PWM0GENB)
Base 0x4002.8000
Offset 0x064
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Action for Comparator B Down
The action to be taken when the counter matches comparator B while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
11:10 ActCmpBD R/W 0x0
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Bit/Field Name Type Reset Description
Action for Comparator B Up
The action to be taken when the counter matches comparator B while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
9:8 ActCmpBU R/W 0x0
Action for Comparator A Down
The action to be taken when the counter matches comparator A while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
7:6 ActCmpAD R/W 0x0
Action for Comparator A Up
The action to be taken when the counter matches comparator A while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
5:4 ActCmpAU R/W 0x0
Action for Counter=Load
The action to be taken when the counter matches the load value.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
3:2 ActLoad R/W 0x0
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Bit/Field Name Type Reset Description
Action for Counter=0
The action to be taken when the counter is 0.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
1:0 ActZero R/W 0x0
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Register 30: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068
Register 31: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8
The PWM0DBCTL register controls the dead-band generator, which produces the PWM0 and PWM1
signals based on the PWM0A and PWM0B signals. When disabled, the PWM0A signal passes through
to the PWM0 signal and the PWM0B signal passes through to the PWM1 signal. When enabled and
inverting the resulting waveform, the PWM0B signal is ignored; the PWM0 signal is generated by
delaying the rising edge(s) of the PWM0A signal by the value in the PWM0DBRISE register (see
page 499), and the PWM1 signal is generated by delaying the falling edge(s) of the PWM0A signal by
the value in the PWM0DBFALL register (see page 500). In a similar manner, PWM2 and PWM3 are
produced from the PWM1A and PWM1B signals.
PWM0 Dead-Band Control (PWM0DBCTL)
Base 0x4002.8000
Offset 0x068
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Enable
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Dead-Band Generator Enable
When set, the dead-band generator inserts dead bands into the output
signals; when clear, it simply passes the PWM signals through.
0 Enable R/W 0
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Register 32: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset
0x06C
Register 33: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset
0x0AC
The PWM0DBRISE register contains the number of clock ticks to delay the rising edge of the PWM0A
signal when generating the PWM0 signal. If the dead-band generator is disabled through the
PWMnDBCTL register, the PWM0DBRISE register is ignored. If the value of this register is larger
than the width of a High pulse on the input PWM signal, the rising-edge delay consumes the entire
High time of the signal, resulting in no High time on the output. Care must be taken to ensure that
the input High time always exceeds the rising-edge delay. In a similar manner, PWM2 is generated
from PWM1A with its rising edge delayed.
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE)
Base 0x4002.8000
Offset 0x06C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RiseDelay
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Dead-Band Rise Delay
The number of clock ticks to delay the rising edge.
11:0 RiseDelay R/W 0
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Register 34: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset
0x070
Register 35: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset
0x0B0
The PWM0DBFALL register contains the number of clock ticks to delay the falling edge of the
PWM0A signal when generating the PWM1 signal. If the dead-band generator is disabled, this register
is ignored. If the value of this register is larger than the width of a Low pulse on the input PWM
signal, the falling-edge delay consumes the entire Low time of the signal, resulting in no Low time
on the output. Care must be taken to ensure that the input Low time always exceeds the falling-edge
delay. In a similar manner, PWM3 is generated from PWM1A with its falling edge delayed.
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL)
Base 0x4002.8000
Offset 0x070
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved FallDelay
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Dead-Band Fall Delay
The number of clock ticks to delay the falling edge.
11:0 FallDelay R/W 0x00
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Pulse Width Modulator (PWM)
19 Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
The Stellaris® quadrature encoder interface (QEI) module interprets the code produced by a
quadrature encoder wheel to integrate position over time and determine direction of rotation. In
addition, it can capture a running estimate of the velocity of the encoder wheel.
The Stellaris® quadrature encoder has the following features:
■ Position integrator that tracks the encoder position
■ Velocity capture using built-in timer
■ Interrupt generation on:
– Index pulse
– Velocity-timer expiration
– Direction change
– Quadrature error detection
19.1 Block Diagram
Figure 19-1 on page 501 provides a block diagram of a Stellaris® QEI module.
Figure 19-1. QEI Block Diagram
Quadrature
Encoder
Velocity
Predivider
Interrupt Control
QEIINTEN
QEIRIS
QEIISC
Position Integrator
QEIMAXPOS
QEIPOS
Velocity Accumulator
QEICOUNT
QEISPEED
Velocity Timer
QEILOAD
QEITIME
PhA
PhB
IDX
clk
dir
Interrupt
Control & Status
QEICTL
QEISTAT
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19.2 Functional Description
The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate
position over time and determine direction of rotation. In addition, it can capture a running estimate
of the velocity of the encoder wheel.
The position integrator and velocity capture can be independently enabled, though the position
integrator must be enabled before the velocity capture can be enabled. The two phase signals, PhA
and PhB, can be swapped before being interpreted by the QEI module to change the meaning of
forward and backward, and to correct for miswiring of the system. Alternatively, the phase signals
can be interpreted as a clock and direction signal as output by some encoders.
The QEI module supports two modes of signal operation: quadrature phase mode and clock/direction
mode. In quadrature phase mode, the encoder produces two clocks that are 90 degrees out of
phase; the edge relationship is used to determine the direction of rotation. In clock/direction mode,
the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction
of rotation. This mode is determined by the SigMode bit of the QEI Control (QEICTL) register (see
page 506).
When the QEI module is set to use the quadrature phase mode (SigMode bit equals zero), the
capture mode for the position integrator can be set to update the position counter on every edge of
the PhA signal or to update on every edge of both PhA and PhB. Updating the position counter on
every PhA and PhB provides more positional resolution at the cost of less range in the positional
counter.
When edges on PhA lead edges on PhB , the position counter is incremented. When edges on PhB
lead edges on PhA , the position counter is decremented. When a rising and falling edge pair is
seen on one of the phases without any edges on the other, the direction of rotation has changed.
The positional counter is automatically reset on one of two conditions: sensing the index pulse or
reaching the maximum position value. Which mode is determined by the ResMode bit of the QEI
Control (QEICTL) register.
When ResMode is 0, the positional counter is reset when the index pulse is sensed. This limits the
positional counter to the values [0:N-1], where N is the number of phase edges in a full revolution
of the encoder wheel. The QEIMAXPOS register must be programmed with N-1 so that the reverse
direction from position 0 can move the position counter to N-1. In this mode, the position register
contains the absolute position of the encoder relative to the index (or home) position once an index
pulse has been seen.
When ResMode is 1, the positional counter is constrained to the range [0:M], where M is the
programmable maximum value. The index pulse is ignored by the positional counter in this mode.
The velocity capture has a configurable timer and a count register. It counts the number of phase
edges (using the same configuration as for the position integrator) in a given time period. The edge
count from the previous time period is available to the controller via the QEISPEED register, while
the edge count for the current time period is being accumulated in the QEICOUNT register. As soon
as the current time period is complete, the total number of edges counted in that time period is made
available in the QEISPEED register (losing the previous value), the QEICOUNT is reset to 0, and
counting commences on a new time period. The number of edges counted in a given time period
is directly proportional to the velocity of the encoder.
Figure 19-2 on page 503 shows how the Stellaris® quadrature encoder converts the phase input
signals into clock pulses, the direction signal, and how the velocity predivider operates (in Divide
by 4 mode).
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Figure 19-2. Quadrature Encoder and Velocity Predivider Operation
-1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+1 +1 +1 +1 +1 +1 +1 +1
PhA
PhB
clk
clkdiv
dir
pos
rel
The period of the timer is configurable by specifying the load value for the timer in the QEILOAD
register. When the timer reaches zero, an interrupt can be triggered, and the hardware reloads the
timer with the QEILOAD value and continues to count down. At lower encoder speeds, a longer
timer period is needed to be able to capture enough edges to have a meaningful result. At higher
encoder speeds, both a shorter timer period and/or the velocity predivider can be used.
The following equation converts the velocity counter value into an rpm value:
rpm = (clock * (2 ^ VelDiv) * Speed * 60) ÷ (Load * ppr * edges)
where:
clock is the controller clock rate
ppr is the number of pulses per revolution of the physical encoder
edges is 2 or 4, based on the capture mode set in the QEICTL register (2 for CapMode set to 0 and
4 for CapMode set to 1)
For example, consider a motor running at 600 rpm. A 2048 pulse per revolution quadrature encoder
is attached to the motor, producing 8192 phase edges per revolution. With a velocity predivider of
÷1 (VelDiv set to 0) and clocking on both PhA and PhB edges, this results in 81,920 pulses per
second (the motor turns 10 times per second). If the timer were clocked at 10,000 Hz, and the load
value was 2,500 (¼ of a second), it would count 20,480 pulses per update. Using the above equation:
rpm = (10000 * 1 * 20480 * 60) ÷ (2500 * 2048 * 4) = 600 rpm
Now, consider that the motor is sped up to 3000 rpm. This results in 409,600 pulses per second,
or 102,400 every ¼ of a second. Again, the above equation gives:
rpm = (10000 * 1 * 102400 * 60) ÷ (2500 * 2048 * 4) = 3000 rpm
Care must be taken when evaluating this equation since intermediate values may exceed the capacity
of a 32-bit integer. In the above examples, the clock is 10,000 and the divider is 2,500; both could
be predivided by 100 (at compile time if they are constants) and therefore be 100 and 25. In fact, if
they were compile-time constants, they could also be reduced to a simple multiply by 4, cancelled
by the ÷4 for the edge-count factor.
Important: Reducing constant factors at compile time is the best way to control the intermediate
values of this equation, as well as reducing the processing requirement of computing
this equation.
The division can be avoided by selecting a timer load value such that the divisor is a power of 2; a
simple shift can therefore be done in place of the division. For encoders with a power of 2 pulses
per revolution, this is a simple matter of selecting a power of 2 load value. For other encoders, a
load value must be selected such that the product is very close to a power of two. For example, a
100 pulse per revolution encoder could use a load value of 82, resulting in 32,800 as the divisor,
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which is 0.09% above 214; in this case a shift by 15 would be an adequate approximation of the
divide in most cases. If absolute accuracy were required, the controller’s divide instruction could be
used.
The QEI module can produce a controller interrupt on several events: phase error, direction change,
reception of the index pulse, and expiration of the velocity timer. Standard masking, raw interrupt
status, interrupt status, and interrupt clear capabilities are provided.
19.3 Initialization and Configuration
The following example shows how to configure the Quadrature Encoder module to read back an
absolute position:
1. Enable the QEI clock by writing a value of 0x0000.0100 to the RCGC1 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register.
4. Configure the quadrature encoder to capture edges on both signals and maintain an absolute
position by resetting on index pulses. Using a 1000-line encoder at four edges per line, there
are 4000 pulses per revolution; therefore, set the maximum position to 3999 (0xF9F) since the
count is zero-based.
■ Write the QEICTL register with the value of 0x0000.0018.
■ Write the QEIMAXPOS register with the value of 0x0000.0F9F.
5. Enable the quadrature encoder by setting bit 0 of the QEICTL register.
6. Delay for some time.
7. Read the encoder position by reading the QEIPOS register value.
19.4 Register Map
Table 19-1 on page 504 lists the QEI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the module’s base address:
■ QEI0: 0x4002.C000
Table 19-1. QEI Register Map
See
Offset Name Type Reset Description page
0x000 QEICTL R/W 0x0000.0000 QEI Control 506
0x004 QEISTAT RO 0x0000.0000 QEI Status 508
0x008 QEIPOS R/W 0x0000.0000 QEI Position 509
0x00C QEIMAXPOS R/W 0x0000.0000 QEI Maximum Position 510
0x010 QEILOAD R/W 0x0000.0000 QEI Timer Load 511
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See
Offset Name Type Reset Description page
0x014 QEITIME RO 0x0000.0000 QEI Timer 512
0x018 QEICOUNT RO 0x0000.0000 QEI Velocity Counter 513
0x01C QEISPEED RO 0x0000.0000 QEI Velocity 514
0x020 QEIINTEN R/W 0x0000.0000 QEI Interrupt Enable 515
0x024 QEIRIS RO 0x0000.0000 QEI Raw Interrupt Status 516
0x028 QEIISC R/W1C 0x0000.0000 QEI Interrupt Status and Clear 517
19.5 Register Descriptions
The remainder of this section lists and describes the QEI registers, in numerical order by address
offset.
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Register 1: QEI Control (QEICTL), offset 0x000
This register contains the configuration of the QEI module. Separate enables are provided for the
quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in
order to capture the velocity, but the velocity does not need to be captured in applications that do
not need it. The phase signal interpretation, phase swap, Position Update mode, Position Reset
mode, and velocity predivider are all set via this register.
QEI Control (QEICTL)
QEI0 base: 0x4002.C000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved STALLEN INVI INVB INVA VelDiv VelEn ResMode CapMode SigMode Swap Enable
Type RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:13 reserved RO 0x00
Stall QEI
When set, the QEI stalls when the microcontroller asserts Halt.
12 STALLEN R/W 0
Invert Index Pulse
When set , the input Index Pulse is inverted.
11 INVI R/W 0
Invert PhB
When set, the PhB input is inverted.
10 INVB R/W 0
Invert PhA
When set, the PhA input is inverted.
9 INVA R/W 0
Predivide Velocity
A predivider of the input quadrature pulses before being applied to the
QEICOUNT accumulator. This field can be set to the following values:
Value Predivider
0x0 ÷1
0x1 ÷2
0x2 ÷4
0x3 ÷8
0x4 ÷16
0x5 ÷32
0x6 ÷64
0x7 ÷128
8:6 VelDiv R/W 0x0
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Bit/Field Name Type Reset Description
Capture Velocity
When set, enables capture of the velocity of the quadrature encoder.
5 VelEn R/W 0
Reset Mode
The Reset mode for the position counter. When 0, the position counter
is reset when it reaches the maximum; when 1, the position counter is
reset when the index pulse is captured.
4 ResMode R/W 0
Capture Mode
The Capture mode defines the phase edges that are counted in the
position. When 0, only the PhA edges are counted; when 1, the PhA
and PhB edges are counted, providing twice the positional resolution
but half the range.
3 CapMode R/W 0
Signal Mode
When 1, the PhA and PhB signals are clock and direction; when 0, they
are quadrature phase signals.
2 SigMode R/W 0
Swap Signals
Swaps the PhA and PhB signals.
1 Swap R/W 0
Enable QEI
Enables the quadrature encoder module.
0 Enable R/W 0
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Register 2: QEI Status (QEISTAT), offset 0x004
This register provides status about the operation of the QEI module.
QEI Status (QEISTAT)
QEI0 base: 0x4002.C000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Direction Error
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Direction of Rotation
Indicates the direction the encoder is rotating.
The Direction values are defined as follows:
Value Description
0 Forward rotation
1 Reverse rotation
1 Direction RO 0
Error Detected
Indicates that an error was detected in the gray code sequence (that is,
both signals changing at the same time).
0 Error RO 0
508 November 30, 2007
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Quadrature Encoder Interface (QEI)
Register 3: QEI Position (QEIPOS), offset 0x008
This register contains the current value of the position integrator. Its value is updated by inputs on
the QEI phase inputs, and can be set to a specific value by writing to it.
QEI Position (QEIPOS)
QEI0 base: 0x4002.C000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Position
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Position
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Current Position Integrator Value
The current value of the position integrator.
31:0 Position R/W 0x00
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Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C
This register contains the maximum value of the position integrator. When moving forward, the
position register resets to zero when it increments past this value. When moving backward, the
position register resets to this value when it decrements from zero.
QEI Maximum Position (QEIMAXPOS)
QEI0 base: 0x4002.C000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MaxPos
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MaxPos
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Maximum Position Integrator Value
The maximum value of the position integrator.
31:0 MaxPos R/W 0x00
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Quadrature Encoder Interface (QEI)
Register 5: QEI Timer Load (QEILOAD), offset 0x010
This register contains the load value for the velocity timer. Since this value is loaded into the timer
the clock cycle after the timer is zero, this value should be one less than the number of clocks in
the desired period. So, for example, to have 2000 clocks per timer period, this register should contain
1999.
QEI Timer Load (QEILOAD)
QEI0 base: 0x4002.C000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Load
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Load
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Velocity Timer Load Value
The load value for the velocity timer.
31:0 Load R/W 0x00
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Register 6: QEI Timer (QEITIME), offset 0x014
This register contains the current value of the velocity timer. This counter does not increment when
VelEn in QEICTL is 0.
QEI Timer (QEITIME)
QEI0 base: 0x4002.C000
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Time
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Time
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Velocity Timer Current Value
The current value of the velocity timer.
31:0 Time RO 0x00
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Quadrature Encoder Interface (QEI)
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018
This register contains the running count of velocity pulses for the current time period. Since this is
a running total, the time period to which it applies cannot be known with precision (that is, a read of
this register does not necessarily correspond to the time returned by the QEITIME register since
there is a small window of time between the two reads, during which time either value may have
changed). The QEISPEED register should be used to determine the actual encoder velocity; this
register is provided for information purposes only. This counter does not increment when VelEn in
QEICTL is 0.
QEI Velocity Counter (QEICOUNT)
QEI0 base: 0x4002.C000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Count
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Count
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Velocity Pulse Count
The running total of encoder pulses during this velocity timer period.
31:0 Count RO 0x00
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Register 8: QEI Velocity (QEISPEED), offset 0x01C
This register contains the most recently measured velocity of the quadrature encoder. This
corresponds to the number of velocity pulses counted in the previous velocity timer period. This
register does not update when VelEn in QEICTL is 0.
QEI Velocity (QEISPEED)
QEI0 base: 0x4002.C000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Speed
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Speed
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Velocity
The measured speed of the quadrature encoder in pulses per period.
31:0 Speed RO 0x00
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Quadrature Encoder Interface (QEI)
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020
This register contains enables for each of the QEI module’s interrupts. An interrupt is asserted to
the controller if its corresponding bit in this register is set to 1.
QEI Interrupt Enable (QEIINTEN)
QEI0 base: 0x4002.C000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntError IntDir IntTimer IntIndex
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
Phase Error Interrupt Enable
When 1, an interrupt occurs when a phase error is detected.
3 IntError R/W 0
Direction Change Interrupt Enable
When 1, an interrupt occurs when the direction changes.
2 IntDir R/W 0
Timer Expires Interrupt Enable
When 1, an interrupt occurs when the velocity timer expires.
1 IntTimer R/W 0
Index Pulse Detected Interrupt Enable
When 1, an interrupt occurs when the index pulse is detected.
0 IntIndex R/W 0
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Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (this is set through the QEIINTEN register).
Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in
question has not occurred.
QEI Raw Interrupt Status (QEIRIS)
QEI0 base: 0x4002.C000
Offset 0x024
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntError IntDir IntTimer IntIndex
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
Phase Error Detected
Indicates that a phase error was detected.
3 IntError RO 0
Direction Change Detected
Indicates that the direction has changed.
2 IntDir RO 0
Velocity Timer Expired
Indicates that the velocity timer has expired.
1 IntTimer RO 0
Index Pulse Asserted
Indicates that the index pulse has occurred.
0 IntIndex RO 0
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Quadrature Encoder Interface (QEI)
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028
This register provides the current set of interrupt sources that are asserted to the controller. Bits set
to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question
has not occurred. This is a R/W1C register; writing a 1 to a bit position clears the corresponding
interrupt reason.
QEI Interrupt Status and Clear (QEIISC)
QEI0 base: 0x4002.C000
Offset 0x028
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntError IntDir IntTimer IntIndex
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
Phase Error Interrupt
Indicates that a phase error was detected.
3 IntError R/W1C 0
Direction Change Interrupt
Indicates that the direction has changed.
2 IntDir R/W1C 0
Velocity Timer Expired Interrupt
Indicates that the velocity timer has expired.
1 IntTimer R/W1C 0
Index Pulse Interrupt
Indicates that the index pulse has occurred.
0 IntIndex R/W1C 0
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20 Pin Diagram
Figure 20-1 on page 518 shows the pin diagram and pin-to-signal-name mapping.
Figure 20-1. Pin Connection Diagram
LM3S6952
38
39
40
41
42
43
44
45
46
47
48
49
50
1 75
26 100
2
27
5
6
3
4
7
8
11
9
10
99
28 98
29 97
30 96
31 95
32 94
33 93
34 92
35 91
36 90
73
72
74
71
69
68
70
67
65
66
12
13
14
17
18
15
16
19
20
23
21
22
24
25
64
37 89
88
87
86
85
84
83
82
81
80
79
78
77
76
63
61
60
62
59
57
56
58
55
53
54
52
51
ADC0
ADC1
VDDA
GNDA
ADC2
PE4
LDO
VDD
GND
PD0/PWM0
PD1/PWM1
PD2/U1Rx
PD3/U1Tx
VDD25
GND
XTALPPHY
XTALNPHY
PG1/U2Tx
PG0/U2Rx
VDD
GND
PC7/C2-
PC6/C2+
PC5/C1+/C1o
PC4/PhA0
PA0/U0Rx
PA1/U0Tx
PA2/SSI0Clk
PA3/SSI0Fss
PA4/SSI0Rx
PA5/SSI0Tx
VDD
GND
PA6/CCP1
PA7
VCCPHY
RXIN
VDD25
GND
RXIP
GNDPHY
GNDPHY
TXOP
VDD
GND
TXON
PF0/PhB0
OSC0
OSC1
WAKE
HIB
XOSC0
XOSC1
GND
VBAT
VDD
GND
MDIO
PF3/LED0
PF2/LED1
PF1
VDD25
GND
RST
CMOD0
PB0/PWM2
PB1/PWM3
VDD
GND
PB2/I2C0SCL
PB3/I2C0SDA
PE0/CCP3
PE1
PE2
PE3
CMOD1
PC3/TDO/SWO
PC2/TDI
PC1/TMS/SWDIO
PC0/TCK/SWCLK
VDD
GND
VCCPHY
VCCPHY
GNDPHY
GNDPHY
GND
VDD25
PB7/TRST
PB6/C0+/C0o
PB5/C1-
PB4/C0-
VDD
GND
PD4/CCP0
PD5/CCP2
GNDA
VDDA
PD6/Fault
PD7/IDX0
518 November 30, 2007
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Pin Diagram
21 Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register.
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
Table 21-1 on page 519 shows the pin-to-signal-name mapping, including functional characteristics
of the signals. Table 21-2 on page 523 lists the signals in alphabetical order by signal name.
Table 21-3 on page 527 groups the signals by functionality, except for GPIOs. Table 21-4 on page
531 lists the GPIO pins and their alternate functionality.
Table 21-1. Signals by Pin Number
Pin Number Pin Name Pin Type Buffer Type Description
1 ADC0 I Analog Analog-to-digital converter input 0.
2 ADC1 I Analog Analog-to-digital converter input 1.
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
3 VDDA - Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
4 GNDA - Power
5 ADC2 I Analog Analog-to-digital converter input 2.
6 PE4 I/O TTL GPIO port E bit 4
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 μF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
7 LDO - Power
8 VDD - Power Positive supply for I/O and some logic.
9 GND - Power Ground reference for logic and I/O pins.
10 PD0 I/O TTL GPIO port D bit 0
PWM0 O TTL PWM 0
11 PD1 I/O TTL GPIO port D bit 1
PWM1 O TTL PWM 1
12 PD2 I/O TTL GPIO port D bit 2
UART module 1 receive. When in IrDA mode,
this signal has IrDA modulation.
U1Rx I TTL
13 PD3 I/O TTL GPIO port D bit 3
UART module 1 transmit. When in IrDA mode,
this signal has IrDA modulation.
U1Tx O TTL
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Pin Number Pin Name Pin Type Buffer Type Description
Positive supply for most of the logic function,
including the processor core and most
peripherals.
14 VDD25 - Power
15 GND - Power Ground reference for logic and I/O pins.
16 XTALPPHY O TTL XTALP of the Ethernet PHY
17 XTALNPHY I TTL XTALN of the Ethernet PHY
18 PG1 I/O TTL GPIO port G bit 1
UART 2 Transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Tx O TTL
19 PG0 I/O TTL GPIO port G bit 0
UART 2 Receive. When in IrDA mode, this
signal has IrDA modulation.
U2Rx I TTL
20 VDD - Power Positive supply for I/O and some logic.
21 GND - Power Ground reference for logic and I/O pins.
22 PC7 I/O TTL GPIO port C bit 7
C2- I Analog Analog comparator 2 negative input
23 PC6 I/O TTL GPIO port C bit 6
C2+ I Analog Analog comparator positive input
24 PC5 I/O TTL GPIO port C bit 5
C1+ I Analog Analog comparator positive input
C1o O TTL Analog comparator 1 output
25 PC4 I/O TTL GPIO port C bit 4
PhA0 I TTL QEI module 0 Phase A
26 PA0 I/O TTL GPIO port A bit 0
UART module 0 receive. When in IrDA mode,
this signal has IrDA modulation.
U0Rx I TTL
27 PA1 I/O TTL GPIO port A bit 1
UART module 0 transmit. When in IrDA mode,
this signal has IrDA modulation.
U0Tx O TTL
28 PA2 I/O TTL GPIO port A bit 2
SSI0Clk I/O TTL SSI module 0 clock
29 PA3 I/O TTL GPIO port A bit 3
SSI0Fss I/O TTL SSI module 0 frame
30 PA4 I/O TTL GPIO port A bit 4
SSI0Rx I TTL SSI module 0 receive
31 PA5 I/O TTL GPIO port A bit 5
SSI0Tx O TTL SSI module 0 transmit
32 VDD - Power Positive supply for I/O and some logic.
33 GND - Power Ground reference for logic and I/O pins.
34 PA6 I/O TTL GPIO port A bit 6
CCP1 I/O TTL Capture/Compare/PWM 1
35 PA7 I/O TTL GPIO port A bit 7
36 VCCPHY I TTL VCC of the Ethernet PHY
37 RXIN I Analog RXIN of the Ethernet PHY
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Signal Tables
Pin Number Pin Name Pin Type Buffer Type Description
Positive supply for most of the logic function,
including the processor core and most
peripherals.
38 VDD25 - Power
39 GND - Power Ground reference for logic and I/O pins.
40 RXIP I Analog RXIP of the Ethernet PHY
41 GNDPHY I TTL GND of the Ethernet PHY
42 GNDPHY I TTL GND of the Ethernet PHY
43 TXOP O Analog TXOP of the Ethernet PHY
44 VDD - Power Positive supply for I/O and some logic.
45 GND - Power Ground reference for logic and I/O pins.
46 TXON O Analog TXON of the Ethernet PHY
47 PF0 I/O TTL GPIO port F bit 0
PhB0 I TTL QEI module 1 Phase B
Main oscillator crystal input or an external
clock reference input.
48 OSC0 I Analog
49 OSC1 I Analog Main oscillator crystal output.
An external input that brings the processor out
of hibernate mode when asserted.
50 WAKE I OD
An output that indicates the processor is in
hibernate mode.
51 HIB O TTL
Hibernation Module oscillator crystal input or
an external clock reference input. Note that
this is either a 4.19-MHz crystal or a
32.768-kHz oscillator for the Hibernation
Module RTC. See the CLKSEL bit in the
HIBCTL register.
52 XOSC0 I Analog
53 XOSC1 I Analog Hibernation Module oscillator crystal output.
54 GND - Power Ground reference for logic and I/O pins.
Power source for the Hibernation Module. It
is normally connected to the positive terminal
of a battery and serves as the battery
backup/Hibernation Module power-source
supply.
55 VBAT - Power
56 VDD - Power Positive supply for I/O and some logic.
57 GND - Power Ground reference for logic and I/O pins.
58 MDIO I/O TTL MDIO of the Ethernet PHY
59 PF3 I/O TTL GPIO port F bit 3
LED0 O TTL MII LED 0
60 PF2 I/O TTL GPIO port F bit 2
LED1 O TTL MII LED 1
61 PF1 I/O TTL GPIO port F bit 1
Positive supply for most of the logic function,
including the processor core and most
peripherals.
62 VDD25 - Power
63 GND - Power Ground reference for logic and I/O pins.
64 RST I TTL System reset input.
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
65 CMOD0 I/O TTL
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Pin Number Pin Name Pin Type Buffer Type Description
66 PB0 I/O TTL GPIO port B bit 0
PWM2 O TTL PWM 2
67 PB1 I/O TTL GPIO port B bit 1
PWM3 O TTL PWM 3
68 VDD - Power Positive supply for I/O and some logic.
69 GND - Power Ground reference for logic and I/O pins.
70 PB2 I/O TTL GPIO port B bit 2
I2C0SCL I/O OD I2C module 0 clock
71 PB3 I/O TTL GPIO port B bit 3
I2C0SDA I/O OD I2C module 0 data
72 PE0 I/O TTL GPIO port E bit 0
CCP3 I/O TTL Capture/Compare/PWM 3
73 PE1 I/O TTL GPIO port E bit 1
74 PE2 I/O TTL GPIO port E bit 2
75 PE3 I/O TTL GPIO port E bit 3
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
76 CMOD1 I/O TTL
77 PC3 I/O TTL GPIO port C bit 3
TDO O TTL JTAG TDO and SWO
SWO O TTL JTAG TDO and SWO
78 PC2 I/O TTL GPIO port C bit 2
TDI I TTL JTAG TDI
79 PC1 I/O TTL GPIO port C bit 1
TMS I/O TTL JTAG TMS and SWDIO
SWDIO I/O TTL JTAG TMS and SWDIO
80 PC0 I/O TTL GPIO port C bit 0
TCK I TTL JTAG/SWD CLK
SWCLK I TTL JTAG/SWD CLK
81 VDD - Power Positive supply for I/O and some logic.
82 GND - Power Ground reference for logic and I/O pins.
83 VCCPHY I TTL VCC of the Ethernet PHY
84 VCCPHY I TTL VCC of the Ethernet PHY
85 GNDPHY I TTL GND of the Ethernet PHY
86 GNDPHY I TTL GND of the Ethernet PHY
87 GND - Power Ground reference for logic and I/O pins.
Positive supply for most of the logic function,
including the processor core and most
peripherals.
88 VDD25 - Power
89 PB7 I/O TTL GPIO port B bit 7
TRST I TTL JTAG TRSTn
90 PB6 I/O TTL GPIO port B bit 6
C0+ I Analog Analog comparator 0 positive input
C0o O TTL Analog comparator 0 output
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Pin Number Pin Name Pin Type Buffer Type Description
91 PB5 I/O TTL GPIO port B bit 5
C1- I Analog Analog comparator 1 negative input
92 PB4 I/O TTL GPIO port B bit 4
C0- I Analog Analog comparator 0 negative input
93 VDD - Power Positive supply for I/O and some logic.
94 GND - Power Ground reference for logic and I/O pins.
95 PD4 I/O TTL GPIO port D bit 4
CCP0 I/O TTL Capture/Compare/PWM 0
96 PD5 I/O TTL GPIO port D bit 5
CCP2 I/O TTL Capture/Compare/PWM 2
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
97 GNDA - Power
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
98 VDDA - Power
99 PD6 I/O TTL GPIO port D bit 6
Fault I TTL PWM Fault
100 PD7 I/O TTL GPIO port D bit 7
IDX0 I TTL QEI module 0 index
Table 21-2. Signals by Signal Name
Pin Name Pin Number Pin Type Buffer Type Description
ADC0 1 I Analog Analog-to-digital converter input 0.
ADC1 2 I Analog Analog-to-digital converter input 1.
ADC2 5 I Analog Analog-to-digital converter input 2.
C0+ 90 I Analog Analog comparator 0 positive input
C0- 92 I Analog Analog comparator 0 negative input
C0o 90 O TTL Analog comparator 0 output
C1+ 24 I Analog Analog comparator positive input
C1- 91 I Analog Analog comparator 1 negative input
C1o 24 O TTL Analog comparator 1 output
C2+ 23 I Analog Analog comparator positive input
C2- 22 I Analog Analog comparator 2 negative input
CCP0 95 I/O TTL Capture/Compare/PWM 0
CCP1 34 I/O TTL Capture/Compare/PWM 1
CCP2 96 I/O TTL Capture/Compare/PWM 2
CCP3 72 I/O TTL Capture/Compare/PWM 3
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD0 65 I/O TTL
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Pin Name Pin Number Pin Type Buffer Type Description
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1 76 I/O TTL
Fault 99 I TTL PWM Fault
GND 9 - Power Ground reference for logic and I/O pins.
GND 15 - Power Ground reference for logic and I/O pins.
GND 21 - Power Ground reference for logic and I/O pins.
GND 33 - Power Ground reference for logic and I/O pins.
GND 39 - Power Ground reference for logic and I/O pins.
GND 45 - Power Ground reference for logic and I/O pins.
GND 54 - Power Ground reference for logic and I/O pins.
GND 57 - Power Ground reference for logic and I/O pins.
GND 63 - Power Ground reference for logic and I/O pins.
GND 69 - Power Ground reference for logic and I/O pins.
GND 82 - Power Ground reference for logic and I/O pins.
GND 87 - Power Ground reference for logic and I/O pins.
GND 94 - Power Ground reference for logic and I/O pins.
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
GNDA 4 - Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
GNDA 97 - Power
GNDPHY 41 I TTL GND of the Ethernet PHY
GNDPHY 42 I TTL GND of the Ethernet PHY
GNDPHY 85 I TTL GND of the Ethernet PHY
GNDPHY 86 I TTL GND of the Ethernet PHY
An output that indicates the processor is in
hibernate mode.
HIB 51 O TTL
I2C0SCL 70 I/O OD I2C module 0 clock
I2C0SDA 71 I/O OD I2C module 0 data
IDX0 100 I TTL QEI module 0 index
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 μF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
LDO 7 - Power
LED0 59 O TTL MII LED 0
LED1 60 O TTL MII LED 1
MDIO 58 I/O TTL MDIO of the Ethernet PHY
Main oscillator crystal input or an external
clock reference input.
OSC0 48 I Analog
OSC1 49 I Analog Main oscillator crystal output.
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Pin Name Pin Number Pin Type Buffer Type Description
PA0 26 I/O TTL GPIO port A bit 0
PA1 27 I/O TTL GPIO port A bit 1
PA2 28 I/O TTL GPIO port A bit 2
PA3 29 I/O TTL GPIO port A bit 3
PA4 30 I/O TTL GPIO port A bit 4
PA5 31 I/O TTL GPIO port A bit 5
PA6 34 I/O TTL GPIO port A bit 6
PA7 35 I/O TTL GPIO port A bit 7
PB0 66 I/O TTL GPIO port B bit 0
PB1 67 I/O TTL GPIO port B bit 1
PB2 70 I/O TTL GPIO port B bit 2
PB3 71 I/O TTL GPIO port B bit 3
PB4 92 I/O TTL GPIO port B bit 4
PB5 91 I/O TTL GPIO port B bit 5
PB6 90 I/O TTL GPIO port B bit 6
PB7 89 I/O TTL GPIO port B bit 7
PC0 80 I/O TTL GPIO port C bit 0
PC1 79 I/O TTL GPIO port C bit 1
PC2 78 I/O TTL GPIO port C bit 2
PC3 77 I/O TTL GPIO port C bit 3
PC4 25 I/O TTL GPIO port C bit 4
PC5 24 I/O TTL GPIO port C bit 5
PC6 23 I/O TTL GPIO port C bit 6
PC7 22 I/O TTL GPIO port C bit 7
PD0 10 I/O TTL GPIO port D bit 0
PD1 11 I/O TTL GPIO port D bit 1
PD2 12 I/O TTL GPIO port D bit 2
PD3 13 I/O TTL GPIO port D bit 3
PD4 95 I/O TTL GPIO port D bit 4
PD5 96 I/O TTL GPIO port D bit 5
PD6 99 I/O TTL GPIO port D bit 6
PD7 100 I/O TTL GPIO port D bit 7
PE0 72 I/O TTL GPIO port E bit 0
PE1 73 I/O TTL GPIO port E bit 1
PE2 74 I/O TTL GPIO port E bit 2
PE3 75 I/O TTL GPIO port E bit 3
PE4 6 I/O TTL GPIO port E bit 4
PF0 47 I/O TTL GPIO port F bit 0
PF1 61 I/O TTL GPIO port F bit 1
PF2 60 I/O TTL GPIO port F bit 2
PF3 59 I/O TTL GPIO port F bit 3
PG0 19 I/O TTL GPIO port G bit 0
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Pin Name Pin Number Pin Type Buffer Type Description
PG1 18 I/O TTL GPIO port G bit 1
PhA0 25 I TTL QEI module 0 Phase A
PhB0 47 I TTL QEI module 1 Phase B
PWM0 10 O TTL PWM 0
PWM1 11 O TTL PWM 1
PWM2 66 O TTL PWM 2
PWM3 67 O TTL PWM 3
RST 64 I TTL System reset input.
RXIN 37 I Analog RXIN of the Ethernet PHY
RXIP 40 I Analog RXIP of the Ethernet PHY
SSI0Clk 28 I/O TTL SSI module 0 clock
SSI0Fss 29 I/O TTL SSI module 0 frame
SSI0Rx 30 I TTL SSI module 0 receive
SSI0Tx 31 O TTL SSI module 0 transmit
SWCLK 80 I TTL JTAG/SWD CLK
SWDIO 79 I/O TTL JTAG TMS and SWDIO
SWO 77 O TTL JTAG TDO and SWO
TCK 80 I TTL JTAG/SWD CLK
TDI 78 I TTL JTAG TDI
TDO 77 O TTL JTAG TDO and SWO
TMS 79 I/O TTL JTAG TMS and SWDIO
TRST 89 I TTL JTAG TRSTn
TXON 46 O Analog TXON of the Ethernet PHY
TXOP 43 O Analog TXOP of the Ethernet PHY
UART module 0 receive. When in IrDA mode,
this signal has IrDA modulation.
U0Rx 26 I TTL
UART module 0 transmit. When in IrDA mode,
this signal has IrDA modulation.
U0Tx 27 O TTL
UART module 1 receive. When in IrDA mode,
this signal has IrDA modulation.
U1Rx 12 I TTL
UART module 1 transmit. When in IrDA mode,
this signal has IrDA modulation.
U1Tx 13 O TTL
UART 2 Receive. When in IrDA mode, this
signal has IrDA modulation.
U2Rx 19 I TTL
UART 2 Transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Tx 18 O TTL
Power source for the Hibernation Module. It
is normally connected to the positive terminal
of a battery and serves as the battery
backup/Hibernation Module power-source
supply.
VBAT 55 - Power
VCCPHY 36 I TTL VCC of the Ethernet PHY
VCCPHY 83 I TTL VCC of the Ethernet PHY
VCCPHY 84 I TTL VCC of the Ethernet PHY
VDD 8 - Power Positive supply for I/O and some logic.
VDD 20 - Power Positive supply for I/O and some logic.
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Pin Name Pin Number Pin Type Buffer Type Description
VDD 32 - Power Positive supply for I/O and some logic.
VDD 44 - Power Positive supply for I/O and some logic.
VDD 56 - Power Positive supply for I/O and some logic.
VDD 68 - Power Positive supply for I/O and some logic.
VDD 81 - Power Positive supply for I/O and some logic.
VDD 93 - Power Positive supply for I/O and some logic.
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 14 - Power
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 38 - Power
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 62 - Power
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 88 - Power
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
VDDA 3 - Power
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
VDDA 98 - Power
An external input that brings the processor out
of hibernate mode when asserted.
WAKE 50 I OD
Hibernation Module oscillator crystal input or
an external clock reference input. Note that
this is either a 4.19-MHz crystal or a
32.768-kHz oscillator for the Hibernation
Module RTC. See the CLKSEL bit in the
HIBCTL register.
XOSC0 52 I Analog
XOSC1 53 I Analog Hibernation Module oscillator crystal output.
XTALNPHY 17 I TTL XTALN of the Ethernet PHY
XTALPPHY 16 O TTL XTALP of the Ethernet PHY
Table 21-3. Signals by Function, Except for GPIO
Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
ADC ADC0 1 I Analog Analog-to-digital converter input 0.
ADC1 2 I Analog Analog-to-digital converter input 1.
ADC2 5 I Analog Analog-to-digital converter input 2.
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Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
Analog C0+ 90 I Analog Analog comparator 0 positive input
Comparators C0- 92 I Analog Analog comparator 0 negative input
C0o 90 O TTL Analog comparator 0 output
C1+ 24 I Analog Analog comparator positive input
C1- 91 I Analog Analog comparator 1 negative input
C1o 24 O TTL Analog comparator 1 output
C2+ 23 I Analog Analog comparator positive input
C2- 22 I Analog Analog comparator 2 negative input
Ethernet PHY GNDPHY 41 I TTL GND of the Ethernet PHY
GNDPHY 42 I TTL GND of the Ethernet PHY
GNDPHY 85 I TTL GND of the Ethernet PHY
GNDPHY 86 I TTL GND of the Ethernet PHY
LED0 59 O TTL MII LED 0
LED1 60 O TTL MII LED 1
MDIO 58 I/O TTL MDIO of the Ethernet PHY
RXIN 37 I Analog RXIN of the Ethernet PHY
RXIP 40 I Analog RXIP of the Ethernet PHY
TXON 46 O Analog TXON of the Ethernet PHY
TXOP 43 O Analog TXOP of the Ethernet PHY
VCCPHY 36 I TTL VCC of the Ethernet PHY
VCCPHY 83 I TTL VCC of the Ethernet PHY
VCCPHY 84 I TTL VCC of the Ethernet PHY
XTALNPHY 17 I TTL XTALN of the Ethernet PHY
XTALPPHY 16 O TTL XTALP of the Ethernet PHY
General-Purpose CCP0 95 I/O TTL Capture/Compare/PWM 0
Timers CCP1 34 I/O TTL Capture/Compare/PWM 1
CCP2 96 I/O TTL Capture/Compare/PWM 2
CCP3 72 I/O TTL Capture/Compare/PWM 3
I2C I2C0SCL 70 I/O OD I2C module 0 clock
I2C0SDA 71 I/O OD I2C module 0 data
JTAG/SWD/SWO SWCLK 80 I TTL JTAG/SWD CLK
SWDIO 79 I/O TTL JTAG TMS and SWDIO
SWO 77 O TTL JTAG TDO and SWO
TCK 80 I TTL JTAG/SWD CLK
TDI 78 I TTL JTAG TDI
TDO 77 O TTL JTAG TDO and SWO
TMS 79 I/O TTL JTAG TMS and SWDIO
PWM Fault 99 I TTL PWM Fault
PWM0 10 O TTL PWM 0
PWM1 11 O TTL PWM 1
PWM2 66 O TTL PWM 2
PWM3 67 O TTL PWM 3
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Signal Tables
Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
Power GND 9 - Power Ground reference for logic and I/O pins.
GND 15 - Power Ground reference for logic and I/O pins.
GND 21 - Power Ground reference for logic and I/O pins.
GND 33 - Power Ground reference for logic and I/O pins.
GND 39 - Power Ground reference for logic and I/O pins.
GND 45 - Power Ground reference for logic and I/O pins.
GND 54 - Power Ground reference for logic and I/O pins.
GND 57 - Power Ground reference for logic and I/O pins.
GND 63 - Power Ground reference for logic and I/O pins.
GND 69 - Power Ground reference for logic and I/O pins.
GND 82 - Power Ground reference for logic and I/O pins.
GND 87 - Power Ground reference for logic and I/O pins.
GND 94 - Power Ground reference for logic and I/O pins.
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
GNDA 4 - Power
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
GNDA 97 - Power
An output that indicates the processor is in
hibernate mode.
HIB 51 O TTL
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 μF or greater. When the on-chip LDO is
used to provide power to the logic, the LDO pin
must also be connected to the VDD25 pins at the
board level in addition to the decoupling
capacitor(s).
LDO 7 - Power
Power source for the Hibernation Module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation Module power-source supply.
VBAT 55 - Power
VDD 8 - Power Positive supply for I/O and some logic.
VDD 20 - Power Positive supply for I/O and some logic.
VDD 32 - Power Positive supply for I/O and some logic.
VDD 44 - Power Positive supply for I/O and some logic.
VDD 56 - Power Positive supply for I/O and some logic.
VDD 68 - Power Positive supply for I/O and some logic.
VDD 81 - Power Positive supply for I/O and some logic.
VDD 93 - Power Positive supply for I/O and some logic.
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 14 - Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 38 - Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 62 - Power
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Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
VDD25 Positive supply for most of the logic function,
including the processor core and most peripherals.
88 - Power
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
VDDA 3 - Power
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
VDDA 98 - Power
An external input that brings the processor out of
hibernate mode when asserted.
WAKE 50 I OD
QEI IDX0 100 I TTL QEI module 0 index
PhA0 25 I TTL QEI module 0 Phase A
PhB0 47 I TTL QEI module 1 Phase B
SSI SSI0Clk 28 I/O TTL SSI module 0 clock
SSI0Fss 29 I/O TTL SSI module 0 frame
SSI0Rx 30 I TTL SSI module 0 receive
SSI0Tx 31 O TTL SSI module 0 transmit
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
System Control & CMOD0 65 I/O TTL
Clocks
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1 76 I/O TTL
Main oscillator crystal input or an external clock
reference input.
OSC0 48 I Analog
OSC1 49 I Analog Main oscillator crystal output.
RST 64 I TTL System reset input.
TRST 89 I TTL JTAG TRSTn
Hibernation Module oscillator crystal input or an
external clock reference input. Note that this is
either a 4.19-MHz crystal or a 32.768-kHz oscillator
for the Hibernation Module RTC. See the CLKSEL
bit in the HIBCTL register.
XOSC0 52 I Analog
XOSC1 53 I Analog Hibernation Module oscillator crystal output.
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
UART U0Rx 26 I TTL
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U0Tx 27 O TTL
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
U1Rx 12 I TTL
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U1Tx 13 O TTL
UART 2 Receive. When in IrDA mode, this signal
has IrDA modulation.
U2Rx 19 I TTL
UART 2 Transmit. When in IrDA mode, this signal
has IrDA modulation.
U2Tx 18 O TTL
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Table 21-4. GPIO Pins and Alternate Functions
GPIO Pin Pin Number Multiplexed Function Multiplexed Function
PA0 26 U0Rx
PA1 27 U0Tx
PA2 28 SSI0Clk
PA3 29 SSI0Fss
PA4 30 SSI0Rx
PA5 31 SSI0Tx
PA6 34 CCP1
PA7 35
PB0 66 PWM2
PB1 67 PWM3
PB2 70 I2C0SCL
PB3 71 I2C0SDA
PB4 92 C0-
PB5 91 C1-
PB6 90 C0+ C0o
PB7 89 TRST
PC0 80 TCK SWCLK
PC1 79 TMS SWDIO
PC2 78 TDI
PC3 77 TDO SWO
PC4 25 PhA0
PC5 24 C1+ C1o
PC6 23 C2+
PC7 22 C2-
PD0 10 PWM0
PD1 11 PWM1
PD2 12 U1Rx
PD3 13 U1Tx
PD4 95 CCP0
PD5 96 CCP2
PD6 99 Fault
PD7 100 IDX0
PE0 72 CCP3
PE1 73
PE2 74
PE3 75
PE4 6
PF0 47 PhB0
PF1 61
PF2 60 LED1
PF3 59 LED0
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GPIO Pin Pin Number Multiplexed Function Multiplexed Function
PG0 19 U2Rx
PG1 18 U2Tx
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22 Operating Characteristics
Table 22-1. Temperature Characteristics
Characteristic Symbol Value Unit
Operating temperature rangea TA -40 to +85 °C
a. Maximum storage temperature is 150°C.
Table 22-2. Thermal Characteristics
Characteristic Symbol Value Unit
Thermal resistance (junction to ambient)a ΘJA 55.3 °C/W
Average junction temperatureb TJ TA + (PAVG • ΘJA) °C
a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator.
b. Power dissipation is a function of temperature.
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23 Electrical Characteristics
23.1 DC Characteristics
23.1.1 Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device.
Note: The device is not guaranteed to operate properly at the maximum ratings.
Table 23-1. Maximum Ratings
Characteristic Symbol Value Unit
a
Min Max
I/O supply voltage (VDD) VDD 0 4 V
Core supply voltage (VDD25) VDD25 0 4 V
Analog supply voltage (VDDA) VDDA 0 4 V
Battery supply voltage (VBAT) VBAT 0 4 V
Ethernet PHY supply voltage (VCCPHY) VCCPHY 0 4 V
Input voltage VIN -0.3 5.5 V
Maximum current per output pins I - 25 mA
a. Voltages are measured with respect to GND.
Important: This device contains circuitry to protect the inputs against damage due to high-static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are
connected to an appropriate logic voltage level (for example, either GND or VDD).
23.1.2 Recommended DC Operating Conditions
Table 23-2. Recommended DC Operating Conditions
Parameter Parameter Name Min Nom Max Unit
VDD I/O supply voltage 3.0 3.3 3.6 V
VDD25 Core supply voltage 2.25 2.5 2.75 V
VDDA Analog supply voltage 3.0 3.3 3.6 V
VBAT Battery supply voltage 2.3 3.0 3.6 V
VCCPHY Ethernet PHY supply voltage 3.0 3.3 3.6 V
VIH High-level input voltage 2.0 - 5.0 V
VIL Low-level input voltage -0.3 - 1.3 V
VSIH High-level input voltage for Schmitt trigger inputs 0.8 * VDD - VDD V
VSIL Low-level input voltage for Schmitt trigger inputs 0 - 0.2 * VDD V
VOH High-level output voltage 2.4 - - V
VOL Low-level output voltage - - 0.4 V
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Parameter Parameter Name Min Nom Max Unit
IOH High-level source current, VOH=2.4 V
2-mA Drive 2.0 - - mA
4-mA Drive 4.0 - - mA
8-mA Drive 8.0 - - mA
IOL Low-level sink current, VOL=0.4 V
2-mA Drive 2.0 - - mA
4-mA Drive 4.0 - - mA
8-mA Drive 8.0 - - mA
23.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics
Table 23-3. LDO Regulator Characteristics
Parameter Parameter Name Min Nom Max Unit
VLDOOUT Programmable internal (logic) power supply output value 2.25 2.5 2.75 V
Output voltage accuracy - 2% - %
tPON Power-on time - - 100 μs
tON Time on - - 200 μs
tOFF Time off - - 100 μs
VSTEP Step programming incremental voltage - 50 - mV
CLDO External filter capacitor size for internal power supply 1.0 - 3.0 μF
23.1.4 Power Specifications
The power measurements specified in the tables that follow are run on the core processor using
SRAM with the following specifications (except as noted):
■ VDD = 3.3 V
■ VDD25 = 2.50 V
■ VBAT = 3.0 V
■ VDDA = 3.3 V
■ VDDPHY = 3.3 V
■ Temperature = 25°C
■ Clock Source (MOSC) =3.579545 MHz Crystal Oscillator
■ Main oscillator (MOSC) = enabled
■ Internal oscillator (IOSC) = disabled
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Table 23-4. Detailed Power Specifications
3.3 V VDD, VDDA, 2.5 V VDD25 3.0 V VBAT Unit
VDDPHY
Parameter Conditions
Name
Parameter
Nom Max Nom Max Nom Max
VDD25 = 2.50 V 48 pendinga 108 pendinga 0 pendinga mA
Code= while(1){} executed in
Flash
Peripherals = All ON
System Clock = 50 MHz (with
PLL)
Run mode 1
(Flash loop)
IDD_RUN
VDD25 = 2.50 V 5 pendinga 52 pendinga 0 pendinga mA
Code= while(1){} executed in
Flash
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
Run mode 2
(Flash loop)
VDD25 = 2.50 V 48 pendinga 100 pendinga 0 pendinga mA
Code= while(1){} executed in
SRAM
Peripherals = All ON
System Clock = 50 MHz (with
PLL)
Run mode 1
(SRAM loop)
VDD25 = 2.50 V 5 pendinga 45 pendinga 0 pendinga mA
Code= while(1){} executed in
SRAM
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
Run mode 2
(SRAM loop)
VDD25 = 2.50 V 5 pendinga 16 pendinga 0 pendinga mA
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
IDD_SLEEP Sleep mode
LDO = 2.25 V 4.6 pendinga 0.21 pendinga 0 pendinga mA
Peripherals = All OFF
System Clock = IOSC30KHZ/64
Deep-Sleep
mode
IDD_DEEPSLEEP
VBAT = 3.0 V 0 pendinga 0 pendinga 16 pendinga μA
VDD = 0 V
VDD25 = 0 V
VDDA = 0 V
VDDPHY = 0 V
Peripherals = All OFF
System Clock = OFF
Hibernate Module = 32 kHz
Hibernate
mode
IDD_HIBERNATE
a. Pending characterization completion.
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23.1.5 Flash Memory Characteristics
Table 23-5. Flash Memory Characteristics
Parameter Parameter Name Min Nom Max Unit
PECYC Number of guaranteed program/erase cycles before failurea 10,000 100,000 - cycles
TRET Data retention at average operating temperature of 85˚C 10 - - years
TPROG Word program time 20 - - μs
TERASE Page erase time 20 - - ms
TME Mass erase time 200 - - ms
a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1.
23.2 AC Characteristics
23.2.1 Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements. Timing
measurements are for 4-mA drive strength.
Figure 23-1. Load Conditions
CL = 50 pF
GND
pin
23.2.2 Clocks
Table 23-6. Phase Locked Loop (PLL) Characteristics
Parameter Parameter Name Min Nom Max Unit
fref_crystal Crystal referencea 3.579545 - 8.192 MHz
fref_ext External clock referencea 3.579545 - 8.192 MHz
fpll PLL frequencyb - 400 - MHz
TREADY PLL lock time - - 0.5 ms
a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration
(RCC) register.
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register.
Table 23-7. Clock Characteristics
Parameter Parameter Name Min Nom Max Unit
fIOSC Internal 12 MHz oscillator frequency 8.4 12 15.6 MHz
fIOSC30KHZ Internal 30 KHz oscillator frequency 21 30 39 KHz
fXOSC Hibernation module oscillator frequency - 4.194304 - MHz
fXOSC_XTAL Crystal reference for hibernation oscillator - 4.194304 - MHz
fXOSC_EXT External clock reference for hibernation module - 32.768 - KHz
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Parameter Parameter Name Min Nom Max Unit
fMOSC Main oscillator frequency 1 - 8 MHz
tMOSC_per Main oscillator period 125 - 1000 ns
Crystal reference using the main oscillator (PLL in BYPASS mode) 1 - 8 MHz
a
fref_crystal_bypass
fref_ext_bypass External clock reference (PLL in BYPASS mode)a 0 - 50 MHz
fsystem_clock System clock 0 - 50 MHz
a. The ADC must be clocked from the PLL or directly from a 14-MHz to 18-MHz clock source to operate properly.
Table 23-8. Crystal Characteristics
Parameter Name Value Units
Frequency 8 6 4 3.5 MHz
Frequency tolerance ±50 ±50 ±50 ±50 ppm
Aging ±5 ±5 ±5 ±5 ppm/yr
Oscillation mode Parallel Parallel Parallel Parallel
Temperature stability (0 - 85 °C) ±25 ±25 ±25 ±25 ppm
Motional capacitance (typ) 27.8 37.0 55.6 63.5 pF
Motional inductance (typ) 14.3 19.1 28.6 32.7 mH
Equivalent series resistance (max) 120 160 200 220 Ω
Shunt capacitance (max) 10 10 10 10 pF
Load capacitance (typ) 16 16 16 16 pF
Drive level (typ) 100 100 100 100 μW
23.2.3 Analog-to-Digital Converter
Table 23-9. ADC Characteristics
Parameter Parameter Name Min Nom Max Unit
VADCIN Maximum single-ended, full-scale analog input voltage - - 3.0 V
Minimum single-ended, full-scale analog input voltage - - 0 V
Maximum differential, full-scale analog input voltage - - 1.5 V
Minimum differential, full-scale analog input voltage - - -1.5 V
CADCIN Equivalent input capacitance - 1 - pF
N Resolution - 10 - bits
fADC ADC internal clock frequency 7 8 9 MHz
tADCCONV Conversion time - - 16 tADCcyclesa
f ADCCONV Conversion rate 438 500 563 k samples/s
INL Integral nonlinearity - - ±1 LSB
DNL Differential nonlinearity - - ±1 LSB
OFF Offset - - ±1 LSB
GAIN Gain - - ±1 LSB
a. tADC= 1/fADC clock
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23.2.4 Analog Comparator
Table 23-10. Analog Comparator Characteristics
Parameter Parameter Name Min Nom Max Unit
VOS Input offset voltage - ±10 ±25 mV
VCM Input common mode voltage range 0 - VDD-1.5 V
CMRR Common mode rejection ratio 50 - - dB
TRT Response time - - 1 μs
TMC Comparator mode change to Output Valid - - 10 μs
Table 23-11. Analog Comparator Voltage Reference Characteristics
Parameter Parameter Name Min Nom Max Unit
RHR Resolution high range - VDD/32 - LSB
RLR Resolution low range - VDD/24 - LSB
AHR Absolute accuracy high range - - ±1/2 LSB
ALR Absolute accuracy low range - - ±1/4 LSB
23.2.5 I2C
Table 23-12. I2C Characteristics
Parameter No. Parameter Parameter Name Min Nom Max Unit
I1a tSCH Start condition hold time 36 - - system clocks
I2a tLP Clock Low period 36 - - system clocks
I3b tSRT I2CSCL/I2CSDA rise time (VIL =0.5 V to V IH =2.4 V) - - (see note b) ns
I4a tDH Data hold time 2 - - system clocks
I5c tSFT I2CSCL/I2CSDA fall time (VIH =2.4 V to V IL =0.5 V) - 9 10 ns
I6a tHT Clock High time 24 - - system clocks
I7a tDS Data setup time 18 - - system clocks
Start condition setup time (for repeated start condition 36 - - system clocks
only)
I8a tSCSR
I9a tSCS Stop condition setup time 24 - - system clocks
a. Values depend on the value programmed into the TPR bit in the I2C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
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Figure 23-2. I2C Timing
I2CSCL
I2CSDA
I1
I2
I4
I6
I7 I8
I5
I3 I9
23.2.6 Ethernet Controller
Table 23-13. 100BASE-TX Transmitter Characteristicsa
Parameter Name Min Nom Max Unit
Peak output amplitude 950 - 1050 mVpk
Output amplitude symmetry 0.98 - 1.02 mVpk
Output overshoot - - 5 %
Rise/Fall time 3 - 5 ns
Rise/Fall time imbalance - - 500 ps
Duty cycle distortion - - - ps
Jitter - - 1.4 ns
a. Measured at the line side of the transformer.
Table 23-14. 100BASE-TX Transmitter Characteristics (informative)a
Parameter Name Min Nom Max Unit
Return loss 16 - - dB
Open-circuit inductance 350 - - μs
a. The specifications in this table are included for information only. They are mainly a function of the external transformer
and termination resistors used for measurements.
Table 23-15. 100BASE-TX Receiver Characteristics
Parameter Name Min Nom Max Unit
Signal detect assertion threshold 600 700 mVppd
Signal detect de-assertion threshold 350 425 - mVppd
Differential input resistance 20 - - kΩ
Jitter tolerance (pk-pk) 4 - - ns
Baseline wander tracking -75 - +75 %
Signal detect assertion time - - 1000 μs
Signal detect de-assertion time - - 4 μs
Table 23-16. 10BASE-T Transmitter Characteristicsa
Parameter Name Min Nom Max Unit
Peak differential output signal 2.2 - 2.8 V
Harmonic content 27 - - dB
Link pulse width - 100 - ns
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Parameter Name Min Nom Max Unit
300 - ns
350
Start-of-idle pulse width -
a. The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using
the procedures found in Clause 14 of IEEE 802.3.
Table 23-17. 10BASE-T Transmitter Characteristics (informative)a
Parameter Name Min Nom Max Unit
Output return loss 15 - - dB
Output impedance balance 29-17log(f/10) - - dB
Peak common-mode output voltage - - 50 mV
Common-mode rejection - - 100 mV
Common-mode rejection jitter - - 1 ns
a. The specifications in this table are included for information only. They are mainly a function of the external transformer
and termination resistors used for measurements.
Table 23-18. 10BASE-T Receiver Characteristics
Parameter Name Min Nom Max Unit
DLL phase acquisition time - 10 - BT
Jitter tolerance (pk-pk) 30 - - ns
Input squelched threshold 500 600 700 mVppd
Input unsquelched threshold 275 350 425 mVppd
Differential input resistance - 20 - kΩ
Bit error ratio - 10-10 - -
Common-mode rejection 25 - - V
Table 23-19. Isolation Transformersa
Name Value Condition
Turns ratio 1 CT : 1 CT +/- 5%
Open-circuit inductance 350 uH (min) @ 10 mV, 10 kHz
Leakage inductance 0.40 uH (max) @ 1 MHz (min)
Inter-winding capacitance 25 pF (max)
DC resistance 0.9 Ohm (max)
Insertion loss 0.4 dB (typ) 0-65 MHz
HIPOT 1500 Vrms
a. Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common-mode
chokes are recommended for exceeding FCC requirements. This table gives the recommended line transformer
characteristics.
Note: The 100Base-TX amplitude specifications assume a transformer loss of 0.4 dB. For the
transmit line transformer with higher insertion losses, up to 1.2 dB of insertion loss can be
compensated by selecting the appropriate setting in the Transmit Amplitude Selection (TXO)
bits in the MR19 register.
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Table 23-20. Ethernet Reference Crystala
Name Value Condition
Frequency 25.00000 MHz
Load capacitanceb 4c pF
Frequency tolerance ±50 PPM
Aging ±2 PPM/yr
Temperature stability (0° to 70°) ±5 PPM
Oscillation mode Parallel resonance, fundamental mode
Parameters at 25° C ±2° C; Drive level = 0.5 mW
Drive level (typ) 50-100 μW
Shunt capacitance (max) 10 pF
Motional capacitance (min) 10 fF
Serious resistance (max) 60 Ω
Spurious response (max) > 5 dB below main within 500 kHz
a. If the internal crystal oscillator is used, select a crystal with the following characteristics.
b. Equivalent differential capacitance across XTLP/XTLN.
c. If crystal with a larger load is used, external shunt capacitors to ground should be added to make up the equivalent
capacitance difference.
Figure 23-3. External XTLP Oscillator Characteristics
Tclkper
Tr
Tclkhi Tclklo
Tf
Table 23-21. External XTLP Oscillator Characteristics
Parameter Name Symbol Min Nom Max Unit
XTLN Input Low Voltage XTLNILV - - 0.8 -
XTLP Frequencya XTLPf - 25.0 - -
XTLP Periodb Tclkper - 40 - -
60 %
60
40 -
40
XTLPDC XTLP Duty Cycle
Rise/Fall Time Tr , Tf - - 4.0 ns
Absolute Jitter - - 0.1 ns
a. IEEE 802.3 frequency tolerance ±50 ppm.
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b. IEEE 802.3 frequency tolerance ±50 ppm.
23.2.7 Hibernation Module
The Hibernation Module requires special system implementation considerations since it is intended
to power-down all other sections of its host device. The system power-supply distribution and
interfaces of the system must be driven to 0 VDC or powered down with the same regulator controlled
by HIB.
The regulators controlled by HIB are expected to have a settling time of 250 μs or less.
Table 23-22. Hibernation Module Characteristics
Parameter No Parameter Parameter Name Min Nom Max Unit
H1 tHIB_LOW Internal 32.768 KHz clock reference rising edge to /HIB asserted - 200 - μs
H2 tHIB_HIGH Internal 32.768 KHz clock reference rising edge to /HIB deasserted - 30 - μs
H3 tWAKE_ASSERT /WAKE assertion time 62 - - μs
H4 tWAKETOHIB /WAKE assert to /HIB desassert 62 - 124 μs
H5 tXOSC_SETTLE XOSC settling timea 20 - - ms
H6 tHIB_REG_WRITE Time for a write to non-volatile registers in HIB module to complete 92 - - μs
H7 tHIB_TO_VDD HIB deassert to VDD and VDD25 at minimum operational level - - 250 μs
a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care
must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance).
Figure 23-4. Hibernation Module Timing
32.768 KHz
(internal)
/HIB
H4
H1
/WAKE
H2
H3
23.2.8 Synchronous Serial Interface (SSI)
Table 23-23. SSI Characteristics
Parameter No. Parameter Parameter Name Min Nom Max Unit
S1 tclk_per SSIClk cycle time 2 - 65024 system clocks
S2 tclk_high SSIClk high time - 1/2 - t clk_per
S3 tclk_low SSIClk low time - 1/2 - t clk_per
S4 tclkrf SSIClk rise/fall time - 7.4 26 ns
S5 tDMd Data from master valid delay time 0 - 20 ns
S6 tDMs Data from master setup time 20 - - ns
S7 tDMh Data from master hold time 40 - - ns
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Parameter No. Parameter Parameter Name Min Nom Max Unit
S8 tDSs Data from slave setup time 20 - - ns
S9 tDSh Data from slave hold time 40 - - ns
Figure 23-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement
SSIClk
SSIFss
SSITx
SSIRx MSB LSB
S2
S3
S1
S4
4 to 16 bits
Figure 23-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer
0
SSIClk
SSIFss
SSITx
SSIRx
MSB LSB
MSB LSB
S2
S3
S1
8-bit control
4 to 16 bits output data
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Figure 23-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1
SSIClk
(SPO=1)
SSITx
(master)
SSIRx
(slave) LSB
SSIClk
(SPO=0)
S2
S1
S4
SSIFss
LSB
S3
MSB
S5
S6 S7
S8 S9
MSB
23.2.9 JTAG and Boundary Scan
Table 23-24. JTAG Characteristics
Parameter No. Parameter Parameter Name Min Nom Max Unit
J1 fTCK TCK operational clock frequency 0 - 10 MHz
J2 tTCK TCK operational clock period 100 - - ns
J3 tTCK_LOW TCK clock Low time - tTCK - ns
J4 tTCK_HIGH TCK clock High time - tTCK - ns
J5 tTCK_R TCK rise time 0 - 10 ns
J6 tTCK_F TCK fall time 0 - 10 ns
J7 tTMS_SU TMS setup time to TCK rise 20 - - ns
J8 tTMS_HLD TMS hold time from TCK rise 20 - - ns
J9 tTDI_SU TDI setup time to TCK rise 25 - - ns
J10 tTDI_HLD TDI hold time from TCK rise 25 - - ns
J11 TCK fall to Data Valid from High-Z 2-mA drive - 23 35 ns
t TDO_ZDV 4-mA drive 15 26 ns
8-mA drive 14 25 ns
8-mA drive with slew rate control 18 29 ns
J12 TCK fall to Data Valid from Data Valid 2-mA drive - 21 35 ns
t TDO_DV 4-mA drive 14 25 ns
8-mA drive 13 24 ns
8-mA drive with slew rate control 18 28 ns
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Parameter No. Parameter Parameter Name Min Nom Max Unit
J13 TCK fall to High-Z from Data Valid 2-mA drive - 9 11 ns
t TDO_DVZ 4-mA drive 7 9 ns
8-mA drive 6 8 ns
8-mA drive with slew rate control 7 9 ns
J14 tTRST TRST assertion time 100 - - ns
J15 tTRST_SU TRST setup time to TCK rise 10 - - ns
Figure 23-8. JTAG Test Clock Input Timing
TCK
J6 J5
J3 J4
J2
Figure 23-9. JTAG Test Access Port (TAP) Timing
TDO Output Valid
TCK
TDO Output Valid
J12
TDO
TDI
TMS
TDI Input Valid TDI Input Valid
J13
J9 J10
TMS Input Valid
J9 J10
TMS Input Valid
J11
J7 J8 J7 J8
Figure 23-10. JTAG TRST Timing
TCK
J14 J15
TRST
23.2.10 General-Purpose I/O
Note: All GPIOs are 5 V-tolerant.
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Table 23-25. GPIO Characteristics
Parameter Parameter Name Condition Min Nom Max Unit
tGPIOR GPIO Rise Time (from 20% to 80% of VDD) 2-mA drive - 17 26 ns
4-mA drive 9 13 ns
8-mA drive 6 9 ns
8-mA drive with slew rate control 10 12 ns
tGPIOF GPIO Fall Time (from 80% to 20% of VDD) 2-mA drive - 17 25 ns
4-mA drive 8 12 ns
8-mA drive 6 10 ns
8-mA drive with slew rate control 11 13 ns
23.2.11 Reset
Table 23-26. Reset Characteristics
Parameter No. Parameter Parameter Name Min Nom Max Unit
R1 VTH Reset threshold - 2.0 - V
R2 VBTH Brown-Out threshold 2.85 2.9 2.95 V
R3 TPOR Power-On Reset timeout - 10 - ms
R4 TBOR Brown-Out timeout - 500 - μs
R5 TIRPOR Internal reset timeout after POR 6 - 11 ms
R6 TIRBOR Internal reset timeout after BORa 0 - 1 μs
R7 TIRHWR Internal reset timeout after hardware reset (RST pin) 0 - 1 ms
R8 TIRSWR Internal reset timeout after software-initiated system reset a 2.5 - 20 μs
R9 TIRWDR Internal reset timeout after watchdog reseta 2.5 - 20 μs
R10 TVDDRISE Supply voltage (VDD) rise time (0V-3.3V) - - 100 ms
R11 TMIN Minimum RST pulse width 2 - - μs
a. 20 * t MOSC_per
Figure 23-11. External Reset Timing (RST)
RST
/Reset
(Internal)
R11 R7
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Figure 23-12. Power-On Reset Timing
VDD
/POR
(Internal)
/Reset
(Internal)
R3
R1
R5
Figure 23-13. Brown-Out Reset Timing
VDD
/BOR
(Internal)
/Reset
(Internal)
R2
R4
R6
Figure 23-14. Software Reset Timing
R8
SW Reset
/Reset
(Internal)
Figure 23-15. Watchdog Reset Timing
WDOG
Reset
(Internal)
/Reset
(Internal)
R9
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24 Package Information
Figure 24-1. 100-Pin LQFP Package
Note: The following notes apply to the package drawing.
1. All dimensions shown in mm.
2. Dimensions shown are nominal with tolerances indicated.
3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane.
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Body +2.00 mm Footprint, 1.4 mm package thickness
Symbols Leads 100L
A Max. 1.60
A1 0.05 Min./0.15 Max.
A2 ±0.05 1.40
D ±0.20 16.00
D1 ±0.05 14.00
E ±0.20 16.00
E1 ±0.05 14.00
L ±0.15/-0.10 0.60
e BASIC 0.50
b ±0.05 0.22
θ === 0˚~7˚
ddd Max. 0.08
ccc Max. 0.08
JEDEC Reference Drawing MS-026
Variation Designator BED
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Package Information
A Serial Flash Loader
A.1 Serial Flash Loader
The Stellaris® serial flash loader is a preprogrammed flash-resident utility used to download code
to the flash memory of a device without the use of a debug interface. The serial flash loader uses
a simple packet interface to provide synchronous communication with the device. The flash loader
runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used.
The two serial interfaces that can be used are the UART0 and SSI0 interfaces. For simplicity, both
the data format and communication protocol are identical for both serial interfaces.
A.2 Interfaces
Once communication with the flash loader is established via one of the serial interfaces, that interface
is used until the flash loader is reset or new code takes over. For example, once you start
communicating using the SSI port, communications with the flash loader via the UART are disabled
until the device is reset.
A.2.1 UART
The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial
format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is
automatically detected by the flash loader and can be any valid baud rate supported by the host
and the device. The auto detection sequence requires that the baud rate should be no more than
1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the
same as the hardware limitation for the maximum baud rate for any UART on a Stellaris® device
which is calculated as follows:
Max Baud Rate = System Clock Frequency / 16
In order to determine the baud rate, the serial flash loader needs to determine the relationship
between its own crystal frequency and the baud rate. This is enough information for the flash loader
to configure its UART to the same baud rate as the host. This automatic baud-rate detection allows
the host to use any valid baud rate that it wants to communicate with the device.
The method used to perform this automatic synchronization relies on the host sending the flash
loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can
use to calculate the ratios needed to program the UART to match the host’s baud rate. After the
host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader
returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received
after at least twice the time required to transfer the two bytes, the host can resend another pattern
of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader acknowledges that it has
received a synchronization pattern correctly. For example, the time to wait for data back from the
flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate
of 115200, this time is 2*(20/115200) or 0.35 ms.
A.2.2 SSI
The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications,
with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See “Frame
Formats” on page 339 in the SSI chapter for more information on formats for this transfer protocol.
Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI
clock can run. This allows the SSI clock to be at most 1/12 the crystal frequency of the board running
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the flash loader. Since the host device is the master, the SSI on the flash loader device does not
need to determine the clock as it is provided directly by the host.
A.3 Packet Handling
All communications, with the exception of the UART auto-baud, are done via defined packets that
are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same
format for receiving and sending packets, including the method used to acknowledge successful or
unsuccessful reception of a packet.
A.3.1 Packet Format
All packets sent and received from the device use the following byte-packed format.
struct
{
unsigned char ucSize;
unsigned char ucCheckSum;
unsigned char Data[];
};
ucSize The first byte received holds the total size of the transfer including
the size and checksum bytes.
ucChecksum This holds a simple checksum of the bytes in the data buffer only.
The algorithm is Data[0]+Data[1]+…+ Data[ucSize-3].
Data This is the raw data intended for the device, which is formatted in
some form of command interface. There should be ucSize–2
bytes of data provided in this buffer to or from the device.
A.3.2 Sending Packets
The actual bytes of the packet can be sent individually or all at once; the only limitation is that
commands that cause flash memory access should limit the download sizes to prevent losing bytes
during flash programming. This limitation is discussed further in the section that describes the serial
flash loader command, COMMAND_SEND_DATA (see “COMMAND_SEND_DATA
(0x24)” on page 554).
Once the packet has been formatted correctly by the host, it should be sent out over the UART or
SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned
from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from
the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This
does not indicate that the actual contents of the command issued in the data portion of the packet
were valid, just that the packet was received correctly.
A.3.3 Receiving Packets
The flash loader sends a packet of data in the same format that it receives a packet. The flash loader
may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte
is the size of the packet followed by a checksum byte, and finally followed by the data itself. There
is no break in the data after the first non-zero byte is sent from the flash loader. Once the device
communicating with the flash loader receives all the bytes, it must either ACK or NAK the packet to
indicate that the transmission was successful. The appropriate response after sending a NAK to
the flash loader is to resend the command that failed and request the data again. If needed, the
host may send leading zeros before sending down the ACK/NAK signal to the flash loader, as the
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flash loader only accepts the first non-zero data as a valid response. This zero padding is needed
by the SSI interface in order to receive data to or from the flash loader.
A.4 Commands
The next section defines the list of commands that can be sent to the flash loader. The first byte of
the data should always be one of the defined commands, followed by data or parameters as
determined by the command that is sent.
A.4.1 COMMAND_PING (0X20)
This command simply accepts the command and sets the global status to success. The format of
the packet is as follows:
Byte[0] = 0x03;
Byte[1] = checksum(Byte[2]);
Byte[2] = COMMAND_PING;
The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one
byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status,
the receipt of an ACK can be interpreted as a successful ping to the flash loader.
A.4.2 COMMAND_GET_STATUS (0x23)
This command returns the status of the last command that was issued. Typically, this command
should be sent after every command to ensure that the previous command was successful or to
properly respond to a failure. The command requires one byte in the data of the packet and should
be followed by reading a packet with one byte of data that contains a status code. The last step is
to ACK or NAK the received data so the flash loader knows that the data has been read.
Byte[0] = 0x03
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_GET_STATUS
A.4.3 COMMAND_DOWNLOAD (0x21)
This command is sent to the flash loader to indicate where to store data and how many bytes will
be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit
values that are both transferred MSB first. The first 32-bit value is the address to start programming
data into, while the second is the 32-bit size of the data that will be sent. This command also triggers
an erase of the full area to be programmed so this command takes longer than other commands.
This results in a longer time to receive the ACK/NAK back from the board. This command should
be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size
are valid for the device running the flash loader.
The format of the packet to send this command is a follows:
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_DOWNLOAD
Byte[3] = Program Address [31:24]
Byte[4] = Program Address [23:16]
Byte[5] = Program Address [15:8]
Byte[6] = Program Address [7:0]
Byte[7] = Program Size [31:24]
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Byte[8] = Program Size [23:16]
Byte[9] = Program Size [15:8]
Byte[10] = Program Size [7:0]
A.4.4 COMMAND_SEND_DATA (0x24)
This command should only follow a COMMAND_DOWNLOAD command or another
COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands
automatically increment address and continue programming from the previous location. The caller
should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program
successfully and not overflow input buffers of the serial interfaces. The command terminates
programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been
received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to
ensure that the data was successfully programmed into the flash. If the flash loader sends a NAK
to this command, the flash loader does not increment the current address to allow retransmission
of the previous data.
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_SEND_DATA
Byte[3] = Data[0]
Byte[4] = Data[1]
Byte[5] = Data[2]
Byte[6] = Data[3]
Byte[7] = Data[4]
Byte[8] = Data[5]
Byte[9] = Data[6]
Byte[10] = Data[7]
A.4.5 COMMAND_RUN (0x22)
This command is used to tell the flash loader to execute from the address passed as the parameter
in this command. This command consists of a single 32-bit value that is interpreted as the address
to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK
signal back to the host device before actually executing the code at the given address. This allows
the host to know that the command was received successfully and the code is now running.
Byte[0] = 7
Byte[1] = checksum(Bytes[2:6])
Byte[2] = COMMAND_RUN
Byte[3] = Execute Address[31:24]
Byte[4] = Execute Address[23:16]
Byte[5] = Execute Address[15:8]
Byte[6] = Execute Address[7:0]
A.4.6 COMMAND_RESET (0x25)
This command is used to tell the flash loader device to reset. This is useful when downloading a
new image that overwrote the flash loader and wants to start from a full reset. Unlike the
COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set
up for the new code. It can also be used to reset the flash loader if a critical error occurs and the
host device wants to restart communication with the flash loader.
554 November 30, 2007
Preliminary
Serial Flash Loader
Byte[0] = 3
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_RESET
The flash loader responds with an ACK signal back to the host device before actually executing the
software reset to the device running the flash loader. This allows the host to know that the command
was received successfully and the part will be reset.
November 30, 2007 555
Preliminary
LM3S6952 Microcontroller
B Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
System Control
Base 0x400F.E000
DID0, type RO, offset 0x000, reset -
VER CLASS
MAJOR MINOR
PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD
BORIOR
LDOPCTL, type R/W, offset 0x034, reset 0x0000.0000
VADJ
RIS, type RO, offset 0x050, reset 0x0000.0000
PLLLRIS BORRIS
IMC, type R/W, offset 0x054, reset 0x0000.0000
PLLLIM BORIM
MISC, type R/W1C, offset 0x058, reset 0x0000.0000
PLLLMIS BORMIS
RESC, type R/W, offset 0x05C, reset -
LDO SW WDT BOR POR EXT
RCC, type R/W, offset 0x060, reset 0x07AE.3AD1
ACG SYSDIV USESYSDIV USEPWMDIV PWMDIV
PWRDN BYPASS XTAL OSCSRC IOSCDIS MOSCDIS
PLLCFG, type RO, offset 0x064, reset -
F R
RCC2, type R/W, offset 0x070, reset 0x0780.2800
USERCC2 SYSDIV2
PWRDN2 BYPASS2 OSCSRC2
DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000
DSDIVORIDE
DSOSCSRC
DID1, type RO, offset 0x004, reset -
VER FAM PARTNO
PINCOUNT TEMP PKG ROHS QUAL
DC0, type RO, offset 0x008, reset 0x00FF.007F
SRAMSZ
FLASHSZ
DC1, type RO, offset 0x010, reset 0x0011.32FF
PWM ADC
MINSYSDIV MAXADCSPD MPU HIB TEMPSNS PLL WDT SWO SWD JTAG
DC2, type RO, offset 0x014, reset 0x0707.1117
COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0
I2C0 QEI0 SSI0 UART2 UART1 UART0
DC3, type RO, offset 0x018, reset 0x0F07.BFCF
CCP3 CCP2 CCP1 CCP0 ADC2 ADC1 ADC0
PWMFAULT C2PLUS C2MINUS C1O C1PLUS C1MINUS C0O C0PLUS C0MINUS PWM3 PWM2 PWM1 PWM0
556 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DC4, type RO, offset 0x01C, reset 0x5000.007F
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
RCGC0, type R/W, offset 0x100, reset 0x00000040
PWM ADC
MAXADCSPD HIB WDT
SCGC0, type R/W, offset 0x110, reset 0x00000040
PWM ADC
MAXADCSPD HIB WDT
DCGC0, type R/W, offset 0x120, reset 0x00000040
PWM ADC
MAXADCSPD HIB WDT
RCGC1, type R/W, offset 0x104, reset 0x00000000
COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0
I2C0 QEI0 SSI0 UART2 UART1 UART0
SCGC1, type R/W, offset 0x114, reset 0x00000000
COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0
I2C0 QEI0 SSI0 UART2 UART1 UART0
DCGC1, type R/W, offset 0x124, reset 0x00000000
COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0
I2C0 QEI0 SSI0 UART2 UART1 UART0
RCGC2, type R/W, offset 0x108, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
SCGC2, type R/W, offset 0x118, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
DCGC2, type R/W, offset 0x128, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
SRCR0, type R/W, offset 0x040, reset 0x00000000
PWM ADC
HIB WDT
SRCR1, type R/W, offset 0x044, reset 0x00000000
COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0
I2C0 QEI0 SSI0 UART2 UART1 UART0
SRCR2, type R/W, offset 0x048, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Hibernation Module
Base 0x400F.C000
HIBRTCC, type RO, offset 0x000, reset 0x0000.0000
RTCC
RTCC
HIBRTCM0, type R/W, offset 0x004, reset 0xFFFF.FFFF
RTCM0
RTCM0
HIBRTCM1, type R/W, offset 0x008, reset 0xFFFF.FFFF
RTCM1
RTCM1
HIBRTCLD, type R/W, offset 0x00C, reset 0xFFFF.FFFF
RTCLD
RTCLD
November 30, 2007 557
Preliminary
LM3S6952 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HIBCTL, type R/W, offset 0x010, reset 0x0000.0000
VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBREQ RTCEN
HIBIM, type R/W, offset 0x014, reset 0x0000.0000
EXTW LOWBAT RTCALT1 RTCALT0
HIBRIS, type RO, offset 0x018, reset 0x0000.0000
EXTW LOWBAT RTCALT1 RTCALT0
HIBMIS, type RO, offset 0x01C, reset 0x0000.0000
EXTW LOWBAT RTCALT1 RTCALT0
HIBIC, type R/W1C, offset 0x020, reset 0x0000.0000
EXTW LOWBAT RTCALT1 RTCALT0
HIBRTCT, type R/W, offset 0x024, reset 0x0000.7FFF
TRIM
HIBDATA, type R/W, offset 0x030-0x12C, reset 0x0000.0000
RTD
RTD
Internal Memory
Flash Control Offset
Base 0x400F.D000
FMA, type R/W, offset 0x000, reset 0x0000.0000
OFFSET
OFFSET
FMD, type R/W, offset 0x004, reset 0x0000.0000
DATA
DATA
FMC, type R/W, offset 0x008, reset 0x0000.0000
WRKEY
COMT MERASE ERASE WRITE
FCRIS, type RO, offset 0x00C, reset 0x0000.0000
PRIS ARIS
FCIM, type R/W, offset 0x010, reset 0x0000.0000
PMASK AMASK
FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000
PMISC AMISC
Internal Memory
System Control Offset
Base 0x400F.E000
USECRL, type R/W, offset 0x140, reset 0x31
USEC
FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
558 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
USER_DBG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE
NW DATA
DATA DBG1 DBG0
USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF
NW DATA
DATA
USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF
NW DATA
DATA
FMPRE1, type R/W, offset 0x204, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE2, type R/W, offset 0x208, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE3, type R/W, offset 0x20C, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE2, type R/W, offset 0x408, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE3, type R/W, offset 0x40C, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
General-Purpose Input/Outputs (GPIOs)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIODATA, type R/W, offset 0x000, reset 0x0000.0000
DATA
GPIODIR, type R/W, offset 0x400, reset 0x0000.0000
DIR
GPIOIS, type R/W, offset 0x404, reset 0x0000.0000
IS
GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000
IBE
GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000
IEV
November 30, 2007 559
Preliminary
LM3S6952 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOIM, type R/W, offset 0x410, reset 0x0000.0000
IME
GPIORIS, type RO, offset 0x414, reset 0x0000.0000
RIS
GPIOMIS, type RO, offset 0x418, reset 0x0000.0000
MIS
GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000
IC
GPIOAFSEL, type R/W, offset 0x420, reset -
AFSEL
GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF
DRV2
GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000
DRV4
GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000
DRV8
GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000
ODE
GPIOPUR, type R/W, offset 0x510, reset -
PUE
GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000
PDE
GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000
SRL
GPIODEN, type R/W, offset 0x51C, reset -
DEN
GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001
LOCK
LOCK
GPIOCR, type -, offset 0x524, reset -
CR
GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
560 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061
PID0
GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
General-Purpose Timers
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000
GPTMCFG
GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000
TAAMS TACMR TAMR
GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000
TBAMS TBCMR TBMR
GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000
TBPWML TBOTE TBEVENT TBSTALL TBEN TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN
GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000
CBEIM CBMIM TBTOIM RTCIM CAEIM CAMIM TATOIM
GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000
CBERIS CBMRIS TBTORIS RTCRIS CAERIS CAMRIS TATORIS
November 30, 2007 561
Preliminary
LM3S6952 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPTMMIS, type RO, offset 0x020, reset 0x0000.0000
CBEMIS CBMMIS TBTOMIS RTCMIS CAEMIS CAMMIS TATOMIS
GPTMICR, type W1C, offset 0x024, reset 0x0000.0000
CBECINT CBMCINT TBTOCINT RTCCINT CAECINT CAMCINT TATOCINT
GPTMTAILR, type R/W, offset 0x028, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
TAILRH
TAILRL
GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF
TBILRL
GPTMTAMATCHR, type R/W, offset 0x030, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
TAMRH
TAMRL
GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF
TBMRL
GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000
TAPSR
GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000
TBPSR
GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000
TAPSMR
GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000
TBPSMR
GPTMTAR, type RO, offset 0x048, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
TARH
TARL
GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF
TBRL
Watchdog Timer
Base 0x4000.0000
WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF
WDTLoad
WDTLoad
WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF
WDTValue
WDTValue
WDTCTL, type R/W, offset 0x008, reset 0x0000.0000
RESEN INTEN
WDTICR, type WO, offset 0x00C, reset -
WDTIntClr
WDTIntClr
WDTRIS, type RO, offset 0x010, reset 0x0000.0000
WDTRIS
562 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTMIS, type RO, offset 0x014, reset 0x0000.0000
WDTMIS
WDTTEST, type R/W, offset 0x418, reset 0x0000.0000
STALL
WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000
WDTLock
WDTLock
WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005
PID0
WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018
PID1
WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Analog-to-Digital Converter (ADC)
Base 0x4003.8000
ADCACTSS, type R/W, offset 0x000, reset 0x0000.0000
ASEN3 ASEN2 ASEN1 ASEN0
ADCRIS, type RO, offset 0x004, reset 0x0000.0000
INR3 INR2 INR1 INR0
November 30, 2007 563
Preliminary
LM3S6952 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCIM, type R/W, offset 0x008, reset 0x0000.0000
MASK3 MASK2 MASK1 MASK0
ADCISC, type R/W1C, offset 0x00C, reset 0x0000.0000
IN3 IN2 IN1 IN0
ADCOSTAT, type R/W1C, offset 0x010, reset 0x0000.0000
OV3 OV2 OV1 OV0
ADCEMUX, type R/W, offset 0x014, reset 0x0000.0000
EM3 EM2 EM1 EM0
ADCUSTAT, type R/W1C, offset 0x018, reset 0x0000.0000
UV3 UV2 UV1 UV0
ADCSSPRI, type R/W, offset 0x020, reset 0x0000.3210
SS3 SS2 SS1 SS0
ADCPSSI, type WO, offset 0x028, reset -
SS3 SS2 SS1 SS0
ADCSAC, type R/W, offset 0x030, reset 0x0000.0000
AVG
ADCSSMUX0, type R/W, offset 0x040, reset 0x0000.0000
MUX7 MUX6 MUX5 MUX4
MUX3 MUX2 MUX1 MUX0
ADCSSCTL0, type R/W, offset 0x044, reset 0x0000.0000
TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
ADCSSFIFO0, type RO, offset 0x048, reset 0x0000.0000
DATA
ADCSSFIFO1, type RO, offset 0x068, reset 0x0000.0000
DATA
ADCSSFIFO2, type RO, offset 0x088, reset 0x0000.0000
DATA
ADCSSFIFO3, type RO, offset 0x0A8, reset 0x0000.0000
DATA
ADCSSFSTAT0, type RO, offset 0x04C, reset 0x0000.0100
FULL EMPTY HPTR TPTR
ADCSSFSTAT1, type RO, offset 0x06C, reset 0x0000.0100
FULL EMPTY HPTR TPTR
ADCSSFSTAT2, type RO, offset 0x08C, reset 0x0000.0100
FULL EMPTY HPTR TPTR
564 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCSSFSTAT3, type RO, offset 0x0AC, reset 0x0000.0100
FULL EMPTY HPTR TPTR
ADCSSMUX1, type RO, offset 0x060, reset 0x0000.0000
MUX3 MUX2 MUX1 MUX0
ADCSSMUX2, type RO, offset 0x080, reset 0x0000.0000
MUX3 MUX2 MUX1 MUX0
ADCSSCTL1, type RO, offset 0x064, reset 0x0000.0000
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
ADCSSCTL2, type RO, offset 0x084, reset 0x0000.0000
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
ADCSSMUX3, type R/W, offset 0x0A0, reset 0x0000.0000
MUX0
ADCSSCTL3, type R/W, offset 0x0A4, reset 0x0000.0002
TS0 IE0 END0 D0
ADCTMLB, type RO, offset 0x100, reset 0x0000.0000
CNT CONT DIFF TS MUX
ADCTMLB, type WO, offset 0x100, reset 0x0000.0000
LB
Universal Asynchronous Receivers/Transmitters (UARTs)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UARTDR, type R/W, offset 0x000, reset 0x0000.0000
OE BE PE FE DATA
UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000
OE BE PE FE
UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000
DATA
UARTFR, type RO, offset 0x018, reset 0x0000.0090
TXFE RXFF TXFF RXFE BUSY
UARTILPR, type R/W, offset 0x020, reset 0x0000.0000
ILPDVSR
UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000
DIVINT
UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000
DIVFRAC
November 30, 2007 565
Preliminary
LM3S6952 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000
SPS WLEN FEN STP2 EPS PEN BRK
UARTCTL, type R/W, offset 0x030, reset 0x0000.0300
RXE TXE LBE SIRLP SIREN UARTEN
UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012
RXIFLSEL TXIFLSEL
UARTIM, type R/W, offset 0x038, reset 0x0000.0000
OEIM BEIM PEIM FEIM RTIM TXIM RXIM
UARTRIS, type RO, offset 0x03C, reset 0x0000.000F
OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS
UARTMIS, type RO, offset 0x040, reset 0x0000.0000
OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS
UARTICR, type W1C, offset 0x044, reset 0x0000.0000
OEIC BEIC PEIC FEIC RTIC TXIC RXIC
UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011
PID0
UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
566 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Synchronous Serial Interface (SSI)
SSI0 base: 0x4000.8000
SSICR0, type R/W, offset 0x000, reset 0x0000.0000
SCR SPH SPO FRF DSS
SSICR1, type R/W, offset 0x004, reset 0x0000.0000
SOD MS SSE LBM
SSIDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
SSISR, type RO, offset 0x00C, reset 0x0000.0003
BSY RFF RNE TNF TFE
SSICPSR, type R/W, offset 0x010, reset 0x0000.0000
CPSDVSR
SSIIM, type R/W, offset 0x014, reset 0x0000.0000
TXIM RXIM RTIM RORIM
SSIRIS, type RO, offset 0x018, reset 0x0000.0008
TXRIS RXRIS RTRIS RORRIS
SSIMIS, type RO, offset 0x01C, reset 0x0000.0000
TXMIS RXMIS RTMIS RORMIS
SSIICR, type W1C, offset 0x020, reset 0x0000.0000
RTIC RORIC
SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022
PID0
SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
November 30, 2007 567
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Inter-Integrated Circuit (I2C) Interface
I2C Master
I2C Master 0 base: 0x4002.0000
I2CMSA, type R/W, offset 0x000, reset 0x0000.0000
SA R/S
I2CMCS, type RO, offset 0x004, reset 0x0000.0000
BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY
I2CMCS, type WO, offset 0x004, reset 0x0000.0000
ACK STOP START RUN
I2CMDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001
TPR
I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000
IM
I2CMRIS, type RO, offset 0x014, reset 0x0000.0000
RIS
I2CMMIS, type RO, offset 0x018, reset 0x0000.0000
MIS
I2CMICR, type WO, offset 0x01C, reset 0x0000.0000
IC
I2CMCR, type R/W, offset 0x020, reset 0x0000.0000
SFE MFE LPBK
Inter-Integrated Circuit (I2C) Interface
568 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C Slave
I2C Slave 0 base: 0x4002.0800
I2CSOAR, type R/W, offset 0x000, reset 0x0000.0000
OAR
I2CSCSR, type RO, offset 0x004, reset 0x0000.0000
FBR TREQ RREQ
I2CSCSR, type WO, offset 0x004, reset 0x0000.0000
DA
I2CSDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
I2CSIMR, type R/W, offset 0x00C, reset 0x0000.0000
IM
I2CSRIS, type RO, offset 0x010, reset 0x0000.0000
RIS
I2CSMIS, type RO, offset 0x014, reset 0x0000.0000
MIS
I2CSICR, type WO, offset 0x018, reset 0x0000.0000
IC
Ethernet Controller
Ethernet MAC
Base 0x4004.8000
MACRIS, type RO, offset 0x000, reset 0x0000.0000
PHYINT MDINT RXER FOV TXEMP TXER RXINT
MACIACK, type W1C, offset 0x000, reset 0x0000.0000
PHYINT MDINT RXER FOV TXEMP TXER RXINT
MACIM, type R/W, offset 0x004, reset 0x0000.007F
PHYINTM MDINTM RXERM FOVM TXEMPM TXERM RXINTM
MACRCTL, type R/W, offset 0x008, reset 0x0000.0008
RSTFIFO BADCRC PRMS AMUL RXEN
MACTCTL, type R/W, offset 0x00C, reset 0x0000.0000
DUPLEX CRC PADEN TXEN
MACDATA, type RO, offset 0x010, reset 0x0000.0000
RXDATA
RXDATA
MACDATA, type WO, offset 0x010, reset 0x0000.0000
TXDATA
TXDATA
November 30, 2007 569
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACIA0, type R/W, offset 0x014, reset 0x0000.0000
MACOCT4 MACOCT3
MACOCT2 MACOCT1
MACIA1, type R/W, offset 0x018, reset 0x0000.0000
MACOCT6 MACOCT5
MACTHR, type R/W, offset 0x01C, reset 0x0000.003F
THRESH
MACMCTL, type R/W, offset 0x020, reset 0x0000.0000
REGADR WRITE START
MACMDV, type R/W, offset 0x024, reset 0x0000.0080
DIV
MACMTXD, type R/W, offset 0x02C, reset 0x0000.0000
MDTX
MACMRXD, type R/W, offset 0x030, reset 0x0000.0000
MDRX
MACNP, type RO, offset 0x034, reset 0x0000.0000
NPR
MACTR, type R/W, offset 0x038, reset 0x0000.0000
NEWTX
Ethernet Controller
MII Management
Base 0x4004.8000
MR0, type R/W, address 0x00, reset 0x3100
RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT
MR1, type RO, address 0x01, reset 0x7849
100X_F 100X_H 10T_F 10T_H MFPS ANEGC RFAULT ANEGA LINK JAB EXTD
MR2, type RO, address 0x02, reset 0x000E
OUI[21:6]
MR3, type RO, address 0x03, reset 0x7237
OUI[5:0] MN RN
MR4, type R/W, address 0x04, reset 0x01E1
NP RF A3 A2 A1 A0 S[4:0]
MR5, type RO, address 0x05, reset 0x0000
NP ACK RF A[7:0] S[4:0]
MR6, type RO, address 0x06, reset 0x0000
PDF LPNPA PRX LPANEGA
MR16, type R/W, address 0x10, reset 0x0140
RPTR INPOL TXHIM SQEI NL10 APOL RVSPOL PCSBP RXCC
MR17, type R/W, address 0x11, reset 0x0000
JABBER_IE RXER_IE PRX_IE PDF_IE LPACK_IE LSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INT RXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT ANEGCOMP_INT
MR18, type RO, address 0x12, reset 0x0000
ANEGF DPLX RATE RXSD RX_LOCK
MR19, type R/W, address 0x13, reset 0x4000
TXO[1:0]
570 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR23, type R/W, address 0x17, reset 0x0010
LED1[3:0] LED0[3:0]
MR24, type R/W, address 0x18, reset 0x00C0
PD_MODE AUTO_SW MDIX MDIX_CM MDIX_SD
Analog Comparators
Base 0x4003.C000
ACMIS, type R/W1C, offset 0x00, reset 0x0000.0000
IN2 IN1 IN0
ACRIS, type RO, offset 0x04, reset 0x0000.0000
IN2 IN1 IN0
ACINTEN, type R/W, offset 0x08, reset 0x0000.0000
IN2 IN1 IN0
ACREFCTL, type R/W, offset 0x10, reset 0x0000.0000
EN RNG VREF
ACSTAT0, type RO, offset 0x20, reset 0x0000.0000
OVAL
ACSTAT1, type RO, offset 0x40, reset 0x0000.0000
OVAL
ACSTAT2, type RO, offset 0x60, reset 0x0000.0000
OVAL
ACCTL0, type R/W, offset 0x24, reset 0x0000.0000
TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV
ACCTL1, type R/W, offset 0x44, reset 0x0000.0000
TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV
ACCTL2, type R/W, offset 0x64, reset 0x0000.0000
TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV
Pulse Width Modulator (PWM)
Base 0x4002.8000
PWMCTL, type R/W, offset 0x000, reset 0x0000.0000
GlobalSync1 GlobalSync0
PWMSYNC, type R/W, offset 0x004, reset 0x0000.0000
Sync1 Sync0
PWMENABLE, type R/W, offset 0x008, reset 0x0000.0000
PWM3En PWM2En PWM1En PWM0En
PWMINVERT, type R/W, offset 0x00C, reset 0x0000.0000
PWM3Inv PWM2Inv PWM1Inv PWM0Inv
November 30, 2007 571
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LM3S6952 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWMFAULT, type R/W, offset 0x010, reset 0x0000.0000
Fault3 Fault2 Fault1 Fault0
PWMINTEN, type R/W, offset 0x014, reset 0x0000.0000
IntFault
IntPWM1 IntPWM0
PWMRIS, type RO, offset 0x018, reset 0x0000.0000
IntFault
IntPWM1 IntPWM0
PWMISC, type R/W1C, offset 0x01C, reset 0x0000.0000
IntFault
IntPWM1 IntPWM0
PWMSTATUS, type RO, offset 0x020, reset 0x0000.0000
Fault
PWM0CTL, type RO, offset 0x040, reset 0x0000.0000
CmpBUpd CmpAUpd LoadUpd Debug Mode Enable
PWM1CTL, type RO, offset 0x080, reset 0x0000.0000
CmpBUpd CmpAUpd LoadUpd Debug Mode Enable
PWM0INTEN, type RO, offset 0x044, reset 0x0000.0000
TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM1INTEN, type RO, offset 0x084, reset 0x0000.0000
TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM0RIS, type RO, offset 0x048, reset 0x0000.0000
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM1RIS, type RO, offset 0x088, reset 0x0000.0000
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM0ISC, type RO, offset 0x04C, reset 0x0000.0000
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM1ISC, type RO, offset 0x08C, reset 0x0000.0000
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM0LOAD, type RO, offset 0x050, reset 0x0000.0000
Load
PWM1LOAD, type RO, offset 0x090, reset 0x0000.0000
Load
PWM0COUNT, type RO, offset 0x054, reset 0x0000.0000
Count
PWM1COUNT, type RO, offset 0x094, reset 0x0000.0000
Count
572 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM0CMPA, type RO, offset 0x058, reset 0x0000.0000
CompA
PWM1CMPA, type RO, offset 0x098, reset 0x0000.0000
CompA
PWM0CMPB, type RO, offset 0x05C, reset 0x0000.0000
CompB
PWM1CMPB, type RO, offset 0x09C, reset 0x0000.0000
CompB
PWM0GENA, type RO, offset 0x060, reset 0x0000.0000
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
PWM1GENA, type RO, offset 0x0A0, reset 0x0000.0000
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
PWM0GENB, type RO, offset 0x064, reset 0x0000.0000
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
PWM1GENB, type RO, offset 0x0A4, reset 0x0000.0000
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
PWM0DBCTL, type RO, offset 0x068, reset 0x0000.0000
Enable
PWM1DBCTL, type RO, offset 0x0A8, reset 0x0000.0000
Enable
PWM0DBRISE, type RO, offset 0x06C, reset 0x0000.0000
RiseDelay
PWM1DBRISE, type RO, offset 0x0AC, reset 0x0000.0000
RiseDelay
PWM0DBFALL, type RO, offset 0x070, reset 0x0000.0000
FallDelay
PWM1DBFALL, type RO, offset 0x0B0, reset 0x0000.0000
FallDelay
Quadrature Encoder Interface (QEI)
QEI0 base: 0x4002.C000
QEICTL, type R/W, offset 0x000, reset 0x0000.0000
STALLEN INVI INVB INVA VelDiv VelEn ResMode CapMode SigMode Swap Enable
QEISTAT, type RO, offset 0x004, reset 0x0000.0000
Direction Error
QEIPOS, type R/W, offset 0x008, reset 0x0000.0000
Position
Position
November 30, 2007 573
Preliminary
LM3S6952 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QEIMAXPOS, type R/W, offset 0x00C, reset 0x0000.0000
MaxPos
MaxPos
QEILOAD, type R/W, offset 0x010, reset 0x0000.0000
Load
Load
QEITIME, type RO, offset 0x014, reset 0x0000.0000
Time
Time
QEICOUNT, type RO, offset 0x018, reset 0x0000.0000
Count
Count
QEISPEED, type RO, offset 0x01C, reset 0x0000.0000
Speed
Speed
QEIINTEN, type R/W, offset 0x020, reset 0x0000.0000
IntError IntDir IntTimer IntIndex
QEIRIS, type RO, offset 0x024, reset 0x0000.0000
IntError IntDir IntTimer IntIndex
QEIISC, type R/W1C, offset 0x028, reset 0x0000.0000
IntError IntDir IntTimer IntIndex
574 November 30, 2007
Preliminary
Register Quick Reference
C Ordering and Contact Information
C.1 Ordering Information
L M 3 S n n n n – g p p s s – r r m
Part Number
Temperature
Package
Speed
Revision
Shipping Medium
I = -40 C to 85 C
T = Tape-and-reel
Omitted = Default shipping (tray or tube)
Omitted = Default to current shipping
revision
A0 = First all-layer mask
A1 = Metal layers update to A0
A2 = Metal layers update to A1
B0 = Second all-layer mask revision
RN = 28-pin SOIC
QN = 48-pin LQFP
QC = 100-pin LQFP
20 = 20 MHz
25 = 25 MHz
50 = 50 MHz
Table C-1. Part Ordering Information
Orderable Part Number Description
Stellaris® LM3S6952-IQC50 LM3S6952 Microcontroller
Stellaris® LM3S6952-IQC50(T) LM3S6952 Microcontroller
C.2 Kits
The Luminary Micro Stellaris® Family provides the hardware and software tools that engineers need
to begin development quickly.
■ Reference Design Kits accelerate product development by providing ready-to-run hardware, and
comprehensive documentation including hardware design files:
http://www.luminarymicro.com/products/reference_design_kits/
■ Evaluation Kits provide a low-cost and effective means of evaluating Stellaris® microcontrollers
before purchase:
http://www.luminarymicro.com/products/evaluation_kits/
■ Development Kits provide you with all the tools you need to develop and prototype embedded
applications right out of the box:
http://www.luminarymicro.com/products/boards.html
See the Luminary Micro website for the latest tools available or ask your Luminary Micro distributor.
C.3 Company Information
Luminary Micro, Inc. designs, markets, and sells ARM Cortex-M3-based microcontrollers (MCUs).
Austin, Texas-based Luminary Micro is the lead partner for the Cortex-M3 processor, delivering the
world's first silicon implementation of the Cortex-M3 processor. Luminary Micro's introduction of the
November 30, 2007 575
Preliminary
LM3S6952 Microcontroller
Stellaris® family of products provides 32-bit performance for the same price as current 8- and 16-bit
microcontroller designs. With entry-level pricing at $1.00 for an ARM technology-based MCU,
Luminary Micro's Stellaris product line allows for standardization that eliminates future architectural
upgrades or software tool changes.
Luminary Micro, Inc.
108 Wild Basin, Suite 350
Austin, TX 78746
Main: +1-512-279-8800
Fax: +1-512-279-8879
http://www.luminarymicro.com
sales@luminarymicro.com
C.4 Support Information
For support on Luminary Micro products, contact:
support@luminarymicro.com +1-512-279-8800, ext. 3
576 November 30, 2007
Preliminary
Ordering and Contact Information
Evaluation Board User Guide
UG-146
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the ADE7878 Energy Metering IC
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 36
FEATURES
Evaluation board designed to be used with accompanying software to implement a fully functional 3-phase energy meter Easy connection of external transducers via screw terminals Easy modification of signal conditioning components using PCB sockets LED indicators on the CF1, CF2, CF3, IRQ0, and IRQ1 logic outputs Optically isolated metering components and USB-based communication with a PC External voltage reference option available for on-chip reference evaluation PC COM port-based firmware updates
GENERAL DESCRIPTION
The ADE7878 is a high accuracy, 3-phase electrical energy measurement IC with serial interfaces and three flexible pulse outputs. The ADE7878 incorporates seven ADCs, reference circuitry, and all signal processing required to perform total (fundamental and harmonic) active, reactive, and apparent energy measurement, fundamental active and reactive energy measurement, and rms calculations.
This user guide describes the ADE7878 evaluation kit hardware, firmware, and software functionality. The evaluation board contains an ADE7878 and a LPC2368 microcontroller (from NXP Semiconductors). The ADE7878 and its associated metering components are optically isolated from the microcontroller. The microcontroller communicates with the PC using a USB interface. Firmware updates can be loaded using one PC com port and a regular serial cable.
The ADE7878 evaluation board and this user guide, together with the ADE7878 data sheet, provide a complete evaluation platform for the ADE7878.
The evaluation board has been designed so that the ADE7878 can be evaluated in an energy meter. Using appropriate current transducers, the evaluation board can be connected to a test bench or high voltage (240 V rms) test circuit. On-board resistor divider networks provide the attenuation for the line voltages. This user guide describes how the current transducers should be connected for the best performance. The evaluation board requires two external 3.3 V power supplies and the appropriate current transducers.
EVALUATION BOARD CONNECTION DIAGRAM
ADE78xxP1P2P3P4P5P6P7P8P9IAPIANIBPIBNICPICNINPINNGNDVNGNDVCPGNDVBPGNDVAPGNDVDDFILTERNETWORKFILTER NETWORKAND ATTENUATIONADR280OPTIONAL EXTERNAL1.2V REFERENCEOPTIONALEXTERNALCLOCK INDIGITALISOLATORSLPC2368P10GND2VDD2P12MCU_GNDMCU_VDDUSB PORTJ2J3J4CF3CF2CF1P13JTAGINTERFACEP15CONNECTOR TOPC COM PORT09078-001 Figure 1.
UG-146 Evaluation Board User Guide
Rev. 0 | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Evaluation Board Connection Diagram ........................................ 1
Revision History ............................................................................... 2
Evaluation Board Hardware ............................................................ 3
Power Supplies .............................................................................. 3
Analog Inputs (P1 to P4 and P5 to P8) ...................................... 3
Setting Up the Evaluation Board as an Energy Meter ............. 6
Evaluation Board Software .............................................................. 8
Installing and Uninstalling the ADE7878 Software ................. 8
Front Panel .................................................................................... 8
PSM0 Mode—Normal Power Mode .......................................... 9
PSM1 Mode ................................................................................. 17
PSM2 Mode ................................................................................. 17
PSM3 Mode ................................................................................. 18
Managing the Communication Protocol Between the Microcontroller and the ADE7878 .............................................. 19
Acquiring HSDC Data Continuously ...................................... 21
Starting the ADE7878 DSP ....................................................... 22
Stopping the ADE7878 DSP ..................................................... 22
Upgrading Microcontroller Firmware ......................................... 23
Control Registers Data File ....................................................... 23
Evaluation Board Schematics and Layout ................................... 25
Schematic..................................................................................... 25
Layout .......................................................................................... 32
Ordering Information .................................................................... 34
Bill of Materials ........................................................................... 34
REVISION HISTORY
8/10—Revision 0: Initial Version
Evaluation Board User Guide UG-146
Rev. 0 | Page 3 of 36
EVALUATION BOARD HARDWARE
POWER SUPPLIES
The evaluation board has three power domains: one that supplies the microcontroller and one side of the isocouplers, one that supplies the other side of the optocouplers, and one that supplies the ADE7878. The ground of the microcontroller’s power domain is connected to the ground of the PC through the USB cable. The ground of the ADE7878 power domain is determined by the ground of the phase voltages, VAP, VBP, VCP, and VN, and must be different from the ground of the micro-controller’s power domain.
The microcontroller 3.3 V supply is provided at the P12 connector. The ADE7878 3.3 V supply is provided at the P9 connector. Close jumper JP2 to ensure that the same 3.3 V supply from ADE7878 is also provided at the isocouplers.
ANALOG INPUTS (P1 TO P4 AND P5 TO P8)
Current and voltage signals are connected at the screw terminal, P1 to P4 and P5 to P8, respectively. All analog input signals are filtered using the on-board antialiasing filters before the signals are connected to the ADE7878. The components used on the board are the recommended values to be used with the ADE7878.
Current Sense Inputs (P1, P2, P3, and P4)
The ADE7878 measures three phase currents and the neutral current. Current transformers or Rogowski coils can be used to sense the current but should not be mixed together. The ADE7878 contains different internal PGA gains on phase currents and on the neutral current; therefore, sensors with different ratios can be used. The only requirement is to have the same scale signals at the PGA outputs; otherwise, the mismatch functionality of the ADE7878 is compromised (see the ADE7878 data sheet for more details about neutral current mismatch). Figure 2 shows the structure used for the Phase A current; the sensor outputs are connected to the P1 connector. The R1 and R2 resistors are the burden resistors and, by default, they are not populated. They can also be disabled using the JP1A and JP2A jumpers. The R9/C9 and R10/C10 RC networks are used in conjunction with Rogowski coils. They can be disabled using the JP3A and JP4A jumpers. The R17/C17 and R18/C18 RC networks are the antialiasing filters. The default corner frequency of these low pass filters is 7.2 kHz (1 kΩ/22 nF). These filters can easily be adjusted by replacing the components on the evaluation board. All the other current channels (that is, Phase B, Phase C, and the neutral current) have a similar input structure.
Using a Current Transformer as the Current Sensor
Figure 3 shows how a current transformer can be used as a current sensor in one phase of a 3-phase, 4-wire distribution system (Phase A). The other two phases and the neutral current require similar connections. P1IAPIANJP1AJP2AR1R2R17R10R18100Ω1kΩ100Ω1kΩC922,000pFC1022,000pFC1722,000pFC1822,000pFR9JP4AJP5AJP3AJP6AIAPIANADE78xxTP1TP209078-002
Figure 2. Phase A Current Input Structure on the Evaluation Board IMAX = 6A rmsCT1:2000P1JP1AJP2AR150ΩR250ΩR17R10R18100Ω1kΩ100Ω1kΩC922,000pFC1022,000pFC1722,000pFC1822,000pFR9JP4AJP5AJP3AJP6AIAPIANADE78xxTP1TP209078-003
Figure 3. Example of a Current Transformer Connection The R1 and R2 burden resistors must be defined as functions of the current transformer ratio and maximum current of the system, using the following formula: R1 = R2 = 1/2 × 0.5/sqrt(2) × N/IFS where: 0.5/sqrt(2) is the rms value of the full-scale voltage accepted at the ADC input. N is the input-to-output ratio of the current transformer. IFS is the maximum rms current to be measured.
The JP1A and JP2A jumpers should be opened if R1 and R2 are used. The antialiasing filters should be enabled by opening the J5A and J6A jumpers (see Figure 3). The secondary current of the transformer is converted to a voltage by using a burden resistor across the secondary winding outputs. Care should be taken when using a current transformer as the current sensor. If the secondary is left open (that is, no burden is connected), a large voltage may be present at the secondary outputs. This can cause an electric shock hazard and potentially damage electronic components.
Most current transformers introduce a phase shift that the manufacturer indicates in the data sheet. This phase shift can lead to significant energy measurement errors, especially at low power factors. The ADE7878 can correct the phase error using the APHCAL[9:0], BPHCAL[9:0], and CPHCAL[9:0] phase calibration registers as long as the error stays between −6.732° and +1.107° at 50 Hz (see the ADE7878 data sheet for more
UG-146 Evaluation Board User Guide
Rev. 0 | Page 4 of 36
details). The software supplied with the ADE7878 evaluation board allows user adjustment of phase calibration registers.
For this particular example, burden resistors of 50 Ω signify an input current of 7.05 A rms at the ADE7878 ADC full-scale input (0.5 V). In addition, the PGA gains for the current channel must be set at 1. For more information about setting PGA gains, see the ADE7878 data sheet. The evaluation software allows the user to configure the current channel gain.
Using a Rogowski Coil as the Current Sensor
Figure 4 shows how a Rogowski coil can be used as a current sensor in one phase of a 3-phase, 4-wire distribution system (Phase A). The other two phases and the neutral current require similar connections. The Rogowski coil does not require any burden resistors; therefore, R1 and R2 should not be populated. The antialiasing filters should be enabled by opening the J5A and J6A jumpers. To account for the high frequency noise introduced by the coil, an additional antialiasing filter must be introduced by opening the JP3A and JP4A jumpers. Then, to compensate for the 20 dB/dec gain introduced by the di/dt sensor, the integrator of the ADE7878 must be enabled by setting Bit 0 (INTEN) of the CONFIG register. The integrator has a −20 dB/dec attenuation and an approximately −90° phase shift and, when combined with the di/dt sensor, results in a magnitude and phase response with a flat gain over the frequency band of interest. ROGOWSKICOILP1JP1AJP2AR1R2R17R10R18100Ω1kΩ100Ω1kΩC922,000pFC1022,000pFC1722,000pFC1822,000pFR9JP4AJP5AJP3AJP6AIAPIANADE78xxTP1TP209078-004
Figure 4. Example of a Rogowski Coil Connection
Voltage Sense Inputs (P5, P6, P7, and P8 Connectors)
The voltage input connections on the ADE7878 evaluation board can be directly connected to the line voltage sources. The line voltages are attenuated using a simple resistor divider network before they are supplied to the ADE7878. The attenuation network on the voltage channels is designed so that the corner frequency (3 dB frequency) of the network matches that of the antialiasing filters in the current channel inputs. This prevents the occurrence of large energy errors at low power factors.
Figure 5 shows a typical connection of the Phase A voltage inputs; the resistor divider is enabled by opening the JP7A jumper. The antialiasing filter on the VN data path is enabled by opening the JP7N jumper. JP8A and JP8N are also opened. The VN analog input is connected to AGND via the R25/C25 antialiasing filter using the JP8N connector. The attenuation networks can be easily modified by the user to accommodate any input level. However, the value of R32 (1 kΩ), should be modified only together with the corresponding resistors in the current channel (R17 and R18 on the Phase A current data path). P8JP8AVAPVNR291MΩ100kΩR321kΩC3222,000pFC2522,000pFR26JP7AVAPADE78xxTP12JP9AVNPHASE ANEUTRALP5JP8N1kΩR25JP7NVNTP9ACOMB12309078-005
Figure 5. Phase A Voltage Input Structure on the Evaluation Board
The maximum signal level permissible at the VAP, VBP, and VCP pins of the ADE7878 is 0.5 V peak. Although the ADE7878 analog inputs can withstand ±2 V without risk of permanent damage, the signal range should not exceed ±0.5 V with respect to AGND for a specified operation.
Evaluation Board User Guide UG-146
Rev. 0 | Page 5 of 36 Table 1. Recommended Settings for Evaluation Board Connectors Jumper Option Description
JP1 Soldered Connects AGND to ground. By default, it is soldered. JP1A, JP1B,
JP1C, JP1N,
Open Connect IAP, IBP, IC, and INP to AGND. By default, they are open.
JP2 Closed Connects the ADE7878 VDD power supply (VDD_F at the P9 connector) to the power supply of the
isocouplers (VDD2 at the P10 connector). By default, it is closed. JP2A, JP2B,
JP2C, JP2N
Open Connect IAN, IBN, ICN, and INN to AGND. By default, they are open.
JP3 Unsoldered Connects the pad metal below the ADE7878 to AGND. By default, it is unsoldered.
JP3A, JP3B,
JP3C, JP3N
Closed Disable the phase compensation network in the IAP, IBP, ICP, and INP data path. By default, they are
closed. JP4 Soldered Connects C3 to DVDD. By default, it is soldered.
JP4A, JP4B,
JP4C, JP4N
Closed Disable the phase compensation network in the IAN, IBN, ICN, and INN data path. By default, they are
closed. JP5 Soldered Connects C5 to AVDD. By default, it is soldered.
JP5A, JP5B,
JP5C, JP5N
Open Disable the phase antialiasing filter in the IAP, IBP, ICP, and INP data path. By default, they are open.
JP6 Soldered Connects C41 to the REF pin of the ADE7878. By default, it is soldered. JP6A, JP6B,
JP6C, JP6N
Open Disable the phase antialiasing filter in the IAN, IBN, ICN, and INN data path. By default, they are open.
JP7 Closed Enables the supply to the microcontroller. When open, takes out the supply to the microcontroller. By default, it is closed.
JP7A, JP7B,
JP7C
Open Disable the resistor divider in the VAP, VBP, and VCP data path. By default, they are open.
JP7N Open Disables the antialiasing filter in the VN data path. By default, it is open.
JP8 Open Sets the microcontroller in flash memory programming mode. By default, it is open.
JP8A, JP8B,
JP8C
Open Connect VAP, VBP, and VCP to AGND. By default, they are open.
JP8N Closed Connects VN to AGND. By default, it is closed.
JP9 Open When closed, signals the microcontroller to declare all I/O pins as outputs. It is used when another
microcontroller is used to manage the ADE7878 through the P38 socket. By default, it is open. JP9A, JP9B,
JP9C
Soldered to Pin
1 (AGND) Connect the ground of antialiasing filters in the VAP, VB, and VCP data path to AGND or VN. By default,
they are soldered to AGND. JP10 Open Connects the external voltage reference to ADE7878. By default, it is open. JP11 Soldered to Pin
1
Connects the CLKIN pin of the ADE7878 to a 16,384 MHz crystal (Pin 1 of JP11) or to an external clock
input provided at J1. By default, it is soldered to Pin 1.
JP12 Soldered to Pin
3 (AGND) Connects DGND (Pin 2 of JP12) of the ADE7878 to ground (Pin 1 of JP12) or to AGND (Pin 3 of JP12).
JP35, JP33 Open If I2C communication between the NXP LPC2368 and the ADE7878 is used, these connectors should be
closed with 0 Ω resistors, and the JP36 and JP34 connectors should be opened. By default, the SPI is the
communication used between the NXP LPC2368 and the ADE7878; therefore, these connectors are open. JP31, JP37 Open If HSDC communication is used, these connectors should be closed with 0 Ω resistors, and the JP35 and JP33 connectors should also be closed. By default, the SPI is the communication used between the NXP
LPC2368 and the ADE7878; therefore, these connectors are open.
JP36, JP34,
JP32, JP38
Closed with
0 Ω resistors If SPI communication is used between the NXP LPC2368 and the ADE7878, these connectors should be
closed and JP35, JP33, JP31, and JP37 should be opened. By default, the SPI is the communication used
between the NXP LPC2368 and the ADE7878; therefore, these connectors are closed.
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SETTING UP THE EVALUATION BOARD AS AN ENERGY METER
Figure 6 shows a typical setup for the ADE7878 evaluation board. In this example, an energy meter for a 4-wire, 3-phase distribution system is shown. Current transformers are used to sense the phase and neutral currents and are connected as shown in Figure 6. The line voltages are connected directly to the evaluation board as shown. Note that the state of all jumpers must match the states shown in Figure 6, keeping in mind that the board is supplied from two different 3.3 V power supplies, one for the ADE7878 domain, VDD, and one for the NXP LPC2368 domain, MCU_VDD. Because the two domains are isolated to ensure that there is no electrical connection between the high voltage test circuit and the control circuit, the power supplies should have floating voltage outputs. The evaluation board is connected to the PC using a regular USB cable supplied with the board. When the evaluation board is powered up and connected to the PC, the enumeration process begins and the PC recognizes new hardware and asks to install the appropriate driver. The drive can be found in the VirCOM_ Driver_XP folder of the CD. After the driver is installed, the supplied evaluation software can be launched. The next section describes the ADE7878 evaluation software in detail and how it can be installed and uninstalled.
Activating Serial Communication Between the ADE7878 and the NXP LPC2368
The ADE7878 evaluation board is supplied with communica-tion between the ADE7878 and the NXP LPC2368 that is set through the SPI ports. The JP32, JP34, JP36, and JP38 jumpers are closed using 0 Ω resistors, and the JP31, JP33, JP35, and JP37 jumpers are open. The SPI port should be chosen as the active port in the ADE7878 control panel.
Communication between the ADE7878 and the NXP LPC2368 is also possible using the I2C ports. To accomplish this, the JP31, JP33, JP35, and JP37 jumpers should be closed using 0 Ω resistors, and the JP32, JP34, JP36, and JP38 jumpers should be open. In this case, the I2C port should be chosen as the active port in the ADE7878 control panel (see Table 2).
Table 2. Jumper State to Activate SPI or I2C Communication
Active Communication
Jumpers Closed with 0 Ω Resistors
Jumpers Open
SPI (Default)
JP32, JP34, JP36, JP38
JP31, JP33, JP35, JP37
I2C
JP31, JP33, JP35, JP37
JP32, JP34, JP36, JP38
Using the Evaluation Board with Another Microcontroller
It is possible to manage the ADE7878 mounted on the evalua-tion board with a different microcontroller mounted on another board. The ADE7878 can be connected to this second board through one of two connectors: P11 or P38. P11 is placed on the same power domain as the ADE7878. P38 is placed on the power domain of the NXP LPC2368 and communicates with the ADE7878 through the isocouplers. If P11 is used, the power domain of the NXP LPC2368 should not be supplied at P12. If P38 is used, a conflict may arise with the NXP LPC2368 I/O ports. The following two options are provided to deal with this situation:
• One option is to keep the NXP LPC2368 running and close JP9. This tells the NXP LPC2368 to set all of its I/Os high to allow the other microcontroller to communicate with the ADE7878. After JP9 is closed, the S2 reset button should be pressed low to force the NXP LPC2368 to reset. This is necessary because the state of JP9 is checked inside the NXP LPC2368 program only once after reset.
• The other option is to cut the power supply of the NXP LPC2368 by disconnecting JP7.
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P1IAPIANIAPIANVAPVOLTAGE SOURCEGNDP9VDDJP1A, JP2A = OPENJP3A, JP4A = CLOSEDJP5A, JP6A = OPENNEUTRALPHASE BPHASE CLOADNEUTRALVOLTAGE SOURCEMCU_GNDP12MCU_VDDJP1, JP2 = CLOSEDR1R2P2IBPIBNIBPIBNJP1B, JP2B = OPENJP3B, JP4B = CLOSEDJP5B, JP6B = OPENR3R4P3ICPICNICPICNJP1C, JP2C = OPENJP3C, JP4C = CLOSEDJP5C, JP6C = OPENR5R6P4INPINNINPINNJP1N, JP2N = OPENJP3N, JP4N = CLOSEDJP5N, JP6N = OPENJP7A, JP8A = OPENR7R8P8VAPR26R29R32C32VBPJP7B, JP8B = OPENP7VBPR27R30R33C33VCPJP7C, JP8C = OPENJP7N = OPENJP8N = CLOSEDP6VCPR28R31R34C34C34VNP5VNR2509078-006
Figure 6. Typical Setup for the ADE7878 Evaluation Board
UG-146 Evaluation Board User Guide
Rev. 0 | Page 8 of 36 EVALUATION BOARD SOFTWARE
The ADE7878 evaluation board is supported by Windows®
based software that allows the user to access all the functionality
of the ADE7878. The software communicates with the NXP
LPC2368 microcontroller using the USB as a virtual COM port.
The NXP LPC2368 communicates with the ADE7878 to process the requests that are sent from the PC. INSTALLING AND UNINSTALLING THE ADE7878
SOFTWARE
The ADE7878 software is supplied on one CD-ROM. It contains two projects: one that represents the NXP LPC2368
project and one LabVIEW™ based program that runs on the PC.
The NXP LPC2368 project is already loaded into the processor, but the LabVIEW based program must be installed. 1. To install the ADE7878 software, place the CD-ROM in the CD-ROM reader and double-click
LabView_project\installation_files\setup.exe. This
launches the setup program that automatically installs all the software components, including the uninstall
program, and creates the required directories. 2. To launch the software, go to the Start/Programs/ ADE7878 Eval Software menu and click ADE7878
Eval Software.
Both the ADE7878 evaluation software program and the NI
run-time engine are easily uninstalled by using the Add/ Remove Programs option in the control panel. 1. Before installing a new version of the ADE7878 evaluation software, first uninstall the previous version. 2. Select the Add/Remove Programs option in the Windows control panel. 3. Select the program to uninstall and click the Add/Remove
button. FRONT PANEL When the software is launched, the Front Panel is opened. This panel contains three areas: the main menu at the left, the sub-
menu at the right, and a box that displays the name of the communication port used by the PC to connect to the
evaluation port, also at the right (see Figure 7). The COM port used to connect the PC with the evaluation board must be selected first. The program displays a list of the
active COM ports, allowing you to select the right one. To learn
what COM port is used by the evaluation board, launch the
Windows Device Manager (the devmgmt.msc file) in the Run
window on the Windows Start menu. By default, the program offers the option of searching for the COM port. Serial communication between the microcontroller and the
ADE7878 is introduced using a switch. By default, the SPI port is used. Note that the active serial port must first be set in the
hardware. See the Activating Serial Communication Between the ADE7878 and the NXP LPC2368 section for details on how
to set it up. The main menu has only one choice, other than Exit, enabled,
Find COM Port. Clicking it starts a process in which the PC
tries to connect to the evaluation board using the port indicated
in the Start menu. It uses the echo function of the communica-
tion protocol (see the Managing the Communication Protocol Between the Microcontroller and the ADE7878 section). It displays the port that matches the protocol and then sets it to 115,200 baud, eight data bits, no parity, no flow control, one
stop bit. 09078-007
Figure 7. Front Panel of ADE7878 Software If the evaluation board is not connected, the port is displayed as
XXXXX. In this case, the evaluation software is still accessible, but no communication can be executed. In both cases, whether
the search for the COM port is successful or not, the cursor is
positioned back at Please select from the following options in
the main menu, Find COM Port is grayed out, and the next main menu options are enabled (see Figure 8). These options allow
you to command the ADE7878 in either the PSM0 or PSM3
power mode. The other power modes, PSM1 and PSM2, are not
available because initializations have to be made in PSM0 before the ADE7878 can be used in one of these other modes.
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09078-008
Figure 8. Front Panel After the COM Port Is Identified
PSM0 MODE—NORMAL POWER MODE
Enter PSM0 Mode
When the evaluation board is powered up, the ADE7878 is in PSM3 sleep mode. When Enter PSM0 mode is selected, the microcontroller manipulates the PM0 and PM1 pins of the ADE7878 to switch it into PSM0 mode. It waits 50 ms for the circuit to power up and, if SPI communication is activated on the board, it executes three SPI write operations to Address 0xEBFF of the ADE7878 to activate the SPI port. If the operation has been correctly executed or I2C communi-cation is used, the message Configuring LPC2368 – ADE7878 communication was successful is displayed, and you must click OK to continue. The only error that may occur during this operation is communication related; if this happens, the following message is displayed: Configuring LPC2368 – ADE7878 communication was not successful. Please check the communication between the PC and ADE7878 evaluation board and between LPC2368 and ADE78xx.
Bit 1 (I2C_LOCK) of the CONFIG2[7:0] register is now set to 1 to lock in the serial port choice. Then the DICOEFF register is initialized with 0xFF8000, and the DSP of the ADE7878 is started when the software program writes RUN = 0x1. At the end of this process, the entire main menu is grayed out, and the submenu is enabled. You can now manage all functionality of the ADE7878 in PSM0 mode. To switch the ADE7878 to another power mode, click the Exit button on the submenu. The state of the Front Panel is shown in Figure 9.
09078-009
Figure 9. Front Panel After the ADE7878 Enters PSM0 Mode
Reset ADE7878
When Reset ADE78xx is selected on the Front Panel, the RESET pin of the ADE7878 is kept low for 20 ms and then is set high. If the operation is correctly executed, the message ADE7878 was reset successfully is displayed, and you must click OK to continue. The only error that may occur during this operation is communication related; if this happens, the following message is displayed: The communication between PC and ADE7878 evaluation board or between LPC2368 and ADE78xx did not function correctly. There is no guarantee the reset of ADE7878 has been performed.
Configure Communication
When Configure Communication is selected on the Front Panel, the panel shown in Figure 10 is opened. This panel is useful if an ADE7878 reset has been performed and the SPI is no longer the active serial port. Select the SPI port by clicking the I2C/SPI Selector button and then click OK to update the selection and lock the port. If the port selection is successful, the message, Configuring LPC2368 – ADE7878 communica-tion was successful, is displayed, and you must click OK to continue. If a communication error occurs, the message, Configuring LPC2368 – ADE7878 communication was not successful. Please check the communication between the PC and ADE7878 evaluation board, is displayed.
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09078-010
Figure 10. Configure Communication Panel The CONFIG2[7:0] register is written with Bit 1 (I2C_LOCK) set to 1 so that you do not need to remember to set it once the communication is set. The contents of CONFIG2[7:0] are then read back and displayed with Bit 1 (I2C_LOCK). To close the panel, click the Exit button; the cursor is positioned at Please select from the following options in the submenu of the Front Panel.
Total Active Power
When Total Active Power is selected on the Front Panel, the panel shown in Figure 11 is opened. The screen has an upper half and a lower half: the lower half shows the total active power data path of one phase, and the upper half shows bits, registers, and commands necessary to power management. 09078-011
Figure 11. Total Active Power Panel
The Active Data Path button manages which data path is shown in the bottom half. Some registers or bits, like the WTHR0[23:0] register or Bit 0 (INTEN) of the CONFIG[15:0] register, are common to all data paths, independent of the phase shown. When these registers are updated, all the values in all data paths are updated. The HPFDIS[23:0] register is included twice in the data path, but only the register value from the current data path is written into the ADE7878. All the other instances take this value directly.
1. Click the Read Configuration button to cause all registers that manage the total active power to be read and displayed. Registers from the inactive data paths are also read and updated.
2. Click the Write Configuration button to cause all registers that manage the total active power to be written into the ADE7878. Registers from the inactive data paths are also written. The ADE78xx status box shows the power mode that the ADE7878 is in (it should always be PSM0 in this window), the active serial port (it should always be SPI), and the CHECKSUM[31:0] register. After every read and write operation, the CHECKSUM[31:0] register is read and its contents displayed.
3. Click the CFx Configuration button to open a new panel (see Figure 12). This panel gives access to all bits and registers that configure the CF1, CF2, and CF3 outputs of the ADE7878. The Read Setup and Write Setup buttons update and display the CF1, CF2, and CF3 output values.
09078-012
Figure 12. CFx Configuration Panel Like the Total Active Power panel, the CHECKSUM[31:0] register is read back whenever a read or write operation is executed in the CFx Configuration panel. To select more than one option for a TERMSELx bit in the COMPMODE [15:0] register, press the CTRL key while clicking the options you want.
Clicking the Exit button closes the panel and redisplays the Total Active Power panel. When the Read Energy Registers button in the Total Active Power panel is clicked, a new panel is opened (see Figure 13). This panel gives access to bits and registers that configure the energy accumulation. The Read Setup and Write Setup buttons update and display the bit and register values.
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The CHECKSUM[31:0] register is read back whenever a read or write operation is executed in the Read Energy Registers panel. Clicking the Read all energy registers button causes all energy registers to be read immediately, without regard to the modes in which they function. 09078-013
Figure 13. Read Energy Registers Panel The panel also gives the choice of reading the energy registers synchronous to CFx interrupts (pulses) or using line cycle accumulation mode. When the Read energy registers synchronous with CF1 pulses button is clicked, the following happens:
1. The STATUS0[31:0] register is read and then written back to so that all nonzero interrupt flag bits are cancelled.
2. Bit 14 (CF1) in the MASK0[31:0] register is set to 1, and the interrupt protocol is started (see the Managing the Communication Protocol Between the Microcontroller and the ADE7878 section for protocol details).
3. The microcontroller then waits until the IRQ0 pin goes low. If the wait is longer than the timeout you indicate in 3 sec increments, the following error message is displayed: No CF1 pulse was generated. Verify all the settings before attempting to read energy registers in this mode!
4. When the IRQ0 pin goes low, the STATUS0[31:0] register is read and written back to cancel Bit 14 (CF1); then the energy registers involved in the CF1 signal are read and their contents are displayed. A timer in 10 ms increments can be used to measure the reaction time after the IRQ0 pin goes low.
5. The operation is repeated until the button is clicked again.
The process is similar when the other CF2, CF3, and line accum-ulation (Read Energy Registers panel) buttons are clicked. It is recommended to always use a timeout when dealing with interrupts. By default, the timeout is set to 10 (indicating a 30 sec timeout), and the timer is set to 0 (indicating that the STATUSx[31:0] and energy registers are read immediately after the IRQ0 pin goes low).
When clicked on the Front Panel, the Total Reactive Power, Fundamental Active Power, and Fundamental Reactive Power buttons open panels that are very similar to the Total Active Power panel. These panels are shown in Figure 14, Figure 15, and Figure 16.
09078-014
Figure 14. Total Reactive Power Panel 09078-015
Figure 15. Fundamental Active Power Panel 09078-016
Figure 16. Fundamental Reactive Power Panel
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Apparent Power
When Apparent Power is selected on the Front Panel, a new panel is opened (see Figure 17). Similar to the other panels that deal with power measurement, this panel is divided into two parts: the lower half shows the apparent power data path of one phase and the ADE7878 status; the upper half shows the bits, registers, and commands necessary to power management. 09078-017
Figure 17. Apparent Power Panel
Current RMS
When RMS Current is selected on the Front Panel, a new panel is opened (see Figure 18). All data paths of all phases are available. 09078-018
Figure 18. Current RMS panel Clicking the Read Setup button causes a read of all registers shown in the panel. Clicking the Write Setup button causes writes to the xIRMSOS[23:0] registers.
You can use the Start Digital Signal Processor and Stop Digital Signal Processor buttons to manage the Run[15:0] register and the Read xIRMS registers button, which uses the ZXIA, ZXIB, and ZXIC interrupts at the IRQ1 pin, to read the xIRMS[23:0]registers 500 consecutive times and then compute and display their average. If no interrupt occurs for the time indicated by the timeout (in 3 sec increments), the following message is displayed: No ZXIA, ZXIB or ZXIC interrupt was generated. Verify at least one sinusoidal signal is provided between IAP-IAN, IBP-IBN or ICP-ICN pins. A delay can be introduced (in 10 ms increments) between the time the IRQ1 pin goes low and the moment the xIRMS registers are read. The operation is repeated until the button is clicked again.
Mean Absolute Value Current
When Mean Absolute Value Current is selected on the Front Panel, a new panel is opened (see Figure 19). When the Read xIMAV registers button is clicked, the xIMAV[19:0] registers are read 10 consecutive times, and their average is computed and displayed. After this operation, the button is returned to high automatically. The ADE7878 status is also displayed. 09078-019
Figure 19. Mean Absolute Value Current Panel
Voltage RMS
When RMS Voltage is selected on the Front Panel, the Voltage RMS panel is opened (see Figure 20). This panel is very similar to the Current RMS panel. Clicking the Read Setup button executes a read of the xVRMSOS[23:0] and xVRMS[23:0] registers.
Clicking Write Setup writes the xVRMSOS[23:0] registers into the ADE7878. The Start Digital Signal Processor and Stop Digital Signal Processor buttons manage the Run[15:0] register. When the Read xVRMS registers button is clicked, the xVRMS[23:0] registers are read 500 consecutive times and the average is displayed. The operation is repeated until the button is clicked again. Note that the ZXVA, ZXVB, and ZXVC zero-crossing interrupts are not used in this case because they are disabled when the voltages go below 10% of full scale. This allows rms voltage registers to be read even when the phase voltages are very low.
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09078-020
Figure 20. Voltage RMS Panel
Power Quality
The Power Quality panel is accessible from the Front Panel and is divided into two parts (see Figure 21). The lower part displays registers that manage the power quality measurement functions for the Active Measurement button in the upper part of the panel. The upper part also displays the ADE7878 status and the buttons that manage the measurements.
When the READ CONFIGURATION button is clicked, all power quality registers (MASK1[31:0], STATUS1[31:0], PERIOD[15:0], MMODE[7:0], ISUM[27:0], OVLVL[23:0], OILVL[23:0], PHSTATUS[15:0], IPEAK[31:0], VPEAK[31:0], SAGLVL[23:0], SAGCYC[7:0], ANGLE0[15:0], ANGLE1[15:0], ANGLE2[15:0], COMPMODE[15:0], CHECKSUM[31:0], and PEAKCYC[7:0]) are read, and the ones belonging to the active panel are displayed. Based on the PERIOD[15:0] register, the line frequency is computed and displayed in the lower part of the panel, in Zero Crossing Measurements. Based on the ANGLEx[15:0] registers, cos(ANGLEx) is computed and displayed in the Time Intervals Between Phases panel that is accessible from the Active Measurement Zero Crossing dropdown box (see Figure 21).
When the WRITE CONFIGURATION button is clicked, MMODE[7:0], OVLVL[23:0], OILVL[23:0], SAGLVL[23:0], SAGCYC[7:0], COMPMODE[15:0], and PEAKCYC[7:0] are written into the ADE7878, and CHECKSUM[31:0] is read back and displayed in the CHECKSUM[31:0] box at the top of the upper part of the panel. 09078-021
Figure 21. Power Quality Zero-Crossing Measurements Panel When the WAIT FOR INTERRUPTS button is clicked, the interrupts that you have enabled in the MASK1[31:0] register are monitored. When the IRQ1 pin goes low, the STATUS1[31:0] register is read and its bits are displayed. The ISUM[27:0], PHSTATUS[15:0], IPEAK[31:0], VPEAK[31:0], ANGLE0[15:0], ANGLE1[15:0], and ANGLE2[15:0] registers are also read and displayed. A timeout should be introduced in 3 sec increments to ensure that the program does not wait indefinitely for interrupts. A timer (in 10 ms increments) is provided to allow reading of the registers with a delay from the moment the interrupt is triggered.
The Active Measurement Zero Crossing button gives access to the Zero Crossing, Neutral Current Mismatch, Overvoltage and Overcurrent Measurement, Peak Detection, and Time Intervals Between Phases panels (see Figure 21 through Figure 25). The line frequency is computed using the PERIOD[15:0] register, based on the following formula: ][000,256HzPeriodf= The cosine of the ANGLE0[15:0], ANGLE1[15:0], and ANGLE2[15:0] measurements is computed using the following formula: =000,256×360×)(fANGLExcosANGLExcos
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Figure 22. Neutral Current Mismatch Panel 09078-023
Figure 23. Overvoltage and Overcurrent Measurements Panel 09078-024
Figure 24. Peak Detection Panel 09078-025
Figure 25. Time Intervals Between Phases Panel
Waveform Sampling
The Waveform Sampling panel (see Figure 26) is accessible from the Front Panel and uses the HSDC port to acquire data from the ADE7878 and display it. It can be accessed only if the communication between the ADE7878 and the NXP LPC2368 is through the I2C. See the Activating Serial Communication Between the ADE7878 and the NXP LPC2368 section for details on how to set I2C communication on the ADE7878 evaluation board. 09078-026
Figure 26. Waveform Sampling Panel
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The HSDC transmits data to the NXP LPC2368 at 4 MHz because this is the maximum speed at which the slave SPI of the NXP LPC2368 can receive data. The panel contains some switches that must be set before acquiring data.
• One switch chooses the quantities that are displayed: phase currents and voltages or phase powers. For every set of quantities, only one can be acquired at a time. This choice is made using the Select Waveform button.
• A second switch allows acquired data to be stored in files for further use. This switch is set with the ACQUIRE DATA button.
• The acquisition time should also be set before an acquis-ition is ordered. By default, this time is 150 ms. It is unlimited for phase currents and voltages and for phase powers. The NXP LPC2368 executes in real time three tasks using the ping pong buffer method: continuously receiving data from HSDC, storing the data into its USB memory, and sending the data to the PC. Transmitting seven phase currents and voltages at 4 MHz takes 103.25 μs (which is less than 125 μs); therefore, the HSDC update rate is 8 kHz (HSDC_CFG = 0x0F). Transmitting nine phase powers takes 72 μs (again, less than 125 μs); therefore, the HSDC update rate is also 8 kHz (HSDC_CGF = 0x11).
To start the acquisition, click the ACQUIRE DATA button. The data is displayed on one plot. If you click the Write waveforms to file?/No writing to files switch to enable the writing of waveforms to a file, the program asks for the name and location of the files before storing the waveform.
Checksum Register
The Checksum Register panel is accessible from the Front Panel and gives access to all ADE7878 registers that are used to compute the CHECKSUM[31:0] register (see Figure 27). You can read/write the values of these registers by clicking the Read and Write buttons. The LabView program estimates the value of the CHECKSUM[31:0] register and displays it whenever one of the registers is changed. When the Read button is pressed, the registers are read and the CHECKSUM[31:0] register is read and its values displayed. This allows you to compare the value of the CHECKSUM[31:0] register estimated by LabView with the value read from the ADE7878. The values should always be identical. 09078-027
Figure 27. Checksum Register Panel
All Registers Access
The All Registers Access panel is accessible from the Front Panel and gives read/write access to all ADE7878 registers. Because there are many, the panel can scroll up and down and has multiple read, write, and exit buttons (see Figure 28 and Figure 29). The registers are listed in columns in alphabetical order, starting at the upper left. The panel also allows you to save all control registers into a data file by clicking the Save All Regs into a file button. By clicking the Load All Regs from a file button, you can load all control registers from a data file. Then, by clicking the Write All Regs button, you can load these values into the ADE7878. The order in which the registers are stored into a file is shown in the Control Registers Data File section. 09078-028
Figure 28. Panel Giving Access to All ADE7878 Registers (1)
UG-146 Evaluation Board User Guide
Rev. 0 | Page 16 of 36
09078-029
Figure 29. Panel Giving Access to All ADE7878 Registers (2)
Quick Startup
The Quick Startup panel is accessible from the Front Panel and can be used to rapidly initialize a 3-phase meter (see Figure 30). 09078-030
Figure 30. Panel Used to Quickly Set Up the 3-Phase Meter The meter constant (MC, in impulses/kWh), the nominal voltage (Un, in V rms units), the nominal current (In, in A rms units), and the nominal line frequency (fn, in either 50 Hz or 60 Hz) must be introduced in the panel controls. Then phase voltages and phase currents must be provided through the relative sensors.
Clicking the Begin Computations button starts the program that reads rms voltages and currents and calculates the full-scale voltage and currents used to further initialize the meter. This process takes 7 sec as the program reads the rms voltages 100 times and the rms currents 100 times and then averages them (this is because the PC reads the rms values directly and cannot synchronize the readings with the zero crossings).
The program then computes the full-scale voltages and currents and the constants that are important for setting up the ADE7878: nominal values (n), CFDEN, WTHR1, VARTHR1, VATHR1 and WTHR0, VARTHR0, and VATHR0. At this point, you can overwrite these values. You can also click the Update Registers button to cause the program to do the following:
• Initialize the CFxDEN and xTHR registers
• Enable the CF1 pin to provide a signal proportional to the total active power, the CF2 pin to provide a signal proportional to the total reactive power, and the CF3 pin to provide a signal proportional to the apparent power.
Throughout the program, it is assumed that PGA gains are 1 (for simplicity) and that the Rogowski coil integrators are disabled. You can enter and modify the PGAs and enable the integrators before executing this quick startup if necessary.
At this point, the evaluation board is set up as a 3-phase meter, and calibration can be executed. To store the register initializa-tions, click the Save All Regs into a file button in the All Registers Access panel. After the board is powered down and then powered up again, the registers can be loaded into the ADE7878 by simply loading back the content of the data file. To do this, click the Load All Regs from a file button in the All Registers Access panel.
PSM2 Settings
The PSM2 Settings panel, which is accessible from the Front Panel, gives access to the LPOILVL[7:0] register that is used to access PSM2 low power mode (see Figure 31). You can manipulate its LPOIL[2:0] and LPLINE[4:0] bits. The value shown in the LPOILVL[7:0] register is composed from these bits and then displayed. Note that you cannot write a value into the register by writing a value in the LPOILVL[7:0] register box.
Evaluation Board User Guide UG-146
Rev. 0 | Page 17 of 36
09078-031
Figure 31. PSM2 Settings Panel
PSM1 MODE
Enter PSM1 Mode
When Enter PSM1 mode is selected on the Front Panel, the microcontroller manipulates the PM0 and PM1 pins of the ADE7878 to switch the ADE7878 into PSM1 reduced power mode. Then, the submenu allows access only to the Mean Absolute Value Current function because this is the only ADE7878 functionality available in this reduced power mode (see Figure 32). 09078-032
Figure 32. Front Panel After the ADE7878 Enters PSM1 Mode
Mean Absolute Value Current in PSM1 Mode
The Mean Absolute Value Current panel, which is accessible from the Front Panel when Enter PSM1 mode is selected, is very similar to the panel accessible in PSM0 mode (see the Mean Absolute Value Current section for details). The only difference is that ADE7878 status does not show the CHECKSUM[31:0] register because it is not available in PSM1 mode (see Figure 33) 09078-033
Figure 33. Mean Absolute Value Currents Panel in PSM1 Mode
PSM2 MODE
Enter PSM2 Mode
When Enter PSM2 mode is selected on the Front Panel, the microcontroller manipulates the PM0 and PM1 pins of the ADE7878 to switch the ADE7878 into PSM2 low power mode. Then the submenu allows access only to the Phase Current Monitoring function because this is the only ADE7878 functionality available in this low power mode. 09078-034 Figure 34. Front Panel After the ADE7878 Enters PSM2 Mode
UG-146 Evaluation Board User Guide
Rev. 0 | Page 18 of 36
Phase Current Monitoring
The Phase Current Monitoring panel is accessible from the Front Panel when Enter PSM2 mode is selected; it allows you to display the state of the IRQ0and IRQ1 pins because, in PSM2 low power mode, the ADE7878 compares the phase currents against a threshold determined by the LPOILVL[7:0] register (see Figure 35). Clicking the READ STATUS OF IRQ0 AND IRQ1 PINS button reads the status of these pins and displays and interprets the status.
This operation is managed by the LPOILVL[7:0] register and can be modified only in PSM0 mode. The panel offers this option by switching the ADE7878 into PSM0 mode and then back to PSM2 mode when one of the READ LPOILVL/WRITE LPOILVL buttons is clicked. To avoid toggling both the PM0 and PM1 pins at the same time during this switch, the ADE7878 is set to PSM3 when changing modes.
09078-035
Figure 35. Panel Managing Current Monitoring in PSM2 Mode
PSM3 MODE
Enter PSM3 Mode
In PSM3 sleep mode, most of the internal circuits of the ADE7878 are turned off. Therefore, no submenu is activated while in this mode. You can click the Enter PSM0 mode, Enter PSM1 mode, or Enter PSM2 mode button to set the ADE7878 to one of these power modes.
Evaluation Board User Guide UG-146
Rev. 0 | Page 19 of 36
MANAGING THE COMMUNICATION PROTOCOL BETWEEN THE MICROCONTROLLER AND
THE ADE7878
In this section, the protocol commands are listed that have been
implemented to manage the ADE7878 from the PC using the
microcontroller. The microcontroller is a pure slave during the communication
process. It receives a command from the PC, executes the
command, and sends an answer to the PC. The PC should wait for the answer before sending a new command to the micro-
controller.
Table 3. Echo Command—Message from the PC to the Micro-
controller
Byte Description
0 A = 0x41
1 N = number of bytes transmitted after this byte
2 Data Byte N − 1 (MSB)
3 Data Byte N − 2 4 Data Byte N − 3 … …
N Data Byte 1 N + 1 Data Byte 0 (LSB)
Table 4. Echo Command—Answer from the Microcontroller to
the PC
Byte Description
0 R = 0x52
1 A = 0x41
2 N = number of bytes transmitted after this byte
3 Data byte N − 1 (MSB)
4 Data byte N − 2
… …
N + 1 Data Byte 1 N + 2 Data Byte 0 (LB)
Table 5. Power Mode Select—Message from the PC to the
Microcontroller
Byte Description
0 B = 0x42, change PSM mode 1 N = 1
2 Data Byte 0: 0x00 = PSM0
0x01 = PSM1
0x02 = PSM2
0x03 = PSM3
Table 6. Power Mode Select—Answer from the Microcon-
troller to the PC
Byte Description
0 R = 0x52
1 ~ = 0x7E, to acknowledge that the operation was
successful
Table 7. Reset—Message from the PC to the Microcontroller
Byte Description
0 C = 0x43, toggle the RESET pin and keep it low for at least 10 ms
1 N = 1
2 Data Byte 0: this byte can have any value
Table 8. Reset—Answer from the Microcontroller to the PC
Byte Description
0 R = 0x52
1 ~ = 0x7E, to acknowledge that the operation was
successful
Table 9. I2C/SPI Select (Configure Communication)—
Message from the PC to the Microcontroller
Byte Description
0 D = 0x44, select I2C and SPI and initialize them; then set
CONFIG2[7:0] = 0x2 to lock in the port choice. When I2C
is selected, also enable SSP0 of the LPC2368 (used for
HSDC). 1 N = 1.
2 Data Byte 0: 0x00 = I2C, 0x01 = SPI.
Table 10. I2C/SPI Select (Configure Communication)—
Answer from the Microcontroller to the PC
Byte Description
0 R = 0x52
1 ~ = 0x7E, to acknowledge that the operation was
successful
Table 11. Data Write—Message from the PC to the Micro-
controller
Byte Description
0 E = 0x45.
1 N = number of bytes transmitted after this byte. N can
be 1 + 2, 2 + 2, 4 + 2, or 6 + 2.
2 MSB of the address. 3 LSB of the address. 4 Data Byte N − 3 (MSN). 5 Data Byte N − 4. 6 Data Byte N − 5. … …
N + 2 Data Byte 1.
N + 3 Data Byte 0 (LSB).
Table 12. Data Write—Answer from the Microcontroller to
the PC
Byte Description
0 R = 0x52
1 ~ = 0x7E, to acknowledge that the operation was
successful
UG-146 Evaluation Board User Guide
Rev. 0 | Page 20 of 36
Table 13. Data Read—Message from the PC to the Micro-
controller
Byte Description
0 F = 0x46.
1 N = number of bytes transmitted after this byte; N = 3.
2 MSB of the address. 3 LSB of the address. 4 M = number of bytes to be read from the address above.
M can be 1, 2, 4, or 6.
Table 14. Data Read—Answer from the Microcontroller to
the PC
Byte Description
0 R = 0x52.
1 MSB of the address. 2 LSB of the address. 3 Byte 5, Byte 3, Byte 1, or Byte 0 (MSB) read at the location
indicated by the address. The location may contain 6, 4,
2, or 1 byte. The content is transmitted MSB first.
4 Byte 4, Byte 2, or Byte 0. 5 Byte 3, Byte 1. 6 Byte 2, Byte 0. 7 Byte 1. 8 Byte 0. Table 15. Interrupt Setup—Message from the PC to the
Microcontroller
Byte Description
0 J = 0x4A. 1 N = 8, number of bytes transmitted after this byte.
2 MSB of the MASK1[31:0] or MASK0[31:0] register.
3 LSB of the MASK1[31:0] or MASK0[31:0] register.
4 Byte 3 of the desired value of the MASK0[31:0] or MASK1[31:0] register.
5 Byte 2. 6 Byte 1. 7 Byte 0. 8 Time out byte: time the MCU must wait for the interrupt
to be triggered. It is measured in 3 sec increments. Time out byte (TOB) = 0 means that timeout is disabled. 9 IRQ timer: time the MCU leaves the IRQx pin low before writing back to clear the interrupt flag. It is measured in
10 ms increments.
Timer = 0 means that timeout is disabled. Table 16. Interrupt Setup—Message from the Microcon-
troller to the PC
Byte Description
0 R = 0x52.
1 Byte 3 of the STATUS0[31:0] or STATUS1[31:0] register.
If the program waited for TOB × 3 sec and the interrupt
was not triggered, then Byte 3 = Byte 2 = Byte 1 = Byte 0
= 0xFF. 2 Byte 2 of the STATUS0[31:0] or STATUS1[31:0] register.
3 Byte 1 of the STATUS0[31:0] or STATUS1[31:0] register.
4 Byte 0 of the STATUS0[31:0] or STATUS1[31:0] register.
The microcontroller executes the following operations once the
interrupt setup command is received: 1. Reads the STATUS0[31:0] or STATUS1[31:0] register
(depending on the address received from the PC) and, if it shows an interrupt already triggered (one of its bits is equal
to 1), it erases the interrupt by writing it back. 2. Writes to the MASK0[31:0] or MASK1[31:0] register with the value received from the PC. 3. Waits for the interrupt to be triggered. If the wait is more
than the timeout specified in the command, 0xFFFFFFFF
is sent back. 4. If the interrupt is triggered, the STATUS0[31:0] or STATUS1[31:0] register is read and then written back to clear it. The value read at this point is the value sent back
to the PC so that you can see the source of the interrupts. 5. Sends back the answer. Table 17. Interrupt Pins Status—Message from the PC to the
Microcontroller
Byte Description
0 H = 0x48.
1 N = 1, number of bytes transmitted after this byte.
2 Any byte. This value is not used by the program but it is
used in the communication because N must not be equal
to 0.
Table 18. Interrupt Pins Status—Answer from the Micro-
controller to the PC
Byte Description
0 R = 0x52.
1 A number representing the status of the IRQ0 and IRQ1
pins.
0: IRQ0 = low, IRQ1 = low 1: IRQ0 = low, IRQ1 = high.
2: IRQ0 = high, IRQ1 = low. 3: IRQ0 = high, IRQ1 = high.
The reason for the IRQ0 and IRQ1 order is that on the
microcontroller IO port, IRQ0= P0.1 and IRQ1 = P0.0.
Evaluation Board User Guide UG-146
Rev. 0 | Page 21 of 36
ACQUIRING HSDC DATA CONTINUOUSLY
This function acquires data from the HSDC continuously for a defined time period and for up to two variables. The microcon-troller sends data in packages of 4 kB.
Table 19 describes the protocol when two instantaneous phase currents or voltages are acquired.
Table 19. Acquire HSDC Data Continuously—Message from the PC to the Microcontroller If Phase Currents and Voltages Are Acquired
Byte
Description
0
G = 0x47.
1
N = number of bytes transmitted after this byte. N = 32.
2
0: corresponds to Byte 3 of IA. Because this byte is only a sign extension of Byte 2, it is not sent back by the microcontroller.
3
Increment_IA_Byte2. If IA is to be acquired, Byte 3, Byte 4, and Byte 5 are 1. Otherwise, they are 0.
4
Increment_IA_Byte1.
5
Increment_IA_Byte2.
6
0.
7
Increment_VA_Byte2. If VA is to be acquired, Byte 7, Byte 8, and Byte 9 are 1. Otherwise, they are 0.
8
Increment_VA_Byte1.
9
Increment_VA_Byte0.
10
0.
11
Increment_IB_Byte2. If IB is to be acquired, Byte 11, Byte 12, and Byte 13 are 1. Otherwise, they are 0.
12
Increment_IB_Byte1.
13
Increment_IB_Byte0.
14
0.
15
Increment_VB_Byte2. If VB is to be acquired, Byte 15, Byte 16, and Byte 17 are 1. Otherwise, they are 0.
16
Increment_VB_Byte1.
17
Increment_VB_Byte0.
18
0.
19
Increment_IC_Byte2. If IC is to be acquired, Byte 19, Byte 20, and Byte 21 are 1. Otherwise, they are 0.
20
Increment_IC_Byte1.
21
Increment_IC_Byte0.
22
0.
23
Increment_VC_Byte2. If VC is to be acquired, Byte 23, Byte 24, and Byte 25 are 1. Otherwise, they are 0.
24
Increment_VC_Byte1.
25
Increment_VC_Byte0.
26
0.
27
Increment_IN_Byte2. If IN is to be acquired, Byte 27, Byte 28, and Byte 29 are 1. Otherwise, they are 0.
28
Increment_IN_Byte1.
29
Increment_IN_Byte0.
30
Byte 1 of M. M is a 16-bit number. The number of 32-bit samples acquired by the microcontroller is (2 × M + 1) × 67 per channel.
31
Byte 0 of M.
If two of the phase powers are to be acquired, the protocol changes (see Table 20).
Table 20. Acquire HSDC Data Continuously—Message from the PC to the Microcontroller If Phase Powers Are Acquired
Byte
Description
0
G = 0x47
1
N = number of bytes transmitted after this byte. N = 38.
2
0: corresponds to Byte 3 of AVA. Because this byte is only a sign extension of Byte 2, it is not sent back by the microcontroller.
3
Increment_AVA_Byte2. If AVA is to be acquired, Byte 3, Byte 4, and Byte 5 are 1. Otherwise, they are 0.
4
Increment_AVA_Byte1.
5
Increment_AVA_Byte2.
6
0.
7
Increment_BVA_Byte2. If BVA is to be acquired, Byte 7, Byte 8, and Byte 9 are 1. Otherwise, they are 0.
8
Increment_BVA_Byte1.
9
Increment_BVA_Byte0.
10
0.
11
Increment_CVA_Byte2. If CVA is to be acquired, Byte 11, Byte 12, and Byte 13 are 1. Otherwise, they are 0.
12
Increment_CVA_Byte1.
13
Increment_CVA_Byte0.
14
0.
15
Increment_AWATT_Byte2. If AWATT is to be acquired, Byte 15, Byte 16, and Byte 17 are 1. Otherwise, they are 0.
16
Increment_AWATT_Byte1.
17
Increment_AWATT_Byte0.
18
0.
19
Increment_BWATT_Byte2. If BWATT is to be acquired, then Byte 19, Byte 20, and Byte 21 are 1. Otherwise, they are 0.
20
Increment_BWATT_Byte1.
21
Increment_BWATT_Byte0.
22
0.
23
Increment_CWATT_Byte2. If CWATT is to be acquired, Byte 23, Byte 24, and Byte 25 are 1. Otherwise, they are 0.
24
Increment_CWATT_Byte1.
25
Increment_CWATT_Byte0.
26
0.
27
Increment_AVAR_Byte2. If AVAR is to be acquired, Byte 27, Byte 28, and Byte 29 are 1. Otherwise, they are 0.
28
Increment_AVAR_Byte1.
29
Increment_AVAR_Byte0.
30
0.
31
Increment_BVAR_Byte2. If BVAR is to be acquired, then Byte 31, Byte 32, and Byte 33 are 1. Otherwise, they are 0.
32
Increment_BVAR_Byte1.
33
Increment_BVAR_Byte0.
34
0.
35
Increment_CVAR_Byte2. If CVAR is to be acquired, Byte 35, Byte 36, and Byte 37 are 1. Otherwise, they are 0.
UG-146 Evaluation Board User Guide
Rev. 0 | Page 22 of 36
Byte
Description
36
Increment_CVAR_Byte1.
37
Increment_CVAR_Byte0.
38
Byte 1 of M. M is a 16-bit number. The number of 32-bit samples acquired by the microcontroller is (2 × M + 1) × 67 per channel.
39
Byte 0 of M.
After receiving the command, the microcontroller enables the HSDC port and acquires 67 × 7 × 4 = 1876 bytes into BUFFER0. As soon as BUFFER0 is filled, data is acquired in BUFFER1 (equal in size to BUFFER0), while 2 × 3 × 67 = 402 bytes (134 24-bit words) from BUFFER0 are transmitted to the PC. As soon as BUFFER1 is filled, data is acquired into BUFFER0 while 402 bytes from BUFFER1 are transmitted to the PC. Only the less significant 24 bits of every 32-bit instantaneous value are sent to the PC to decrease the size of the buffer sent to the PC. The most significant eight bits are only an extension of a 24-bit signed word; therefore, no information is lost. The protocol used by the microcontroller to send data to the PC is shown in Table 21.
Table 21. Acquire HSDC Data Continuously—Answer from the Microcontroller to the PC
Byte
Description
0
R = 0x52
1
Byte 2 (MSB) of Word 1
2
Byte 1 of Word 1
3
Byte 0 (LSB) of Word 1
4
Byte 2 (MSB) of Word 2
5
Byte 1 (MSB) of Word 2
…
…
402
Byte 0 (LSB) of Word 134
STARTING THE ADE7878 DSP
This function orders the microcontroller to start the DSP. The microcontroller writes to the run register with 0x1. Table 22. Start ADE7878 DSP—Message from the PC to the Microcontroller
Byte
Description
0
N = 0x4E
1
N = number of bytes transmitted after this byte; N = 1
2
Any byte
Table 23. Start ADE7878 DSP—Answer from the Micro-controller to the PC
Byte
Description
0
R = 0x52
1
~ = 0x7E, to acknowledge that the operation was successful
STOPPING THE ADE7878 DSP
This function orders the microcontroller to stop the DSP. The microcontroller writes to the run register with 0x0. Table 24. Stop ADE7878 DSP—Message from the PC to the Microcontroller
Byte
Description
0
O = 0x4F
1
N = number of bytes transmitted after this byte; N = 1
2
Any byte
Table 25. Stop ADE7878 DSP—Answer from the Micro-controller to the PC
Byte
Description
0
R = 0x52
1
~ = 0x7E to acknowledge that the operation was successful
Evaluation Board User Guide UG-146
Rev. 0 | Page 23 of 36
UPGRADING MICROCONTROLLER FIRMWARE
Although the evaluation board is supplied with the microcontroller firmware already installed, the ADE7878 evaluation software CD provides the NXP LPC2368 microcontroller project developed under the IAR embedded workbench environment for ARM. Users in possession of this tool can modify the project at will and can download it using an IAR J-link debugger. As an alternative, the executable can be downloaded using a program called Flash Magic, available on the evaluation software CD or at the following website: http://www.flashmagictool.com/. Flash Magic uses the PC COM port to download the micro-controller firmware. The procedure for using Flash Magic is as follows:
1. Plug a serial cable into connector P15 of the ADE7878 evaluation board and into a PC COM port. As an alternative, use the ADE8052Z-DWDL1 ADE downloader from Analog Devices, Inc., together with a USB cable.
2. Launch the Device Manager under Windows XP by writing devmgmt.msc into the Start/Run box. This helps to identify which COM port is used by the serial cable.
3. Plug the USB2UART board into the P15 connector of the ADE7878 evaluation board with the VDD pin of the USB2UART aligned at Pin 1 of P15.
4. Connect Jumper JP8. The P2.10/EINT0 pin of the microcontroller is now connected to ground.
5. Supply the board with two 3.3 V supplies at the P10 and P12 connectors.
6. Press and release the reset button, S2, on the ADE7878 evaluation board.
7. Launch Flash Magic and do the following:
a. Select a COM port (COMx as seen in the Device Manager).
b. Set the baud rate to 115,200.
c. Select the NXP LPC2368 device.
d. Set the interface to none (ISP).
e. Set the DOscillator frequency (MHz) to 12.0.
f. Select Erase all Flash + Code Rd Block.
g. Choose ADE7878_Eval_Board.hex from the \Debug\Exe project folder.
h. Select Verify after programming.
The Flash Magic settings are shown in Figure 36. 09078-036
Figure 36. Flash Magic Settings
8. Click Start to begin the download process.
9. After the process finishes, extract the JP8 jumper.
10. Reset the ADE7878 evaluation board by pressing and releasing the S2 reset button.
At this point, the program should be functional, and a USB cable can be connected to the board. When the PC recognizes the evaluation board and asks for a driver, point it to the project \VirCOM_Driver_XP folder. The ADE7878_eval_board_ vircomport.inf file is the driver.
CONTROL REGISTERS DATA FILE
Table 26 shows the order in which the control registers of the ADE7878 are stored into a data file when you click the Save All Regs into a file button in the All Registers Access panel.
UG-146 Evaluation Board User Guide
Rev. 0 | Page 24 of 36
Table 26. Control Register Data File Content
Line Number
Register
1
AIGAIN
2
AVGAIN
3
BIGAIN
4
BVGAIN
5
CIGAIN
6
CVGAIN
7
NIGAIN
8
AIRMSOS
9
AVRMSOS
10
BIRMSOS
11
BVRMSOS
12
CIRMSOS
13
CVRMSOS
14
NIRMSOS
15
AVAGAIN
16
BVAGAIN
17
CVAGAIN
18
AWGAIN
19
AWATTOS
20
BWGAIN
21
BWATTOS
22
CWGAIN
23
CWATTOS
24
AVARGAIN
25
AVAROS
26
BVARGAIN
27
BVAROS
28
CVARGAIN
29
CVAROS
30
AFWGAIN
31
AFWATTOS
32
BFWGAIN
33
BFWATTOS
34
CFWGAIN
35
CFWATTOS
36
AFVARGAIN
37
AFVAROS
38
BFVARGAIN
39
BFVAROS
40
CFVARGAIN
41
CFVAROS
Line Number
Register
42
VATHR1
43
VATHR0
44
WTHR1
45
WTHR0
46
VARTHR1
47
VARTHR0
48
VANOLOAD
49
APNOLOAD
50
VARNOLOAD
51
VLEVEL
52
DICOEFF
53
HPFDIS
54
ISUMLVL
55
RUN
56
OILVL
57
OVLVL
58
SAGLVL
59
MASK0
60
MASK1
61
VNOM
62
LINECYC
63
ZXTOUT
64
COMPMODE
65
Gain
66
CFMODE
67
CF1DEN
68
CF2DEN
69
CF3DEN
70
APHCAL
71
BPHCAL
72
CPHCAL
73
CONFIG
74
MMODE
75
ACCMODE
76
LCYCMODE
77
PEAKCYC
78
SAGCYC
79
CFCYC
80
HSDC_CFG
81
LPOILVL
82
CONFIG2
Evaluation Board User Guide UG-146
Rev. 0 | Page 25 of 36
EVALUATION BOARD SCHEMATICS AND LAYOUT
SCHEMATIC
09078-037NOTE:MOUNT JP? DIRECTLY BELOWPAD METAL. CONNECT TO PADWITH MULTIPLE VIAS.REPEAT VIA GRID TO AGND PLANEEXTRA GROUND TP FOR PROBINGOUTPUT LED CIRCUITIRQ1BCF1CF2IRQ0BCF3DEVICE INTERFACE HEADERREFERENCE DECOUPLING AND EXTERNAL REFRESONANT CIRCUIT. THIS OPTION SHOULD BE PLACED ASXTAL CKTBY DEFAULT SELECT OPTION A
TO COMPLETE PARALLELCLOSE TO DEVICE AS POSSIBLE.C27C26C25C6C4NPC41NPC5NPC321C38C43C42C40C7C2NPC8NPC1NPC44ACCR5ACCR4ACCR3ACCR2ACCR1RSBR43R42R41R40R3921E8NR69R84R85R70R68231JP12R35R361TP293421S121JP321JP421JP521JP621JP101TP49231A11TP511TP501TP341TP361TP381TP371TP391TP351TP331TP321TP311TP301TP281TP271TP261TP251TP241TP231TP2221JP221P10R371TP151TP141TP139876543231303292827262524232221202191817161514131211101P111826192223393641732PAD3837322915161314912785628273534332425U1213Q5213Q2213Q4213Q3213Q121JP121P9R381TP921P521JP7NR2521JP8N54321CLKIN21Y1231JP11DGND_DCLKOUTIRQ0B20PF20PF3PIN_SOLDER_JUMPERBLKCLKINAMP227699-2BLK1.0UFIBP10KCF2CMD28-21VGCTR8T1BLKVDD_FBLKVDD_F10UFVDD0.1UF0.1UF0.1UFBLKBLKBLKVDD2VDD0BLKJPR04021500 OHMSVNBERG69157-1021KBERG69157-102BLKBLKREFEXT_CLKINBLKBLKBLKBLKCF1SSB/HSAMOSI/SDACF3/HSCLKIRQ0B16.384MHZIRQ1BPM0PM1RESETBCLKOUTEXT_CLKINSAMTSW-1-30-08-GDSCLK/SCLCF2MISO/HSDFDV302P10KCF3/HSCLKFDV302PFDV302P10KVDD2CF1JPR0402JPR0402BLKWEILAND25.161.0253VDD2DVDDAVDD3PIN_SOLDER_JUMPERBLKBLKB3S1000BLKBLKBLKBLKPAD_CNVDD_FICNPM0PM1VCPVBPVAPCLKININPINNVNCF2IRQ0BBERG69157-102BLKJPR0402ADR280ARTZ10K499499499ICPIANIAPRESETBFDV302P4994992VDD2FDV302PIRQ1B10KCMD28-21VGCTR8T1CMD28-21VGCTR8T1CMD28-21VGCTR8T1CMD28-21VGCTR8T1XREF10UFVDD_F10UFVDD_F10KJPR04024.7UFMOSI/SDAIBNADE7858CPZSCLK/SCLPAD_CNBLKSSB/HSAMISO/HSD0.1UF4.7UFCF3/HSCLKCF1IRQ1BDVDDCLKOUTREFAVDDBERG69157-102BLK0.22UF0.22UF10KVDD20.1UFVDDBLK4.7UFDGND_DWEILAND25.161.025310KWEILAND25.161.0253VN_IN22NFAGNDDGNDBCOMADGNDDGNDAGNDAGNDAGNDDGNDAGNDAGNDAGNDV-V+VODGNDSCLK_SCLSS_N_HSAMISO_HSDMOSI_SDAIRQ1_N_SBSDAIRQ0_N_SBSCLRESET_NCF3_HSCLKCF2VNINNINPCF1CLKOUTCLKINVDDVAPVBPVCPREFIN_OUTDVDDPM1PM0PADAVDDAGNDDGNDICNICPIBNIBPIANIAPDGNDGDSDGNDGDSDGNDGDSDGNDGDSDGNDGDSDGNDAGNDAGNDAGNDAGNDAGNDAGNDBCOMA Figure 37.
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INPUT ANTI-ALIAS AND DEVICE CONNECTIONC12C11C20C19C24C23C16C15C22C14C13C18C17C10C9C2121E2N21E1N21E2C21E1C21E1A21E2A21E1B21E2B21JP2N21JP1N21JP2C21JP1C21JP2B21JP1B21JP1A21JP2A21JP6N21JP4N21JP5N21JP3N21JP6C21JP5C21JP4C21JP3C21JP6B21JP4B21JP5B21JP3B21JP6A21JP4A21JP5A21JP3A21P421P321P121P21TP7R71TP8R23R24R15R16R81TP5R51TP6R21R22R13R14R6R4R3R12R11R20R191TP41TP31TP21TP1R17R18R2R1R10R9TBD12061500 OHMSBERG69157-102100TBD1206INN_INWEILAND25.161.0253TBD1206BERG69157-102BERG69157-102BERG69157-102WEILAND25.161.0253IBP_INIBN_INBERG69157-102BERG69157-102100TBD12061001K1KBERG69157-102BLKBERG69157-102BERG69157-102BERG69157-1021001KBLKBERG69157-102IBNIAPBERG69157-102BLK1KBLK100TBD12061KBLKBERG69157-102BERG69157-102TBD1206100INPINN1500 OHMS1500 OHMSTBD12061500 OHMSIAP_INICP100BERG69157-102IBPBERG69157-102TBD1206BERG69157-102ICN100BERG69157-102BLK1KBERG69157-1021500 OHMSIAN_IN1500 OHMSICP_INBLK1KBERG69157-1021500 OHMSICN_INWEILAND25.161.0253BERG69157-102BERG69157-102WEILAND25.161.02531500 OHMS1KBLKIAN22NF22NF22NF22NF22NF22NF22NF22NFBERG69157-102BERG69157-102INP_IN22NF22NF22NF22NF22NF22NF22NF22NFAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGND09078-043 Figure 38.
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PHASE A VOLTAGEPHASE C VOLTAGEPHASE B VOLTAGEC34C33C32R26R28R2721E8C21E8B21E8A1TP10231JP9C21P621JP8CR3121JP7CR3421P721JP8BR3021JP7BR331TP11231JP9B21JP8A1TP1221JP7A21P8231JP9AR32R2922NF3PIN_SOLDER_JUMPERBERG69157-1021K1500 OHMSWEILAND25.161.0253WEILAND25.161.0253BERG69157-1021KBLK3PIN_SOLDER_JUMPERVBP1500 OHMSVCP_INVBP_INVN100KBERG69157-1021500 OHMS1KBERG69157-102VNBLK100KBERG69157-1021M1MWEILAND25.161.02531M3PIN_SOLDER_JUMPER100KBERG69157-102VCPVNBLKVAPVAP_IN22NF22NFBCOMAAGNDAGNDAGNDAGNDAGNDAGNDBCOMAAGNDAGNDAGNDBCOMA09078-044 Figure 39.
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BYPASSING CONTROLLER(OPTIONAL; CUSTOMER SUPPLIED)TP FOR EVAL PROBE - DISTRIBUTE AROUND ISOLATED CIRCUITSNCD-D+GNDVBUS(5V)USB IFMRESETMCU CIRCUITUARTSHIELD D+, D-, VREF_MCU WITH GNDFROM CONN TO MCUISOLATED PSU CONNECTIONSP2_11P2_12PM0_CTRLP1_29P1_28P1_27P1_19CF3_HSCLK_ISOP2_9P2_8P2_7P2_6PM1_CTRLMCU_XT2P1_15SSB_ISOCF2_ISOP4_29IRQ1B_ISOP1_26P1_25P1_0P1_4P1_8MCU_XT1TMSP1_22P0_24P0_26MOSI_ISOGNDGNDGNDAMP227699-2CF1_ISOCF2_ISOAMP227699-2AMP227699-2CF3_HSCLK_ISOP0_20SML-LXT0805GW-TRBLK680CF3_HSCLK_ISOIRQ0B_ISOP2_1310KRTCK0.1UFWEILAND25.161.0253MCU_VDD_ISO10KBERG69157-102P2_2SAMTSW-1-30-08-GDRXDTXD10KBLKP1_31MCU_RSTSAMTECTSW10608GS4PINMCU_VDD10K27BLKMCU_VDD10UF0.1UF1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF1.5KP1_23MCU_VDDMCU_VDD10KLPC2368FBD100P0_22MCU_VDDD+D-D-_MCUD+_MCUVBUS274-1734376-8RSTOUT_NRTCX2P1_1USB_UPP4_28P3_26P3_25D+_MCUSDA_ISOIRQ_OUT_EN_ISOIRQ_IN_ENMISO_ISOSCLK_ISORESB_CTRLPM0_CTRLIRQ1B_ISOPM1_CTRLSBENB_ISOSSB_ISOTCLKTRST_NTDI10K10KP0_21P0_19P0_5D-_MCURXDTXDWPP0_4P0_9BLKBLKBLKBLKBLKBLKBLKBLKBLKBLKVBUSP2_1P2_0P2_3P2_5HSDATA_ISOMCU_XT120PFMCU_XT220PF12.000MHZMCU_RSTMCU_VDDB3S100010KP1_9P1_17P1_14P1_10P1_16MCU_VDDSAMTECTSW11008GDTMS10K10KTDITCLKRTCKTDOMCU_RST10KTDOSCL_ISOTRST_NHSA_ISOBLKBLKBLKP2_4IRQ0B_ISOMCU_RSTRESB_CTRLHSA_ISOMOSI_ISOSDA_ISOMISO_HSD_ISOSCLK_ISOSCL_ISOCF1_ISOR79R80R81TP461TP421TP431TP411P151234R82P1212C78PNC79TP161TP171TP181CF312345CF212345CF112345C72U8464849626361605947585756987625242998309981807978777695908988878632339434353637383940434445212093929175535251507473706968676665642726828517141001618521341928547196134284101215314155728397112223C75C73C76C77C83C84C80C81C82R78P131101112131415161718192203456789R44R45R75R73R72R71R83TP521TP441TP541TP451TP551TP531TP481TP471TP401S21243R74C74Y212C70C71CR6CAR77P14123456R76JP712P381101112131415161718192202122232425262728293303132456789P2_10TRST_NTCKP1_18_USB_UP_LED_PWM1_1VBATVREFVDDAVDD_DCDC_3V3_3VDD_DCDC_3V3_2VDD_DCDC_3V3_1VDD_3V3_4VDD_3V3_3VDD_3V3_2VDD_3V3_1VSSAVSSP1_0_ENET_TXD0P2_12_EINT2_MCIDAT2_I2STX_WSP2_11_EINT1_MCIDAT1_I2STX_CLKP2_10_EINT0P2_9_USB_CONNECT_RXD2_EXTIN0P2_8_TD2_TXD2_TRACEPKT3P2_7_RD2_RTS1_TRACEPKT2P2_6_PCAP1_0_RI1_TRACEPKT1P2_5_PWM1_6_DTR1_TRACEPKT0P2_4_PWM1_5_DSR1_TRACESYNCP2_3_PWM1_4_DCD1_PIPESTAT2P2_2_PWM1_3_CTS1_PIPESTAT1P2_1_PWM1_2_RXD1_PIPESTAT0P2_0_PWM1_1_TXD1_TRACECLKP1_31_SCK1_AD0_5P1_30_VBUS_AD0_4P1_29_PCAP1_1_MAT0_1P1_28_PCAP1_0_MAT0_0P1_27_CAP0_1P1_26_PWM1_6_CAP0_0P1_25_MAT1_1P1_24_PWM1_5_MOSI0P1_23_PWM1_4_MISO0P1_22_MAT1_0P1_21_PWM1_3_SSEL0P1_20_PWM1_2_SCK0P1_19_CAP1_1P1_17_ENET_MDIOP1_16_ENET_MDCP1_15_ENET_REF_CLKP1_14_ENET_RX_ERP1_10_ENET_RXD1P1_9_ENET_RXD0P1_8_ENET_CRSP1_4_ENET_TX_ENP1_1_ENET_TXD1RTCX2XTAL2RSTOUT_NTDORTCKP2_13_EINT3_MCIDAT3_I2STX_SDAP4_29_MAT2_1_RXD3P4_28_MAT2_0_TXD3P3_26_MAT0_1_PWM1_3P3_25_MAT0_0_PWM1_2P0_30_USB_DNP0_29_USB_DPP0_28_SCL0P0_27_SDA0P0_26_AD0_3_AOUT_RXD3P0_25_AD0_2_I2SRX_SDA_TXD3P0_24_AD0_1_I2SRX_WS_CAP3_1P0_23_AD0_0_I2SRX_CLK_CAP3_0P0_22_RTS1_MCIDAT0_TD1P0_21_RI1_MCIPWR_RD1P0_20_DTR1_MCICMD_SCL1P0_19_DSR1_MCICLK_SDA1P0_18_DCD1_MOSI0_MOSIP0_17_CTS1_MISO0_MISOP0_16_RXD1_SSEL0_SSELP0_15_TXD1_SCK0_SCKP0_11_RXD2_SCL2_MAT3_1P0_10_TXD2_SDA2_MAT3_0P0_9_I2STX_SDA_MOSI1_MAT2_3P0_8_I2STX_WS_MISO1_MAT2_2P0_7_I2STX_CLK_SCK1_MAT2_1P0_6_I2SRX_SDA_SSEL1_MAT2_0P0_5_I2SRX_WS_TD2_CAP2_1P0_4_I2SRX_CLK_RD2_CAP2_0P0_3_RXD0P0_2_TXD0P0_1_TD1_RXD3_SCL1P0_0_RD1_TXD3_SDA1RTCX1XTAL1RESET_NTMSTDI09078-038 Figure 40.
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<- DUTISOLATION CIRCUITI2C/HSDC CONFIGSPI CONFIGSPI CONFIGI2C/HSDC CONFIGMCU ->0SDA_ISOSDA_ISO0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UFSB_ENBSCL_ISOSCLSDASCLKSSBMOSISCLK_ISOMOSI_ISOSSB_ISOIRQ_OUT_ENMISO_HSD_ISOCF3_HSCLK_ISOHSA_ISOVE2_U6MISO/HSDCF3/HSCLKHSACTIVEIRQ_OUT_EN_ISOIRQ1BWP_UXIRQ0BIRQ1BCF2IRQ_IN_ENSBENB_ISOCF1_ISORESETBPM0PM1RESB_CTRLPM1_CTRLCF1ADUM1401BRWZ10KVE2_U310KADUM1401BRWZHSDATA_ISOSCLK/SCLSDAVDD2MCU_VDDSCLIRQ1B_ISOIRQ1B_ISOIRQ0B_ISO10KVE2_U610KADUM1401BRWZ10KHSACTIVESSB/HSASCLSSBSCLK00MISO_ISOMISO_HSD_ISO00SCL_ISO10K10KADUM1401BRWZ10K10K10KADUM1401BRWZIRQ_IN_ENCF2_ISOIRQ0B_ISO10K10KPM0_CTRLVE2_U3WPIRQ0B0.1UF10KIRQ_OUT_EN0.1UFADUM1250ARZMOSI/SDA0SDADNIDNIDNIDNIMOSI010K0A245362718U428915116710345111413126U328915116710345111413126U628915116710345111413126R48R49R51R55R54JP35JP33JP37JP3612JP3412JP3812JP3212JP31C58C59R58BR58AR59BR59AC56C57U728915116710345111413126R57R53U528915116710345111413126R50R46R47C55C54C53C52C51C50C49C48GND2VDD2VOAVOBVICVIDVE2GND1VE1VODVOCVIBVIAVDD1GND2VDD2VOAVOBVICVIDVE2GND1VE1VODVOCVIBVIAVDD1GND2VDD2VOAVOBVICVIDVE2GND1VE1VODVOCVIBVIAVDD1DGNDGNDSCL2SCL1SDA2SDA1VDD1VDD2GND1GND2GND2VDD2VOAVOBVICVIDVE2GND1VE1VODVOCVIBVIAVDD1GND2VDD2VOAVOBVICVIDVE2GND1VE1VODVOCVIBVIAVDD109078-045 Figure 41.
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09078-039LEFT MOST PINS SHOULD BE FURTHEST FROM DUT26ALIGN PORTS AS DRAWN NEXT TO MCUSIDE WITH PINS76 -
100100755025DO NOT INSTALLSIDE WITH PINS1 -
25DO NOT INSTALLSIDE WITH PINS51 -
75DO NOT INSTALLDO NOT INSTALLALIGN PORTS AS DRAWN NEXT TO MCUALIGN PORTS AS DRAWN NEXT TO MCU1SIDE WITH PINS26 -
50ALIGN PORTS AS DRAWN NEXT TO MCU5176R5221JP9R5621JP8R8654321P1954321P2154321P2554321P2954321P3354321P3754321P2054321P2454321P2854321P3254321P3654321P2354321P2754321P3554321P3154321P2654321P3054321P3454321P2254321P18P1_29SAMTECTSW10608GS5PINBERG69157-102SAMTECTSW10608GS5PINP3_25D+_MCUP2_10SAMTECTSW10608GS5PINP0_20SAMTECTSW10608GS5PINDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNIDNITDOSAMTECTSW10608GS5PINSAMTECTSW10608GS5PINMISO_ISOSAMTECTSW10608GS5PINP1_28P1_22SAMTECTSW10608GS5PINSAMTECTSW10608GS5PINSAMTECTSW10608GS5PINHSA_ISOP1_19USB_UPP0_19P0_21TDISAMTECTSW10608GS5PINSAMTECTSW10608GS5PINP0_5PM1_CTRLP3_26P2_12P0_9SAMTECTSW10608GS5PINMCU_XT2SCL_ISOVBUSMCU_XT1SAMTECTSW10608GS5PINP1_31WPIRQ0B_ISOIRQ1B_ISOP2_13P2_0P2_1P2_2SAMTECTSW10608GS5PINP1_27P2_6P2_4P2_5RXDTXDRTCKSAMTECTSW10608GS5PINP1_8P1_0RSTOUT_NP1_26P1_25P1_23P2_8P2_9SSB_ISOSCLK_ISOSAMTECTSW10608GS5PINP1_16P1_17P1_10P1_15P1_14P1_4P1_1P1_9CF3_HSCLK_ISOSDA_ISOMCU_RSTRTCX2PM0_CTRLSBENB_ISOD-_MCUP4_29MOSI_ISOP2_3TMSP0_26IRQ_OUT_EN_ISOSAMTECTSW10608GS5PINSAMTECTSW10608GS5PINDNITRST_NTCLKIRQ_IN_ENP2_11P0_22P0_4P4_28RESB_CTRL10KBERG69157-10210K10KP0_24MCU_VDDP2_7HSDATA_ISOP0_24SAMTECTSW10608GS5PINGNDGND Figure 42.
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DO NOT POPULATE U2SELF BOOT EEPROMFACTORY USE ONLYCURRENT MEASUREMENT - DO NOT INSTALLC61C62C63R66R651TP611TP6221P17482631A3R6221JP6021JP61R61R63R6074295310186A4321P16R6474856321U20.1UFVDD2VDD210KMICRO24LC128-I-SN0.1UFWP_UXSBSCLDNIDNIBLKBLKISNS_OUTWEILAND25.161.0253AD8553ARMZDNIDNI560PFVDD_F200KIRQ0BDNIDNI4.02KDNIDNIDO NOT INSTALLDNI100K100KVREF_ISNSVDDDNI10KVDD2SBSCLVDD200SBSDAIRQ1B10KSBCONSBCONSB_ENBMOLEX22-03-2031SBSDAADG820BRMZDNIDGNDDGNDDGNDDGNDVDDS2S1INGNDDVFBGNDVREFENVCCVORGBRGASCLA1A2A0WPSDAVSSVCC09078-046 Figure 43.
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LAYOUT
09078-040 Figure 44. 09078-041
Figure 45.
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09078-042 Figure 46. 09078-043 Figure 47.
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ORDERING INFORMATION
BILL OF MATERIALS
Table 27.
Qty Designator Description Manufacturer/Part Number
1 A1 IC-ADI, 1.2 V, ultralow power, high PSRR voltage
reference Analog Devices, Inc./ADR280ARTZ 1 A2 IC swappable dual isolator Analog Devices, Inc./ADUM1250ARZ 4 C1, C8, C44, C78 Capacitor, tantalum, 10 μF AVX
20 C9 to C25, C32 to C34 Capacitor, ceramic, 22 nF AVX
30 C2, C7, C40, C42, C43, C48 to C59,
C61, C62, C72, C73, C75 to C77, C79
to C84
Capacitor, chip, X7R 0805, 0.1 μF Murata
4 C26, C27, C70, C71 Capacitor, mono, ceramic, C0G, 0402, 20 pF Murata
3 C3, C5, C41 Capacitor, tantalum, 4.7 μF AVX
2 C38, C74 Capacitor, ceramic chip, 1206, X7R, 1.0 μF Taiyo Yuden
2 C4, C6 Capacitor, ceramic, X7R, 0.22 μF Phycomp (Yageo)
4 CF1 to CF3, CLKIN Connector, PCB coax, BNC, ST AMP (Tyco)/227699-2
5 CR1 to CR5 Diode, LED, green, SMD Chicago Mini Lamp (CML Innovative Technologies)/CMD28-21VGCTR8T1 1 CR6 LED, green, surface mount LUMEX/SML-LXT0805GW-TR
12 E1A, E1B, E1C, E1N, E2A, E2B, E2C,
E2N, E8A, E8B, E8C, E8N Inductor, chip, ferrite bead, 0805, 1500 Ω Murata
37 JP2, JP7 to JP10, JP1A to JP8A, JP1B
to JP8B, JP1C to JP8C, JP1N to JP8N Connector, PCB Berg jumper, ST, male 2-pin Berg/69157-102
5 JP11, JP12, JP9A, JP9B, JP9C 3-pin solder jumper N/A
6 JP32, JP34, JP36, JP38, JP60, JP61 Resistor jumper, SMD 0805 (open), 0 Ω Panasonic
11 P1 to P10, P12 Connector, PCB TERM, black, 2-pin, ST WeilandD/25.161.0253
2 P11, P38 Connector, PCB, header, SHRD, ST, male 32-pin Samtec/TSW-1-30-08-G-D
1 P13 Connector, PCB, Berg, header, ST, male 20-pin Samtec/TSW-110-08-G-D
1 P14 Connector, PCB, USB, Type B, R/A, through hole AMP (Tyco)/4-1734376-8
1 P15 Connector, PCB, Berg, header, ST, male 4-pin Samtec/TSW106-08-G-S
1 P16 Connector, PCB straight header 3-pin Molex/22-03-2031
5 Q1 to Q5 Trans digital FET P channel Fairchild/FDV302P
8 R1 to R8 Do not install (TBD_R1206) N/A
8 R9 to R16 Resistor, PREC, thick film chip, R1206, 100 Ω Panasonic
12 R17 to R25, R32 to R34 Resistor, PREC, thick film chip, R0805, 1 kΩ Panasonic
3 R26 to R28 Resistor, MF, RN55, 1 M Vishay-Dale 3 R29 to R31 Resistor, MF, RN5, 100 kΩ Vishay-Dale 39 R35, R36, R38, R44 to R57, R64 to R66, R68 to R76, R78, R82 to R86, R58A, R58B, R59A, R59B
Resistor PREC thick film chip, R0805, 10 kΩ Panasonic
1 R37 Resistor, film, SMD 0805, 2 Ω Panasonic
5 R39 to R43 Resistor, PREC, thick film chip, R1206, 499 Panasonic
1 R77 Resistor, film, SMD, 0805, 680 Ω Multicomp
2 R79, R80 Resistor, film, SMD, 1206, 27 Ω Yageo-Phycomp
1 R81 Resistor, PREC, thick film chip, R1206, 1.5 kΩ Panasonic
1 RSB Resistor, jumper, SMD, 1206 (open), 0 Panasonic
2 S1, S2 SW SM mechanical key switch Omron/B3S1000
52 TP1 to TP18, TP22 to TP55 Connector, PCB, test point, black Components Corporation
1 U1 IC-ADI, polyphase, multifunction, energy metering IC Analog Devices, Inc./ADE7878CPZ 5 U3 to U7 IC-ADI quad channel digital isolator Analog Devices, Inc./ADum1401BRWZ
1 U8 IC ARM7, MCU, flash, 512 kΩ, 100 LQFP NXP/LPC2368FBD100
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Qty Designator Description Manufacturer/Part Number
1 Y1 IC crystal, 16.384 MHz Valpey Fisher Corporation
1 Y2 IC crystal quartz, 12.000 MHz ECS
1 A3 IC-ADI 1.8 V to 5.5 V 2:1 MUX/SPDT switches Analog Devices, Inc./ADG820BRMZ
1 A4 IC-ADI 1.8 V to 5 V auto-zero in amp with shutdown Analog Devices, Inc./AD8553ARMZ
1 C63 Capacitor, ceramic, NP0, 560 pF Phycomp (Yageo)
4 JP31, JP33, JP35, JP37 Resistor, jumper, SMD, 0805 (SHRT), 0 Panasonic
1 P17 Connector, PCB, TERM, black, 2-pin, ST Weiland/25.161.0253
20 P18 to P37 Connector, PCB, Berg, header, ST, male 5-pin Samtec/TSW106-08-G-S
1 R60 Resistor, PREC, thick film chip, R0805, 4.02 kΩ Panasonic
2 R61, R62 Resistor, PREC, thick film chip, R0805, 100 kΩ Panasonic
1 R63 Resistor, PREC, thick film chip, R1206, 200 kΩ Panasonic
2 TP61, TP62 Connector, PCB test point, black Components Corporation 1 U2 IC, serial EEPROM, 128 kΩ, 2.5 V Microchip/24LC128-I-SN
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NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
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©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG09078-0-8/10(0)
UCD3138
Highly Integrated Digital Controller for Isolated Power
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLUSAP2B
March 2012–Revised July 2012
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
Contents
1 Introduction ........................................................................................................................ 6
1.1 Features ...................................................................................................................... 6
1.2 Applications .................................................................................................................. 7
2 Overview ............................................................................................................................ 7
2.1 Description ................................................................................................................... 7
2.2 Ordering Information ........................................................................................................ 8
2.3 Product Selection Matrix ................................................................................................... 8
2.4 Functional Block Diagram .................................................................................................. 9
2.5 UCD3138 64 QFN – Pin Assignments ................................................................................. 10
2.6 Pin Functions .............................................................................................................. 11
2.7 UCD3138 40 QFN – Pin Assignments ................................................................................. 13
2.8 Pin Functions .............................................................................................................. 14
3 Electrical Specifications ..................................................................................................... 15
3.1 ABSOLUTE MAXIMUM RATINGS ...................................................................................... 15
3.2 THERMAL INFORMATION .............................................................................................. 15
3.3 RECOMMENDED OPERATING CONDITIONS ....................................................................... 15
3.4 ELECTRICAL CHARACTERISTICS .................................................................................... 16
3.5 PMBus/SMBus/I2C Timing ............................................................................................... 19
3.6 Power On Reset (POR) / Brown Out Reset (BOR) ................................................................... 20
3.7 Typical Clock Gating Power Savings ................................................................................... 21
3.8 Typical Temperature Characteristics ................................................................................... 22
4 Functional Overview .......................................................................................................... 23
4.1 ARM Processor ............................................................................................................ 23
4.2 Memory ..................................................................................................................... 23
4.2.1 CPU Memory Map and Interrupts ............................................................................ 23
4.2.1.1 Memory Map (After Reset Operation) ........................................................... 23
4.2.1.2 Memory Map (Normal Operation) ................................................................ 24
4.2.1.3 Memory Map (System and Peripherals Blocks) ................................................ 24
4.2.2 Boot ROM ....................................................................................................... 24
4.2.3 Customer Boot Program ....................................................................................... 25
4.2.4 Flash Management ............................................................................................. 25
4.3 System Module ............................................................................................................ 25
4.3.1 Address Decoder (DEC) ....................................................................................... 25
4.3.2 Memory Management Controller (MMC) .................................................................... 25
4.3.3 System Management (SYS) ................................................................................... 25
4.3.4 Central Interrupt Module (CIM) ............................................................................... 26
4.4 Peripherals ................................................................................................................. 27
4.4.1 Digital Power Peripherals ...................................................................................... 27
4.4.1.1 Front End ............................................................................................ 27
4.4.1.2 DPWM Module ..................................................................................... 28
4.4.1.3 DPWM Events ...................................................................................... 29
4.4.1.4 High Resolution DPWM ........................................................................... 31
4.4.1.5 Over Sampling ...................................................................................... 31
4.4.1.6 DPWM Interrupt Generation ...................................................................... 31
4.4.1.7 DPWM Interrupt Scaling/Range .................................................................. 31
4.5 DPWM Modes of Operation .............................................................................................. 32
4.5.1 Normal Mode .................................................................................................... 32
4.6 Phase Shifting ............................................................................................................. 34
4.7 DPWM Multiple Output Mode ............................................................................................ 35
4.8 DPWM Resonant Mode .................................................................................................. 36
4.9 Triangular Mode ........................................................................................................... 38
2 Contents Copyright © 2012, Texas Instruments Incorporated
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
4.10 Leading Edge Mode ....................................................................................................... 39
4.11 Sync FET Ramp and IDE Calculation .................................................................................. 41
4.12 Automatic Mode Switching ............................................................................................... 41
4.12.1 Phase Shifted Full Bridge Example .......................................................................... 41
4.12.2 LLC Example .................................................................................................... 42
4.12.3 Mechanism for Automatic Mode Switching .................................................................. 44
4.13 DPWMC, Edge Generation, IntraMux .................................................................................. 45
4.14 Filter ......................................................................................................................... 46
4.14.1 Loop Multiplexer ................................................................................................ 48
4.14.2 Fault Multiplexer ................................................................................................ 49
4.15 Communication Ports ..................................................................................................... 51
4.15.1 SCI (UART) Serial Communication Interface ............................................................... 51
4.15.2 PMBUS .......................................................................................................... 51
4.15.3 General Purpose ADC12 ...................................................................................... 52
4.15.4 Timers ............................................................................................................ 53
4.15.4.1 24-bit PWM Timer .................................................................................. 53
4.15.4.2 16-Bit PWM Timers ................................................................................ 54
4.15.4.3 Watchdog Timer .................................................................................... 54
4.16 Miscellaneous Analog ..................................................................................................... 54
4.17 Package ID Information ................................................................................................... 54
4.18 Brownout ................................................................................................................... 54
4.19 Global I/O ................................................................................................................... 55
4.20 Temperature Sensor Control ............................................................................................. 56
4.21 I/O Mux Control ............................................................................................................ 56
4.21.1 JTAG Use for I/O and JTAG Security ........................................................................ 57
4.22 Current Sharing Control .................................................................................................. 57
4.23 Temperature Reference .................................................................................................. 58
5 IC Grounding and Layout Recommendations ........................................................................ 59
6 Tools and Documentation ................................................................................................... 60
7 References ....................................................................................................................... 62
Revision History ......................................................................................................................... 63
Copyright © 2012, Texas Instruments Incorporated Contents 3
UCD3138
SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com
List of Figures
3-1 I2C/SMBus/PMBus Timing Diagram ........................................................................................... 20
3-2 Bus Timing in Extended Mode.................................................................................................. 20
3-3 Power On Reset (POR) / Brown Out Reset (BOR) .......................................................................... 20
3-4 EADC LSB Size with 4X Gain (mV) vs. Temperature ....................................................................... 22
3-5 ADC12 Measurement Temperature Sensor Voltage vs. Temperature.................................................... 22
3-6 ADC12 2.5-V Reference vs. Temperature .................................................................................... 22
3-7 ADC12 Temperature Sensor Measurement Error vs. Temperature....................................................... 22
3-8 UCD3138 Oscillator Frequency (2MHz Reference, Divided Down from 250MHz) vs. Temperature.................. 22
4-1 Input Stage of EADC Module ................................................................................................... 28
4-2 Front End Module ................................................................................................................ 28
4-3 Secondary-Referenced Phase-Shifted Full Bridge Control
With Synchronous Rectification ................................................................................................ 42
4-4 Secondary-Referenced Half-Bridge Resonant LLC Control
With Synchronous Rectification ................................................................................................ 43
4-5 Fault Mux Block Diagram ....................................................................................................... 51
4-6 PMBus Address Detection Method ............................................................................................ 52
4-7 ADC12 Control Block Diagram ................................................................................................. 53
4-8 Internal Temp Sensor............................................................................................................ 56
4-9 Simplified Current Sharing Circuitry ........................................................................................... 57
4 List of Figures Copyright © 2012, Texas Instruments Incorporated
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
List of Tables
2-1 Pin Functions ..................................................................................................................... 11
2-2 Pin Functions ..................................................................................................................... 14
3-1 I2C/SMBus/PMBus Timing Characteristics.................................................................................... 19
4-1 Interrupt Priority Table ........................................................................................................... 26
4-2 DPWM Interrupt Divide Ratio ................................................................................................... 31
Copyright © 2012, Texas Instruments Incorporated List of Tables 5
UCD3138
SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com
Highly Integrated Digital Controller for Isolated Power
Check for Samples: UCD3138
1 Introduction
1.1 Features
1
• Digital Control of up to 3 Independent – Synchronous Rectifier Soft On/Off
Feedback Loops – Low IC Standby Power
– Dedicated PID based hardware • Soft Start / Stop with and without Pre-bias
– 2-pole/2-zero configurable • Fast Input Voltage Feed Forward Hardware
– Non-Linear Control • Primary Side Voltage Sensing
• Up to 16MHz Error Analog to Digital Converter • Copper Trace Current Sensing
(EADC) • Flux and Phase Current Balancing for Non-
– Configurable Resolution as Small as Peak Current Mode Control Applications
1mV/LSB • Current Share Bus Support
– Automatic Resolution Selection – Analog Average
– Up to 8x Oversampling – Master/Slave
– Hardware Based Averaging (up to 8x) • Feature Rich Fault Protection Options
– 14 bit Effective DAC – 7 High Speed Analog Comparators
– Adaptive Sample Trigger Positioning – Cycle-by-Cycle Current Limiting
• Up to 8 High Resolution Digital Pulse Width – Programmable Fault Counting
Modulated (DPWM) Outputs – External Fault Inputs
– 250ps Pulse Width Resolution – 10 Digital Comparators
– 4ns Frequency Resolution – Programmable blanking time
– 4ns Phase Resolution • Synchronization of DPWM waveforms between
– Adjustable Phase Shift Between Outputs multiple UCD3138 devices
– Adjustable Dead-band Between Pairs • 14 channel, 12 bit, 267 ksps General Purpose
– Cycle-by-Cycle Duty Cycle Matching ADC with integrated
– Up to 2MHz Switching Frequency – Programmable averaging filters
• Configurable PWM Edge Movement – Dual sample and hold
– Trailing Modulation • Internal Temperature Sensor
– Leading Modulation • Fully Programmable High-Performance
– Triangular Modulation 31.25MHz, 32-bit ARM7TDMI-S Processor
• Configurable Feedback Control – 32 kByte (kB) Program Flash
– Voltage Mode – 2 kB Data Flash with ECC
– Average Current Mode – 4 kB Data RAM
– Peak Current Mode Control – 4 kB Boot ROM Enables Firmware Boot-Load
– Constant Current in the Field via I2C or UART
– Constant Power • Communication Peripherals
• Configurable Modulation Methods – I2C/PMBus
– Frequency Modulation – 2 UARTs on UCD3138RGC (64-pin QFN)
– Phase Shift Modulation – 1 UART on UCD3138RHA (40-pin QFN)
– Pulse Width Modulation • JTAG Debug Port
• Fast, Automatic and Smooth Mode Switching • Timer capture with selectable input pins
– Frequency Modulation and PWM • Up to 5 Additional General Purpose Timers
– Phase Shift Modulation and PWM • Built In Watchdog: BOD and POR
• High Efficiency and Light Load Management • 64-pin QFN and 40-pin QFN packages
– Burst Mode • Operating Temperature: –40°C to 125°C
– Ideal Diode Emulation • Fusion_Digital_Power_Designer GUI Support 1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2012, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
1.2 Applications
• Power Supplies and Telecom Rectifiers
• Power Factor Correction
• Isolated dc-dc Modules
2 Overview
2.1 Description
The UCD3138 is a digital power supply controller from Texas Instruments offering superior levels of
integration and performance in a single chip solution. The flexible nature of the UCD3138 makes it
suitable for a wide variety of power conversion applications. In addition, multiple peripherals inside the
device have been specifically optimized to enhance the performance of ac/dc and isolated dc/dc
applications and reduce the solution component count in the IT and network infrastructure space.
The UCD3138 is a fully programmable solution offering customers complete control of their application,
along with ample ability to differentiate their solution. At the same time, TI is committed to simplifying our
customer’s development effort through offering best in class development tools, including application
firmware, Code Composer Studio™ software development environment, and TI’s power development GUI
which enables customers to configure and monitor key system parameters.
At the core of the UCD3138 controller are the digital control loop peripherals, also known as Digital Power
Peripherals (DPP). Each DPP implements a high speed digital control loop consisting of a dedicated Error
Analog to Digital Converter (EADC), a PID based 2 pole–2 zero digital compensator and DPWM outputs
with 250 ps pulse width resolution. The device also contains a 12-bit, 267ksps general purpose ADC with
up to 14 channels, timers, interrupt control, JTAG debug and PMBus and UART communications ports.
The device is based on a 32-bit ARM7TDMI-S RISC microcontroller that performs real-time monitoring,
configures peripherals and manages communications. The ARM microcontroller executes its program out
of programmable flash memory as well as on-chip RAM and ROM.
In addition to the FDPP, specific power management peripherals have been added to enable high
efficiency across the entire operating range, high integration for increased power density, reliability, and
lowest overall system cost and high flexibility with support for the widest number of control schemes and
topologies. Such peripherals include: light load burst mode, synchronous rectification, LLC and phase
shifted full bridge mode switching, input voltage feed forward, copper trace current sense, ideal diode
emulation, constant current constant power control, synchronous rectification soft on and off, peak current
mode control, flux balancing, secondary side input voltage sensing, high resolution current sharing,
hardware configurable soft start with pre bias, as well as several other features. Topology support has
been optimized for voltage mode and peak current mode controlled phase shifted full bridge, single and
dual phase PFC, bridgeless PFC, hard switched full bridge and half bridge, and LLC half bridge and full
bridge.
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2.2 Ordering Information
PART NUMBER PIN COUNT PACKAGE SUPPLY TOP SIDE MARKING OPERATING TEMPERATURE RANGE, TA
UCD3138RGCT 64 QFN 250 (Small Reel) UCD3138 –40°C to 125°C
UCD3138RGCR 64 QFN 2000 (Large Reel) UCD3138 –40°C to 125°C
UCD3138RHAT 40 QFN 250 (Small Reel) UCD3138 –40°C to 125°C
UCD3138RHAR 40 QFN 2500 (large Reel) UCD3138 –40°C to 125°C
2.3 Product Selection Matrix
FEATURE UCD3138 64 PIN UCD3138 40 PIN
ARM7TDMI-S Core Processor 31.25 MHz 31.25 MHz
High Resolution DPWM Outputs (250ps Resolution) 8 8
Number of High Speed Independent Feedback Loops (# Regulated Output 3 3 Voltages)
12-bit, 267ksps, General Purpose ADC Channels 14 7
Digital Comparators at ADC Outputs 4 4
Flash Memory (Program) 32 KB 32 KB
Flash Memory (Data) 2 KB 2 KB
Flash Security √ √
RAM 4 KB 4 KB
DPWM Switching Frequency up to 2 MHz up to 2 MHz
Programmable Fault Inputs 4 1 + 2(1)
High Speed Analog Comparators with Cycle-by-Cycle Current Limiting 7(2) 6(2)
UART (SCI) 2 1(1)
PMBus √ √
Timers 4 (16 bit) and 1 (24 bit) 4 (16 bit) and 1 (24 bit)
Timer PWM Outputs 2 1
Timer Capture Inputs 1 1(1)
Watchdog √ √
On Chip Oscillator √ √
Power-On Reset and Brown-Out Reset √ √
JTAG √ √
Package Offering 64 Pin QFN (9mm x 9mm) 40 Pin QFN (6mm x 6mm)
Sync IN and Sync OUT Functions √ √
Total GPIO (includes all pins with multiplexed functions such as, DPWM, Fault 30 18 Inputs, SCI, etc.)
External Interrupts 1 0
(1) This number represents an alternate pin out that is programmable via firmware. See the UCD3138 Digital Power Peripherals
Programmer’s Manual for details.
(2) To facilitate simple OVP and UVP connections both comparators B and C are connected to the AD03 pin.
8 Overview Copyright © 2012, Texas Instruments Incorporated
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Front End 2
Analog
Comparators
Power and
1.8 V Voltage
Regulator
AD07
AD06
AD04
V33DIO /RESET
SCI_RX0
SCI_TX0
PMBUS_CLK
PMBUS_DATA
AGND
V33D
BP18
FAULT3
FAULT2
TCAP
TMS
TDI
TDO
TCK
EXT_INT
FAULT1
FAULT0
PWM1
PWM0
SCI_RX1
SCI_TX1
PMBUS_CTRL
PMBUS_ALERT
SYNC
DGND
DPWM3B
DPWM3A
DPWM2B
DPWM2A
DPWM1B
DPWM1A
DPWM0B
DPWM0A
EAP0
EAN0
EAP1
EAN1
V33 A
AD00
AD01
AD0 2
AD1 3
PID Based
Filter 0
DPWM0
DPWM1
DPWM2
DPWM3
PID Based
Filter 1
PID Based
Filter 2
ADC_EXT_ TRIG
ADC12
ADC12 Control
Sequencing, Averaging,
Digital Compare, Dual
Sample and hold AD[13:0 ]
A
B
C
D
E
F
G
Current Share
Analog, Average, Master/Slave
AD03
AD0 2
AD1 3
AGND
PMBus
Timers
4 – 16 bit (PWM)
1 – 24 bit
UART0
UART1
GPIO
Control
JTAG
Loop MUX
ARM7TDMI-S
32 bit, 31.25 MHz
Memory
PFLASH 32 kB
DFLASH 2 kB
RAM 4 kB
ROM 4 kB
Power On Reset
Brown Out Detection
Oscillator
Internal Temperature
Sensor
Advanced Power Control
Mode Switching, Burst Mode, IDE,
Synchronous Rectification soft on & off
Front End 1
Constant Power Constant
Current
Input Voltage Feed Forward
Front End Averaging
Digital Comparators
Fault MUX &
Control
Cycle by Cycle
Current Limit
Digital
Comparators
DAC0
EADC
X
AFE
Value
Dither
!
CPCC
Filter x
Ramp
SAR/Prebias
Abs()
2 Avg() AFE
23-AFE
Peak Current Mode
Control Comparator
A0
EAP2
EAN2
Front End 0
UCD3138
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2.4 Functional Block Diagram
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UCD3138
(64 QFN)
AGND 1
AD13 2
AD12 3
AD10 4
AD07 5
AD06 6
AD04 7
AD03 8
V33DIO 9
10
/RESET 11
ADC_EXT_TRIG/TCAP/SYNC/PWM0 12
SCI_RX0 13
SCI_TX0 14
DGND
PMBUS_CLK/SCI_TX0 15
PMBUS_DATA/SCI_RX0 16
48 AGND
47 V33D
46 BP18
45 V33DIO
44 DGND
43 FAULT3
42 FAULT2
41 TCAP
40 TMS
39 TDI/SCI_RX0/PMBUS_CTRL/FAULT1
38 TDO/SCI_TX0/PMBUS_ALERT/FAULT0
37 TCK/TCAP/SYNC/PWM0
36 FAULT1
35 FAULT0
34 INT_EXT
33 DGND
32
PWM1
31
PWM0
30
SCI_RX1/PMBUS_CTRL
29
SCI_TX1/PMBUS_ALERT
28
PMBUS_CTRL
27
PMBUS_ALERT
26
SYNC/TCAP/ADC_EXT_TRIG/PWM0
25
DGND
24
DPWM3B
23
DPWM3A
22
DPWM2B
21
DPWM2A
20
DPWM1B
19
DPWM1A
18
DPWM0B
17
DPWM0A
64
AGND
63
EAP0
62
EAN0
61
EAP1
60
EAN1
59
EAP2
58
EAN2
57
AGND
56
V33A
55
AD00
54
AD01
53
AD02
52
AD05
51
AD08
50
AD09
49
AD11
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2.5 UCD3138 64 QFN – Pin Assignments
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2.6 Pin Functions
Additional pin functionality is specified in the following table.
Table 2-1. Pin Functions
ALTERNATE ASSIGNMENT PIN NAME PRIMARY ASSIGNMENT CONFIGURABLE NO. 1 NO. 2 NO. 3 AS A GPIO?
1 AGND Analog ground
2 AD13 12-bit ADC, Ch 13, comparator E, I-share DAC output
3 AD12 12-bit ADC, Ch 12
4 AD10 12-bit ADC, Ch 10
5 AD07 12-bit ADC, Ch 7, Connected to comparator F and reference DAC output to comparator G
6 AD06 12-bit ADC, Ch 6, Connected to comparator F DAC output
7 AD04 12-bit ADC, Ch 4, Connected to comparator D DAC output
8 AD03 12-bit ADC, Ch 3, Connected to comparator B and C
9 V33DIO Digital I/O 3.3V core supply
10 DGND Digital ground
11 RESET Device Reset Input, active low
12 ADC_EXT_TRIG ADC conversion external trigger input TCAP SYNC PWM0 Yes
13 SCI_RX0 SCI RX 0 Yes
14 SCI_TX0 SCI TX 0 Yes
15 PMBUS_CLK PMBUS Clock (Open Drain) SCI TX 0 Yes
16 PMBUS_DATA PMBus data (Open Drain) SCI RX 0 Yes
17 DPWM0A DPWM 0A output Yes
18 DPWM0B DPWM 0B output Yes
19 DPWM1A DPWM 1A output Yes
20 DPWM1B DPWM 1B output Yes
21 DPWM2A DPWM 2A output Yes
22 DPWM2B DPWM 2B output Yes
23 DPWM3A DPWM 3A output Yes
24 DPWM3B DPWM 3B output Yes
25 DGND Digital ground
26 SYNC DPWM Synchronize pin TCAP ADC_EXT_ PWM0 Yes TRIG
27 PMBUS_ALERT PMBus Alert (Open Drain) Yes
28 PMBUS_CTRL PMBus Control (Open Drain) Yes
29 SCI_TX1 SCI TX 1 PMBUS_AL Yes ERT
30 SCI_RX1 SCI RX 1 PMBUS_CT Yes RL
31 PWM0 General purpose PWM 0 Yes
32 PWM1 General purpose PWM 1 Yes
33 DGND Digital ground
34 INT_EXT External Interrupt Yes
35 FAULT0 External fault input 0 Yes
36 FAULT1 External fault input 1 Yes
37 TCK JTAG TCK TCAP SYNC PWM0 Yes
38 TDO JTAG TDO SCI_TX0 PMBUS_AL FAULT0 Yes ERT
39 TDI JTAG TDI SCI_RX0 PMBUS_CT FAULT1 Yes RL
40 TMS JTAG TMS Yes
41 TCAP Timer capture input Yes
42 FAULT2 External fault input 2 Yes
43 FAULT3 External fault input 3 Yes
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Table 2-1. Pin Functions (continued)
ALTERNATE ASSIGNMENT PIN NAME PRIMARY ASSIGNMENT CONFIGURABLE NO. 1 NO. 2 NO. 3 AS A GPIO?
44 DGND Digital ground
45 V33DIO Digital I/O 3.3V core supply
46 BP18 1.8V Bypass
47 V33D Digital 3.3V core supply
48 AGND Substrate analog ground
49 AGND Analog ground
50 EAP0 Channel #0, differential analog voltage, positive input
51 EAN0 Channel #0, differential analog voltage, negative input
52 EAP1 Channel #1, differential analog voltage, positive input
53 EAN1 Channel #1, differential analog voltage, negative input
54 EAP2 Channel #2, differential analog voltage, positive input
55 EAN2 Channel #2, differential analog voltage, negative input
56 AGND Analog ground
57 V33A Analog 3.3V supply
58 AD00 12-bit ADC, Ch 0, Connected to current source
59 AD01 12-bit ADC, Ch 1, Connected to current source
60 AD02 12-bit ADC, Ch 2, Connected to comparator A, I-share
61 AD05 12-bit ADC, Ch 5
62 AD08 12-bit ADC, Ch 8
63 AD09 12-bit ADC, Ch 9
64 AD11 12-bit ADC, Ch 11
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UCD3138
(40 QFN)
AGND 1
2
3
4
5
AD13
6
AD06
7
AD04
8
AD03
9
DGND
10
/RESET
11
ADC_EXT_TRIG/TCAP/SYNC/PWM0
12 13 14 15
PMBUS_CLK/SCI_TX0
16
PMBUS_DATA/SCI_RX0
AGND
BP18
DGND
V33D
40 39
TMS
38
TDI/SCI_RX0/PMBUS_CTRL/FAULT1
37
TDO/SCI_TX0/PMBUS_ALERT/FAULT0
36
TCK/TCAP/SYNC/PWM0
35 34 33
FAULT2
32 31
AGND
30
29
28
27
26
DPWM3B
25
DPWM3A
24
PMBUS_CTRL
23
PMBUS_ALERT
22
DPWM2B
21
DPWM2A
20
DPWM1B
19
DPWM1A
18
DPWM0B
17
DPWM0A
EAP0
EAN0
EAP1
EAN1
EAP2
AGND
V33A
AD00
AD01
AD02
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2.7 UCD3138 40 QFN – Pin Assignments
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2.8 Pin Functions
Additional pin functionality is specified in the following table.
Table 2-2. Pin Functions
ALTERNATE ASSIGNMENT PIN NAME PRIMARY ASSIGNMENT CONFIGURABLE NO. 1 NO. 2 NO. 3 AS A GPIO?
1 AGND Analog ground
2 AD13 12-bit ADC, Ch 13, Connected to comparator E, I-share
3 AD06 12-bit ADC, Ch 6, Connected to comparator F
4 AD04 12-bit ADC, Ch 4, Connected to comparator D
5 AD03 12-bit ADC, Ch 3, Connected to comparator B & C
6 DGND Digital ground
7 RESET Device Reset Input, active low
8 ADC_EXT_TRIG ADC conversion external trigger input TCAP SYNC PWM0 Yes
9 PMBUS_CLK PMBUS Clock (Open Drain) SCI_TX0 Yes
10 PMBUS_DATA PMBus data (Open Drain) SCI_RX0 Yes
11 DPWM0A DPWM 0A output Yes
12 DPWM0B DPWM 0B output Yes
13 DPWM1A DPWM 1A output Yes
14 DPWM1B DPWM 1B output Yes
15 DPWM2A DPWM 2A output Yes
16 DPWM2B DPWM 2B output Yes
17 DWPM3A DPWM 3A output Yes
18 DPWM3B DPWM 3B output Yes
19 PMBUS_ALERT PMBus Alert (Open Drain) Yes
20 PMBUS_CTRL PMBus Control (Open Drain) Yes
21 TCK JTAG TCK TCAP SYNC PWM0 Yes
22 TDO JTAG TDO SCI_TX0 PMBUS_A FAULT0 Yes
LERT
23 TDI JTAG TDI SCI_RX0 PMBUS_C FAULT1 Yes
TRL
24 TMS JTAG TMS Yes
25 FAULT2 External fault input 2 Yes
26 DGND Digital ground
27 V33D Digital 3.3V core supply
28 BP18 1.8V Bypass
29 AGND Substrate analog ground
30 AGND Analog ground
31 EAP0 Channel #0, differential analog voltage, positive input
32 EAN0 Channel #0, differential analog voltage, negative input
33 EAP1 Channel #1, differential analog voltage, positive input
34 EAN1 Channel #1, differential analog voltage, negative input
35 EAP2 Channel #2, differential analog voltage, positive input
36 AGND Analog ground
37 V33A Analog 3.3V supply
38 AD00 12-bit ADC, Ch 0, Connected to current source
39 AD01 12-bit ADC, Ch 1, Connected to current source
40 AD02 12-bit ADC, Ch 2, Connected to comparator A, I-share
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3 Electrical Specifications
3.1 ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
MIN MAX
V33D V33D to DGND –0.3 3.8 V
V33DIO V33DIO to DGND –0.3 3.8 V
V33A V33A to AGND –0.3 3.8 V
|DGND – AGND| Ground difference 0.3 V
All Pins, excluding AGND(2) Voltage applied to any pin –0.3 3.8 V
TOPT Junction Temperature –40 125 °C
TSTG Storage temperature –55 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Referenced to DGND
3.2 THERMAL INFORMATION
UCD3138 UCD3138
THERMAL METRIC(1) 64 PIN QFN 40 PIN UNITS
QFN
θJA Junction-to-ambient thermal resistance (2) 25.1 31.8
θJCtop Junction-to-case (top) thermal resistance (3) 10.5 18.5
θJB Junction-to-board thermal resistance (4) 4.6 6.8
°C/W
ψJT Junction-to-top characterization parameter(5) 0.2 0.2
ψJB Junction-to-board characterization parameter (6) 4.6 6.7
θJCbot Junction-to-case (bottom) thermal resistance (7) 1.2 1.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
3.3 RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
V33D Digital power 3.0 3.3 3.6 V
V33DIO Digital I/O power 3.0 3.3 3.6
V33A Analog power 3.0 3.3 3.6 V
TJ Junction temperature -40 - 125 °C
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3.4 ELECTRICAL CHARACTERISTICS
V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SUPPLY CURRENT
Measured on V33A. The device is
I33A powered up but all ADC12 and EADC 6.3 mA
sampling is disabled
I33DIO All GPIO and communication pins are 0.35 mA open
I33D ROM program execution 60 mA
I33D Flash programming in ROM mode 70 mA
The device is in ROM mode with all
I33 DPWMs enabled and switching at 2 100 mA
MHz. The DPWMs are all unloaded.
ERROR ADC INPUTS EAP, EAN
EAP – AGND –0.15 1.998 V
EAP – EAN –0.256 1.848 V
Typical error range AFE = 0 –256 248 mV
AFE = 3 0.8 1 1.20 mV
AFE = 2 1.7 2 2.30 mV
EAP – EAN Error voltage digital resolution
AFE = 1 3.55 4 4.45 mV
AFE = 0 6.90 8 9.10 mV
REA Input impedance (See Figure 4-1) AGND reference 0.5 MΩ
IOFFSET Input offset current (See Figure 4-1) –5 5 μA
Input voltage = 0 V at AFE = 0 –2 2 LSB
Input voltage = 0 V at AFE = 1 –2.5 2.5 LSB
EADC Offset
Input voltage = 0 V at AFE = 2 –3 -3 LSB
Input voltage = 0 V at AFE = 3 –4 4 LSB
Sample Rate 16 MHz
Analog Front End Amplifier Bandwidth 100 MHz
Gain See Figure 4-2 1 V/V
A0 Minimum output voltage 100 mV
EADC DAC
DAC range 0 1.6 V
VREF DAC reference resolution 10 bit, No dithering enabled 1.56 mV
VREF DAC reference resolution With 4 bit dithering enabled 97.6 μV
INL –3.0 3.0 LSB
DNL Does not include MSB transition –2.1 1.6 LSB
DNL at MSB transition -1.4 LSB
DAC reference voltage 1.58 1.61 V
τ Settling Time From 10% to 90% 250 ns
ADC12
IBIAS Bias current for PMBus address pins 9.5 10.5 μA
Measurement range for voltage monitoring 0 2.5 V
Internal ADC reference voltage –40°C to 125°C 2.475 2.500 2.525 V
–40°C to 25°C –0.4
Change in Internal ADC reference from 25°C to 85°C –1.8 mV 25°C reference voltage(1)
25°C to 125°C –4.2
(1) As designed and characterized. Not 100% tested in production.
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ELECTRICAL CHARACTERISTICS (continued)
V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
ADC12 INL integral nonlinearity(1) +/-2.5 LSB
ADC12 DNL differential nonlinearity(1) ADC_SAMPLINGSEL = 6 for all ADC12 –0.7/+2.5 LSB
ADC Zero Scale Error data, 25 °C to 125 °C –7 7 mV
ADC Full Scale Error –35 35 mV
Input bias 2.5 V applied to pin 400 nA
Input leakage resistance(1) ADC_SAMPLINGSEL= 6 or 0 1 MΩ
Input Capacitance(1) 10 pF
ADC single sample conversion time(1) ADC_SAMPLINGSEL= 6 or 0 3.9 μs
DIGITAL INPUTS/OUTPUTS(2) (3)
V DGND OL Low-level output voltage(4) IOH = 4 mA, V33DIO = 3 V + 0.25 V
V V33DIO OH High-level output voltage (4) IOH = –4 mA, V33DIO = 3 V – 0.6 V
VIH High-level input voltage V33DIO = 3 V 2.1 V
VIL Low-level input voltage V33DIO = 3 V 1.1 V
IOH Output sinking current 4 mA
IOL Output sourcing current –4 mA
SYSTEM PERFORMANCE
TWD Watchdog time out range Total time is: TWD x 14.6 17 20.5 ms (WDCTRL.PERIOD+1)
Time to disable DPWM output based on High level on FAULT pin 70 ns active FAULT pin signal
Processor master clock (MCLK) 31.25 MHz
tDelay Digital compensator delay(5) (1 clock = 32ns) 6 clocks
VDD Slew minimum VDD slew rate(6) VDD slew rate between 2.3 V and 2.9 V 0.25 V/ms
t(reset) Pulse width needed at reset(6) 10 μs
Retention period of flash content (data TJ = 25°C 100 years retention and program)
Program time to erase one page or block in 20 ms data flash or program flash
Program time to write one word in data 20 μs flash or program flash
f(PCLK) Internal oscillator frequency 240 250 260 MHz
Sync-in/sync-out pulse width Sync pin 256 ns
Flash Read 1 MCLKs
Flash Write 20 μs
I Current share current source (See SHARE Figure 4-9) 238 259 μA
RSHARE Current share resistor (See Figure 4-9) 9.75 10.3 kΩ
POWER ON RESET AND BROWN OUT (V33D pin, See Figure 3-3)
VGH Voltage good High 2.7 V
VGL Voltage good Low 2.5 V
Vres Voltage at which IReset signal is valid 0.8 V
(2) DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.
(3) On the 40 pin package V33DIO is connected to V33D internally.
(4) The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop
specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH.
(5) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which
has no variation associated with it, must be accounted for when calculating the system dynamic response.
(6) As designed and characterized. Not 100% tested in production.
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ELECTRICAL CHARACTERISTICS (continued)
V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
T Time delay after Power is good or POR RESET* relinquished 1 ms
Brownout Internal signal warning of brownout 2.9 V conditions
TEMPERATURE SENSOR(7)
VTEMP Voltage range of sensor 1.46 2.44 V
Voltage resolution Volts/°C 5.9 mV/ºC
Temperature resolution Degree C per bit 0.1034 ºC/LSB
Accuracy(7) (8) -40°C to 125°C –10 ±5 10 ºC
Temperature range -40°C to 125°C –40 125 ºC
ITEMP Current draw of sensor when active 30 μA
TON Turn on time / settling time of sensor 100 μs
VAMB Ambient temperature Trimmed 25°C reading 1.85 V
ANALOG COMPARATOR
DAC Reference DAC Range 0 2.5 V
Reference Voltage 2.478 2.5 2.513 V
Bits 7 bits
INL(7) –0.42 0.21 LSB
DNL(7) 0.06 0.12 LSB
Offset –5.5 19.5 mV
Time to disable DPWM output based on 0
V to 2.5 V step input on the analog 150 ns
comparator.(9)
Reference DAC buffered output load(10) 0.5 1 mA
Buffer offset (-0.5 mA) 4.6 8.3 mV
Buffer offset (1.0 mA) –0.05 17 mV
(7) Characterized by design and not production tested.
(8) Ambient temperature offset value should be used from the TEMPSENCTRL register to meet accuracy.
(9) As designed and characterized. Not 100% tested in production.
(10) Available from reference DACs for comparators D, E, F and G.
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3.5 PMBus/SMBus/I2C Timing
The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus,
and PMBus in Slave or Master mode are shown in Table 3-1, Figure 3-1, and Figure 3-2. The numbers in
Table 3-1 are for 400 kHz operating frequency. However, the device supports all three speeds, standard
(100 kHz), fast (400 kHz), and fast mode plus (1 MHz).
Table 3-1. I2C/SMBus/PMBus Timing Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Typical values at TA = 25°C and VCC = 3.3 V (unless otherwise noted)
fSMB SMBus/PMBus operating frequency Slave mode, SMBC 50% duty cycle 100 1000 kHz
fI2C I2C operating frequency Slave mode, SCL 50% duty cycle 100 1000 kHz
t(BUF) Bus free time between start and stop 1.3 ms
t(HD:STA) Hold time after (repeated) start 0.6 ms
t(SU:STA) Repeated start setup time 0.6 ms
t(SU:STO) Stop setup time 0.6 ms
t(HD:DAT) Data hold time Receive mode 0 ns
t(SU:DAT) Data setup time 100 ns
t(TIMEOUT) Error signal/detect(1) 35 ms
t(LOW) Clock low period 1.3 ms
t(HIGH) Clock high period(2) 0.6 ms
t Cumulative clock low slave extend (LOW:SEXT) time(3) 25 ms
t 20 + 0.1 f Clock/data fall time Rise time tr = (VILmax – 0.15) to (VIHmin + 0.15) Cb(4) 300 ns
t 20 + 0.1 r Clock/data rise time Fall time tf = 0.9 VDD to (VILmax – 0.15) Cb(4) 300 ns
Cb Total capacitance of one bus line 400 pF
(1) The device times out when any clock low exceeds t(TIMEOUT).
(2) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This
specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
(3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) Cb (pF)
Figure 3-1. I2C/SMBus/PMBus Timing Diagram
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TPOR
undefined
V33D
IReset
3.3 V
TPOR
VGH
VGL
Vres
t
t
Brown Out
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Figure 3-2. Bus Timing in Extended Mode
3.6 Power On Reset (POR) / Brown Out Reset (BOR)
Figure 3-3. Power On Reset (POR) / Brown Out Reset (BOR)
VGH – This is the V33D threshold where the internal power is declared good. The UCD3138 comes
out of reset when above this threshold.
VGL – This is the V33D threshold where the internal power is declared bad. The device goes into
reset when below this threshold.
Vres – This is the V33D threshold where the internal reset signal is no longer valid. Below this
threshold the device is in an indeterminate state.
IReset – This is the internal reset signal. When low, the device is held in reset. This is equivalent to
holding the reset pin on the IC high.
TPOR – The time delay from when VGH is exceeded to when the device comes out of reset.
Brown – This is the V33D voltage threshold at which the device sets the brown out status bit. In
Out addition an interrupt can be triggered if enabled.
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DPWM FE_CTRL PCM ADC12 PMBUS TIMER CPCC FILTER SCI SCI GIO
0
1
2
3
4
5
6
UCD3138 Function
Power Savings (mA)
G001
4.9
2.57
1.2
0.8
0.4 0.4
0.2 0.2
0.1 0.1
0
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3.7 Typical Clock Gating Power Savings
Power disable control register provides control bits that can enable or disable arrival of clock to several
peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more.
All these controls are enabled as default. If a specific peripheral is not used in a specific application the
clock gate can be disabled in order to block the propagation of clock signal to that peripheral and therefore
reduce the overall current consumption of the device.
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2.475
2.480
2.485
2.490
2.495
2.500
2.505
2.510
2.515
−40 −20 0 20 40 60 80 100 120
Temperature (°C)
ADC12 Reference
G003b
ADC12 2.5-V Reference
1.92
1.96
2
2.04
2.08
−40 −20 0 20 40 60 80 100 120
Temperature (°C)
2-MHZ Reference
G004b
UCD3138 Oscillator Frequency
−4
−2
0
2
4
6
8
−40 −20 0 20 40 60 80 100 120
Temperature (°C)
ADC12 Error (LSB)
G002b
ADC12 Temperature Sensor Measurement Error
1.4
1.6
1.8
2.0
2.2
2.4
2.6
−60 −40 −20 0 20 40 60 80 100 120 140 160
Temperature (°C)
Sensor Voltage (V)
G006b
ADC12 Measurement Temperature Sensor Voltage
1.6
1.7
1.8
1.9
2
2.1
−40 −20 0 20 40 60 80 100 120
Temperature (°C)
EADC LSB Size (mV)
G005a
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3.8 Typical Temperature Characteristics
Figure 3-4. EADC LSB Size with 4X Gain (mV) vs. Temperature
Figure 3-5. ADC12 Measurement Temperature Figure 3-7. ADC12 Temperature Sensor
Sensor Voltage vs. Temperature Measurement Error vs. Temperature
Figure 3-6. ADC12 2.5-V Reference vs. Figure 3-8. UCD3138 Oscillator Frequency (2MHz
Temperature Reference, Divided Down from 250MHz) vs.
Temperature
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4 Functional Overview
4.1 ARM Processor
The ARM7TDMI-S processor is a synthesizable member of the ARM family of general purpose 32-bit
microprocessors. The ARM architecture is based on RISC (Reduced Instruction Set Computer) principles
where two instruction sets are available. The 32-bit ARM instruction set and the 16-bit Thumb instruction
set. The Thumb instruction allows for higher code density equivalent to a 16-bit microprocessor, with the
performance of the 32-bit microprocessor.
The three-staged pipelined ARM processor has fetch, decode and execute stage architecture. Major
blocks in the ARM processor include a 32-bit ALU, 32 x 8 multiplier, and a barrel shifter. A JTAG port is
also available for firmware debugging.
4.2 Memory
The UCD3138 (ARM7TDMI-S) is a Von-Neumann architecture, where a single bus provides access to all
of the memory modules. All of the memory module addresses are sequentially aligned along the same
address range. This applies to program flash, data flash, ROM and all other peripherals.
Within the UCD3138 architecture, there is a 1024x32-bit Boot ROM that contains the initial firmware
startup routines for PMBUS communication and non-volatile (FLASH) memory download. This boot ROM
is executed after power-up-reset checks if there is a valid FLASH program written. If a valid program is
present, the ROM code branches to the main FLASH-program execution.
UCD3138 also supports customization of the boot program by allowing an alternative boot routine to be
executed from program FLASH. This feature enables assignment of a unique address to each device;
therefore, enabling firmware reprogramming even when several devices are connected on the same
communication bus.
Two separate FLASH memory areas are present inside the device. The 32 kB Program FLASH is
organized as an 8 k x 32 bit memory block and is intended to be for the firmware program. The block is
configured with page erase capability for erasing blocks as small as 1kB per page, or with a mass erase
for erasing the entire program FLASH array. The FLASH endurance is specified at 1000 erase/write
cycles and the data retention is good for 100 years. The 2 kB data FLASH array is organized as a 512 x
32 bit memory (32 byte page size). The Data FLASH is intended for firmware data value storage and data
logging. Thus, the Data FLASH is specified as a high endurance memory of 20 k cycles with embedded
error correction code (ECC).
For run time data storage and scratchpad memory, a 4 kB RAM is available. The RAM is organized as a 1
k x 32 bit array.
4.2.1 CPU Memory Map and Interrupts
When the device comes out of power-on-reset, the data memories are mapped to the processor as
follows:
4.2.1.1 Memory Map (After Reset Operation)
Address Size Module
0x0000_0000 – 0x0000_FFFF In 16 repeated blocks of 4K each 16 X 4K Boot ROM
0x0001_0000 – 0x0001_7FFF 32K Program Flash
0x0001_8800 – 0x0001_8FFF 2K Data Flash
0x0001_9000 – 0x0001_9FFF 4K Data RAM
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4.2.1.2 Memory Map (Normal Operation)
Just before the boot ROM program gives control to FLASH program, the ROM configures the memory as
follows:
Address Size Module
0x0000_0000 – 0x0000_7FFF 32K Program Flash
0x0001_0000 – 0x0001_AFFF 4K Boot ROM
0x0001_8800 – 0x0001_8FFF 2K Data Flash
0x0001_9000 – 0x0001_9FFF 4K Data RAM
4.2.1.3 Memory Map (System and Peripherals Blocks)
Address Size Module
0x0002_0000 - 0x0002_00FF 256 Loop Mux
0x0003_0000 - 0x0003_00FF 256 Fault Mux
0x0004_0000 - 0x0004_00FF 256 ADC
0x0005_0000 - 0x0005_00FF 256 DPWM 3
0x0006_0000 - 0x0006_00FF 256 Filter 2
0x0007_0000 - 0x0007_00FF 256 DPWM 2
0x0008_0000 - 0x0008_00FF 256 Front End/Ramp I/F 2
0x0009_0000 - 0x0009_00FF 256 Filter 1
0x000A_0000 - 0x000A_00FF 256 DPWM 1
0x000B_0000 – 0x000B_00FF 256 Front End/Ramp I/F 1
0x000C_0000 - 0x000C_00FF 256 Filter 0
0x000D_0000 - 0x000D_00FF 256 DPWM 0
0x000E_0000 - 0x000E_00FF 256 Front End/Ramp I/F 0
0xFFF7_EC00 - 0xFFF7_ECFF 256 UART 0
0xFFF7_ED00 - 0xFFF7_EDFF 256 UART 1
0xFFF7_F000 - 0xFFF7_F0FF 256 Miscellaneous Analog Control
0xFFF7_F600 - 0xFFF7_F6FF 256 PMBus Interface
0xFFF7_FA00 - 0xFFF7_FAFF 256 GIO
0xFFF7_FD00 - 0xFFF7_FDFF 256 Timer
0xFFFF_FD00 - 0xFFFF_FDFF 256 MMC
0xFFFF_FE00 - 0xFFFF_FEFF 256 DEC
0xFFFF_FF20 - 0xFFFF_FF37 23 CIM
0xFFFF_FF40 - 0xFFFF_FF50 16 PSA
0xFFFF_FFD0 - 0xFFFF_FFEC 28 SYS
The registers and bit definitions inside the System and Peripheral blocks are detailed in the programmer’s
guide for each peripheral.
4.2.2 Boot ROM
The UCD3138 incorporates a 4k boot ROM. This boot ROM includes support for:
• Program download through the PMBus
• Device initialization
• Examining and modifying registers and memory
• Verifying and executing program FLASH automatically
• Jumping to a customer defined boot program
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The Boot ROM is entered automatically on device reset. It initializes the device and then performs
checksums on the Program FLASH. If the first 2 kB of program FLASH has a valid checksum, the
program jumps to location 0 in the Program FLASH. This permits the use of a customer boot program. If
the first checksum fails, it performs a checksum on the complete 32 kB of program flash. If this is valid, it
also jumps to location 0 in the program flash. This permits full automated program memory checking,
when there is no need for a custom boot program.
If neither checksum is valid, the Boot ROM stays in control, and accepts commands via the PMBus
interface
These functions can be used to read and write to all memory locations in the UCD3138. Typically they are
used to download a program to Program Flash, and to command its execution
4.2.3 Customer Boot Program
As described above, it is possible to generate a user boot program using 2 kB or more of the Program
Flash. This can support things which the Boot ROM does not support, including:
• Program download via UART – useful especially for applications where the UCD3138 is isolated from
the host (e.g., PFC)
• Encrypted download – useful for code security in field updates.
4.2.4 Flash Management
The UCD3138 offers a variety of features providing for easy prototyping and easy flash programming. At
the same time, high levels of security are possible for production code, even with field updates. Standard
firmware will be provided for storing multiple copies of system parameters in data flash. This is minimizes
the risk of losing information if programming is interrupted.
4.3 System Module
The System Module contains the interface logic and configuration registers to control and configure all the
memory, peripherals and interrupt mechanisms. The blocks inside the system module are the address
decoder, memory management controller, system management unit, central interrupt unit, and clock
control unit.
4.3.1 Address Decoder (DEC)
The Address Decoder generates the memory selects for the FLASH, ROM and RAM arrays. The memory
map addresses are selectable through configurable register settings. These memory selects can be
configured from 1 kB to 16 MB. Power on reset uses the default addresses in the memory map for ROM
execution, which is then configured by the ROM code to the application setup. During access to the DEC
registers, a wait state is asserted to the CPU. DEC registers are only writable in the ARM privilege mode
for user mode protection.
4.3.2 Memory Management Controller (MMC)
The MMC manages the interface to the peripherals by controlling the interface bus for extending the read
and write accesses to each peripheral. The unit generates eight peripheral select lines with 1 kB of
address space decoding.
4.3.3 System Management (SYS)
The SYS unit contains the software access protection by configuring user privilege levels to memory or
peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal
address or access conditions. A clock control setup for the processor clock (MCLK) speed, is also
available.
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4.3.4 Central Interrupt Module (CIM)
The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor
supports two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides
hardware expansion of interrupts by use of FIQ/IRQ vector registers for providing the offset index in a
vector table. This numerical index value indicates the highest precedence channel with a pending interrupt
and is used to locate the interrupt vector address from the interrupt vector table. Interrupt channel 0 has
the lowest precedence and interrupt channel 31 has the highest precedence. To remove the interrupt
request, the firmware should clear the request as the first action in the interrupt service routine. The
request channels are maskable, allowing individual channels to be selectively disabled or enabled.
Table 4-1. Interrupt Priority Table
NAME MODULE COMPONENT OR DESCRIPTION PRIORITY REGISTER
BRN_OUT_INT Brownout Brownout interrupt 0 (Lowest)
EXT_INT External Interrupts Interrupt on external input pin 1
WDRST_INT Watchdog Control Interrupt from watchdog exceeded (reset) 2
WDWAKE_INT Watchdog Control Wakeup interrupt when watchdog equals half of set 3 watch time
SCI_ERR_INT UART or SCI Control UART or SCI error Interrupt. Frame, parity or overrun 4
SCI_RX_0_INT UART or SCI Control UART0 RX buffer has a byte 5
SCI_TX_0_INT UART or SCI Control UART0 TX buffer empty 6
SCI_RX_1_INT UART or SCI Control UART1 RX buffer has a byte 7
SCI_TX_1_INT UART or SCI Control UART1 TX buffer empty 8
PMBUS_INT PMBus related interrupt 9
DIG_COMP_INT 12-bit ADC Control Digital comparator interrupt 10
“Prebias complete”, “Ramp Delay Complete”, “Ramp
FE0_INT Front End 0 Complete”, “Load Step Detected”, 11
“Over-Voltage Detected”, “EADC saturated”
“Prebias complete”, “Ramp Delay Complete”, “Ramp
FE1_INT Front End 1 Complete”, “Load Step Detected”, 12
“Over-Voltage Detected”, “EADC saturated”
“Prebias complete”, “Ramp Delay Complete”, “Ramp
FE2_INT Front End 2 Complete”, “Load Step Detected”, 13
“Over-Voltage Detected”, “EADC saturated”
PWM3_INT 16-bit Timer PWM 3 16-bit Timer PWM3 counter overflow or compare interrupt 14
PWM2_INT 16-bit Timer PWM 2 16-bit Timer PWM2 counter Overflow or compare 15 interrupt
PWM1_INT 16-bit Timer PWM 1 16-bit Timer PWM1 counter overflow or compare interrupt 16
PWM0_INT 16-bit timer PWM 0 16-bit Timer PWM1 counter overflow or compare interrupt 17
OVF24_INT 24-bit Timer Control 24-bit Timer counter overflow interrupt 18
CAPTURE_1_INT 24-bit Timer Control 24-bit Timer capture 1 interrupt 19
COMP_1_INT 24-bit Timer Control 24-bit Timer compare 1 interrupt 20
CAPTURE_0_INT 24-bit Timer Control 24-bit Timer capture 0 interrupt 21
COMP_0_INT 24-bit Timer Control 24-bit Timer compare 0 interrupt 22
CPCC_INT Constant Power Constant Current Mode switched in CPCC module Flag needs to be read 23 for details
ADC_CONV_INT 12-bit ADC Control ADC end of conversion interrupt 24
Analog comparator interrupts, Over-Voltage detection,
FAULT_INT Fault Mux Interrupt Under-Voltage detection, 25
LLM load step detection
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Error ADC
(Front End)
Filter
Digital
PWM
EAP
EAN
DPWMA
DPWMB
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Table 4-1. Interrupt Priority Table (continued)
NAME MODULE COMPONENT OR DESCRIPTION PRIORITY REGISTER
DPWM3 DPWM3 Same as DPWM1 26
DPWM2 DPWM2 Same as DPWM1 27
1) Every (1-256) switching cycles
DPWM1 DPWM1 2) Fault Detection 28
3) Mode switching
DPWM0 DPWM0 Same as DPWM1 29
EXT_FAULT_INT External Faults Fault pin interrupt 30
SYS_SSI_INT System Software System software interrupt 31 (highest)
4.4 Peripherals
4.4.1 Digital Power Peripherals
At the core of the UCD3138 controller are 3 Digital Power Peripherals (DPP). Each DPP can be
configured to drive from one to eight DPWM outputs. Each DPP consists of:
• Differential input error ADC (EADC) with sophisticated controls
• Hardware accelerated digital 2-pole/2-zero PID based compensator
• Digital PWM module with support for a variety of topologies
These can be connected in many different combinations, with multiple filters and DPWMs. They are
capable of supporting functions like input voltage feed forward, current mode control, and constant
current/constant power, etc.. The simplest configuration is shown in the following figure:
4.4.1.1 Front End
Figure 4-1 shows the block diagram of the front end module. It consists of a differential amplifier, an
adjustable gain error amplifier, a high speed flash analog to digital converter (EADC), digital averaging
filters and a precision high resolution set point DAC reference. The programmable gain amplifier in concert
with the EADC and the adjustable digital gain on the EADC output work together to provide 9 bits of range
with 6 bits of resolution on the EADC output. The output of the Front End module is a 9 bit sign extended
result with a gain of 1 LSB / mV. Depending on the value of AFE selected, the resolution of this output
could be either 1, 2, 4 or 8 LSBs. In addition Front End 0 has the ability to automatically select the AFE
value such that the minimum resolution is maintained that still allows the voltage to fit within the range of
the measurement. The EADC control logic receives the sample request from the DPWM module for
initiating an EADC conversion. EADC control circuitry captures the EADC-9-bit-code and strobes the
digital compensator for processing of the representative error. The set point DAC has 10 bits with an
additional 4 bits of dithering resulting in an effective resolution of 14 bits. This DAC can be driven from a
variety of sources to facilitate things like soft start, nested loops, etc. Some additional features include the
ability to change the polarity of the error measurement and an absolute value mode which automatically
adds the DAC value to the error.
It is possible to operate the controller in a peak current mode control configuration. In this mode topologies
like the phase shifted full bridge converter can be controlled to maintain transformer flux balance. The
internal DAC can be ramped at a synchronously controlled slew rate to achieve a programmable slope
compensation. This eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward
performance. A0 is a unity gain buffer used to isolate the peak current mode comparator. The offset of this
buffer is specified in the Electrical Characteristics table.
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EAP0
EAN0
DAC0
EADC
4 bit dithering gives 14 bits of effective resolution
97.65625 μV/LSB effective resolution
X
6 bit ADC
8 mV/LSB
Signed 9 bit result
(error) 1 mV /LSB
AFE_GAIN
10 bit DAC
1.5625 mV/LSB Value
Dither
S
CPCC
Filter x
Ramp
SAR/Prebias
Absolute Value
Calculation
Averaging
10 bit result
1.5625 mV/LSB
2
3-AFE_GAIN
Peak Current Mode
Comparator
Peak Current
Detected
A0
2
AFE_GAIN
IOFFSET
REA
EAP
EAN
AGND
AGND
IOFFSET
REA
Front End Differential
Amplifier
UCD3138
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Figure 4-1. Input Stage of EADC Module
Figure 4-2. Front End Module
4.4.1.2 DPWM Module
The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B.
Multiple DPWM modules within the UCD3138 system can be configured to support all key power
topologies. DPWM modules can be used as independent DPWM outputs, each controlling one power
supply output voltage rail. It can also be used as a synchronized DPWM—with user selectable phase shift
between the DPWM channels to control power supply outputs with multiphase or interleaved DPWM
configurations.
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The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse
width modulated outputs for the power stage switches. The compensator calculates the necessary duty
ratio as a 24-bit number in Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value
within the range 0.0 to 1.0. This duty ratio value is used to generate the corresponding DPWM output ON
time. The resolution of the DPWM ON time is 250 psec.
Each DPWM module can be synchronized to another module or to an external sync signal. An input
SYNC signal causes a DPWM ramp timer to reset. The SYNC signal outputs—from each of the four
DPWM modules—occur when the ramp timer crosses a programmed threshold. In this way the phase of
the DPWM outputs for multiple power stages can be tightly controlled.
The DPWM logic is probably the most complex of the Digital Peripherals. It takes the output of the
compensator and converts it into the correct DPWM output for several power supply topologies. It
provides for programmable dead times and cycle adjustments for current balancing between phases. It
controls the triggering of the EADC. It can synchronize to other DPWMs or to external sources. It can
provide synchronization information to other DPWMs or to external recipients. In addition, it interfaces to
several fault handling circuits. Some of the control for these fault handling circuits is in the DPWM
registers. Fault handling is covered in the Fault Mux section.
Each DPWM module supports the following features:
• Dedicated 14 bit time-base with period and frequency control
• Shadow period register for end of period updates.
• Quad-event control registers (A and B, rising and falling) (Events 1-4)
– Used for on/off DPWM duty ratio updates.
• Phase control relative to other DPWM modules
• Sample trigger placement for output voltage sensing at any point during the DPWM cycle.
• Support for 2 independent edge placement DPWM outputs (same frequency or period setting)
• Dead-time between DPWM A and B outputs
• High Resolution capabilities – 250 ps
• Pulse cycle adjustment of up to ±8.192 μs ( 32768 × 250 ps)
• Active high/ active low output polarity selection
• Provides events to trigger both CPU interrupts and start of ADC12 conversions.
4.4.1.3 DPWM Events
Each DPWM can control the following timing events:
1. Sample Trigger Count–This register defines where the error voltage is sampled by the EADC in
relationship to the DPWM period. The programmed value set in the register should be one fourth of the
value calculated based on the DPWM clock. As the DCLK (DCLK = 62.5 MHz max) controlling the
circuitry runs at one fourth of the DPWM clock (PCLK = 250MHz max). When this sample trigger count
is equal to the DPWM Counter, it initiates a front end calculation by triggering the EADC, resulting in a
CLA calculation, and a DPWM update. Over-sampling can be set for 2, 4 or 8 times the sampling rate.
2. Phase Trigger Count–count offset for slaving another DPWM (Multi-Phase/Interleaved operation).
3. Period–low resolution switching period count. (count of PCLK cycles)
4. Event 1–count offset for rising DPWM A event. (PCLK cycles)
5. Event 2–DPWM count for falling DPWM A event that sets the duty ratio. Last 4 bits of the register are
for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
6. Event 3–DPWM count for rising DPWM B event. Last 4 bits of the register are for high resolution
control. Upper 14 bits are the number of PCLK cycle counts.
7. Event 4–DPWM count for falling DPWM B event. Last 4 bits of the register are for high resolution
control. Upper 14 bits are the number of PCLK cycle counts.
8. Cycle Adjust–Constant offset for Event 2 and Event 4 adjustments.
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Start of Period
Period Counter
Start of Period
Period
Sample Trigger 1
DPWM Output A
Cycle Adjust A (High Resolution)
Event 2 (High Resolution)
Event 1
Event 3 (High Resolution)
Cycle Adjust B (High Resolution)
Event 4 (High Resolution)
DPWM Output B
Blanking A Begin
Blanking A End
Blanking B Begin
Blanking B End
Phase Trigger
Sample Trigger 2
To Other
Modules
To Other
Modules
Multi Mode Open Loop
Events which change with DPWM mode:
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 2 + Cycle Adjust A
DPWM B Rising Edge = Event 3
DPWM B Falling Edge = Event 4 + Cycle Adjust B
Phase Trigger = Phase Trigger Register value
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin,
Blanking B End
UCD3138
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Basic comparisons between the programmed registers and the DPWM counter can create the desired
edge placements in the DPWM. High resolution edge capability is available on Events 2, 3 and 4.
The drawing above is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely
by its own registers, not by the filter output. In other words, the power supply control loop is not closed.
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The Sample Trigger signals are used to trigger the Front End to sample input signals. The Blanking
signals are used to blank fault measurements during noisy events, such as FET turn on and turn off.
Additional DPWM modes are described below.
4.4.1.4 High Resolution DPWM
Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of
PWM edges, the UCD3138 DPWM can generate waveforms with resolutions as small as 250 ps. This is
16 times the resolution of the clock driving the DPWM module.
This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz
each. The high resolution section of DPWM can be enabled or disabled, also the resolution can be defined
in several steps between 4ns to 250ps. This is done by setting the values of PWM_HR_MULTI_OUT_EN ,
HIRES_SCALE and ALL_PHASE_CLK_ENA inside the DPWM Control Register 1. See the Power
Peripherals programmer’s manual for details.
4.4.1.5 Over Sampling
The DPWM module has the capability to trigger an over sampling event by initiating the EADC to sample
the error voltage. The default “00” configuration has the DPWM trigger the EADC once based on the
sample trigger register value. The over sampling register has the ability to trigger the sampling 2, 4 or 8
times per PWM period. Thus the time the over sample happens is at the divide by 2, 4, or 8 time set in the
sampling register. The “01” setting triggers 2X over sampling, the “10” setting triggers 4X over sampling,
and the “11” triggers over sampling at 8X.
4.4.1.6 DPWM Interrupt Generation
The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in
the period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower
interrupt service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12
trigger for sequence synchronization. Table 4-2 outlines the divide ratios that can be programmed.
4.4.1.7 DPWM Interrupt Scaling/Range
Table 4-2. DPWM Interrupt Divide Ratio
Interrupt Divide Interrupt Divide Interrupt Divide Switching Period Number of 32 MHz Setting Count Count (hex) Frames (assume 1MHz Processor Cycles loop)
1 0 00 1 32
2 1 01 2 64
3 3 03 4 128
4 7 07 8 256
5 15 0F 16 512
6 31 1F 32 1024
7 47 2F 48 1536
8 63 3F 64 2048
9 79 4F 80 2560
10 95 5F 96 3072
11 127 7F 128 4096
12 159 9F 160 5120
13 191 BF 192 6144
14 223 DF 224 7168
15 255 FF 256 8192
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4.5 DPWM Modes of Operation
The DPWM is a complex logic system which is highly configurable to support several different power
supply topologies. The discussion below will focus primarily on waveforms, timing and register settings,
rather than on logic design.
The DPWM is centered on a period counter, which counts up from 0 to PRD, and then is reset and starts
over again.
The DPWM logic causes transitions in many digital signals when the period counter hits the target value
for that signal.
4.5.1 Normal Mode
In Normal mode, the Filter output determines the pulse width on DPWM A. DPWM B fits into the rest of
the switching period, with a dead time separating it from the DPWM A on-time. It is useful for buck
topologies, among others. Here is a drawing of the Normal Mode waveforms:
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Start of Period
Period Counter
Start of Period
Period
DPWM Output A
Cycle Adjust A (High Resolution)
Filter Duty (High Resolution)
Event 1
Event 3 – Event 2 (High Res)
Event 4 (High Res)
DPWM Output B
Blanking B Begin
Blanking B End
Phase Trigger
Sample Trigger 2
To Other
Modules
Normal Mode Closed Loop
Events which change with DPWM mode:
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 1 + Filter Duty + Cycle Adjust A + (Event 3 – Event 2)
DPWM B Falling Edge = Event 4
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Filter controlled edge
Sample Trigger 1
Blanking A Begin
Blanking A End
To Other
Modules
Adaptive Sample Trigger A
Adaptive Sample Trigger B
UCD3138
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Cycle adjust A can be used to adjust pulse widths on individual phases of a multi-phase system. This can
be used for functions like current balancing. The Adaptive Sample Triggers can be used to sample in the
middle of the on-time (for an average output), or at the end of the on-time (to minimize phase delay) The
Adaptive Sample Register provides an offset from the center of the on-time. This can compensate for
external delays, such as MOSFET and gate driver turn on times.
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Phase Shift
Phase Trigger = Phase Trigger Register value or Filter Duty
DPWM0 Start of Period
Period Counter
DPWM0 Start of Period
DPWM1 Start of Period
Period Counter
DPWM1 Start of Period
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Blanking A-Begin and Blanking A-End can be used to blank out noise from the MOSFET turn on at the
beginning of the period (DPWMA rising edge). Blanking B could be used at the turn off time of DPWMB.
The other edges are dynamic, so blanking is more difficult.
Cycle Adjust B has no effect in Normal Mode.
4.6 Phase Shifting
In most modes, it is possible to synchronize multiple DPWM modules using the phase shift signal. The
phase shift signal has two possible sources. It can come from the Phase Shift Register. This provides a
fixed value, which is useful for an interleaved PFC, for example.
The phase shift value can also come from the filter output. In this case, the changes in the filter output
causes changes in the phase relationship of two DPWM modules. This is useful for phase shifted full
bridge topologies.
The following figure shows the mechanism of phase shift:
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Adaptive Sample Trigger B
Start of Period
Period Counter
Start of Period
Period
Adaptive Sample Trigger A
DPWM Output A
Cycle Adjust A (High Resolution)
Filter Duty (High Resolution)
Event 1
To Other
Modules
Multi Mode Closed Loop
Events which change with DPWM mode:
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 3
DPWM B Falling Edge = Event 3 + Filter Duty + Cycle Adjust B
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Filter controlled edge
Event 3 (High Resolution)
Cycle Adjust B (High Resolution)
Filter Duty (High Resolution)
DPWM Output B
Blanking B Begin
Blanking B End
Phase Trigger
Sample Trigger 2
To Other
Modules
Sample Trigger 1
Blanking A Begin
Blanking A End
UCD3138
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4.7 DPWM Multiple Output Mode
Multi mode is used for systems where each phase has only one driver signal. It enables each DPWM
peripheral to drive two phases with the same pulse width, but with a time offset between the phases, and
with different cycle adjusts for each phase.
Here is a diagram for Multi-Mode:
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Event 2 and Event 4 are not relevant in Multi mode.
DPWMB can cross over the period boundary safely, and still have the proper pulse width, so full 100%
pulse width operation is possible. DPWMA cannot cross over the period boundary.
Since the rising edge on DPWM B is also fixed, Blanking B-Begin and Blanking B-End can be used for
blanking this rising edge.
And, of course, Cycle Adjust B is usable on DPWM B.
4.8 DPWM Resonant Mode
This mode provides a symmetrical waveform where DPWMA and DPWMB have the same pulse width. As
the switching frequency changes, the dead times between the pulses remain the same.
The equations for this mode are designed for a smooth transition from PWM mode to resonant mode, as
described in the LLC Example section. Here is a diagram of this mode:
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Start of Period
Period Counter
Start of Period
Filter Period
Adaptive Sample Trigger A
Sample Trigger 1
DPWM Output A
Filter Duty – Average Dead Time
Event 1
Event 3 - Event 2
Period Register – Event 4
DPWM Output B
Blanking A Begin
Blanking A End
Blanking B Begin
Blanking B End
Phase Trigger
Sample Trigger 2
To Other
Modules
To Other
Modules
Resonant Symmetrical Closed Loop
Events which change with DPWM mode:
Dead Time 1 = Event 3 – Event 2
Dead Time 2 = Event 1 + Period Register – Event 4)
Average Dead Time = (Dead Time 1 + Dead Time 2)/2
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 1 + Filter Duty – Average Dead Time
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 1 + Filter Duty – Average Dead Time + (Event 3 – Event 2)
DPWM B Falling Edge = Filter Period – (Period Register – Event 4)
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin,
Blanking B End
Filter controlled edge
Adaptive Sample Trigger B
UCD3138
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The Filter has two outputs, Filter Duty and Filter Period. In this case, the Filter is configured so that the
Filter Period is twice the Filter Duty. So if there were no dead times, each DPWM pin would be on for half
of the period. For dead time handling, the average of the two dead times is subtracted from the Filter Duty
for both DPWM pins. Therefore, both pins will have the same on-time, and the dead times will be fixed
regardless of the period. The only edge which is fixed relative to the start of the period is the rising edge of
DPWM A. This is the only edge for which the blanking signals can be used easily.
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Start of Period
Period Counter
Start of Period
Period
Sample Trigger 1
DPWM Output A
Filter Duty/2 (High Resolution)
Period/2
DPWM Output B
Blanking A Begin
Blanking A End
Blanking B Begin
Blanking B End
Phase Trigger
Sample Trigger 2
To Other
Modules
To Other
Modules
Triangular Mode Closed Loop
Events which change with DPWM mode:
DPWM A Rising Edge = None
DPWM A Falling Edge = None
Adaptive Sample Trigger = None
DPWM B Rising Edge = Period/2 - Filter Duty/2 + Cycle Adjust A
DPWM B Falling Edge = Period/2 + Filter Duty/2 + Cycle Adjust B
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Filter controlled edge
Cycle Adjust A (High Resolution)
Cycle Adjust B (High Resolution)
UCD3138
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4.9 Triangular Mode
Triangular mode provides a stable phase shift in interleaved PFC and similar topologies. In this case, the
PWM pulse is centered in the middle of the period, rather than starting at one end or the other. In
Triangular Mode, only DPWM-B is available. Here is a diagram for Triangular Mode:
All edges are dynamic in triangular mode, so fixed blanking is not that useful. The adaptive sample trigger
is not needed. It is very easy to put a fixed sample trigger exactly in the center of the FET on-time,
because the center of the on-time does not move in this mode.
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4.10 Leading Edge Mode
Leading edge mode is very similar to Normal mode, reversed in time. The DPWM A falling edge is fixed,
and the rising edge moves to the left, or backwards in time, as the filter output increases. The DPWM B
falling edge stays ahead of the DPWMA rising edge by a fixed dead time. Here is a diagram of the
Leading Edge Mode:
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Start of Period
Period Counter
Start of Period
Period
Adaptive Sample Trigger B
Sample Trigger 1
DPWM Output A
Cycle Adjust A (High Resolution)
Filter Duty (High Resolution)
Event 1
Event 2 - Event 3 (High Resolution)
Event 4 (High Resolution)
DPWM Output B
Blanking A Begin
Blanking A End
Blanking B Begin
Blanking B End
Phase Trigger
Sample Trigger 2
To Other
Modules
To Other
Modules
Leading Edge Closed Loop
Events which change with DPWM mode:
DPWM A Falling Edge = Event 1
DPWM A Rising Edge = Event 1 - Filter Duty + Cycle Adjust A
Adaptive Sample Trigger A = Event 1 - Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 - Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 4
DPWM B Falling Edge = Event 1 - Filter Duty + Cycle Adjust A -(Event 2 – Event 3)
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Adaptive Sample Trigger A
UCD3138
SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com
As in the Normal mode, the two edges in the middle of the period are dynamic, so the fixed blanking
intervals are mainly useful for the edges at the beginning and end of the period.
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DPWM3B
(QT1)
DPWM2A
(QT2)
DPWM2B
(QB2)
VTrans
DPWM0B
(QSYN2,4)
DPWM1B
(QSYN1,3)
IPRI
DPWM3A
(QB1)
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
4.11 Sync FET Ramp and IDE Calculation
The UCD3138 has built in logic for controlling MOSFETs for synchronous rectification (Sync FETs). This
comes in two forms:
• Sync FET ramp
• Ideal Diode Emulation (IDE) calculation
When starting up a power supply, sometimes there is already a voltage on the output – this is called
prebias. It is very difficult to calculate the ideal Sync FET on-time for this case. If it is not calculated
correctly, it may pull down the pre-bias voltage, causing the power supply to sink current.
To avoid this, Sync FETs are not turned on until after the power supply has ramped up to the nominal
voltage. The Sync FETs are turned on gradually in order to avoid an output voltage glitch. The Sync FET
Ramp logic can be used to turn them on at a rate below the bandwidth of the filter.
In discontinuous mode, the ideal on-time for the Sync FETs is a function of Vin, Vout, and the primary side
duty cycle (D). The IDE logic in the UCD3138 takes Vin and Vout data from the firmware and combines it
with D data from the filter hardware. It uses this information to calculate the ideal on-time for the Sync
FETs.
4.12 Automatic Mode Switching
Automatic Mode switching enables the DPWM module to switch between modes automatically, with no
firmware intervention. This is useful to increase efficiency and power range. The following paragraphs
describe phase-shifted full bridge and LLC examples:
4.12.1 Phase Shifted Full Bridge Example
In phase shifted full bridge topologies, efficiency can be increased by using pulse width modulation, rather
than phase shift, at light load. This is shown below:
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Q1B
Q1T
QSR1
QSR2
fs< fr
fr
fs= fr_max fs> fr
PWM
Mode LLC Mode
Tr= 1/fr
Tr= 1/fr
ISEC(t )
SynFET Primary
QT1
QB1
Lr
ISOLATED
GATE Transformer SYNCHRONOUS
GATE DRIVE
PRIM
CURRENT
VOUT
+12V
T1
T1
ORING
CTL
VA
VBUS
QT2
QB2
D1
D2
T2
L1
Q5
C1 RL
C2
R2
Q6
Q7
I_SHARE
Vout
Iout
I_pri
temp
Vin
VA
UCD 3138
ARM7
FAULT 0
AD01
AD02/CMP0
AD03/CMP1/CMP2
AD04/CMP3
AD05/CMP4
AD00
AD06/CMP5
FAULT 1
FAULT 2
GPIO2
GPIO3
GPIO1
AD07/CMP6
AD08
AD09
DPWM0B
DPWM1B
DPWM2A
DPWM2B
ORING_CRTL
P_GOOD
DPWM3A
DPWM3B
Vout
ON/OFF
FAILURE
ACFAIL_OUT
ACFAIL_IN
I_pri
Iout
EADC0
EADC1
CLA0
CLA1
EADC2
DPWM0
DPWM1
DPWM2
DPWM3
Duty for mode
switching
Vref
Load Current
PCM
CBC
<
DPWM3A
DPWM3B
DPWM2A
DPWM2B
DPWM0B
DPWM1B
CPCC
PMBus
UART1
UART0
Primary
OSC
WD
RST
Memory
FAULT
Current
Sensing
I_pri
UCD3138
SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com
Figure 4-3. Secondary-Referenced Phase-Shifted Full Bridge Control
With Synchronous Rectification
4.12.2 LLC Example
In LLC, three modes are used. At the highest frequency, a pulse width modulated mode (Multi Mode) is
used. As the frequency decreases, resonant mode is used. As the frequency gets still lower, the
synchronous MOSFET drive changes so that the on-time is fixed and does not increase. In addition, the
LLC control supports cycle-by-cycle current limiting. This protection function operates by a comparator
monitoring the maximum current during the DPWMA conduction time. Any time this current exceeds the
programmable comparator reference the pulse is immediately terminated. Due to classic instability issues
associated with half-bridge topologies it is also possible to force DPWMB to match the truncated pulse
width of DPWMA. Here are the waveforms for the LLC:
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Q1T
CRES
CRES
LM
LK
Q1B
VBUS
VBUS
Transformer
COUT1
QSR1
QSR2
LRES
DPWM0A
DPWM0B
DPWM1A
DPWM1B
Driver
Driver
Driver
Driver
RS
RS1
RS2
CS
RF2 CF
RF1
RLRES
ESR1
COUT2
ESR2
EAP0
EAN0
NP
NS
NS
AD04
ADC13
EAP1
AD03
Oring Circuitry
VOUT
ILR(t)
ILM(t)
ISEC(t)
VCR(t)
VOUT(t)
Rectifier and filter
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
Figure 4-4. Secondary-Referenced Half-Bridge Resonant LLC Control
With Synchronous Rectification
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Filter Duty
Low – Lower Threshold
High – Lower Threshold
Control
Register 1
Auto Config High
Auto Config Mid
High – Upper Threshold
Low – Upper Threshold
0
Full Range
Automatic Mode Switching
With Hysteresis
UCD3138
SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com
4.12.3 Mechanism for Automatic Mode Switching
The UCD3138 allows the customer to enable up to two distinct levels of automatic mode switching. These
different modes are used to enhance light load operation, short circuit operation and soft start. Many of the
configuration parameters for the DPWM are in DPWM Control Register 1. For automatic mode switching,
some of these parameters are duplicated in the Auto Config Mid and Auto Config High registers.
If automatic mode switching is enabled, the filter duty signal is used to select which of these three
registers is used. There are 4 registers which are used to select the points at which the mode switching
takes place. They are used as shown below.
As shown, the registers are used in pairs for hysteresis. The transition from Control Register 1 to Auto
Config Mid only takes place when the Filter Duty goes above the Low Upper threshold. It does not go
back to Auto Config Mid until the Low Lower Threshold is passed. This prevents oscillation between
modes if the filter duty is close to a mode switching point.
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A ON SELECT
A OFF SELECT
B ON SELECT
B OFF SELECT
EGEN A
EGEN B
EDGE GEN
PWM A
PWM B
B SELECT
A SELECT
INTRAMUX
A/B/C (N)
A/B/C (N+1)
C (N+2)
C (N+3)
A(N)
B(N)
A(N+1)
B(N+1)
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
4.13 DPWMC, Edge Generation, IntraMux
The UCD3138 has hardware for generating complex waveforms beyond the simple DPWMA and DPWMB
waveforms already discussed – DPWMC, the Edge Generation Module, and the IntraMux.
DPWMC is a signal inside the DPWM logic. It goes high at the Blanking A begin time, and low at the
Blanking A end time.
The Edge Gen module takes DPWMA and DPWMB from its own DPWM module, and the next one, and
uses them to generate edges for two outputs. For DPWM3, the DPWM0 is considered to be the next
DPWM. Each edge (rising and falling for DPWMA and DPWMB) has 8 options which can cause it.
The options are:
0 = DPWM(n) A Rising edge
1 = DPWM(n) A Falling edge
2 = DPWM(n) B Rising edge
3 = DPWM(n) B Falling edge
4 = DPWM(n+1) A Rising edge
5 = DPWM(n+1) A Falling edge
6 = DPWM(n+1) B Rising edge
7 = DPWM(n+1) B Falling edge
Where “n" is the numerical index of the DPWM module of interest. For example n=1 refers to DPWM1.
The Edge Gen is controlled by the DPWMEDGEGEN register. It also has an enable/disable bit.
The IntraMux is controlled by the Auto Config registers. Intra Mux is short for intra multiplexer. The
IntraMux takes signals from multiple DPWMs and from the Edge Gen and combines them logically to
generate DPWMA and DPWMB signals This is useful for topologies like phase-shifted full bridge,
especially when they are controlled with automatic mode switching. Of course, it can all be disabled, and
DPWMA and DPWMB will be driven as described in the sections above. If the Intra Mux is enabled, high
resolution must be disabled, and DPWM edge resolution goes down to 4 ns.
Here is a drawing of the Edge Gen/Intra Mux:
Here is a list of the IntraMux modes for DPWMA:
0 = DPWMA(n) pass through (default)
1 = Edge-gen output, DPWMA(n)
2 = DPWNC(n)
3 = DPWMB(n) (Crossover)
4 = DPWMA(n+1)
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5 = DPWMB(n+1)
6 = DPWMC(n+1)
7 = DPWMC(n+2)
8 = DPWMC(n+3)
and for DPWMB:
0 = DPWMB(n) pass through (default)
1 = Edge-gen output, DPWMB(n)
2 = DPWNC(n)
3 = DPWMA(n) (Crossover)
4 = DPWMA(n+1)
5 = DPWMB(n+1)
6 = DPWMC(n+1)
7 = DPWMC(n+2)
8 = DPWMC(n+3)
The DPWM number wraps around just like the Edge Gen unit. For DPWM3 the following definitions apply:
DPWM(n) DPWM3
DPWM(n+1) DPWM0
DPWM(n+2) DPWM1
DPWM(n+3) DPWM2
4.14 Filter
The UCD3138 filter is a PID filter with many enhancements for power supply control. Some of its features
include:
• Traditional PID Architecture
• Programmable non-linear limits for automated modification of filter coefficients based on received
EADC error
• Multiple coefficient sets fully configurable by firmware
• Full 24-bit precision throughout filter calculations
• Programmable clamps on integrator branch and filter output
• Ability to load values into internal filter registers while system is running
• Ability to stall calculations on any of the individual filter branches
• Ability to turn off calculations on any of the individual filter branches
• Duty cycle, resonant period, or phase shift generation based on filter output.
• Flux balancing
• Voltage feed forward
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P
I 26
D
24
All are S0.23
24 +
24
Saturate Yn
S2.23 S0.23
24
Shifter
S0.23
24
Yn Scale
Clamp
S0.23
24
Filter Yn
Clamp High
Filter Yn
Clamp Low
Filter Yn
X
24
24
24
Ki_yn reg
Kp Coef
Xn-1 Reg
Xn 16
24
<>
9
9
16
24 24
24
24
24
24
Clamp
Kd yn_reg
Kd alpha
9
16
9 24
24
24
24
P
I
D
Limit Comparator
PID Filter Branch Stages
Ki High
EADC_DATA
9
9 9
9
24
32
Ki Coef
Kd coef
Limit 5
9
9
Limit 6
…..
Limit 0
Coefficient
select
Ki Low
Optional
Selected
by
KI_ADDER_
MODE
Clamp
X
X
X
+
-
+
+
Round
X X +1 n n –
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
Here is the first section of the Filter :
The filter input, Xn, generally comes from a front end. Then there are three branches, P, I. and D. Note
that the D branch also has a pole, Kd Alpha. Clamps are provided both on the I branch and on the D
alpha pole.
The filter also supports a nonlinear mode, where up to 7 different sets of coefficients can be selected
depending on the magnitude of the error input Xn. This can be used to increase the filter gain for higher
errors to improve transient response.
Here is the output section of the filter (S0.23 means that there is 1 sign bit, 0 integer bits and 23 fractional
bits).:
This section combines the P, I, and D sections, and provides for saturation, scaling, and clamping.
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18
24
14
38 18
KCompx
DPWMx Period
Loop_VFF
Filter YN (Duty %) Filter Duty
S0.23
14.0
14.0
14.0
14.0
S14.23
Resonant Duty 14.0
Round to
18 bits,
Clamp to
Positive
Clamp
Filter Output
Clamp High
Filter Output
Clamp Low
X 14.4 14.4
OUTPUT_MULT_SEL
14
Bits [17:4]
Filter Period
24
14
38 18
KCompx
DPWMx Period
Filter YN
S0.23
14.0 14.0
14.0
S14.23
Round to
18 bits,
Clamp to
Positive
Truncate
X low 4 bits
14.0
PERIOD_MULT_SEL
14.4
UCD3138
SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com
There is a final section for the filter, which permits its output to be matched to the DPWM:
This permits the filter output to be multiplied by a variety of correction factors to match the DPWM Period,
to provide for Voltage Feed Forward, or for other purposes. After this, there is another clamp. For resonant
mode, the filter can be used to generate both period and duty cycle.
4.14.1 Loop Multiplexer
The Loop Mux controls interconnections between the filters, front ends, and DPWMs. Any filter, front end,
and DPWM can be combined with each other in many configurations.
It also controls the following connections:
• DPWM to Front End
• Front End DAC control from Filters or Constant Current/Constant Power Module
• Filter Special Coefficients and Feed Forward
• DPWM synchronization
• Filter to DPWM
The following control modules are configured in the Loop Mux:
• Constant Power/Constant Current
• Cycle Adjustment (Current and flux balancing)
• Global Period
• Light Load (Burst Mode)
• Analog Peak Current Mode
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FAULT - CBC
FAULT - AB
FAULT -A
DCOMP– 4X
EXT GPIO– 4X
ACOMP– 7X
FAULT -B
FAULT MODULE
FAULT MODULE
FAULT MODULE
CYCLE BY CYCLE
AB FLAG
AB FLAG
A FLAG
B FLAG
FAULT MUX
ALL_FAULT_EN DPWM_EN
DPWM
CBC_FAULT_EN
CBC_PWM_AB_EN
FAULT MODULE
ANALOG PCM
Bit20 in DPWMCTRL0
Bit30 in DPWMFLTCTRL
Bit 31 in DPWMFLTCTRL Bit0 in DPWMCTRL0
DISABLE PWM A AND B
DISABLE PWM A AND B
DISABLE PWM A ONLY
DISABLE PWM B ONLY
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
4.14.2 Fault Multiplexer
In order to allow a flexible way of mapping several fault triggering sources to all the DPWMs channels, the
UCD3138 provides an extensive array of multiplexers that are united under the name Fault Mux module.
The Fault Mux Module supports the following types of mapping between all the sources of fault and all
different fault response mechanism inside each DPWM module.
• Many fault sources mapped to a single fault response mechanism. For instance an analog comparator
in charge of over voltage protection, a digital comparator in charge of over current protection and an
external digital fault pin can be all mapped to a fault-A signal connected to a single FAULT MODULE
and shut down DPWM1-A.
• A single fault source can be mapped to many fault response mechanisms inside many DPWM
modules. For instance an analog comparator in charge of over current protection can be mapped to
DPWM-0 through DPWM-3 by way of several fault modules.
• Many fault sources can be mapped to many fault modules inside many DPWM modules.
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CYCLE BY CYCLE
FAULT - CBC CLIM
FAULT MODULE
FAULT IN FAULT FLAG
MAX COUNT
FAULT EN
DPWM EN
UCD3138
SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com
The Fault Mux Module provides a multitude of fault protection functions within the UCD3138 high-speed
loop (Front End Control, Filter, DPWM and Loop Mux modules). The Fault Mux Module allows highly
configurable fault generation based on digital comparators, high-speed analog comparators and external
fault pins. Each of the fault inputs to the DPWM modules can be configured to one or any combination of
the fault events provided in the Fault Mux Module.
Each one of the DPWM engines has four fault modules. The modules are called CBC fault module, AB
fault module, A fault module and B fault module.
The internal circuitry in all the four fault modules is identical, and the difference between the modules is
limited to the way the modules are attached to the DPWMs.
All fault modules provide immediate fault detection but only once per DPWM switching cycle. Each one of
the fault modules own a separate max_count and the fault flag will be set only if sequential cycle-by-cycle
faults count exceeds max_count.
Once the fault flag is set DPWMs need to be disabled by DPWM_EN going low in order to clear the fault
flags. Please note, all four Fault Modules share the same DPWM_EN control, all fault flags (output of Fault
Modules) will be cleared simultaneously.
All four Fault Modules share the same global FAULT_EN as well. Therefore a specific Fault Module
cannot be enabled/ disabled separately.
Unlike Fault Modules, only one Cycle by Cycle block is available in each DPWM module.
The Cycle by Cycle block works in conjunction with CBC Fault Module and enables DPWM reaction to
signals arriving from Analog Peak current mode (PCM) module.
The Fault Mux Module supports the following basic functions:
• 4 digital comparators with programmable thresholds and fault generation
• Configuration for 7 high speed analog comparators with programmable thresholds and fault generation
• External GPIO detection control with programmable fault generation
• Configurable DPWM fault generation for DPWM Current Limit Fault, DPWM Over-Voltage Detection
Fault, DPWM A External Fault, DPWM B External Fault and DPWM IDE Flag
• Clock Failure Detection for High and Low Frequency Oscillator blocks
• Discontinuous Conduction Mode Detection
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Digital Comparator 0
Control
Digital Comparator 1
Control
Digital Comparator 2
Control
Digital Comparator 3
Control
Front End
Control 0
Front End
Control 1
Front End
Control 2
Analog
Comparator 0
Analog Comparator 0
Control
Analog
Comparator 1
Analog Comparator 1
Control
Analog
Comparator 2
Analog Comparator 2
Control
Analog
Comparator 3
Analog Comparator 3
Control
Analog
Comparator 4
Analog Comparator 4
Control
Analog
Comparator 5
Analog Comparator 5
Control
Analog
Comparator 6
Analog Comparator 6
Control
External GPIO
Detection
fault[2:0]
DPWM 0 DPWM 1 DPWM 2 DPWM 3
DPWM 0
Fault Control
DPWM 1
Fault Control
DPWM 2
Fault Control
DPWM 3
Fault Control
Analog Comparator
Automated Ramp
DCM Detection
HFO/LFO
Fail Detect
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
Figure 4-5. Fault Mux Block Diagram
4.15 Communication Ports
4.15.1 SCI (UART) Serial Communication Interface
A maximum of two independent Serial Communication Interface (SCI) or Universal Asynchronous
Receiver/Transmitter pre-scaler (UART) interfaces are included within the device for asynchronous startstop
serial data communication (see the pin out sections for details) Each interface has a 24 bit for
supporting programmable baud rates and has programmable data word and stop bit options. Half or full
duplex operation is configurable through register bits. A loop back feature can also be setup for firmware
verification. Both SCI-TX and SCI-RX pin sets can be used as GPIO pins when the peripheral is not being
used.
4.15.2 PMBUS
The PMBus Interface supports independent master and slave modes controlled directly by firmware
through a processor bus interface. Individual control and status registers enable firmware to send or
receive I2C, SMBus or PMBus messages in any of the accepted protocols, in accordance with the I2C
Specification, SMBus Specification (Version 2.0) and the PMBUS Power System Management Protocol
Specification.
The PMBus interface is controlled through a processor bus interface, utilizing a 32-bit data bus and 6-bit
address bus. The PMBus interface is connected to the expansion bus, which features 4 byte write
enables, a peripheral select dedicated for the PMBus interface, separated 32-bit data buses for reading
and writing of data and active-low write and output enable control signals. In addition, the PMBus Interface
connects directly to the I2C/SMBus/PMBus Clock, Data, Alert, and Control signals.
Example: PMBus Address Decode via ADC12 Reading
The user can allocate 2 pins of the 12-bit ADC input channels, AD_00 and AD_01, for PMBus address
decoding. At power-up the device applies IBIAS to each address detect pin and the voltage on that pin is
captured by the internal 12-bit ADC.
Where bin(VAD0x) is the address bin for one of 12 address as shown in Figure 4-6.
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Vdd
IBIAS
To ADC Mux
On/Off Control
AD00,
AD01
pin
Resistor to
set PMBus
Address
UCD3138
SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com
Figure 4-6. PMBus Address Detection Method
4.15.3 General Purpose ADC12
The ADC12 is a 12 bit, high speed analog to digital converter, equipped with the following options:
• Typical conversion speed of 267 ksps
• Conversions can consist from 1 to 16 ADC channel conversions in any desired sequence
• Post conversion averaging capability, ranging from 4X, 8X, 16X or 32X samples
• Configurable triggering for ADC conversions from the following sources: firmware, DPWM rising edge,
ADC_EXT_TRIG pin or Analog Comparator results
• Interrupt capability to embedded processor at completion of ADC conversion
• Six digital comparators on the first 6 channels of the conversion sequence using either raw ADC data
or averaged ADC data
• Two 10 μA current sources for excitation of PMBus addressing resistors
• Dual sample and hold for accurate power measurement
• Internal temperature sensor for temperature protection and monitoring
The control module ( ADC12 Contol Block Diagram) contains the control and conversion logic for autosequencing
a series of conversions. The sequencing is fully configurable for any combination of 16
possible ADC channels through an analog multiplexer embedded in the ADC12 block. Once converted,
the selected channel value is stored in the result register associated with the sequence number. Input
channels can be sampled in any desired order or programmed to repeat conversions on the same channel
multiple times during a conversion sequence. Selected channel conversions are also stored in the result
registers in order of conversion, where the result 0 register is the first conversion of a 16-channel
sequence and result 15 register is the last conversion of a 16-channel sequence. The number of channels
converted in a sequence can vary from 1 to 16.
Unlike EADC0 through EADC2, which are primarily designed for closing high speed compensation loops,
the ADC12 is not usually used for loop compensation purposes. The EADC converters have a
substantially faster conversion rate, thus making them more attractive for closed loop control. The ADC12
features make it best suited for monitoring and detection of currents, voltages, temperatures and faults.
Please see the Typical Characteristics plots for the temperature variation associated with this function.
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ADC
Channels
S/H
12-bit SAR
ADC
ADC12 Block
ADC12
Control
ADC Channel
ADC
Averaging
Digital
Comparators
DPWM
Modules
ADC12 Registers
Analog
Comparators
ADC External Trigger (from pin)
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
Figure 4-7. ADC12 Control Block Diagram
4.15.4 Timers
External to the Digital Power Peripherals there are 3 different types of timers in UCD3138. They are the
24-bit timer, 16-bit timer and the Watchdog timer
4.15.4.1 24-bit PWM Timer
There is one 24 bit counter PWM timer which runs off the Interface Clock and can further be divided down
by an 8-bit pre-scalar to generate a slower PWM time period. The timer has two compare registers (Data
Registers) for generating the PWM set/unset events. Additionally, the timer has a shadow register (Data
Buffer register) which can be used to store CPU updates of the compare events while still using the timer.
The selected shadow register update mode happens after the compare event matches.
The two capture pins TCMP0 and TCMP1 are inputs for recording a capture event. A capture event can
be set either to rising, falling, or both edges of the capture pin. Upon this event, the counter value is stored
in the corresponding capture data register.
The counter reset can be configured to happen on a counter roll over, a compare equal event, or by
software controlled register. Five Interrupts from the PWM timer can be set, which are the counter rollover
event (overflow), either capture event 0 or 1, or the two comparison match events. Each interrupt can be
disabled or enabled.
Upon an event comparison on only the second event, the TCMP pin can be configured to set, clear, toggle
or have no action at the output. The value of PWM pin output can be read for status or simply configured
as general purpose I/O for reading the value of the input at the pin. The first compare event can only be
used as an interrupt.
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4.15.4.2 16-Bit PWM Timers
There are four 16 bit counter PWM timers which run off the Interface Clock and can further be divided
down by a 8-bit pre-scaler to generate slower PWM time periods. Each timer has two compare registers
(Data Registers) for generating the PWM set/unset events. Additionally, each timer has a shadow register
(Data Buffer register) which can be used to store CPU updates of compare events while still using the
timer. The selected shadow register update mode happens after the compare event matches.
The counter reset can be configured to happen on a counter roll over, a compare equal event, or by a
software controlled register. Interrupts from the PWM timer can be set due to the counter rollover event
(overflow) or by the two comparison match events. Each comparison match and the overflow interrupts
can be disabled or enabled.
Upon an event comparison, the PWM pin can be configured to set, clear, toggle or have no action at the
output. The value of PWM pin output can be read for status or simply configured as General Purpose I/O
for reading the value of the input at the pin.
4.15.4.3 Watchdog Timer
A watchdog timer is provided on the device for ensuring proper firmware loop execution. The timer is
clocked off of a separate low speed oscillator source. If the timer is allowed to expire, a reset condition is
issued to the ARM processor. The watchdog is reset by a simple CPU write bit to the watchdog key
register by the firmware routine. On device power-up the watchdog is disabled. Yet after it is enabled, the
watchdog cannot be disabled by firmware. Only a device reset can put this bit back to the default disabled
state. A half timer flag is also provided for status monitoring of the watchdog.
4.16 Miscellaneous Analog
The Miscellaneous Analog Control (MAC) Registers are a catch-all of registers that control and monitor a
wide variety of functions. These functions include device supervisory features such as Brown-Out and
power saving configuration, general purpose input/output configuration and interfacing, internal
temperature sensor control and current sharing control.
The MAC module also provides trim signals to the oscillator and AFE blocks. These controls are usually
used at the time of trimming at manufacturing; therefore this document will not cover these trim controls.
The MAC registers and peripherals are all available in the UCD3138 (64 pin version). Other UCD3138
devices may have reduced resources. See the device pin out description for details.
4.17 Package ID Information
Package ID register includes information regarding the package type of the device and can be read by
firmware for reporting through PMBus or for other package sensitive decisions.
BIT NUMBER 1:0
Bit Name PKG_ID
Access R/W
Default 0 – UCD3138RGC, 1 – UCD3138RHA
4.18 Brownout
Brownout function is used to determine if the device supply voltage is lower than a threshold voltage, a
condition that may be considered unsafe for proper operation of the device.
The brownout threshold is higher than the reset threshold voltage; therefore, when the supply voltage is
lower than brownout threshold, it still does not necessarily trigger a device reset.
The brownout interrupt flag can be polled or alternatively can trigger an interrupt to service such case by
an interrupt service routine. Please see the Power On Reset (POR) / Brown Out Reset (BOR) section.
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4.19 Global I/O
Up to 30 pins in UCD3138 can be configured to serve as a general purpose input or output pin (GPIO).
This includes all digital input or output pins except for the RESET pin.
The pins that cannot be configured as GPIO pins are the supply pins, ground pins, ADC-12 analog input
pins, EADC analog input pins and the RESET pin.
There are two ways to configure and use the digital pins as GPIO pins:
1. Through the centralized Global I/O control registers.
2. Through the distributed control registers in the specific peripheral that shares it pins with the standard
GPIO functionality.
The Global I/O registers offer full control of:
1. Configuring each pin as a GPIO.
2. Setting each pin as input or output.
3. Reading the pin’s logic state, if it is configured as an input pin.
4. Setting the logic state of the pin, if it is configured as an output pin.
5. Connecting pin/pins to high rail through internal pull up resistors.
The Global I/O registers include Global I/O EN register, Global I/O OE Register, Global I/O Open Drain
Control Register, Global I/O Value Register and Global I/O Read Register.
The following is showing the format of Global I/O EN Register (GLBIOEN) as an example:
BIT NUMBER 29:0
Bit Name GLOBAL_IO_EN
Access R/W
Default 00_0000_0000_0000_0000_0000_0000_0000
Bits 29-0: GLOBAL_IO_EN – This register enables the global control of digital I/O pins
0 = Control of IO is done by the functional block assigned to the IO (Default)
1 = Control of IO is done by Global IO registers.
PIN NUMBER
BIT PIN_NAME
UCD3138-64 PIN UCD3138-40 PIN
29 FAULT[3] 43 NA
28 ADC_EXT_TRIG 12, 26 8
27 TCK 37 21
26 TDO 38 20
25 TMS 40 24
24 TDI 39 23
23 SCI_TX[1] 29 NA
22 SCI_TX[0] 14 22
21 SCI_RX[1] 30 NA
20 SCI_RX[0] 13 23
19 TMR_CAP 12, 26, 41 8, 21
18 TMR_PWM[1] 32 NA
17 TMR_PWM[0] 12, 26, 31, 37 21
16 PMBUS-CLK 15 9
15 PMBUS-DATA 16 10
14 CONTROL 30 20
13 ALERT 29 19
12 EXT_INT 26, 34 NA
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Temperature
Sensor
Ch14
ADC 12
Temp Cal
UCD3138
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PIN NUMBER
BIT PIN_NAME
UCD3138-64 PIN UCD3138-40 PIN
11 FAULT[2] 42 25
10 FAULT[1] 36 23
9 FAULT[0] 35, 39 22
8 SYNC 12, 26,37 8, 21
7 DPWM3B 24 18
6 DPWM3A 23 17
5 DPWM2B 22 16
4 DPWM2A 21 15
3 DPWM1B 20 14
2 DPWM1A 19 13
1 DPWM0B 18 12
0 DPWM0A 17 11
4.20 Temperature Sensor Control
Temperature sensor control register provides internal temperature sensor enabling and trimming
capabilities. The internal temperature sensor is disabled as default.
Figure 4-8. Internal Temp Sensor
Temperature sensor is calibrated at room temperature (25 °C) via a calibration register value.
The temperature sensor is measured using ADC12 (via Ch14). The temperature is then calculated using a
mathematical formula involving the calibration register (this effectively adds a delta to the ADC
measurement).
The temperature sensor can be enabled or disabled.
4.21 I/O Mux Control
In different packages of UCD3138 several I/O functions are multiplexed and routed toward a single
physical pin. I/O Mux Control register may be used in order to choose a single specific functionality that is
desired to be assigned to a physical device pin for your application.
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EXT CAP
AD02
400 Ω
Digital
RSHARE
250 Ω
3.3 V
ISHARE
ADC12 and
CMP
ESD
ESD
3.2 kΩ 250 Ω
ESD
AD13
3.3V
SW2
SW1
SW3
3.3 V
ADC12 and
CMP
UCD3138
www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012
4.21.1 JTAG Use for I/O and JTAG Security
The UCD3138 provides a JTAG interface for debugging and for uploading data and programs. The pins
are multiplexed with other pins, and will not be available in certain topologies. For power supplies, other
debugging techniques (PMBus, UART, code instrumentation) are often superior to JTAG. Code
downloading is much faster via PMBus, or with a user boot program via UART. PMBus support is
available from TI. JTAG for debugging has limited support from TI’s Code Composer Studio. JTAG
parameter download may be supported by third parties.
4.22 Current Sharing Control
UCD3138 provides three separate modes of current sharing operation.
• Analog bus current sharing
• PWM bus current sharing
• Master/Slave current sharing
• AD02 has a special ESD protection mechanism that prevents the pin from pulling down the currentshare
bus if power is missing from the UCD3138
The simplified current sharing circuitry is shown in the drawing below:
Figure 4-9. Simplified Current Sharing Circuitry
CURRENT SHARING MODE FOR TEST ONLY, CS_MODE EN_SW1 EN_SW2 DPWM ALWAYS KEEP 00
Off or Slave Mode (3-state) 00 00 (default) 0 0 0
PWM Bus 00 01 1 0 ACTIVE
Off or Slave Mode (3-state) 00 10 0 0 0
Analog Bus or Master 00 11 0 1 0
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The period and the duty of 8-bit PWM current source and the state of the SW1 and SW2 switches can be
controlled through the current sharing control register (CSCTRL).
4.23 Temperature Reference
The temperature reference register (TEMPREF) provides the ADC12 count when ADC12 measures the
internal temperature sensor (channel 14) during the factory trim and calibration.
This information can be used by different periodic temperature compensation routines implemented in the
firmware. But it should not be overwritten by firmware, otherwise this factory written value will be lost.
58 Functional Overview Copyright © 2012, Texas Instruments Incorporated
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2 .2 μF
1 .0 μF
BPCAP
DGND
V33D
UCD3138
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5 IC Grounding and Layout Recommendations
• Two grounds are recommended: AGND (analog) and DGND (digital).
– AGND plane should be on a different layer than DGND, and right under the UCD3138 device.
– UCD3138 power pad should be tied to AGND plane by at least 4 vias
– AGND plane should be just large enough to connect to all required components.
– Power ground (PGND) can be independent or combined with DGND
– The power pad of the driver IC should be tied to DGND
• Both 3.3VD and 3.3VA should have a local 4.7μF capacitor placed as close as possible to the device
pins
• BPCAP decoupling (2.2 μF typically) MUST be connected to DGND
• All analog signal filter capacitors should be tied to AGND
– If the gate driver device, such as UCD27524 or UCD27511/7 driver is used, the filter capacitor for
the current sensing pin can be tied to DGND for easy layout
• All digital signals, such as GPIO, PMBus and PWM are referenced to DGND.
• The RESET pin capacitor (0.1μF) should be connected to either DGND or AGND locally. A 10kΩ pullup
resistor to 3.3V is recommended.
• All filter and decoupling capacitors should be placed close to UCD3138 as possible
– Resistor placement is less critical and can be moved a little further away
• The DGND and AGND net-short resistor MUST be placed right between one UCD3138’s DGND pin
and one AGND pin. Ground connections to the net short element should be made by a large via (or
multiple paralleled vias) for each terminal of the net-short element.
• If a gate driver device such as UCC27524 or UCC27511/7 is on the control card and there is a PGND
connection, a net-short resistor should be tied to the DGND plane and PGND plane by multiple vias. In
addition the net-short element should be close to the driver IC.
Copyright © 2012, Texas Instruments Incorporated IC Grounding and Layout Recommendations 59
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6 Tools and Documentation
The application firmware for UCD3138 is developed on Texas Instruments Code Composer Studio (CCS)
integrated development environment (v3.3 recommended).
Monitoring and Configuration of key device parameters and real time debug capabilities are offered
through Texas Instruments’ FUSION_DIGITAL_POWER_DESIGNER Graphical User Interface (GUI),
http://www.ti.com/tool/fusion_digital_power_designer.
The FUSION_DIGITAL_POWER_DESIGNER software application uses PMBus protocol to communicate
with the device over serial bus by way of a interface adaptor known as USB-TO-GPIO, available as an
EVM from Texas Instruments (http://www.ti.com/tool/usb-to-gpio).
The software application can also be used to program the devices, with a version of the tool known as
FUSION_MFR_GUI optimized for manufacturing environments (http://www.ti.com/tool/fusion_mfr_gui).
The FUSION_MFR_GUI tool supports multiple devices on a board, and includes built-in logging and
reporting capabilities.
In terms of reference documentation, the following 3 programmer’s manuals are available offering detailed
information regarding the application and usage of UCD3138 digital controller:
1. UCD3138 Digital Power Peripheral Programmer's Manual Key topics covered in this manual include:
– Digital Pulse Width Modulator (DPWM)
– Modes of Operation (Normal/Multi/Phase-shift/Resonant etc)
– Automatic Mode Switching
– DPWMC, Edge Generation & Intra-Mux
– Front End
– Analog Front End
– Error ADC or EADC
– Front End DAC
– Ramp Module
– Successive Approximation Register Module
– Filter
– Filter Math
– Loop Mux
– Analog Peak Current Mode
– Constant Current/Constant Power (CCCP)
– Automatic Cycle Adjustment
– Fault Mux
– Analog Comparators
– Digital Comparators
– Fault Pin functions
– DPWM Fault Action
– Ideal Diode Emulation (IDE), DCM Detection
– Oscillator Failure Detection
– Register Map for all of the above peripherals in UCD3138
2. UCD3138 Monitoring and Communications Programmer’s Manual
Key topics covered in this manual include:
– ADC12
– Control, Conversion, Sequencing & Averaging
– Digital Comparators
– Temperature Sensor
– PMBUS Addressing
– Dual Sample & Hold
– Miscellaneous Analog Controls (Current Sharing, Brown-Out, Clock-Gating)
– PMBUS Interface
– General Purpose Input Output (GPIO)
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– Timer Modules
– PMBus
– Register Map for all of the above peripherals in UCD3138
3. UCD3138 ARM and Digital System Programmer’s Manual
Key topics covered in this manual include:
– Boot ROM & Boot Flash
– BootROM Function
– Memory Read/Write Functions
– Checksum Functions
– Flash Functions
– Avoiding Program Flash Lock-Up
– ARM7 Architecture
– Modes of Operation
– Hardware/Software Interrupts
– Instruction Set
– Dual State Inter-working (Thumb 16-bit Mode/ARM 32-bit Mode)
– Memory & System Module
– Address Decoder, DEC (Memory Mapping)
– Memory Controller (MMC)
– Central Interrupt Module
– Register Map for all of the above peripherals in UCD3138
In addition to the tools and documentation described above, for the most up to date information regarding
evaluation modules, reference application firmware and application notes/design tips, please visit
http://www.ti.com/product/ucd3138.
Copyright © 2012, Texas Instruments Incorporated Tools and Documentation 61
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7 References
1. UCD3138 Digital Power Peripherals Programmer’s Manual (Literature Number:SLUU995)
2. UCD3138 Monitoring & Communications Programmer’s Manual (Literature Number:SLUU996)
3. UCD3138 ARM and Digital System Programmer’s Manual (Literature Number:SLUU994)
4. Code Composer Studio Development Tools v3.3 – Getting Started Guide, (Literature Number:
SPRU509H)
5. ARM7TDMI-S Technical Reference Manual
6. System Management Bus (SMBus) Specification
7. PMBusTM Power System Management Prototcol Specification (1)
(1) PMBus is a trademark of SMIF, Inc.
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2012) to Revision A Page
• Added Production Data statement to footnote and removed "Product Preview" banner ........................... 6
Changes from Revision A (March 2012) to Revision B Page
• Added Feature bullets ............................................................................................................. 6
• Changed "Dual Edge Modulation" to "Triangular Modulation" in Features section ................................. 6
• Changed "265 ksps" to "267 ksps" in Features section ................................................................... 6
• Clarified number of UARTs in Feature section ............................................................................... 6
• Changed "FDPP" to "DDP" throughout. ....................................................................................... 7
• Changed Total GPIO pin count for the UCD3138 40-pin device from "17" to "18" in the Product Selection
Matrix table. .......................................................................................................................... 8
• Changed "VREG" to "BP18" in conditions statement for Electrical Characteristics table. ....................... 16
• Changed EAP – EAN Error voltage digital resolution MIN values for AFE=3, AFE=2, AFE=1, AFE=0 from
0.95, 1.90, 3.72, and 7.3 respectively; to, 0.8, 1.7, 3.55, and 6.90 respectively. ....................................... 16
• Changed "VREG" to "BP18" in conditions statement for Electrical Characteristics table. ....................... 17
• Changed conditions for VOL and VOH specs in the Electrical Characteristics table ................................. 17
• Added TWD spec to Electrical Characteristics table ...................................................................... 17
• Changed "VREG" to "BP18" in conditions statement for Electrical Characteristics table. ....................... 18
• Changed "PWM" to "DPWM" in DPWM Module. ............................................................................ 29
• Changed "PWMA" and "PWMB" to "DPWMA" and "DPWMB" in . ...................................................... 34
• Changed waveforms graphic for "Phase Shifted Full Bridge Example" for clarification .......................... 41
• Added text to section LLC Example .......................................................................................... 42
• Changed typical conversion speed from "268 ksps" to "267 ksps" in the General Purpose ADC12
section. .............................................................................................................................. 52
• Added package ID information for the UCD3138RGC and UCD3138RHA devices. ................................. 54
• Added bullet "AD02 has a special ESD protection mechanism that prevents the pin from pulling down
the current-share bus if power is missing from the UCD3138" to Current Sharing Control. ..................... 57
• Added sub-bullet "The power pad of the driver IC should be tied to DGND" and changed capacitor value
from "0.1 μF" to "4.7 μF" in IC Grounding and Layout Recommendations ........................................... 59
• Added "Tools and Documentation" section ................................................................................. 60
• Changed " Mechanical Data" section to "References" section ......................................................... 62
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing
Pins Package Qty Eco Plan (2) Lead/
Ball Finish
MSL Peak Temp (3) Samples
(Requires Login)
UCD3138RGCR ACTIVE VQFN RGC 64 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
UCD3138RGCT ACTIVE VQFN RGC 64 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
UCD3138RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
UCD3138RHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
UCD3138RGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
UCD3138RGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
UCD3138RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
UCD3138RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCD3138RGCR VQFN RGC 64 2000 367.0 367.0 38.0
UCD3138RGCT VQFN RGC 64 250 210.0 185.0 35.0
UCD3138RHAR VQFN RHA 40 2500 367.0 367.0 38.0
UCD3138RHAT VQFN RHA 40 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jul-2012
Pack Materials-Page 2
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Copyright © 2012, Texas Instruments Incorporated
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 1 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
Power Electronics R&D Center
Wireless Connectivity
Panasonic Industrial Devices Europe GmbH
APPROVED
CHECKED
DESIGNED
Specification for Production
Panasonic Industrial Devices Europe GmbH
Zeppelinstrasse 19
21337 Lüneburg
Applicant / Manufacturer
Hardware
Germany
Not applikable
Applicant / Manufacturer
Software
Software Version
Not applikable
Contents
Approval for Mass Production
Customer
Bluetooth QDL ID
Qualified Design Listing (QDL) ID: B019784
As Controller Sub-System Listing for PAN13xx Series.
By purchase of any products described in this document the customer accepts the document's validity and declares their agreement and understanding of its contents and recommendations. Panasonic reserves the right to make changes as required without notification.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 2 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
TABLE OF CONTENTS
1 Scope of this Document..................................................................................................5
1.1 New PAN1315A, PAN1325A.................................................................................5
2 Key Features...................................................................................................................6
2.1 Software Block Diagram........................................................................................6
3 Applications for the Module.............................................................................................7
4 Description for the Module..............................................................................................7
5 Detailed Description........................................................................................................8
5.1 Terminal Layout.....................................................................................................8
5.1.1 5.1.1. Terminal Layout PAN131x without antenna...................................8
5.1.2 5.1.2. Terminal Layout PAN132x with antenna........................................9
5.2 Pin Description.....................................................................................................10
5.3 Device Power Supply...........................................................................................11
5.4 Clock Inputs.........................................................................................................12
6 Bluetooth Features........................................................................................................12
7 Block Diagram...............................................................................................................13
8 Test Conditions.............................................................................................................14
9 General Device Requirements and Operation..............................................................14
9.1 Absolute Maximum Ratings.................................................................................14
9.2 Recommended Operating Conditions..................................................................15
9.3 Current Consumption...........................................................................................15
9.4 General Electrical Characteristics........................................................................16
9.5 nSHUTD Requirements.......................................................................................16
9.6 External Digital Slow Clock Requirements (–20°C to +70°C)..............................16
10 Host Controller Interface...............................................................................................17
11 Audio/Voice Codec Interface.........................................................................................18
11.1 PCM Hardware Interface.....................................................................................18
11.2 Data Format.........................................................................................................18
11.3 Frame Idle Period................................................................................................19
11.4 Clock-Edge Operation.........................................................................................20
11.5 Two-Channel PCM Bus Example........................................................................20
11.6 Audio Encoding....................................................................................................20
11.7 Improved Algorithm For Lost Packets..................................................................21
11.8 Bluetooth/PCM Clock Mismatch Handling...........................................................21
11.9 Bluetooth Inter-IC Sound (I2S)............................................................................21
11.10Current Consumption for Different Bluetooth Scenarios......................................22
12 Bluetooth RF Performance............................................................................................22
13 Soldering Temperature-Time Profile (for reflow soldering)...........................................25
13.1 For lead solder.....................................................................................................25
13.2 For leadfree solder...............................................................................................26
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14 Module Dimension........................................................................................................27
14.1 Module Dimensions PAN131X without Antenna..................................................27
14.2 Module Dimensions PAN132X with Antenna.......................................................28
15 Footprint of the Module.................................................................................................29
15.1 Footprint PAN131x without antenna....................................................................29
15.2 Footprint PAN132x with antenna.........................................................................30
16 Labeling Drawing..........................................................................................................31
17 Mechanical Requirements.............................................................................................31
18 Recommended Foot Pattern.........................................................................................32
18.1 recommended foot pattern PAN131x without antenna........................................32
18.2 recommended foot pattern PAN132x with antenna.............................................33
19 Layout Recommendations with Antenna (PAN132x)....................................................34
20 Bluetooth LE (LOW ENERGY) PAN1316/26................................................................34
20.1 Network Topology................................................................................................34
20.2 module features...................................................................................................35
20.3 Current consumption for different LE scenarios..................................................36
21 ANT PAN1317/27..........................................................................................................36
21.1 Network topology.................................................................................................36
21.2 module features..................................................................................................37
21.3 ANT Current consumption...................................................................................37
22 Triple mode (BR/EDR + Bluetooth low energy + ANT) PAN1323................................38
22.1 Triple Mode Current consumption.......................................................................38
23 Development of Applications.........................................................................................39
23.1 Tools to be needed..............................................................................................39
24 List of Profiles...............................................................................................................40
25 Reliability Tests.............................................................................................................40
26 Cautions........................................................................................................................41
26.1 Design Notes.......................................................................................................41
26.2 Installation Notes.................................................................................................41
26.3 Usage Conditions Notes......................................................................................42
26.4 Storage Notes......................................................................................................42
26.5 Safety Cautions...................................................................................................43
26.6 Other cautions.....................................................................................................43
27 Packaging.....................................................................................................................44
27.1 Packaging of PAN131x without antenna.............................................................44
27.2 Packaging for PAN132x with antenna.................................................................47
28 Ordering Information.....................................................................................................48
29 RoHS Declaration.........................................................................................................49
30 Data Sheet Status.........................................................................................................49
31 History for this Document..............................................................................................50
32 Related Documents.......................................................................................................50
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33 General Information......................................................................................................52
34 Regulatory Information..................................................................................................52
34.1 FCC for US..........................................................................................................52
34.1.1 FCC Notice.............................................................................................52
34.1.2 Caution...................................................................................................53
34.1.3 Labeling Requirements..........................................................................53
34.1.4 Antenna Warning....................................................................................53
34.1.5 Approved Antenna List...........................................................................53
34.1.6 RF Exposure PAN13xx..........................................................................54
34.2 Industry Canada Certification..............................................................................54
34.3 European R&TTE Declaration of Conformity.......................................................54
34.4 NCC for Taiwan...................................................................................................56
34.4.1 Labeling Requirements..........................................................................56
34.4.2 NCC Statement......................................................................................56
34.5 Bluetooth SIG Statement.....................................................................................56
35 Life Support Policy........................................................................................................56
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1
SCOPE OF THIS DOCUMENT
This product specification describes Panasonic’s HCI, Class 1.5 , TI based, Bluetooth®1 modules, series number 13xx.
For detailed family overview that includes part numbers see Chapter 28, Ordering Information.
Non-antenna versions will be refered to as PAN131x, versions with antenna will be refered to as PAN132x in this document.
Fore information and features on Bluetooth Low Energy 4.0 refer to Chapter 19, for information on ANT refer to Chapter 21.
1.1
NEW PAN1315A, PAN1325A
The PAN1315A/1325A Series is based on Texas Instruments’ NEW CC2560A controller. A ROM update from Texas Instruments to the CC2560 IC has allowed Panasonic to improve PAN1315/1325 Series. The NEW PAN1315A/1325A Series Modules has increased power and system efficiency resulting from reduced initialization script size, start-up time and decreased system memory requirements.
Compatibility:
PAN1315, PAN1315A, PAN1316 and PAN1317 are 100% footprint compatible
PAN1325, PAN1325A, PAN1326 and PAN1327 are 100% footprint compatible
As an updated initialization script resident on the application microcontroller is required for modules based on the CC2560A, compatibility between the PAN1315/PAN1325 and PAN1315A/PAN1325A is dependant on the Bluetooth stack. Stacks are available that will operate with all PAN1315/1325 variations.
BT-Stack solutions provided by software development partners are available for most processors, including linux based host systems..
For detailed family overview that includes part numbers see Chapter 28 Ordering Information.
Contact your stack provider or local Panasonic sales company for currently available Bluetooth Profiles.
1 Bluetooth is a registered trademark of the Bluetooth Special Interest Group.
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2
KEY FEATURES
•
Bluetooth specification v2.1 + EDR (Enhanced Data Rate)
•
Surface mount type 6.5(9.5 w. Ant.) x 9.0 x 1.8 mm³
•
Up to 10.5dBm Tx power (typical) with transmit power control
•
High sensitivity (-93 dBm typ.)
•
Texas Instrument’s CC256X BlueLink 7.0 inside
•
Fast Connection Setup
•
Extended SCO Link
•
Supports convenient direct connection to battery (2.2-4.8 V), or connect to DC/DC (1.7-1.98 V) for improved power efficiency
•
Internal crystal oscillator (26MHz)
•
Fully shielded for immunity
•
Full Bluetooth data rate up to 2,178kbps asymmetric
•
Support for Bluetooth power saving modes (Sniff, Hold)
•
Support for very low-power modes (deep sleep and power down)
•
Optional support for ultra-low-power mode. Standby with Battery-Backup
•
PCM Interface Master / Slave supporting 13 or 16 bit linear, 8 bit μ-law or A-law Codecs and CVSD transcoders on up to 3 SCO channels
•
Full 8- to 128-bit encryption
•
UART, I²C and PCM Interface
•
IO operating voltage = 1.8 V nominal
•
3 Channel ADC and 1 Channel DAC
•
Bluetooth profiles such as SPP, A2DP and others are available. Refer to Panasonic’s RF module website for a listing of the most current releases.
•
Manufactured in conformance with RoHS
2.1
SOFTWARE BLOCK DIAGRAM
PAN13xxHost ProcessorApplicationBD/EDRBLEANTHCIL2CAPHCIRF BlockPAN13xxHost Block
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3
APPLICATIONS FOR THE MODULE
All Embedded Wireless Applications
•
Smart Phones
•
Cable Replacement
•
Industrial Control
•
Automotive
•
Medical
•
Access Points
•
Scanners
•
Consumer Electronics
•
Wireless Sensors
•
Monitoring and Control
•
Low Power
•
Access Points
4
DESCRIPTION FOR THE MODULE
The PAN1315 and PAN1315A are short-range, Class 1 or 2, HCI modules for implementing Bluetooth functionality into various electronic devices. A block diagram can be found in Chapter 7.
Communication between the module and the host controller is carried out via UART.
New designs can be completed quickly by mating the PAN13xx series modules with Texas Instruments’ MSP430BT5190 that contains Mindtree’s EtherMind Bluetooth Protocol Stack and serial port profile, additional computing power can be achieved by choosing TI’s Stellaris ARM7 controller that includes StoneStreet One's A2DP profile. Other BT profiles are available on custom development basis.
Additional controllers are also supported by the PAN13xx series by using a TI/Panasonic software development partner to port the Bluetooth stack and profiles. Mindtree's Software Development Kit (SDK) is available on TI's website -- www.ti.com/connectivity.com
Contact your local sales office for further details on additional options and services, by visiting www.panasonic.com/rfmodules or write an e-mail to wireless@eu.panasonic.com.
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5
DETAILED DESCRIPTION
5.1
TERMINAL LAYOUT
5.1.1
5.1.1. Terminal Layout PAN131x without antenna
No
Pin Name
Pull at Reset
Def. Dir. 2
I/O Type 3
Description of Options (Common)
1
GND
Connect to Ground
2
TX_DBG
PU
O
2 mA
Logger output
3
HCI_CTS
PU
I
8 mA
HCI UART clear-to-send.
4
HCI_RTS
PU
O
8 mA
HCI UART request-to-send.
5
HCI_RX
PU
I
8 mA
HCI UART data receive
6
HCI_TX
PU
O
8 mA
HCI UART data transmit
7
AUD_FSYNC
PD
IO
4 mA
PCM frame synch. (NC if not used) Fail safe4
8
SLOW_CLK_IN
I
32.768-kHz clock in Fail safe
9
NC
IO
Not connected
10
MLDO_OUT
O
Main LDO output (1.8 V nom.)
11
CL1.5_LDO_IN
I
PA LDO input
12
GND
Connect to Ground
13
RF
IO
Bluetooth RF IO
14
GND
Connect to Ground
15
MLDO_IN
I
Main LDO input
16
nSHUTD
PD
I
Shutdown input (active low).
17
AUD_OUT
PD
O
4 mA
PCM data output. (NC if not used) Fail safe
18
AUD_IN
PD
I
4 mA
PCM data input. (NC if not used) Fail safe
19
AUD_CLK
PD
IO
HY, 4 mA
PCM clock. (NC if not used) Fail safe
20
GND
Connect to Ground
21
NC
EEPROM I²C SDA (Internal)
22
VDD_IO
PI
I/O power supply 1.8 V Nom
23
NC
EEPROM I²C SCL (Internal)
24
NC
IO
Not connected
2 I = input; O = output; IO = bidirectional; P = power; PU = pulled up; PD = pulled down
3 I/O Type: Digital I/O cells. HY = input hysteresis, current = typ. output current
4 No signals are allowed on the IO pins if no VDD_IO (Pin 22) power supplied, except pin 7, 8, 17-19.
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5.1.2
5.1.2. Terminal Layout PAN132x with antenna
No
Pin Name
Pull at Reset
Def. Dir. 5
I/O Type 6
Description of Options (Common)
A
GND
Connect to Ground
B
GND
Connect to Ground
C
GND
Connect to Ground
D
GND
Connect to Ground
No 1-24 see above in Chapter 5.1.1. Except PIN 13 is not connected. For RF conducted measurements, either use the PAN1323ETU or de-solder the antenna and solder an antenna connector to the hot pin.
5 I = input; O = output; IO = bidirectional; P = power; PU = pulled up; PD = pulled down
6 I/O Type: Digital I/O cells. HY = input hysteresis, current = typ. output current
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5.2
PIN DESCRIPTION
Pin Name
No
ESD 7 (V)
Pull at Reset
Def. Dir. 8
I/O Type 9
Description of Options
Bluetooth IO SIGNALS
HCI_RX
5
750
PU
I
8 mA
HCI UART data receive
HCI_TX
6
750
PU
O
8 mA
HCI UART data transmit
HCI_RTS
4
750
PU
O
8 mA
HCI UART request-to-send.
HCI_CTS
3
750
PU
I
8 mA
HCI UART clear-to-send.
AUD_FYSNC
7
500
PD
IO
4 mA
PCM frame synch (NC if not used) Fail safe
AUD_CLK
19
500
PD
IO
HY, 4 mS
PCM clock (NC if not used) Fail safe
AUD_IN
18
500
PD
I
4 mA
PCM data input (NC if not used) Fail safe
AUD_OUT
17
500
PD
O
4 mA
PCM data output (NC if not used) Fail safe
Logger output
TX_DBG
2
1000
PU
O
2 mA
OPTION: nTX_DBG – logger out (low = 1)
CLOCK SIGNALS
SLOW_CLK_IN
8
1000
I
32.768-kHz clock in Fail safe
Bluetooth ANALOG SIGNALS
RF
13
1000
IO
Bluetooth RF IO (not connected with antenna)
nSHUTD
16
1000
PD
I
Shutdown input (active low).
Bluetooth POWER AND GND SIGNALS
VDD_IO
22
1000
PI
I/O power supply 1.8 V Nom
MLDO_IN
15
1000
I
Main LDO inputConnect directly to battery or to a pre-regulated 1.8-V supply
MLDO_OUT
10
1000
O
Main LDO output (1.8 V nom.) Can not be used as 1.8V supply due to internal connection to the RF part.
CL1.5_LDO_IN
11
1000
I
PA LDO input
Connect directly to battery or to a pre-regulated 1.8-V supply
GND
1
P
Connect to Ground
GND
12
P
Connect to Ground
GND
14
P
Connect to Ground
GND
20
P
Connect to Ground
EEPROM IO SIGNALS (EEPROM is optional in PAN13x product line)
NC
23
1000
PU/PD
I
HY, 4mA
EEPROM I²C SCL (Internal)
NC
21
1000
PU/PD
IO
HY, 4mA
EEPROM I²C IRQ (Internal)
Remark:
HCI_CTS is an input signal to the CC256X device:
- When HCI_CTS is low, then CC256X is allowed to send data to Host device.
- When HCI_CTS is high, then CC256X is not allowed to send data to Host device.
7 ESD: Human Body Model (HBM). JEDEC 22-A114
8 I = input; O = output; IO = bidirectional; P = power; PU = pulled up; PD = pulled down
9 I/O Type: Digital I/O cells. HY = input hysteresis, current = typ output current
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5.3
DEVICE POWER SUPPLY
The PAN13XX Bluetooth radio solution is intended to work in devices with a limited power budget such as cellular phones, headsets, hand-held PC’s and other battery-operated devices. One of the main differentiators of the PAN13XX is its power management – its ability to draw as little current as possible.
The PAN13XX device requires two kinds of power sources:
• Main power supply for the Bluetooth - VDD_IN = VBAT
• Power source for the 1.8 V I/O ring - VDD_IO
The PAN13XX includes several on-chip voltage regulators for increased noise immunity. The PAN13XX can be connected either directly to the battery or to an external 1.8-V DC to DC converter.
There are three ways to supply power:
•
Full-VBAT system:
Maximum RF output power, but not optimum system power:
•
Full-DC2DC system:
Lower RF output power, but optimum system power:
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•
Mixed DC2DC-VBAT system:
Maximum RF output power and optimum system power, but requires routing of VBAT:
5.4
CLOCK INPUTS
The slow clock is always supplied from an external source. It is connected to the SLOW_CLK_IN pin number 8 and can be a digital signal with peak to peak of 0-1.8 V.
The slow clock's frequency accuracy must be 32.768 kHz ±250 ppm for Bluetooth usage (according to the Bluetooth specification).
The Slow Clock 32.768 kHz is mandatory to start the internal controller, otherwise the module does not start up.
6
BLUETOOTH FEATURES
•
Support of Bluetooth2.1+EDR (Lisbon Release) up to HCI level.
•
Very fast AFH algorithm for both ACL and eSCO.
•
Supports typically 4 dBm Class 2 TX power w/o external PA, improving Bluetooth link robustness. Adjusting the host settings, the TX power can be increased to 10 dBm. However it is important, that the national regulations and Bluetooth specification are met.
•
Digital Radio Processor (DRP) single-ended 50 ohm.
•
Internal temperature detection and compensation ensures minimal variation in the RF performance over temperature.
•
Flexible PCM and I2S digital audio/voice interfaces: Full flexibility of data-format (Linear, a-Law, μ-Law), data-width, data order, sampling and slot positioning, master/slave modes, high clock rates up to 15 MHz for slave mode (or 4.096 MHz for Master Mode). Lost packet concealment for improved audio.
•
Proprietary low-power scan method for page and inquiry scans, achieves page and inquiry scans at 1/3rd normal power.
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7
BLOCK DIAGRAM
Note: The Slow Clock 32.768 kHz is mandatory, otherwise the module does not start up, refer to Chapter 5.4 for additional information.
Note: The IO are 1.8V driven and might need external level shifter and LDO. The MLDO_OUT PIN can not be used as reference due to RF internal connection.
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8
TEST CONDITIONS
Measurements shall be made under room temperature and humidity unless otherwise specified.
9
GENERAL DEVICE REQUIREMENTS AND OPERATION
Temperature 25 ± 10°C Humidity 40 to 85%RH SW-Patch V2.30 Supply Voltage 3.3V
All specifications are over temperature and process, unless indicated otherwise.
9.1
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted).
Note
All parameters are measured as follows unless stated otherwise:
VDD_IN 10 = 3.3 V, VDD_IO = 1.8 V.
No
See 11
Value
Unit
Ratings Over Operating Free-Air Temperature Range
1
VDD_IN
Supply voltage range
–0.5 to 5.5
V 12
2
VDDIO_1.8V
–0.5 to 2.145
V
3
Input voltage to RF (Pin 13)
–0.5 to 2.1
V
4
Operating ambient temperature range
–20 to 70
°C
5
Storage temperature range
–40 to 125
°C
6
Bluetooth RF inputs (Pin 13)
10
dBm
7
ESD: Human Body Model (HBM). JEDEC 22-A114
500
V
10 VDD_IN is supplied to MLDO_IN (Pin 15) and CL1.5_LDO_IN (Pin 11), other options are described in Chapter 5.3.
11 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
12 Maximum allowed depends on accumulated time at that voltage: VDD_IN is defined in Reference schematics. When DC2DC supply is used, maximum voltage into MLDO_OUT and LDO_IN = 2.145 V.
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9.2
RECOMMENDED OPERATING CONDITIONS
No
Rating
Condition
Symbol
Min
Max
Unit
1
Power supply voltage 13
VDD_IN
1.7
4.8
V
2
IO power supply voltage
VDD_IO
1.62
1.92
V
3
High-level input voltage
Default
VIH
0.65 x VDD_IO
VDD_IO
V
4
Low-level input voltage
Default
VIL
0
0.35 x VDD_IO
V
5
IO Input rise/fall times, 10% to 90% 14
Tr/Tf
1
10
ns
0 to 0.1 MHz
60
0.1 to 0.5 MHz
50
0.5 to 2.5 MHz
30
2.5 to 3.0 MHz
15
6
Maximum ripple on VDD_IN (Sine wave) for 1.8 V (DC2DC) mode
> 3.0 MHz
5
mVp-p
7
Voltage dips on VDD_IN (VBAT) (duration = 577 μs to2.31 ms, period = 4.6 ms)
400
mV
8
Maximum ambient operating temperature 15
70
°C
9
Minimum ambient operating temperature 16
-20
C
9.3
CURRENT CONSUMPTION
No
Characteristics
Min
25°C
Typ
25°C
Max
25°C
Min
-20°C
Typ
-20°C
Max
-20°C
Min
+70°C
Typ
+70°C
Max
+70°C
Unit
1
Current consumption in shutdown mode 17
1
3
7
μA
2
Current consumption in deep sleep mode 18
40
105
700
μA
3
Total IO current consumption for active mode
1
1
1
mA
4
Current consumption during transmit DH5 full throughput
40
mA
13 Excluding 1.98 < VDD_IN < 2.2 V range – not allowed.
14 Asynchronous mode.
15 The device can be reliably operated for 7 years at Tambient of 70°C, assuming 25% active mode and 75% sleep mode (15,400 cumulative active power-on hours).
16 The device can be reliably operated for 7 years at Tambient of 70°C, assuming 25% active mode and 75% sleep mode (15,400 cumulative active power-on hours).
17 Vbat + Vio
18 Vbat + Vio + Vsd (shutdown)
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9.4
GENERAL ELECTRICAL CHARACTERISTICS
No
Rating
Condition
Min
Max
Value
at 2/4/8 mA
0.8 x VDD_IO
VDD_IO
V
1
High-level output voltage, VOH
at 0.1 mA
VDD_IO – 0.2
VDD_IO
V
at 2/4/8 mA
0
0.2 x VDD_IO
V
2
Low-level output voltage, VOL
at 0.1 mA
0
0.2
V
Resistance
1
MΩ
3
IO input impedance
Capacitance
5
pF
4
Output rise/fall times,10% to 90% (Digital pins)
CL = 20 pF
10
Ns
PU
typ = 6.5
3.5
9.7
TX_DBG, us
PCM b
PD
typ = 27
9.5
55
μA
PU
typ = 100
100
300
5 IO pull currents
All others
PD
typ = 100
100
360
μA
9.5
NSHUTD REQUIREMENTS
No
Parameter
Symbol
Min
Max
Unit
1
Operation mode level 19 V
IH
1.42
1.98
V
2
Shutdown mode level
VIL
0
0.4
V
3
Minimum time for nSHUT_DOWN low to reset the device
5
ms
4
Rise/fall times
Tr/Tf
20
μs
9.6
EXTERNAL DIGITAL SLOW CLOCK REQUIREMENTS (–20°C TO +70°C)
No
Characteristics
Condition
Symbol
Min
Typ
Max
Unit
1
Input slow clock frequency
32768
Hz
2
Input slow clock accuracy (Initial + temp + aging)
Bluetooth
±250
Ppm
3
Input transition time Tr/Tf – 10% to 90%
Tr/Tf
100
Ns
4
Frequency input duty cycle
15%
50%
85%
5
Phase noise
at 1 kHz
-125
dBc/Hz
6
Jitter
Integrated over 300 to 15000 Hz
1
Hz
VIH
0.65 x
VDD_IO
VDD_IO
7
Slow clock input voltage limits
Square wave, DC coupled
VIL
0
0.35 x
VDD_IO
V peak
8
Input impedance
1
MΩ
9
Input capacitance
5
pF
19 Internal pull down retains shut down mode when no external signal is applied to this pin.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
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10
HOST CONTROLLER INTERFACE
The CC256X incorporates one UART module dedicated to the host controller interface (HCI) transport layer. The HCI interface transports commands, events, ACL, and synchronous data between the Bluetooth device and its host using HCI data packets.
The UART module supports H4 (4-wires) protocol with maximum baud rate of 4 Mbps for all fast clock frequencies.
After power up the baud rate is set for 115.2 kbps, irrespective of fast clock frequency. The baud rate can thereafter be changed with a vendor specific command. The CC256X responds with a Command Complete Event (still at 115.2 kbps), after which the baud rate change takes place. HCI hardware includes the following features:
• Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions
• Transmitter underflow detection
• CTS/RTS hardware flow control
The interface includes four signals: TXD, RXD, CTS, and RTS. Flow control between the host and the CC256X is byte-wise by hardware.
Flow control is obtained by the following:
When the UART RX buffer of the CC256X passes the “flow control” threshold, it will set the UART_RTS signal high to stop transmission from the host.
When the UART_CTS signal is set high, the CC256X will stop its transmission on the interface. In case HCI_CTS is set high in the middle of transmitting a byte, the CC256X will finish transmitting the byte and stop the transmission.
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11
AUDIO/VOICE CODEC INTERFACE
The codec interface is a fully-dedicated programmable serial port that provides the logic to interface to several kinds of PCM or I2S codec’s. PAN13XX supports all voice coding schemes required by Bluetooth specification – Log PCM (A-Law or μ-Law) and Linear (CVSD). In addition, module also supports transparent scheme:
• Two voice channels
• Master / slave modes
• μ-Law, A-Law, Linear, Transparent coding schemes
• Long and short frames
• Different data sizes, order, and positions.
• High rate PCM interface for EDR
• Enlarged interface options to support a wider variety of codecs
• PCM bus sharing
11.1
PCM HARDWARE INTERFACE
The PCM interface is one implementation of the codec interface. It contains the following four lines:
• Clock—configurable direction (input or output)
• Frame Sync—configurable direction (input or output)
• Data In—Input
• Data Out—Output/3-state
The Bluetooth device can be either the master of the interface where it generates the clock and the frame-sync signals, or slave where it receives these two signals. The PCM interface is fully configured by a vendor specific command.
For slave mode, clock input frequencies of up to 16 MHz are supported. At clock rates above 12 MHz, the maximum data burst size is 32 bits. For master mode, the CC256X can generate any clock frequency between 64 kHz and 6 MHz.
Please contact your sales representative if using the I2S bus over PCM. We strongly recommend adding a low pass filter (series resistor and capacitor to GND) to the bus for better noise suppression. It is not recommended to directly contact the host μController/DSP with the PCM interface.
11.2
DATA FORMAT
The data format is fully configurable:
• The data length can be from 8 to 320 bits, in 1-bit increments, when working with two channels, or up to 640 bits when using 1 channel. The Data length can be set independently for each channel.
• The data position within a frame is also configurable in with 1 clock (bit) resolution and can be set independently (relative to the edge of the Frame Sync signal) for each channel.
• The Data_In and Data_Out bit order can be configured independently. For example; Data_In can start with the MSB while Data_Out starts with LSB. Each channel is separately configurable. The inverse bit order (that is, LSB first) is supported only for sample sizes up to 24 bits.
• It is not necessary for the data in and data out size to be the same length.
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• The Data_Out line is configured to ‘high-Z’ output between data words. Data_Out can also be set for permanent high-Z, irrespective of data out. This allows the CC256X to be a bus slave in a multi-slave PCM environment. At powerup, Data Out is configured as high-Z.
11.3
FRAME IDLE PERIOD
The codec interface has the capability for frame idle periods, where the PCM clock can “take a break” and become ‘0’ at the end of the PCM frame, after all data has been transferred.
The CC256X supports frame idle periods both as master and slave of the PCM bus.
When CC256X is the master of the interface, the frame idle period is configurable. There are two configurable parameters:
• Clk_Idle_Start – Indicates the number of PCM clock cycles from the beginning of the frame until the beginning of the idle period. After Clk_Idle_Start clock cycles, the clock will become ‘0’.
• Clk_Idle_End – Indicates the time from the beginning of the frame till the end of the idle period. This time is given in multiples of PCM clock periods.
The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period.
For example, for PCM clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90.
Between each two frame syncs there are 70 clock cycles (instead of 100). The clock idle period starts 60 clock cycles after the beginning of the frame, and lasts 90 – 60 = 30 clock cycles. This means that the idle period ends 100 – 90 = 10 clock cycles before the end of the frame. The data transmission must end prior to the beginning of the idle period.
CLASSIFICATION PRODUCT SPECIFICATION No.
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REV.
3.40
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11.4
CLOCK-EDGE OPERATION
The codec interface of the CC256X can work on the rising or the falling edge of the clock. It also has the ability to sample the frame sync and the data at inversed polarity.
This is the operation of a falling-edge-clock type of codec. The codec is the master of the PCM bus. The frame sync signal is updated (by the codec) on the falling clock edge and therefore shall be sampled (by the CC256X) on the next rising clock. The data from the codec is sampled (by the CC256X) on the clock falling edge.
11.5
TWO-CHANNEL PCM BUS EXAMPLE
In below figure, a 2-channel PCM bus is shown where the two channels have different word sizes and arbitrary positions in the bus frame. (FT stands for Frame Timer)
11.6
AUDIO ENCODING
The CC256X codec interface can use one of four audio-coding patterns:
• A-Law (8-bit)
• μ-Law (8-bit)
• Linear (8- or 16-bit)
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11.7
IMPROVED ALGORITHM FOR LOST PACKETS
The CC256X features an improved algorithm for improving voice quality when received voice data packets are lost. There are two options:
• Repeat the last sample – possible only for sample sizes up to 24 bits. For sample sizes >24 bits, the last byte is repeated.
• Repeat a configurable sample of 8 to 24 bits (depends on the real sample size), in order to simulate silence (or anything else) in the PCM bus. The configured sample will be written in a specific register for each channel.
The choice between those two options is configurable separately for each channel.
11.8
BLUETOOTH/PCM CLOCK MISMATCH HANDLING
In Bluetooth RX, the CC256X receives RF voice packets and writes these to the codec I/F. If the CC256X receives data faster than the codec I/F output allows, an overflow will occur. In this case, the Bluetooth has two possible behaviour modes: ‘allow overflow’ and ‘don’t allow overflow’.
• If overflow is allowed, the Bluetooth will continue receiving data and will overwrite any data not yet sent to the codec.
• If overflow is not allowed, RF voice packets received when buffer is full will be discarded.
11.9
BLUETOOTH INTER-IC SOUND (I2S)
The CC256X can be configured as an Inter-IC Sound (I2S) serial interface to an I2S codec device. In this mode, the CC256X audio codec interface is configured as a bi-directional, full-duplex interface, with two time slots per frame: Time slot 0 is used for the left channel audio data and time slot 1 for the right channel audio data. Each time slot is configurable up to 40 serial clock cycles in length and the frame is configurable up to 80 serial clock cycles in length.
Do not connect the the microcontroller/DSP directly to the module's PCM interface, a simple RC low pass filter is recommended to improve noise suppression.
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DS-13xx-2400-102
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11.10
CURRENT CONSUMPTION FOR DIFFERENT BLUETOOTH SCENARIOS
The following table gives average current consumption for different Bluetooth scenarios.
Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz fast clock, nominal unit, 4 dBm output power.
12
BLUETOOTH RF PERFORMANCE
No
Characteristics
Typ
BT Spec Max
BT Spec Min
Class1
Class1
1
Average Power Hopping DH5 [dBm] 21, 22
7.2
20
4
2
Average Power: Ch0 [dBm] 21, 22
7.5
20
4
3
Peak Power: Ch0 [dBm] 21, 22
7.7
23
4
Average Power: Ch39 [dBm] 21, 22
7.0
20
4
5
Peak Power: Ch39 [dBm] 21, 22
7.2
23
6
Average Power: Ch78 [dBm] 21, 22
6.7
20
4
7
Peak Power: Ch78 [dBm] 21, 22
7.0
23
8
Max. Frequency Tolerance: Ch0 [kHz]
-2.6
75
-75
9
Max. Frequency Tolerance: Ch39 [kHz]
-2.2
75
-75
10
Max. Frequency Tolerance: Ch78 [kHz]
-2.1
75
-75
11
Max. Drift: Ch0_DH1 [kHz]
3.6
25
-25
12
Max. Drift: Ch0_DH3 [kHz]
3.7
40
-40
13
Max. Drift: Ch0_DH5 [kHz]
4.0
40
-40
14
Max. Drift Rate: Ch0_DH1 [kHz]
-2.6
20
-20
15
Max. Drift Rate: Ch0_DH3 [kHz]
-3.2
20
-20
16
Max. Drift Rate: Ch0_DH5 [kHz]
-3.3
20
-20
17
Max. Drift: Ch39_DH1 [kHz]
4.0
25
-25
18
Max. Drift: Ch39_DH3 [kHz]
4.3
40
-40
19
Max. Drift: Ch39_DH5 [kHz]
4.3
40
-40
20
Max. Drift Rate: Ch39_DH1 [kHz]
-3.1
20
-20
21
Max. Drift Rate: Ch39_DH3 [kHz]
-3.6
20
-20
22
Max. Drift Rate: Ch39_DH5 [kHz]
-3.7
20
-20
CLASSIFICATION PRODUCT SPECIFICATION No.
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No Characteristics Typ
BT Spec
Max
BT Spec
Min
Class1 Class1
23
Max. Drift: Ch78_DH1 [kHz]
4.1
25
-25
24
Max. Drift: Ch78_DH3 [kHz]
4.5
40
-40
25
Max. Drift: Ch78_DH5 [kHz]
4.4
40
-40
26
Max. Drift Rate: Ch78_DH1 [kHz]
-3.4
20
-20
27
Max. Drift Rate: Ch78_DH3 [kHz]
-3.9
20
-20
28
Max. Drift Rate: Ch78_DH5 [kHz]
-4.1
20
-20
29
Delta F1 Avg: Ch0 [kHz]
159.5
175
140
30
Delta F2 Max.: Ch0 [%]
100.0
99.9
31
Delta F2 Avg/Delta F1 Avg: Ch0
0.9
0.8
32
Delta F1 Avg: Ch39 [kHz]
159.8
175
140
33
Delta F2 Max.: Ch39 [%]
100.0
99.9
34
Delta F2 Avg/Delta F1 Avg: Ch39
0.9
0.8
35
Delta F1 Avg: Ch78 [kHz]
159.1
175
140
36
Delta F2 Max.: Ch78 [%]
100.0
99.9
37
Delta F2 Avg/Delta F1 Avg: Ch78
0.9
0.8
45
Sensitivity
-93.0
-81
46
f(H)-f(L): Ch0 [kHz]
918.4
1000
47
f(H)-f(L): Ch39 [kHz]
918.3
1000
48
f(H)-f(L): Ch78 [kHz]
918.2
1000
49
ACPower -3: Ch3 [dBm]
-51.5
-40
50
ACPower -2: Ch3 [dBm]
-50.4
-40
51
ACPower -1: Ch3 [dBm]
-18.5
52
ACPower Center: Ch3 [dBm]
8.1
20
4
53
ACPower +1: Ch3 [dBm]
-19.2
54
ACPower +2: Ch3 [dBm]
-50.7
-40
55
ACPower +3: Ch3 [dBm]
-53.3
-40
56
ACPower -3: Ch39 [dBm]
-51.6
-40
57
ACPower -2: Ch39 [dBm]
-50.7
-40
58
ACPower -1: Ch39 [dBm]
-19.0
59
ACPower Center: Ch39 [dBm]
7.7
20
4
60
ACPower +1: Ch39 [dBm]
-19.7
61
ACPower +2: Ch39 [dBm]
-50.9
-40
62
ACPower +3: Ch39 [dBm]
-53.2
-40
63
ACPower -3: Ch75 [dBm]
-51.7
-40
64
ACPower -2: Ch75 [dBm]
-50.7
-40
65
ACPower -1: Ch75 [dBm]
-19.2
66
ACPower Center: Ch75 [dBm]
7.5
20
4
67
ACPower +1: Ch75 [dBm]
-20.0
68
ACPower +2: Ch75 [dBm]
-51.0
-40
69
ACPower +3: Ch75 [dBm]
-53.4
-40
70
omega i 2-DH5: Ch0 [kHz]
-4.7
75
-75
71
omega o + omega i 2-DH5: Ch0 [kHz]
-6.0
75
-75
72
omega o 2-DH5: Ch0 [kHz]
-1.5
10
-10
73
DEVM RMS 2-DH5: Ch0 [%]
0.0
0.2
74
DEVM Peak 2-DH5: Ch0 [%]
0.1
0.35
CLASSIFICATION PRODUCT SPECIFICATION No.
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No Characteristics Typ
BT Spec
Max
BT Spec
Min
Class1 Class1
75
DEVM 99% 2-DH5: Ch0 [%]
100.0
99
76
omega i 3-DH5: Ch0 [kHz]
-3.7
75
-75
77
omega o + omega i 3-DH5: Ch0 [kHz]
-5.8
75
-75
78
omega o 3-DH5: Ch0 [kHz]
-2.6
10
-10
79
DEVM RMS 3-DH5: Ch0 [%]
0.0
0.13
80
DEVM Peak 3-DH5: Ch0 [%]
0.1
0.25
81
DEVM 99% 3-DH5: Ch0 [%]
100.0
99
82
omega i 2-DH5: Ch39 [kHz]
-4.8
75
-75
83
omega o + omega i 2-DH5: Ch39 [kHz]
-6.1
75
-75
84
omega o 2-DH5: Ch39 [kHz]
-1.4
10
-10
85
DEVM RMS 2-DH5: Ch39 [%]
0.0
0.2
86
DEVM Peak 2-DH5: Ch39 [%]
0.1
0.35
87
DEVM 99% 2-DH5: Ch39 [%]
100.0
99
88
omega i 3-DH5: Ch39 [kHz]
-3.8
75
-75
89
omega o + omega i 3-DH5: Ch39 [kHz]
-5.9
75
-75
90
omega o 3-DH5: Ch39 [kHz]
-2.6
10
-10
91
DEVM RMS 3-DH5: Ch39 [%]
0.0
0.13
92
DEVM Peak 3-DH5: Ch39 [%]
0.1
0.25
93
DEVM 99% 3-DH5: Ch39 [%]
100.0
99
94
omega i 2-DH5: Ch78 [kHz]
-4.9
75
-75
95
omega o + omega i 2-DH5: Ch78 [kHz]
-6.2
75
-75
96
omega o 2-DH5: Ch78 [kHz]
-1.4
10
-10
97
DEVM RMS 2-DH5: Ch78 [%]
0.0
0.2
98
DEVM Peak 2-DH5: Ch78 [%]
0.1
0.35
99
DEVM 99% 2-DH5: Ch78 [%]
100.0
99
100
omega i 3-DH5: Ch78 [kHz]
-3.8
75
-75
101
omega o + omega i 3-DH5: Ch78 [kHz]
-6.0
75
-75
102
omega o 3-DH5: Ch78 [kHz]
-2.7
10
-10
103
DEVM RMS 3-DH5: Ch78 [%]
0.0
0.13
104
DEVM Peak 3-DH5: Ch78 [%]
0.1
0.25
105
DEVM 99% 3-DH5: Ch78 [%]
100.0
99
No
Characteristics
Condition
Min
Typ
Max
BT Spec
Unit
1
Operation frequency range
2402
2480
MHz
2
Channel spacing
1
MHz
3
Input impedance
50
Ω
GFSK, BER = 0.1%
-93.0
-70
Pi/4-DQPSK, BER = 0.01%
-92.5
-70
4
Sensitivity, Dirty Tx on
8DPSK, BER = 0.01%
-85.5
-70
dBm
CLASSIFICATION PRODUCT SPECIFICATION No.
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3.40
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No
Characteristics
Condition
Typ
Max
Unit
30 kHz to 1 GHz 20, 21, 22
-30
1
Tx and Rx out-of-band emissions
Output signal = 7dBm
1 to 12.75 GHz 20, 21, 22
-30
dBm
2
2nd harmonic
at 7dBm output power 20, 21, 22
-30
dBm
3
3rd harmonic
at 7dBm output power 20, 21, 22
-30
dBm
The values are measured conducted. Better suppression of the spurious emissions with an antenna can be expected as, antenna frequently have band pass filter characteristics.
13
SOLDERING TEMPERATURE-TIME PROFILE (FOR REFLOW SOLDERING)
13.1
FOR LEAD SOLDER
Recommended temp. profile for reflow soldering Temp.[°C] Time [s] 235°C max. 220 ±5°C 200°C150 ±10°C 90 ±30s 10 ±1s 30 +20/-10s
20 Includes effects of frequency hopping
21 Average according FCC, IC and ETSI requirements. Above +7dBm output power (refer also to 22) the customer has to verify the final product against national regulations.
22 +7dBm related to power register value 18, according to TI service pack 2.30
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REV.
3.40
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13.2
FOR LEADFREE SOLDER
Our used temp. profile for reflow soldering Temp.[°C] Time [s] 230°C -250°C max. 220°C150°C – 190°C 90 ±30s 30 +20/-10s
Reflow permissible cycle: 2 Opposite side reflow is prohibited due to module weight.
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14
MODULE DIMENSION
14.1
MODULE DIMENSIONS PAN131X WITHOUT ANTENNA
No.
Item
Dimension
Tolerance
Remark
1
Width
6.50
± 0.20
2
Lenght
9.00
± 0.20
3
Height
1.80
± 0.20
With case
PAN131X Module Drawing
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14.2
MODULE DIMENSIONS PAN132X WITH ANTENNA
No.
Item
Dimension
Tolerance
Remark
1
Width
9.50
± 0.20
2
Lenght
9.00
± 0.20
3
Height
1.80
± 0.20
With case
PAN132X Module Drawing
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DS-13xx-2400-102
REV.
3.40
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CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
15
FOOTPRINT OF THE MODULE
15.1
FOOTPRINT PAN131X WITHOUT ANTENNA
All dimensions are in millimeters. The outer dimensions have a tolerance of ± 0.2mm.
The layout is symetric to center. The inner pins (2,4,6,9,11,14,16,18,21,23) are shifted to the center by 1mm.
0.901.706,500.901.809,00171513141211987653212324211819202210416Pad =
24 x
0.60mm x
0.60mmTop View1.802.702.953.95
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REV.
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CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
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15.2
FOOTPRINT PAN132X WITH ANTENNA
All dimensions are in millimeters. The outer dimensions have a tolerance of ± 0.2mm.
The layout is symetric to center. The inner pins (2,4,6,9,11,14,16,18,21,23) are shifted to the center by 1mm. 2.700.901.709.50171513141211987653212324211819202210416Pad =
28 x
0.60mm x 0.60mm1.80ACBD1.800.551.001.80
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DS-13xx-2400-102
REV.
3.40
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CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
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16
LABELING DRAWING
The above pictures show the laser marking on the top case, this is only an example from PAN1315.
17
MECHANICAL REQUIREMENTS
No.
Item
Limit
Condition
1
Solderability
More than 75% of the soldering area shall be coated by solder
Reflow soldering with recommendable temperature profile
2
Resistance to soldering heat
It shall be satisfied electrical requirements and not be mechanical damage
See Chapter 13.2
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CUSTOMER’S CODE
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18
RECOMMENDED FOOT PATTERN
18.1
RECOMMENDED FOOT PATTERN PAN131X WITHOUT ANTENNA
Dimensions in mm.
171513141211987653212324211819202210416Pad = 24 x 0.60mm x 0.60mmTop View9,00 6,008,50
The land pattern dimensions above are meant to serve only as a guide. This information is provided without any legal liability.
For the solder paste screen, use as a first guideline the same foot print as shown in the figure above. Solder paste screen cutouts (with slightly different dimensions) might be optimum depending on your soldering process. For example, the solder paste screen thickness chosen might have an effect. The solder screen thickness depends on your production standard 120μm to 150μm is recommended.
IMPORTANT: Although the bottom side of PAN131X is fully coated, no copper such as through hole vias, planes or tracks on the board component layer should be located below the PAN131X to avoid creating a short. In cases where a track or through hole via has to be located under the module, it must be kept away from PAN131X bottom pads. The PAN131X multilayer pcb contains an inner RF shielding plane, therefore no pcb shielding plane below the module is needed.
When using an onboard ceramic antenna, place the antenna on the edge of your carrier board (if allowable).
If you have any questions on these points, contact your local Panasonic representative.
Schematics and layouts may be sent to wireless@eu.panasonic.com for final review.
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PANASONIC’S CODE
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18.2
RECOMMENDED FOOT PATTERN PAN132X WITH ANTENNA
Dimensions in mm.
The land pattern dimensions above are meant to serve only as a guide.
For the solder paste screen, use as a first guideline the same foot print as shown in the Figure above. Solder paste screen cutouts (with slightly different dimensions) might be optimum depending on your soldering process. For example, the solder paste screen thickness chosen might have an effect. The solder screen thickness depends on your production standard 120μm to 150μm is recommended.
IMPORTANT: In cases where a track or through hole via has to be located under the module, it must be kept away from PAN132X bottom pads. The PAN132X multilayer pcb contains an inner RF shielding plane, therefore no pcb shielding plane below the module is needed.
If you have any questions on these points, contact your local Panasonic representative.
Schematics and layouts may be sent to wireless@eu.panasonic.com for final review.
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REV.
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PANASONIC’S CODE
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19
LAYOUT RECOMMENDATIONS WITH ANTENNA (PAN132X)
20
BLUETOOTH LE (LOW ENERGY) PAN1316/26
20.1
NETWORK TOPOLOGY
Bluetooth Low Energy is designed to reduce power consumption. It can be put into a sleep mode and is only activated for event activities such as sending files to a gateway, PC or mobile phone. Furthermore the maximum power consumption is set to less than 15 mA and the average power consumption is about 1 uA. The benefit of low energy consumption are short messages and establishing very fast connections (few ms). Using these techniques, energy consumption is reduced to a tenth of a Classic Bluetooth unit. Thus, a small coin cell – such as a CR2032 – is capable of powering a device for up to 10 years of operation.
T
o be backwards compatible with Classic Bluetooth and to be able to offer an affordable solution for very inexpensive devices, Panasonic Low Energy Bluetooth modules are offered in two versions:
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Dual-mode: Bluetooth Low Energy technology combined with Classic Bluetooth functionality on a single module. Dual mode devices act as gateways between these two technologies.
Single Mode: Bluetooth Low Energy technology to optimize power consumption, which is particularly useful for products powered by small batteries. These modules have embedded controllers allowing the module to operate autonomously in low cost applications that lack intelligence.
This data sheet describes dual-mode Bluetooth Low Energy technology combined with Classic Bluetooth functionality on a single module. Additional information on Panasonic’s single mode products can be found by visiting www.panasonic.com/rfmodules or write an e-mail to wireless@eu.panasonic.com.
20.2
MODULE FEATURES
Fully compliant with Bluetooth 4.0:
•
Optimized for proximity and sports use
•
Supports up to 10 simultaneous connections
•
Multiple sniff instances are tightly coupled to minimize power consumption
•
Independent buffering allows a large number of multiple connections without affecting BR/EDR performance
•
Includes built-in coexistence and prioritization handling for BR/EDR and LE
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CUSTOMER’S CODE
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PANASONIC’S CODE
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20.3
CURRENT CONSUMPTION FOR DIFFERENT LE SCENARIOS
Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz fast clock, nominal unit, 10 dBm output power
Mode
Description
Average Current
Unit
Advertising, non-connectable
Advertising in all 3 channels
1.28msec advertising interval
15Bytes advertise Data
104
μA
Advertising, discoverable
Advertising in all 3 channels
1.28msec advertising interval
15Bytes advertise Data
121
μA
Scanning
Listening to a single frequency per window
1.28msec scan interval
11.25msec scan window
302
μA
Connected
(master role)
500msec connection interval
0msec Slave connection latency
Empty Tx/Rx LL packets
169
μA
21
ANT PAN1317/27
ANT+ (sometimes ANT + or ANT Plus) is an interoperability function that can be added to the base ANT protocol (a proprietary wireless sensor network technology).[
21.1
NETWORK TOPOLOGY
ANT™ is a wireless sensor network protocol operating in the 2.4 GHz spectrum. Designed for ultra-low power, ease of use, efficiency and scalability, ANT supports peer-to-peer, star, tree and fixed mesh topologies. It provides reliable data communications, flexible and adaptive network operation and cross-talk immunity. The ANT protocol stack is compact, requiring minimal microcontroller resources to reduce system costs, lighten the computational burden and improve efficiency. Low-level security is implemented to allow user-defined network security.
PAN1317/1327 provides the first wireless, single-chip solution with dual-mode ANT and Bluetooth connectivity with inclusion of TI’s CC2567 device. This solution wirelessly connects 13 million ANT-based devices to the more than 3 billion Bluetooth endpoint devices used by people every day, creating new market opportunities for companies building ANT products and Bluetooth products alike. CC2567 requires 80% less board area than a design with two single-mode solutions (one ANT+, one Bluetooth) and increases the wireless transmission range up to two times the distance of a single-mode ANT+ solution.
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PANASONIC’S CODE
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21.2
MODULE FEATURES
Fully compliant with ANT protocol:
• ANT solution optimized for fitness, health and consumers use cases
• Supports up to eight simultaneous connections, various network topologies and high-resolution proximity pairing
• Includes built-in coexistence and prioritization handling for BR/EDR and ANT
Features
Benefits
Dual-mode ANT+ and Bluetooth (Bluetooth v2.1 + EDR) on a single chip
- Requires 80% less board area than any dual module or device design
- Reduces costs associated with incorporating two wireless technologies
Fully validated optimized single antenna solution
- Enables simultaneous operation of ANT+ and Bluetooth without the need for two devices or modules
- Includes built-in coexistence
Best-in-class Bluetooth and ANT RF performance:
- +10 dBm Tx power with transmit power control
- -93 dBm sensitivity
- Delivers twice the distance between the aggregator and ANT sensor device than competitive single-mode ANT solutions
- Enables a robust and high-throughput connection with extended range
Support for:
- ANT+ ultra low power (master and slave devices)
- Bluetooth power saving modes (park, sniff, hold)
- Bluetooth ultra low power modes (deep sleep, power down)
- Improves battery life and power efficiency of the finished product
Turnkey solution:
- Fully integrated module
- Complete development kit with software and documentation
- TI MSP430 hardware and software platform integration (optional)
- Ease of integration into system allows quick time to market
- Reduces costs and time associated with certification
21.3
ANT CURRENT CONSUMPTION
Mode
Description
Average Current
Unit
Rx message mode
250msec interval
380
μA
Rx message mode
500msec interval
205
μA
Rx message mode
1000msec interval
118
μA
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22
TRIPLE MODE (BR/EDR + BLUETOOTH LOW ENERGY + ANT) PAN1323
The PAN1323 has been engineered to give designers the flexibility to implement Bluetooth Classic (BR/EDR), Bluetooth Low Energy and ANT into an application using a single module, reducing cost and footprint area. Refer to the paragraphs above for complete descriptions on each of the three protocols. The module is fully hardware compatible with the PAN1315, 15A, 16, 17, 25, 25A, 26 and 27. A highly efficent single RF block serves all three protocols. Protocols access the RF block using time division multiplexing. The application layer determines the priority and timing of the RF block.Customers interested in this unique module are encouraged to contact StoneStreetOne for a Bluetooth SIG certified stack.
22.1
TRIPLE MODE CURRENT CONSUMPTION
The current consumption of the PAN1326 is a function of the protocol that the module is running at any point in time. Refer to the paragraphs above for details on current consumption for each of the three protocols or software vendor.
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PANASONIC’S CODE
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23
DEVELOPMENT OF APPLICATIONS
Mindtree Ltd. has developed a Bluetooth SPP freeware for TIs MSP430 and Panasonics PAN1315(A) and PAN1325(A). For other software refer to Chapter 24 or visit the following link www.panasonic.com/rfmodules.
23.1
TOOLS TO BE NEEDED
PAN1323ETU
Tool
Source
TI - MSP-EXP430F5438 - Experimenter Board
MSP-EXP430F5438
TI - MSP-FET430UIF430 - Debugging Interface
MSP-FET430UIF430
TI PAN1323EMK
PAN1323EMK - Bluetooth Evaluation Module Kit for MSP430
Panasonic PAN1323ETU
CC2567-PAN1327ANT-BTKIT
For information on Bluetooth + ANT kit for PAN1327
CC2567 + PAN1327 wiki
In addition you need the software development environment, e.g. IAR Embedded Workbench, refer to:
http://wiki.msp430.com/index.php/MSP430_Bluetooth_Platform
Evaluation kits and modules are available through Panasonic’s network of authorized distributors. For any additional information, please visit www.panasonic.com/rfmodules.
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REV.
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CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
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24
LIST OF PROFILES
Profile
Software Developer
Controller
Availability
Bluetooth
SPP and others
MindTree
TI, MSP430
Now
SPP
Seeran
STM32, MSP430
Now
HDP, SPP
Stollmann
TI, MSP430
Now
A2DP, AVRCP, SPP
StoneStreetOne
TI, Stellaris
Now
SPP and others
ARS
Multiple
Now
Bluetooth LE
All
ARS, MindTree, StoneStreetOne, Stollmann
TI, MSP430 and others
Upon request
ANT Protocoll
ANT
Dynastream
MSP430 and others
Now
Triple Mode Stack
SPP
StoneStreetOne
MSP430 and others
Now
For all other profiles contact your local sales representative.
25
RELIABILITY TESTS
The measurement should be done after being exposed to room temperature and humidity for 1 hour.
No.
Item
Limit
Condition
1
Vibration test
Electrical parameter should be in specification
a) Freq.:10~50Hz,Amplitude:1.5mm
a) 20min. / cycle,1hrs. each of XYZ axis
b) Freq.:30~100Hz, 6G
b) 20min. / cycle,1hrs. each of XYZ axis
2
Shock test
the same as above
Dropped onto hard wood from height of 50cm for 3 times
3
Heat cycle test
the same as above
-40°C for 30min. and +85°C for 30min.;
each temperature 300 cycles
4
Moisture test
the same as above
+60°C, 90% RH, 300h
5
Low temp. test
the same as above
-40°C, 300h
6
High temp. test
the same as above
+85°C, 300h
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
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26
CAUTIONS
Failure to follow the guidelines set forth in this document may result in degrading of the product’s functions and damage to the product.
26.1
DESIGN NOTES
(1)
Follow the conditions written in this specification, especially the control signals of this module.
(2)
The supply voltage has to be free of AC ripple voltage (for example from a battery or a low noise regulator output). For noisy supply voltages, provide a decoupling circuit (for example a ferrite in series connection and a bypass capacitor to ground of at least 47uF directly at the module).
(3)
This product should not be mechanically stressed when installed.
(4)
Keep this product away from heat. Heat is the major cause of decreasing the life of these products.
(5)
Avoid assembly and use of the target equipment in conditions where the products' temperature may exceed the maximum tolerance.
(6)
The supply voltage should not be exceedingly high or reversed. It should not carry noise and/or spikes.
(7)
Keep this product away from other high frequency circuits.
26.2
INSTALLATION NOTES
(1) Reflow soldering is possible twice based on the conditions in Chapter 15. Set up the temperature at the soldering portion of this product according to this reflow profile.
(2)
Carefully position the products so that their heat will not burn into printed circuit boards or affect the other components that are susceptible to heat.
(3)
Carefully locate these products so that their temperatures will not increase due to the effects of heat generated by neighboring components.
(4)
If a vinyl-covered wire comes into contact with the products, then the cover will melt and generate toxic gas, damaging the insulation. Never allow contact between the cover and these products to occur.
(5)
This product should not be mechanically stressed or vibrated when reflowed.
(6)
To repair a board by hand soldering, keep the conditions of this chapter.
(7)
Do not wash this product.
(8)
Refer to the recommended pattern when designing a board.
(9)
Pressing on parts of the metal cover or fastening objects to the metal will cause damage to the unit.
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REV.
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26.
3 USAGE CONDITIONS NOTES
(1) T
ake measures to protect the unit against static electricity. If pulses or other transient loads (a large load applied in a short time) are applied to the products, check and evaluate their operation befor assembly on the final products.
(2)
Do not use dropped products.
(3)
Do not touch, damage or soil the pins.
(4)
Follow the recommended condition ratings about the power supply applied to this product.
(5)
Electrode peeling strength: Do not add pressure of more than 4.9N when soldered on PCB.
(6)
Pressing on parts of the metal cover or fastening objects to the metal cover will cause damage.
(7)
These products are intended for general purpose and standard use in general electronic equipment, such as home appliances, office equipment, information and communication equipment.
26.
4 STORAGE NOTES
(1) T
he module should not be stressed mechanically during storage.
(2)
Do not store these products in the following conditions or the performance characteristics of the product, such as RF performance will be adversely affected:
• St
orage in salty air or in an environment with a high concentration of corrosive gas, such as Cl2, H2S, NH3, SO2, or NOX
•
Storage in direct sunlight
•
Storage in an environment where the temperature may be outside the range of 5°C to 35°C range, or where the humidity may be outside the 45 to 85% range.
•
Storage of the products for more than one year after the date of delivery Storage period: check the adhesive strength of the embossed tape and soldering after 6 months of storage.
(
3) Keep this product away from water, poisonous gas and corrosive gas.
(4)
This product should not be stressed or shocked when transported.
(5)
Follow the specification when stacking packed crates (max. 10).
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
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CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
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26.
5 SAFETY CAUTIONS
These specifications are intended to preserve the quality assurance of products and individual components.
Before use, check and evaluate the operation when mounted on your products. Abide by these specifications, without deviation when using the products. These products may short-circuit. If electrical shocks, smoke, fire, and/or accidents involving human life are anticipated when a short circuit occurs, then provide the following failsafe functions, as a minimum.
(1)
Ensure the safety of the whole system by installing a protection circuit and a protection device.
(2)
Ensure the safety of the whole system by installing a redundant circuit or another system to prevent a single fault causing an unsafe status.
26.
6 OTHER CAUTIONS
(1) T
his specification sheet is copyrighted.
(2)
Do not use the products for other purposes than those listed.
(3)
Be sure to provide an appropriate fail-safe function on your product to prevent an additional damage that may be caused by the abnormal function or the failure of the product.
(4)
This product has been manufactured without any ozone chemical controlled under the Montreal Protocol.
(5)
These products are not intended for other uses, other than under the special conditions shown below. Before using these products under such special conditions, check their performance and reliability under the said special conditions carefully to determine whether or not they can be used in such a manner.
• In
liquid, such as water, salt water, oil, alkali, or organic solvent, or in places where liquid may splash.
•
In direct sunlight, outdoors, or in a dusty environment
•
In an environment where condensation occurs.
•
In an environment with a high concentration of harmful gas (e.g. salty air, HCl, Cl2, SO2, H2S, NH3, and NOX)
(
6) If an abnormal voltage is applied due to a problem occurring in other components or circuits, replace these products with new products because they may not be able to provide normal performance even if their electronic characteristics and appearances appear satisfactory.
(7)
When you have any question or uncertainty, contact Panasonic.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 44 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
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27
PACKAGING
27
.1 PACKAGING OF PAN131X WITHOUT ANTENNA
Tape Dimension
Packing in Tape
trailer (empty)1 x circumference /hub(min 160mm)component packed areastandard 1500pcsleader (empty)minimum 10 pitchTop cover tape more than 1 x circumference plus 100mm to avoid fixing of tape end on sealed modules.Direction of unreeling (for customer)PAN1315 01/01ENW89809M5AYYWWDLLFCC ID: T7V1315Machine readable 2D-BarcodePAN1315 01/01ENW89809M5AYYWWDLLFCC ID: T7V1315Machine readable 2D-Barcode
Empty spaces in component packed area shall be less than two per reel and those spaces shall not be consecutive.
Top cover tape shall not be found on reel holes and shall not stick out from reel.
CLASSIFICATION PRODUCT SPECIFICATION No.
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REV.
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SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 45 of 57
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PAN13XX Core Specification
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Component direction
PAN1315 01/01ENW89809M5AYYWWDLLFCC ID: T7V1315Machine readable 2D-Barcode
Reel dimension
A BD NW2MAXMINMIN±1.0MAX13 +0.525.0 +2.024.4 +3.0 -0.2 -0.0 -0.5*Latch (2PC)All dimensions in millimeters unless otherwise stated Assembly Method24mm330.01.520.2100.030.4*LatchTAPE SIZECW1W3
CLASSIFICATION PRODUCT SPECIFICATION No.
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REV.
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SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 46 of 57
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Label for Package PAN1315Customer CodeENW89818C2JF105 mm
(1T) Lotcode [YYWWDLL] Example from above: YY year printed 08 WW normal calendar week printed 01 D day printed 5 (Friday) L line identifier, if more as one printed 1 L lot identifier per day printed 1 (1P) Customer Order Code, if any, otherwise company name will be printed
(2P) Panasonic Order Code fix as ENW89818C2JF
(9D) Datecode as [YYWW]
(Q) Quantity [XXXX], variable max. 1500
(HW/SW) Hardware /Software Release
Total Package
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
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SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 47 of 57
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PANASONIC’S CODE
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27.2
PACKAGING FOR PAN132X WITH ANTENNA
Tape Dimension
Measured from centreline of sprocket holeMeasured holeCumulative tolerance of 10 sprocketMeasured from centreline of sprocketto centreline of pocket.holes is ± 0.20 .hole to centreline of pocket.(I)(II)(III)(IV)Other material available.ALL DIMENSIONS IN MILLIMETRES UNLESS OTHERWISE STATED.WFP1+/-0.10+/-0.10+/-0.307.5012.0016.00K12.00+/-0.102.80+/-0.10+/-0.109.40BoKo9.90Ao+/-0.10 Tooling code: Flatbed -9 Estimated Max Length: 72m per 22B3 YYXXSECTION Y-Y SCALE 3.5 : 1SECTION X-X SCALE 3.5 : 1
Packing in Tape
All other packaging information is similar to Chapter 27.1
Pin1 Marking
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
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SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 48 of 57
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PAN13XX Core Specification
PANASONIC’S CODE
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28 O
RDERING INFORMATION
Version
Function
Controller
Part number
Antenna on board
Notes
MOQ (1)
PAN1315(2)
CC2560
ENW89818C2JF
NO
PAN1315A
Bluetooth v2.1 + EDR
CC2560A
ENW89829C2JF
NO
CC2560A offers reductions in init script size over CC2560 and is recommended for all new designs
1500
PAN1325(2)
CC2560
ENW89818A2JF
YES
PAN1325A
Bluetooth v2.1 + EDR
CC2560A
ENW89829A2JF
YES
CC2560A offers reductions in init script size over CC2560 and is recommended for all new designs.
1500
PAN1316
Bluetooth v2.1 + EDR
BLE 4.0
CC2564
ENW89823C2JF
NO
1500
PAN1326
Bluetooth v2.1 + EDR BLE 4.0
CC2564
ENW89823C2JF
YES
1500
PAN1317
Bluetooth v2.1 + EDR ANT
CC2567
ENW89827C2JF
NO
1500
PAN1327
Bluetooth v2.1 + EDR ANT
CC2567
ENW89827A2JF
YES
1500
PAN1323
Bluetooth v2.1 + EDR BLE 4.0 ANT
CC2569
ENW89842A2JF
YES
Check with your software developer for details on triple mode functionality.
1500
PAN1323ETU
Bluetooth v2.1 + EDR BLE 4.0 ANT
CC25xx
ENW89825A2JF
YES
Evaluation kit for the whole series. PAN1315-PAN1327.
1
Notes:
(1
) Abbreviation for Minimum Order Quantity (MOQ). The standard MOQ for mass production are 1500 pieces, fewer only on customer demand. Samples for evaluation can be delivered at any quantity.
(2) Not recommended for new designs, please refer to Chapter 1.1
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 49 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
29
ROHS DECLARATION
Declaration of environmental compatibility for supplied products:
Hereby we declare to our best present knowledge based on declaration of our suppliers that this product do not contain by now the following substances which are banned by Directive 2002/95/EC (RoHS) or if contain a maximum concentration of 0,1% by weight in homogeneous materials for
• Le
ad and lead compounds
• M
ercury and mercury compounds
•
Chromium (VI)
•
PBB (polybrominated biphenyl) category
•
PBDE (polybrominated biphenyl ether) category
And a maximum concentration of 0,01% by weight in homogeneous materials for
•
Cadmium and cadmium compounds
3
0 DATA SHEET STATUS
This data sheet contains the final specification (RELEASE).
Panasonic reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Supplementary data will be published at a later date.
Consult the most recently issued data sheet before initiating or completing a design.
Use this URL to search for the most recent version of this data sheet: PAN13xx Latest Data Sheet!
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 50 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
3
1 HISTORY FOR THIS DOCUMENT
Revision
Date
Modification / Remarks
0.90
18.12.2009
1st preliminary version
0.95
01.03.2010
Updated Chapter 14.2 and 28.
0.96
Not released
Change ESD Information on foot note 7 in chapter
Pin Description
0.97
25.03.2010
Various updates. Deleted links to TI Datasheet.
0.98
21.04.2010
Updated Links Some minor changes in Chapter 8 and 9.1 and change the base for the values in Chapter 9.
0.99
22.10.2010
Adopted changes according to CC2560 Datasheet. Included Interface Description, performance values. Not released.
1.00
04.11.2010
1st internal Release.
1.01
03.12.2010
Included reference to PAN1325 Application Note. AN-1325-2420-111.pdf
1.02
10.01.2011
Changed wording in Chapter 34.2 ”
Industry Canada Certification
”.
1.03
23.05.2011
Included DOC for PAN1315 series. Included PAN13xx ANT and BLE Addendum Rev1.x.pdf reference. Included Note for IO voltage and MLD_OUT pin.
1.04
02.07.2011
Corrected wording in Chapter 34.3
Europ
ean R&TTE Declaration of Conformity
.
1.05
28.10.2011
Including CC2560A silicon PAN1315A HW40 at Chapter 1.1, Chapter and Chapter 0. Deleted ES label in Chapter
1.06
15.11.2011
Added overview for the core specification and their addendums. Updated front page. Updated Related Documents.
3.00
11.01.2012
Merging PAN13xx documents into this specification and correct some format
3.10
16.01.2012
Minor mistakes fixed
3.20
29.05.2012
DoC replaced with revised version
3.30
11.06.2012
Added triple mode stack Module PAN1323, add PAN1323 to ordering and software information overview, Software Block Diagram added, Bluetooth Inter IC-Sound chapter information added
Layout Recommandations with Antenna added, Application Note LGA added
3.31
27.06.2012
Added design information to use low pass filter (chapter 11.1 / 11.9) for better noise surpression when using PCM interface
3.40
18.07.2012
Re-organize chapter
Re
gulatory Information
and added 2 chapters
1.
NCC St
atement
(only valid for PAN1325)
2.
Blu
etooth SIG Statement
3. Chapter 11.9, Second Paragraph was updated
4. Link in Chapter 34.1.1. was fixed
32
RELATED DOCUMENTS
For an update, search in the suitable homepage.
[1
] PAN1323ETU Design-Guide: http://www.panasonic.com/industrial/includes/pdf/PAN1323ETUDesignGuide.pdf
[2
] CC2560 Product Bulletin: http://focus.ti.com/pdfs/wtbu/cc2560_slyt377.pdf
[3] Bluetooth SW for MSP430 is supported by IAR IDE service pack 5.10.6 and later. Use full IAR version edition (not the kick-start version). You can find info on IAR at http://www.iar.com/website1/1.0.1.0/3/1/ and www.MSP430.com . Note, that there is an option for a 30-day free version of IAR evaluation edition.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 51 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
[4] PAN13xx CAD data: http://www.pedeu.panasonic.de/pdf/174ext.zip
[5] Application Note Land Grid Array: http://www.pedeu.panasonic.de/pdf/184ext.pdf
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 52 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
33
GENERAL INFORMATION
© Panasonic Industrial Devices Europe GmbH.
All rights reserved.
This document may contain errors. Panasonic reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its literature at any time. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to Panasonic’s terms and conditions of sale supplied at the time of order acknowledgment.
If we deliver ES samples to the customer, these samples have the status Engineering Samples. This means, the design of this product is not yet concluded. Engineering Samples may be partially or fully functional, and there may be differences to be published Data Sheet.
Engineering Samples are not qualified and are not to be used for reliability testing or series production.
Disclaimer:
Customer acknowledges that samples may deviate from the Data Sheet and may bear defects due to their status of development and the lack of qualification mentioned above.
Panasonic rejects any liability or product warranty for Engineering Samples. In particular, Panasonic disclaims liability for damages caused by
• th
e use of the Engineering Sample other than for Evaluation Purposes, particularly the installation or integration in an other product to be sold by Customer,
• de
viation or lapse in function of Engineering Sample,
• im
proper use of Engineering Samples.
Panasonic disclaimes any liability for consequential and incidental damages. Panasonic assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using Panasonic components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. In case of any questions, contact your local sales representative.
34 REGULATORY INFORMATION
34
.1 FCC FOR US
3
4.1.1 FCC Notice
The devices PAN13xx, for details refer to Chapter 28 in this document, including the antennas, which are listed in Chapter 34.5 of this data sheet, complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may
cause undesired operation.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 53 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
3
4.1.2 Caution
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Panasonic Industrial Devices Europe GmbH may void the user's authority to operate the equipment.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
•
Reorient or relocate the receiving antenna.
• I
ncrease the separation between the equipment and receiver.
• Con
nect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consu
lt the dealer or an experienced radio/TV technician for help
34.1.3
Labeling Requirements
The Original Equipment Manufacturer (OEM) must ensure that FCC labeling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Panasonic FCC identifier for this product as well as the FCC Notice above. The FCC identifier are FCC ID: T7V1315. This FCC identifier is valid for all PAN13xx modules, for details, see the Chapter 28. Ordering Information.
In any case the end product must be labelled exterior with "Contains FCC ID: T7V1315"
3
4.1.4 Antenna Warning
For the related part number of PAN13xx refer to Chapter 28. Ordering Information.
This devices are tested with a standard SMA connector and with the antennas listed below. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. The FCC identifier for this device with the antenna listed in item 1 are the same (FCC ID: T7V1315).
3
4.1.5 Approved Antenna List
Note: We are able to qualify your antenna and will add to this list as that process is completed.
Item
Part Number
Manufacturer
Frequency Band
Type
Gain (dBi)
1
2450AT43B100
Johanson Technologies
2.4GHz
Chip-Antenna
+1.3
2
LDA212G3110K
Murata
2.4GHz
Chip-Antenna
+0.9
3
4788930245
Würth Elektronik
2.4GHz
Chip-Antenna
+0.5
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 54 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
3
4.1.6 RF Exposure PAN13xx
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure that the approved antenna in the previous table must be installed.
The preceding statement must be included as a CAUTION statement in manuals for products operating with the approved antennas in the previous table to alert users on FCC RF Exposure compliance.
Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed.
The radiated output power of PAN13xx with mounted ceramic antenna (FCC ID: T7V1315) is far below the FCC radio frequency exposure limits. Nevertheless, the PAN13xx shall be used in such a manner that the potential for human contact during normal operation is minimized.
End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance.
34.2 INDUSTRY CANADA CERTIFICATION
PAN1315 is licensed to meet the regulatory requirements of Industry Canada (IC), license: IC: 216Q-1315
Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca.
This device has been designed to operate with the antennas listed in Table 20 above, having a maximum gain of 1.3 dBi. Antennas not included in this list or having a gain greater than 1.3 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. due to the model size the IC identifier is displayed in the installation instruction.
34.3 EUROPEAN R&TTE DECLARATION OF CONFORMITY
Hereby, Panasonic Industrial Devices Europe GmbH, declares that the Bluetooth module PAN1315 and their versions is in compliance with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labelled as follows:
PAN13xx and their versions in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 55 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 56 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
34.4 N
CC FOR TAIWAN
34.4.1
Labeling Requirements
Due to the limited size on the module, the NCC ID is not visible on the module.
When the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following:
“Contains Transmitter Module NCC ID:” or “Contains NCC ID:” CCAJ11LPxxxxTx
Any similar wording that expresses the same meaning may be used.
Panasonic is able to provide the above content from the label as a vector graphic, please ask at wireless@eu.panasonic.com.
34.4.2 NCC Statement
Due to the national rule from Taiwan we have to print the below statement in Chinese language.
34.5 BLUETOOTH SIG STATEMENT
35 L
IFE SUPPORT POLICY
This Panasonic product is not designed for use in life support appliances, devices, or systems where malfunction can reasonably be expected to result in a significant personal injury to the user, or as a critical component in any life support device or system whose failure to perform can be reasonably expected to cause the failure of the
CLASSIFICATION PRODUCT SPECIFICATION No.
DS-13xx-2400-102
REV.
3.40
SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 57 of 57
CUSTOMER’S CODE
PAN13XX Core Specification
PANASONIC’S CODE
See Chapter 28. Ordering Information DATE 18.07.2012
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de
life support device or system, or to affect its safety or effectiveness. Panasonic customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Panasonic for any damages resulting.
LM3S8933 Microcontroller
DATA SHEET
DS-LM3S8933-2550 Copyright © 2007-2008 Luminary Micro, Inc.
PRELIMINARY
Legal Disclaimers and Trademark Information
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO
LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR
USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS.
Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office
or your distributor to obtain the latest specifications before placing your product order.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these
for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Copyright © 2007-2008 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of
Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks and Cortex is a trademark
of ARM Limited. Other names and brands may be claimed as the property of others.
Luminary Micro, Inc.
108 Wild Basin, Suite 350
®
Austin, TX 78746
Main: +1-512-279-8800
Fax: +1-512-279-8879
http://www.luminarymicro.com
2 March 17, 2008
Preliminary
Table of Contents
About This Document .................................................................................................................... 20
Audience .............................................................................................................................................. 20
About This Manual ................................................................................................................................ 20
Related Documents ............................................................................................................................... 20
Documentation Conventions .................................................................................................................. 20
1 Architectural Overview ...................................................................................................... 22
1.1 Product Features ...................................................................................................................... 22
1.2 Target Applications .................................................................................................................... 27
1.3 High-Level Block Diagram ......................................................................................................... 28
1.4 Functional Overview .................................................................................................................. 28
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 29
1.4.2 Motor Control Peripherals .......................................................................................................... 29
1.4.3 Analog Peripherals .................................................................................................................... 30
1.4.4 Serial Communications Peripherals ............................................................................................ 30
1.4.5 System Peripherals ................................................................................................................... 32
1.4.6 Memory Peripherals .................................................................................................................. 33
1.4.7 Additional Features ................................................................................................................... 33
1.4.8 Hardware Details ...................................................................................................................... 34
2 ARM Cortex-M3 Processor Core ...................................................................................... 35
2.1 Block Diagram .......................................................................................................................... 36
2.2 Functional Description ............................................................................................................... 36
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 36
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 37
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 37
2.2.4 ROM Table ............................................................................................................................... 37
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 37
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 37
3 Memory Map ....................................................................................................................... 41
4 Interrupts ............................................................................................................................ 43
5 JTAG Interface .................................................................................................................... 46
5.1 Block Diagram .......................................................................................................................... 47
5.2 Functional Description ............................................................................................................... 47
5.2.1 JTAG Interface Pins .................................................................................................................. 48
5.2.2 JTAG TAP Controller ................................................................................................................. 49
5.2.3 Shift Registers .......................................................................................................................... 50
5.2.4 Operational Considerations ........................................................................................................ 50
5.3 Initialization and Configuration ................................................................................................... 53
5.4 Register Descriptions ................................................................................................................ 53
5.4.1 Instruction Register (IR) ............................................................................................................. 53
5.4.2 Data Registers .......................................................................................................................... 55
6 System Control ................................................................................................................... 57
6.1 Functional Description ............................................................................................................... 57
6.1.1 Device Identification .................................................................................................................. 57
6.1.2 Reset Control ............................................................................................................................ 57
March 17, 2008 3
Preliminary
LM3S8933 Microcontroller
6.1.3 Power Control ........................................................................................................................... 60
6.1.4 Clock Control ............................................................................................................................ 60
6.1.5 System Control ......................................................................................................................... 62
6.2 Initialization and Configuration ................................................................................................... 63
6.3 Register Map ............................................................................................................................ 64
6.4 Register Descriptions ................................................................................................................ 65
7 Hibernation Module .......................................................................................................... 119
7.1 Block Diagram ........................................................................................................................ 120
7.2 Functional Description ............................................................................................................. 120
7.2.1 Register Access Timing ........................................................................................................... 120
7.2.2 Clock Source .......................................................................................................................... 121
7.2.3 Battery Management ............................................................................................................... 121
7.2.4 Real-Time Clock ...................................................................................................................... 121
7.2.5 Non-Volatile Memory ............................................................................................................... 122
7.2.6 Power Control ......................................................................................................................... 122
7.2.7 Interrupts and Status ............................................................................................................... 122
7.3 Initialization and Configuration ................................................................................................. 123
7.3.1 Initialization ............................................................................................................................. 123
7.3.2 RTC Match Functionality (No Hibernation) ................................................................................ 123
7.3.3 RTC Match/Wake-Up from Hibernation ..................................................................................... 123
7.3.4 External Wake-Up from Hibernation .......................................................................................... 124
7.3.5 RTC/External Wake-Up from Hibernation .................................................................................. 124
7.4 Register Map .......................................................................................................................... 124
7.5 Register Descriptions .............................................................................................................. 125
8 Internal Memory ............................................................................................................... 138
8.1 Block Diagram ........................................................................................................................ 138
8.2 Functional Description ............................................................................................................. 138
8.2.1 SRAM Memory ........................................................................................................................ 138
8.2.2 Flash Memory ......................................................................................................................... 139
8.3 Flash Memory Initialization and Configuration ........................................................................... 140
8.3.1 Flash Programming ................................................................................................................. 140
8.3.2 Nonvolatile Register Programming ........................................................................................... 141
8.4 Register Map .......................................................................................................................... 141
8.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 142
8.6 Flash Register Descriptions (System Control Offset) .................................................................. 149
9 General-Purpose Input/Outputs (GPIOs) ....................................................................... 162
9.1 Functional Description ............................................................................................................. 162
9.1.1 Data Control ........................................................................................................................... 163
9.1.2 Interrupt Control ...................................................................................................................... 164
9.1.3 Mode Control .......................................................................................................................... 165
9.1.4 Commit Control ....................................................................................................................... 165
9.1.5 Pad Control ............................................................................................................................. 165
9.1.6 Identification ........................................................................................................................... 165
9.2 Initialization and Configuration ................................................................................................. 165
9.3 Register Map .......................................................................................................................... 167
9.4 Register Descriptions .............................................................................................................. 169
4 March 17, 2008
Preliminary
Table of Contents
10 General-Purpose Timers ................................................................................................. 204
10.1 Block Diagram ........................................................................................................................ 204
10.2 Functional Description ............................................................................................................. 205
10.2.1 GPTM Reset Conditions .......................................................................................................... 206
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 206
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 207
10.3 Initialization and Configuration ................................................................................................. 211
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 211
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 212
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 212
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 213
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 213
10.3.6 16-Bit PWM Mode ................................................................................................................... 214
10.4 Register Map .......................................................................................................................... 214
10.5 Register Descriptions .............................................................................................................. 215
11 Watchdog Timer ............................................................................................................... 240
11.1 Block Diagram ........................................................................................................................ 240
11.2 Functional Description ............................................................................................................. 240
11.3 Initialization and Configuration ................................................................................................. 241
11.4 Register Map .......................................................................................................................... 241
11.5 Register Descriptions .............................................................................................................. 242
12 Analog-to-Digital Converter (ADC) ................................................................................. 263
12.1 Block Diagram ........................................................................................................................ 264
12.2 Functional Description ............................................................................................................. 264
12.2.1 Sample Sequencers ................................................................................................................ 264
12.2.2 Module Control ........................................................................................................................ 265
12.2.3 Hardware Sample Averaging Circuit ......................................................................................... 266
12.2.4 Analog-to-Digital Converter ...................................................................................................... 266
12.2.5 Differential Sampling ............................................................................................................... 266
12.2.6 Test Modes ............................................................................................................................. 268
12.2.7 Internal Temperature Sensor .................................................................................................... 268
12.3 Initialization and Configuration ................................................................................................. 269
12.3.1 Module Initialization ................................................................................................................. 269
12.3.2 Sample Sequencer Configuration ............................................................................................. 269
12.4 Register Map .......................................................................................................................... 269
12.5 Register Descriptions .............................................................................................................. 270
13 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 296
13.1 Block Diagram ........................................................................................................................ 297
13.2 Functional Description ............................................................................................................. 297
13.2.1 Transmit/Receive Logic ........................................................................................................... 297
13.2.2 Baud-Rate Generation ............................................................................................................. 298
13.2.3 Data Transmission .................................................................................................................. 299
13.2.4 Serial IR (SIR) ......................................................................................................................... 299
13.2.5 FIFO Operation ....................................................................................................................... 300
13.2.6 Interrupts ................................................................................................................................ 300
13.2.7 Loopback Operation ................................................................................................................ 301
13.2.8 IrDA SIR block ........................................................................................................................ 301
13.3 Initialization and Configuration ................................................................................................. 301
March 17, 2008 5
Preliminary
LM3S8933 Microcontroller
13.4 Register Map .......................................................................................................................... 302
13.5 Register Descriptions .............................................................................................................. 303
14 Synchronous Serial Interface (SSI) ................................................................................ 337
14.1 Block Diagram ........................................................................................................................ 337
14.2 Functional Description ............................................................................................................. 337
14.2.1 Bit Rate Generation ................................................................................................................. 338
14.2.2 FIFO Operation ....................................................................................................................... 338
14.2.3 Interrupts ................................................................................................................................ 338
14.2.4 Frame Formats ....................................................................................................................... 339
14.3 Initialization and Configuration ................................................................................................. 346
14.4 Register Map .......................................................................................................................... 347
14.5 Register Descriptions .............................................................................................................. 348
15 Inter-Integrated Circuit (I2C) Interface ............................................................................ 374
15.1 Block Diagram ........................................................................................................................ 374
15.2 Functional Description ............................................................................................................. 374
15.2.1 I2C Bus Functional Overview .................................................................................................... 375
15.2.2 Available Speed Modes ........................................................................................................... 377
15.2.3 Interrupts ................................................................................................................................ 378
15.2.4 Loopback Operation ................................................................................................................ 378
15.2.5 Command Sequence Flow Charts ............................................................................................ 379
15.3 Initialization and Configuration ................................................................................................. 385
15.4 I2C Register Map ..................................................................................................................... 386
15.5 Register Descriptions (I2C Master) ........................................................................................... 387
15.6 Register Descriptions (I2C Slave) ............................................................................................. 400
16 Controller Area Network (CAN) Module ......................................................................... 409
16.1 Controller Area Network Overview ............................................................................................ 409
16.2 Controller Area Network Features ............................................................................................ 409
16.3 Controller Area Network Block Diagram .................................................................................... 410
16.4 Controller Area Network Functional Description ......................................................................... 410
16.4.1 Initialization ............................................................................................................................. 411
16.4.2 Operation ............................................................................................................................... 411
16.4.3 Transmitting Message Objects ................................................................................................. 412
16.4.4 Configuring a Transmit Message Object .................................................................................... 412
16.4.5 Updating a Transmit Message Object ....................................................................................... 413
16.4.6 Accepting Received Message Objects ...................................................................................... 413
16.4.7 Receiving a Data Frame .......................................................................................................... 413
16.4.8 Receiving a Remote Frame ...................................................................................................... 413
16.4.9 Receive/Transmit Priority ......................................................................................................... 414
16.4.10 Configuring a Receive Message Object .................................................................................... 414
16.4.11 Handling of Received Message Objects .................................................................................... 415
16.4.12 Handling of Interrupts .............................................................................................................. 415
16.4.13 Bit Timing Configuration Error Considerations ........................................................................... 416
16.4.14 Bit Time and Bit Rate ............................................................................................................... 416
16.4.15 Calculating the Bit Timing Parameters ...................................................................................... 418
16.5 Controller Area Network Register Map ...................................................................................... 420
16.6 Register Descriptions .............................................................................................................. 421
6 March 17, 2008
Preliminary
Table of Contents
17 Ethernet Controller .......................................................................................................... 449
17.1 Block Diagram ........................................................................................................................ 450
17.2 Functional Description ............................................................................................................. 450
17.2.1 Internal MII Operation .............................................................................................................. 450
17.2.2 PHY Configuration/Operation ................................................................................................... 451
17.2.3 MAC Configuration/Operation .................................................................................................. 452
17.2.4 Interrupts ................................................................................................................................ 455
17.3 Initialization and Configuration ................................................................................................. 455
17.4 Ethernet Register Map ............................................................................................................. 456
17.5 Ethernet MAC Register Descriptions ......................................................................................... 457
17.6 MII Management Register Descriptions ..................................................................................... 475
18 Analog Comparators ....................................................................................................... 494
18.1 Block Diagram ........................................................................................................................ 495
18.2 Functional Description ............................................................................................................. 495
18.2.1 Internal Reference Programming .............................................................................................. 497
18.3 Initialization and Configuration ................................................................................................. 498
18.4 Register Map .......................................................................................................................... 498
18.5 Register Descriptions .............................................................................................................. 499
19 Pin Diagram ...................................................................................................................... 507
20 Signal Tables .................................................................................................................... 509
20.1 100-Pin LQFP Package Pin Tables ........................................................................................... 509
20.2 108-Pin BGA Package Pin Tables ............................................................................................ 520
21 Operating Characteristics ............................................................................................... 534
22 Electrical Characteristics ................................................................................................ 535
22.1 DC Characteristics .................................................................................................................. 535
22.1.1 Maximum Ratings ................................................................................................................... 535
22.1.2 Recommended DC Operating Conditions .................................................................................. 535
22.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 536
22.1.4 Power Specifications ............................................................................................................... 536
22.1.5 Flash Memory Characteristics .................................................................................................. 538
22.2 AC Characteristics ................................................................................................................... 538
22.2.1 Load Conditions ...................................................................................................................... 538
22.2.2 Clocks .................................................................................................................................... 538
22.2.3 Analog-to-Digital Converter ...................................................................................................... 539
22.2.4 Analog Comparator ................................................................................................................. 540
22.2.5 I2C ......................................................................................................................................... 540
22.2.6 Ethernet Controller .................................................................................................................. 541
22.2.7 Hibernation Module ................................................................................................................. 544
22.2.8 Synchronous Serial Interface (SSI) ........................................................................................... 544
22.2.9 JTAG and Boundary Scan ........................................................................................................ 546
22.2.10 General-Purpose I/O ............................................................................................................... 547
22.2.11 Reset ..................................................................................................................................... 548
23 Package Information ........................................................................................................ 550
A Serial Flash Loader .......................................................................................................... 554
A.1 Serial Flash Loader ................................................................................................................. 554
A.2 Interfaces ............................................................................................................................... 554
March 17, 2008 7
Preliminary
LM3S8933 Microcontroller
A.2.1 UART ..................................................................................................................................... 554
A.2.2 SSI ......................................................................................................................................... 554
A.3 Packet Handling ...................................................................................................................... 555
A.3.1 Packet Format ........................................................................................................................ 555
A.3.2 Sending Packets ..................................................................................................................... 555
A.3.3 Receiving Packets ................................................................................................................... 555
A.4 Commands ............................................................................................................................. 556
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 556
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 556
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 556
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 557
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 557
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 557
B Register Quick Reference ............................................................................................... 559
C Ordering and Contact Information ................................................................................. 578
C.1 Ordering Information ................................................................................................................ 578
C.2 Kits ......................................................................................................................................... 578
C.3 Company Information .............................................................................................................. 579
C.4 Support Information ................................................................................................................. 579
8 March 17, 2008
Preliminary
Table of Contents
List of Figures
Figure 1-1. Stellaris® 8000 Series High-Level Block Diagram ............................................................... 28
Figure 2-1. CPU Block Diagram ......................................................................................................... 36
Figure 2-2. TPIU Block Diagram ........................................................................................................ 37
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 47
Figure 5-2. Test Access Port State Machine ....................................................................................... 50
Figure 5-3. IDCODE Register Format ................................................................................................. 55
Figure 5-4. BYPASS Register Format ................................................................................................ 56
Figure 5-5. Boundary Scan Register Format ....................................................................................... 56
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 58
Figure 6-2. Main Clock Tree .............................................................................................................. 61
Figure 7-1. Hibernation Module Block Diagram ................................................................................. 120
Figure 8-1. Flash Block Diagram ...................................................................................................... 138
Figure 9-1. GPIO Port Block Diagram ............................................................................................... 163
Figure 9-2. GPIODATA Write Example ............................................................................................. 164
Figure 9-3. GPIODATA Read Example ............................................................................................. 164
Figure 10-1. GPTM Module Block Diagram ........................................................................................ 205
Figure 10-2. 16-Bit Input Edge Count Mode Example .......................................................................... 209
Figure 10-3. 16-Bit Input Edge Time Mode Example ........................................................................... 210
Figure 10-4. 16-Bit PWM Mode Example ............................................................................................ 211
Figure 11-1. WDT Module Block Diagram .......................................................................................... 240
Figure 12-1. ADC Module Block Diagram ........................................................................................... 264
Figure 12-2. Differential Sampling Range, Vin(-) = 1.5 V ...................................................................... 267
Figure 12-3. Differential Sampling Range, Vin(-) = 0.75 V .................................................................... 267
Figure 12-4. Differential Sampling Range, Vin(-) = 2.25 V .................................................................... 268
Figure 12-5. Internal Temperature Sensor Characteristic ..................................................................... 268
Figure 13-1. UART Module Block Diagram ......................................................................................... 297
Figure 13-2. UART Character Frame ................................................................................................. 298
Figure 13-3. IrDA Data Modulation ..................................................................................................... 300
Figure 14-1. SSI Module Block Diagram ............................................................................................. 337
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 340
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 340
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 341
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 341
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 342
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 343
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 343
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 344
Figure 14-10. MICROWIRE Frame Format (Single Frame) .................................................................... 345
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 346
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 346
Figure 15-1. I2C Block Diagram ......................................................................................................... 374
Figure 15-2. I2C Bus Configuration .................................................................................................... 375
Figure 15-3. START and STOP Conditions ......................................................................................... 375
Figure 15-4. Complete Data Transfer with a 7-Bit Address ................................................................... 376
Figure 15-5. R/S Bit in First Byte ........................................................................................................ 376
March 17, 2008 9
Preliminary
LM3S8933 Microcontroller
Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 376
Figure 15-7. Master Single SEND ...................................................................................................... 379
Figure 15-8. Master Single RECEIVE ................................................................................................. 380
Figure 15-9. Master Burst SEND ....................................................................................................... 381
Figure 15-10. Master Burst RECEIVE .................................................................................................. 382
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 383
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 384
Figure 15-13. Slave Command Sequence ............................................................................................ 385
Figure 16-1. CAN Module Block Diagram ........................................................................................... 410
Figure 16-2. CAN Bit Time ................................................................................................................ 417
Figure 17-1. Ethernet Controller Block Diagram .................................................................................. 450
Figure 17-2. Ethernet Controller ......................................................................................................... 450
Figure 17-3. Ethernet Frame ............................................................................................................. 452
Figure 18-1. Analog Comparator Module Block Diagram ..................................................................... 495
Figure 18-2. Structure of Comparator Unit .......................................................................................... 496
Figure 18-3. Comparator Internal Reference Structure ........................................................................ 497
Figure 19-1. 100-Pin LQFP Package Pin Diagram .............................................................................. 507
Figure 19-2. 108-Ball BGA Package Pin Diagram (Top View) ............................................................... 508
Figure 22-1. Load Conditions ............................................................................................................ 538
Figure 22-2. I2C Timing ..................................................................................................................... 541
Figure 22-3. External XTLP Oscillator Characteristics ......................................................................... 543
Figure 22-4. Hibernation Module Timing ............................................................................................. 544
Figure 22-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 545
Figure 22-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 545
Figure 22-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 546
Figure 22-8. JTAG Test Clock Input Timing ......................................................................................... 547
Figure 22-9. JTAG Test Access Port (TAP) Timing .............................................................................. 547
Figure 22-10. JTAG TRST Timing ........................................................................................................ 547
Figure 22-11. External Reset Timing (RST) .......................................................................................... 548
Figure 22-12. Power-On Reset Timing ................................................................................................. 549
Figure 22-13. Brown-Out Reset Timing ................................................................................................ 549
Figure 22-14. Software Reset Timing ................................................................................................... 549
Figure 22-15. Watchdog Reset Timing ................................................................................................. 549
Figure 23-1. 100-Pin LQFP Package .................................................................................................. 550
Figure 23-2. 100-Ball BGA Package .................................................................................................. 552
10 March 17, 2008
Preliminary
Table of Contents
List of Tables
Table 1. Documentation Conventions ............................................................................................ 20
Table 3-1. Memory Map ................................................................................................................... 41
Table 4-1. Exception Types .............................................................................................................. 43
Table 4-2. Interrupts ........................................................................................................................ 44
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 48
Table 5-2. JTAG Instruction Register Commands ............................................................................... 53
Table 6-1. System Control Register Map ........................................................................................... 64
Table 7-1. Hibernation Module Register Map ................................................................................... 124
Table 8-1. Flash Protection Policy Combinations ............................................................................. 140
Table 8-2. Flash Resident Registers ............................................................................................... 141
Table 8-3. Flash Register Map ........................................................................................................ 141
Table 9-1. GPIO Pad Configuration Examples ................................................................................. 166
Table 9-2. GPIO Interrupt Configuration Example ............................................................................ 166
Table 9-3. GPIO Register Map ....................................................................................................... 168
Table 10-1. Available CCP Pins ........................................................................................................ 205
Table 10-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 208
Table 10-3. Timers Register Map ...................................................................................................... 214
Table 11-1. Watchdog Timer Register Map ........................................................................................ 241
Table 12-1. Samples and FIFO Depth of Sequencers ........................................................................ 264
Table 12-2. Differential Sampling Pairs ............................................................................................. 266
Table 12-3. ADC Register Map ......................................................................................................... 269
Table 13-1. UART Register Map ....................................................................................................... 302
Table 14-1. SSI Register Map .......................................................................................................... 347
Table 15-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 377
Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 386
Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 391
Table 16-1. Transmit Message Object Bit Settings ............................................................................. 412
Table 16-2. Receive Message Object Bit Settings .............................................................................. 414
Table 16-3. CAN Protocol Ranges .................................................................................................... 417
Table 16-4. CAN Register Map ......................................................................................................... 420
Table 17-1. TX & RX FIFO Organization ........................................................................................... 453
Table 17-2. Ethernet Register Map ................................................................................................... 456
Table 18-1. Comparator 0 Operating Modes ..................................................................................... 496
Table 18-2. Comparator 1 Operating Modes ..................................................................................... 496
Table 18-3. Comparator 2 Operating Modes ...................................................................................... 497
Table 18-4. Internal Reference Voltage and ACREFCTL Field Values ................................................. 497
Table 18-5. Analog Comparators Register Map ................................................................................. 499
Table 20-1. Signals by Pin Number ................................................................................................... 509
Table 20-2. Signals by Signal Name ................................................................................................. 513
Table 20-3. Signals by Function, Except for GPIO ............................................................................. 517
Table 20-4. GPIO Pins and Alternate Functions ................................................................................. 519
Table 20-5. Signals by Pin Number ................................................................................................... 520
Table 20-6. Signals by Signal Name ................................................................................................. 525
Table 20-7. Signals by Function, Except for GPIO ............................................................................. 529
Table 20-8. GPIO Pins and Alternate Functions ................................................................................. 532
Table 21-1. Temperature Characteristics ........................................................................................... 534
March 17, 2008 11
Preliminary
LM3S8933 Microcontroller
Table 21-2. Thermal Characteristics ................................................................................................. 534
Table 22-1. Maximum Ratings .......................................................................................................... 535
Table 22-2. Recommended DC Operating Conditions ........................................................................ 535
Table 22-3. LDO Regulator Characteristics ....................................................................................... 536
Table 22-4. Detailed Power Specifications ........................................................................................ 537
Table 22-5. Flash Memory Characteristics ........................................................................................ 538
Table 22-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 538
Table 22-7. Clock Characteristics ..................................................................................................... 538
Table 22-8. Crystal Characteristics ................................................................................................... 539
Table 22-9. ADC Characteristics ....................................................................................................... 539
Table 22-10. Analog Comparator Characteristics ................................................................................. 540
Table 22-11. Analog Comparator Voltage Reference Characteristics .................................................... 540
Table 22-12. I2C Characteristics ......................................................................................................... 540
Table 22-13. 100BASE-TX Transmitter Characteristics ........................................................................ 541
Table 22-14. 100BASE-TX Transmitter Characteristics (informative) ..................................................... 541
Table 22-15. 100BASE-TX Receiver Characteristics ............................................................................ 541
Table 22-16. 10BASE-T Transmitter Characteristics ............................................................................ 541
Table 22-17. 10BASE-T Transmitter Characteristics (informative) ......................................................... 542
Table 22-18. 10BASE-T Receiver Characteristics ................................................................................ 542
Table 22-19. Isolation Transformers ................................................................................................... 542
Table 22-20. Ethernet Reference Crystal ............................................................................................ 543
Table 22-21. External XTLP Oscillator Characteristics ......................................................................... 543
Table 22-22. Hibernation Module Characteristics ................................................................................. 544
Table 22-23. SSI Characteristics ........................................................................................................ 544
Table 22-24. JTAG Characteristics ..................................................................................................... 546
Table 22-25. GPIO Characteristics ..................................................................................................... 548
Table 22-26. Reset Characteristics ..................................................................................................... 548
Table C-1. Part Ordering Information ............................................................................................... 578
12 March 17, 2008
Preliminary
Table of Contents
List of Registers
System Control .............................................................................................................................. 57
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 66
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 68
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 69
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 70
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 71
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 72
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 73
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 74
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 78
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 79
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 81
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 82
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 84
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 85
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 87
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 89
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 91
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 93
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 95
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 97
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 99
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 102
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 105
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 108
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 110
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 112
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 114
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 115
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 117
Hibernation Module ..................................................................................................................... 119
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 126
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 127
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 128
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 129
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 130
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 132
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 133
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 134
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 135
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 136
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 137
Internal Memory ........................................................................................................................... 138
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 143
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 144
March 17, 2008 13
Preliminary
LM3S8933 Microcontroller
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 145
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 147
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 148
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 149
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 150
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 151
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 152
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 153
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 154
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 155
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 156
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 157
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 158
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 159
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 160
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 161
General-Purpose Input/Outputs (GPIOs) ................................................................................... 162
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 170
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 171
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 172
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 173
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 174
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 175
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 176
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 177
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 178
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 179
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 181
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 182
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 183
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 184
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 185
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 186
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 187
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 188
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 189
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 190
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 192
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 193
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 194
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 195
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 196
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 197
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 198
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 199
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 200
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 201
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 202
14 March 17, 2008
Preliminary
Table of Contents
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 203
General-Purpose Timers ............................................................................................................. 204
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 216
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 217
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 219
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 221
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 224
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 226
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 227
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 228
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 230
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 231
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 232
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 233
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 234
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 235
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 236
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 237
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 238
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 239
Watchdog Timer ........................................................................................................................... 240
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 243
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 244
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 245
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 246
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 247
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 248
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 249
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 250
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 251
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 252
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 253
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 254
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 255
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 256
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 257
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 258
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 259
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 260
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 261
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 262
Analog-to-Digital Converter (ADC) ............................................................................................. 263
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 271
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 272
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 273
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 274
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 275
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 276
March 17, 2008 15
Preliminary
LM3S8933 Microcontroller
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 279
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 280
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 281
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 282
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 283
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 285
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 288
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 288
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 288
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 288
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 289
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 289
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 289
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 289
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 290
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 290
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 291
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 291
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 293
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 294
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 295
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 296
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 304
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 306
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 308
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 310
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 311
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 312
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 313
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 315
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 317
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 319
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 321
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 322
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 323
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 325
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 326
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 327
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 328
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 329
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 330
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 331
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 332
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 333
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 334
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 335
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 336
16 March 17, 2008
Preliminary
Table of Contents
Synchronous Serial Interface (SSI) ............................................................................................ 337
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 349
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 351
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 353
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 354
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 356
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 357
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 359
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 360
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 361
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 362
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 363
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 364
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 365
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 366
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 367
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 368
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 369
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 370
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 371
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 372
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 373
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 374
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 388
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 389
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 393
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 394
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 395
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 396
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 397
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 398
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 399
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 401
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 402
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 404
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 405
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 406
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 407
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 408
Controller Area Network (CAN) Module ..................................................................................... 409
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 422
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 424
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 427
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 428
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 430
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 431
Register 7: CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 433
March 17, 2008 17
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LM3S8933 Microcontroller
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 434
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 434
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 435
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 435
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 438
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 438
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 439
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 439
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 440
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 440
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 441
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 441
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 442
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 442
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 444
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 444
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 444
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 444
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 444
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 444
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 444
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 444
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 445
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 445
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 446
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 446
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 447
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 447
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 448
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 448
Ethernet Controller ...................................................................................................................... 449
Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 458
Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 460
Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 461
Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 462
Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 463
Register 6: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 464
Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 466
Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 467
Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 468
Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 469
Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 470
Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 471
Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 472
Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 473
Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 474
Register 16: Ethernet MAC Timer Support (MACTS), offset 0x03C ...................................................... 475
Register 17: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 476
18 March 17, 2008
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Table of Contents
Register 18: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 478
Register 19: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 480
Register 20: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 481
Register 21: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 482
Register 22: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 484
Register 23: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 485
Register 24: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 486
Register 25: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address
0x11 .............................................................................................................................. 488
Register 26: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 490
Register 27: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 491
Register 28: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 492
Register 29: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 493
Analog Comparators ................................................................................................................... 494
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 500
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 501
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 502
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 503
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 504
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 504
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60 ....................................................... 504
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 505
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 505
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64 ...................................................... 505
March 17, 2008 19
Preliminary
LM3S8933 Microcontroller
About This Document
This data sheet provides reference information for the LM3S8933 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■ ARM® Cortex™-M3 Technical Reference Manual
■ ARM® CoreSight Technical Reference Manual
■ ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 20.
Table 1. Documentation Conventions
Notation Meaning
General Register Notation
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
REGISTER
bit A single bit in a register.
bit field Two or more consecutive and related bits.
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 41.
offset 0xnnn
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Register N
20 March 17, 2008
Preliminary
About This Document
Notation Meaning
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
reserved
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
yy:xx
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Register Bit/Field
Types
RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO Software can read this field. Always write the chip reset value.
R/W Software can read or write this field.
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1C
Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
R/W1S
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
W1C
WO Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field This value in the register bit diagram shows the bit/field value after any reset, unless noted.
Reset Value
0 Bit cleared to 0 on chip reset.
1 Bit set to 1 on chip reset.
- Nondeterministic.
Pin/Signal Notation
[ ] Pin alternate function; a pin defaults to the signal without the brackets.
pin Refers to the physical connection on the package.
signal Refers to the electrical signal encoding of a pin.
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
assert a signal
deassert a signal Change the value of the signal from the logically True state to the logically False state.
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
SIGNAL
Numbers
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
X
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
0x
March 17, 2008 21
Preliminary
LM3S8933 Microcontroller
1 Architectural Overview
The Luminary Micro Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The Stellaris® family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris® LM3S8000 series combines Bosch Controller Area Network technology
with both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer.
The LM3S8933 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S8933 microcontroller features
a Battery-backed Hibernation module to efficiently power down the LM3S8933 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S8933 microcontroller perfectly for
battery applications.
In addition, the LM3S8933 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S8933 microcontroller is code-compatible
to all members of the extensive Stellaris® family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network. See “Ordering and Contact Information” on page 578 for
ordering information for Stellaris® family devices.
1.1 Product Features
The LM3S8933 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
22 March 17, 2008
Preliminary
Architectural Overview
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 32 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
– 256 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 64 KB single-cycle SRAM
■ General-Purpose Timers
– Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
• To trigger analog-to-digital conversions
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
• ADC event trigger
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
March 17, 2008 23
Preliminary
LM3S8933 Microcontroller
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ Controller Area Network (CAN)
– Supports CAN protocol version 2.0 part A/B
– Bit rates up to 1Mb/s
– 32 message objects, each with its own identifier mask
– Maskable interrupt
– Disable automatic retransmission mode for TTCAN
– Programmable loop-back mode for self-test operation
■ 10/100 Ethernet Controller
– Conforms to the IEEE 802.3-2002 Specification
– Hardware assistance for IEEE 1588-2002 Precision Time Protocol (PTP)
– Full- and half-duplex for both 100 Mbps and 10 Mbps operation
– Integrated 10/100 Mbps Transceiver (PHY)
– Automatic MDI/MDI-X cross-over correction
– Programmable MAC address
24 March 17, 2008
Preliminary
Architectural Overview
– Power-saving and power-down modes
■ Synchronous Serial Interface (SSI)
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Two fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator allowing speeds up to 3.125 Mbps
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ ADC
– Single- and differential-input configurations
– Four 10-bit channels (inputs) when used as single-ended inputs
– Sample rate of one million samples/second
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Each sequence triggered by software or internal event (timers, analog comparators, or GPIO)
– On-chip temperature sensor
■ Analog Comparators
– Three independent integrated analog comparators
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LM3S8933 Microcontroller
– Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
– Compare external pin input to external pin input or to internal programmable voltage reference
■ I2C
– Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
– Interrupt generation
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ GPIOs
– 6-36 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
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– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial and extended temperature 100-pin RoHS-compliant LQFP package
■ Industrial-range 108-ball RoHS-compliant BGA package
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
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LM3S8933 Microcontroller
1.3 High-Level Block Diagram
Figure 1-1 on page 28 represents the full set of features in the Stellaris® 8000 series of devices;
not all features may be available on the LM3S8933 microcontroller.
Figure 1-1. Stellaris® 8000 Series High-Level Block Diagram
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S8933 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 578.
28 March 17, 2008
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Architectural Overview
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 35)
All members of the Stellaris® product family, including the LM3S8933 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 35 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S8933 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 32 interrupts.
“Interrupts” on page 43 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S8933 controller features Pulse Width Modulation (PWM) outputs.
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
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LM3S8933 Microcontroller
On the LM3S8933, PWM motion control functionality can be achieved through:
■ The motion control features of the general-purpose timers using the CCP pins
CCP Pins (see page 210)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.3 Analog Peripherals
To handle analog signals, the LM3S8933 microcontroller offers an Analog-to-Digital Converter
(ADC).
For support of analog signals, the LM3S8933 microcontroller offers three analog comparators.
1.4.3.1 ADC (see page 263)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The LM3S8933 ADC module features 10-bit conversion resolution and supports four input channels,
plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up
to eight analog input sources without controller intervention. Each sample sequence provides flexible
programming with fully configurable input source, trigger events, interrupt generation, and sequence
priority.
1.4.3.2 Analog Comparators (see page 494)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S8933 microcontroller provides three independent integrated analog comparators that can
be configured to drive an output or generate an interrupt or ADC event.
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
1.4.4 Serial Communications Peripherals
The LM3S8933 controller supports both asynchronous and synchronous serial communications
with:
■ Two fully programmable 16C550-type UARTs
■ One SSI module
■ One I2C module
30 March 17, 2008
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■ One CAN unit
■ Ethernet controller
1.4.4.1 UART (see page 296)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S8933 controller includes two fully programmable 16C550-type UARTs that support data
transfer speeds up to 3.125 Mbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.4.2 SSI (see page 337)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S8933 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.4.3 I2C (see page 374)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL).
The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking
devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and
diagnostic purposes in product development and manufacture.
The LM3S8933 controller includes one I2C module that provides the ability to communicate to other
IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write
and read) data.
Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive,
Slave Transmit, and Slave Receive.
A Stellaris® I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
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LM3S8933 Microcontroller
Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error). The I2C slave generates
interrupts when data has been sent or requested by a master.
1.4.4.4 Controller Area Network (see page 409)
Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair
wire. Originally created for automotive purposes, now it is used in many embedded control
applications (for example, industrial or medical). Bit rates up to 1Mb/s are possible at network lengths
below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kb/s at
500m).
A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis
of the identifier received whether it should process the message. The identifier also determines the
priority that the message enjoys in competition for bus access. Each CAN message can transmit
from 0 to 8 bytes of user information. The LM3S8933 includes one CAN units.
1.4.4.5 Ethernet Controller (see page 449)
Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet
has been standardized as IEEE 802.3. It defines a number of wiring and signaling standards for the
physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer,
and a common addressing format.
The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and
network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3
specifications and fully supports 10BASE-T and 100BASE-TX standards. In addition, the Ethernet
Controller supports automatic MDI/MDI-X cross-over correction.
1.4.5 System Peripherals
1.4.5.1 Programmable GPIOs (see page 162)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris® GPIO module is comprised of seven physical GPIO blocks, each corresponding to
an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation
IP for Real-Time Microcontrollers specification) and supports 6-36 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page
509 for the signals available to each GPIO pin).
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines.
1.4.5.2 Four Programmable Timers (see page 204)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris® General-Purpose Timer Module (GPTM) contains four GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
Timers can also be used to trigger analog-to-digital (ADC) conversions.
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
32 March 17, 2008
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Architectural Overview
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.5.3 Watchdog Timer (see page 240)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
The Stellaris® Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
1.4.6 Memory Peripherals
The LM3S8933 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.6.1 SRAM (see page 138)
The LM3S8933 static random access memory (SRAM) controller supports 64 KB SRAM. The internal
SRAM of the Stellaris® devices is located at offset 0x0000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
1.4.6.2 Flash (see page 139)
The LM3S8933 Flash controller supports 256 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
1.4.7 Additional Features
1.4.7.1 Memory Map (see page 41)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S8933 controller can be found in “Memory Map” on page 41. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
1.4.7.2 JTAG TAP Controller (see page 46)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
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LM3S8933 Microcontroller
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is composed of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
1.4.7.3 System Control and Clocks (see page 57)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
1.4.7.4 Hibernation Module (see page 119)
The Hibernation module provides logic to switch power off to the main processor and peripherals,
and to wake on external or time-based events. The Hibernation module includes power-sequencing
logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt
signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used
for saving state during hibernation.
1.4.8 Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 507
■ “Signal Tables” on page 509
■ “Operating Characteristics” on page 534
■ “Electrical Characteristics” on page 535
■ “Package Information” on page 550
34 March 17, 2008
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Architectural Overview
2 ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that
meets the needs of minimal memory implementation, reduced pin count, and low power consumption,
while delivering outstanding computational performance and exceptional system response to
interrupts. Features include:
■ Compact core.
■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of
memory for microcontroller class applications.
■ Rapid application execution through Harvard architecture characterized by separate buses for
instruction and data.
■ Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.
■ Migration from the ARM7™ processor family for better performance and power efficiency.
■ Full-featured debug solution with a:
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
■ Optimized for single-cycle flash usage
■ Three sleep modes with clock gating for low power
■ Single-cycle multiply instruction and hardware divide
■ Atomic operations
■ ARM Thumb2 mixed 16-/32-bit instruction set
■ 1.25 DMIPS/MHz
The Stellaris® family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motors.
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LM3S8933 Microcontroller
For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference
Manual.
2.1 Block Diagram
Figure 2-1. CPU Block Diagram
Private Peripheral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
Instrumentation
Trace Macrocell
Trace
Port
Interface
Unit
CM3 Core
Instructions Data
Flash
Patch and
Breakpoint
Memory
Protection
Unit
Adv. High-
Perf. Bus
Access Port
Nested
Vectored
Interrupt
Controller
Serial Wire JTAG
Debug Port
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
ROM
Table
Private
Peripheral
Bus
(external)
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex-M3
2.2 Functional Description
Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
This section describes the Stellaris® implementation.
Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 36. As
noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are
flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested
Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.
2.2.1 Serial Wire and JTAG Debug
Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the
ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris® devices.
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ARM Cortex-M3 Processor Core
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
2.2.2 Embedded Trace Macrocell (ETM)
ETM was not implemented in the Stellaris® devices. This means Chapters 15 and 16 of the ARM®
Cortex™-M3 Technical Reference Manual can be ignored.
2.2.3 Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer. The Stellaris® devices have implemented TPIU as shown in Figure 2-2 on page 37.
This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference
Manual, however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
ATB
Interface
Asynchronous FIFO
APB
Interface
Trace Out
(serializer)
Debug
ATB
Slave
Port
APB
Slave
Port
Serial Wire
Trace Port
(SWO)
2.2.4 ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
2.2.5 Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S8933 controller and supports the standard
ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for
protection regions, overlapping protection regions, access permissions, and exporting memory
attributes to the system.
2.2.6 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
■ Facilitates low-latency exception and interrupt handling
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■ Controls power management
■ Implements system control registers
The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of
priority. The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge
of the stacked (nested) interrupts to enable tail-chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode
if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference
Manual). Any other user-mode access causes a bus fault.
All NVIC registers are accessible using byte, halfword, and word unless otherwise stated.
2.2.6.1 Interrupts
The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts
and interrupt priorities. The LM3S8933 microcontroller supports 32 interrupts with eight priority
levels.
2.2.6.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
Functional Description
The timer consists of three registers:
■ A control and status counter to configure its clock, enable the counter, enable the SysTick
interrupt, and determine counter status.
■ The reload value for the counter, used to provide the counter's wrap value.
■ The current value of the counter.
A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris® devices.
When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value
in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks.
Writing a value of zero to the Reload Value register disables the counter on the next wrap. When
the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
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ARM Cortex-M3 Processor Core
Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write
does not trigger the SysTick exception logic. On a read, the current value is the value of the register
at the time the register is accessed.
If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect
to a reference clock. The reference clock can be the core clock or an external clock source.
SysTick Control and Status Register
Use the SysTick Control and Status Register to enable the SysTick features. The reset is
0x0000.0000.
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
31:17 reserved RO 0
Count Flag
Returns 1 if timer counted to 0 since last time this was read. Clears on read by
application. If read by the debugger using the DAP, this bit is cleared on read-only
if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the
COUNTFLAG bit is not changed by the debugger read.
16 COUNTFLAG R/W 0
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
15:3 reserved RO 0
Clock Source
Value Description
0 External reference clock. (Not implemented for Stellaris microcontrollers.)
1 Core clock
If no reference clock is provided, it is held at 1 and so gives the same time as the
core clock. The core clock must be at least 2.5 times faster than the reference clock.
If it is not, the count values are unpredictable.
2 CLKSOURCE R/W 0
Tick Int
Value Description
Counting down to 0 does not pend the SysTick handler. Software can use
the COUNTFLAG to determine if ever counted to 0.
0
1 Counting down to 0 pends the SysTick handler.
1 TICKINT R/W 0
Enable
Value Description
0 Counter disabled.
Counter operates in a multi-shot way. That is, counter loads with the Reload
value and then begins counting down. On reaching 0, it sets the
COUNTFLAG to 1 and optionally pends the SysTick handler, based on
TICKINT. It then loads the Reload value again, and begins counting.
1
0 ENABLE R/W 0
SysTick Reload Value Register
Use the SysTick Reload Value Register to specify the start value to load into the current value
register when the counter reaches 0. It can be any value between 1 and 0x00FF.FFFF. A start value
March 17, 2008 39
Preliminary
LM3S8933 Microcontroller
of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated
when counting from 1 to 0.
Therefore, as a multi-shot timer, repeated over and over, it fires every N+1 clock pulse, where N is
any value from 1 to 0x00FF.FFFF. So, if the tick interrupt is required every 100 clock pulses, 99
must be written into the RELOAD. If a new value is written on each tick interrupt, so treated as single
shot, then the actual count down must be written. For example, if a tick is next required after 400
clock pulses, 400 must be written into the RELOAD.
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a read-modify-write
operation.
31:24 reserved RO 0
Reload
Value to load into the SysTick Current Value Register when the counter reaches 0.
23:0 RELOAD W1C -
SysTick Current Value Register
Use the SysTick Current Value Register to find the current value in the register.
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
31:24 reserved RO 0
Current Value
Current value at the time the register is accessed. No read-modify-write protection is
provided, so change with care.
This register is write-clear. Writing to it with any value clears the register to 0. Clearing
this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
23:0 CURRENT W1C -
SysTick Calibration Value Register
The SysTick Calibration Value register is not implemented.
40 March 17, 2008
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ARM Cortex-M3 Processor Core
3 Memory Map
The memory map for the LM3S8933 controller is provided in Table 3-1 on page 41.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Important: In Table 3-1 on page 41, addresses not listed are reserved.
Table 3-1. Memory Mapa
For details on
registers, see
page ...
Start End Description
Memory
0x0000.0000 0x0003.FFFF On-chip flash b 142
0x0004.0000 0x00FF.FFFF Reserved -
0x0100.0000 0x1FFF.FFFF Reserved -
0x2000.0000 0x2000.FFFF Bit-banded on-chip SRAMc 142
0x2001.0000 0x200F.FFFF Reserved -
0x2010.0000 0x21FF.FFFF Reserved -
0x2200.0000 0x221F.FFFF Bit-band alias of 0x2000.0000 through 0x200F.FFFF 138
0x2220.0000 0x3FFF.FFFF Reserved -
FiRM Peripherals
0x4000.0000 0x4000.0FFF Watchdog timer 242
0x4000.1000 0x4000.3FFF Reserved -
0x4000.4000 0x4000.4FFF GPIO Port A 169
0x4000.5000 0x4000.5FFF GPIO Port B 169
0x4000.6000 0x4000.6FFF GPIO Port C 169
0x4000.7000 0x4000.7FFF GPIO Port D 169
0x4000.8000 0x4000.8FFF SSI0 348
0x4000.A000 0x4000.BFFF Reserved -
0x4000.C000 0x4000.CFFF UART0 303
0x4000.D000 0x4000.DFFF UART1 303
0x4000.F000 0x4000.FFFF Reserved -
0x4001.0000 0x4001.FFFF Reserved -
Peripherals
0x4002.0000 0x4002.07FF I2C Master 0 387
0x4002.0800 0x4002.0FFF I2C Slave 0 400
0x4002.2000 0x4002.3FFF Reserved -
0x4002.4000 0x4002.4FFF GPIO Port E 169
0x4002.5000 0x4002.5FFF GPIO Port F 169
0x4002.6000 0x4002.6FFF GPIO Port G 169
0x4002.9000 0x4002.BFFF Reserved -
0x4002.E000 0x4002.FFFF Reserved -
March 17, 2008 41
Preliminary
LM3S8933 Microcontroller
For details on
registers, see
page ...
Start End Description
0x4003.0000 0x4003.0FFF Timer0 215
0x4003.1000 0x4003.1FFF Timer1 215
0x4003.2000 0x4003.2FFF Timer2 215
0x4003.3000 0x4003.3FFF Timer3 215
0x4003.4000 0x4003.7FFF Reserved -
0x4003.8000 0x4003.8FFF ADC 270
0x4003.9000 0x4003.BFFF Reserved -
0x4003.C000 0x4003.CFFF Analog Comparators 494
0x4003.D000 0x4003.FFFF Reserved -
0x4004.0000 0x4004.0FFF CAN0 Controller 421
0x4004.3000 0x4004.7FFF Reserved -
0x4004.8000 0x4004.8FFF Ethernet Controller 457
0x4004.9000 0x4004.BFFF Reserved -
0x4004.C000 0x4004.FFFF Reserved -
0x4005.1000 0x4005.3FFF Reserved -
0x4005.4000 0x4005.7FFF Reserved -
0x4006.0000 0x400F.BFFF Reserved -
0x400F.C000 0x400F.CFFF Hibernation Module 125
0x400F.D000 0x400F.DFFF Flash control 142
0x400F.E000 0x400F.EFFF System control 65
0x4010.0000 0x41FF.FFFF Reserved -
0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF -
0x4400.0000 0x5FFF.FFFF Reserved -
0x6000.0000 0xDFFF.FFFF Reserved -
Private Peripheral Bus
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM)
0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT)
0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB)
0xE000.3000 0xE000.DFFF Reserved
0xE000.E000 0xE000.EFFF Nested Vectored Interrupt Controller (NVIC)
0xE000.F000 0xE003.FFFF Reserved
0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU)
0xE004.1000 0xFFFF.FFFF Reserved -
a. All reserved space returns a bus fault when read or written.
b. The unavailable flash will bus fault throughout this range.
c. The unavailable SRAM will bus fault throughout this range.
42 March 17, 2008
Preliminary
Memory Map
4 Interrupts
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions. All exceptions are handled in Handler Mode. The processor state is
automatically stored to the stack on an exception, and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which
enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back
interrupts to be performed without the overhead of state saving and restoration.
Table 4-1 on page 43 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 32 interrupts (listed in Table 4-2 on page 44).
Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts
are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt
Priority registers. You also can group priorities by splitting priority levels into pre-emption priorities
and subpriorities. All of the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt
Controller” in the ARM® Cortex™-M3 Technical Reference Manual.
Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and
a Hard Fault. Note that 0 is the default priority for all the settable priorities.
If you assign the same priority level to two or more interrupts, their hardware priority (the lower
position number) determines the order in which the processor activates them. For example, if both
GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority.
See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM®
Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts.
Note: In Table 4-2 on page 44 interrupts not listed are reserved.
Table 4-1. Exception Types
Exception Type Position Prioritya Description
- 0 - Stack top is loaded from first entry of vector table on reset.
Invoked on power up and warm reset. On first instruction, drops to lowest
priority (and then is called the base level of activation). This is
asynchronous.
Reset 1 -3 (highest)
Cannot be stopped or preempted by any exception but reset. This is
asynchronous.
An NMI is only producible by software, using the NVIC Interrupt Control
State register.
Non-Maskable 2 -2
Interrupt (NMI)
All classes of Fault, when the fault cannot activate due to priority or the
configurable fault handler has been disabled. This is synchronous.
Hard Fault 3 -1
MPU mismatch, including access violation and no match. This is
synchronous.
The priority of this exception can be changed.
Memory Management 4 settable
Pre-fetch fault, memory access fault, and other address/memory related
faults. This is synchronous when precise and asynchronous when
imprecise.
You can enable or disable this fault.
Bus Fault 5 settable
Usage fault, such as undefined instruction executed or illegal state
transition attempt. This is synchronous.
Usage Fault 6 settable
- 7-10 - Reserved.
SVCall 11 settable System service call with SVC instruction. This is synchronous.
March 17, 2008 43
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LM3S8933 Microcontroller
Exception Type Position Prioritya Description
Debug monitor (when not halting). This is synchronous, but only active
when enabled. It does not activate if lower priority than the current
activation.
Debug Monitor 12 settable
- 13 - Reserved.
Pendable request for system service. This is asynchronous and only
pended by software.
PendSV 14 settable
SysTick 15 settable System tick timer has fired. This is asynchronous.
Asserted from outside the ARM Cortex-M3 core and fed through the NVIC
(prioritized). These are all asynchronous. Table 4-2 on page 44 lists the
interrupts on the LM3S8933 controller.
16 and settable
above
Interrupts
a. 0 is the default priority for all the settable priorities.
Table 4-2. Interrupts
Interrupt (Bit in Interrupt Registers) Description
0 GPIO Port A
1 GPIO Port B
2 GPIO Port C
3 GPIO Port D
4 GPIO Port E
5 UART0
6 UART1
7 SSI0
8 I2C0
14 ADC Sequence 0
15 ADC Sequence 1
16 ADC Sequence 2
17 ADC Sequence 3
18 Watchdog timer
19 Timer0 A
20 Timer0 B
21 Timer1 A
22 Timer1 B
23 Timer2 A
24 Timer2 B
25 Analog Comparator 0
26 Analog Comparator 1
27 Analog Comparator 2
28 System Control
29 Flash Control
30 GPIO Port F
31 GPIO Port G
35 Timer3 A
36 Timer3 B
39 CAN0
44 March 17, 2008
Preliminary
Interrupts
Interrupt (Bit in Interrupt Registers) Description
42 Ethernet Controller
43 Hibernation Module
March 17, 2008 45
Preliminary
LM3S8933 Microcontroller
5 JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially
into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent
on the current state of the TAP controller. For detailed information on the operation of the JTAG
port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
The JTAG module has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions:
– BYPASS instruction
– IDCODE instruction
– SAMPLE/PRELOAD instruction
– EXTEST instruction
– INTEST instruction
■ ARM additional instructions:
– APACC instruction
– DPACC instruction
– ABORT instruction
■ Integrated ARM Serial Wire Debug (SWD)
See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG
controller.
46 March 17, 2008
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JTAG Interface
5.1 Block Diagram
Figure 5-1. JTAG Module Block Diagram
Instruction Register (IR)
TAP Controller
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TCK
TMS
TDI
TDO
Cortex-M3
Debug
Port
TRST
5.2 Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 47. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and
TMS inputs. The current state of the TAP controller depends on the current value of TRST and the
sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when
the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel
load registers. The current state of the TAP controller also determines whether the Instruction
Register (IR) chain or one of the Data Register (DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 5-2 on page 53 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 546 for JTAG timing diagrams.
March 17, 2008 47
Preliminary
LM3S8933 Microcontroller
5.2.1 JTAG Interface Pins
The JTAG interface consists of five standard pins: TRST,TCK, TMS, TDI, and TDO. These pins and
their associated reset state are given in Table 5-1 on page 48. Detailed information on each pin
follows.
Table 5-1. JTAG Port Pins Reset State
Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value
TRST Input Enabled Disabled N/A N/A
TCK Input Enabled Disabled N/A N/A
TMS Input Enabled Disabled N/A N/A
TDI Input Enabled Disabled N/A N/A
TDO Output Enabled Disabled 2-mA driver High-Z
5.2.1.1 Test Reset Input (TRST)
The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP
controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the
Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters
the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction,
IDCODE.
By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled
on PB7/TRST; otherwise JTAG communication could be lost.
5.2.1.2 Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers
that are daisy-chained together can synchronously communicate serial test data between
components. During normal operation, TCK is driven by a free-running clock with a nominal 50%
duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK
is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction
and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no
clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down
resistors can be turned off to save internal power as long as the TCK pin is constantly being driven
by an external source.
5.2.1.3 Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered.
Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the
value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can
be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine
can be seen in its entirety in Figure 5-2 on page 50.
48 March 17, 2008
Preliminary
JTAG Interface
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost.
5.2.1.4 Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on
the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling
edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost.
5.2.1.5 Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the
pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states.
5.2.2 JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 5-2 on page 50. The TAP controller
state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR)
or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module
to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed
information on the function of the TAP controller and the operations that occur in each state, please
refer to IEEE Standard 1149.1.
March 17, 2008 49
Preliminary
LM3S8933 Microcontroller
Figure 5-2. Test Access Port State Machine
Test Logic Reset
Run Test Idle Select DR Scan Select IR Scan
Capture DR Capture IR
Shift DR Shift IR
Exit 1 DR Exit 1 IR
Exit 2 DR Exit 2 IR
Pause DR Pause IR
Update DR Update IR
1 1 1
1 1
1
1 1
1 1
1 1
1 1
1 0 1 0
0 0
0 0
0 0
0 0
0 0
0 0
0
0
5.2.3 Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 53.
5.2.4 Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG pins
can be programmed to be GPIOs, board configuration and reset conditions on these pins must be
considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the
method for switching between these two operational modes is described below.
50 March 17, 2008
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JTAG Interface
5.2.4.1 GPIO Functionality
When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting
GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate
hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and
PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging
or board-level testing, this provides five more GPIOs for use in the design.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors,
and apply RST or power-cycle the part.
In addition, it is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 190) have been set to 1.
Recovering a "Locked" Device
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug sequence that can be used to recover the device. Performing
a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset
mass erases the flash memory. The sequence to recover the device is:
1. Assert and hold the RST signal.
2. Perform the JTAG-to-SWD switch sequence.
3. Perform the SWD-to-JTAG switch sequence.
4. Perform the JTAG-to-SWD switch sequence.
5. Perform the SWD-to-JTAG switch sequence.
6. Perform the JTAG-to-SWD switch sequence.
7. Perform the SWD-to-JTAG switch sequence.
8. Perform the JTAG-to-SWD switch sequence.
9. Perform the SWD-to-JTAG switch sequence.
10. Perform the JTAG-to-SWD switch sequence.
11. Perform the SWD-to-JTAG switch sequence.
March 17, 2008 51
Preliminary
LM3S8933 Microcontroller
12. Release the RST signal.
The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug
(SWD)” on page 52. When performing switch sequences for the purpose of recovering the debug
capabilities of the device, only steps 1 and 2 of the switch sequence need to be performed.
5.2.4.2 ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller
in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the
following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test
Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run
Test Idle, Select DR, Select IR, and Test Logic Reset states.
Stepping through this sequences of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
probability of this sequence occurring during normal operation of the TAP controller, it should not
affect normal performance of the JTAG interface.
JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in SWD mode, before sending the switch sequence, the SWD goes into the line reset
state.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to JTAG mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
52 March 17, 2008
Preliminary
JTAG Interface
2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C.
3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic
Reset state.
5.3 Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. This is done by enabling the five JTAG
pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register.
5.4 Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The registers
can be broken down into two main categories: Instruction Registers and Data Registers.
5.4.1 Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register
connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct
states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the
chain and updated, they are interpreted as the current instruction. The decode of the Instruction
Register bits is shown in Table 5-2 on page 53. A detailed explanation of each instruction, along
with its associated Data Register, follows.
Table 5-2. JTAG Instruction Register Commands
IR[3:0] Instruction Description
Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD
instruction onto the pads.
0000 EXTEST
Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD
instruction into the controller.
0001 INTEST
Captures the current I/O values and shifts the sampled values out of the Boundary Scan
Chain while new preload data is shifted in.
0010 SAMPLE / PRELOAD
1000 ABORT Shifts data into the ARM Debug Port Abort Register.
1010 DPACC Shifts data into and out of the ARM DP Access Register.
1011 APACC Shifts data into and out of the ARM AC Access Register.
Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE
chain and shifts it out.
1110 IDCODE
1111 BYPASS Connects TDI to TDO through a single Shift Register chain.
All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO.
5.4.1.1 EXTEST Instruction
The EXTEST instruction does not have an associated Data Register chain. The EXTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. This allows
March 17, 2008 53
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tests to be developed that drive known values out of the controller, which can be used to verify
connectivity.
5.4.1.2 INTEST Instruction
The INTEST instruction does not have an associated Data Register chain. The INTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. This allows tests
to be developed that drive known values into the controller, which can be used for testing. It is
important to note that although the RST input pin is on the Boundary Scan Data Register chain, it
is only observable.
5.4.1.3 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data
Register” on page 56 for more information.
5.4.1.4 ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. Please see the “ABORT Data Register” on page 56 for more
information.
5.4.1.5 DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. Please see “DPACC
Data Register” on page 56 for more information.
5.4.1.6 APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
Please see “APACC Data Register” on page 56 for more information.
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5.4.1.7 IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure their input and output data streams. IDCODE is the default instruction that is loaded into
the JTAG Instruction Register when a power-on-reset (POR) is asserted, TRST is asserted, or the
Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 55 for more
information.
5.4.1.8 BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 55 for
more information.
5.4.2 Data Registers
The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan,
APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed
in the following sections.
5.4.2.1 IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-3 on page 55. The standard requires that every JTAG-compliant device implement either
the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This allows auto configuration test tools to determine which instruction is the default instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly, and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x3BA00477. This value indicates an ARM Cortex-M3, Version 1
processor. This allows the debuggers to automatically configure themselves to work correctly with
the Cortex-M3 during debug.
Figure 5-3. IDCODE Register Format
Version Part Number Manufacturer ID 1
31 28 27 12 11 1 0
TDI TDO
5.4.2.2 BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-4 on page 56. The standard requires that every JTAG-compliant device implement either
the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This allows auto configuration test tools to determine which instruction is the default instruction.
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LM3S8933 Microcontroller
Figure 5-4. BYPASS Register Format
TDI 0 TDO
0
5.4.2.3 Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 56. Each GPIO
pin, in a counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data
Register. Each GPIO pin has three associated digital signals that are included in the chain. These
signals are input, output, and output enable, and are arranged in that order as can be seen in the
figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because
the reset pin is always an input, only the input signal is included in the Data Register chain.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.
Figure 5-5. Boundary Scan Register Format
O TDO TDI O IN
E UT
O O IN
U E
T
O O IN
E UT
O O IN
U E
T
I
N ... ...
GPIO PB6 GPIO m RST GPIO m+1 GPIO n
For detailed information on the order of the input, output, and output enable bits for each of the
GPIO ports, please refer to the Stellaris® Family Boundary Scan Description Language (BSDL) files,
downloadable from www.luminarymicro.com.
5.4.2.4 APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.5 DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.6 ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
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6 System Control
System control determines the overall operation of the device. It provides information about the
device, controls the clocking to the core and individual peripherals, and handles reset detection and
reporting.
6.1 Functional Description
The System Control module provides the following capabilities:
■ Device identification, see “Device Identification” on page 57
■ Local control, such as reset (see “Reset Control” on page 57), power (see “Power
Control” on page 60) and clock control (see “Clock Control” on page 60)
■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 62
6.1.1 Device Identification
Seven read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers.
6.1.2 Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
6.1.2.1 CMOD0 and CMOD1 Test-Mode Control Pins
Two pins, CMOD0 and CMOD1, are defined for use by Luminary Micro for testing the devices during
manufacture. They have no end-user function and should not be used. The CMOD pins should be
connected to ground.
6.1.2.2 Reset Sources
The controller has five sources of reset:
1. External reset input pin (RST) assertion, see “RST Pin Assertion” on page 57.
2. Power-on reset (POR), see “Power-On Reset (POR)” on page 58.
3. Internal brown-out (BOR) detector, see “Brown-Out Reset (BOR)” on page 58.
4. Software-initiated reset (with the software reset registers), see “Software Reset” on page 59.
5. A watchdog timer reset condition violation, see “Watchdog Timer Reset” on page 59.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator.
6.1.2.3 RST Pin Assertion
The external reset pin (RST) resets the controller. This resets the core and all the peripherals except
the JTAG TAP controller (see “JTAG Interface” on page 46). The external reset sequence is as
follows:
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1. The external reset pin (RST) is asserted and then de-asserted.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
A few clocks cycles from RST de-assertion to the start of the reset sequence is necessary for
synchronization.
The external reset timing is shown in Figure 22-11 on page 548.
6.1.2.4 Power-On Reset (POR)
The Power-On Reset (POR) circuit monitors the power supply voltage (VDD). The POR circuit
generates a reset signal to the internal logic when the power supply ramp reaches a threshold value
(VTH). If the application only uses the POR circuit, the RST input needs to be connected to the power
supply (VDD) through a pull-up resistor (1K to 10K Ω).
The device must be operating within the specified operating parameters at the point when the on-chip
power-on reset pulse is complete. The 3.3-V power supply to the device must reach 3.0 V within
10 msec of it crossing 2.0 V to guarantee proper operation. For applications that require the use of
an external reset to hold the device in reset longer than the internal POR, the RST input may be
used with the circuit as shown in Figure 6-1 on page 58.
Figure 6-1. External Circuitry to Extend Reset
R1
C1
R2
RST
Stellaris
D1
The R1 and C1 components define the power-on delay. The R2 resistor mitigates any leakage from
the RST input. The diode (D1) discharges C1 rapidly when the power supply is turned off.
The Power-On Reset sequence is as follows:
1. The controller waits for the later of external reset (RST) or internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing
is shown in Figure 22-12 on page 549.
Note: The power-on reset also resets the JTAG controller. An external reset does not.
6.1.2.5 Brown-Out Reset (BOR)
A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops
below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may
generate a controller interrupt or a system reset.
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Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset.
The brown-out reset is equivelent to an assertion of the external RST input and the reset is held
active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt
handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to
determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 22-13 on page 549.
6.1.2.6 Software Reset
Software can reset a specific peripheral or generate a reset to the entire system .
Peripherals can be individually reset by software via three registers that control reset signals to each
peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and
subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with
the encoding of the clock gating control for peripherals and on-chip functions (see “System
Control” on page 62). Note that all reset signals for all clocks of the specified unit are asserted as
a result of a software-initiated reset.
The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is deasserted and the controller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
The software-initiated system reset timing is shown in Figure 22-14 on page 549.
6.1.2.7 Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts
down to its zero state again before the first time-out interrupt is cleared, and the reset signal has
been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset
sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the controller loads from memory the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
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The watchdog reset timing is shown in Figure 22-15 on page 549.
6.1.3 Power Control
The Stellaris® microcontroller provides an integrated LDO regulator that may be used to provide
power to the majority of the controller's internal logic. The LDO regulator provides software a
mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V
to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ
field in the LDO Power Control (LDOPCTL) register.
Note: The use of the LDO is optional. The internal logic may be supplied by the on-chip LDO or
by an external regulator. If the LDO is used, the LDO output pin is connected to the VDD25
pins on the printed circuit board. The LDO requires decoupling capacitors on the printed
circuit board. If an external regulator is used, it is strongly recommended that the external
regulator supply the controller only and not be shared with other devices on the printed
circuit board.
6.1.4 Clock Control
System control determines the control of clocks in this part.
6.1.4.1 Fundamental Clock Sources
There are four clock sources for use in the device:
■ Internal Oscillator (IOSC): The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
Applications that do not depend on accurate clock sources may use this clock source to reduce
system cost. The internal oscillator is the clock source the device uses during and following POR.
If the main oscillator is required, software must enable the main oscillator following reset and
allow the main oscillator to stabilize before changing the clock reference.
■ Main Oscillator (MOSC): The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. The crystal value
allowed depends on whether the main oscillator is used as the clock reference source to the
PLL. If so, the crystal must be one of the supported frequencies between 3.579545 MHz through
8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC
through the specified speed of the device. The supported crystals are listed in the XTAL bit field
in the RCC register (see page 74).
■ Internal 30-kHz Oscillator: The internal 30-kHz oscillator is similar to the internal oscillator,
except that it provides an operational frequency of 30 kHz ± 30%. It is intended for use during
Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal
switching and also allows the main oscillator to be powered down.
■ External Real-Time Oscillator: The external real-time oscillator provides a low-frequency,
accurate clock reference. It is intended to provide the system with a real-time clock source. The
real-time oscillator is part of the Hibernation Module (“Hibernation Module” on page 119) and may
also provide an accurate source of Deep-Sleep or Hibernate mode power savings.
The internal system clock (SysClk), is derived from any of the four sources plus two others: the
output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The
frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive).
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The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options.
Figure 6-2 on page 61 shows the logic for the main clock tree. The peripheral blocks are driven by
the system clock signal and can be programmatically enabled/disabled. The ADC clock signal is
automatically divided down to 16 MHz for proper ADC operation.
Figure 6-2. Main Clock Tree
PLL
(240 MHz) ÷ 4
PLL
Main OSC (400 MHz)
Internal
OSC
(12 MHz)
Internal
OSC
(30 kHz)
÷ 4
Hibernation
Module
(32.768 kHz)
÷ 25
PWRDN
ADC Clock
System Clock
USB Clock
XTALa
USBPWRDNc
XTALa
PWRDN b
MOSCDIS a
IOSCDISa
OSCSRCb,d
BYPASS b,d
SYSDIVb,d
USESYSDIV a,d
PWMDW a
USEPWMDIVa
PWM Clock
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
6.1.4.2 Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise,
the range of supported crystals is 1 to 8.192 MHz.
The XTAL bit in the RCC register (see page 74) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
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6.1.4.3 Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software configures the main PLL input reference clock source, specifies the output divisor
to set the system clock frequency, and enables the main PLL to drive the output.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 78). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency.
The Crystal Value field (XTAL) on page 74 describes the available crystal choices and default
programming of the PLLCFG register. The crystal number is written into the XTAL field of the
Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings
are translated and the internal PLL settings are updated.
6.1.4.4 PLL Modes
The PLL has two modes of operation: Normal and Power-Down
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 74 and page 79).
6.1.4.5 PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
22-6 on page 538). During the relock time, the affected PLL is not usable as a clock reference.
The PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■ Change in the PLL from Power-Down to Normal mode.
A counter is defined to measure the TREADY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is set
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). . Hardware is provided to
keep the PLL from being used as a system clock until the TREADY condition is met after one of the
two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator)
before the RCC/RCC2 register is switched to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the controller from the source to the PLL until the main PLL is
stable (TREADY time met), after which it changes to the PLL. Software can use many methods to
ensure that the system is clocked from the main PLL, including periodically polling the PLLLRIS bit
in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock interrupt.
6.1.5 System Control
For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep
mode, respectively.
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In Run mode, the processor executes code. In Sleep mode, the clock frequency of the active
peripherals is unchanged, but the processor is not clocked and therefore no longer executes code.
In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the
Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns
the device to Run mode from one of the sleep modes; the sleep modes are entered on request from
the code. Each mode is described in more detail below.
There are four levels of operation for the device defined as:
■ Run Mode. Run mode provides normal operation of the processor and all of the peripherals that
are currently enabled by the RCGCn registers. The system clock can be any of the available
clock sources including the PLL.
■ Sleep Mode. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for
Interrupt) instruction. Any properly configured interrupt event in the system will bring the
processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3
Technical Reference Manual for more details.
In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked.
Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
■ Deep-Sleep Mode. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in
the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any
properly configured interrupt event in the system will bring the processor back into Run mode.
See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual
for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up,
if necessary, and the main oscillator is powered down. If the PLL is running at the time of the
WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active
RCC/RCC2 register to be /16 or /64, respectively. When the Deep-Sleep exit event occurs,
hardware brings the system clock back to the source and frequency it had at the onset of
Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep
duration.
■ Hibernate Mode. In this mode, the power supplies are turned off to the main part of the device
and only the Hibernation module's circuitry is active. An external wake event or RTC event is
required to bring the device back to Run mode. The Cortex-M3 processor and peripherals outside
of the Hibernation module see a normal "power on" sequence and the processor starts running
code. It can determine that it has been restarted from Hibernate mode by inspecting the
Hibernation module registers.
6.2 Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
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1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source (using the
main oscillator or internal oscillator) and allows for the new PLL configuration to be validated
before switching the system clock to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
6.3 Register Map
Table 6-1 on page 64 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use by Luminary Micro, Inc. Software should not modify any reserved memory
address.
Table 6-1. System Control Register Map
See
Offset Name Type Reset Description page
0x000 DID0 RO - Device Identification 0 66
0x004 DID1 RO - Device Identification 1 82
0x008 DC0 RO 0x00FF.007F Device Capabilities 0 84
0x010 DC1 RO 0x0101.33FF Device Capabilities 1 85
0x014 DC2 RO 0x070F.1013 Device Capabilities 2 87
0x018 DC3 RO 0x0F0F.3FC0 Device Capabilities 3 89
0x01C DC4 RO 0x5100.007F Device Capabilities 4 91
0x030 PBORCTL R/W 0x0000.7FFD Brown-Out Reset Control 68
0x034 LDOPCTL R/W 0x0000.0000 LDO Power Control 69
0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 114
0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 115
0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 117
0x050 RIS RO 0x0000.0000 Raw Interrupt Status 70
0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 71
0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 72
0x05C RESC R/W - Reset Cause 73
64 March 17, 2008
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System Control
See
Offset Name Type Reset Description page
0x060 RCC R/W 0x0780.3AD1 Run-Mode Clock Configuration 74
0x064 PLLCFG RO - XTAL to PLL Translation 78
0x070 RCC2 R/W 0x0780.2800 Run-Mode Clock Configuration 2 79
0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 93
0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 99
0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 108
0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 95
0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 102
0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 110
0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 97
0x124 DCGC1 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 105
0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 112
0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 81
6.4 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
March 17, 2008 65
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LM3S8933 Microcontroller
Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the device.
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved VER reserved CLASS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJOR MINOR
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows:
Value Description
0x1 Second version of the DID0 register format.
30:28 VER RO 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:24 reserved RO 0x0
Device Class
The CLASS field value identifies the internal design from which all mask
sets are generated for all devices in a particular product line. The CLASS
field value is changed for new product lines, for changes in fab process
(for example, a remap or shrink), or any case where the MAJOR or MINOR
fields require differentiation from prior devices. The value of the CLASS
field is encoded as follows (all other encodings are reserved):
Value Description
0x1 Stellaris® Fury-class devices.
23:16 CLASS RO 0x1
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System Control
Bit/Field Name Type Reset Description
Major Revision
This field specifies the major revision number of the device. The major
revision reflects changes to base layers of the design. The major revision
number is indicated in the part number as a letter (A for first revision, B
for second, and so on). This field is encoded as follows:
Value Description
0x0 Revision A (initial device)
0x1 Revision B (first base layer revision)
0x2 Revision C (second base layer revision)
and so on.
15:8 MAJOR RO -
Minor Revision
This field specifies the minor revision number of the device. The minor
revision reflects changes to the metal layers of the design. The MINOR
field value is reset when the MAJOR field is changed. This field is numeric
and is encoded as follows:
Value Description
0x0 Initial device, or a major revision update.
0x1 First metal layer change.
0x2 Second metal layer change.
and so on.
7:0 MINOR RO -
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LM3S8933 Microcontroller
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BORIOR reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x0
BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the controller. If set, a
reset is signaled. Otherwise, an interrupt is signaled.
1 BORIOR R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
68 March 17, 2008
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System Control
Register 3: LDO Power Control (LDOPCTL), offset 0x034
The VADJ field in this register adjusts the on-chip output voltage (VOUT).
LDO Power Control (LDOPCTL)
Base 0x400F.E000
Offset 0x034
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved VADJ
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0
LDO Output Voltage
This field sets the on-chip output voltage. The programming values for
the VADJ field are provided below.
Value VOUT (V)
0x00 2.50
0x01 2.45
0x02 2.40
0x03 2.35
0x04 2.30
0x05 2.25
0x06-0x3F Reserved
0x1B 2.75
0x1C 2.70
0x1D 2.65
0x1E 2.60
0x1F 2.55
5:0 VADJ R/W 0x0
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LM3S8933 Microcontroller
Register 4: Raw Interrupt Status (RIS), offset 0x050
Central location for system control raw interrupts. These are set and cleared by hardware.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLRIS reserved BORRIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Raw Interrupt Status
This bit is set when the PLL TREADY Timer asserts.
6 PLLLRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
Brown-Out Reset Raw Interrupt Status
This bit is the raw interrupt status for any brown-out conditions. If set,
a brown-out condition is currently active. This is an unregistered signal
from the brown-out detection circuit. An interrupt is reported if the BORIM
bit in the IMC register is set and the BORIOR bit in the PBORCTL register
is cleared.
1 BORRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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System Control
Register 5: Interrupt Mask Control (IMC), offset 0x054
Central location for system control interrupt masks.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLIM reserved BORIM reserved
Type RO RO RO RO RO RO RO RO RO R/W RO RO RO RO R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Interrupt Mask
This bit specifies whether a current limit detection is promoted to a
controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS
is set; otherwise, an interrupt is not generated.
6 PLLLIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
Brown-Out Reset Interrupt Mask
This bit specifies whether a brown-out condition is promoted to a
controller interrupt. If set, an interrupt is generated if BORRIS is set;
otherwise, an interrupt is not generated.
1 BORIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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LM3S8933 Microcontroller
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
Central location for system control result of RIS AND IMC to generate an interrupt to the controller.
All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS
register (see page 70).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLMIS reserved BORMIS reserved
Type RO RO RO RO RO RO RO RO RO R/W1C RO RO RO RO R/W1C RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Masked Interrupt Status
This bit is set when the PLL TREADY timer asserts. The interrupt is cleared
by writing a 1 to this bit.
6 PLLLMIS R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
BOR Masked Interrupt Status
The BORMIS is simply the BORRIS ANDed with the mask value, BORIM.
1 BORMIS R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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System Control
Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an external reset is the cause, and then
all the other bits in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved LDO SW WDT BOR POR EXT
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0
LDO Reset
When set, indicates the LDO circuit has lost regulation and has
generated a reset event.
5 LDO R/W -
Software Reset
When set, indicates a software reset is the cause of the reset event.
4 SW R/W -
Watchdog Timer Reset
When set, indicates a watchdog reset is the cause of the reset event.
3 WDT R/W -
Brown-Out Reset
When set, indicates a brown-out reset is the cause of the reset event.
2 BOR R/W -
Power-On Reset
When set, indicates a power-on reset is the cause of the reset event.
1 POR R/W -
External Reset
When set, indicates an external reset (RST assertion) is the cause of
the reset event.
0 EXT R/W -
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LM3S8933 Microcontroller
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x0780.3AD1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved ACG SYSDIV USESYSDIV reserved
Type RO RO RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWRDN reserved BYPASS reserved XTAL OSCSRC reserved IOSCDIS MOSCDIS
Type RO RO R/W RO R/W RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W
Reset 0 0 1 1 1 0 1 0 1 1 0 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:28 reserved RO 0x0
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.
27 ACG R/W 0
74 March 17, 2008
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System Control
Bit/Field Name Type Reset Description
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
Value Divisor (BYPASS=1) Frequency (BYPASS=0)
0x0 reserved reserved
0x1 /2 reserved
0x2 /3 reserved
0x3 /4 50 MHz
0x4 /5 40 MHz
0x5 /6 33.33 MHz
0x6 /7 28.57 MHz
0x7 /8 25 MHz
0x8 /9 22.22 MHz
0x9 /10 20 MHz
0xA /11 18.18 MHz
0xB /12 16.67 MHz
0xC /13 15.38 MHz
0xD /14 14.29 MHz
0xE /15 13.33 MHz
0xF /16 12.5 MHz (default)
When reading the Run-Mode Clock Configuration (RCC) register (see
page 74), the SYSDIV value is MINSYSDIV if a lower divider was
requested and the PLL is being used. This lower value is allowed to
divide a non-PLL source.
26:23 SYSDIV R/W 0xF
Enable System Clock Divider
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
22 USESYSDIV R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
21:14 reserved RO 0
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
13 PWRDN R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12 reserved RO 1
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LM3S8933 Microcontroller
Bit/Field Name Type Reset Description
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
Note: The ADC must be clocked from the PLL or directly from a
14-MHz to 18-MHz clock source to operate properly. While
the ADC works in a 14-18 MHz range, to maintain a 1 M
sample/second rate, the ADC must be provided a 16-MHz
clock source.
11 BYPASS R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10 reserved RO 0
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below.
Crystal Frequency (MHz)
Using the PLL
Crystal Frequency (MHz)
Not Using the PLL
Value
0x0 1.000 reserved
0x1 1.8432 reserved
0x2 2.000 reserved
0x3 2.4576 reserved
0x4 3.579545 MHz
0x5 3.6864 MHz
0x6 4 MHz
0x7 4.096 MHz
0x8 4.9152 MHz
0x9 5 MHz
0xA 5.12 MHz
0xB 6 MHz (reset value)
0xC 6.144 MHz
0xD 7.3728 MHz
0xE 8 MHz
0xF 8.192 MHz
9:6 XTAL R/W 0xB
Oscillator Source
Picks among the four input sources for the OSC. The values are:
Value Input Source
0x0 Main oscillator
0x1 Internal oscillator (default)
0x2 Internal oscillator / 4 (this is necessary if used as input to PLL)
0x3 reserved
5:4 OSCSRC R/W 0x1
76 March 17, 2008
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System Control
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0x0
Internal Oscillator Disable
0: Internal oscillator (IOSC) is enabled.
1: Internal oscillator is disabled.
1 IOSCDIS R/W 0
Main Oscillator Disable
0: Main oscillator is enabled .
1: Main oscillator is disabled (default).
0 MOSCDIS R/W 1
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LM3S8933 Microcontroller
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 74).
The PLL frequency is calculated using the PLLCFG field values, as follows:
PLLFreq = OSCFreq * F / (R + 1)
XTAL to PLL Translation (PLLCFG)
Base 0x400F.E000
Offset 0x064
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved F R
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x0
PLL F Value
This field specifies the value supplied to the PLL’s F input.
13:5 F RO -
PLL R Value
This field specifies the value supplied to the PLL’s R input.
4:0 R RO -
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System Control
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields when the USERCC2 bit is set. This allows
RCC2 to be used to extend the capabilities, while also providing a means to be backward-compatible
to previous parts. The fields within the RCC2 register occupy the same bit positions as they do
within the RCC register as LSB-justified.
The SYSDIV2 field is wider so that additional larger divisors are possible. This allows a lower system
clock frequency for improved Deep Sleep power consumption.
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x0780.2800
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USERCC2 reserved SYSDIV2 reserved
Type R/W RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWRDN2 reserved BYPASS2 reserved OSCSRC2 reserved
Type RO RO R/W RO R/W RO RO RO RO R/W R/W R/W RO RO RO RO
Reset 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Use RCC2
When set, overrides the RCC register fields.
31 USERCC2 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30:29 reserved RO 0x0
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
This field is wider than the RCC register SYSDIV field in order to provide
additional divisor values. This permits the system clock to be run at
much lower frequencies during Deep Sleep mode. For example, where
the RCC register SYSDIV encoding of 1111 provides /16, the RCC2
register SYSDIV2 encoding of 111111 provides /64.
28:23 SYSDIV2 R/W 0x0F
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:14 reserved RO 0x0
Power-Down PLL
When set, powers down the PLL.
13 PWRDN2 R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12 reserved RO 0
Bypass PLL
When set, bypasses the PLL for the clock source.
11 BYPASS2 R/W 1
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LM3S8933 Microcontroller
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10:7 reserved RO 0x0
System Clock Source
Value Description
0x0 Main oscillator (MOSC)
0x1 Internal oscillator (IOSC)
0x2 Internal oscillator / 4
0x3 30 kHz internal oscillator
0x7 32 kHz external oscillator
6:4 OSCSRC2 R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0
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System Control
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved DSDIVORIDE reserved
Type RO RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DSOSCSRC reserved
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:29 reserved RO 0x0
Divider Field Override
6-bit system divider field to override when Deep-Sleep occurs with PLL
running.
28:23 DSDIVORIDE R/W 0x0F
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:7 reserved RO 0x0
Clock Source
When set, forces IOSC to be clock source during Deep Sleep mode.
Value Name Description
0x0 NOORIDE No override to the oscillator clock source is done
0x1 IOSC Use internal 12 MHz oscillator as source
0x3 30kHz Use 30 kHz internal oscillator
0x7 32kHz Use 32 kHz external oscillator
6:4 DSOSCSRC R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0x0
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Register 12: Device Identification 1 (DID1), offset 0x004
This register identifies the device family, part number, temperature range, pin count, and package
type.
Device Identification 1 (DID1)
Base 0x400F.E000
Offset 0x004
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VER FAM PARTNO
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOUNT reserved TEMP PKG ROHS QUAL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 0 0 0 0 0 - - - - - 1 - -
Bit/Field Name Type Reset Description
DID1 Version
This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Value Description
0x1 Second version of the DID1 register format.
31:28 VER RO 0x1
Family
This field provides the family identification of the device within the
Luminary Micro product portfolio. The value is encoded as follows (all
other encodings are reserved):
Value Description
Stellaris family of microcontollers, that is, all devices with
external part numbers starting with LM3S.
0x0
27:24 FAM RO 0x0
Part Number
This field provides the part number of the device within the family. The
value is encoded as follows (all other encodings are reserved):
Value Description
0x8C LM3S8933
23:16 PARTNO RO 0x8C
Package Pin Count
This field specifies the number of pins on the device package. The value
is encoded as follows (all other encodings are reserved):
Value Description
0x2 100-pin or 108-ball package
15:13 PINCOUNT RO 0x2
82 March 17, 2008
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12:8 reserved RO 0
Temperature Range
This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x0 Commercial temperature range (0°C to 70°C)
0x1 Industrial temperature range (-40°C to 85°C)
0x2 Extended temperature range (-40°C to 105°C)
7:5 TEMP RO -
Package Type
This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):
Value Description
0x0 SOIC package
0x1 LQFP package
0x2 BGA package
4:3 PKG RO -
RoHS-Compliance
This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.
2 ROHS RO 1
Qualification Status
This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x0 Engineering Sample (unqualified)
0x1 Pilot Production (unqualified)
0x2 Fully Qualified
1:0 QUAL RO -
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Register 13: Device Capabilities 0 (DC0), offset 0x008
This register is predefined by the part and can be used to verify features.
Device Capabilities 0 (DC0)
Base 0x400F.E000
Offset 0x008
Type RO, reset 0x00FF.007F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRAMSZ
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASHSZ
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
SRAM Size
Indicates the size of the on-chip SRAM memory.
Value Description
0x00FF 64 KB of SRAM
31:16 SRAMSZ RO 0x00FF
Flash Size
Indicates the size of the on-chip flash memory.
Value Description
0x007F 256 KB of Flash
15:0 FLASHSZ RO 0x007F
84 March 17, 2008
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System Control
Register 14: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: CANs, PWM,
ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the
maximum clock frequency and maximum ADC sample rate. The format of this register is consistent
with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control
register.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0101.33FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved CAN0 reserved ADC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MINSYSDIV MAXADCSPD MPU HIB TEMPSNS PLL WDT SWO SWD JTAG
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:25 reserved RO 0
CAN Module 0 Present
When set, indicates that CAN unit 0 is present.
24 CAN0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:17 reserved RO 0
ADC Module Present
When set, indicates that the ADC module is present.
16 ADC RO 1
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4.
15:12 MINSYSDIV RO 0x3
Max ADC Speed
Indicates the maximum rate at which the ADC samples data.
Value Description
0x3 1M samples/second
11:8 MAXADCSPD RO 0x3
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Bit/Field Name Type Reset Description
MPU Present
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the ARM Cortex-M3 Technical Reference Manual
for details on the MPU.
7 MPU RO 1
Hibernation Module Present
When set, indicates that the Hibernation module is present.
6 HIB RO 1
Temp Sensor Present
When set, indicates that the on-chip temperature sensor is present.
5 TEMPSNS RO 1
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
4 PLL RO 1
Watchdog Timer Present
When set, indicates that a watchdog timer is present.
3 WDT RO 1
SWO Trace Port Present
When set, indicates that the Serial Wire Output (SWO) trace port is
present.
2 SWO RO 1
SWD Present
When set, indicates that the Serial Wire Debugger (SWD) is present.
1 SWD RO 1
JTAG Present
When set, indicates that the JTAG debugger interface is present.
0 JTAG RO 1
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System Control
Register 15: Device Capabilities 2 (DC2), offset 0x014
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register
is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software
reset control register.
Device Capabilities 2 (DC2)
Base 0x400F.E000
Offset 0x014
Type RO, reset 0x070F.1013
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C0 reserved SSI0 reserved UART1 UART0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Present
When set, indicates that analog comparator 2 is present.
26 COMP2 RO 1
Analog Comparator 1 Present
When set, indicates that analog comparator 1 is present.
25 COMP1 RO 1
Analog Comparator 0 Present
When set, indicates that analog comparator 0 is present.
24 COMP0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:20 reserved RO 0
Timer 3 Present
When set, indicates that General-Purpose Timer module 3 is present.
19 TIMER3 RO 1
Timer 2 Present
When set, indicates that General-Purpose Timer module 2 is present.
18 TIMER2 RO 1
Timer 1 Present
When set, indicates that General-Purpose Timer module 1 is present.
17 TIMER1 RO 1
Timer 0 Present
When set, indicates that General-Purpose Timer module 0 is present.
16 TIMER0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
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Bit/Field Name Type Reset Description
I2C Module 0 Present
When set, indicates that I2C module 0 is present.
12 I2C0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:5 reserved RO 0
SSI0 Present
When set, indicates that SSI module 0 is present.
4 SSI0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
UART1 Present
When set, indicates that UART module 1 is present.
1 UART1 RO 1
UART0 Present
When set, indicates that UART module 0 is present.
0 UART0 RO 1
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System Control
Register 16: Device Capabilities 3 (DC3), offset 0x018
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os.
Device Capabilities 3 (DC3)
Base 0x400F.E000
Offset 0x018
Type RO, reset 0x0F0F.3FC0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved CCP3 CCP2 CCP1 CCP0 reserved ADC3 ADC2 ADC1 ADC0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved C2PLUS C2MINUS C1O C1PLUS C1MINUS C0O C0PLUS C0MINUS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:28 reserved RO 0
CCP3 Pin Present
When set, indicates that Capture/Compare/PWM pin 3 is present.
27 CCP3 RO 1
CCP2 Pin Present
When set, indicates that Capture/Compare/PWM pin 2 is present.
26 CCP2 RO 1
CCP1 Pin Present
When set, indicates that Capture/Compare/PWM pin 1 is present.
25 CCP1 RO 1
CCP0 Pin Present
When set, indicates that Capture/Compare/PWM pin 0 is present.
24 CCP0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:20 reserved RO 0
ADC3 Pin Present
When set, indicates that ADC pin 3 is present.
19 ADC3 RO 1
ADC2 Pin Present
When set, indicates that ADC pin 2 is present.
18 ADC2 RO 1
ADC1 Pin Present
When set, indicates that ADC pin 1 is present.
17 ADC1 RO 1
ADC0 Pin Present
When set, indicates that ADC pin 0 is present.
16 ADC0 RO 1
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:14 reserved RO 0
C2+ Pin Present
When set, indicates that the analog comparator 2 (+) input pin is present.
13 C2PLUS RO 1
C2- Pin Present
When set, indicates that the analog comparator 2 (-) input pin is present.
12 C2MINUS RO 1
C1o Pin Present
When set, indicates that the analog comparator 1 output pin is present.
11 C1O RO 1
C1+ Pin Present
When set, indicates that the analog comparator 1 (+) input pin is present.
10 C1PLUS RO 1
C1- Pin Present
When set, indicates that the analog comparator 1 (-) input pin is present.
9 C1MINUS RO 1
C0o Pin Present
When set, indicates that the analog comparator 0 output pin is present.
8 C0O RO 1
C0+ Pin Present
When set, indicates that the analog comparator 0 (+) input pin is present.
7 C0PLUS RO 1
C0- Pin Present
When set, indicates that the analog comparator 0 (-) input pin is present.
6 C0MINUS RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:0 reserved RO 0
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System Control
Register 17: Device Capabilities 4 (DC4), offset 0x01C
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Ethernet MAC
and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2,
and DCGC2 clock control registers and the SRCR2 software reset control register.
Device Capabilities 4 (DC4)
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x5100.007F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved E1588 reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
Ethernet PHY0 Present
When set, indicates that Ethernet PHY module 0 is present.
30 EPHY0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
Ethernet MAC0 Present
When set, indicates that Ethernet MAC module 0 is present.
28 EMAC0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:25 reserved RO 0
1588 Capable
When set, indicates that that EMAC0 is 1588-capable.
24 E1588 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:7 reserved RO 0
GPIO Port G Present
When set, indicates that GPIO Port G is present.
6 GPIOG RO 1
GPIO Port F Present
When set, indicates that GPIO Port F is present.
5 GPIOF RO 1
GPIO Port E Present
When set, indicates that GPIO Port E is present.
4 GPIOE RO 1
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Bit/Field Name Type Reset Description
GPIO Port D Present
When set, indicates that GPIO Port D is present.
3 GPIOD RO 1
GPIO Port C Present
When set, indicates that GPIO Port C is present.
2 GPIOC RO 1
GPIO Port B Present
When set, indicates that GPIO Port B is present.
1 GPIOB RO 1
GPIO Port A Present
When set, indicates that GPIO Port A is present.
0 GPIOA RO 1
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System Control
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 0 (RCGC0)
Base 0x400F.E000
Offset 0x100
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved CAN0 reserved ADC
Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MAXADCSPD reserved HIB reserved WDT reserved
Type RO RO RO RO R/W R/W R/W R/W RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:25 reserved RO 0
CAN0 Clock Gating Control
This bit controls the clock gating for CAN unit 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
24 CAN0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:17 reserved RO 0
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:12 reserved RO 0
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Bit/Field Name Type Reset Description
ADC Sample Speed
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:
Value Description
0x3 1M samples/second
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second
11:8 MAXADCSPD R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.
6 HIB R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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System Control
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved CAN0 reserved ADC
Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MAXADCSPD reserved HIB reserved WDT reserved
Type RO RO RO RO R/W R/W R/W R/W RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:25 reserved RO 0
CAN0 Clock Gating Control
This bit controls the clock gating for CAN unit 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
24 CAN0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:17 reserved RO 0
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:12 reserved RO 0
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Bit/Field Name Type Reset Description
ADC Sample Speed
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:
Value Description
0x3 1M samples/second
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second
11:8 MAXADCSPD R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.
6 HIB R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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System Control
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved CAN0 reserved ADC
Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MAXADCSPD reserved HIB reserved WDT reserved
Type RO RO RO RO R/W R/W R/W R/W RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:25 reserved RO 0
CAN0 Clock Gating Control
This bit controls the clock gating for CAN unit 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
24 CAN0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:17 reserved RO 0
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:12 reserved RO 0
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Bit/Field Name Type Reset Description
ADC Sample Speed
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:
Value Description
0x3 1M samples/second
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second
11:8 MAXADCSPD R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.
6 HIB R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
98 March 17, 2008
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System Control
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 1 (RCGC1)
Base 0x400F.E000
Offset 0x104
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C0 reserved SSI0 reserved UART1 UART0
Type RO RO RO R/W RO RO RO RO RO RO RO R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
26 COMP2 R/W 0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
25 COMP1 R/W 0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:20 reserved RO 0
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Bit/Field Name Type Reset Description
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
19 TIMER3 R/W 0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18 TIMER2 R/W 0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17 TIMER1 R/W 0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
12 I2C0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:5 reserved RO 0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
1 UART1 R/W 0
100 March 17, 2008
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System Control
Bit/Field Name Type Reset Description
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0 UART0 R/W 0
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Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 1 (SCGC1)
Base 0x400F.E000
Offset 0x114
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C0 reserved SSI0 reserved UART1 UART0
Type RO RO RO R/W RO RO RO RO RO RO RO R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
26 COMP2 R/W 0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
25 COMP1 R/W 0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:20 reserved RO 0
102 March 17, 2008
Preliminary
System Control
Bit/Field Name Type Reset Description
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
19 TIMER3 R/W 0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18 TIMER2 R/W 0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17 TIMER1 R/W 0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
12 I2C0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:5 reserved RO 0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
1 UART1 R/W 0
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Bit/Field Name Type Reset Description
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0 UART0 R/W 0
104 March 17, 2008
Preliminary
System Control
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C0 reserved SSI0 reserved UART1 UART0
Type RO RO RO R/W RO RO RO RO RO RO RO R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
26 COMP2 R/W 0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
25 COMP1 R/W 0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:20 reserved RO 0
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LM3S8933 Microcontroller
Bit/Field Name Type Reset Description
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
19 TIMER3 R/W 0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18 TIMER2 R/W 0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17 TIMER1 R/W 0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
12 I2C0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:5 reserved RO 0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
1 UART1 R/W 0
106 March 17, 2008
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System Control
Bit/Field Name Type Reset Description
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0 UART0 R/W 0
March 17, 2008 107
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LM3S8933 Microcontroller
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 2 (RCGC2)
Base 0x400F.E000
Offset 0x108
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
6 GPIOG R/W 0
108 March 17, 2008
Preliminary
System Control
Bit/Field Name Type Reset Description
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 GPIOF R/W 0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 GPIOE R/W 0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3 GPIOD R/W 0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 GPIOC R/W 0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 GPIOB R/W 0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0 GPIOA R/W 0
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LM3S8933 Microcontroller
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset
0x118
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 2 (SCGC2)
Base 0x400F.E000
Offset 0x118
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
110 March 17, 2008
Preliminary
System Control
Bit/Field Name Type Reset Description
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
6 GPIOG R/W 0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 GPIOF R/W 0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 GPIOE R/W 0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3 GPIOD R/W 0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 GPIOC R/W 0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 GPIOB R/W 0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0 GPIOA R/W 0
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Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
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Bit/Field Name Type Reset Description
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
6 GPIOG R/W 0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 GPIOF R/W 0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 GPIOE R/W 0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3 GPIOD R/W 0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 GPIOC R/W 0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 GPIOB R/W 0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0 GPIOA R/W 0
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Register 27: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved CAN0 reserved ADC
Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved HIB reserved WDT reserved
Type RO RO RO RO RO RO RO RO RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:25 reserved RO 0
CAN0 Reset Control
Reset control for CAN unit 0.
24 CAN0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:17 reserved RO 0
ADC0 Reset Control
Reset control for SAR ADC module 0.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:7 reserved RO 0
HIB Reset Control
Reset control for the Hibernation module.
6 HIB R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Reset Control
Reset control for Watchdog unit.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 28: Software Reset Control 1 (SRCR1), offset 0x044
Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C0 reserved SSI0 reserved UART1 UART0
Type RO RO RO R/W RO RO RO RO RO RO RO R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comp 2 Reset Control
Reset control for analog comparator 2.
26 COMP2 R/W 0
Analog Comp 1 Reset Control
Reset control for analog comparator 1.
25 COMP1 R/W 0
Analog Comp 0 Reset Control
Reset control for analog comparator 0.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:20 reserved RO 0
Timer 3 Reset Control
Reset control for General-Purpose Timer module 3.
19 TIMER3 R/W 0
Timer 2 Reset Control
Reset control for General-Purpose Timer module 2.
18 TIMER2 R/W 0
Timer 1 Reset Control
Reset control for General-Purpose Timer module 1.
17 TIMER1 R/W 0
Timer 0 Reset Control
Reset control for General-Purpose Timer module 0.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
I2C0 Reset Control
Reset control for I2C unit 0.
12 I2C0 R/W 0
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:5 reserved RO 0
SSI0 Reset Control
Reset control for SSI unit 0.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
UART1 Reset Control
Reset control for UART unit 1.
1 UART1 R/W 0
UART0 Reset Control
Reset control for UART unit 0.
0 UART0 R/W 0
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Register 29: Software Reset Control 2 (SRCR2), offset 0x048
Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register.
Software Reset Control 2 (SRCR2)
Base 0x400F.E000
Offset 0x048
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Reset Control
Reset control for Ethernet PHY unit 0.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Reset Control
Reset control for Ethernet MAC unit 0.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
Port G Reset Control
Reset control for GPIO Port G.
6 GPIOG R/W 0
Port F Reset Control
Reset control for GPIO Port F.
5 GPIOF R/W 0
Port E Reset Control
Reset control for GPIO Port E.
4 GPIOE R/W 0
Port D Reset Control
Reset control for GPIO Port D.
3 GPIOD R/W 0
Port C Reset Control
Reset control for GPIO Port C.
2 GPIOC R/W 0
Port B Reset Control
Reset control for GPIO Port B.
1 GPIOB R/W 0
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Bit/Field Name Type Reset Description
Port A Reset Control
Reset control for GPIO Port A.
0 GPIOA R/W 0
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7 Hibernation Module
The Hibernation Module manages removal and restoration of power to the rest of the microcontroller
to provide a means for reducing power consumption. When the processor and peripherals are idle,
power can be completely removed with only the Hibernation Module remaining powered. Power
can be restored based on an external signal, or at a certain time using the built-in real-time clock
(RTC). The Hibernation module can be independently supplied from a battery or an auxiliary power
supply.
The Hibernation module has the following features:
■ Power-switching logic to discrete external regulator
■ Dedicated pin for waking from an external signal
■ Low-battery detection, signaling, and interrupt generation
■ 32-bit real-time counter (RTC)
■ Two 32-bit RTC match registers for timed wake-up and interrupt generation
■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal
■ RTC predivider trim for making fine adjustments to the clock rate
■ 64 32-bit words of non-volatile memory
■ Programmable interrupts for RTC match, external wake, and low battery events
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7.1 Block Diagram
Figure 7-1. Hibernation Module Block Diagram
HIBIM
HIBRIS
HIBMIS
HIBIC
HIBRTCT
Pre-Divider
/128
XOSC0
XOSC1
HIBCTL.CLK32EN
HIBCTL.CLKSEL
HIBRTCC
HIBRTCLD
HIBRTCM0
HIBRTCM1
RTC
Interrupts
Power
Sequence
Logic
MATCH0/1
WAKE
Interrupts
to CPU
Low Battery
Detect
LOWBAT
VDD
VBAT
HIB
HIBCTL.LOWBATEN HIBCTL.PWRCUT
HIBCTL.EXTWEN
HIBCTL.RTCWEN
HIBCTL.VABORT
Non-Volatile
Memory
HIBDATA
7.2 Functional Description
The Hibernation module controls the power to the processor with an enable signal (HIB) that signals
an external voltage regulator to turn off. The Hibernation module power is determined dynamically.
The supply voltage of the Hibernation module is the larger of the main voltage source (VDD) or the
battery/auxilliary voltage source (VBAT). A voting circuit indicates the larger and an internal power
switch selects the appropriate voltage source. The Hibernation module also has a separate clock
source to maintain a real-time clock (RTC). Once in hibernation, the module signals an external
voltage regulator to turn back on the power when an external pin (WAKE) is asserted, or when the
internal RTC reaches a certain value. The Hibernation module can also detect when the battery
voltage is low, and optionally prevent hibernation when this occurs.
Power-up from a power cut to code execution is defined as the regulator turn-on time (specified at
tHIB_TO_VDD maximum) plus the normal chip POR (see “Hibernation Module” on page 544).
7.2.1 Register Access Timing
Because the Hibernation module has an independent clocking domain, certain registers must be
written only with a timing gap between accesses. The delay time is tHIB_REG_WRITE, therefore software
must guarantee that a delay of tHIB_REG_WRITE is inserted between back-to-back writes to certain
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Hibernation registers, or between a write followed by a read to those same registers. There is no
restriction on timing for back-to-back reads from the Hibernation module.
7.2.2 Clock Source
The Hibernation module must be clocked by an external source, even if the RTC feature will not be
used. An external oscillator or crystal can be used for this purpose. To use a crystal, a 4.194304-MHz
crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to
produce the 32.768-kHz clock reference. To use a more precise clock source, a 32.768-kHz oscillator
can be connected to the XOSC0 pin.
The clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The type of clock
source is selected by setting the CLKSEL bit to 0 for a 4.194304-MHz clock source, and to 1 for a
32.768-kHz clock source. If the bit is set to 0, the input clock is divided by 128, resulting in a
32.768-kHz clock source. If a crystal is used for the clock source, the software must leave a delay
of tXOSC_SETTLE after setting the CLK32EN bit and before any other accesses to the Hibernation
module registers. The delay allows the crystal to power up and stabilize. If an oscillator is used for
the clock source, no delay is needed.
7.2.3 Battery Management
The Hibernation module can be independently powered by a battery or an auxiliary power source.
The module can monitor the voltage level of the battery and detect when the voltage drops below
2.35 V. When this happens, an interrupt can be generated. The module also can be configured so
that it will not go into Hibernate mode if the battery voltage drops below this threshold.
Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher
voltage. Therefore, it is important to design the circuit to ensure that VDD is higher that VBAT under
nominal conditions or else the Hibernation module draws power from the battery even when VDD
is available.
The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN
bit of the HIBCTL register. In this configuration, the LOWBAT bit of the HIBRIS register will be set
when the battery level is low. If the VABORT bit is also set, then the module is prevented from entering
Hibernation mode when a low battery is detected. The module can also be configured to generate
an interrupt for the low-battery condition (see “Interrupts and Status” on page 122).
7.2.4 Real-Time Clock
The Hibernation module includes a 32-bit counter that increments once per second with a proper
clock source and configuration (see “Clock Source” on page 121). The 32.768-kHz clock signal is
fed into a predivider register which counts down the 32.768-kHz clock ticks to achieve a once per
second clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock
source by using the predivider trim register, HIBRTCT. This register has a nominal value of 0x7FFF,
and is used for one second out of every 64 seconds to divide the input clock. This allows the software
to make fine corrections to the clock rate by adjusting the predivider trim register up or down from
0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC
rate, and down from 0x7FFF in order to speed up the RTC rate.
The Hibernation module includes two 32-bit match registers that are compared to the value of the
RTC counter. The match registers can be used to wake the processor from hibernation mode, or
to generate an interrupt to the processor if it is not in hibernation.
The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be
set at any time by writing to the HIBRTCLD register. The predivider trim can be adjusted by reading
and writing the HIBRTCT register. The predivider uses this register once every 64 seconds to adjust
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the clock rate. The two match registers can be set by writing to the HIBRTCM0 and HIBRTCM1
registers. The RTC can be configured to generate interrupts by using the interrupt registers (see
“Interrupts and Status” on page 122).
7.2.5 Non-Volatile Memory
The Hibernation module contains 64 32-bit words of memory which are retained during hibernation.
This memory is powered from the battery or auxiliary power supply during hibernation. The processor
software can save state information in this memory prior to hibernation, and can then recover the
state upon waking. The non-volatile memory can be accessed through the HIBDATA registers.
7.2.6 Power Control
The Hibernation module controls power to the processor through the use of the HIB pin, which is
intended to be connected to the enable signal of the external regulator(s) providing 3.3 V and/or
2.5 V to the microcontroller. When the HIB signal is asserted by the Hibernation module, the external
regulator is turned off and no longer powers the microcontroller. The Hibernation module remains
powered from the VBAT supply, which could be a battery or an auxiliary power source. Hibernation
mode is initiated by the microcontroller setting the HIBREQ bit of the HIBCTL register. Prior to doing
this, a wake-up condition must be configured, either from the external WAKE pin, or by using an RTC
match.
The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN
bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Either
one or both of these bits can be set prior to going into hibernation. The WAKE pin includes a weak
internal pull-up. Note that both the HIB and WAKE pins use the Hibernation module's internal power
supply as the logic 1 reference.
When the Hibernation module wakes, the microcontroller will see a normal power-on reset. It can
detect that the power-on was due to a wake from hibernation by examining the raw interrupt status
register (see “Interrupts and Status” on page 122) and by looking for state data in the non-volatile
memory (see “Non-Volatile Memory” on page 122).
When the HIB signal deasserts, enabling the external regulator, the external regulator must reach
the operating voltage within tHIB_TO_VDD.
7.2.7 Interrupts and Status
The Hibernation module can generate interrupts when the following conditions occur:
■ Assertion of WAKE pin
■ RTC match
■ Low battery detected
All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate
module can only generate a single interrupt request to the controller at any given time. The software
interrupt handler can service multiple interrupt events by reading the HIBMIS register. Software can
also read the status of the Hibernation module at any time by reading the HIBRIS register which
shows all of the pending events. This register can be used at power-on to see if a wake condition
is pending, which indicates to the software that a hibernation wake occurred.
The events that can trigger an interrupt are configured by setting the appropriate bits in the HIBIM
register. Pending interrupts can be cleared by writing the corresponding bit in the HIBIC register.
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7.3 Initialization and Configuration
The Hibernation module can be set in several different configurations. The following sections show
the recommended programming sequence for various scenarios. The examples below assume that
a 32.768-kHz oscillator is used, and thus always show bit 2 (CLKSEL) of the HIBCTL register set
to 1. If a 4.194304-MHz crystal is used instead, then the CLKSEL bit remains cleared. Because the
Hibernation module runs at 32 kHz and is asynchronous to the rest of the system, software must
allow a delay of tHIB_REG_WRITE after writes to certain registers (see “Register Access
Timing” on page 120). The registers that require a delay are listed in a note in “Register Map” on page
124 as well as in each register description.
7.3.1 Initialization
The clock source must be enabled first, even if the RTC will not be used. If a 4.194304-MHz crystal
is used, perform the following steps:
1. Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128
input path.
2. Wait for a time of tXOSC_SETTLE for the crystal to power up and stabilize before performing any
other operations with the Hibernation module.
If a 32.678-kHz oscillator is used, then perform the following steps:
1. Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input.
2. No delay is necessary.
The above is only necessary when the entire system is initialized for the first time. If the processor
is powered due to a wake from hibernation, then the Hibernation module has already been powered
up and the above steps are not necessary. The software can detect that the Hibernation module
and clock are already powered by examining the CLK32EN bit of the HIBCTL register.
7.3.2 RTC Match Functionality (No Hibernation)
Use the following steps to implement the RTC match functionality of the Hibernation module:
1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the
HIBIM register at offset 0x014.
4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting.
7.3.3 RTC Match/Wake-Up from Hibernation
Use the following steps to implement the RTC match and wake-up functionality of the Hibernation
module:
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
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4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the
HIBCTL register at offset 0x010.
7.3.4 External Wake-Up from Hibernation
Use the following steps to implement the Hibernation module with the external WAKE pin as the
wake-up source for the microcontroller:
1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the
HIBCTL register at offset 0x010.
7.3.5 RTC/External Wake-Up from Hibernation
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F
to the HIBCTL register at offset 0x010.
7.4 Register Map
Table 7-1 on page 124 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000.
Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 120.
Table 7-1. Hibernation Module Register Map
See
Offset Name Type Reset Description page
0x000 HIBRTCC RO 0x0000.0000 Hibernation RTC Counter 126
0x004 HIBRTCM0 R/W 0xFFFF.FFFF Hibernation RTC Match 0 127
0x008 HIBRTCM1 R/W 0xFFFF.FFFF Hibernation RTC Match 1 128
0x00C HIBRTCLD R/W 0xFFFF.FFFF Hibernation RTC Load 129
0x010 HIBCTL R/W 0x0000.0000 Hibernation Control 130
0x014 HIBIM R/W 0x0000.0000 Hibernation Interrupt Mask 132
0x018 HIBRIS RO 0x0000.0000 Hibernation Raw Interrupt Status 133
0x01C HIBMIS RO 0x0000.0000 Hibernation Masked Interrupt Status 134
0x020 HIBIC R/W1C 0x0000.0000 Hibernation Interrupt Clear 135
0x024 HIBRTCT R/W 0x0000.7FFF Hibernation RTC Trim 136
0x030- HIBDATA R/W 0x0000.0000 Hibernation Data 137
0x12C
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7.5 Register Descriptions
The remainder of this section lists and describes the Hibernation module registers, in numerical
order by address offset.
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Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000
This register is the current 32-bit value of the RTC counter.
Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 120.
Hibernation RTC Counter (HIBRTCC)
Base 0x400F.C000
Offset 0x000
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
RTC Counter
A read returns the 32-bit counter value. This register is read-only. To
change the value, use the HIBRTCLD register.
31:0 RTCC RO 0x0000.0000
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Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004
This register is the 32-bit match 0 register for the RTC counter.
Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 120.
Hibernation RTC Match 0 (HIBRTCM0)
Base 0x400F.C000
Offset 0x004
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCM0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCM0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
RTC Match 0
A write loads the value into the RTC match register.
A read returns the current match value.
31:0 RTCM0 R/W 0xFFFF.FFFF
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Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008
This register is the 32-bit match 1 register for the RTC counter.
Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 120.
Hibernation RTC Match 1 (HIBRTCM1)
Base 0x400F.C000
Offset 0x008
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCM1
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCM1
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
RTC Match 1
A write loads the value into the RTC match register.
A read returns the current match value.
31:0 RTCM1 R/W 0xFFFF.FFFF
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Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C
This register is the 32-bit value loaded into the RTC counter.
Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 120.
Hibernation RTC Load (HIBRTCLD)
Base 0x400F.C000
Offset 0x00C
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCLD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCLD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
RTC Load
A write loads the current value into the RTC counter (RTCC).
A read returns the 32-bit load value.
31:0 RTCLD R/W 0xFFFF.FFFF
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Register 5: Hibernation Control (HIBCTL), offset 0x010
This register is the control register for the Hibernation module.
Hibernation Control (HIBCTL)
Base 0x400F.C000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBREQ RTCEN
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Power Cut Abort Enable
Value Description
0 Power cut occurs during a low-battery alert.
1 Power cut is aborted.
7 VABORT R/W 0
32-kHz Oscillator Enable
Value Description
0 Disabled
1 Enabled
This bit must be enabled to use the Hibernation module. If a crystal is
used, then software should wait 20 ms after setting this bit to allow the
crystal to power up and stabilize.
6 CLK32EN R/W 0
Low Battery Monitoring Enable
Value Description
0 Disabled
1 Enabled
When set, low battery voltage detection is enabled (VBAT < 2.35 V).
5 LOWBATEN R/W 0
External WAKE Pin Enable
Value Description
0 Disabled
1 Enabled
When set, an external event on the WAKE pin will re-power the device.
4 PINWEN R/W 0
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Bit/Field Name Type Reset Description
RTC Wake-up Enable
Value Description
0 Disabled
1 Enabled
When set, an RTC match event (RTCM0 or RTCM1) will re-power the
device based on the RTC counter value matching the corresponding
match register 0 or 1.
3 RTCWEN R/W 0
Hibernation Module Clock Select
Value Description
0 Use Divide by 128 output. Use this value for a 4-MHz crystal.
1 Use raw output. Use this value for a 32-kHz oscillator.
2 CLKSEL R/W 0
Hibernation Request
Value Description
0 Disabled
1 Hibernation initiated
After a wake-up event, this bit is cleared by hardware.
1 HIBREQ R/W 0
RTC Timer Enable
Value Description
0 Disabled
1 Enabled
0 RTCEN R/W 0
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Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014
This register is the interrupt mask register for the Hibernation module interrupt sources.
Hibernation Interrupt Mask (HIBIM)
Base 0x400F.C000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
External Wake-Up Interrupt Mask
Value Description
0 Masked
1 Unmasked
3 EXTW R/W 0
Low Battery Voltage Interrupt Mask
Value Description
0 Masked
1 Unmasked
2 LOWBAT R/W 0
RTC Alert1 Interrupt Mask
Value Description
0 Masked
1 Unmasked
1 RTCALT1 R/W 0
RTC Alert0 Interrupt Mask
Value Description
0 Masked
1 Unmasked
0 RTCALT0 R/W 0
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Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018
This register is the raw interrupt status for the Hibernation module interrupt sources.
Hibernation Raw Interrupt Status (HIBRIS)
Base 0x400F.C000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
3 EXTW RO 0 External Wake-Up Raw Interrupt Status
2 LOWBAT RO 0 Low Battery Voltage Raw Interrupt Status
1 RTCALT1 RO 0 RTC Alert1 Raw Interrupt Status
0 RTCALT0 RO 0 RTC Alert0 Raw Interrupt Status
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Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C
This register is the masked interrupt status for the Hibernation module interrupt sources.
Hibernation Masked Interrupt Status (HIBMIS)
Base 0x400F.C000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
3 EXTW RO 0 External Wake-Up Masked Interrupt Status
2 LOWBAT RO 0 Low Battery Voltage Masked Interrupt Status
1 RTCALT1 RO 0 RTC Alert1 Masked Interrupt Status
0 RTCALT0 RO 0 RTC Alert0 Masked Interrupt Status
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Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020
This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources.
Hibernation Interrupt Clear (HIBIC)
Base 0x400F.C000
Offset 0x020
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
External Wake-Up Masked Interrupt Clear
Reads return an indeterminate value.
3 EXTW R/W1C 0
Low Battery Voltage Masked Interrupt Clear
Reads return an indeterminate value.
2 LOWBAT R/W1C 0
RTC Alert1 Masked Interrupt Clear
Reads return an indeterminate value.
1 RTCALT1 R/W1C 0
RTC Alert0 Masked Interrupt Clear
Reads return an indeterminate value.
0 RTCALT0 R/W1C 0
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Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024
This register contains the value that is used to trim the RTC clock predivider. It represents the
computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock
cycles.
Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 120.
Hibernation RTC Trim (HIBRTCT)
Base 0x400F.C000
Offset 0x024
Type R/W, reset 0x0000.7FFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
RTC Trim Value
This value is loaded into the RTC predivider every 64 seconds. It is used
to adjust the RTC rate to account for drift and inaccuracy in the clock
source. The compensation is made by software by adjusting the default
value of 0x7FFF up or down.
15:0 TRIM R/W 0x7FFF
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Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C
This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the
system processor in order to store any non-volatile state data and will not lose power during a power
cut operation.
Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write
accesses. See “Register Access Timing” on page 120.
Hibernation Data (HIBDATA)
Base 0x400F.C000
Offset 0x030-0x12C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
31:0 RTD R/W 0x0000.0000 Hibernation Module NV Registers[63:0]
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8 Internal Memory
The LM3S8933 microcontroller comes with 64 KB of bit-banded SRAM and 256 KB of flash memory.
The flash controller provides a user-friendly interface, making flash programming a simple task.
Flash protection can be applied to the flash memory on a 2-KB block basis.
8.1 Block Diagram
Figure 8-1. Flash Block Diagram
Flash Control
FMA
FCMISC
FCIM
FCRIS
FMC
FMD
Flash Timing
USECRL
Flash Protection
FMPREn
FMPPEn
Flash Array
SRAM Array
Bridge
Cortex-M3
ICode
DCode
System Bus
APB
User Registers
USER_REG0
USER_REG1
USER_DBG
8.2 Functional Description
This section describes the functionality of both the flash and SRAM memories.
8.2.1 SRAM Memory
The internal SRAM of the Stellaris® devices is located at address 0x2000.0000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has
introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor,
certain regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
The bit-band alias is calculated by using the formula:
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bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3
Technical Reference Manual.
8.2.2 Flash Memory
The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be
programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB
blocks that can be individually protected. The protection allows blocks to be marked as read-only
or execute-only, providing different levels of code protection. Read-only blocks cannot be erased
or programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
See also “Serial Flash Loader” on page 554 for a preprogrammed flash-resident utility used to
download code to the flash memory of a device without the use of a debug interface.
8.2.2.1 Flash Memory Timing
The timing for the flash is automatically handled by the flash controller. However, in order to do so,
it must know the clock rate of the system in order to time its internal signals properly. The number
of clock cycles per microsecond must be provided to the flash controller for it to accomplish this
timing. It is software's responsibility to keep the flash controller updated with this information via the
USec Reload (USECRL) register.
On reset, the USECRL register is loaded with a value that configures the flash timing so that it works
with the maximum clock rate of the part. If software changes the system operating frequency, the
new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash
modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value
of 0x13 (20-1) must be written to the USECRL register.
8.2.2.2 Flash Memory Protection
The user is provided two forms of flash protection per 2-KB flash blocks in four pairs of 32-bit wide
registers. The protection policy for each form is controlled by individual bits (per policy per block)
in the FMPPEn and FMPREn registers.
■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed
(written) or erased. If cleared, the block may not be changed.
■ Flash Memory Protection Read Enable (FMPREn): If set, the block may be executed or read
by software or debuggers. If cleared, the block may only be executed and contents of the memory
block are prohibited from being accessed as data.
The policies may be combined as shown in Table 8-1 on page 140.
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Table 8-1. Flash Protection Policy Combinations
FMPPEn FMPREn Protection
Execute-only protection. The block may only be executed and may not be written or erased. This mode
is used to protect code.
0 0
1 0 The block may be written, erased or executed, but not read. This combination is unlikely to be used.
Read-only protection. The block may be read or executed but may not be written or erased. This mode
is used to lock the block from further modification while allowing any read or execute access.
0 1
1 1 No protection. The block may be written, erased, executed or read.
An access that attempts to program or erase a PE-protected block is prohibited. A controller interrupt
may be optionally generated (by setting the AMASK bit in the FIM register) to alert software developers
of poorly behaving software during the development and debug phases.
An access that attempts to read an RE-protected block is prohibited. Such accesses return data
filled with all 0s. A controller interrupt may be optionally generated to alert software developers of
poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. This implements a policy of open access and programmability. The register bits may be
changed by writing the specific register bit. The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. Details on
programming these bits are discussed in “Nonvolatile Register Programming” on page 141.
8.3 Flash Memory Initialization and Configuration
8.3.1 Flash Programming
The Stellaris® devices provide a user-friendly interface for flash programming. All erase/program
operations are handled via three registers: FMA, FMD, and FMC.
8.3.1.1 To program a 32-bit word
1. Write source data to the FMD register.
2. Write the target address to the FMA register.
3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register.
4. Poll the FMC register until the WRITE bit is cleared.
8.3.1.2 To perform an erase of a 1-KB page
1. Write the page address to the FMA register.
2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register.
3. Poll the FMC register until the ERASE bit is cleared.
8.3.1.3 To perform a mass erase of the flash
1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register.
2. Poll the FMC register until the MERASE bit is cleared.
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8.3.2 Nonvolatile Register Programming
This section discusses how to update registers that are resident within the flash memory itself.
These registers exist in a separate space from the main flash array and are not affected by an
ERASE or MASS ERASE operation. These nonvolatile registers are updated by using the COMT bit
in the FMC register to activate a write operation. For the USER_DBG register, the data to be written
must be loaded into the FMD register before it is "committed". All other registers are R/W and can
have their operation tried before committing them to nonvolatile memory.
Important: These registers can only have bits changed from 1 to 0 by the user and there is no
mechanism for the user to erase them back to a 1 value.
In addition, the USER_REG0, USER_REG1, and USER_DBG use bit 31 (NW) of their respective
registers to indicate that they are available for user write. These three registers can only be written
once whereas the flash protection registers may be written multiple times. Table 8-2 on page 141
provides the FMA address required for commitment of each of the registers and the source of the
data to be written when the COMT bit of the FMC register is written with a value of 0xA442.0008.
After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to
complete.
Table 8-2. Flash Resident Registersa
Register to be Committed FMA Value Data Source
FMPRE0 0x0000.0000 FMPRE0
FMPRE1 0x0000.0002 FMPRE1
FMPRE2 0x0000.0004 FMPRE2
FMPRE3 0x0000.0008 FMPRE3
FMPPE0 0x0000.0001 FMPPE0
FMPPE1 0x0000.0003 FMPPE1
FMPPE2 0x0000.0005 FMPPE2
FMPPE3 0x0000.0007 FMPPE3
USER_REG0 0x8000.0000 USER_REG0
USER_REG1 0x8000.0001 USER_REG1
USER_DBG 0x7510.0000 FMD
a. Which FMPREn and FMPPEn registers are available depend on the flash size of your particular Stellaris® device.
8.4 Register Map
Table 8-3 on page 141 lists the Flash memory and control registers. The offset listed is a hexadecimal
increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers
are relative to the Flash control base address of 0x400F.D000. The FMPREn, FMPPEn, USECRL,
USER_DBG, and USER_REGn registers are relative to the System Control base address of
0x400F.E000.
Table 8-3. Flash Register Map
See
Offset Name Type Reset Description page
Flash Control Offset
0x000 FMA R/W 0x0000.0000 Flash Memory Address 143
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See
Offset Name Type Reset Description page
0x004 FMD R/W 0x0000.0000 Flash Memory Data 144
0x008 FMC R/W 0x0000.0000 Flash Memory Control 145
0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 147
0x010 FCIM R/W 0x0000.0000 Flash Controller Interrupt Mask 148
0x014 FCMISC R/W1C 0x0000.0000 Flash Controller Masked Interrupt Status and Clear 149
System Control Offset
0x130 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 151
0x200 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 151
0x134 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 152
0x400 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 152
0x140 USECRL R/W 0x31 USec Reload 150
0x1D0 USER_DBG R/W 0xFFFF.FFFE User Debug 153
0x1E0 USER_REG0 R/W 0xFFFF.FFFF User Register 0 154
0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 155
0x204 FMPRE1 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 1 156
0x208 FMPRE2 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 2 157
0x20C FMPRE3 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 3 158
0x404 FMPPE1 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 1 159
0x408 FMPPE2 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 2 160
0x40C FMPPE3 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 3 161
8.5 Flash Register Descriptions (Flash Control Offset)
This section lists and describes the Flash Memory registers, in numerical order by address offset.
Registers in this section are relative to the Flash control base address of 0x400F.D000.
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Internal Memory
Register 1: Flash Memory Address (FMA), offset 0x000
During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations, this register contains a 1 KB-aligned address and specifies
which page is erased. Note that the alignment requirements must be met by software or the results
of the operation are unpredictable.
Flash Memory Address (FMA)
Base 0x400F.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved OFFSET
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:18 reserved RO 0x0
Address Offset
Address offset in flash where operation is performed, except for
nonvolatile registers (see “Nonvolatile Register Programming” on page
141 for details on values for this field).
17:0 OFFSET R/W 0x0
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Register 2: Flash Memory Data (FMD), offset 0x004
This register contains the data to be written during the programming cycle or read during the read
cycle. Note that the contents of this register are undefined for a read access of an execute-only
block. This register is not used during the erase cycles.
Flash Memory Data (FMD)
Base 0x400F.D000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Data Value
Data value for write operation.
31:0 DATA R/W 0x0
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Register 3: Flash Memory Control (FMC), offset 0x008
When this register is written, the flash controller initiates the appropriate access cycle for the location
specified by the Flash Memory Address (FMA) register (see page 143). If the access is a write
access, the data contained in the Flash Memory Data (FMD) register (see page 144) is written.
This is the final register written and initiates the memory operation. There are four control bits in the
lower byte of this register that, when set, initiate the memory operation. The most used of these
register bits are the ERASE and WRITE bits.
It is a programming error to write multiple control bits and the results of such an operation are
unpredictable.
Flash Memory Control (FMC)
Base 0x400F.D000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRKEY
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved COMT MERASE ERASE WRITE
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Flash Write Key
This field contains a write key, which is used to minimize the incidence
of accidental flash writes. The value 0xA442 must be written into this
field for a write to occur. Writes to the FMC register without this WRKEY
value are ignored. A read of this field returns the value 0.
31:16 WRKEY WO 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:4 reserved RO 0x0
Commit Register Value
Commit (write) of register value to nonvolatile storage. A write of 0 has
no effect on the state of this bit.
If read, the state of the previous commit access is provided. If the
previous commit access is complete, a 0 is returned; otherwise, if the
commit access is not complete, a 1 is returned.
This can take up to 50 μs.
3 COMT R/W 0
Mass Erase Flash Memory
If this bit is set, the flash main memory of the device is all erased. A
write of 0 has no effect on the state of this bit.
If read, the state of the previous mass erase access is provided. If the
previous mass erase access is complete, a 0 is returned; otherwise, if
the previous mass erase access is not complete, a 1 is returned.
This can take up to 250 ms.
2 MERASE R/W 0
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Bit/Field Name Type Reset Description
Erase a Page of Flash Memory
If this bit is set, the page of flash main memory as specified by the
contents of FMA is erased. A write of 0 has no effect on the state of this
bit.
If read, the state of the previous erase access is provided. If the previous
erase access is complete, a 0 is returned; otherwise, if the previous
erase access is not complete, a 1 is returned.
This can take up to 25 ms.
1 ERASE R/W 0
Write a Word into Flash Memory
If this bit is set, the data stored in FMD is written into the location as
specified by the contents of FMA. A write of 0 has no effect on the state
of this bit.
If read, the state of the previous write update is provided. If the previous
write access is complete, a 0 is returned; otherwise, if the write access
is not complete, a 1 is returned.
This can take up to 50 μs.
0 WRITE R/W 0
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Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled
if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Base 0x400F.D000
Offset 0x00C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PRIS ARIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x0
Programming Raw Interrupt Status
This bit indicates the current state of the programming cycle. If set, the
programming cycle completed; if cleared, the programming cycle has
not completed. Programming cycles are either write or erase actions
generated through the Flash Memory Control (FMC) register bits (see
page 145).
1 PRIS RO 0
Access Raw Interrupt Status
This bit indicates if the flash was improperly accessed. If set, the program
tried to access the flash counter to the policy as set in the Flash Memory
Protection Read Enable (FMPREn) and Flash Memory Protection
Program Enable (FMPPEn) registers. Otherwise, no access has tried
to improperly access the flash.
0 ARIS RO 0
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LM3S8933 Microcontroller
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the flash controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PMASK AMASK
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x0
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the controller. If set, a programming-generated interrupt is promoted
to the controller. Otherwise, interrupts are recorded but suppressed from
the controller.
1 PMASK R/W 0
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
controller. If set, an access-generated interrupt is promoted to the
controller. Otherwise, interrupts are recorded but suppressed from the
controller.
0 AMASK R/W 0
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Internal Memory
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PMISC AMISC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x0
Programming Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because a
programming cycle completed and was not masked. This bit is cleared
by writing a 1. The PRIS bit in the FCRIS register (see page 147) is also
cleared when the PMISC bit is cleared.
1 PMISC R/W1C 0
Access Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because an improper
access was attempted and was not masked. This bit is cleared by writing
a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC
bit is cleared.
0 AMISC R/W1C 0
8.6 Flash Register Descriptions (System Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the System Control base address of
0x400F.E000.
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Register 7: USec Reload (USECRL), offset 0x140
Note: Offset is relative to System Control base address of 0x400F.E000
This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller.
The internal flash has specific minimum and maximum requirements on the length of time the high
voltage write pulse can be applied. It is required that this register contain the operating frequency
(in MHz -1) whenever the flash is being erased or programmed. The user is required to change this
value if the clocking conditions are changed for a flash erase/program operation.
USec Reload (USECRL)
Base 0x400F.E000
Offset 0x140
Type R/W, reset 0x31
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved USEC
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0
Microsecond Reload Value
MHz -1 of the controller clock when the flash is being erased or
programmed.
USEC should be set to 0x31 (50 MHz) whenever the flash is being erased
or programmed.
7:0 USEC R/W 0x31
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Internal Memory
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130
and 0x200
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 0 (FMPRE0)
Base 0x400F.D000
Offset 0x130 and 0x200
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset
0x134 and 0x400
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 0 (FMPPE0)
Base 0x400F.D000
Offset 0x134 and 0x400
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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Register 10: User Debug (USER_DBG), offset 0x1D0
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides a write-once mechanism to disable external debugger access to the device
in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory
and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0
disables any external debugger access to the device permanently, starting with the next power-up
cycle of the device. The NOTWRITTEN bit (bit 31) indicates that the register is available to be written
and is controlled through hardware to ensure that the register is only written once.
User Debug (USER_DBG)
Base 0x400F.E000
Offset 0x1D0
Type R/W, reset 0xFFFF.FFFE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NW DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA DBG1 DBG0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Bit/Field Name Type Reset Description
User Debug Not Written
Specifies that this 32-bit dword has not been written.
31 NW R/W 1
User Data
Contains the user data value. This field is initialized to all 1s and can
only be written once.
30:2 DATA R/W 0x1FFFFFFF
Debug Control 1
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
1 DBG1 R/W 1
Debug Control 0
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
0 DBG0 R/W 0
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Register 11: User Register 0 (USER_REG0), offset 0x1E0
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 0 (USER_REG0)
Base 0x400F.E000
Offset 0x1E0
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NW DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Not Written
Specifies that this 32-bit dword has not been written.
31 NW R/W 1
User Data
Contains the user data value. This field is initialized to all 1s and can
only be written once.
30:0 DATA R/W 0x7FFFFFFF
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Register 12: User Register 1 (USER_REG1), offset 0x1E4
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 1 (USER_REG1)
Base 0x400F.E000
Offset 0x1E4
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NW DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Not Written
Specifies that this 32-bit dword has not been written.
31 NW R/W 1
User Data
Contains the user data value. This field is initialized to all 1s and can
only be written once.
30:0 DATA R/W 0x7FFFFFFF
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Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 1 (FMPRE1)
Base 0x400F.E000
Offset 0x204
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 2 (FMPRE2)
Base 0x400F.E000
Offset 0x208
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 3 (FMPRE3)
Base 0x400F.E000
Offset 0x20C
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset
0x404
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 1 (FMPPE1)
Base 0x400F.E000
Offset 0x404
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset
0x408
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 2 (FMPPE2)
Base 0x400F.E000
Offset 0x408
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset
0x40C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 3 (FMPPE3)
Base 0x400F.E000
Offset 0x40C
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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9 General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, and Port G, ). The GPIO module supports
6-36 programmable input/output pins, depending on the peripherals being used.
The GPIO module has the following features:
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ 5-V-tolerant input/outputs
■ 4 high-drive GPIO capacity per device: 18mA maximum at Vol = 1.2V (a maximum of two
high-drive pins per device side or BGA pin group).
■ Bit masking in both read and write operations through address lines
■ Programmable control for GPIO pad configuration:
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; 18mA pad drive for high current
applications
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
9.1 Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
9-1 on page 163). The LM3S8933 microcontroller contains seven ports and thus seven of these
physical GPIO blocks.
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Figure 9-1. GPIO Port Block Diagram
Alternate Input
Alternate Output
Alternate Output Enable
Interrupt
GPIO Input
GPIO Output
GPIO Output Enable
Pad Output
Pad Output Enable
Package I/O Pin
GPIODATA
GPIODIR
Data
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
Interrupt
Control
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
Pad
Control
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
Identification Registers
GPIOAFSEL
Mode
Control
DEMUX MUX MUX
Digital
I/O Pad
Pad Input
GPIOLOCK
Commit
Control
GPIOCR
9.1.1 Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
9.1.1.1 Data Direction Operation
The GPIO Direction (GPIODIR) register (see page 171) is used to configure each individual pin as
an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and
the corresponding data register bit will capture and store the value on the GPIO port. When the data
direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit
will be driven out on the GPIO port.
9.1.1.2 Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 170) by using bits [9:2] of the address bus as a mask.
This allows software drivers to modify individual GPIO pins in a single instruction, without affecting
the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write
operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA
register covers 256 locations in the memory map.
During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA
register is altered. If it is cleared to 0, it is left unchanged.
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For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 9-2 on page 164, where u is data unchanged by the write.
Figure 9-2. GPIODATA Write Example
0 0 1 0 0 1 1 0 1 0
u u 1 u u 0 1 u
9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 1 1
7 6 5 4 3 2 1 0
GPIODATA
0xEB
0x098
ADDR[9:2]
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value.
For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 9-3 on page 164.
Figure 9-3. GPIODATA Read Example
0 0 1 1 0 0 0 1 0 0
0 0 1 1 0 0 0 0
9 8 7 6 5 4 3 2 1 0
1 0 1 1 1 1 1 0
7 6 5 4 3 2 1 0
Returned Value
GPIODATA
0x0C4
ADDR[9:2]
9.1.2 Interrupt Control
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source
holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:
■ GPIO Interrupt Sense (GPIOIS) register (see page 172)
■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 173)
■ GPIO Interrupt Event (GPIOIEV) register (see page 174)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 175).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 176 and page 177). As the name implies, the GPIOMIS register only shows interrupt
conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a
GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller.
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In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not
only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC
Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC
conversion is initiated.
If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored
Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts
and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt
handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC
interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC
registers until the conversion is completed.
Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR)
register (see page 178).
When programming the following interrupt control registers, the interrupts should be masked (GPIOIM
set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can
generate a spurious interrupt if the corresponding bits are enabled.
9.1.3 Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is enabled
via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179), the pin state is
controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO
mode, where the GPIODATA register is used to read/write the corresponding pins.
9.1.4 Commit Control
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 190) have been set to 1.
9.1.5 Pad Control
The pad control registers allow for GPIO pad configuration by software based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers.
9.1.6 Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
9.2 Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 9-1 on page 166
shows all possible configurations of the GPIO pads and the control register settings required to
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achieve them. Table 9-2 on page 166 shows how a rising edge interrupt would be configured for pin
2 of a GPIO port.
Table 9-1. GPIO Pad Configuration Examples
Configuration GPIO Register Bit Valuea
AFSEL DIR ODR DEN PUR PDR DR2R DR4R DR8R SLR
Digital Input (GPIO) 0 0 0 1 ? ? X X X X
Digital Output (GPIO) 0 1 0 1 ? ? ? ? ? ?
Open Drain Input 0 0 1 1 X X X X X X
(GPIO)
Open Drain Output 0 1 1 1 X X ? ? ? ?
(GPIO)
Open Drain 1 X 1 1 X X ? ? ? ?
Input/Output (I2C)
Digital Input (Timer 1 X 0 1 ? ? X X X X
CCP)
Digital Output (Timer 1 X 0 1 ? ? ? ? ? ?
PWM)
Digital Input/Output 1 X 0 1 ? ? ? ? ? ?
(SSI)
Digital Input/Output 1 X 0 1 ? ? ? ? ? ?
(UART)
Analog Input 0 0 0 0 0 0 X X X X
(Comparator)
Digital Output 1 X 0 1 ? ? ? ? ? ?
(Comparator)
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
Table 9-2. GPIO Interrupt Configuration Example
Desired Pin 2 Bit Valuea
Interrupt
Event
Trigger
Register
7 6 5 4 3 2 1 0
0=edge X X X X X 0 X X
1=level
GPIOIS
0=single X X X X X 0 X X
edge
1=both
edges
GPIOIBE
0=Low level, X X X X X 1 X X
or negative
edge
1=High level,
or positive
edge
GPIOIEV
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Desired Pin 2 Bit Valuea
Interrupt
Event
Trigger
Register
7 6 5 4 3 2 1 0
0=masked 0 0 0 0 0 1 0 0
1=not
masked
GPIOIM
a. X=Ignored (don’t care bit)
9.3 Register Map
Table 9-3 on page 168 lists the GPIO registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that GPIO port’s base address:
■ GPIO Port A: 0x4000.4000
■ GPIO Port B: 0x4000.5000
■ GPIO Port C: 0x4000.6000
■ GPIO Port D: 0x4000.7000
■ GPIO Port E: 0x4002.4000
■ GPIO Port F: 0x4002.5000
■ GPIO Port G: 0x4002.6000
Important: The GPIO registers in this chapter are duplicated in each GPIO block, however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to those unconnected bits has no effect and reading those unconnected
bits returns no meaningful data.
Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are
0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and
PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default
reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
The default register type for the GPIOCR register is RO for all GPIO pins, with the exception
of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because of this, the register type for
GPIO Port B7 and GPIO Port C[3:0] is R/W.
The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the
exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port
is not accidentally programmed as a GPIO, these five pins default to non-committable.
Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while
the default reset value of GPIOCR for Port C is 0x0000.00F0.
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Table 9-3. GPIO Register Map
See
Offset Name Type Reset Description page
0x000 GPIODATA R/W 0x0000.0000 GPIO Data 170
0x400 GPIODIR R/W 0x0000.0000 GPIO Direction 171
0x404 GPIOIS R/W 0x0000.0000 GPIO Interrupt Sense 172
0x408 GPIOIBE R/W 0x0000.0000 GPIO Interrupt Both Edges 173
0x40C GPIOIEV R/W 0x0000.0000 GPIO Interrupt Event 174
0x410 GPIOIM R/W 0x0000.0000 GPIO Interrupt Mask 175
0x414 GPIORIS RO 0x0000.0000 GPIO Raw Interrupt Status 176
0x418 GPIOMIS RO 0x0000.0000 GPIO Masked Interrupt Status 177
0x41C GPIOICR W1C 0x0000.0000 GPIO Interrupt Clear 178
0x420 GPIOAFSEL R/W - GPIO Alternate Function Select 179
0x500 GPIODR2R R/W 0x0000.00FF GPIO 2-mA Drive Select 181
0x504 GPIODR4R R/W 0x0000.0000 GPIO 4-mA Drive Select 182
0x508 GPIODR8R R/W 0x0000.0000 GPIO 8-mA Drive Select 183
0x50C GPIOODR R/W 0x0000.0000 GPIO Open Drain Select 184
0x510 GPIOPUR R/W - GPIO Pull-Up Select 185
0x514 GPIOPDR R/W 0x0000.0000 GPIO Pull-Down Select 186
0x518 GPIOSLR R/W 0x0000.0000 GPIO Slew Rate Control Select 187
0x51C GPIODEN R/W - GPIO Digital Enable 188
0x520 GPIOLOCK R/W 0x0000.0001 GPIO Lock 189
0x524 GPIOCR - - GPIO Commit 190
0xFD0 GPIOPeriphID4 RO 0x0000.0000 GPIO Peripheral Identification 4 192
0xFD4 GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 193
0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 194
0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 195
0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 196
0xFE4 GPIOPeriphID1 RO 0x0000.0000 GPIO Peripheral Identification 1 197
0xFE8 GPIOPeriphID2 RO 0x0000.0018 GPIO Peripheral Identification 2 198
0xFEC GPIOPeriphID3 RO 0x0000.0001 GPIO Peripheral Identification 3 199
0xFF0 GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 200
0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 201
0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 202
0xFFC GPIOPCellID3 RO 0x0000.00B1 GPIO PrimeCell Identification 3 203
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9.4 Register Descriptions
The remainder of this section lists and describes the GPIO registers, in numerical order by address
offset.
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Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 171).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from
the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause
the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the
corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
GPIO Data (GPIODATA)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Data
This register is virtually mapped to 256 locations in the address space.
To facilitate the reading and writing of data to these registers by
independent drivers, the data read from and the data written to the
registers are masked by the eight address lines ipaddr[9:2]. Reads
from this register return its current state. Writes to this register only affect
bits that are not masked by ipaddr[9:2] and are configured as
outputs. See “Data Register Operation” on page 163 for examples of
reads and writes.
7:0 DATA R/W 0x00
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Register 2: GPIO Direction (GPIODIR), offset 0x400
The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure
the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are
cleared by a reset, meaning all GPIO pins are inputs by default.
GPIO Direction (GPIODIR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x400
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DIR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Data Direction
The DIR values are defined as follows:
Value Description
0 Pins are inputs.
1 Pins are outputs.
7:0 DIR R/W 0x00
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Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the
corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits
are cleared by a reset.
GPIO Interrupt Sense (GPIOIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x404
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IS
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Sense
The IS values are defined as follows:
Value Description
0 Edge on corresponding pin is detected (edge-sensitive).
1 Level on corresponding pin is detected (level-sensitive).
7:0 IS R/W 0x00
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Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register (see page 172) is set to detect edges, bits set to High in GPIOIBE
configure the corresponding pin to detect both rising and falling edges, regardless of the
corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 174). Clearing a bit
configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.
GPIO Interrupt Both Edges (GPIOIBE)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x408
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IBE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Both Edges
The IBE values are defined as follows:
Value Description
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 174).
0
1 Both edges on the corresponding pin trigger an interrupt.
Note: Single edge is determined by the corresponding bit
in GPIOIEV.
7:0 IBE R/W 0x00
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LM3S8933 Microcontroller
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C
The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the
corresponding pin to detect rising edges or high levels, depending on the corresponding bit value
in the GPIO Interrupt Sense (GPIOIS) register (see page 172). Clearing a bit configures the pin to
detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are
cleared by a reset.
GPIO Interrupt Event (GPIOIEV)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x40C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IEV
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Event
The IEV values are defined as follows:
Value Description
Falling edge or Low levels on corresponding pins trigger
interrupts.
0
Rising edge or High levels on corresponding pins trigger
interrupts.
1
7:0 IEV R/W 0x00
174 March 17, 2008
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding
pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables
interrupt triggering on that pin. All bits are cleared by a reset.
GPIO Interrupt Mask (GPIOIM)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x410
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IME
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Mask Enable
The IME values are defined as follows:
Value Description
0 Corresponding pin interrupt is masked.
1 Corresponding pin interrupt is not masked.
7:0 IME R/W 0x00
March 17, 2008 175
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LM3S8933 Microcontroller
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the
status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the
requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask
(GPIOIM) register (see page 175). Bits read as zero indicate that corresponding input pins have not
initiated an interrupt. All bits are cleared by a reset.
GPIO Raw Interrupt Status (GPIORIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x414
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Raw Status
Reflects the status of interrupt trigger condition detection on pins (raw,
prior to masking).
The RIS values are defined as follows:
Value Description
0 Corresponding pin interrupt requirements not met.
1 Corresponding pin interrupt has met requirements.
7:0 RIS RO 0x00
176 March 17, 2008
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect
the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has
been generated, or the interrupt is masked.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not
only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC
Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC
conversion is initiated.
If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored
Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts
and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt
handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC
interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC
registers until the conversion is completed.
GPIOMIS is the state of the interrupt after masking.
GPIO Masked Interrupt Status (GPIOMIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x418
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Masked Interrupt Status
Masked value of interrupt due to corresponding pin.
The MIS values are defined as follows:
Value Description
0 Corresponding GPIO line interrupt not active.
1 Corresponding GPIO line asserting interrupt.
7:0 MIS RO 0x00
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LM3S8933 Microcontroller
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt edge detection logic register. Writing a 0 has no effect.
GPIO Interrupt Clear (GPIOICR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x41C
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IC
Type RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Clear
The IC values are defined as follows:
Value Description
0 Corresponding interrupt is unaffected.
1 Corresponding interrupt is cleared.
7:0 IC W1C 0x00
178 March 17, 2008
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register
selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore
no GPIO line is set to hardware control by default.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 190) have been set to 1.
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors,
and apply RST or power-cycle the part.
In addition, it is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
GPIO Alternate Function Select (GPIOAFSEL)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x420
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved AFSEL
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
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LM3S8933 Microcontroller
Bit/Field Name Type Reset Description
GPIO Alternate Function Select
The AFSEL values are defined as follows:
Value Description
0 Software control of corresponding GPIO line (GPIO mode).
Hardware control of corresponding GPIO line (alternate
hardware function).
1
Note: The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
7:0 AFSEL R/W -
180 March 17, 2008
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO
signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 2-mA Drive Select (GPIODR2R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x500
Type R/W, reset 0x0000.00FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DRV2
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad 2-mA Drive Enable
A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the
corresponding 2-mA enable bit. The change is effective on the second
clock cycle after the write.
7:0 DRV2 R/W 0xFF
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LM3S8933 Microcontroller
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504
The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 4-mA Drive Select (GPIODR4R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x504
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DRV4
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad 4-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the
corresponding 4-mA enable bit. The change is effective on the second
clock cycle after the write.
7:0 DRV4 R/W 0x00
182 March 17, 2008
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R
register are automatically cleared by hardware.
GPIO 8-mA Drive Select (GPIODR8R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x508
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DRV8
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad 8-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the
corresponding 8-mA enable bit. The change is effective on the second
clock cycle after the write.
7:0 DRV8 R/W 0x00
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LM3S8933 Microcontroller
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see
page 188). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R,
and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open
drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open drain output
when set to 1.
GPIO Open Drain Select (GPIOODR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x50C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ODE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad Open Drain Enable
The ODE values are defined as follows:
Value Description
0 Open drain configuration is disabled.
1 Open drain configuration is enabled.
7:0 ODE R/W 0x00
184 March 17, 2008
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up
resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 186).
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 190) have been set to 1.
GPIO Pull-Up Select (GPIOPUR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x510
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PUE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Pad Weak Pull-Up Enable
A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n]
enables. The change is effective on the second clock cycle after the
write.
Note: The default reset value for the GPIOAFSEL, GPIOPUR, and
GPIODEN registers are 0x0000.0000 for all GPIO pins, with
the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
These five pins default to JTAG/SWD functionality. Because
of this, the default reset value of these registers for GPIO Port
B is 0x0000.0080 while the default reset value for Port C is
0x0000.000F.
7:0 PUE R/W -
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LM3S8933 Microcontroller
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak
pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 185).
GPIO Pull-Down Select (GPIOPDR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x514
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PDE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Pad Weak Pull-Down Enable
A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n]
enables. The change is effective on the second clock cycle after the
write.
7:0 PDE R/W 0x00
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General-Purpose Input/Outputs (GPIOs)
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
The GPIOSLR register is the slew rate control register. Slew rate control is only available when
using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see
page 183).
GPIO Slew Rate Control Select (GPIOSLR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x518
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SRL
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Slew Rate Limit Enable (8-mA drive only)
The SRL values are defined as follows:
Value Description
0 Slew rate control disabled.
1 Slew rate control enabled.
7:0 SRL R/W 0x00
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Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
The GPIODEN register is the digital enable register. By default, with the exception of the GPIO
signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven
(tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not
allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or
alternate function), the corresponding GPIODEN bit must be set.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 190) have been set to 1.
GPIO Digital Enable (GPIODEN)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x51C
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DEN
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Digital Enable
The DEN values are defined as follows:
Value Description
0 Digital functions disabled.
1 Digital functions enabled.
Note: The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
7:0 DEN R/W -
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General-Purpose Input/Outputs (GPIOs)
Register 19: GPIO Lock (GPIOLOCK), offset 0x520
The GPIOLOCK register enables write access to the GPIOCR register (see page 190). Writing
0x1ACC.E551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value
to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns
the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses
are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses
are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000.
GPIO Lock (GPIOLOCK)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x520
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
GPIO Lock
A write of the value 0x1ACC.E551 unlocks the GPIO Commit (GPIOCR)
register for write access.
A write of any other value or a write to the GPIOCR register reapplies
the lock, preventing any register updates. A read of this register returns
the following values:
Value Description
0x0000.0001 locked
0x0000.0000 unlocked
31:0 LOCK R/W 0x0000.0001
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Register 20: GPIO Commit (GPIOCR), offset 0x524
The GPIOCR register is the commit register. The value of the GPIOCR register determines which
bits of the GPIOAFSEL register are committed when a write to the GPIOAFSEL register is performed.
If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit in the
GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the GPIOCR
register is a one, the data being written to the corresponding bit of the GPIOAFSEL register will be
committed to the register and will reflect the new value.
The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked.
Writes to the GPIOCR register are ignored if the GPIOLOCK register is locked.
Important: This register is designed to prevent accidental programming of the registers that control
connectivity to the JTAG/SWD debug hardware. By initializing the bits of the GPIOCR
register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only be converted
to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and the
corresponding registers.
Because this protection is currently only implemented on the JTAG/SWD pins on PB7
and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0.
These bits are hardwired to 0x1, ensuring that it is always possible to commit new
values to the GPIOAFSEL register bits of these other pins.
GPIO Commit (GPIOCR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x524
Type -, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CR
Type RO RO RO RO RO RO RO RO - - - - - - - -
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
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General-Purpose Input/Outputs (GPIOs)
Bit/Field Name Type Reset Description
GPIO Commit
On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL
bit to be set to its alternate function.
Note: The default register type for the GPIOCR register is RO for
all GPIO pins, with the exception of the five JTAG/SWD pins
(PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because
of this, the register type for GPIO Port B7 and GPIO Port
C[3:0] is R/W.
The default reset value for the GPIOCR register is
0x0000.00FF for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the
JTAG port is not accidentally programmed as a GPIO, these
five pins default to non-committable. Because of this, the
default reset value of GPIOCR for GPIO Port B is
0x0000.007F while the default reset value of GPIOCR for Port
C is 0x0000.00F0.
7:0 CR - -
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Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 4 (GPIOPeriphID4)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID4 RO 0x00 GPIO Peripheral ID Register[7:0]
192 March 17, 2008
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General-Purpose Input/Outputs (GPIOs)
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 5 (GPIOPeriphID5)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID5 RO 0x00 GPIO Peripheral ID Register[15:8]
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Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 6 (GPIOPeriphID6)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID6 RO 0x00 GPIO Peripheral ID Register[23:16]
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General-Purpose Input/Outputs (GPIOs)
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 7 (GPIOPeriphID7)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID7 RO 0x00 GPIO Peripheral ID Register[31:24]
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Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 0 (GPIOPeriphID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE0
Type RO, reset 0x0000.0061
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID0 RO 0x61
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General-Purpose Input/Outputs (GPIOs)
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 1 (GPIOPeriphID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID1 RO 0x00
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Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 2 (GPIOPeriphID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID2 RO 0x18
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General-Purpose Input/Outputs (GPIOs)
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 3 (GPIOPeriphID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID3 RO 0x01
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Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 0 (GPIOPCellID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
7:0 CID0 RO 0x0D
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General-Purpose Input/Outputs (GPIOs)
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 1 (GPIOPCellID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
7:0 CID1 RO 0xF0
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Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 2 (GPIOPCellID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
7:0 CID2 RO 0x05
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Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 3 (GPIOPCellID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
7:0 CID3 RO 0xB1
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10 General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris® General-Purpose Timer Module (GPTM) contains four GPTM blocks (Timer0, Timer1,
Timer 2, and Timer 3). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA
and TimerB) that can be configured to operate independently as timers or event counters, or
configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be
used to trigger analog-to-digital (ADC) conversions. The trigger signals from all of the general-purpose
timers are ORed together before reaching the ADC module, so only one timer should be used to
trigger ADC events.
The General-Purpose Timer Module is one timing resource available on the Stellaris® microcontrollers.
Other timer resources include the System Timer (SysTick) (see “System Timer
(SysTick)” on page 38).
The following modes are supported:
■ 32-bit Timer modes
– Programmable one-shot timer
– Programmable periodic timer
– Real-Time Clock using 32.768-KHz input clock
– Software-controlled event stalling (excluding RTC mode)
■ 16-bit Timer modes
– General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only)
– Programmable one-shot timer
– Programmable periodic timer
– Software-controlled event stalling
■ 16-bit Input Capture modes
– Input edge count capture
– Input edge time capture
■ 16-bit PWM mode
– Simple PWM mode with software-programmable output inversion of the PWM signal
10.1 Block Diagram
Note: In Figure 10-1 on page 205, the specific CCP pins available depend on the Stellaris® device.
See Table 10-1 on page 205 for the available CCPs.
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Figure 10-1. GPTM Module Block Diagram
TA Comparator
TB Comparator
GPTMTBR
GPTMAR
Clock / Edge
Detect
RTC Divider
Clock / Edge
Detect
TimerA
Interrupt
TimerB
Interrupt
System
Clock
0x0000 (Down Counter Modes)
0x0000 (Down Counter Modes)
32 KHz or
Even CCP Pin
Odd CCP Pin
En
En
TimerA Control
GPTMTAPMR
GPTMTAILR
GPTMTAMATCHR
GPTMTAPR
GPTMTAMR
TimerB Control
GPTMTBPMR
GPTMTBILR
GPTMTBMATCHR
GPTMTBPR
GPTMTBMR
Interrupt / Config
GPTMCFG
GPTMRIS
GPTMICR
GPTMMIS
GPTMIMR
GPTMCTL
Table 10-1. Available CCP Pins
Timer 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin
Timer 0 TimerA CCP0 -
TimerB - CCP1
Timer 1 TimerA CCP2 -
TimerB - CCP3
Timer 2 TimerA - -
TimerB - -
Timer 3 TimerA - -
TimerB - -
10.2 Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit
load/initialization registers and their associated control functions. The exact functionality of each
GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 216),
the GPTM TimerA Mode (GPTMTAMR) register (see page 217), and the GPTM TimerB Mode
(GPTMTBMR) register (see page 219). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
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10.2.1 GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters TimerA and TimerB are initialized to
0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 230) and the GPTM TimerB Interval Load (GPTMTBILR) register
(see page 231). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale
(GPTMTAPR) register (see page 234) and the GPTM TimerB Prescale (GPTMTBPR) register (see
page 235).
10.2.2 32-Bit Timer Operating Modes
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configuration.
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 230
■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 231
■ GPTM TimerA (GPTMTAR) register [15:0], see page 238
■ GPTM TimerB (GPTMTBR) register [15:0], see page 239
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
10.2.2.1 32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB
registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is
determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register
(see page 217), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register.
When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 221), the
timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the
timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to
be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If
configured as a periodic timer, it continues counting.
In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches
the 0x000.0000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status
(GPTMRIS) register (see page 226), and holds it until it is cleared by writing the GPTM Interrupt
Clear (GPTMICR) register (see page 228). If the time-out interrupt is enabled in the GPTM Interrupt
Mask (GPTIMR) register (see page 224), the GPTM also sets the TATOMIS bit in the GPTM Masked
Interrupt Status (GPTMMIS) register (see page 227). The trigger is enabled by setting the TAOTE
bit in GPTMCTL, and can trigger SoC-level events such as ADC conversions.
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If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal
is deasserted.
10.2.2.2 32-Bit Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is
loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA
Match (GPTMTAMATCHR) register (see page 232) by the controller.
The input clock on the CCP0, CCP2, or CCP4 pins is required to be 32.768 KHz in RTC mode. The
clock signal is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter.
When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its
preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until
either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs,
the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the
GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags
are cleared by writing the RTCCINT bit in GPTMICR.
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if
the RTCEN bit is set in GPTMCTL.
10.2.3 16-Bit Timer Operating Modes
The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration
(GPTMCFG) register (see page 216). This section describes each of the GPTM 16-bit modes of
operation. TimerA and TimerB have identical modes, so a single description is given using an n to
reference both.
10.2.3.1 16-Bit One-Shot/Periodic Timer Mode
In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with
an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The
selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR)
register.
When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from
its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from
GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops
counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it
continues counting.
In addition to reloading the count value, the timer generates interrupts and triggers when it reaches
the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is
cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR, the GPTM
also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. The trigger is enabled
by setting the TnOTE bit in the GPTMCTL register, and can trigger SoC-level events such as ADC
conversions.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
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If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal
is deasserted.
The following example shows a variety of configurations for a 16-bit free running timer while using
the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period).
Table 10-2. 16-Bit Timer With Prescaler Configurations
Prescale #Clock (T c)a Max Time Units
00000000 1 1.3107 mS
00000001 2 2.6214 mS
00000010 3 3.9321 mS
------------ -- -- --
11111100 254 332.9229 mS
11111110 255 334.2336 mS
11111111 256 335.5443 mS
a. Tc is the clock period.
10.2.3.2 16-Bit Input Edge Count Mode
Note: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
Note: The prescaler is not available in 16-Bit Input Edge Count mode.
In Edge Count mode, the timer is configured as a down-counter capable of capturing three types
of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit
of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined
by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match
(GPTMTnMATCHR) register is configured so that the difference between the value in the
GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that
must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count
matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the
GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded
using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in
the GPTMCTL register. Once the event count has been reached, all further events are ignored until
TnEN is re-enabled by software.
Figure 10-2 on page 209 shows how input edge count mode works. In this case, the timer start value
is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so that four
edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit after
the current count matches the value in the GPTMnMR register.
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Figure 10-2. 16-Bit Input Edge Count Mode Example
0x000A
0x0006
0x0007
0x0008
0x0009
Input Signal
Timer stops,
flags
asserted
Timer reload
Count on next cycle Ignored Ignored
10.2.3.3 16-Bit Input Edge Time Mode
Note: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
Note: The prescaler is not available in 16-Bit Input Edge Time mode.
In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value
loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of
either rising or falling edges, but not both. The timer is placed into Edge Time mode by setting the
TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined
by the TnEVENT fields of the GPTMCnTL register.
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture.
When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR
register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and
the CnEMIS bit, if the interrupt is not masked).
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the
GPTMnILR register.
Figure 10-3 on page 210 shows how input edge timing mode works. In the diagram, it is assumed
that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture
rising edge events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR
register, and is held there until another rising edge is detected (at which point the new count value
is loaded into GPTMTnR).
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Figure 10-3. 16-Bit Input Edge Time Mode Example
GPTMTnR=Y
Input Signal
Time
Count
GPTMTnR=X GPTMTnR=Z
Z
X
Y
0xFFFF
10.2.3.4 16-Bit PWM Mode
Note: The prescaler is not available in 16-Bit PWM mode.
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled
with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR
field to 0x2.
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from
GPTMTnILR and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL
register. No interrupts or status bits are asserted in PWM mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTM Timern Match
Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by
setting the TnPWML bit in the GPTMCTL register.
Figure 10-4 on page 211 shows how to generate an output PWM with a 1-ms period and a 66% duty
cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML
=1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is
GPTMnMR=0x411A.
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Figure 10-4. 16-Bit PWM Mode Example
Output
Signal
Time
Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR
0xC350
0x411A
TnPWML = 0
TnPWML = 1
TnEN set
10.3 Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0,
TIMER1, TIMER2, and TIMER3 bits in the RCGC1 register.
This section shows module initialization and configuration examples for each of the supported timer
modes.
10.3.1 32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0.
3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR).
5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
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7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
In One-Shot mode, the timer stops counting after step 7 on page 212. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
10.3.2 32-Bit Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on its CCP0, CCP2, or CCP4
pins. To enable the RTC feature, follow these steps:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1.
3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR).
4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired.
5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded
with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared.
10.3.3 16-Bit One-Shot/Periodic Timer Mode
A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4.
3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register:
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register
(GPTMTnPR).
5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR).
6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start
counting.
8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
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In One-Shot mode, the timer stops counting after step 8 on page 212. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
10.3.4 16-Bit Input Edge Count Mode
A timer is configured to Input Edge Count mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.
4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register.
7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.
9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM
Interrupt Clear (GPTMICR) register.
In Input Edge Count Mode, the timer stops after the desired number of edge events has been
detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 213
through step 9 on page 213.
10.3.5 16-Bit Input Edge Timing Mode
A timer is configured to Input Edge Timing mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3.
4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting.
8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM
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Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timern (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
10.3.6 16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field
of the GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
10.4 Register Map
Table 10-3 on page 214 lists the GPTM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that timer’s base address:
■ Timer0: 0x4003.0000
■ Timer1: 0x4003.1000
■ Timer2: 0x4003.2000
■ Timer3: 0x4003.3000
Table 10-3. Timers Register Map
See
Offset Name Type Reset Description page
0x000 GPTMCFG R/W 0x0000.0000 GPTM Configuration 216
0x004 GPTMTAMR R/W 0x0000.0000 GPTM TimerA Mode 217
0x008 GPTMTBMR R/W 0x0000.0000 GPTM TimerB Mode 219
0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 221
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See
Offset Name Type Reset Description page
0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 224
0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 226
0x020 GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 227
0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 228
GPTM TimerA Interval Load 230
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
0x028 GPTMTAILR R/W
0x02C GPTMTBILR R/W 0x0000.FFFF GPTM TimerB Interval Load 231
GPTM TimerA Match 232
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
0x030 GPTMTAMATCHR R/W
0x034 GPTMTBMATCHR R/W 0x0000.FFFF GPTM TimerB Match 233
0x038 GPTMTAPR R/W 0x0000.0000 GPTM TimerA Prescale 234
0x03C GPTMTBPR R/W 0x0000.0000 GPTM TimerB Prescale 235
0x040 GPTMTAPMR R/W 0x0000.0000 GPTM TimerA Prescale Match 236
0x044 GPTMTBPMR R/W 0x0000.0000 GPTM TimerB Prescale Match 237
GPTM TimerA 238
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
0x048 GPTMTAR RO
0x04C GPTMTBR RO 0x0000.FFFF GPTM TimerB 239
10.5 Register Descriptions
The remainder of this section lists and describes the GPTM registers, in numerical order by address
offset.
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Register 1: GPTM Configuration (GPTMCFG), offset 0x000
This register configures the global operation of the GPTM module. The value written to this register
determines whether the GPTM is in 32- or 16-bit mode.
GPTM Configuration (GPTMCFG)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPTMCFG
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
GPTM Configuration
The GPTMCFG values are defined as follows:
Value Description
0x0 32-bit timer configuration.
0x1 32-bit real-time clock (RTC) counter configuration.
0x2 Reserved
0x3 Reserved
16-bit timer configuration, function is controlled by bits 1:0 of
GPTMTAMR and GPTMTBMR.
0x4-0x7
2:0 GPTMCFG R/W 0x0
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General-Purpose Timers
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.
GPTM TimerA Mode (GPTMTAMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TAAMS TACMR TAMR
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
GPTM TimerA Alternate Mode Select
The TAAMS values are defined as follows:
Value Description
0 Capture mode is enabled.
1 PWM mode is enabled.
Note: To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.
3 TAAMS R/W 0
GPTM TimerA Capture Mode
The TACMR values are defined as follows:
Value Description
0 Edge-Count mode
1 Edge-Time mode
2 TACMR R/W 0
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Bit/Field Name Type Reset Description
GPTM TimerA Mode
The TAMR values are defined as follows:
Value Description
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
The Timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register (16-or 32-bit).
In 16-bit timer configuration, TAMR controls the 16-bit timer modes for
TimerA.
In 32-bit timer configuration, this register controls the mode and the
contents of GPTMTBMR are ignored.
1:0 TAMR R/W 0x0
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Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to
0x2.
GPTM TimerB Mode (GPTMTBMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBAMS TBCMR TBMR
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
GPTM TimerB Alternate Mode Select
The TBAMS values are defined as follows:
Value Description
0 Capture mode is enabled.
1 PWM mode is enabled.
Note: To enable PWM mode, you must also clear the TBCMR
bit and set the TBMR field to 0x2.
3 TBAMS R/W 0
GPTM TimerB Capture Mode
The TBCMR values are defined as follows:
Value Description
0 Edge-Count mode
1 Edge-Time mode
2 TBCMR R/W 0
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Bit/Field Name Type Reset Description
GPTM TimerB Mode
The TBMR values are defined as follows:
Value Description
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
The timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
In 16-bit timer configuration, these bits control the 16-bit timer modes
for TimerB.
In 32-bit timer configuration, this register’s contents are ignored and
GPTMTAMR is used.
1:0 TBMR R/W 0x0
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Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBPWML TBOTE reserved TBEVENT TBSTALL TBEN reserved TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN
Type RO R/W R/W RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:15 reserved RO 0x00
GPTM TimerB PWM Output Level
The TBPWML values are defined as follows:
Value Description
0 Output is unaffected.
1 Output is inverted.
14 TBPWML R/W 0
GPTM TimerB Output Trigger Enable
The TBOTE values are defined as follows:
Value Description
0 The output TimerB trigger is disabled.
1 The output TimerB trigger is enabled.
13 TBOTE R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12 reserved RO 0
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Bit/Field Name Type Reset Description
GPTM TimerB Event Mode
The TBEVENT values are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
11:10 TBEVENT R/W 0x0
GPTM TimerB Stall Enable
The TBSTALL values are defined as follows:
Value Description
0 TimerB stalling is disabled.
1 TimerB stalling is enabled.
9 TBSTALL R/W 0
GPTM TimerB Enable
The TBEN values are defined as follows:
Value Description
0 TimerB is disabled.
TimerB is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
8 TBEN R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
GPTM TimerA PWM Output Level
The TAPWML values are defined as follows:
Value Description
0 Output is unaffected.
1 Output is inverted.
6 TAPWML R/W 0
GPTM TimerA Output Trigger Enable
The TAOTE values are defined as follows:
Value Description
0 The output TimerA trigger is disabled.
1 The output TimerA trigger is enabled.
5 TAOTE R/W 0
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Bit/Field Name Type Reset Description
GPTM RTC Enable
The RTCEN values are defined as follows:
Value Description
0 RTC counting is disabled.
1 RTC counting is enabled.
4 RTCEN R/W 0
GPTM TimerA Event Mode
The TAEVENT values are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
3:2 TAEVENT R/W 0x0
GPTM TimerA Stall Enable
The TASTALL values are defined as follows:
Value Description
0 TimerA stalling is disabled.
1 TimerA stalling is enabled.
1 TASTALL R/W 0
GPTM TimerA Enable
The TAEN values are defined as follows:
Value Description
0 TimerA is disabled.
TimerA is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
0 TAEN R/W 0
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Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables
the interrupt, while writing a 0 disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x018
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBEIM CBMIM TBTOIM reserved RTCIM CAEIM CAMIM TATOIM
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Interrupt Mask
The CBEIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
10 CBEIM R/W 0
GPTM CaptureB Match Interrupt Mask
The CBMIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
9 CBMIM R/W 0
GPTM TimerB Time-Out Interrupt Mask
The TBTOIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
8 TBTOIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0
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Bit/Field Name Type Reset Description
GPTM RTC Interrupt Mask
The RTCIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
3 RTCIM R/W 0
GPTM CaptureA Event Interrupt Mask
The CAEIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
2 CAEIM R/W 0
GPTM CaptureA Match Interrupt Mask
The CAMIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
1 CAMIM R/W 0
GPTM TimerA Time-Out Interrupt Mask
The TATOIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
0 TATOIM R/W 0
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Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBERIS CBMRIS TBTORIS reserved RTCRIS CAERIS CAMRIS TATORIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
10 CBERIS RO 0
GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
9 CBMRIS RO 0
GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
8 TBTORIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x0
GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
3 RTCRIS RO 0
GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
2 CAERIS RO 0
GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
1 CAMRIS RO 0
GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
0 TATORIS RO 0
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Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x020
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBEMIS CBMMIS TBTOMIS reserved RTCMIS CAEMIS CAMMIS TATOMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Masked Interrupt
This is the CaptureB event interrupt status after masking.
10 CBEMIS RO 0
GPTM CaptureB Match Masked Interrupt
This is the CaptureB match interrupt status after masking.
9 CBMMIS RO 0
GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
8 TBTOMIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x0
GPTM RTC Masked Interrupt
This is the RTC event interrupt status after masking.
3 RTCMIS RO 0
GPTM CaptureA Event Masked Interrupt
This is the CaptureA event interrupt status after masking.
2 CAEMIS RO 0
GPTM CaptureA Match Masked Interrupt
This is the CaptureA match interrupt status after masking.
1 CAMMIS RO 0
GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
0 TATOMIS RO 0
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Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x024
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBECINT CBMCINT TBTOCINT reserved RTCCINT CAECINT CAMCINT TATOCINT
Type RO RO RO RO RO W1C W1C W1C RO RO RO RO W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Interrupt Clear
The CBECINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
10 CBECINT W1C 0
GPTM CaptureB Match Interrupt Clear
The CBMCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
9 CBMCINT W1C 0
GPTM TimerB Time-Out Interrupt Clear
The TBTOCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
8 TBTOCINT W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x0
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Bit/Field Name Type Reset Description
GPTM RTC Interrupt Clear
The RTCCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
3 RTCCINT W1C 0
GPTM CaptureA Event Interrupt Clear
The CAECINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
2 CAECINT W1C 0
GPTM CaptureA Match Raw Interrupt
This is the CaptureA match interrupt status after masking.
1 CAMCINT W1C 0
GPTM TimerA Time-Out Raw Interrupt
The TATOCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
0 TATOCINT W1C 0
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Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028
This register is used to load the starting count value into the timer. When GPTM is configured to
one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond
to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
GPTM TimerA Interval Load (GPTMTAILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x028
Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAILRH
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAILRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
GPTM TimerA Interval Load Register High
When configured for 32-bit mode via the GPTMCFG register, the GPTM
TimerB Interval Load (GPTMTBILR) register loads this value on a
write. A read returns the current value of GPTMTBILR.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBILR.
0xFFFF
(32-bit mode)
0x0000 (16-bit
mode)
31:16 TAILRH R/W
GPTM TimerA Interval Load Register Low
For both 16- and 32-bit modes, writing this field loads the counter for
TimerA. A read returns the current value of GPTMTAILR.
15:0 TAILRL R/W 0xFFFF
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Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C
This register is used to load the starting count value into TimerB. When the GPTM is configured to
a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes.
GPTM TimerB Interval Load (GPTMTBILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBILRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
GPTM TimerB Interval Load Register
When the GPTM is not configured as a 32-bit timer, a write to this field
updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads
return the current value of GPTMTBILR.
15:0 TBILRL R/W 0xFFFF
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Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerA Match (GPTMTAMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x030
Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMRH
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
GPTM TimerA Match Register High
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the upper half of
GPTMTAR, to determine match events.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBMATCHR.
0xFFFF
(32-bit mode)
0x0000 (16-bit
mode)
31:16 TAMRH R/W
GPTM TimerA Match Register Low
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the lower half of
GPTMTAR, to determine match events.
When configured for PWM mode, this value along with GPTMTAILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTAILR
minus this value.
15:0 TAMRL R/W 0xFFFF
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Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034
This register is used in 16-bit PWM and Input Edge Count modes.
GPTM TimerB Match (GPTMTBMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x034
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBMRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
GPTM TimerB Match Register Low
When configured for PWM mode, this value along with GPTMTBILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTBILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTBILR
minus this value.
15:0 TBMRL R/W 0xFFFF
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Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerA Prescale (GPTMTAPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TAPSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerA Prescale
The register loads this value on a write. A read returns the current value
of the register.
Refer to Table 10-2 on page 208 for more details and an example.
7:0 TAPSR R/W 0x00
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General-Purpose Timers
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerB Prescale (GPTMTBPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x03C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBPSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerB Prescale
The register loads this value on a write. A read returns the current value
of this register.
Refer to Table 10-2 on page 208 for more details and an example.
7:0 TBPSR R/W 0x00
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LM3S8933 Microcontroller
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040
This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerA Prescale Match (GPTMTAPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x040
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TAPSMR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerA Prescale Match
This value is used alongside GPTMTAMATCHR to detect timer match
events while using a prescaler.
7:0 TAPSMR R/W 0x00
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General-Purpose Timers
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044
This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerB Prescale Match (GPTMTBPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x044
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBPSMR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerB Prescale Match
This value is used alongside GPTMTBMATCHR to detect timer match
events while using a prescaler.
7:0 TBPSMR R/W 0x00
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LM3S8933 Microcontroller
Register 17: GPTM TimerA (GPTMTAR), offset 0x048
This register shows the current value of the TimerA counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerA (GPTMTAR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x048
Type RO, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TARH
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TARL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
GPTM TimerA Register High
If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the
GPTMCFG is in a 16-bit mode, this is read as zero.
0xFFFF
(32-bit mode)
0x0000 (16-bit
mode)
31:16 TARH RO
GPTM TimerA Register Low
A read returns the current value of the GPTM TimerA Count Register,
except in Input Edge Count mode, when it returns the timestamp from
the last edge event.
15:0 TARL RO 0xFFFF
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General-Purpose Timers
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C
This register shows the current value of the TimerB counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerB (GPTMTBR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x04C
Type RO, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBRL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
GPTM TimerB
A read returns the current value of the GPTM TimerB Count Register,
except in Input Edge Count mode, when it returns the timestamp from
the last edge event.
15:0 TBRL RO 0xFFFF
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LM3S8933 Microcontroller
11 Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
The Stellaris® Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, a locking register, and user-enabled stalling.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
11.1 Block Diagram
Figure 11-1. WDT Module Block Diagram
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
WDTRIS
WDTMIS
WDTLOCK
WDTTEST
WDTLOAD
WDTVALUE
Comparator
32-Bit Down
Counter
0x00000000
Interrupt
System Clock
Identification Registers
WDTPCellID0 WDTPeriphID0 WDTPeriphID4
WDTPCellID1 WDTPeriphID1 WDTPeriphID5
WDTPCellID2 WDTPeriphID2 WDTPeriphID6
WDTPCellID3 WDTPeriphID3 WDTPeriphID7
11.2 Functional Description
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the
240 March 17, 2008
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Watchdog Timer
Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written,
which prevents the timer configuration from being inadvertently altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) register.
The Watchdog module interrupt and reset generation can be enabled or disabled as required. When
the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its
last state.
11.3 Initialization and Configuration
To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register.
The Watchdog Timer is configured using the following sequence:
1. Load the WDTLOAD register with the desired timer load value.
2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.
3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register.
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write
a value of 0x1ACC.E551.
11.4 Register Map
Table 11-1 on page 241 lists the Watchdog registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000.
Table 11-1. Watchdog Timer Register Map
See
Offset Name Type Reset Description page
0x000 WDTLOAD R/W 0xFFFF.FFFF Watchdog Load 243
0x004 WDTVALUE RO 0xFFFF.FFFF Watchdog Value 244
0x008 WDTCTL R/W 0x0000.0000 Watchdog Control 245
0x00C WDTICR WO - Watchdog Interrupt Clear 246
0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 247
0x014 WDTMIS RO 0x0000.0000 Watchdog Masked Interrupt Status 248
0x418 WDTTEST R/W 0x0000.0000 Watchdog Test 249
0xC00 WDTLOCK R/W 0x0000.0000 Watchdog Lock 250
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LM3S8933 Microcontroller
See
Offset Name Type Reset Description page
0xFD0 WDTPeriphID4 RO 0x0000.0000 Watchdog Peripheral Identification 4 251
0xFD4 WDTPeriphID5 RO 0x0000.0000 Watchdog Peripheral Identification 5 252
0xFD8 WDTPeriphID6 RO 0x0000.0000 Watchdog Peripheral Identification 6 253
0xFDC WDTPeriphID7 RO 0x0000.0000 Watchdog Peripheral Identification 7 254
0xFE0 WDTPeriphID0 RO 0x0000.0005 Watchdog Peripheral Identification 0 255
0xFE4 WDTPeriphID1 RO 0x0000.0018 Watchdog Peripheral Identification 1 256
0xFE8 WDTPeriphID2 RO 0x0000.0018 Watchdog Peripheral Identification 2 257
0xFEC WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 258
0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 259
0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 260
0xFF8 WDTPCellID2 RO 0x0000.0005 Watchdog PrimeCell Identification 2 261
0xFFC WDTPCellID3 RO 0x0000.00B1 Watchdog PrimeCell Identification 3 262
11.5 Register Descriptions
The remainder of this section lists and describes the WDT registers, in numerical order by address
offset.
242 March 17, 2008
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Watchdog Timer
Register 1: Watchdog Load (WDTLOAD), offset 0x000
This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the
value is immediately loaded and the counter restarts counting down from the new value. If the
WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated.
Watchdog Load (WDTLOAD)
Base 0x4000.0000
Offset 0x000
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTLoad
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTLoad
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
31:0 WDTLoad R/W 0xFFFF.FFFF Watchdog Load Value
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LM3S8933 Microcontroller
Register 2: Watchdog Value (WDTVALUE), offset 0x004
This register contains the current count value of the timer.
Watchdog Value (WDTVALUE)
Base 0x4000.0000
Offset 0x004
Type RO, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTValue
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTValue
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Watchdog Value
Current value of the 32-bit down counter.
31:0 WDTValue RO 0xFFFF.FFFF
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Watchdog Timer
Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.
Watchdog Control (WDTCTL)
Base 0x4000.0000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RESEN INTEN
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Watchdog Reset Enable
The RESEN values are defined as follows:
Value Description
0 Disabled.
1 Enable the Watchdog module reset output.
1 RESEN R/W 0
Watchdog Interrupt Enable
The INTEN values are defined as follows:
Value Description
Interrupt event disabled (once this bit is set, it can only be
cleared by a hardware reset).
0
1 Interrupt event enabled. Once enabled, all writes are ignored.
0 INTEN R/W 0
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LM3S8933 Microcontroller
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C
This register is the interrupt clear register. A write of any value to this register clears the Watchdog
interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is
indeterminate.
Watchdog Interrupt Clear (WDTICR)
Base 0x4000.0000
Offset 0x00C
Type WO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTIntClr
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTIntClr
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
31:0 WDTIntClr WO - Watchdog Interrupt Clear
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Watchdog Timer
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010
This register is the raw interrupt status register. Watchdog interrupt events can be monitored via
this register if the controller interrupt is masked.
Watchdog Raw Interrupt Status (WDTRIS)
Base 0x4000.0000
Offset 0x010
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WDTRIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Watchdog Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of WDTINTR.
0 WDTRIS RO 0
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LM3S8933 Microcontroller
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.
Watchdog Masked Interrupt Status (WDTMIS)
Base 0x4000.0000
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WDTMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Watchdog Masked Interrupt Status
Gives the masked interrupt state (after masking) of the WDTINTR
interrupt.
0 WDTMIS RO 0
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Watchdog Timer
Register 7: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
Watchdog Test (WDTTEST)
Base 0x4000.0000
Offset 0x418
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved STALL reserved
Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:9 reserved RO 0x00
Watchdog Stall Enable
When set to 1, if the Stellaris® microcontroller is stopped with a
debugger, the watchdog timer stops counting. Once the microcontroller
is restarted, the watchdog timer resumes counting.
8 STALL R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0 reserved RO 0x00
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LM3S8933 Microcontroller
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00
Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing
any other value to the WDTLOCK register re-enables the locked state for register writes to all the
other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value
written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns
0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)).
Watchdog Lock (WDTLOCK)
Base 0x4000.0000
Offset 0xC00
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTLock
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTLock
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Watchdog Lock
A write of the value 0x1ACC.E551 unlocks the watchdog registers for
write access. A write of any other value reapplies the lock, preventing
any register updates.
A read of this register returns the following values:
Value Description
0x0000.0001 Locked
0x0000.0000 Unlocked
31:0 WDTLock R/W 0x0000
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Watchdog Timer
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 4 (WDTPeriphID4)
Base 0x4000.0000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID4 RO 0x00 WDT Peripheral ID Register[7:0]
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LM3S8933 Microcontroller
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset
0xFD4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 5 (WDTPeriphID5)
Base 0x4000.0000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID5 RO 0x00 WDT Peripheral ID Register[15:8]
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Watchdog Timer
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset
0xFD8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 6 (WDTPeriphID6)
Base 0x4000.0000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID6 RO 0x00 WDT Peripheral ID Register[23:16]
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LM3S8933 Microcontroller
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset
0xFDC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 7 (WDTPeriphID7)
Base 0x4000.0000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID7 RO 0x00 WDT Peripheral ID Register[31:24]
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Watchdog Timer
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset
0xFE0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 0 (WDTPeriphID0)
Base 0x4000.0000
Offset 0xFE0
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID0 RO 0x05 Watchdog Peripheral ID Register[7:0]
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Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset
0xFE4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 1 (WDTPeriphID1)
Base 0x4000.0000
Offset 0xFE4
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID1 RO 0x18 Watchdog Peripheral ID Register[15:8]
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Watchdog Timer
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset
0xFE8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 2 (WDTPeriphID2)
Base 0x4000.0000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID2 RO 0x18 Watchdog Peripheral ID Register[23:16]
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Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset
0xFEC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 3 (WDTPeriphID3)
Base 0x4000.0000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID3 RO 0x01 Watchdog Peripheral ID Register[31:24]
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Watchdog Timer
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 0 (WDTPCellID0)
Base 0x4000.0000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID0 RO 0x0D Watchdog PrimeCell ID Register[7:0]
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Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 1 (WDTPCellID1)
Base 0x4000.0000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID1 RO 0xF0 Watchdog PrimeCell ID Register[15:8]
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Watchdog Timer
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 2 (WDTPCellID2)
Base 0x4000.0000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID2 RO 0x05 Watchdog PrimeCell ID Register[23:16]
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Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 3 (WDTPCellID3)
Base 0x4000.0000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID3 RO 0xB1 Watchdog PrimeCell ID Register[31:24]
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Watchdog Timer
12 Analog-to-Digital Converter (ADC)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The Stellaris® ADC module features 10-bit conversion resolution and supports four input channels,
plus an internal temperature sensor. The ADC module contains a programmable sequencer which
allows for the sampling of multiple analog input sources without controller intervention. Each sample
sequence provides flexible programming with fully configurable input source, trigger events, interrupt
generation, and sequence priority.
The Stellaris® ADC provides the following features:
■ Four analog input channels
■ Single-ended and differential-input configurations
■ Internal temperature sensor
■ Sample rate of one million samples/second
■ Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
■ Flexible trigger control
– Controller (software)
– Timers
– Analog Comparators
– GPIO
■ Hardware averaging of up to 64 samples for improved accuracy
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12.1 Block Diagram
Figure 12-1. ADC Module Block Diagram
Analog-to-Digital
Converter
ADCSSFSTAT0
ADCSSCTL0
ADCSSMUX0
Sample
Sequencer 0
ADCSSFSTAT1
ADCSSCTL1
ADCSSMUX1
Sample
Sequencer 1
ADCSSFSTAT2
ADCSSCTL2
ADCSSMUX2
Sample
Sequencer 2
ADCSSFSTAT3
ADCSSCTL3
ADCSSMUX3
Sample
Sequencer 3
ADCUSTAT
ADCOSTAT
ADCACTSS
Control/Status
ADCSSPRI
ADCISC
ADCRIS
ADCIM
Interrupt Control
Analog Inputs
SS0 Interrupt
SS1 Interrupt
SS2 Interrupt
SS3 Interrupt
ADCEMUX
ADCPSSI
Trigger Events
SS0
SS1
SS2
SS3
Comparator
GPIO (PB4)
Timer
PWM
Comparator
GPIO (PB4)
Timer
PWM
Comparator
GPIO (PB4)
Timer
PWM
Comparator
GPIO (PB4)
Timer
PWM
ADCSSFIFO0
ADCSSFIFO1
ADCSSFIFO2
ADCSSFIFO3
FIFO Block
Hardware Averager
ADCSAC
12.2 Functional Description
The Stellaris® ADC collects sample data by using a programmable sequence-based approach
instead of the traditional single or double-sampling approach found on many ADC modules. Each
sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the
ADC to collect data from multiple input sources without having to be re-configured or serviced by
the controller. The programming of each sample in the sample sequence includes parameters such
as the input source and mode (differential versus single-ended input), interrupt generation on sample
completion, and the indicator for the last sample in the sequence.
12.2.1 Sample Sequencers
The sampling control and data capture is handled by the Sample Sequencers. All of the sequencers
are identical in implementation except for the number of samples that can be captured and the depth
of the FIFO. Table 12-1 on page 264 shows the maximum number of samples that each Sequencer
can capture and its corresponding FIFO depth. In this implementation, each FIFO entry is a 32-bit
word, with the lower 10 bits containing the conversion result.
Table 12-1. Samples and FIFO Depth of Sequencers
Sequencer Number of Samples Depth of FIFO
SS3 1 1
SS2 4 4
SS1 4 4
SS0 8 8
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For a given sample sequence, each sample is defined by two 4-bit nibbles in the ADC Sample
Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control
(ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn
nibbles select the input pin, while the ADCSSCTLn nibbles contain the sample control bits
corresponding to parameters such as temperature sensor selection, interrupt enable, end of
sequence, and differential input mode. Sample Sequencers are enabled by setting the respective
ASENn bit in the ADC Active Sample Sequencer (ADCACTSS) register, but can be configured
before being enabled.
When configuring a sample sequence, multiple uses of the same input pin within the same sequence
is allowed. In the ADCSSCTLn register, the Interrupt Enable (IE) bits can be set for any
combination of samples, allowing interrupts to be generated after every sample in the sequence if
necessary. Also, the END bit can be set at any point within a sample sequence. For example, if
Sequencer 0 is used, the END bit can be set in the nibble associated with the fifth sample, allowing
Sequencer 0 to complete execution of the sample sequence after the fifth sample.
After a sample sequence completes execution, the result data can be retrieved from the ADC
Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers
that read a single address to "pop" result data. For software debug purposes, the positions of the
FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn)
registers along with FULL and EMPTY status flags. Overflow and underflow conditions are monitored
using the ADCOSTAT and ADCUSTAT registers.
12.2.2 Module Control
Outside of the Sample Sequencers, the remainder of the control logic is responsible for tasks such
as interrupt generation, sequence prioritization, and trigger configuration.
Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider
is configured automatically by hardware when the system XTAL is selected. The automatic clock
divider configuration targets 16.667 MHz operation for all Stellaris® devices.
12.2.2.1 Interrupts
The Sample Sequencers dictate the events that cause interrupts, but they don't have control over
whether the interrupt is actually sent to the interrupt controller. The ADC module's interrupt signal
is controlled by the state of the MASK bits in the ADC Interrupt Mask (ADCIM) register. Interrupt
status can be viewed at two locations: the ADC Raw Interrupt Status (ADCRIS) register, which
shows the raw status of a Sample Sequencer's interrupt signal, and the ADC Interrupt Status and
Clear (ADCISC) register, which shows the logical AND of the ADCRIS register’s INR bit and the
ADCIM register’s MASK bits. Interrupts are cleared by writing a 1 to the corresponding IN bit in
ADCISC.
12.2.2.2 Prioritization
When sampling events (triggers) happen concurrently, they are prioritized for processing by the
values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in
the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active Sample
Sequencer units with the same priority do not provide consistent results, so software must ensure
that all active Sample Sequencer units have a unique priority value.
12.2.2.3 Sampling Events
Sample triggering for each Sample Sequencer is defined in the ADC Event Multiplexer Select
(ADCEMUX) register. The external peripheral triggering sources vary by Stellaris® family member,
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but all devices share the "Controller" and "Always" triggers. Software can initiate sampling by setting
the CH bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register.
When using the "Always" trigger, care must be taken. If a sequence's priority is too high, it is possible
to starve other lower priority sequences.
12.2.3 Hardware Sample Averaging Circuit
Higher precision results can be generated using the hardware averaging circuit, however, the
improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged
to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the
number of samples in the averaging calculation. For example, if the averaging circuit is configured
to average 16 samples, the throughput is decreased by a factor of 16.
By default the averaging circuit is off and all data from the converter passes through to the sequencer
FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC)
register (see page 282). There is a single averaging circuit and all input channels receive the same
amount of averaging whether they are single-ended or differential.
12.2.4 Analog-to-Digital Converter
The converter itself generates a 10-bit output value for selected analog input. Special analog pads
are used to minimize the distortion on the input. An internal 3 V reference is used by the converter
resulting in sample values ranging from 0x000 at 0 V input to 0x3FF at 3 V input when in single-ended
input mode.
12.2.5 Differential Sampling
In addition to traditional single-ended sampling, the ADC module supports differential sampling of
two analog input channels. To enable differential sampling, software must set the D bit in a step's
configuration nibble.
When a sequence step is configured for differential sampling, its corresponding value in the
ADCSSMUX register must be set to one of the four differential pairs, numbered 0-3. Differential pair
0 samples analog inputs 0 and 1; differential pair 1 samples analog inputs 2 and 3; and so on (see
Table 12-2 on page 266). The ADC does not support other differential pairings such as analog input
0 with analog input 3. The number of differential pairs supported is dependent on the number of
analog inputs (see Table 12-2 on page 266).
Table 12-2. Differential Sampling Pairs
Differential Pair Analog Inputs
0 0 and 1
1 2 and 3
The voltage sampled in differential mode is the difference between the odd and even channels:
ΔV (differential voltage) = V0 (even channels) – V1 (odd channels), therefore:
■ If ΔV = 0, then the conversion result = 0x1FF
■ If ΔV > 0, then the conversion result > 0x1FF (range is 0x1FF–0x3FF)
■ If ΔV < 0, then the conversion result < 0x1FF (range is 0–0x1FF)
The differential pairs assign polarities to the analog inputs: the even-numbered input is always
positive, and the odd-numbered input is always negative. In order for a valid conversion result to
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appear, the negative input must be in the range of ± 1.5 V of the positive input. If an analog input
is greater than 3 V or less than 0 V (the valid range for analog inputs), the input voltage is clipped,
meaning it appears as either 3 V or 0 V, respectively, to the ADC.
Figure 12-2 on page 267 shows an example of the negative input centered at 1.5 V. In this
configuration, the differential range spans from -1.5 V to 1.5 V. Figure 12-3 on page 267 shows an
example where the negative input is centered at -0.75 V, meaning inputs on the positive input
saturate past a differential voltage of -0.75 V since the input voltage is less than 0 V. Figure
12-4 on page 268 shows an example of the negative input centered at 2.25 V, where inputs on the
positive channel saturate past a differential voltage of 0.75 V since the input voltage would be greater
than 3 V.
Figure 12-2. Differential Sampling Range, Vin(-) = 1.5 V
ADC Conversion Result
Differential Voltage,
Vin (+) = 1.5V
-1.5V +1.5V
0x1FF
0x3FF
- Input Saturation
Figure 12-3. Differential Sampling Range, Vin(-) = 0.75 V
ADC Conversion Result
-1.5V +1.5V
0x1FF
0x3FF
Differential Voltage,
Vin (+) = 0.75V
0x0FF
-0.75V
- Input Saturation
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Figure 12-4. Differential Sampling Range, Vin(-) = 2.25 V
ADC Conversion Result
-1.5V +1.5V
0x1FF
0x3FF
Differential Voltage,
Vin (+) = 2.25V
0x2FF
+0.75V
- Input Saturation
12.2.6 Test Modes
There is a user-available test mode that allows for loopback operation within the digital portion of
the ADC module. This can be useful for debugging software without having to provide actual analog
stimulus. This mode is available through the ADC Test Mode Loopback (ADCTMLB) register (see
page 295).
12.2.7 Internal Temperature Sensor
The internal temperature sensor provides an analog temperature reading as well as a reference
voltage. The voltage at the output terminal SENSO is given by the following equation:
SENSO = 2.7 - ((T + 55) / 75)
This relation is shown in Figure 12-5 on page 268.
Figure 12-5. Internal Temperature Sensor Characteristic
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12.3 Initialization and Configuration
In order for the ADC module to be used, the PLL must be enabled and using a supported crystal
frequency (see the RCC register). Using unsupported frequencies can cause faulty operation in the
ADC module.
12.3.1 Module Initialization
Initialization of the ADC module is a simple process with very few steps. The main steps include
enabling the clock to the ADC and reconfiguring the Sample Sequencer priorities (if needed).
The initialization sequence for the ADC is as follows:
1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC1 register (see page 99).
2. If required by the application, reconfigure the Sample Sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority, and Sample
Sequencer 3 as the lowest priority.
12.3.2 Sample Sequencer Configuration
Configuration of the Sample Sequencers is slightly more complex than the module initialization
since each sample sequence is completely programmable.
The configuration for each Sample Sequencer should be as follows:
1. Ensure that the Sample Sequencer is disabled by writing a 0 to the corresponding ASEN bit in
the ADCACTSS register. Programming of the Sample Sequencers is allowed without having
them enabled. Disabling the Sequencer during programming prevents erroneous execution if
a trigger event were to occur during the configuration process.
2. Configure the trigger event for the Sample Sequencer in the ADCEMUX register.
3. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn register.
4. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register.
6. Enable the Sample Sequencer logic by writing a 1 to the corresponding ASEN bit in the
ADCACTSS register.
12.4 Register Map
Table 12-3 on page 269 lists the ADC registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the ADC base address of 0x4003.8000.
Table 12-3. ADC Register Map
See
Offset Name Type Reset Description page
0x000 ADCACTSS R/W 0x0000.0000 ADC Active Sample Sequencer 271
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See
Offset Name Type Reset Description page
0x004 ADCRIS RO 0x0000.0000 ADC Raw Interrupt Status 272
0x008 ADCIM R/W 0x0000.0000 ADC Interrupt Mask 273
0x00C ADCISC R/W1C 0x0000.0000 ADC Interrupt Status and Clear 274
0x010 ADCOSTAT R/W1C 0x0000.0000 ADC Overflow Status 275
0x014 ADCEMUX R/W 0x0000.0000 ADC Event Multiplexer Select 276
0x018 ADCUSTAT R/W1C 0x0000.0000 ADC Underflow Status 279
0x020 ADCSSPRI R/W 0x0000.3210 ADC Sample Sequencer Priority 280
0x028 ADCPSSI WO - ADC Processor Sample Sequence Initiate 281
0x030 ADCSAC R/W 0x0000.0000 ADC Sample Averaging Control 282
0x040 ADCSSMUX0 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 0 283
0x044 ADCSSCTL0 R/W 0x0000.0000 ADC Sample Sequence Control 0 285
0x048 ADCSSFIFO0 RO 0x0000.0000 ADC Sample Sequence Result FIFO 0 288
0x04C ADCSSFSTAT0 RO 0x0000.0100 ADC Sample Sequence FIFO 0 Status 289
0x060 ADCSSMUX1 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 1 290
0x064 ADCSSCTL1 R/W 0x0000.0000 ADC Sample Sequence Control 1 291
0x068 ADCSSFIFO1 RO 0x0000.0000 ADC Sample Sequence Result FIFO 1 288
0x06C ADCSSFSTAT1 RO 0x0000.0100 ADC Sample Sequence FIFO 1 Status 289
0x080 ADCSSMUX2 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 2 290
0x084 ADCSSCTL2 R/W 0x0000.0000 ADC Sample Sequence Control 2 291
0x088 ADCSSFIFO2 RO 0x0000.0000 ADC Sample Sequence Result FIFO 2 288
0x08C ADCSSFSTAT2 RO 0x0000.0100 ADC Sample Sequence FIFO 2 Status 289
0x0A0 ADCSSMUX3 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 3 293
0x0A4 ADCSSCTL3 R/W 0x0000.0002 ADC Sample Sequence Control 3 294
0x0A8 ADCSSFIFO3 RO 0x0000.0000 ADC Sample Sequence Result FIFO 3 288
0x0AC ADCSSFSTAT3 RO 0x0000.0100 ADC Sample Sequence FIFO 3 Status 289
0x100 ADCTMLB R/W 0x0000.0000 ADC Test Mode Loopback 295
12.5 Register Descriptions
The remainder of this section lists and describes the ADC registers, in numerical order by address
offset.
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Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000
This register controls the activation of the Sample Sequencers. Each Sample Sequencer can be
enabled/disabled independently.
ADC Active Sample Sequencer (ADCACTSS)
Base 0x4003.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ASEN3 ASEN2 ASEN1 ASEN0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
ADC SS3 Enable
Specifies whether Sample Sequencer 3 is enabled. If set, the sample
sequence logic for Sequencer 3 is active. Otherwise, the Sequencer is
inactive.
3 ASEN3 R/W 0
ADC SS2 Enable
Specifies whether Sample Sequencer 2 is enabled. If set, the sample
sequence logic for Sequencer 2 is active. Otherwise, the Sequencer is
inactive.
2 ASEN2 R/W 0
ADC SS1 Enable
Specifies whether Sample Sequencer 1 is enabled. If set, the sample
sequence logic for Sequencer 1 is active. Otherwise, the Sequencer is
inactive.
1 ASEN1 R/W 0
ADC SS0 Enable
Specifies whether Sample Sequencer 0 is enabled. If set, the sample
sequence logic for Sequencer 0 is active. Otherwise, the Sequencer is
inactive.
0 ASEN0 R/W 0
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Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each Sample Sequencer. These bits
may be polled by software to look for interrupt conditions without having to generate controller
interrupts.
ADC Raw Interrupt Status (ADCRIS)
Base 0x4003.8000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved INR3 INR2 INR1 INR0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SS3 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL3 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN3 bit.
3 INR3 RO 0
SS2 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL2 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN2 bit.
2 INR2 RO 0
SS1 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL1 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN1 bit.
1 INR1 RO 0
SS0 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL0 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN0 bit.
0 INR0 RO 0
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Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the Sample Sequencer raw interrupt signals are promoted to controller
interrupts. The raw interrupt signal for each Sample Sequencer can be masked independently.
ADC Interrupt Mask (ADCIM)
Base 0x4003.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MASK3 MASK2 MASK1 MASK0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SS3 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 3
(ADCRIS register INR3 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
3 MASK3 R/W 0
SS2 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 2
(ADCRIS register INR2 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
2 MASK2 R/W 0
SS1 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 1
(ADCRIS register INR1 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
1 MASK1 R/W 0
SS0 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 0
(ADCRIS register INR0 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
0 MASK0 R/W 0
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Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C
This register provides the mechanism for clearing interrupt conditions, and shows the status of
controller interrupts generated by the Sample Sequencers. When read, each bit field is the logical
AND of the respective INR and MASK bits. Interrupts are cleared by writing a 1 to the corresponding
bit position. If software is polling the ADCRIS instead of generating interrupts, the INR bits are still
cleared via the ADCISC register, even if the IN bit is not set.
ADC Interrupt Status and Clear (ADCISC)
Base 0x4003.8000
Offset 0x00C
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN3 IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SS3 Interrupt Status and Clear
This bit is set by hardware when the MASK3 and INR3 bits are both 1,
providing a level-based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR3 bit.
3 IN3 R/W1C 0
SS2 Interrupt Status and Clear
This bit is set by hardware when the MASK2 and INR2 bits are both 1,
providing a level based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR2 bit.
2 IN2 R/W1C 0
SS1 Interrupt Status and Clear
This bit is set by hardware when the MASK1 and INR1 bits are both 1,
providing a level based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR1 bit.
1 IN1 R/W1C 0
SS0 Interrupt Status and Clear
This bit is set by hardware when the MASK0 and INR0 bits are both 1,
providing a level based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR0 bit.
0 IN0 R/W1C 0
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Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010
This register indicates overflow conditions in the Sample Sequencer FIFOs. Once the overflow
condition has been handled by software, the condition can be cleared by writing a 1 to the
corresponding bit position.
ADC Overflow Status (ADCOSTAT)
Base 0x4003.8000
Offset 0x010
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OV3 OV2 OV1 OV0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SS3 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 3 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
3 OV3 R/W1C 0
SS2 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 2 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
2 OV2 R/W1C 0
SS1 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 1 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
1 OV1 R/W1C 0
SS0 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 0 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
0 OV0 R/W1C 0
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Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014
The ADCEMUX selects the event (trigger) that initiates sampling for each Sample Sequencer. Each
Sample Sequencer can be configured with a unique trigger source.
ADC Event Multiplexer Select (ADCEMUX)
Base 0x4003.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM3 EM2 EM1 EM0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
SS3 Trigger Select
This field selects the trigger source for Sample Sequencer 3.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
0x6 Reserved
0x7 Reserved
0x8 Reserved
0x9-0xE reserved
0xF Always (continuously sample)
15:12 EM3 R/W 0x00
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Bit/Field Name Type Reset Description
SS2 Trigger Select
This field selects the trigger source for Sample Sequencer 2.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
0x6 Reserved
0x7 Reserved
0x8 Reserved
0x9-0xE reserved
0xF Always (continuously sample)
11:8 EM2 R/W 0x00
SS1 Trigger Select
This field selects the trigger source for Sample Sequencer 1.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
0x6 Reserved
0x7 Reserved
0x8 Reserved
0x9-0xE reserved
0xF Always (continuously sample)
7:4 EM1 R/W 0x00
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Bit/Field Name Type Reset Description
SS0 Trigger Select
This field selects the trigger source for Sample Sequencer 0.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
0x5 Timer
0x6 Reserved
0x7 Reserved
0x8 Reserved
0x9-0xE reserved
0xF Always (continuously sample)
3:0 EM0 R/W 0x00
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Analog-to-Digital Converter (ADC)
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018
This register indicates underflow conditions in the Sample Sequencer FIFOs. The corresponding
underflow condition can be cleared by writing a 1 to the relevant bit position.
ADC Underflow Status (ADCUSTAT)
Base 0x4003.8000
Offset 0x018
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved UV3 UV2 UV1 UV0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SS3 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 3 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
3 UV3 R/W1C 0
SS2 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 2 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
2 UV2 R/W1C 0
SS1 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 1 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
1 UV1 R/W1C 0
SS0 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 0 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
0 UV0 R/W1C 0
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Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020
This register sets the priority for each of the Sample Sequencers. Out of reset, Sequencer 0 has
the highest priority, and sample sequence 3 has the lowest priority. When reconfiguring sequence
priorities, each sequence must have a unique priority or the ADC behavior is inconsistent.
ADC Sample Sequencer Priority (ADCSSPRI)
Base 0x4003.8000
Offset 0x020
Type R/W, reset 0x0000.3210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SS3 reserved SS2 reserved SS1 reserved SS0
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x00
SS3 Priority
The SS3 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 3. A priority encoding of 0 is highest
and 3 is lowest. The priorities assigned to the Sequencers must be
uniquely mapped. ADC behavior is not consistent if two or more fields
are equal.
13:12 SS3 R/W 0x3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0x0
SS2 Priority
The SS2 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 2.
9:8 SS2 R/W 0x2
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0x0
SS1 Priority
The SS1 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 1.
5:4 SS1 R/W 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0x0
SS0 Priority
The SS0 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 0.
1:0 SS0 R/W 0x0
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Analog-to-Digital Converter (ADC)
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028
This register provides a mechanism for application software to initiate sampling in the Sample
Sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.
ADC Processor Sample Sequence Initiate (ADCPSSI)
Base 0x4003.8000
Offset 0x028
Type WO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SS3 SS2 SS1 SS0
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved WO -
SS3 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 3, assuming the Sequencer is enabled in the ADCACTSS
register.
3 SS3 WO -
SS2 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 2, assuming the Sequencer is enabled in the ADCACTSS
register.
2 SS2 WO -
SS1 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 1, assuming the Sequencer is enabled in the ADCACTSS
register.
1 SS1 WO -
SS0 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 0, assuming the Sequencer is enabled in the ADCACTSS
register.
0 SS0 WO -
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Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030
This register controls the amount of hardware averaging applied to conversion results. The final
conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified
ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6,
then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An
AVG = 7 provides unpredictable results.
ADC Sample Averaging Control (ADCSAC)
Base 0x4003.8000
Offset 0x030
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved AVG
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Hardware Averaging Control
Specifies the amount of hardware averaging that will be applied to ADC
samples. The AVG field can be any value between 0 and 6. Entering a
value of 7 creates unpredictable results.
Value Description
0x0 No hardware oversampling
0x1 2x hardware oversampling
0x2 4x hardware oversampling
0x3 8x hardware oversampling
0x4 16x hardware oversampling
0x5 32x hardware oversampling
0x6 64x hardware oversampling
0x7 Reserved
2:0 AVG R/W 0x0
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Analog-to-Digital Converter (ADC)
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0),
offset 0x040
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 0.
This register is 32-bits wide and contains information for eight possible samples.
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0)
Base 0x4003.8000
Offset 0x040
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved MUX7 reserved MUX6 reserved MUX5 reserved MUX4
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:30 reserved RO 0
8th Sample Input Select
The MUX7 field is used during the eighth sample of a sequence executed
with the Sample Sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion. The value set here indicates
the corresponding pin, for example, a value of 1 indicates the input is
ADC1.
29:28 MUX7 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:26 reserved RO 0
7th Sample Input Select
The MUX6 field is used during the seventh sample of a sequence
executed with the Sample Sequencer and specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
25:24 MUX6 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:22 reserved RO 0
6th Sample Input Select
The MUX5 field is used during the sixth sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
21:20 MUX5 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:18 reserved RO 0
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Bit/Field Name Type Reset Description
5th Sample Input Select
The MUX4 field is used during the fifth sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
17:16 MUX4 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:14 reserved RO 0
4th Sample Input Select
The MUX3 field is used during the fourth sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
13:12 MUX3 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0
3rd Sample Input Select
The MUX2 field is used during the third sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
9:8 MUX2 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0
2nd Sample Input Select
The MUX1 field is used during the second sample of a sequence
executed with the Sample Sequencer and specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
5:4 MUX1 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
1st Sample Input Select
The MUX0 field is used during the first sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
1:0 MUX0 R/W 0
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Analog-to-Digital Converter (ADC)
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 0. When configuring a sample sequence, the END bit must be set at some point,
whether it be after the first sample, last sample, or any sample in between.
This register is 32-bits wide and contains information for eight possible samples.
ADC Sample Sequence Control 0 (ADCSSCTL0)
Base 0x4003.8000
Offset 0x044
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
8th Sample Temp Sensor Select
The TS7 bit is used during the eighth sample of the sample sequence
and specifies the input source of the sample. If set, the temperature
sensor is read. Otherwise, the input pin specified by the ADCSSMUX
register is read.
31 TS7 R/W 0
8th Sample Interrupt Enable
The IE7 bit is used during the eighth sample of the sample sequence
and specifies whether the raw interrupt signal (INR0 bit) is asserted at
the end of the sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to a controller-level interrupt.
When this bit is set, the raw interrupt is asserted, otherwise it is not. It
is legal to have multiple samples within a sequence generate interrupts.
30 IE7 R/W 0
8th Sample is End of Sequence
The END7 bit indicates that this is the last sample of the sequence. It is
possible to end the sequence on any sample position. Samples defined
after the sample containing a set END are not requested for conversion
even though the fields may be non-zero. It is required that software write
the END bit somewhere within the sequence. (Sample Sequencer 3,
which only has a single sample in the sequence, is hardwired to have
the END0 bit set.)
Setting this bit indicates that this sample is the last in the sequence.
29 END7 R/W 0
8th Sample Diff Input Select
The D7 bit indicates that the analog input is to be differentially sampled.
The corresponding ADCSSMUXx nibble must be set to the pair number
"i", where the paired inputs are "2i and 2i+1". The temperature sensor
does not have a differential option. When set, the analog inputs are
differentially sampled.
28 D7 R/W 0
7th Sample Temp Sensor Select
Same definition as TS7 but used during the seventh sample.
27 TS6 R/W 0
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Bit/Field Name Type Reset Description
7th Sample Interrupt Enable
Same definition as IE7 but used during the seventh sample.
26 IE6 R/W 0
7th Sample is End of Sequence
Same definition as END7 but used during the seventh sample.
25 END6 R/W 0
7th Sample Diff Input Select
Same definition as D7 but used during the seventh sample.
24 D6 R/W 0
6th Sample Temp Sensor Select
Same definition as TS7 but used during the sixth sample.
23 TS5 R/W 0
6th Sample Interrupt Enable
Same definition as IE7 but used during the sixth sample.
22 IE5 R/W 0
6th Sample is End of Sequence
Same definition as END7 but used during the sixth sample.
21 END5 R/W 0
6th Sample Diff Input Select
Same definition as D7 but used during the sixth sample.
20 D5 R/W 0
5th Sample Temp Sensor Select
Same definition as TS7 but used during the fifth sample.
19 TS4 R/W 0
5th Sample Interrupt Enable
Same definition as IE7 but used during the fifth sample.
18 IE4 R/W 0
5th Sample is End of Sequence
Same definition as END7 but used during the fifth sample.
17 END4 R/W 0
5th Sample Diff Input Select
Same definition as D7 but used during the fifth sample.
16 D4 R/W 0
4th Sample Temp Sensor Select
Same definition as TS7 but used during the fourth sample.
15 TS3 R/W 0
4th Sample Interrupt Enable
Same definition as IE7 but used during the fourth sample.
14 IE3 R/W 0
4th Sample is End of Sequence
Same definition as END7 but used during the fourth sample.
13 END3 R/W 0
4th Sample Diff Input Select
Same definition as D7 but used during the fourth sample.
12 D3 R/W 0
3rd Sample Temp Sensor Select
Same definition as TS7 but used during the third sample.
11 TS2 R/W 0
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Bit/Field Name Type Reset Description
3rd Sample Interrupt Enable
Same definition as IE7 but used during the third sample.
10 IE2 R/W 0
3rd Sample is End of Sequence
Same definition as END7 but used during the third sample.
9 END2 R/W 0
3rd Sample Diff Input Select
Same definition as D7 but used during the third sample.
8 D2 R/W 0
2nd Sample Temp Sensor Select
Same definition as TS7 but used during the second sample.
7 TS1 R/W 0
2nd Sample Interrupt Enable
Same definition as IE7 but used during the second sample.
6 IE1 R/W 0
2nd Sample is End of Sequence
Same definition as END7 but used during the second sample.
5 END1 R/W 0
2nd Sample Diff Input Select
Same definition as D7 but used during the second sample.
4 D1 R/W 0
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
3 TS0 R/W 0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
2 IE0 R/W 0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
1 END0 R/W 0
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0 D0 R/W 0
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Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset
0x0A8
This register contains the conversion results for samples collected with the Sample Sequencer (the
ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1,
ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return
conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the
FIFO is not properly handled by software, overflow and underflow conditions are registered in the
ADCOSTAT and ADCUSTAT registers.
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0)
Base 0x4003.8000
Offset 0x048
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0x00
9:0 DATA RO 0x00 Conversion Result Data
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Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset
0x04C
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset
0x06C
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset
0x08C
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset
0x0AC
This register provides a window into the Sample Sequencer, providing full/empty status information
as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty
FIFO. The ADCSSFSTAT0 register provides status on FIF0, ADCSSFSTAT1 on FIFO1,
ADCSSFSTAT2 on FIFO2, and ADCSSFSTAT3 on FIFO3.
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0)
Base 0x4003.8000
Offset 0x04C
Type RO, reset 0x0000.0100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved FULL reserved EMPTY HPTR TPTR
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:13 reserved RO 0x00
FIFO Full
When set, indicates that the FIFO is currently full.
12 FULL RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:9 reserved RO 0x00
FIFO Empty
When set, indicates that the FIFO is currently empty.
8 EMPTY RO 1
FIFO Head Pointer
This field contains the current "head" pointer index for the FIFO, that is,
the next entry to be written.
7:4 HPTR RO 0x00
FIFO Tail Pointer
This field contains the current "tail" pointer index for the FIFO, that is,
the next entry to be read.
3:0 TPTR RO 0x00
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Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1),
offset 0x060
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2),
offset 0x080
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 1 or 2. These registers are 16-bits wide and contain information for four possible
samples. See the ADCSSMUX0 register on page 283 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1)
Base 0x4003.8000
Offset 0x060
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x00
13:12 MUX3 R/W 0 4th Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0
9:8 MUX2 R/W 0 3rd Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0
5:4 MUX1 R/W 0 2nd Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
1:0 MUX0 R/W 0 1st Sample Input Select
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Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084
These registers contain the configuration information for each sample for a sequence executed with
Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set at some
point, whether it be after the first sample, last sample, or any sample in between. This register is
16-bits wide and contains information for four possible samples. See the ADCSSCTL0 register on
page 285 for detailed bit descriptions.
ADC Sample Sequence Control 1 (ADCSSCTL1)
Base 0x4003.8000
Offset 0x064
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
4th Sample Temp Sensor Select
Same definition as TS7 but used during the fourth sample.
15 TS3 R/W 0
4th Sample Interrupt Enable
Same definition as IE7 but used during the fourth sample.
14 IE3 R/W 0
4th Sample is End of Sequence
Same definition as END7 but used during the fourth sample.
13 END3 R/W 0
4th Sample Diff Input Select
Same definition as D7 but used during the fourth sample.
12 D3 R/W 0
3rd Sample Temp Sensor Select
Same definition as TS7 but used during the third sample.
11 TS2 R/W 0
3rd Sample Interrupt Enable
Same definition as IE7 but used during the third sample.
10 IE2 R/W 0
3rd Sample is End of Sequence
Same definition as END7 but used during the third sample.
9 END2 R/W 0
3rd Sample Diff Input Select
Same definition as D7 but used during the third sample.
8 D2 R/W 0
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Bit/Field Name Type Reset Description
2nd Sample Temp Sensor Select
Same definition as TS7 but used during the second sample.
7 TS1 R/W 0
2nd Sample Interrupt Enable
Same definition as IE7 but used during the second sample.
6 IE1 R/W 0
2nd Sample is End of Sequence
Same definition as END7 but used during the second sample.
5 END1 R/W 0
2nd Sample Diff Input Select
Same definition as D7 but used during the second sample.
4 D1 R/W 0
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
3 TS0 R/W 0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
2 IE0 R/W 0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
1 END0 R/W 0
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0 D0 R/W 0
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Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3),
offset 0x0A0
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 3. This register is 4-bits wide and contains information for one possible sample.
See the ADCSSMUX0 register on page 283 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3)
Base 0x4003.8000
Offset 0x0A0
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MUX0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
1:0 MUX0 R/W 0 1st Sample Input Select
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Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 3. The END bit is always set since there is only one sample in this sequencer.
This register is 4-bits wide and contains information for one possible sample. See the ADCSSCTL0
register on page 285 for detailed bit descriptions.
ADC Sample Sequence Control 3 (ADCSSCTL3)
Base 0x4003.8000
Offset 0x0A4
Type R/W, reset 0x0000.0002
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TS0 IE0 END0 D0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
3 TS0 R/W 0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
2 IE0 R/W 0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
1 END0 R/W 1
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0 D0 R/W 0
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Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100
This register provides loopback operation within the digital logic of the ADC, which can be useful in
debugging software without having to provide actual analog stimulus. This test mode is entered by
writing a value of 0x0000.0001 to this register. When data is read from the FIFO in loopback mode,
the read-only portion of this register is returned.
ADC Test Mode Loopback (ADCTMLB)
Base 0x4003.8000
Offset 0x100
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved LB
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Loopback Mode Enable
When set, forces a loopback within the digital block to provide information
on input and unique numbering. The ADCSSFIFOn registers do not
provide sample data, but instead provide the 10-bit loopback data as
shown below.
Bit/Field Name Description
Continuous Sample Counter
Continuous sample counter that is initialized to 0 and
counts each sample as it processed. This helps
provide a unique value for the data received.
9:6 CNT
Continuation Sample Indicator
When set, indicates that this is a continuation sample.
For example, if two sequencers were to run
back-to-back, this indicates that the controller kept
continuously sampling at full rate.
5 CONT
Differential Sample Indicator
When set, indicates that this is a differential sample.
4 DIFF
Temp Sensor Sample Indicator
When set, indicates that this is a temperature sensor
sample.
3 TS
Analog Input Indicator
Indicates which analog input is to be sampled.
2:0 MUX
0 LB R/W 0
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13 Universal Asynchronous Receivers/Transmitters
(UARTs)
The Stellaris® Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable,
16C550-type serial interface characteristics. The LM3S8933 controller is equipped with two UART
modules.
Each UART has the following features:
■ Separate transmit and receive FIFOs
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Programmable baud-rate generator allowing rates up to 3.125 Mbps
■ Standard asynchronous communication bits for start, stop, and parity
■ False start bit detection
■ Line-break generation and detection
■ Fully programmable serial interface characteristics:
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing:
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
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13.1 Block Diagram
Figure 13-1. UART Module Block Diagram
Receiver
Transmitter
System Clock
Control / Status
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
UARTILPR
Interrupt Control
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
Baud Rate
Generator
UARTIBRD
UARTFBRD
Identification
Registers
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UART PeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
UARTDR
TXFIFO
16x8
...
RXFIFO
16x8
...
Interrupt
UnTx
UnRx
13.2 Functional Description
Each Stellaris® UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 315). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected
to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
13.2.1 Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
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bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 13-2 on page 298 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 13-2. UART Character Frame
1
0 5-8 data bits
LSB MSB
Parity bit
if enabled
1-2
stop bits
UnTX
n
Start
13.2.2 Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 311) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 312). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.)
BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
where UARTSysClk is the system clock connected to the UART.
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register)
can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and
adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as
Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error
detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 313), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
■ UARTIBRD write, UARTFBRD write, and UARTLCRH write
■ UARTFBRD write, UARTIBRD write, and UARTLCRH write
■ UARTIBRD write and UARTLCRH write
■ UARTFBRD write and UARTLCRH write
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13.2.3 Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 308) is asserted as soon as
data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has
been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 (described in “Transmit/Receive Logic” on page 297).
The start bit is valid if UnRx is still low on the eighth cycle of Baud16, otherwise a false start bit is
detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR)
register (see page 306). If the start bit was valid, successive data bits are sampled on every 16th
cycle of Baud16 (that is, one bit period later) according to the programmed length of the data
characters. The parity bit is then checked if parity mode was enabled. Data length and parity are
defined in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When
a full word is received, the data is stored in the receive FIFO, with any error bits associated with
that word.
13.2.4 Serial IR (SIR)
The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream, and half-duplex
serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to
provide a digital encoded output, and decoded input to the UART. The UART signal pins can be
connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block
has two modes of operation:
■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the
selected baud rate bit period on the output pin, while logic one levels are transmitted as a static
LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light
for each zero. On the reception side, the incoming light pulses energize the photo transistor base
of the receiver, pulling its output LOW. This drives the UART input pin LOW.
■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the
period of the internally generated IrLPBaud16 signal (1.63 μs, assuming a nominal 1.8432 MHz
frequency) by changing the appropriate bit in the UARTCR register. See page 310 for more
information on IrDA low-power pulse-duration configuration.
Figure 13-3 on page 300 shows the UART transmit and receive signals, with and without IrDA
modulation.
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Figure 13-3. IrDA Data Modulation
0 1 0 1 0 0 1 1 0 1
Data bits
0 1 0 1 0 0 1 1 0 1
Start Data bits
bit
Start Stop
Bit period Bit period
3
16
UnTx
UnTx with IrDA
UnRx with IrDA
UnRx
Stop
bit
In both normal and low-power IrDA modes:
■ During transmission, the UART data bit is used as the base for encoding
■ During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay
between transmission and reception. This delay must be generated by software because it is not
automatically supported by the UART. The delay is required because the infrared receiver electronics
might become biased, or even saturated from the optical power coupled from the adjacent transmitter
LED. This delay is known as latency, or receiver setup time.
13.2.5 FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 304). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data
in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 313).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 308) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the
UARTRSR register shows overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 317). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For
example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt
after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the
½ mark.
13.2.6 Interrupts
The UART can generate interrupts when the following conditions are observed:
■ Overrun Error
■ Break Error
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■ Parity Error
■ Framing Error
■ Receive Timeout
■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)
■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 322).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM ) register (see page 319) by setting the corresponding IM bit to 1. If interrupts are
not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 321).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 323).
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data
is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO
becomes empty through reading all the data (or by reading the holding register), or when a 1 is
written to the corresponding bit in the UARTICR register.
13.2.7 Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 315). In loopback mode,
data transmitted on UnTx is received on the UnRx input.
13.2.8 IrDA SIR block
The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the
SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR
transceiver.
The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same
time. Transmission must be stopped before data can be received. The IrDA SIR physical layer
specifies a minimum 10-ms delay between transmission and reception.
13.3 Initialization and Configuration
To use the UARTs, the peripheral clock must be enabled by setting the UART0 or UART1 bits in the
RCGC1 register.
This section discusses the steps that are required to use a UART module. For this example, the
UART clock is assumed to be 20 MHz and the desired UART configuration is:
■ 115200 baud rate
■ Data length of 8 bits
■ One stop bit
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■ No parity
■ FIFOs disabled
■ No interrupts
The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the
UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the
equation described in “Baud-Rate Generation” on page 298, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 311) should be set to 10.
The value to be loaded into the UARTFBRD register (see page 312) is calculated by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Enable the UART by setting the UARTEN bit in the UARTCTL register.
13.4 Register Map
Table 13-1 on page 302 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■ UART0: 0x4000.C000
■ UART1: 0x4000.D000
Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 315)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 13-1. UART Register Map
See
Offset Name Type Reset Description page
0x000 UARTDR R/W 0x0000.0000 UART Data 304
0x004 UARTRSR/UARTECR R/W 0x0000.0000 UART Receive Status/Error Clear 306
0x018 UARTFR RO 0x0000.0090 UART Flag 308
0x020 UARTILPR R/W 0x0000.0000 UART IrDA Low-Power Register 310
0x024 UARTIBRD R/W 0x0000.0000 UART Integer Baud-Rate Divisor 311
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See
Offset Name Type Reset Description page
0x028 UARTFBRD R/W 0x0000.0000 UART Fractional Baud-Rate Divisor 312
0x02C UARTLCRH R/W 0x0000.0000 UART Line Control 313
0x030 UARTCTL R/W 0x0000.0300 UART Control 315
0x034 UARTIFLS R/W 0x0000.0012 UART Interrupt FIFO Level Select 317
0x038 UARTIM R/W 0x0000.0000 UART Interrupt Mask 319
0x03C UARTRIS RO 0x0000.000F UART Raw Interrupt Status 321
0x040 UARTMIS RO 0x0000.0000 UART Masked Interrupt Status 322
0x044 UARTICR W1C 0x0000.0000 UART Interrupt Clear 323
0xFD0 UARTPeriphID4 RO 0x0000.0000 UART Peripheral Identification 4 325
0xFD4 UARTPeriphID5 RO 0x0000.0000 UART Peripheral Identification 5 326
0xFD8 UARTPeriphID6 RO 0x0000.0000 UART Peripheral Identification 6 327
0xFDC UARTPeriphID7 RO 0x0000.0000 UART Peripheral Identification 7 328
0xFE0 UARTPeriphID0 RO 0x0000.0011 UART Peripheral Identification 0 329
0xFE4 UARTPeriphID1 RO 0x0000.0000 UART Peripheral Identification 1 330
0xFE8 UARTPeriphID2 RO 0x0000.0018 UART Peripheral Identification 2 331
0xFEC UARTPeriphID3 RO 0x0000.0001 UART Peripheral Identification 3 332
0xFF0 UARTPCellID0 RO 0x0000.000D UART PrimeCell Identification 0 333
0xFF4 UARTPCellID1 RO 0x0000.00F0 UART PrimeCell Identification 1 334
0xFF8 UARTPCellID2 RO 0x0000.0005 UART PrimeCell Identification 2 335
0xFFC UARTPCellID3 RO 0x0000.00B1 UART PrimeCell Identification 3 336
13.5 Register Descriptions
The remainder of this section lists and describes the UART registers, in numerical order by address
offset.
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Register 1: UART Data (UARTDR), offset 0x000
This register is the data register (the interface to the FIFOs).
When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs
are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.
UART Data (UARTDR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OE BE PE FE DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0
UART Overrun Error
The OE values are defined as follows:
Value Description
0 There has been no data loss due to a FIFO overrun.
New data was received when the FIFO was full, resulting in
data loss.
1
11 OE RO 0
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the receive data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state) and the next valid start bit is received.
10 BE RO 0
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Bit/Field Name Type Reset Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
9 PE RO 0
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
8 FE RO 0
Data Transmitted or Received
When written, the data that is to be transmitted via the UART. When
read, the data that was received by the UART.
7:0 DATA R/W 0
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Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset
0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared to 0 on reset.
Read-Only Receive Status (UARTRSR) Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OE BE PE FE
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0
UART Overrun Error
When this bit is set to 1, data is received and the FIFO is already full.
This bit is cleared to 0 by a write to UARTECR.
The FIFO contents remain valid since no further data is written when
the FIFO is full, only the contents of the shift register are overwritten.
The CPU must now read the data in order to empty the FIFO.
3 OE RO 0
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the received data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
2 BE RO 0
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Bit/Field Name Type Reset Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
1 PE RO 0
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
0 FE RO 0
Write-Only Error Clear (UARTECR) Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x004
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved WO 0
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
7:0 DATA WO 0
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Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.
UART Flag (UARTFR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x018
Type RO, reset 0x0000.0090
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXFE RXFF TXFF RXFE BUSY reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding
register is empty.
If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO
is empty.
7 TXFE RO 1
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is full.
If the FIFO is enabled, this bit is set when the receive FIFO is full.
6 RXFF RO 0
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding register
is full.
If the FIFO is enabled, this bit is set when the transmit FIFO is full.
5 TXFF RO 0
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Bit/Field Name Type Reset Description
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is empty.
If the FIFO is enabled, this bit is set when the receive FIFO is empty.
4 RXFE RO 1
UART Busy
When this bit is 1, the UART is busy transmitting data. This bit remains
set until the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
3 BUSY RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor
value used to derive the low-power SIR pulse width clock by dividing down the system clock (SysClk).
All the bits are cleared to 0 when reset.
The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power
divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode
is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is
calculated as follows:
ILPDVSR = SysClk / FIrLPBaud16
where FIrLPBaud16 is nominally 1.8432 MHz.
You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power
pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency
of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that
pulses greater than 1.4 μs are accepted as valid pulses.
Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
UART IrDA Low-Power Register (UARTILPR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ILPDVSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
IrDA Low-Power Divisor
This is an 8-bit low-power divisor value.
7:0 ILPDVSR R/W 0x00
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Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 298
for configuration details.
UART Integer Baud-Rate Divisor (UARTIBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x024
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVINT
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0
15:0 DIVINT R/W 0x0000 Integer Baud-Rate Divisor
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Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 298
for configuration details.
UART Fractional Baud-Rate Divisor (UARTFBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x028
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DIVFRAC
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
5:0 DIVFRAC R/W 0x000 Fractional Baud-Rate Divisor
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Register 7: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
UART Line Control (UARTLCRH)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x02C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SPS WLEN FEN STP2 EPS PEN BRK
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
7 SPS R/W 0
UART Word Length
The bits indicate the number of data bits transmitted or received in a
frame as follows:
Value Description
0x3 8 bits
0x2 7 bits
0x1 6 bits
0x0 5 bits (default)
6:5 WLEN R/W 0
UART Enable FIFOs
If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO
mode).
When cleared to 0, FIFOs are disabled (Character mode). The FIFOs
become 1-byte-deep holding registers.
4 FEN R/W 0
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Bit/Field Name Type Reset Description
UART Two Stop Bits Select
If this bit is set to 1, two stop bits are transmitted at the end of a frame.
The receive logic does not check for two stop bits being received.
3 STP2 R/W 0
UART Even Parity Select
If this bit is set to 1, even parity generation and checking is performed
during transmission and reception, which checks for an even number
of 1s in data and parity bits.
When cleared to 0, then odd parity is performed, which checks for an
odd number of 1s.
This bit has no effect when parity is disabled by the PEN bit.
2 EPS R/W 0
UART Parity Enable
If this bit is set to 1, parity checking and generation is enabled; otherwise,
parity is disabled and no parity bit is added to the data frame.
1 PEN R/W 0
UART Send Break
If this bit is set to 1, a Low level is continually output on the UnTX output,
after completing transmission of the current character. For the proper
execution of the break command, the software must set this bit for at
least two frames (character periods). For normal use, this bit must be
cleared to 0.
0 BRK R/W 0
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Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are written.
If the UART is disabled during a transmit or receive operation, the current transaction is completed
prior to the UART stopping.
Note: The UARTCTL register should not be changed while the UART is enabled or else the results
are unpredictable. The following sequence is recommended for making changes to the
UARTCTL register.
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by disabling bit 4 (FEN) in the line control register (UARTLCRH).
4. Reprogram the control register.
5. Enable the UART.
UART Control (UARTCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x030
Type R/W, reset 0x0000.0300
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RXE TXE LBE reserved SIRLP SIREN UARTEN
Type RO RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0
UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled. When
the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note: To enable reception, the UARTEN bit must also be set.
9 RXE R/W 1
UART Transmit Enable
If this bit is set to 1, the transmit section of the UART is enabled. When
the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note: To enable transmission, the UARTEN bit must also be set.
8 TXE R/W 1
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Bit/Field Name Type Reset Description
UART Loop Back Enable
If this bit is set to 1, the UnTX path is fed through the UnRX path.
7 LBE R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:3 reserved RO 0
UART SIR Low Power Mode
This bit selects the IrDA encoding mode. If this bit is cleared to 0,
low-level bits are transmitted as an active High pulse with a width of
3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted
with a pulse width which is 3 times the period of the IrLPBaud16 input
signal, regardless of the selected bit rate. Setting this bit uses less power,
but might reduce transmission distances. See page 310 for more
information.
2 SIRLP R/W 0
UART SIR Enable
If this bit is set to 1, the IrDA SIR block is enabled, and the UART will
transmit and receive data using SIR protocol.
1 SIREN R/W 0
UART Enable
If this bit is set to 1, the UART is enabled. When the UART is disabled
in the middle of transmission or reception, it completes the current
character before stopping.
0 UARTEN R/W 0
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Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.
UART Interrupt FIFO Level Select (UARTIFLS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x034
Type R/W, reset 0x0000.0012
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RXIFLSEL TXIFLSEL
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
Value Description
0x0 RX FIFO ≥ 1/8 full
0x1 RX FIFO ≥ ¼ full
0x2 RX FIFO ≥ ½ full (default)
0x3 RX FIFO ≥ ¾ full
0x4 RX FIFO ≥ 7/8 full
0x5-0x7 Reserved
5:3 RXIFLSEL R/W 0x2
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Bit/Field Name Type Reset Description
UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
Value Description
0x0 TX FIFO ≤ 1/8 full
0x1 TX FIFO ≤ ¼ full
0x2 TX FIFO ≤ ½ full (default)
0x3 TX FIFO ≤ ¾ full
0x4 TX FIFO ≤ 7/8 full
0x5-0x7 Reserved
2:0 TXIFLSEL R/W 0x2
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to
a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a
0 prevents the raw interrupt signal from being sent to the interrupt controller.
UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OEIM BEIM PEIM FEIM RTIM TXIM RXIM reserved
Type RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
UART Overrun Error Interrupt Mask
On a read, the current mask for the OEIM interrupt is returned.
Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller.
10 OEIM R/W 0
UART Break Error Interrupt Mask
On a read, the current mask for the BEIM interrupt is returned.
Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller.
9 BEIM R/W 0
UART Parity Error Interrupt Mask
On a read, the current mask for the PEIM interrupt is returned.
Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller.
8 PEIM R/W 0
UART Framing Error Interrupt Mask
On a read, the current mask for the FEIM interrupt is returned.
Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller.
7 FEIM R/W 0
UART Receive Time-Out Interrupt Mask
On a read, the current mask for the RTIM interrupt is returned.
Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller.
6 RTIM R/W 0
UART Transmit Interrupt Mask
On a read, the current mask for the TXIM interrupt is returned.
Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller.
5 TXIM R/W 0
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Bit/Field Name Type Reset Description
UART Receive Interrupt Mask
On a read, the current mask for the RXIM interrupt is returned.
Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller.
4 RXIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0x00
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x03C
Type RO, reset 0x0000.000F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
UART Overrun Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
10 OERIS RO 0
UART Break Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
9 BERIS RO 0
UART Parity Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
8 PERIS RO 0
UART Framing Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
7 FERIS RO 0
UART Receive Time-Out Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
6 RTRIS RO 0
UART Transmit Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
5 TXRIS RO 0
UART Receive Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
4 RXRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0xF
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Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x040
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
UART Overrun Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
10 OEMIS RO 0
UART Break Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
9 BEMIS RO 0
UART Parity Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
8 PEMIS RO 0
UART Framing Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
7 FEMIS RO 0
UART Receive Time-Out Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
6 RTMIS RO 0
UART Transmit Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
5 TXMIS RO 0
UART Receive Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
4 RXMIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x044
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OEIC BEIC PEIC FEIC RTIC TXIC RXIC reserved
Type RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
Overrun Error Interrupt Clear
The OEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
10 OEIC W1C 0
Break Error Interrupt Clear
The BEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
9 BEIC W1C 0
Parity Error Interrupt Clear
The PEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
8 PEIC W1C 0
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Bit/Field Name Type Reset Description
Framing Error Interrupt Clear
The FEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
7 FEIC W1C 0
Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
6 RTIC W1C 0
Transmit Interrupt Clear
The TXIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
5 TXIC W1C 0
Receive Interrupt Clear
The RXIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
4 RXIC W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0x00
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 4 (UARTPeriphID4)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID4 RO 0x0000
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Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 5 (UARTPeriphID5)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID5 RO 0x0000
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 6 (UARTPeriphID6)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID6 RO 0x0000
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Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 7 (UARTPeriphID7)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID7 RO 0x0000
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 0 (UARTPeriphID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFE0
Type RO, reset 0x0000.0011
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID0 RO 0x11
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Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 1 (UARTPeriphID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID1 RO 0x00
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 2 (UARTPeriphID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID2 RO 0x18
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Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 3 (UARTPeriphID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID3 RO 0x01
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 0 (UARTPCellID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
7:0 CID0 RO 0x0D
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Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 1 (UARTPCellID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
7:0 CID1 RO 0xF0
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 2 (UARTPCellID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
7:0 CID2 RO 0x05
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Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 3 (UARTPCellID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
7:0 CID3 RO 0xB1
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Universal Asynchronous Receivers/Transmitters (UARTs)
14 Synchronous Serial Interface (SSI)
The Stellaris® Synchronous Serial Interface (SSI) is a master or slave interface for synchronous
serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas
Instruments synchronous serial interfaces.
The Stellaris® SSI module has the following features:
■ Master or slave operation
■ Programmable clock bit rate and prescale
■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
14.1 Block Diagram
Figure 14-1. SSI Module Block Diagram
Transmit/
Receive
Logic
Clock
Prescaler
SSICPSR
Control / Status
SSICR0
SSICR1
SSISR
Interrupt Control
SSIIM
SSIMIS
SSIRIS
SSIICR
SSIDR
TxFIFO
8 x 16
...
RxFIFO
8 x 16
...
System Clock
SSITx
SSIRx
SSIClk
SSIFss
Interrupt
Identification Registers
SSIPCellID0 SSIPeriphID0 SSIPeriphID4
SSIPCellID1 SSIPeriphID1 SSIPeriphID5
SSIPCellID2 SSIPeriphID2 SSIPeriphID6
SSIPCellID3 SSIPeriphID3 SSIPeriphID7
14.2 Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
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internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes.
14.2.1 Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 356). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 349).
The frequency of the output clock SSIClk is defined by:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
Note: Although the SSIClk transmit clock can theoretically be 25 MHz, the module may not be
able to operate at that speed. For master mode, the system clock must be at least two times
faster than the SSIClk. For slave mode, the system clock must be at least 12 times faster
than the SSIClk.
See “Synchronous Serial Interface (SSI)” on page 544 to view SSI timing parameters.
14.2.2 FIFO Operation
14.2.2.1 Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 353), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
14.2.2.2 Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
14.2.3 Interrupts
The SSI can generate interrupts when the following conditions are observed:
■ Transmit FIFO service
■ Receive FIFO service
■ Receive FIFO time-out
■ Receive FIFO overrun
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All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
can only generate a single interrupt request to the controller at any given time. You can mask each
of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask
(SSIIM) register (see page 357). Setting the appropriate mask bit to 1 enables the interrupt.
Provision of the individual outputs, as well as a combined interrupt output, allows use of either a
global interrupt service routine, or modular device drivers to handle interrupts. The transmit and
receive dynamic dataflow interrupts have been separated from the status interrupts so that data
can be read or written in response to the FIFO trigger levels. The status of the individual interrupt
sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status
(SSIMIS) registers (see page 359 and page 360, respectively).
14.2.4 Frame Formats
Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. There are three basic frame types that can be selected:
■ Texas Instruments synchronous serial
■ Freescale SPI
■ MICROWIRE
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and
latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique, which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
14.2.4.1 Texas Instruments Synchronous Serial Frame Format
Figure 14-2 on page 340 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
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Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer)
SSIClk
4 to 16 bits
SSIFss
SSITx/SSIRx MSB LSB
In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is
pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data
is shifted onto the SSIRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSIClk after the LSB has been latched.
Figure 14-3 on page 340 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer)
MSB LSB
4 to 16 bits
SSIClk
SSIFss
SSITx/SSIRx
14.2.4.2 Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk
pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not
being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition
before the first data capture edge. When the SPH phase control bit is Low, data is captured on the
first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition.
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14.2.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 14-4 on page 341 and Figure 14-5 on page 341.
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
4 to 16 bits
SSIClk
SSIFss
SSIRx Q
SSITx
MSB
MSB
LSB
LSB
Note: Q is undefined.
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx LSB
SSITx MSB LSB
4 to 16 bits
LSB MSB
MSB
MSB
LSB
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto
the SSIRx input line of the master. The master SSITx output pad is enabled.
One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the
master and slave data have been set, the SSIClk master clock pin goes High after one further half
SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
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serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
14.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
14-6 on page 342, which covers both single and continuous transfers.
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1
4 to 16 bits
SSIClk
SSIFss
SSIRx
SSITx
Q
MSB
Q MSB
LSB
LSB
Note: Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After
a further one half SSIClk period, both master and slave valid data is enabled onto their respective
transmission lines. At the same time, the SSIClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned
to its idle High state one SSIClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
14.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 14-7 on page 343 and Figure 14-8 on page 343.
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Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
4 to 16 bits
SSIClk
SSIFss
SSIRx
SSITx
MSB Q
MSB LSB
LSB
Note: Q is undefined.
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSITx/SSIRx MSB LSB
4 to 16 bits
LSB MSB
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low, which causes slave data to be immediately
transferred onto the SSIRx line of the master. The master SSITx output pad is enabled.
One half period later, valid master data is transferred to the SSITx line. Now that both the master
and slave data have been set, the SSIClk master clock pin becomes Low after one further half
SSIClk period. This means that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss
line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
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14.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
14-9 on page 344, which covers both single and continuous transfers.
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1
4 to 16 bits
SSIClk
SSIFss
SSIRx
SSITx
Q Q
MSB
MSB
LSB
LSB
Note: Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled.
After a further one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until
the final bit of the last word has been captured, and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
14.2.4.7 MICROWIRE Frame Format
Figure 14-10 on page 345 shows the MICROWIRE frame format, again for a single frame. Figure
14-11 on page 346 shows the same format when back-to-back frames are transmitted.
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Figure 14-10. MICROWIRE Frame Format (Single Frame)
SSIClk
SSIFss
SSIRx MSB LSB
4 to 16 bits
output data
0
SSITx MSB LSB
8-bit control
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
full-duplex, using a master-slave message passing technique. Each serial transmission begins with
an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss
causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the
SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains
tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of
each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a
one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven
onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising
edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one
clock period after the last bit has been latched in the receive serial shifter, which causes the data
to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk
after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer.
However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs
back-to-back. The control byte of the next frame follows directly after the LSB of the received data
from the current frame. Each of the received values is transferred from the receive shifter on the
falling edge of SSIClk, after the LSB of the frame has been latched into the SSI.
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Figure 14-11. MICROWIRE Frame Format (Continuous Transfer)
8-bit control
SSIClk
SSIFss
SSIRx MSB LSB
4 to 16 bits
output data
0
SSITx LSB MSB LSB
MSB
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
Figure 14-12 on page 346 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
SSIClk
SSIFss
SSIRx
First RX data to be
sampled by SSI slave
tSetup=(2*tSSIClk)
tHold=tSSIClk
14.3 Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the clock prescale divisor by writing the SSICPSR register.
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4. Write the SSICR0 register with the following configuration:
■ Serial clock rate (SCR)
■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
■ The data size (DSS)
5. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
■ Master operation
■ Freescale SPI mode (SPO=1, SPH=1)
■ 1 Mbps bit rate
■ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is disabled.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
14.4 Register Map
Table 14-1 on page 347 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■ SSI0: 0x4000.8000
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 14-1. SSI Register Map
See
Offset Name Type Reset Description page
0x000 SSICR0 R/W 0x0000.0000 SSI Control 0 349
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See
Offset Name Type Reset Description page
0x004 SSICR1 R/W 0x0000.0000 SSI Control 1 351
0x008 SSIDR R/W 0x0000.0000 SSI Data 353
0x00C SSISR RO 0x0000.0003 SSI Status 354
0x010 SSICPSR R/W 0x0000.0000 SSI Clock Prescale 356
0x014 SSIIM R/W 0x0000.0000 SSI Interrupt Mask 357
0x018 SSIRIS RO 0x0000.0008 SSI Raw Interrupt Status 359
0x01C SSIMIS RO 0x0000.0000 SSI Masked Interrupt Status 360
0x020 SSIICR W1C 0x0000.0000 SSI Interrupt Clear 361
0xFD0 SSIPeriphID4 RO 0x0000.0000 SSI Peripheral Identification 4 362
0xFD4 SSIPeriphID5 RO 0x0000.0000 SSI Peripheral Identification 5 363
0xFD8 SSIPeriphID6 RO 0x0000.0000 SSI Peripheral Identification 6 364
0xFDC SSIPeriphID7 RO 0x0000.0000 SSI Peripheral Identification 7 365
0xFE0 SSIPeriphID0 RO 0x0000.0022 SSI Peripheral Identification 0 366
0xFE4 SSIPeriphID1 RO 0x0000.0000 SSI Peripheral Identification 1 367
0xFE8 SSIPeriphID2 RO 0x0000.0018 SSI Peripheral Identification 2 368
0xFEC SSIPeriphID3 RO 0x0000.0001 SSI Peripheral Identification 3 369
0xFF0 SSIPCellID0 RO 0x0000.000D SSI PrimeCell Identification 0 370
0xFF4 SSIPCellID1 RO 0x0000.00F0 SSI PrimeCell Identification 1 371
0xFF8 SSIPCellID2 RO 0x0000.0005 SSI PrimeCell Identification 2 372
0xFFC SSIPCellID3 RO 0x0000.00B1 SSI PrimeCell Identification 3 373
14.5 Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
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Register 1: SSI Control 0 (SSICR0), offset 0x000
SSICR0 is control register 0 and contains bit fields that control various functions within the SSI
module. Functionality such as protocol mode, clock rate, and data size are configured in this register.
SSI Control 0 (SSICR0)
SSI0 base: 0x4000.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCR SPH SPO FRF DSS
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
SSI Serial Clock Rate
The value SCR is used to generate the transmit and receive bit rate of
the SSI. The bit rate is:
BR=FSSIClk/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
15:8 SCR R/W 0x0000
SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. It has the most impact on the first bit transmitted by
either allowing or not allowing a clock transition before the first data
capture edge.
When the SPH bit is 0, data is captured on the first clock edge transition.
If SPH is 1, data is captured on the second clock edge transition.
7 SPH R/W 0
SSI Serial Clock Polarity
This bit is only applicable to the Freescale SPI Format.
When the SPO bit is 0, it produces a steady state Low value on the
SSIClk pin. If SPO is 1, a steady state High value is placed on the
SSIClk pin when data is not being transferred.
6 SPO R/W 0
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Bit/Field Name Type Reset Description
SSI Frame Format Select
The FRF values are defined as follows:
Value Frame Format
0x0 Freescale SPI Frame Format
0x1 Texas Intruments Synchronous Serial Frame Format
0x2 MICROWIRE Frame Format
0x3 Reserved
5:4 FRF R/W 0x0
SSI Data Size Select
The DSS values are defined as follows:
Value Data Size
0x0-0x2 Reserved
0x3 4-bit data
0x4 5-bit data
0x5 6-bit data
0x6 7-bit data
0x7 8-bit data
0x8 9-bit data
0x9 10-bit data
0xA 11-bit data
0xB 12-bit data
0xC 13-bit data
0xD 14-bit data
0xE 15-bit data
0xF 16-bit data
3:0 DSS R/W 0x00
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Register 2: SSI Control 1 (SSICR1), offset 0x004
SSICR1 is control register 1 and contains bit fields that control various functions within the SSI
module. Master and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SOD MS SSE LBM
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In multiple-slave
systems, it is possible for the SSI master to broadcast a message to all
slaves in the system while ensuring that only one slave drives data onto
the serial output line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD bit can be
configured so that the SSI slave does not drive the SSITx pin.
The SOD values are defined as follows:
Value Description
0 SSI can drive SSITx output in Slave Output mode.
1 SSI must not drive the SSITx output in Slave mode.
3 SOD R/W 0
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
SSI is disabled (SSE=0).
The MS values are defined as follows:
Value Description
0 Device configured as a master.
1 Device configured as a slave.
2 MS R/W 0
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Bit/Field Name Type Reset Description
SSI Synchronous Serial Port Enable
Setting this bit enables SSI operation.
The SSE values are defined as follows:
Value Description
0 SSI operation disabled.
1 SSI operation enabled.
Note: This bit must be set to 0 before any control registers
are reprogrammed.
1 SSE R/W 0
SSI Loopback Mode
Setting this bit enables Loopback Test mode.
The LBM values are defined as follows:
Value Description
0 Normal serial port operation enabled.
Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.
1
0 LBM R/W 0
352 March 17, 2008
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Register 3: SSI Data (SSIDR), offset 0x008
SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO
(pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI
receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed
to by the current FIFO write pointer).
When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written
to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is
loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed
bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
SSI0 base: 0x4000.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.
15:0 DATA R/W 0x0000
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Register 4: SSI Status (SSISR), offset 0x00C
SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
Offset 0x00C
Type RO, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BSY RFF RNE TNF TFE
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 reserved RO 0x00
SSI Busy Bit
The BSY values are defined as follows:
Value Description
0 SSI is idle.
SSI is currently transmitting and/or receiving a frame, or the
transmit FIFO is not empty.
1
4 BSY RO 0
SSI Receive FIFO Full
The RFF values are defined as follows:
Value Description
0 Receive FIFO is not full.
1 Receive FIFO is full.
3 RFF RO 0
SSI Receive FIFO Not Empty
The RNE values are defined as follows:
Value Description
0 Receive FIFO is empty.
1 Receive FIFO is not empty.
2 RNE RO 0
SSI Transmit FIFO Not Full
The TNF values are defined as follows:
Value Description
0 Transmit FIFO is full.
1 Transmit FIFO is not full.
1 TNF RO 1
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Bit/Field Name Type Reset Description
SSI Transmit FIFO Empty
The TFE values are defined as follows:
Value Description
0 Transmit FIFO is not empty.
1 Transmit FIFO is empty.
0 TFE R0 1
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LM3S8933 Microcontroller
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
SSICPSR is the clock prescale register and specifies the division factor by which the system clock
must be internally divided before further use.
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CPSDVSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254, depending on the
frequency of SSIClk. The LSB always returns 0 on reads.
7:0 CPSDVSR R/W 0x00
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Synchronous Serial Interface (SSI)
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding
mask.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXIM RXIM RTIM RORIM
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SSI Transmit FIFO Interrupt Mask
The TXIM values are defined as follows:
Value Description
0 TX FIFO half-full or less condition interrupt is masked.
1 TX FIFO half-full or less condition interrupt is not masked.
3 TXIM R/W 0
SSI Receive FIFO Interrupt Mask
The RXIM values are defined as follows:
Value Description
0 RX FIFO half-full or more condition interrupt is masked.
1 RX FIFO half-full or more condition interrupt is not masked.
2 RXIM R/W 0
SSI Receive Time-Out Interrupt Mask
The RTIM values are defined as follows:
Value Description
0 RX FIFO time-out interrupt is masked.
1 RX FIFO time-out interrupt is not masked.
1 RTIM R/W 0
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Bit/Field Name Type Reset Description
SSI Receive Overrun Interrupt Mask
The RORIM values are defined as follows:
Value Description
0 RX FIFO overrun interrupt is masked.
1 RX FIFO overrun interrupt is not masked.
0 RORIM R/W 0
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Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
Offset 0x018
Type RO, reset 0x0000.0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXRIS RXRIS RTRIS RORRIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SSI Transmit FIFO Raw Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
3 TXRIS RO 1
SSI Receive FIFO Raw Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
2 RXRIS RO 0
SSI Receive Time-Out Raw Interrupt Status
Indicates that the receive time-out has occurred, when set.
1 RTRIS RO 0
SSI Receive Overrun Raw Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
0 RORRIS RO 0
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Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXMIS RXMIS RTMIS RORMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0
SSI Transmit FIFO Masked Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
3 TXMIS RO 0
SSI Receive FIFO Masked Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
2 RXMIS RO 0
SSI Receive Time-Out Masked Interrupt Status
Indicates that the receive time-out has occurred, when set.
1 RTMIS RO 0
SSI Receive Overrun Masked Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
0 RORMIS RO 0
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Synchronous Serial Interface (SSI)
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
Offset 0x020
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RTIC RORIC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
SSI Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
0 No effect on interrupt.
1 Clears interrupt.
1 RTIC W1C 0
SSI Receive Overrun Interrupt Clear
The RORIC values are defined as follows:
Value Description
0 No effect on interrupt.
1 Clears interrupt.
0 RORIC W1C 0
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Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 4 (SSIPeriphID4)
SSI0 base: 0x4000.8000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID4 RO 0x00
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Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 5 (SSIPeriphID5)
SSI0 base: 0x4000.8000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID5 RO 0x00
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Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 6 (SSIPeriphID6)
SSI0 base: 0x4000.8000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID6 RO 0x00
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Synchronous Serial Interface (SSI)
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 7 (SSIPeriphID7)
SSI0 base: 0x4000.8000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID7 RO 0x00
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Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 0 (SSIPeriphID0)
SSI0 base: 0x4000.8000
Offset 0xFE0
Type RO, reset 0x0000.0022
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID0 RO 0x22
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Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 1 (SSIPeriphID1)
SSI0 base: 0x4000.8000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID1 RO 0x00
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Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 2 (SSIPeriphID2)
SSI0 base: 0x4000.8000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID2 RO 0x18
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Synchronous Serial Interface (SSI)
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 3 (SSIPeriphID3)
SSI0 base: 0x4000.8000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID3 RO 0x01
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Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 0 (SSIPCellID0)
SSI0 base: 0x4000.8000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
7:0 CID0 RO 0x0D
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Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 1 (SSIPCellID1)
SSI0 base: 0x4000.8000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
7:0 CID1 RO 0xF0
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Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 2 (SSIPCellID2)
SSI0 base: 0x4000.8000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
7:0 CID2 RO 0x05
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Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 3 (SSIPCellID3)
SSI0 base: 0x4000.8000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
7:0 CID3 RO 0xB1
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15 Inter-Integrated Circuit (I2C) Interface
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C
bus may also be used for system testing and diagnostic purposes in product development and
manufacture. The LM3S8933 microcontroller includes one I2C module, providing the ability to interact
(both send and receive) with other I2C devices on the bus.
Devices on the I2C bus can be designated as either a master or a slave. The Stellaris® I2C module
supports both sending and receiving data as either a master or a slave, and also supports the
simultaneous operation as both a master and a slave. There are a total of four I2C modes: Master
Transmit, Master Receive, Slave Transmit, and Slave Receive. The Stellaris® I2C module can
operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
Both the I2C master and slave can generate interrupts; the I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error) and the I2C slave generates
interrupts when data has been sent or requested by a master.
15.1 Block Diagram
Figure 15-1. I2C Block Diagram
I2C I/O Select
I2C Master Core
Interrupt
I2C Slave Core
I2CSCL
I2CSDA
I2CSDA
I2CSCL
I2CSDA
I2CSCL
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIM
I2CSRIS
I2CSMIS
I2CMMIS I2CSICR
I2C Control
15.2 Functional Description
The I2C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I2C bus configuration is shown in Figure 15-2 on page 375.
See “I2C” on page 540 for I2C timing diagrams.
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Figure 15-2. I2C Bus Configuration
RPUP
StellarisTM
I2CSCL I2CSDA
RPUP
3rd Party Device
with I2C Interface
SCL SDA
I2C Bus
SCL
SDA
3rd Party Device
with I2C Interface
SCL SDA
15.2.1 I2C Bus Functional Overview
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris®
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are high.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 375) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
15.2.1.1 START and STOP Conditions
The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP.
A high-to-low transition on the SDA line while the SCL is high is defined as a START condition, and
a low-to-high transition on the SDA line while SCL is high is defined as a STOP condition. The bus
is considered busy after a START condition and free after a STOP condition. See Figure
15-3 on page 375.
Figure 15-3. START and STOP Conditions
START
condition
SDA
SCL
STOP
condition
SDA
SCL
15.2.1.2 Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 15-4 on page 376. After the START condition, a
slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction
bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates
a request for data (receive). A data transfer is always terminated by a STOP condition generated
by the master, however, a master can initiate communications with another device on the bus by
generating a repeated START condition and addressing another slave without first generating a
STOP condition. Various combinations of receive/send formats are then possible within a single
transfer.
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Figure 15-4. Complete Data Transfer with a 7-Bit Address
Slave address Data
SDA MSB LSB R/S ACK MSB LSB ACK
SCL 1 2 7 8 9 1 2 7 8 9
The first seven bits of the first byte make up the slave address (see Figure 15-5 on page 376). The
eighth bit determines the direction of the message. A zero in the R/S position of the first byte means
that the master will write (send) data to the selected slave, and a one in this position means that
the master will receive data from the slave.
Figure 15-5. R/S Bit in First Byte
R/S
LSB
Slave address
MSB
15.2.1.3 Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is low (see Figure 15-6 on page 376).
Figure 15-6. Data Validity During Bit Transfer on the I2C Bus
Change
of data
allowed
Dataline
stable
SDA
SCL
15.2.1.4 Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data
validity requirements described in “Data Validity” on page 376.
When a slave receiver does not acknowledge the slave address, SDA must be left high by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Since the master controls the number of bytes in the transfer, it signals the end
of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave
transmitter must then release SDA to allow the master to generate the STOP or a repeated START
condition.
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15.2.1.5 Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is high. During arbitration, the first of the
competing master devices to place a '1' (high) on SDA while another master transmits a '0' (low)
will switch off its data output stage and retire until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
15.2.2 Available Speed Modes
The I2C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP.
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see
page 394).
The I2C clock period is calculated as follows:
SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/T = 333 Khz
Table 15-1 on page 377 gives examples of timer period, system clock, and speed mode (Standard
or Fast).
Table 15-1. Examples of I2C Master Timer Period versus Speed Mode
System Clock Timer Period Standard Mode Timer Period Fast Mode
4 Mhz 0x01 100 Kbps - -
6 Mhz 0x02 100 Kbps - -
12.5 Mhz 0x06 89 Kbps 0x01 312 Kbps
16.7 Mhz 0x08 93 Kbps 0x02 278 Kbps
20 Mhz 0x09 100 Kbps 0x02 333 Kbps
25 Mhz 0x0C 96.2 Kbps 0x03 312 Kbps
33Mhz 0x10 97.1 Kbps 0x04 330 Kbps
40Mhz 0x13 100 Kbps 0x04 400 Kbps
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System Clock Timer Period Standard Mode Timer Period Fast Mode
50Mhz 0x18 100 Kbps 0x06 357 Kbps
15.2.3 Interrupts
The I2C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master transaction error
■ Slave transaction received
■ Slave transaction requested
There is a separate interrupt signal for the I2C master and I2C modules. While both modules can
generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
15.2.3.1 I2C Master Interrupts
The I2C master module generates an interrupt when a transaction completes (either transmit or
receive), or when an error occurs during a transaction. To enable the I2C master interrupt, software
must write a '1' to the I2C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition
is met, software must check the ERROR bit in the I2C Master Control/Status (I2CMCS) register to
verify that an error didn't occur during the last transaction. An error condition is asserted if the last
transaction wasn't acknowledge by the slave or if the master was forced to give up ownership of
the bus due to a lost arbitration round with another master. If an error is not detected, the application
can proceed with the transfer. The interrupt is cleared by writing a '1' to the I2C Master Interrupt
Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Master Raw Interrupt Status (I2CMRIS) register.
15.2.3.2 I2C Slave Interrupts
The slave module generates interrupts as it receives requests from an I2C master. To enable the
I2C slave interrupt, write a '1' to the I2C Slave Interrupt Mask (I2CSIMR) register. Software
determines whether the module should write (transmit) or read (receive) data from the I2C Slave
Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status
(I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received,
the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a '1' to the I2C Slave
Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Slave Raw Interrupt Status (I2CSRIS) register.
15.2.4 Loopback Operation
The I2C modules can be placed into an internal loopback mode for diagnostic or debug work. This
is accomplished by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In
loopback mode, the SDA and SCL signals from the master and slave modules are tied together.
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15.2.5 Command Sequence Flow Charts
This section details the steps required to perform the various I2C transfer types in both master and
slave mode.
15.2.5.1 I2C Master Command Sequences
The figures that follow show the command sequences available for the I2C master.
Figure 15-7. Master Single SEND
Idle
Write Slave
Address to
I2CMSA
Write data to
I2CMDR
Read I2CMCS
Sequence
may be
omitted in a
Single Master
system
BUSBSY bit=0? NO
Write ---0-111 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
Error Service
Idle
YES
NO
NO
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Figure 15-8. Master Single RECEIVE
Idle
Write Slave
Address to
I2CMSA
Read I2CMCS
Sequence may be
omitted in a Single
Master system
BUSBSY bit=0? NO
Write ---00111 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
Error Service
Idle
NO
NO
Read data from
I2CMDR
YES
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Figure 15-9. Master Burst SEND
Idle
Write Slave
Address to
I2CMSA
Write data to
I2CMDR
Read I2CMCS
BUSBSY bit=0?
YES
Write ---0-011 to
I2CMCS
NO
Read I2CMCS
BUSY bit=0?
YES
ERROR bit=0?
YES
Write data to ARBLST bit=1?
I2CMDR
Write ---0-100 to
Index=n? I2CMCS
NO
Error Service
Idle
YES
Write ---0-001 to
I2CMCS
Write ---0-101 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
NO
Idle
YES
Error Service NO
NO
NO
NO
Sequence
may be
omitted in a
Single Master
system
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Figure 15-10. Master Burst RECEIVE
Idle
Write Slave
Address to
I2CMSA
Read I2CMCS
BUSBSY bit=0? NO
Write ---01011 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0? NO
ERROR bit=0?
YES
ARBLST bit=1?
Write ---0-100 to
I2CMCS
NO
Error Service
YES
Idle
Read data from
I2CMDR
Index=m-1?
Write ---00101 to
I2CMCS
YES
Idle
Read data from
Error Service I2CMDR
ERROR bit=0?
YES
Write ---01001 to
I2CMCS
Read I2CMCS
BUSY bit=0? NO
YES
Sequence
may be
omitted in a
Single Master
system
NO
NO
NO
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Figure 15-11. Master Burst RECEIVE after Burst SEND
Idle
Master operates in
Master Transmit mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---01011 to
I2CMCS
Master operates in
Master Receive mode
Idle
Repeated START
condition is generated
with changing data
direction
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Figure 15-12. Master Burst SEND after Burst RECEIVE
Idle
Master operates in
Master Receive mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---0-011 to
I2CMCS
Master operates in
Master Transmit mode
Idle
Repeated START
condition is generated
with changing data
direction
15.2.5.2 I2C Slave Command Sequences
Figure 15-13 on page 385 presents the command sequence available for the I2C slave.
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Figure 15-13. Slave Command Sequence
Idle
Write OWN Slave
Address to
I2CSOAR
Write -------1 to
I2CSCSR
Read I2CSCSR
RREQ bit=1?
Read data from
I2CSDR
YES
TREQ bit=1? NO
Write data to
I2CSDR
YES
NO
FBR is
also valid
15.3 Initialization and Configuration
The following example shows how to configure the I2C module to send a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation.
4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020.
5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:
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TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1;
TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
6. Specify the slave address of the master and that the next operation will be a Send by writing
the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired
data.
8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with
a value of 0x0000.0007 (STOP, START, RUN).
9. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
15.4 I2C Register Map
Table 15-2 on page 386 lists the I2C registers. All addresses given are relative to the I2C base
addresses for the master and slave:
■ I2C Master 0: 0x4002.0000
■ I2C Slave 0: 0x4002.0800
Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map
See
Offset Name Type Reset Description page
I2C Master
0x000 I2CMSA R/W 0x0000.0000 I2C Master Slave Address 388
0x004 I2CMCS R/W 0x0000.0000 I2C Master Control/Status 389
0x008 I2CMDR R/W 0x0000.0000 I2C Master Data 393
0x00C I2CMTPR R/W 0x0000.0001 I2C Master Timer Period 394
0x010 I2CMIMR R/W 0x0000.0000 I2C Master Interrupt Mask 395
0x014 I2CMRIS RO 0x0000.0000 I2C Master Raw Interrupt Status 396
0x018 I2CMMIS RO 0x0000.0000 I2C Master Masked Interrupt Status 397
0x01C I2CMICR WO 0x0000.0000 I2C Master Interrupt Clear 398
0x020 I2CMCR R/W 0x0000.0000 I2C Master Configuration 399
I2C Slave
0x000 I2CSOAR R/W 0x0000.0000 I2C Slave Own Address 401
0x004 I2CSCSR RO 0x0000.0000 I2C Slave Control/Status 402
0x008 I2CSDR R/W 0x0000.0000 I2C Slave Data 404
0x00C I2CSIMR R/W 0x0000.0000 I2C Slave Interrupt Mask 405
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See
Offset Name Type Reset Description page
0x010 I2CSRIS RO 0x0000.0000 I2C Slave Raw Interrupt Status 406
0x014 I2CSMIS RO 0x0000.0000 I2C Slave Masked Interrupt Status 407
0x018 I2CSICR WO 0x0000.0000 I2C Slave Interrupt Clear 408
15.5 Register Descriptions (I2C Master)
The remainder of this section lists and describes the I2C master registers, in numerical order by
address offset. See also “Register Descriptions (I2C Slave)” on page 400.
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Register 1: I2C Master Slave Address (I2CMSA), offset 0x000
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Send (Low).
I2C Master Slave Address (I2CMSA)
I2C Master 0 base: 0x4002.0000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SA R/S
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
I2C Slave Address
This field specifies bits A6 through A0 of the slave address.
7:1 SA R/W 0
Receive/Send
The R/S bit specifies if the next operation is a Receive (High) or Send
(Low).
Value Description
0 Send.
1 Receive.
0 R/S R/W 0
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Register 2: I2C Master Control/Status (I2CMCS), offset 0x004
This register accesses four control bits when written, and accesses seven status bits when read.
The status register consists of seven bits, which when read determine the state of the I2C bus
controller.
The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes
the generation of the START, or REPEATED START condition.
The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst.
To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with
the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1),
STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed
(or aborted due an error), the interrupt pin becomes active and the data may be read from the
I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set
normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after
each byte. This bit must be reset when the I2C bus controller requires no further data to be sent
from the slave transmitter.
Read-Only Status Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x00
Bus Busy
This bit specifies the state of the I2C bus. If set, the bus is busy;
otherwise, the bus is idle. The bit changes based on the START and
STOP conditions.
6 BUSBSY RO 0
I2C Idle
This bit specifies the I2C controller state. If set, the controller is idle;
otherwise the controller is not idle.
5 IDLE RO 0
Arbitration Lost
This bit specifies the result of bus arbitration. If set, the controller lost
arbitration; otherwise, the controller won arbitration.
4 ARBLST RO 0
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Bit/Field Name Type Reset Description
Acknowledge Data
This bit specifies the result of the last data operation. If set, the
transmitted data was not acknowledged; otherwise, the data was
acknowledged.
3 DATACK RO 0
Acknowledge Address
This bit specifies the result of the last address operation. If set, the
transmitted address was not acknowledged; otherwise, the address was
acknowledged.
2 ADRACK RO 0
Error
This bit specifies the result of the last bus operation. If set, an error
occurred on the last operation; otherwise, no error was detected. The
error can be from the slave address not being acknowledged, the
transmit data not being acknowledged, or because the controller lost
arbitration.
1 ERROR RO 0
I2C Busy
This bit specifies the state of the controller. If set, the controller is busy;
otherwise, the controller is idle. When the BUSY bit is set, the other status
bits are not valid.
0 BUSY RO 0
Write-Only Control Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
Offset 0x004
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ACK STOP START RUN
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved WO 0x00
Data Acknowledge Enable
When set, causes received data byte to be acknowledged automatically
by the master. See field decoding in Table 15-3 on page 391.
3 ACK WO 0
Generate STOP
When set, causes the generation of the STOP condition. See field
decoding in Table 15-3 on page 391.
2 STOP WO 0
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Bit/Field Name Type Reset Description
Generate START
When set, causes the generation of a START or repeated START
condition. See field decoding in Table 15-3 on page 391.
1 START WO 0
I2C Master Enable
When set, allows the master to send or receive data. See field decoding
in Table 15-3 on page 391.
0 RUN WO 0
Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3)
Current I2CMSA[0] I2CMCS[3:0] Description
State R/S ACK STOP START RUN
START condition followed by SEND (master goes to the
Master Transmit state).
Idle 0 Xa 0 1 1
START condition followed by a SEND and STOP
condition (master remains in Idle state).
0 X 1 1 1
START condition followed by RECEIVE operation with
negative ACK (master goes to the Master Receive state).
1 0 0 1 1
START condition followed by RECEIVE and STOP
condition (master remains in Idle state).
1 0 1 1 1
START condition followed by RECEIVE (master goes to
the Master Receive state).
1 1 0 1 1
1 1 1 1 1 Illegal.
All other combinations not listed are non-operations. NOP.
SEND operation (master remains in Master Transmit
state).
Master X X 0 0 1
Transmit
X X 1 0 0 STOP condition (master goes to Idle state).
SEND followed by STOP condition (master goes to Idle
state).
X X 1 0 1
Repeated START condition followed by a SEND (master
remains in Master Transmit state).
0 X 0 1 1
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
0 X 1 1 1
Repeated START condition followed by a RECEIVE
operation with a negative ACK (master goes to Master
Receive state).
1 0 0 1 1
Repeated START condition followed by a SEND and
STOP condition (master goes to Idle state).
1 0 1 1 1
Repeated START condition followed by RECEIVE (master
goes to Master Receive state).
1 1 0 1 1
1 1 1 1 1 Illegal.
All other combinations not listed are non-operations. NOP.
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Current I2CMSA[0] I2CMCS[3:0] Description
State R/S ACK STOP START RUN
RECEIVE operation with negative ACK (master remains
in Master Receive state).
Master X 0 0 0 1
Receive
X X 1 0 0 STOP condition (master goes to Idle state).b
RECEIVE followed by STOP condition (master goes to
Idle state).
X 0 1 0 1
RECEIVE operation (master remains in Master Receive
state).
X 1 0 0 1
X 1 1 0 1 Illegal.
Repeated START condition followed by RECEIVE
operation with a negative ACK (master remains in Master
Receive state).
1 0 0 1 1
Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
1 0 1 1 1
Repeated START condition followed by RECEIVE (master
remains in Master Receive state).
1 1 0 1 1
Repeated START condition followed by SEND (master
goes to Master Transmit state).
0 X 0 1 1
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
0 X 1 1 1
All other combinations not listed are non-operations. NOP.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.
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Register 3: I2C Master Data (I2CMDR), offset 0x008
This register contains the data to be transmitted when in the Master Transmit state, and the data
received when in the Master Receive state.
I2C Master Data (I2CMDR)
I2C Master 0 base: 0x4002.0000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Data Transferred
Data transferred during transaction.
7:0 DATA R/W 0x00
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Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C
This register specifies the period of the SCL clock.
I2C Master Timer Period (I2CMTPR)
I2C Master 0 base: 0x4002.0000
Offset 0x00C
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TPR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SCL Clock Period
This field specifies the period of the SCL clock.
SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD
where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the Timer Period register value (range of 1 to 255).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
7:0 TPR R/W 0x1
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Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C Master 0 base: 0x4002.0000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IM
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Interrupt Mask
This bit controls whether a raw interrupt is promoted to a controller
interrupt. If set, the interrupt is not masked and the interrupt is promoted;
otherwise, the interrupt is masked.
0 IM R/W 0
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Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014
This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
I2C Master 0 base: 0x4002.0000
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Raw Interrupt Status
This bit specifies the raw interrupt state (prior to masking) of the I2C
master block. If set, an interrupt is pending; otherwise, an interrupt is
not pending.
0 RIS RO 0
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Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018
This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
I2C Master 0 base: 0x4002.0000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Masked Interrupt Status
This bit specifies the raw interrupt state (after masking) of the I2C master
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.
0 MIS RO 0
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Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C
This register clears the raw interrupt.
I2C Master Interrupt Clear (I2CMICR)
I2C Master 0 base: 0x4002.0000
Offset 0x01C
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Interrupt Clear
This bit controls the clearing of the raw interrupt. A write of 1 clears the
interrupt; otherwise, a write of 0 has no affect on the interrupt state. A
read of this register returns no meaningful data.
0 IC WO 0
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Register 9: I2C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
I2C Master Configuration (I2CMCR)
I2C Master 0 base: 0x4002.0000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SFE MFE reserved LPBK
Type RO RO RO RO RO RO RO RO RO RO R/W R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
I2C Slave Function Enable
This bit specifies whether the interface may operate in Slave mode. If
set, Slave mode is enabled; otherwise, Slave mode is disabled.
5 SFE R/W 0
I2C Master Function Enable
This bit specifies whether the interface may operate in Master mode. If
set, Master mode is enabled; otherwise, Master mode is disabled and
the interface clock is disabled.
4 MFE R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:1 reserved RO 0x00
I2C Loopback
This bit specifies whether the interface is operating normally or in
Loopback mode. If set, the device is put in a test mode loopback
configuration; otherwise, the device operates normally.
0 LPBK R/W 0
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15.6 Register Descriptions (I2C Slave)
The remainder of this section lists and describes the I2C slave registers, in numerical order by
address offset. See also “Register Descriptions (I2C Master)” on page 387.
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Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000
This register consists of seven address bits that identify the Stellaris® I2C device on the I2C bus.
I2C Slave Own Address (I2CSOAR)
I2C Slave 0 base: 0x4002.0800
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OAR
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x00
I2C Slave Own Address
This field specifies bits A6 through A0 of the slave address.
6:0 OAR R/W 0x00
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Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004
This register accesses one control bit when written, and three status bits when read.
The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First
Byte Received (FBR) bit is set only after the Stellaris® device detects its own slave address
and receives the first data byte from the I2C master. The Receive Request (RREQ) bit indicates
that the Stellaris® I2C device has received a data byte from an I2C master. Read one data byte from
the I2C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit
indicates that the Stellaris® I2C device is addressed as a Slave Transmitter. Write one data byte
into the I2C Slave Data (I2CSDR) register to clear the TREQ bit.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
Stellaris® I2C slave operation.
Read-Only Status Register
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved FBR TREQ RREQ
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
First Byte Received
Indicates that the first byte following the slave’s own address is received.
This bit is only valid when the RREQ bit is set, and is automatically cleared
when data has been read from the I2CSDR register.
Note: This bit is not used for slave transmit operations.
2 FBR RO 0
Transmit Request
This bit specifies the state of the I2C slave with regards to outstanding
transmit requests. If set, the I2C unit has been addressed as a slave
transmitter and uses clock stretching to delay the master until data has
been written to the I2CSDR register. Otherwise, there is no outstanding
transmit request.
1 TREQ RO 0
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Bit/Field Name Type Reset Description
Receive Request
This bit specifies the status of the I2C slave with regards to outstanding
receive requests. If set, the I2C unit has outstanding receive data from
the I2C master and uses clock stretching to delay the master until the
data has been read from the I2CSDR register. Otherwise, no receive
data is outstanding.
0 RREQ RO 0
Write-Only Control Register
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
Offset 0x004
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Device Active
Value Description
0 Disables the I2C slave operation.
1 Enables the I2C slave operation.
0 DA WO 0
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Register 12: I2C Slave Data (I2CSDR), offset 0x008
This register contains the data to be transmitted when in the Slave Transmit state, and the data
received when in the Slave Receive state.
I2C Slave Data (I2CSDR)
I2C Slave 0 base: 0x4002.0800
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Data for Transfer
This field contains the data for transfer during a slave receive or transmit
operation.
7:0 DATA R/W 0x0
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Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C Slave 0 base: 0x4002.0800
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IM
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Interrupt Mask
This bit controls whether a raw interrupt is promoted to a controller
interrupt. If set, the interrupt is not masked and the interrupt is promoted;
otherwise, the interrupt is masked.
0 IM R/W 0
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Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010
This register specifies whether an interrupt is pending.
I2C Slave Raw Interrupt Status (I2CSRIS)
I2C Slave 0 base: 0x4002.0800
Offset 0x010
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Raw Interrupt Status
This bit specifies the raw interrupt state (prior to masking) of the I2C
slave block. If set, an interrupt is pending; otherwise, an interrupt is not
pending.
0 RIS RO 0
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Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C Slave 0 base: 0x4002.0800
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Masked Interrupt Status
This bit specifies the raw interrupt state (after masking) of the I2C slave
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.
0 MIS RO 0
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Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018
This register clears the raw interrupt.
I2C Slave Interrupt Clear (I2CSICR)
I2C Slave 0 base: 0x4002.0800
Offset 0x018
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Clear Interrupt
This bit controls the clearing of the raw interrupt. A write of 1 clears the
interrupt; otherwise a write of 0 has no affect on the interrupt state. A
read of this register returns no meaningful data.
0 IC WO 0
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16 Controller Area Network (CAN) Module
16.1 Controller Area Network Overview
Controller Area Network (CAN) is a multicast shared serial bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair
wire. Originally created for automotive purposes, it is also used in many embedded control
applications (such as industrial and medical). Bit rates up to 1 Mbps are possible at network lengths
below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at
500 m).
16.2 Controller Area Network Features
The Stellaris® CAN module supports the following features:
■ CAN protocol version 2.0 part A/B
■ Bit rates up to 1 Mbps
■ 32 message objects
■ Each message object has its own identifier mask
■ Maskable interrupt
■ Disable Automatic Retransmission mode for Time Triggered CAN (TTCAN) applications
■ Programmable Loopback mode for self-test operation
■ Programmable FIFO mode
■ Gluelessly attachable to an external CAN PHY through the CAN0Tx and CAN0Rx pins
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16.3 Controller Area Network Block Diagram
Figure 16-1. CAN Module Block Diagram
APB
Interface CAN Core
CANCTL
CANSTS
CANBIT
CANINT
CANTST
CANBRPE
CANIF1CRQ
CANIF1CMSK
CANIF1MSK1
CANIF1MSK2
CANIF1ARB1
CANIF1ARB2
CANIF1MCTL
CANIF1DA1
CANIF1DA2
CANIF1DB1
CANIF1DB2
CANIF2CRQ
CANIF2CMSK
CANIF2MSK1
CANIF2MSK2
CANIF2ARB1
CANIF2ARB2
CANIF2MCTL
CANIF2DA1
CANIF2DA2
CANIF2DB1
CANIF2DB2
ABP Pins CAN Tx/Rx
Message RAM
32 Message Objects
16.4 Controller Area Network Functional Description
The CAN module conforms to the CAN protocol version 2.0 (parts A and B). Message transfers that
include data, remote, error, and overload frames with an 11-bit identifier (standard) or a 29-bit
identifier (extended) are supported. Transfer rates can be programmed up to 1 Mbps.
The CAN module consists of three major parts:
■ CAN protocol controller and message handler
■ Message memory
■ CAN register interface
The protocol controller transfers and receives the serial data from the CAN bus and passes the data
on to the message handler. The message handler then loads this information into the appropriate
message object based on the current filtering and identifiers in the message object memory. The
message handler is also responsible for generating interrupts based on events on the CAN bus.
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The message object memory is a set of 32 identical memory blocks that hold the current configuration,
status, and actual data for each message object. These are accessed via the CAN message object
register interface. The message memory is not directly accessable in the Stellaris® memory map,
so the Stellaris® CAN controller provides an interface to communicate with the message memory.
The CAN message object register interface provides two register sets for communicating with the
message objects. Since there is no direct access to the message object memory, these two interfaces
must be used to read or write to each message object. The two message object interfaces allow
parallel access to the CAN controller message objects when multiple objects may have new
information that needs to be processed.
16.4.1 Initialization
The software initialization is started by setting the INIT bit in the CAN Control (CANCTL) register
(with software or by a hardware reset) or by going bus-off, which occurs when the transmitter's error
counter exceeds a count of 255. While INIT is set, all message transfers to and from the CAN bus
are stopped and the status of the CAN transmit output is recessive (High). Entering the initialization
state does not change the configuration of the CAN controller, the message objects, or the error
counters. However, some configuration registers are only accessible when in the initialization state.
To initialize the CAN controller, set the CAN Bit Timing (CANBIT) register and configure each
message object. If a message object is not needed, it is sufficient to set it as not valid by clearing
the MsgVal bit in the CANIFnARB2 register. Otherwise, the whole message object has to be
initialized, as the fields of the message object may not have valid information, causing unexpected
results. Access to the CAN Bit Timing (CANBIT) register and to the CAN Baud Rate Prescalar
Extension (CANBRPE) register to configure the bit timing is enabled when both the INIT and CCE
bits in the CANCTL register are set. To leave the initialization state, the INIT bit must be cleared.
Afterwards, the internal Bit Stream Processor (BSP) synchronizes itself to the data transfer on the
CAN bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits (Bus Idle)
before it takes part in bus activities and starts message transfers. The initialization of the message
objects is independent of being in the initialization state and can be done on the fly, but message
objects should all be configured to particular identifiers or set to not valid before the BSP starts the
message transfer. To change the configuration of a message object during normal operation, set
the MsgVal bit in the CANIFnARB2 register to 0 (not valid). When the configuration is completed,
MsgVal is set to 1 again (valid).
16.4.2 Operation
Once the CAN module is initialized and the INIT bit in the CANCTL register is reset to 0, the CAN
module synchronizes itself to the CAN bus and starts the message transfer. As messages are
received, they are stored in their appropriate message objects if they pass the message handler's
filtering. The whole message (including all arbitration bits, data-length code, and eight data bytes)
is stored in the message object. If the Identifier Mask (the Msk bits in the CANIFnMSKn registers)
is used, the arbitration bits that are masked to "don't care" may be overwritten in the message object.
The CPU may read or write each message at any time via the CAN Interface Registers (CANIFnCRQ,
CANIFnCMSK, CANIFnMSKn, CANIFnARBn, CANIFnMCTL, CANIFnDAn, and CANIFnDBn).
The message handler guarantees data consistency in case of concurrent accesses.
The transmission of message objects is under the control of the software that is managing the CAN
hardware. These can be message objects used for one-time data transfers, or permanent message
objects used to respond in a more periodic manner. Permanent message objects have all arbitration
and control set up, and only the data bytes are updated. To start the transmission, the TxRqst bit
in the CANTXRQn register and the NewDat bit in the CANNWDAn register are set. If several transmit
messages are assigned to the same message object (when the number of message objects is not
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sufficient), the whole message object has to be configured before the transmission of this message
is requested.
The transmission of any number of message objects may be requested at the same time; they are
transmitted according to their internal priority, which is based on the message identifier for the
message object. Messages may be updated or set to not valid any time, even when their requested
transmission is still pending. The old data is discarded when a message is updated before its pending
transmission has started. Depending on the configuration of the message object, the transmission
of a message may be requested autonomously by the reception of a remote frame with a matching
identifier.
There are two sets of CAN Interface Registers (CANIF1x and CANIF2x), which are used to access
the Message Objects in the Message RAM. The CAN controller coordinates transfers to and from
the Message RAM to and from the registers. The function of the two sets are independent and
identical and can be used to queue transactions.
16.4.3 Transmitting Message Objects
If the internal transmit shift register of the CAN module is ready for loading, and if there is no data
transfer between the CAN Interface Registers and message RAM, the valid message object with
the highest priority that has a pending transmission request is loaded into the transmit shift register
by the message handler and the transmission is started. The message object's NewDat bit is reset
and can be viewed in the CANNWDAn register. After a successful transmission, and if no new data
was written to the message object since the start of the transmission, the TxRqst bit in the
CANIFnCMSK register is reset. If the TxIE bit in the CANIFnMCTL register is set, the IntPnd bit
in the CANIFnMCTL register is set after a successful transmission. If the CAN module has lost the
arbitration or if an error occurred during the transmission, the message is re-transmitted as soon
as the CAN bus is free again. If, meanwhile, the transmission of a message with higher priority has
been requested, the messages are transmitted in the order of their priority.
16.4.4 Configuring a Transmit Message Object
Table 16-1 on page 412 specifies the bit settings for a transmit message object.
Table 16-1. Transmit Message Object Bit Settings
Register CANIFnARB2 CANIFnCMSK CANIFnMCTL CANIFnARB2 CANIFnMCTL
Bit MsgVal Arb Data Mask EoB Dir NewDat MsgLst RxIE TxIE IntPnd RmtEn TxRqst
Value 1 appl appl appl 1 1 0 0 0 appl 0 appl 0
The Xtd and ID bit fields in the CANIFnARBn registers are set by an application. They define the
identifier and type of the outgoing message. If an 11-bit Identifier (Standard Frame) is used, it is
programmed to bits [12:2] of CANIFnARB2, and the remaining identifier bits are not used by the
CAN controller.
If the TxIE bit is set, the IntPnd bit is set after a successful transmission of the message object.
When the RmtEn bit is set, a matching received remote frame causes the TxRqst bit to be set and
the message object automatically transfers the message object's data or generates an interrupt
indicating a remote frame was requested. This can be strictly a single message identifier or it can
be a range of values specified in the message object. The CAN mask registers, CANIFnMSKn,
configure which groups of frames are identified as remote frame requests. The UMask bit in the
CANIFnMCTL register enables the Msk bits in the CANIFnMSKn register to filter which frames are
identified as a remote frame request. The MXtd bit should be set if only 29-bit extended identifiers
should trigger a remote frame request.
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The DLC bit in the CANIFnMCTL register is set to the number of bytes to transfer to the message
object. TxRqst and RmtEn should not be set before the data is valid, as the current data in the
message object can be transmitted as soon as these bits are set.
16.4.5 Updating a Transmit Message Object
The CPU may update the data bytes of a Transmit Message Object any time via the CAN Interface
Registers and neither the MsgVal nor the TxRqst bits have to be reset before the update.
Even if only a part of the data bytes are to be updated, all four bytes of the corresponding
CANIFnDAn or CANIFnDBn register have to be valid before the content of that register is transferred
to the message object. Either the CPU has to write all four bytes into the CANIFnDAn or CANIFnDBn
register or the message object is transferred to the CANIFnDAn or CANIFnDBn register before the
CPU writes the new data bytes.
In order to only update the data in a message object, the WR, NewDat, DataA, and DataB bits are
written to the CAN IFn Command Mask (CANIFnMSKn) register, followed by writing the CAN IFn
Data registers, and then the number of the message object is written to the CAN IFn Command
Request (CANIFnCRQ) register, to update the data bytes and the TxRqst bit at the same time.
To prevent the reset of TxRqst at the end of a transmission that may already be in progress while
the data is updated, NewDat has to be set together with TxRqst. When NewDat is set together
with TxRqst, NewDat is reset as soon as the new transmission has started.
16.4.6 Accepting Received Message Objects
When the arbitration and control field (ID + Xtd + RmtEn + DLC) of an incoming message is
completely shifted into the CAN module, the message handling capability of the module starts
scanning the message RAM for a matching valid message object. To scan the message RAM for
a matching message object, the Acceptance Filtering unit is loaded with the arbitration bits from the
core. Then the arbitration and mask fields (including MsgVal, UMask, NewDat, and EoB) of message
object 1 are loaded into the Acceptance Filtering unit and compared with the arbitration field from
the shift register. This is repeated with each following message object until a matching message
object is found or until the end of the message RAM is reached. If a match occurs, the scanning is
stopped and the message handler proceeds depending on the type of frame received.
16.4.7 Receiving a Data Frame
The message handler stores the message from the CAN module receive shift register into the
respective message object in the message RAM. It stores the data bytes, all arbitration bits, and
the Data Length Code into the corresponding message object. This is implemented to keep the data
bytes connected with the identifier even if arbitration mask registers are used. The NewDat bit of
the CANIFnMCTL register is set to indicate that new data has been received. The CPU should reset
this bit when it reads the message object to indicate to the controller that the message has been
received and the buffer is free to receive more messages. If the CAN controller receives a message
and the NewDat bit was already set, the MsgLst bit is set to indicate that the previous data was
lost. If the RxIE bit of the CANIFnMCTL register is set, the IntPnd bit of the same register is set,
causing the CANINT interrupt register to point to the message object that just received a message.
The TxRqst bit of this message object should be cleared to prevent the transmission of a remote
frame.
16.4.8 Receiving a Remote Frame
When a remote frame is received, three different configurations of the matching message object
have to be considered:
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Configuration Description
At the reception of a matching remote frame, the TxRqst bit of this message object is set.
The rest of the message object remains unchanged, and the controller will transfer the data
in the message object.
Dir = 1 (direction = transmit)
RmtEn = 1
UMask = 1 or 0
At the reception of a matching remote frame, the TxRqst bit of this message object remains
unchanged; the remote frame is ignored. This remote frame is disabled and will not
automatically respond or indicate that the remote frame ever happened.
Dir = 1 (direction = transmit)
RmtEn = 0
UMask = 0
At the reception of a matching remote frame, the TxRqst bit of this message object is reset.
The arbitration and control field (ID + Xtd + RmtEn + DLC) from the shift register is stored
into the message object in the message RAM and the NewDat bit of this message object is
set. The data field of the message object remains unchanged; the remote frame is treated
similar to a received data frame. This is useful for a remote data request from another CAN
device for which the Stellaris® controller does not have readily available data. The software
must fill the data and answer the frame manually.
Dir = 1 (direction = transmit)
RmtEn = 0
UMask = 1
16.4.9 Receive/Transmit Priority
The receive/transmit priority for the message objects is controlled by the message number. Message
object 1 has the highest priority, while message object 32 has the lowest priority. If more than one
transmission request is pending, the message objects are transmitted in order based on the message
object with the lowest message number. This should not be confused with the message identifier
as that priority is enforced by the CAN bus. This means that if message object 1 and message object
2 both have valid messages that need to be transmitted, message object 1 will always be transmitted
first regardless of the message identifier in the message object itself.
16.4.10 Configuring a Receive Message Object
Table 16-2 on page 414 specifies the bit settings for a transmit message object.
Table 16-2. Receive Message Object Bit Settings
Register CANIFnARB2 CANIFnCMSK CANIFnMCTL CANIFnARB2 CANIFnMCTL
Bit MsgVal Arb Data Mask EoB Dir NewDat MsgLst RxIE TxIE IntPnd RmtEn TxRqst
Value 1 appl appl appl 1 0 0 0 appl 0 0 0 0
The Xtd and ID bit fields in the CANIFnARBn registers are set by an application. They define the
identifier and type of accepted received messages. If an 11-bit Identifier (Standard Frame) is used,
it is programmed to bits [12:2] of CANIFnARB2, and the remaining identifier bits are ignored by the
CAN controller. When a data frame with an 11-bit Identifier is received, only bits 12:2 of CANIFnARB2
are valid and the rest are set to 0.
If the RxIE bit is set, the IntPnd bit is set when a received data frame is accepted and stored in
the message object.
When the message handler stores a data frame in the message object, it stores the received Data
Length Code and eight data bytes. If the Data Length Code is less than 8, the remaining bytes of
the message object are overwritten by nonspecified values.
The CAN mask registers can be used to allow groups of data frames to be received by a message
object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are received by
a message object. The UMask bit in the CANIFnMCTL register enables the Msk bits in the
CANIFnMSKn register to filter which frames are received. The MXtd bit should be set if only 29-bit
extended identifiers should be received by this message object.
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16.4.11 Handling of Received Message Objects
The CPU may read a received message any time via the CAN Interface registers because the data
consistency is guaranteed by the message handler state machine.
Typically, the CPU first writes 0x007F to the CAN IFn Command Mask (CANIFnCMSK) register
and then writes the number of the message object to the CAN IFn Command Request
(CANIFnCRQ) register. That combination transfers the whole received message from the message
RAM into the Message Buffer registers (CANIFnMSKn, CANIFnARBn, and CANIFnMCTL).
Additionally, the NewDat and IntPnd bits are cleared in the message RAM, acknowledging that
the message has been read and clearing the pending interrupt being generated by this message
object.
If the message object uses masks for acceptance filtering, the arbitration bits show which of the
matching messages has been received.
The actual value of NewDat shows whether a new message has been received since the last time
this message object was read. The actual value of MsgLst shows whether more than one message
has been received since the last time this message object was read. MsgLst is not automatically
reset.
Using a remote frame, the CPU may request new data from another CAN node on the CAN bus.
Setting the TxRqst bit of a receive object causes the transmission of a remote frame with the receive
object's identifier. This remote frame triggers the other CAN node to start the transmission of the
matching data frame. If the matching data frame is received before the remote frame could be
transmitted, the TxRqst bit is automatically reset. This prevents the possible loss of data when the
other device on the CAN bus has already transmitted the data slightly earlier than expected.
16.4.12 Handling of Interrupts
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding their chronological order. An interrupt remains pending until
the CPU has cleared it.
The Status Interrupt has the highest priority. Among the message interrupts, the message object's
interrupt priority decreases with increasing message number. A message interrupt is cleared by
clearing the message object's IntPnd bit. The Status Interrupt is cleared by reading the CAN Status
(CANSTS) register.
The interrupt identifier IntId in the CANINT register indicates the cause of the interrupt. When no
interrupt is pending, the register holds the value to 0. If the value of CANINT is different from 0, then
there is an interrupt pending. If the IE bit is set in the CANCTL register, the interrupt line to the CPU
is active. The interrupt line remains active until CANINT is 0, all interrupt sources have been cleared
(the cause of the interrupt is reset), or until IE is reset, which disables interrupts from the CAN
controller.
The value 0x8000 in the CANINT register indicates that an interrupt is pending because the CAN
module has updated, but not necessarily changed, the CANSTS register (Error Interrupt or Status
Interrupt). This indicates that there is either a new Error Interrupt or a new Status Interrupt. A write
access can clear the RxOK, TxOK, and LEC flags in the CANSTS register, however, only a read
access to the CANSTS register will clear the source of the Status Interrupt.
IntId points to the pending message interrupt with the highest interrupt priority. The SIE bit in the
CANCTL register controls whether a change of the status register may cause an interrupt. The EIE
bit in the CANCTL register controls whether any interrupt from the CAN controller actually generates
an interrupt to the microcontroller's interrupt controller. The CANINT interrupt register is updated
even when the IE bit is set to zero.
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There are two possibilities when handling the source of a message interrupt. The first is to read the
IntId bit in the CANINT interrupt register to determine the highest priority interrupt that is pending,
and the second is to read the CAN Message Interrupt Pending (CANMSGnINT) register to see
all of the message objects that have pending interrupts.
An interrupt service routine reading the message that is the source of the interrupt may read the
message and reset the message object's IntPnd at the same time by setting the ClrIntPnd bit
in the CAN IFn Command Mask (CANIFnCMSK) register. When the IntPnd bit is cleared, the
CANINT register will contain the message number for the next message object with a pending
interrupt.
16.4.13 Bit Timing Configuration Error Considerations
Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the
performance of a CAN network can be reduced significantly. In many cases, the CAN bit
synchronization amends a faulty configuration of the CAN bit timing to such a degree that only
occasionally an error frame is generated. In the case of arbitration, however, when two or more
CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the
transmitters to become error passive. The analysis of such sporadic errors requires a detailed
knowledge of the CAN bit synchronization inside a CAN node and of the CAN nodes' interaction on
the CAN bus.
16.4.14 Bit Time and Bit Rate
The CAN system supports bit rates in the range of lower than 1 Kbps up to 1000 Kbps. Each member
of the CAN network has its own clock generator. The timing parameter of the bit time can be
configured individually for each CAN node, creating a common bit rate even though the CAN nodes'
oscillator periods may be different.
Because of small variations in frequency caused by changes in temperature or voltage and by
deteriorating components, these oscillators are not absolutely stable. As long as the variations
remain inside a specific oscillator's tolerance range, the CAN nodes are able to compensate for the
different bit rates by periodically resynchronizing to the bit stream.
According to the CAN specification, the bit time is divided into four segments (see Figure
16-2 on page 417): the Synchronization Segment, the Propagation Time Segment, the Phase Buffer
Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific, programmable
number of time quanta (see Table 16-3 on page 417). The length of the time quantum (tq), which is
the basic time unit of the bit time, is defined by the CAN controller's system clock (fsys) and the
Baud Rate Prescaler (BRP):
tq = BRP / fsys
The CAN module's system clock fsys is the frequency of its CAN module clock input.
The Synchronization Segment Sync_Seg is that part of the bit time where edges of the CAN bus
level are expected to occur; the distance between an edge that occurs outside of Sync_Seg and
the Sync_Seg is called the phase error of that edge.
The Propagation Time Segment Prop_Seg is intended to compensate for the physical delay times
within the CAN network.
The Phase Buffer Segments Phase_Seg1 and Phase_Seg2 surround the Sample Point.
The (Re-)Synchronization Jump Width (SJW) defines how far a resynchronization may move the
Sample Point inside the limits defined by the Phase Buffer Segments to compensate for edge phase
errors.
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A given bit rate may be met by different bit-time configurations, but for the proper function of the
CAN network, the physical delay times and the oscillator's tolerance range have to be considered.
Figure 16-2. CAN Bit Time
Table 16-3. CAN Protocol Rangesa
Parameter Range Remark
BRP [1 .. 32] Defines the length of the time quantum tq
Sync_Seg 1 tq Fixed length, synchronization of bus input to system clock
Prop_Seg [1 .. 8] tq Compensates for the physical delay times
Phase_Seg1 [1 .. 8] tq May be lengthened temporarily by synchronization
Phase_Seg2 [1 .. 8] tq May be shortened temporarily by synchronization
SJW [1 .. 4] tq May not be longer than either Phase Buffer Segment
a. This table describes the minimum programmable ranges required by the CAN protocol.
The bit timing configuration is programmed in two register bytes in the CANBIT register. The sum
of Prop_Seg and Phase_Seg1 (as TSEG1) is combined with Phase_Seg2 (as TSEG2) in one byte,
and SJW and BRP are combined in the other byte.
In these bit timing registers, the four components TSEG1, TSEG2, SJW, and BRP have to be
programmed to a numerical value that is one less than its functional value; so instead of values in
the range of [1..n], values in the range of [0..n-1] are programmed. That way, for example, SJW
(functional range of [1..4]) is represented by only two bits. Therefore, the length of the bit time is
(programmed values):
[TSEG1 + TSEG2 + 3] × tq
or (functional values):
[Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] × tq
The data in the bit timing registers are the configuration input of the CAN protocol controller. The
Baud Rate Prescalar (configured by BRP) defines the length of the time quantum, the basic time
unit of the bit time; the Bit Timing Logic (configured by TSEG1, TSEG2, and SJW) defines the number
of time quanta in the bit time.
The processing of the bit time, the calculation of the position of the Sample Point, and occasional
synchronizations are controlled by the CAN controller and are evaluated once per time quantum.
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The CAN controller translates messages to and from frames. It generates and discards the enclosing
fixed format bits, inserts and extracts stuff bits, calculates and checks the CRC code, performs the
error management, and decides which type of synchronization is to be used. It is evaluated at the
Sample Point and processes the sampled bus input bit. The time after the Sample Point that is
needed to calculate the next bit to be sent (that is, the data bit, CRC bit, stuff bit, error flag, or idle)
is called the Information Processing Time (IPT).
The IPT is application-specific but may not be longer than 2 tq; the CAN's IPT is 0 tq. Its length is
the lower limit of the programmed length of Phase_Seg2. In case of synchronization, Phase_Seg2
may be shortened to a value less than IPT, which does not affect bus timing.
16.4.15 Calculating the Bit Timing Parameters
Usually, the calculation of the bit timing configuration starts with a desired bit rate or bit time. The
resulting bit time (1/bit rate) must be an integer multiple of the system clock period.
The bit time may consist of 4 to 25 time quanta. Several combinations may lead to the desired bit
time, allowing iterations of the following steps.
The first part of the bit time to be defined is the Prop_Seg. Its length depends on the delay times
measured in the system. A maximum bus length as well as a maximum node delay has to be defined
for expandable CAN bus systems. The resulting time for Prop_Seg is converted into time quanta
(rounded up to the nearest integer multiple of tq).
The Sync_Seg is 1 tq long (fixed), which leaves (bit time - Prop_Seg - 1) tq for the two Phase Buffer
Segments. If the number of remaining tq is even, the Phase Buffer Segments have the same length,
that is, Phase_Seg2 = Phase_Seg1, else Phase_Seg2 = Phase_Seg1 + 1.
The minimum nominal length of Phase_Seg2 has to be regarded as well. Phase_Seg2 may not
be shorter than the CAN controller's Information Processing Time, which is, depending on the actual
implementation, in the range of [0..2] tq.
The length of the Synchronization Jump Width is set to its maximum value, which is the minimum
of 4 and Phase_Seg1.
The oscillator tolerance range necessary for the resulting configuration is calculated by the formula
given below:
(1 -df) x fnom <= fosc <= (1+ df) × fnom
where:
■ df = Maximum tolerance of oscillator frequency
■ fosc = Actual oscillator frequency
■ fnom = Nominal oscillator frequency
Maximum frequency tolerance must take into account the following formulas:
df <= (Phase_Seg1,Phase_Seg2)min/ 2 × (13 × tbit - Phase_Seg2)
dfmax = 2 × df × fnom
where:
■ Phase_Seg1 and Phase_Seg2 are from Table 16-3 on page 417
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■ tbit = Bit Time
■ dfmax = Maximum difference between two oscillators
If more than one configuration is possible, that configuration allowing the highest oscillator tolerance
range should be chosen.
CAN nodes with different system clocks require different configurations to come to the same bit
rate. The calculation of the propagation time in the CAN network, based on the nodes with the
longest delay times, is done once for the whole network.
The CAN system's oscillator tolerance range is limited by the node with the lowest tolerance range.
The calculation may show that bus length or bit rate have to be decreased or that the oscillator
frequencies' stability has to be increased in order to find a protocol-compliant configuration of the
CAN bit timing.
The resulting configuration is written into the CAN Bit Timing (CANBIT) register :
(Phase_Seg2-1)&(Phase_Seg1+Prop_Seg-1)&(SynchronizationJumpWidth-1)&(Prescaler-1)
16.4.15.1 Example for Bit Timing at High Baud Rate
In this example, the frequency of CAN clock is 25 MHz, BRP is 0, and the bit rate is 1 Mbps.
tq 40 ns = 1/((BRP + 1) × CAN Clock)
delay of bus driver 50 ns
delay of receiver circuit 30 ns
delay of bus line (40m) 220 ns
tProp 640 ns = 16 × tq
tSJW 160 ns = 4 × tq
tTSeg1 800 ns = tProp + tSJW
tTSeg2 160 ns = Information Processing Time + 4 × tq
tSync-Seg 40 ns = 1 × tq
bit time 1000 ns = tSync-Seg + tTSeg1 + tTSeg2
tolerance for CAN_CLK 0.39 % =
min(PB1,PB2)/ 2 × (13 x bit time - PB2) =
0.1us/ 2 x (13x 1us - 2us)
In the above example, the parameters for the CANBIT register are: TSeg2=3, TSeg1=15, SJW =3
and BRP=0. This makes the final value programmed into the CANBIT register, 0x3FC0.
16.4.15.2 Example for Bit Timing at Low Baud Rate
In this example, the frequency of CAN clock is 50 MHz, BRP is 25, and the bit rate is 100 Kbps.
tq 500 ns = 1/((BRP + 1) × CAN clock)
delay of bus driver 200 ns
delay of receiver circuit 80 ns
delay of bus line (40m) 220 ns
tProp 4.5 ms = 9 × tq
tSJW 2 ms = 4 × tq
tTSeg1 6.5 ms = tProp + tSJW
tTSeg2 3 ms = Information Processing Time + 6 × tq
tSync-Seg 500 ns = 1 × tq
bit time 10 ms = tSync-Seg + tTSeg1 + tTSeg2
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tolerance for CAN_CLK 1.58 % =
min(PB1,PB2)/ 2 x (13 x bit time - PB2) =
4us/ 2 x (13 x 10us - 4us)
In this example, the concatenated bit time parameters are (4-1)3&(5-1)4&(4-1)2&(2-1)6, and CANBIT
is programmed to 0x34C1.
In the above example, the parameters for the CANBIT register are: TSeg2=5, TSeg1=12, SJW =3
and BRP=24. This makes the final value programmed into the CANBIT register, 0x5CD8.
16.5 Controller Area Network Register Map
Table 16-4 on page 420 lists the registers. All addresses given are relative to the CAN base address
of:
■ CAN0: 0x4004.0000
Table 16-4. CAN Register Map
See
Offset Name Type Reset Description page
0x000 CANCTL R/W 0x0000.0001 CAN Control 422
0x004 CANSTS R/W 0x0000.0000 CAN Status 424
0x008 CANERR RO 0x0000.0000 CAN Error Counter 427
0x00C CANBIT R/W 0x0000.2301 CAN Bit Timing 428
0x010 CANINT RO 0x0000.0000 CAN Interrupt 430
0x014 CANTST R/W 0x0000.0000 CAN Test 431
0x018 CANBRPE R/W 0x0000.0000 CAN Baud Rate Prescalar Extension 433
0x020 CANIF1CRQ R/W 0x0000.0001 CAN IF1 Command Request 434
0x024 CANIF1CMSK R/W 0x0000.0000 CAN IF1 Command Mask 435
0x028 CANIF1MSK1 R/W 0x0000.FFFF CAN IF1 Mask 1 438
0x02C CANIF1MSK2 R/W 0x0000.FFFF CAN IF1 Mask 2 439
0x030 CANIF1ARB1 R/W 0x0000.0000 CAN IF1 Arbitration 1 440
0x034 CANIF1ARB2 R/W 0x0000.0000 CAN IF1 Arbitration 2 441
0x038 CANIF1MCTL R/W 0x0000.0000 CAN IF1 Message Control 442
0x03C CANIF1DA1 R/W 0x0000.0000 CAN IF1 Data A1 444
0x040 CANIF1DA2 R/W 0x0000.0000 CAN IF1 Data A2 444
0x044 CANIF1DB1 R/W 0x0000.0000 CAN IF1 Data B1 444
0x048 CANIF1DB2 R/W 0x0000.0000 CAN IF1 Data B2 444
0x080 CANIF2CRQ R/W 0x0000.0001 CAN IF2 Command Request 434
0x084 CANIF2CMSK R/W 0x0000.0000 CAN IF2 Command Mask 435
0x088 CANIF2MSK1 R/W 0x0000.FFFF CAN IF2 Mask 1 438
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See
Offset Name Type Reset Description page
0x08C CANIF2MSK2 R/W 0x0000.FFFF CAN IF2 Mask 2 439
0x090 CANIF2ARB1 R/W 0x0000.0000 CAN IF2 Arbitration 1 440
0x094 CANIF2ARB2 R/W 0x0000.0000 CAN IF2 Arbitration 2 441
0x098 CANIF2MCTL R/W 0x0000.0000 CAN IF2 Message Control 442
0x09C CANIF2DA1 R/W 0x0000.0000 CAN IF2 Data A1 444
0x0A0 CANIF2DA2 R/W 0x0000.0000 CAN IF2 Data A2 444
0x0A4 CANIF2DB1 R/W 0x0000.0000 CAN IF2 Data B1 444
0x0A8 CANIF2DB2 R/W 0x0000.0000 CAN IF2 Data B2 444
0x100 CANTXRQ1 RO 0x0000.0000 CAN Transmission Request 1 445
0x104 CANTXRQ2 RO 0x0000.0000 CAN Transmission Request 2 445
0x120 CANNWDA1 RO 0x0000.0000 CAN New Data 1 446
0x124 CANNWDA2 RO 0x0000.0000 CAN New Data 2 446
0x140 CANMSG1INT RO 0x0000.0000 CAN Message 1 Interrupt Pending 447
0x144 CANMSG2INT RO 0x0000.0000 CAN Message 2 Interrupt Pending 447
0x160 CANMSG1VAL RO 0x0000.0000 CAN Message 1 Valid 448
0x164 CANMSG2VAL RO 0x0000.0000 CAN Message 2 Valid 448
16.6 Register Descriptions
The remainder of this section lists and describes the CAN registers, in numerical order by address
offset. There are two sets of Interface Registers that are used to access the Message Objects in
the Message RAM: CANIF1x and CANIF2x. The function of the two sets are identical and are used
to queue transactions.
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Register 1: CAN Control (CANCTL), offset 0x000
This control register initializes the module and enables test mode and interrupts.
The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting
or resetting INIT. If the device goes bus-off, it sets INIT, stopping all bus activities. Once INIT
has been cleared by the CPU, the device then waits for 129 occurrences of Bus Idle (129 * 11
consecutive High bits) before resuming normal operations. At the end of the bus-off recovery
sequence, the Error Management Counters are reset.
During the waiting time after INIT is reset, each time a sequence of 11 High bits has been monitored,
a Bit0Error code is written to the CANSTS status register, enabling the CPU to readily check
whether the CAN bus is stuck Low or continuously disturbed, and to monitor the proceeding of the
bus-off recovery sequence.
CAN Control (CANCTL)
CAN0 base: 0x4004.0000
Offset 0x000
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Test CCE DAR reserved EIE SIE IE INIT
Type RO RO RO RO RO RO RO RO R/W R/W R/W RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0000
Test Mode Enable
0: Normal Operation
1: Test Mode
7 Test R/W 0
Configuration Change Enable
0: Do not allow write access to the CANBIT register.
1: Allow write access to the CANBIT register if the INIT bit is 1.
6 CCE R/W 0
Disable Automatic Retransmission
0: Auto retransmission of disturbed messages is enabled.
1: Auto retransmission is disabled.
5 DAR R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4 reserved RO 0
Error Interrupt Enable
0: Disabled. No Error Status interrupt is generated.
1: Enabled. A change in the Boff or EWarn bits in the CANSTS register
generates an interrupt.
3 EIE R/W 0
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Bit/Field Name Type Reset Description
Status Interrupt Enable
0: Disabled. No Status interrupt is generated.
1: Enabled. An interrupt is generated when a message has successfully
been transmitted or received, or a CAN bus error has been detected. A
change in the TxOK or RxOK bits in the CANSTS register generates an
interrupt.
2 SIE R/W 0
CAN Interrupt Enable
0: Interrupts disabled.
1: Interrupts enabled.
1 IE R/W 0
Initialization
0: Normal operation.
1: Initialization started.
0 INIT R/W 1
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Register 2: CAN Status (CANSTS), offset 0x004
The status register contains information for interrupt servicing such as Bus-Off, error count threshold,
and error types.
The LEC field holds the code that indicates the type of the last error to occur on the CAN bus. This
field is cleared to 0 when a message has been transferred (reception or transmission) without error.
The unused error code 7 may be written by the CPU to manually set this field to an invalid error so
that it can be checked for a change later.
An Error Interrupt is generated by the BOff and EWarn bits and a Status Interrupt is generated by
the RxOK, TxOK, and LEC bits, assuming that the corresponding enable bits in the CAN Control
(CANCTL) register are set. A change of the EPass bit or a write to the RxOK, TxOK, or LEC bits
does not generate an interrupt.
Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register, if it is
pending.
CAN Status (CANSTS)
CAN0 base: 0x4004.0000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BOff EWarn EPass RxOK TxOK LEC
Type RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0000
Bus-Off Status
0: Module is not in bus-off state.
1: Module is in bus-off state.
7 BOff RO 0
Warning Status
0: Both error counters are below the error warning limit of 96.
1: At least one of the error counters has reached the error warning limit
of 96.
6 EWarn RO 0
Error Passive
0: The CAN module is in the Error Active state, that is, the receive or
transmit error count is less than or equal to 127.
1: The CAN module is in the Error Passive state, that is, the receive or
transmit error count is greater than 127.
5 EPass RO 0
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Bit/Field Name Type Reset Description
Received a Message Successfully
0: Since this bit was last reset to 0, no message has been successfully
received.
1: Since this bit was last reset to 0, a message has been successfully
received, independent of the result of the acceptance filtering.
This bit is never reset by the CAN module.
4 RxOK R/W 0
Transmitted a Message Successfully
0: Since this bit was last reset to 0, no message has been successfully
transmitted.
1: Since this bit was last reset to 0, a message has been successfully
transmitted error-free and acknowledged by at least one other node.
This bit is never reset by the CAN module.
3 TxOK R/W 0
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Bit/Field Name Type Reset Description
Last Error Code
This is the type of the last error to occur on the CAN bus.
Value Definition
0x0 No Error
Stuff Error
More than 5 equal bits in a sequence have occurred in a part
of a received message where this is not allowed.
0x1
Format Error
A fixed format part of the received frame has the wrong format.
0x2
ACK Error
The message transmitted was not acknowledged by another
node.
0x3
Bit 1 Error
When a message is transmitted, the CAN controller monitors
the data lines to detect any conflicts. When the arbitration field
is transmitted, data conflicts are a part of the arbitration protocol.
When other frame fields are transmitted, data conflicts are
considered errors.
A Bit 1 Error indicates that the device wanted to send a High
level (logical 1) but the monitored bus value was Low (logical
0).
0x4
Bit 0 Error
A Bit 0 Error indicates that the device wanted to send a Low
level (logical 0), but the monitored bus value was High (logical
1).
During bus-off recovery, this status is set each time a sequence
of 11 High bits has been monitored. This enables the CPU to
monitor the proceeding of the bus-off recovery sequence without
any disturbances to the bus.
0x5
CRC Error
The CRC checksum was incorrect in the received message,
indicating that the calculated value received did not match the
calculated CRC of the data.
0x6
Unused
When the LEC bit shows this value, no CAN bus event was
detected since the CPU wrote this value to LEC.
0x7
2:0 LEC R/W 0x0
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Register 3: CAN Error Counter (CANERR), offset 0x008
This register contains the error counter values, which can be used to analyze the cause of an error.
CAN Error Counter (CANERR)
CAN0 base: 0x4004.0000
Offset 0x008
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RP REC TEC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Received Error Passive
0: The Receive Error counter is below the Error Passive level (127 or
less).
1: The Receive Error counter has reached the Error Passive level (128
or greater).
15 RP RO 0
Receive Error Counter
State of the receiver error counter (0 to 127).
14:8 REC RO 0x0
Transmit Error Counter
State of the transmit error counter (0 to 255).
7:0 TEC RO 0x0
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Register 4: CAN Bit Timing (CANBIT), offset 0x00C
This register is used to program the bit width and bit quantum. Values are to be programmed to the
system clock frequency. This register is write-enabled by the CCE and INIT bits in the CANCTL
register. See “Bit Time and Bit Rate” on page 416 for more information.
CAN Bit Timing (CANBIT)
CAN0 base: 0x4004.0000
Offset 0x00C
Type R/W, reset 0x0000.2301
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TSeg2 TSeg1 SJW BRP
Type RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:15 reserved RO 0x0000
Time Segment after Sample Point
0x00-0x07: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, a reset value of 0x2 defines that there is 3(2+1) bit
time quanta defined for Phase_Seg2 (see Figure 16-2 on page 417).
The bit time quanta is defined by BRP.
14:12 TSeg2 R/W 0x2
Time Segment Before Sample Point
0x00-0x0F: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, the reset value of 0x3 defines that there is 4(3+1) bit
time quanta defined for Phase_Seg1 (see Figure 16-2 on page 417).
The bit time quanta is define by BRP.
11:8 TSeg1 R/W 0x3
(Re)Synchronization Jump Width
0x00-0x03: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
During the start of frame (SOF), if the CAN controller detects a phase
error (misalignment), it can adjust the length of TSeg2 or TSeg1 by the
value in SJW. So the reset value of 0 adjusts the length by 1 bit time
quanta.
7:6 SJW R/W 0x0
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Bit/Field Name Type Reset Description
Baud Rate Prescalar
The value by which the oscillator frequency is divided for generating the
bit time quanta. The bit time is built up from a multiple of this quantum.
0x00-0x03F: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
BRP defines the number of CAN clock periods that make up 1 bit time
quanta, so the reset value is 2 bit time quanta (1+1).
The CANBRPE register can be used to further divide the bit time.
5:0 BRP R/W 0x1
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Register 5: CAN Interrupt (CANINT), offset 0x010
This register indicates the source of the interrupt.
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding their chronological order. An interrupt remains pending until
the CPU has cleared it. If the IntId bit is not 0x0000 (the default) and the IE bit in the CANCTL
register is set, the interrupt is active. The interrupt line remains active until the IntId bit is set back
to 0x0000 when the cause of all interrupts are reset, or until IE is reset.
Note: Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register,
if it is pending.
CAN Interrupt (CANINT)
CAN0 base: 0x4004.0000
Offset 0x010
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IntId
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Interrupt Identifier
The number in this field indicates the source of the interrupt.
Value Definition
0x0000 No interrupt pending
Number of the message object that caused the
interrupt
0x0001-0x0020
0x0021-0x7FFF Unused
0x8000 Status Interrupt
0x8001-0xFFFF Unused
15:0 IntId RO 0x0000
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Controller Area Network (CAN) Module
Register 6: CAN Test (CANTST), offset 0x014
This is the test mode register for self-test and external pin access. It is write-enabled by the Test
bit in the CANCTL register. Different test functions may be combined, however, CAN transfers will
be affected if the Tx bits in this register are not zero.
CAN Test (CANTST)
CAN0 base: 0x4004.0000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Rx Tx LBack Silent Basic reserved
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0000
Receive Observation
Displays the value on the CANnRx pin.
7 Rx RO 0
Transmit Control
Overrides control of the CANnTx pin.
Value Description
0x0 CANnTx is controlled by the CAN module
0x1 Sample Point signal driven on the CANnTx pin
0x2 CANnTx drives a Low value
0x3 CANnTx drives a High value
6:5 Tx R/W 0x0
Loopback Mode
0: Disabled.
1: Enabled.
4 LBack R/W 0
Silent Mode
Do not transmit data; monitor the bus. Also known as Bus Monitor mode.
0: Disabled.
1: Enabled.
3 Silent R/W 0
Basic Mode
0: Disabled.
1: Use CANIF1 registers as transmit buffer, and use CANIF2 registers
as receive buffer.
2 Basic R/W 0
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1:0 reserved RO 0x0
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Controller Area Network (CAN) Module
Register 7: CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018
This register is used to further divide the bit time set with the BRP bit in the CANBIT register. It is
write-enabled with the CCE bit in the CANCTL register.
CAN Baud Rate Prescalar Extension (CANBRPE)
CAN0 base: 0x4004.0000
Offset 0x018
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BRPE
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x0000
Baud Rate Prescalar Extension
0x00-0x0F: Extend the BRP bit in the CANBIT register to values up to
1023. The actual interpretation by the hardware is one more than the
value programmed by BRPE (MSBs) and BRP (LSBs).
3:0 BRPE R/W 0x0
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Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080
This register is used to start a transfer when its MNUM bit field is updated. Its Busy bit indicates that
the information is transferring from the CAN Interface Registers to the internal message RAM.
A message transfer is started as soon as there is a write of the message object number with the
MNUM bit. With this write operation, the Busy bit is automatically set to 1 to indicate that a transfer
is in progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer between the interface register
and the message RAM completes, which then sets the Busy bit back to 0.
CAN IF1 Command Request (CANIF1CRQ)
CAN0 base: 0x4004.0000
Offset 0x020
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Busy reserved MNUM
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Busy Flag
0: Reset when read/write action has finished.
1: Set when a write occurs to the message number in this register.
15 Busy RO 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14:6 reserved RO 0x00
Message Number
Selects one of the 32 message objects in the message RAM for data
transfer. The message objects are numbered from 1 to 32.
Value Description
0 is not a valid message number; it is interpreted as 0x20,
or object 32.
0x00
0x01-0x20 Indicates specified message object 1 to 32.
Not a valid message number; values are shifted and it is
interpreted as 0x01-0x1F.
0x21-0x3F
5:0 MNUM R/W 0x01
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Controller Area Network (CAN) Module
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084
The Command Mask registers specify the transfer direction and select which buffer registers are
the source or target of the data transfer.
Read-Only CANIFnCMSK Register
CAN IF1 Command Mask (CANIF1CMSK)
CAN0 base: 0x4004.0000
Offset 0x024
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WRNRD Mask Arb Control ClrIntPnd NewDat DataA DataB
Type RO RO RO RO RO RO RO RO R R R R R R R R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0000
Write, Not Read
Transfer the message object address specified by the CAN Command
Request (CANIFnCRQ) register to the CAN message buffer registers
(CANIFnMSK1, CANIFnMSK2, CANIFnARB1, CANIFnARB2,
CANIFnCTL, CANIFnDA1, CANIFnDA2, CANIFnDB1, and
CANIFnDB2).
7 WRNRD R 0
Access Mask Bits
0: Mask bits unchanged.
1: Transfer IDMask + Dir + MXtd of the message object into the
Interface registers.
6 Mask R 0
Access Arbitration Bits
0: Arbitration bits unchanged.
1: Transfer ID + Dir + Xtd + MsgVal of the message object into the
Interface registers.
5 Arb R 0
Access Control Bits
0: Control bits unchanged.
1: Transfer control bits into Interface registers.
4 Control R 0
Clear Interrupt Pending Bit
0: IntPnd bit in CANIFnMCTL register remains unchanged.
1: Clear IntPnd bit in the CANIFnMCTL register in the message object.
3 ClrIntPnd R 0
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Bit/Field Name Type Reset Description
Access New Data
0: NewDat bit unchanged.
1: Clear NewDat bit in the message object.
Note: A read access to a message object can be combined with the
reset of the control bits IntPdn and NewDat. The values of
these bits that are transferred to the CANIFnMCTL register
always reflect the status before resetting these bits.
2 NewDat R 0
Access Data Byte 0 to 3
0: Data bytes 0-3 are unchanged.
1: Transfer data bytes 0-3 in message object to CANIFnDA1 and
CANIFnDA2.
1 DataA R 0
Access Data Byte 4 to 7
0: Data bytes 4-7 unchanged.
1: Transfer data bytes 4-7 in message object to CANIFnDB1 and
CANIFnDB2.
0 DataB R 0
Write-Only CANIFnCMSK Register
CAN IF1 Command Mask (CANIF1CMSK)
CAN0 base: 0x4004.0000
Offset 0x024
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WRNRD Mask Arb Control reserved TxRqst DataA DataB
Type RO RO RO RO RO RO RO RO W W W W RO W W W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0000
Write, Not Read
0: Read.
1: Write. Transfer data from the message buffer registers to the message
object address specified by the CANIFnCRQ register.
7 WRNRD W 0
Access Mask Bits
0: Mask bits unchanged.
1: Transfer IDMask + Dir + MXtd to message object.
6 Mask W 0
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Bit/Field Name Type Reset Description
Access Arbitration Bits
0: Arbitration bits unchanged.
1: Transfer ID + Dir + Xtd + MsgVal to message object.
5 Arb W 0
Access Control Bits
0: Control bits unchanged.
1: Transfer control bits to message object.
4 Control W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
Access Transmission Request Bit
0: TxRqst bit unchanged.
1: Set TxRqst bit
Note: If a transmission is requested by programming this TxRqst
bit, the parallel TxRqst in the CANIFnMCTL register is
ignored.
2 TxRqst W 0
Access Data Byte 0 to 3
0: Data bytes 0-3 are unchanged.
1: Transfer data bytes 0-3 (CANIFnDA1 and CANIFnDA2) to message
object.
1 DataA W 0
Access Data Byte 4 to 7
0: Data bytes 4-7 unchanged.
1: Transfer data bytes 4-7 (CANIFnDB1 and CANIFnDB2) to message
object.
0 DataB W 0
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Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088
The mask information provided in this register accompanies the data (CANIFnDAn), arbitration
information (CANIFnARBn), and control information (CANIFnMCTL) to the message object in the
message RAM. The mask is used with the ID bit in the CANIFnARBn register for acceptance
filtering. Additional mask information is contained in the CANIFnMSK2 register.
CAN IF1 Mask 1 (CANIF1MSK1)
CAN0 base: 0x4004.0000
Offset 0x028
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Msk
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Identifier Mask
0: The corresponding identifier bit (ID) in the message object cannot
inhibit the match in acceptance filtering.
1: The corresponding identifier bit (ID) is used for acceptance filtering.
15:0 Msk R/W 0xFF
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Controller Area Network (CAN) Module
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C
This register holds extended mask information that accompanies the CANIFnMSK1 register.
CAN IF1 Mask 2 (CANIF1MSK2)
CAN0 base: 0x4004.0000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MXtd MDir reserved Msk
Type R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Mask Extended Identifier
0: The extended identifier bit (Xtd in the CANIFnARB2 register) has
no effect on the acceptance filtering.
1: The extended identifier bit Xtd is used for acceptance filtering.
15 MXtd R/W 0x1
Mask Message Direction
0: The message direction bit (Dir in the CANIFnARB2 register) has
no effect for acceptance filtering.
1: The message direction bit Dir is used for acceptance filtering.
14 MDir R/W 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13 reserved RO 0x1
Identifier Mask
0: The corresponding identifier bit (ID) in the message object cannot
inhibit the match in acceptance filtering.
1: The corresponding identifier bit (ID) is used for acceptance filtering.
12:0 Msk R/W 0xFF
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Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090
These registers hold the identifiers for acceptance filtering.
CAN IF1 Arbitration 1 (CANIF1ARB1)
CAN0 base: 0x4004.0000
Offset 0x030
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Message Identifier
This bit field is used with the ID field in the CANIFnARB2 register to
create the message identifier. ID[28:0] is the Extended Frame and
ID[28:18] is the Standard Frame.
15:0 ID R/W 0x00
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Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094
These registers hold information for acceptance filtering.
CAN IF1 Arbitration 2 (CANIF1ARB2)
CAN0 base: 0x4004.0000
Offset 0x034
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MsgVal Xtd Dir ID
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Message Valid
0: The message object is ignored by the message handler.
1: The message object is configured and will be considered by the
message handler within the CAN controller.
All unused message objects should have this bit cleared during
initialization and before clearing the Init bit in the CANCTL register.
The MsgVal bit must also be cleared before any of the following bits
are modified or if the message object is no longer required: the ID bit
fields in the CANIFnARBn registers, the Xtd and Dir bits in the
CANIFnARB2 register, or the DLC bits in the CANIFnMCTL register.
15 MsgVal R/W 0x0
Extended Identifier
0: The 11-bit Standard Identifier will be used for this message object.
1: The 29-bit Extended Identifier will be used for this message object.
14 Xtd R/W 0x0
Message Direction
0: Receive. On TxRqst, a remote frame with the identifier of this
message object is transmitted. On reception of a data frame with
matching identifier, that message is stored in this message object.
1: Transmit. On TxRqst, the respective message object is transmitted
as a data frame. On reception of a remote frame with matching identifier,
TxRqst bit of this message object is set (if RmtEn=1).
13 Dir R/W 0x0
Message Identifier
Used with the ID bit in the CANIFnARB1 register to create the message
identifier. ID[28:0] is the Extended Frame and ID[28:18] is the Standard
Frame.
12:0 ID R/W 0x0
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Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098
This register holds the control information associated with the message object to be sent to the
Message RAM.
CAN IF1 Message Control (CANIF1MCTL)
CAN0 base: 0x4004.0000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NewDat MsgLst IntPnd UMask TxIE RxIE RmtEn TxRqst EoB reserved DLC
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
New Data
0: No new data has been written into the data portion of this message
object by the message handler since the last time this flag was cleared
by the CPU.
1: The message handler or the CPU has written new data into the data
portion of this message object.
15 NewDat R/W 0x0
Message Lost
0 : No message was lost since the last time this bit was reset by the
CPU.
1: The message handler stored a new message into this object when
NewDat was set; the CPU has lost a message.
This bit is only valid for message objects with the Dir bit in the
CANIFnARB2 register set to 0 (receive).
14 MsgLst R/W 0x0
Interrupt Pending
0: This message object is not the source of an interrupt.
1: This message object is the source of an interrupt. The interrupt
identifier in the CAN Interrupt (CANINT) register will point to this
message object if there is not another interrupt source with a higher
priority.
13 IntPnd R/W 0x0
Use Acceptance Mask
0: Mask ignored.
1: Use mask (Msk, MXtd, and MDir) for acceptance filtering.
12 UMask R/W 0x0
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Bit/Field Name Type Reset Description
Transmit Interrupt Enable
0: The IntPnd bit in the CANIFnMCTL register is unchanged after a
successful transmission of a frame.
1: The IntPnd bit in the CANIFnMCTL register is set after a successful
transmission of a frame.
11 TxIE R/W 0x0
Receive Interrupt Enable
0: The IntPnd bit in the CANIFnMCTL register is unchanged after a
successful reception of a frame.
1: The IntPnd bit in the CANIFnMCTL register is set after a successful
reception of a frame.
10 RxIE R/W 0x0
Remote Enable
0: At the reception of a remote frame, the TxRqst bit in the
CANIFnMCTL register is left unchanged.
1: At the reception of a remote frame, the TxRqst bit in the
CANIFnMCTL register is set.
9 RmtEn R/W 0x0
Transmit Request
0: This message object is not waiting for transmission.
1: The transmission of this message object is requested and is not yet
done.
8 TxRqst R/W 0x0
End of Buffer
0: Message object belongs to a FIFO Buffer and is not the last message
object of that FIFO Buffer.
1: Single message object or last message object of a FIFO Buffer.
This bit is used to concatenate two or more message objects (up to 32)
to build a FIFO buffer. For a single message object (thus not belonging
to a FIFO buffer), this bit must be set to 1.
7 EoB R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:4 reserved RO 0x0
Data Length Code
Value Description
0x0-0x8 Specifies the number of bytes in the data frame.
0x9-0xF Defaults to a data frame with 8 bytes.
The DLC bit in the CANIFnMCTL register of a message object must be
defined the same as in all the corresponding objects with the same
identifier at other nodes. When the message handler stores a data frame,
it writes DLC to the value given by the received message.
3:0 DLC R/W 0x0
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Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8
These registers contain the data to be sent or that has been received. In a CAN data frame, data
byte 0 is the first byte to be transmitted or received and data byte 7 is the last byte to be transmitted
or received. In CAN's serial bit stream, the MSB of each byte is transmitted first.
CAN IF1 Data A1 (CANIF1DA1)
CAN0 base: 0x4004.0000
Offset 0x03C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Data
The CANIFnDA1 registers contain data bytes 1 and 0; CANIFnDA2
data bytes 3 and 2; CANIFnDB1 data bytes 5 and 4; and CANIFnDB2
data bytes 7 and 6.
15:0 Data R/W 0x00
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Controller Area Network (CAN) Module
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104
The CANTXRQ1 and CANTXRQ2 registers hold the TxRqst bits of the 32 message objects. By
reading out these bits, the CPU can check which message object has a transmission request pending.
The TxRqst bit of a specific message object can be changed by three sources: (1) the CPU via the
CAN IFn Message Control (CANIFnMCTL) register, (2) the message handler state machine after
the reception of a remote frame, or (3) the message handler state machine after a successful
transmission.
The CANTXRQ1 register contains the TxRqst bit of the first 16 message objects in the message
RAM; the CANTXRQ2 register contains the TxRqst bit of the second 16 message objects.
CAN Transmission Request 1 (CANTXRQ1)
CAN0 base: 0x4004.0000
Offset 0x100
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxRqst
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Transmission Request Bits
(of all message objects)
0: The message object is not waiting for transmission.
1: The transmission of the message object is requested and is not yet
done.
15:0 TxRqst RO 0x00
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Register 32: CAN New Data 1 (CANNWDA1), offset 0x120
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124
The CANNWDA1 and CANNWDA2 registers hold the NewDat bits of the 32 message objects. By
reading these bits, the CPU can check which message object has its data portion updated. The
NewDat bit of a specific message object can be changed by three sources: (1) the CPU via the
CAN IFn Message Control (CANIFnMCTL) register, (2) the message handler state machine after
the reception of a data frame, or (3) the message handler state machine after a successful
transmission.
The CANNWDA1 register contains the NewDat bit of the first 16 message objects in the message
RAM; the CANNWDA2 register contains the NewDat bit of the second 16 message objects.
CAN New Data 1 (CANNWDA1)
CAN0 base: 0x4004.0000
Offset 0x120
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NewDat
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
New Data Bits
(of all message objects)
0: No new data has been written into the data portion of this message
object by the message handler since the last time this flag was cleared
by the CPU.
1: The message handler or the CPU has written new data into the data
portion of this message object.
15:0 NewDat RO 0x00
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Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144
The CANMSG1INT and CANMSG2INT registers hold the IntPnd bits of the 32 message objects.
By reading these bits, the CPU can check which message object has an interrupt pending. The
IntPnd bit of a specific message object can be changed through two sources: (1) the CPU via the
CAN IFn Message Control (CANIFnMCTL) register, or (2) the message handler state machine
after the reception or transmission of a frame.
This field is also encoded in the CAN Interrupt (CANINT) register.
The CANMSG1INT register contains the IntPnd bit of the first 16 message objects in the message
RAM; the CANMSG2INT register contains the IntPnd bit of the second 16 message objects.
CAN Message 1 Interrupt Pending (CANMSG1INT)
CAN0 base: 0x4004.0000
Offset 0x140
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IntPnd
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Interrupt Pending Bits
(of all message objects)
0: This message object is not the source of an interrupt.
1: This message object is the source of an interrupt.
15:0 IntPnd RO 0x00
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Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164
The CANMSG1VAL and CANMSG2VAL registers hold the MsgVal bits of the 32 message objects.
By reading these bits, the CPU can check which message object is valid. The message value of a
specific message object can be changed with the CAN IFn Message Control (CANIFnMCTL)
register.
The CANMSG1VAL register contains the MsgVal bit of the first 16 message objects in the message
RAM; the CANMSG2VAL register contains the MsgVal bit of the second 16 message objects in
the message RAM.
CAN Message 1 Valid (CANMSG1VAL)
CAN0 base: 0x4004.0000
Offset 0x160
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MsgVal
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Message Valid Bits
(of all message objects)
0: This message object is not configured and is ignored by the message
handler.
1: This message object is configured and should be considered by the
message handler.
15:0 MsgVal RO 0x00
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Controller Area Network (CAN) Module
17 Ethernet Controller
The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and
network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3
specifications and fully supports 10BASE-T and 100BASE-TX standards.
The Ethernet Controller module has the following features:
■ Conforms to the IEEE 802.3-2002 specification
– 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer
interface to the line
– 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler
– Full-featured auto-negotiation
■ Multiple operational modes
– Full- and half-duplex 100 Mbps
– Full- and half-duplex 10 Mbps
– Power-saving and power-down modes
■ Highly configurable
– Programmable MAC address
– LED activity selection
– Promiscuous mode support
– CRC error-rejection control
– User-configurable interrupts
■ Physical media manipulation
– Automatic MDI/MDI-X cross-over correction
– Register-programmable transmit amplitude
– Automatic polarity correction and 10BASE-T signal reception
■ IEEE 1588 Precision Time Protocol
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17.1 Block Diagram
Figure 17-1. Ethernet Controller Block Diagram
MACISR
MACIACK
MACIMR
Interrupt
Control
MACRCR
MACNPR
Receive
Control
MACTCR
MACITHR
MACTRR
Transmit
Control
Transmit
FIFO
Receive
FIFO
MACIAR0
MACIAR1
Individual
Address
MACMDTX
MACMCR
MACMDVR
MACMAR
MACMDRX
MII
Control
MACDR
Data
Access
MACTSR
Timer
Support
TXOP
TXON
RXIP
RXIN
XTLP
XTLN
MDIX
Clock
Reference
Transmit
Encoding
Pulse
Shaping
Receive
Decoding
Clock
Recovery
Auto
Negotiation
Carrier
Sense
MR3
MR0
MR1
MR2
MR4
Media Independent Interface
Management Register Set
MR5
MR18
MR6
MR16
MR17
MR19
MR23
MR24
Collision
Detect System Clock
Interrupt
17.2 Functional Description
As shown in Figure 17-2 on page 450, the Ethernet Controller is functionally divided into two layers
or modules: the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These
correspond to the OSI model layers 2 and 1. The primary interface to the Ethernet Controller is a
simple bus interface to the MAC layer. The MAC layer provides transmit and receive processing for
Ethernet frames. The MAC layer also provides the interface to the PHY module via an internal Media
Independent Interface (MII).
Figure 17-2. Ethernet Controller
Cortex M3
Media Access
Controller
MAC
(Layer 2)
Physical
Layer Entity
PHY
(Layer 1)
Magnetics RJ45
Ethernet Controller
17.2.1 Internal MII Operation
For the MII management interface to function properly, the MDIO signal must be connected through
a 10k Ω pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor prevents
management transactions on this internal MII to function. Note that it is possible for data transmission
across the MII to still function since the PHY layer auto-negotiates the link parameters by default.
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Ethernet Controller
For the MII management interface to function properly, the internal clock must be divided down from
the system clock to a frequency no greater than 2.5 MHz. The MACMDV register contains the divider
used for scaling down the system clock. See page 470 for more details about the use of this register.
17.2.2 PHY Configuration/Operation
The Physical Layer (PHY) in the Ethernet Controller includes integrated ENDECs,
scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions.
The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an
adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery.
The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX
applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The
Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external
filter is required.
17.2.2.1 Clock Selection
The PHY has an on-chip crystal oscillator which can also be driven by an external oscillator. In this
mode of operation, a 25-MHz crystal should be connected between the XTALPPHY and XTALNPHY
pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY pin. In this
mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground.
17.2.2.2 Auto-Negotiation
The PHY supports the auto-negotiation functions of Clause 28 of the IEEE 802.3 standard for 10/100
Mbps operation over copper wiring. This function can be enabled via register settings. The
auto-negotiation function defaults to On and the ANEGEN bit in the MR0 register is High after reset.
Software can disable the auto-negotiation function by writing to the ANEGEN bit. The contents of the
MR4 register are sent to the PHY’s link partner during auto-negotiation via fast-link pulse coding.
Once auto-negotiation is complete, the DPLX and RATE bits in the MR18 register reflect the actual
speed and duplex that was chosen. If auto-negotiation fails to establish a link for any reason, the
ANEGF bit in the MR18 register reflects this and auto-negotiation restarts from the beginning. Writing
a 1 to the RANEG bit in the MR0 register also causes auto-negotiation to restart.
17.2.2.3 Polarity Correction
The PHY is capable of either automatic or manual polarity reversal for 10BASE-T and auto-negotiation
functions. Bits 4 and 5 (RVSPOL and APOL) in the MR16 register control this feature. The default is
automatic mode, where APOL is Low and RVSPOL indicates if the detection circuitry has inverted
the input signal. To enter manual mode, APOL should be set High and RVSPOL then controls the
signal polarity.
17.2.2.4 MDI/MDI-X Configuration
The PHY supports the automatic MDI/MDI-X configuration as defined in IEEE 802.3-2002
specification. This eliminates the need for cross-over cables when connecting to another device,
such as a hub. The algorithm is controlled via settings in the MR24 register. Refer to page 493 for
additional details about these settings.
17.2.2.5 LED Indicators
The PHY supports two LED signals that can be used to indicate various states of operation of the
Ethernet Controller. These signals are mapped to the LED0 and LED1 pins. By default, these pins
are configured as GPIO signals (PF3 and PF2). For the PHY layer to drive these signals, they must
be reconfigured to their hardware function. See “General-Purpose Input/Outputs (GPIOs)” on page
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162 for additional details. The function of these pins is programmable via the PHY layer MR23 register.
Refer to page 492 for additonal details on how to program these LED functions.
17.2.3 MAC Configuration/Operation
17.2.3.1 Ethernet Frame Format
Ethernet data is carried by Ethernet frames. The basic frame format is shown in Figure
17-3 on page 452.
Figure 17-3. Ethernet Frame
Preamble SFD Destination Address Source Address Length/
Type Data FCS
7
Bytes
6
Bytes
6
Bytes
2
Bytes
1
Byte
4
Bytes
46 - 1500
Bytes
The seven fields of the frame are transmitted from left to right. The bits within the frame are
transmitted from least to most significant bit.
■ Preamble
The Preamble field is used by the physical layer signaling circuitry to synchronize with the received
frame’s timing. The preamble is 7 octets long.
■ Start Frame Delimiter (SFD)
The SFD field follows the preamble pattern and indicates the start of the frame. Its value is
1010.1011.
■ Destination Address (DA)
This field specifies destination addresses for which the frame is intended. The LSB of the DA
determines whether the address is an individual (0), or group/multicast (1) address.
■ Source Address (SA)
The source address field identifies the station from which the frame was initiated.
■ Length/Type Field
The meaning of this field depends on its numeric value. The first of two octets is most significant.
This field can be interpreted as length or type code. The maximum length of the data field is
1500 octets. If the value of the Length/Type field is less than or equal to 1500 decimal, it indicates
the number of MAC client data octets. If the value of this field is greater than or equal to 1536
decimal, then it is type interpretation. The meaning of the Length/Type field when the value is
between 1500 and 1536 decimal is unspecified by the standard. The MAC module assumes
type interpretation if the value of the Length/Type field is greater than 1500 decimal.
■ Data
The data field is a sequence of 0 to 1500 octets. Full data transparency is provided so any values
can appear in this field. A minimum frame size is required to properly meet the IEEE standard.
If necessary, the data field is extended by appending extra bits (a pad). The pad field can have
a size of 0 to 46 octets. The sum of the data and pad lengths must be a minimum of 46 octets.
The MAC module automatically inserts pads if required, though it can be disabled by a register
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Ethernet Controller
write. For the MAC module core, data sent/received can be larger than 1500 bytes, and no Frame
Too Long error is reported. Instead, a FIFO Overrun error is reported when the frame received
is too large to fit into the Ethernet Controller’s RAM.
■ Frame Check Sequence (FCS)
The frame check sequence carries the cyclic redundancy check (CRC) value. The value of this
field is computed over destination address, source address, length/type, data, and pad fields
using the CRC-32 algorithm. The MAC module computes the FCS value one nibble at a time.
For transmitted frames, this field is automatically inserted by the MAC layer, unless disabled by
the CRC bit in the MACTCTL register. For received frames, this field is automatically checked.
If the FCS does not pass, the frame is not placed in the RX FIFO, unless the FCS check is
disabled by the BADCRC bit in the MACRCTL register.
17.2.3.2 MAC Layer FIFOs
For Ethernet frame transmission, a 2 KB TX FIFO is provided that can be used to store a single
frame. While the IEEE 802.3 specification limits the size of an Ethernet frame's payload section to
1500 Bytes, the Ethernet Controller places no such limit. The full buffer can be used, for a payload
of up to 2032 bytes.
For Ethernet frame reception, a 2-KB RX FIFO is provided that can be used to store multiple frames,
up to a maximum of 31 frames. If a frame is received and there is insufficient space in the RX FIFO,
an overflow error is indicated.
For details regarding the TX and RX FIFO layout, refer to Table 17-1 on page 453. Please note the
following difference between TX and RX FIFO layout. For the TX FIFO, the Data Length field in the
first FIFO word refers to the Ethernet frame data payload, as shown in the 5th to nth FIFO positions.
For the RX FIFO, the Frame Length field is the total length of the received Ethernet frame, including
the FCS and Frame Length bytes. Also note that if FCS generation is disabled with the CRC bit in
the MACTCTL register, the last word in the FIFO must be the FCS bytes for the frame that has been
written to the FIFO.
Also note that if the length of the data payload section is not a multiple of 4, the FCS field overlaps
words in the FIFO. However, for the RX FIFO, the beginning of the next frame is always on a word
boundary.
Table 17-1. TX & RX FIFO Organization
FIFO Word Read/Write Word Bit Fields TX FIFO (Write) RX FIFO (Read)
Sequence
1st 7:0 Data Length LSB Frame Length LSB
15:8 Data Length MSB Frame Length MSB
23:16 DA oct 1
31:24 DA oct 2
2nd 7:0 DA oct 3
15:8 DA oct 4
23:16 DA oct 5
31:24 DA oct 6
3rd 7:0 SA oct 1
15:8 SA oct 2
23:16 SA oct 3
31:24 SA oct 4
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FIFO Word Read/Write Word Bit Fields TX FIFO (Write) RX FIFO (Read)
Sequence
4th 7:0 SA oct 5
15:8 SA oct 6
23:16 Len/Type MSB
31:24 Len/Type LSB
5th to nth 7:0 data oct n
15:8 data oct n+1
23:16 data oct n+2
31:24 data oct n+3
FCS 1 (if the CRC bit in FCS 1
MACCTL is 0)
last 7:0
FCS 2 (if the CRC bit in FCS 2
MACCTL is 0)
15:8
FCS 3 (if the CRC bit in FCS 3
MACCTL is 0)
23:16
FCS 4 (if the CRC bit in FCS 4
MACCTL is 0)
31:24
17.2.3.3 Ethernet Transmission Options
The Ethernet Controller can automatically generate and insert the Frame Check Sequence (FCS)
at the end of the transmit frame. This is controlled by the CRC bit in the MACTCTL register. For test
purposes, in order to generate a frame with an invalid CRC, this feature can be disabled.
The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46
bytes. The Ethernet Controller can be configured to automatically pad the data section if the payload
data section loaded into the FIFO is less than the minimum 46 bytes. This feature is controlled by
the PADEN bit in the MACTCTL register.
At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation
by using the DUPLEX bit in the MACTCTL register.
17.2.3.4 Ethernet Reception Options
Using the BADCRC bit in the MACRCTL register, the Ethernet Controller can be configured to reject
incoming Ethernet frames with an invalid FCS field.
The Ethernet receiver can also be configured for Promiscuous and Multicast modes using the PRMS
and AMUL fields in the MACRCTL register. If these modes are not enabled, only Ethernet frames
with a broadcast address, or frames matching the MAC address programmed into the MACIA0 and
MACIA1 register is placed into the RX FIFO.
17.2.3.5 Packet Timestamps
Using the TSEN bit in the MACTS register, the MAC transmit and receive interrupts can be used to
trigger edge capture events on General-Purpose Timer 3. The transmit interrupt is routed to the
CCP (even) input of General-Purpose Timer 3, while the receive interrupt is routed to the CCP (odd)
input of General-Purpose Timer 3. This timer can then be configured in 16-bit edge capture mode
and be used with a third 16-bit free-running timer to capture a more accurate timestamp for the
transmit or receive packet. This feature can be used with a protocol such as IEEE-1588 to provide
more accurate timestamps of the synchronization packets, improving the overall accuracy of the
protocol.
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17.2.4 Interrupts
The Ethernet Controller can generate an interrupt for one or more of the following conditions:
■ A frame has been received into an empty RX FIFO
■ A frame transmission error has occurred
■ A frame has been transmitted successfully
■ A frame has been received with no room in the RX FIFO (overrun)
■ A frame has been received with one or more error conditions (for example, FCS failed)
■ An MII management transaction between the MAC and PHY layers has completed
■ One or more of the following PHY layer conditions occurs:
– Auto-Negotiate Complete
– Remote Fault
– Link Status Change
– Link Partner Acknowledge
– Parallel Detect Fault
– Page Received
– Receive Error
– Jabber Event Detected
17.3 Initialization and Configuration
To use the Ethernet Controller, the peripheral must be enabled by setting the EPHY0 and EMAC0
bits in the RCGC2 register. The following steps can then be used to configure the Ethernet Controller
for basic operation.
1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming
a 20-MHz system clock, the MACDIV value would be 4.
2. Program the MACIA0 and MACIA1 register for address filtering.
3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation
using a value of 0x16.
4. Program the MACRCTL register to reject frames with bad FCS using a value of 0x08.
5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and
MACRCTL registers.
6. To transmit a frame, write the frame into the TX FIFO using the MACDATA register. Then set
the NEWTX bit in the MACTR register to initiate the transmit process. When the NEWTX bit has
been cleared, the TX FIFO is available for the next transmit frame.
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7. To receive a frame, wait for the NPR field in the MACNP register to be non-zero. Then begin
reading the frame from the RX FIFO by using the MACDATA register. When the frame (including
the FCS field) has been read, the NPR field should decrement by one. When there are no more
frames in the RX FIFO, the NPR field reads 0.
17.4 Ethernet Register Map
Table 17-2 on page 456 lists the Ethernet MAC registers. All addresses given are relative to the
Ethernet MAC base address of 0x4004.8000.
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY.
The registers are collectively known as the MII Management registers and are detailed in Section
22.2.4 of the IEEE 802.3 specification. Table 17-2 on page 456 also lists these MII Management
registers. All addresses given are absolute and are written directly to the REGADR field of the
MACMCTL register. The format of registers 0 to 15 are defined by the IEEE specification and are
common to all PHY implementations. The only variance allowed is for features that may or may not
be supported by a specific PHY. Registers 16 to 31 are vendor-specific registers, used to support
features that are specific to a vendors PHY implementation. Vendor-specific registers not listed are
reserved.
Table 17-2. Ethernet Register Map
See
Offset Name Type Reset Description page
Ethernet MAC
0x000 MACRIS RO 0x0000.0000 Ethernet MAC Raw Interrupt Status 458
0x000 MACIACK W1C 0x0000.0000 Ethernet MAC Interrupt Acknowledge 460
0x004 MACIM R/W 0x0000.007F Ethernet MAC Interrupt Mask 461
0x008 MACRCTL R/W 0x0000.0008 Ethernet MAC Receive Control 462
0x00C MACTCTL R/W 0x0000.0000 Ethernet MAC Transmit Control 463
0x010 MACDATA R/W 0x0000.0000 Ethernet MAC Data 464
0x014 MACIA0 R/W 0x0000.0000 Ethernet MAC Individual Address 0 466
0x018 MACIA1 R/W 0x0000.0000 Ethernet MAC Individual Address 1 467
0x01C MACTHR R/W 0x0000.003F Ethernet MAC Threshold 468
0x020 MACMCTL R/W 0x0000.0000 Ethernet MAC Management Control 469
0x024 MACMDV R/W 0x0000.0080 Ethernet MAC Management Divider 470
0x02C MACMTXD R/W 0x0000.0000 Ethernet MAC Management Transmit Data 471
0x030 MACMRXD R/W 0x0000.0000 Ethernet MAC Management Receive Data 472
0x034 MACNP RO 0x0000.0000 Ethernet MAC Number of Packets 473
0x038 MACTR R/W 0x0000.0000 Ethernet MAC Transmission Request 474
0x03C MACTS R/W 0x0000.0000 Ethernet MAC Timer Support 475
MII Management
- MR0 R/W 0x3100 Ethernet PHY Management Register 0 – Control 476
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See
Offset Name Type Reset Description page
- MR1 RO 0x7849 Ethernet PHY Management Register 1 – Status 478
Ethernet PHY Management Register 2 – PHY Identifier 480
- MR2 RO 0x000E 1
Ethernet PHY Management Register 3 – PHY Identifier 481
- MR3 RO 0x7237 2
Ethernet PHYManagement Register 4 – Auto-Negotiation 482
- MR4 R/W 0x01E1 Advertisement
Ethernet PHYManagement Register 5 – Auto-Negotiation 484
- MR5 RO 0x0000 Link Partner Base Page Ability
Ethernet PHYManagement Register 6 – Auto-Negotiation 485
- MR6 RO 0x0000 Expansion
Ethernet PHY Management Register 16 – 486
- MR16 R/W 0x0140 Vendor-Specific
Ethernet PHY Management Register 17 – Interrupt 488
- MR17 R/W 0x0000 Control/Status
- MR18 RO 0x0000 Ethernet PHY Management Register 18 – Diagnostic 490
Ethernet PHY Management Register 19 – Transceiver 491
- MR19 R/W 0x4000 Control
Ethernet PHY Management Register 23 – LED 492
- MR23 R/W 0x0010 Configuration
Ethernet PHY Management Register 24 –MDI/MDIX 493
- MR24 R/W 0x00C0 Control
17.5 Ethernet MAC Register Descriptions
The remainder of this section lists and describes the Ethernet MAC registers, in numerical order by
address offset. Also see “MII Management Register Descriptions” on page 475.
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Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000
The MACRIS register is the interrupt status register. On a read, this register gives the current status
value of the corresponding interrupt prior to masking.
Ethernet MAC Raw Interrupt Status (MACRIS)
Base 0x4004.8000
Offset 0x000
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PHYINT MDINT RXER FOV TXEMP TXER RXINT
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x0
PHY Interrupt
When set, indicates that an enabled interrupt in the PHY layer has
occured. MR17 in the PHY must be read to determine the specific PHY
event that triggered this interrupt.
6 PHYINT RO 0x0
MII Transaction Complete
When set, indicates that a transaction (read or write) on the MII interface
has completed successfully.
5 MDINT RO 0x0
Receive Error
This bit indicates that an error was encountered on the receiver. The
possible errors that can cause this interrupt bit to be set are:
■ A receive error occurs during the reception of a frame (100 Mb/s
only).
■ The frame is not an integer number of bytes (dribble bits) due to an
alignment error.
■ The CRC of the frame does not pass the FCS check.
■ The length/type field is inconsistent with the frame data size when
interpreted as a length field.
4 RXER RO 0x0
FIFO Overrrun
When set, indicates that an overrun was encountered on the receive
FIFO.
3 FOV RO 0x0
Transmit FIFO Empty
When set, indicates that the packet was transmitted and that the TX
FIFO is empty.
2 TXEMP RO 0x0
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Bit/Field Name Type Reset Description
Transmit Error
When set, indicates that an error was encountered on the transmitter.
The possible errors that can cause this interrupt bit to be set are:
■ The data length field stored in the TX FIFO exceeds 2032. The
frame is not sent when this error occurs.
■ The retransmission attempts during the backoff process have
exceeded the maximum limit of 16.
1 TXER RO 0x0
Packet Received
When set, indicates that at least one packet has been received and is
stored in the receiver FIFO.
0 RXINT RO 0x0
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Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000
A write of a 1 to any bit position of this register clears the corresponding interrupt bit in the Ethernet
MAC Raw Interrupt Status (MACRIS) register.
Ethernet MAC Interrupt Acknowledge (MACIACK)
Base 0x4004.8000
Offset 0x000
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PHYINT MDINT RXER FOV TXEMP TXER RXINT
Type RO RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x0
Clear PHY Interrupt
A write of a 1 clears the PHYINT interrupt read from the MACRIS
register.
6 PHYINT W1C 0x0
Clear MII Transaction Complete
A write of a 1 clears the MDINT interrupt read from the MACRIS register.
5 MDINT W1C 0x0
Clear Receive Error
A write of a 1 clears the RXER interrupt read from the MACRIS register.
4 RXER W1C 0x0
Clear FIFO Overrun
A write of a 1 clears the FOV interrupt read from the MACRIS register.
3 FOV W1C 0x0
Clear Transmit FIFO Empty
A write of a 1 clears the TXEMP interrupt read from the MACRIS register.
2 TXEMP W1C 0x0
Clear Transmit Error
A write of a 1 clears the TXER interrupt read from the MACRIS register
and resets the TX FIFO write pointer.
1 TXER W1C 0x0
Clear Packet Received
A write of a 1 clears the RXINT interrupt read from the MACRIS register.
0 RXINT W1C 0x0
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Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004
This register allows software to enable/disable Ethernet MAC interrupts. Writing a 0 disables the
interrupt, while writing a 1 enables it.
Ethernet MAC Interrupt Mask (MACIM)
Base 0x4004.8000
Offset 0x004
Type R/W, reset 0x0000.007F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PHYINTM MDINTM RXERM FOVM TXEMPM TXERM RXINTM
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x0
Mask PHY Interrupt
This bit masks the PHYINT bit in the MACRIS register from being
asserted.
6 PHYINTM R/W 1
Mask MII Transaction Complete
This bit masks the MDINT bit in the MACRIS register from being
asserted.
5 MDINTM R/W 1
Mask Receive Error
This bit masks the RXER bit in the MACRIS register from being asserted.
4 RXERM R/W 1
Mask FIFO Overrrun
This bit masks the FOV bit in the MACRIS register from being asserted.
3 FOVM R/W 1
Mask Transmit FIFO Empty
This bit masks the TXEMP bit in the MACRIS register from being
asserted.
2 TXEMPM R/W 1
Mask Transmit Error
This bit masks the TXER bit in the MACRIS register from being asserted.
1 TXERM R/W 1
Mask Packet Received
This bit masks the RXINT bit in the MACRIS register from being
asserted.
0 RXINTM R/W 1
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Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008
This register enables software to configure the receive module and control the types of frames that
are received from the physical medium. It is important to note that when the receive module is
enabled, all valid frames with a broadcast address of FF-FF-FF-FF-FF-FF in the Destination Address
field is received and stored in the RX FIFO, even if the AMUL bit is not set.
Ethernet MAC Receive Control (MACRCTL)
Base 0x4004.8000
Offset 0x008
Type R/W, reset 0x0000.0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RSTFIFO BADCRC PRMS AMUL RXEN
Type RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 reserved RO 0x0
Clear Receive FIFO
When set, clears the receive FIFO. This should be done when software
initialization is performed.
It is recommended that the receiver be disabled (RXEN = 0), and then
the reset initiated (RSTFIFO = 1). This sequence flushes and resets the
RX FIFO.
4 RSTFIFO R/W 0x0
Enable Reject Bad CRC
The BADCRC bit enables the rejection of frames with an incorrectly
calculated CRC.
3 BADCRC R/W 0x1
Enable Promiscuous Mode
The PRMS bit enables Promiscuous mode, which accepts all valid frames,
regardless of the Destination Address.
2 PRMS R/W 0x0
Enable Multicast Frames
The AMUL bit enables the reception of multicast frames from the physical
medium.
1 AMUL R/W 0x0
Enable Receiver
The RXEN bit enables the Ethernet receiver. When this bit is Low, the
receiver is disabled and all frames on the physical medium are ignored.
0 RXEN R/W 0x0
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Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C
This register enables software to configure the transmit module, and control frames are placed onto
the physical medium.
Ethernet MAC Transmit Control (MACTCTL)
Base 0x4004.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DUPLEX reserved CRC PADEN TXEN
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 reserved RO 0x0
Enable Duplex Mode
When set, enables Duplex mode, allowing simultaneous transmission
and reception.
4 DUPLEX R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0x0
Enable CRC Generation
When set, enables the automatic generation of the CRC and the
placement at the end of the packet. If this bit is not set, the frames placed
in the TX FIFO are sent exactly as they are written into the FIFO.
2 CRC R/W 0x0
Enable Packet Padding
When set, enables the automatic padding of packets that do not meet
the minimum frame size.
1 PADEN R/W 0x0
Enable Transmitter
When set, enables the transmitter. When this bit is 0, the transmitter is
disabled.
0 TXEN R/W 0x0
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Register 6: Ethernet MAC Data (MACDATA), offset 0x010
This register enables software to access the TX and RX FIFOs.
Reads from this register return the data stored in the RX FIFO from the location indicated by the
read pointer.
Writes to this register store the data in the TX FIFO at the location indicated by the write pointer.
The write pointer is then auto-incremented to the next TX FIFO location.
There is no mechanism for randomly accessing bytes in either the RX or TX FIFOs. Data must be
read from the RX FIFO sequentially and stored in a buffer for further processing. Once a read has
been performed, the data in the FIFO cannot be re-read. Data must be written to the TX FIFO
sequentially. If an error is made in placing the frame into the TX FIFO, the write pointer can be reset
to the start of the TX FIFO by writing the TXER bit of the MACIACK register and then the data
re-written.
Read-Only Register
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDATA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Receive FIFO Data
The RXDATA bits represent the next four bytes of data stored in the RX
FIFO.
31:0 RXDATA RO 0x0
Write-Only Register
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDATA
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit/Field Name Type Reset Description
Transmit FIFO Data
The TXDATA bits represent the next four bytes of data to place in the
TX FIFO for transmission.
31:0 TXDATA WO 0x0
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Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014
This register enables software to program the first four bytes of the hardware MAC address of the
Network Interface Card (NIC). (The last two bytes are in MACIA1). The 6-byte IAR is compared
against the incoming Destination Address fields to determine whether the frame should be received.
Ethernet MAC Individual Address 0 (MACIA0)
Base 0x4004.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MACOCT4 MACOCT3
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACOCT2 MACOCT1
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
MAC Address Octet 4
The MACOCT4 bits represent the fourth octet of the MAC address used
to uniquely identify each Ethernet Controller.
31:24 MACOCT4 R/W 0x0
MAC Address Octet 3
The MACOCT3 bits represent the third octet of the MAC address used
to uniquely identify each Ethernet Controller.
23:16 MACOCT3 R/W 0x0
MAC Address Octet 2
The MACOCT2 bits represent the second octet of the MAC address used
to uniquely identify each Ethernet Controller.
15:8 MACOCT2 R/W 0x0
MAC Address Octet 1
The MACOCT1 bits represent the first octet of the MAC address used to
uniquely identify each Ethernet Controller.
7:0 MACOCT1 R/W 0x0
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Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018
This register enables software to program the last two bytes of the hardware MAC address of the
Network Interface Card (NIC). (The first four bytes are in MACIA0). The 6-byte IAR is compared
against the incoming Destination Address fields to determine whether the frame should be received.
Ethernet MAC Individual Address 1 (MACIA1)
Base 0x4004.8000
Offset 0x018
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACOCT6 MACOCT5
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0
MAC Address Octet 6
The MACOCT6 bits represent the sixth octet of the MAC address used
to uniquely identify each Ethernet Controller.
15:8 MACOCT6 R/W 0x0
MAC Address Octet 5
The MACOCT5 bits represent the fifth octet of the MAC address used to
uniquely identify each Ethernet Controller.
7:0 MACOCT5 R/W 0x0
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Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C
This register enables software to set the threshold level at which the transmission of the frame
begins. If the THRESH bits are set to 0x3F, which is the reset value, transmission does not start until
the NEWTX bit is set in the MACTR register. This effectively disables the early transmission feature.
Writing the THRESH bits to any value besides all 1s enables the early transmission feature. Once
the byte count of data in the TX FIFO reaches this level, transmission of the frame begins. When
THRESH is set to all 0s, transmission of the frame begins after 4 bytes (a single write) are stored in
the TX FIFO. Each increment of the THRESH bit field waits for an additional 32 bytes of data (eight
writes) to be stored in the TX FIFO. Therefore, a value of 0x01 would wait for 36 bytes of data to
be written while a value of 0x02 would wait for 68 bytes to be written. In general, early transmission
starts when:
Number of Bytes >= 4 (THRESH x 8 + 1)
Reaching the threshold level has the same effect as setting the NEWTX bit in the MACTR register.
Transmission of the frame begins and then the number of bytes indicated by the Data Length field
is sent out on the physical medium. Because under-run checking is not performed, it is possible
that the tail pointer may reach and pass the write pointer in the TX FIFO. This causes indeterminate
values to be written to the physical medium rather than the end of the frame. Therefore, sufficient
bus bandwidth for writing to the TX FIFO must be guaranteed by the software.
If a frame smaller than the threshold level needs to be sent, the NEWTX bit in the MACTR register
must be set with an explicit write. This initiates the transmission of the frame even though the
threshold limit has not been reached.
If the threshold level is set too small, it is possible for the transmitter to underrun. If this occurs, the
transmit frame is aborted, and a transmit error occurs.
Ethernet MAC Threshold (MACTHR)
Base 0x4004.8000
Offset 0x01C
Type R/W, reset 0x0000.003F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved THRESH
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x0
Threshold Value
The THRESH bits represent the early transmit threshold. Once the amount
of data in the TX FIFO exceeds this value, transmission of the packet
begins.
5:0 THRESH R/W 0x3F
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Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020
This register enables software to control the transfer of data to and from the MII Management
registers in the Ethernet PHY. The address, name, type, reset configuration, and functional description
of each of these registers can be found in Table 17-2 on page 456 and in “MII Management Register
Descriptions” on page 475.
In order to initiate a read transaction from the MII Management registers, the WRITE bit must be
written with a 0 during the same cycle that the START bit is written with a 1.
In order to initiate a write transaction to the MII Management registers, the WRITE bit must be written
with a 1 during the same cycle that the START bit is written with a 1.
Ethernet MAC Management Control (MACMCTL)
Base 0x4004.8000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved REGADR reserved WRITE START
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0
MII Register Address
The REGADR bit field represents the MII Management register address
for the next MII management interface transaction.
7:3 REGADR R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2 reserved RO 0x0
MII Register Transaction Type
The WRITE bit represents the operation of the next MII management
interface transaction. If WRITE is set, the next operation is a write;
otherwise, it is a read.
1 WRITE R/W 0x0
MII Register Transaction Enable
The START bit represents the initiation of the next MII management
interface transaction. When a 1 is written to this bit, the MII register
located at REGADR is read (WRITE=0) or written (WRITE=1).
0 START R/W 0x0
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Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024
This register enables software to set the clock divider for the Management Data Clock (MDC). This
clock is used to synchronize read and write transactions between the system and the MII Management
registers. The frequency of the MDC clock can be calculated from the following formula:
Fmdc = Fipclk / (2 * (MACMDVR + 1 ))
The clock divider must be written with a value that ensures that the MDC clock does not exceed a
frequency of 2.5 MHz.
Ethernet MAC Management Divider (MACMDV)
Base 0x4004.8000
Offset 0x024
Type R/W, reset 0x0000.0080
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DIV
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0
Clock Divider
The DIV bits are used to set the clock divider for the MDC clock used
to transmit data between the MAC and PHY over the serial MII interface.
7:0 DIV R/W 0x80
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Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset
0x02C
This register holds the next value to be written to the MII Management registers.
Ethernet MAC Management Transmit Data (MACMTXD)
Base 0x4004.8000
Offset 0x02C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDTX
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0
MII Register Transmit Data
The MDTX bits represent the data that will be written in the next MII
management transaction.
15:0 MDTX R/W 0x0
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Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset
0x030
This register holds the last value read from the MII Management registers.
Ethernet MAC Management Receive Data (MACMRXD)
Base 0x4004.8000
Offset 0x030
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDRX
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0
MII Register Receive Data
The MDRX bits represent the data that was read in the previous MII
management transaction.
15:0 MDRX R/W 0x0
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Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034
This register holds the number of frames that are currently in the RX FIFO. When NPR is 0, there
are no frames in the RX FIFO and the RXINT bit is not set. When NPR is any other value, there is
at least one frame in the RX FIFO and the RXINT bit in the MACRIS register is set.
Ethernet MAC Number of Packets (MACNP)
Base 0x4004.8000
Offset 0x034
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved NPR
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x0
Number of Packets in Receive FIFO
The NPR bits represent the number of packets stored in the RX FIFO.
While the NPR field is greater than 0, the RXINT interrupt in the MACRIS
register is asserted.
5:0 NPR RO 0x0
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Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038
This register enables software to initiate the transmission of the frame currently located in the TX
FIFO to the physical medium. Once the frame has been transmitted to the medium from the TX
FIFO or a transmission error has been encountered, the NEWTX bit is auto-cleared by the hardware.
Ethernet MAC Transmission Request (MACTR)
Base 0x4004.8000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved NEWTX
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x0
New Transmission
When set, the NEWTX bit initiates an Ethernet transmission once the
packet has been placed in the TX FIFO. This bit is cleared once the
transmission has been completed. If early transmission is being used
(see the MACTHR register), this bit does not need to be set.
0 NEWTX R/W 0x0
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Register 16: Ethernet MAC Timer Support (MACTS), offset 0x03C
This register enables software to enable timer support on the transmission and reception of frames.
This register is only applicable for devices that have 1588 hardware support; for all others, a read
returns 0s.
Ethernet MAC Timer Support (MACTS)
Base 0x4004.8000
Offset 0x03C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TSEN
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x0
Time Stamp Enable
When set, the TSEN bit multiplexes the TX and RX interrupts to the CCP
inputs of General-Purpose Timer 3.
0 TSEN R/W 0x0
17.6 MII Management Register Descriptions
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY.
The registers are collectively known as the MII Management registers. All addresses given are
absolute. Addresses not listed are reserved. Also see “Ethernet MAC Register
Descriptions” on page 457.
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Register 17: Ethernet PHY Management Register 0 – Control (MR0), address
0x00
This register enables software to configure the operation of the PHY. The default settings of these
registers are designed to initialize the PHY to a normal operational mode without configuration.
Ethernet PHY Management Register 0 – Control (MR0)
Base 0x4004.8000
Address 0x00
Type R/W, reset 0x3100
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT reserved
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Reset Registers
When set, resets the registers to their default state and reinitializes
internal state machines. Once the reset operation has completed, this
bit is cleared by hardware.
15 RESET R/W 0
Loopback Mode
When set, enables the Loopback mode of operation. The receive circuitry
is isolated from the physical medium and transmissions are sent back
through the receive circuitry instead of the medium.
14 LOOPBK R/W 0
Speed Select
Value Description
1 Enables the 100 Mb/s mode of operation (100BASE-TX).
0 Enables the 10 Mb/s mode of operation (10BASE-T).
13 SPEEDSL R/W 1
Auto-Negotiation Enable
When set, enables the Auto-Negotiation process.
12 ANEGEN R/W 1
Power Down
When set, places the PHY into a low-power consuming state.
11 PWRDN R/W 0
Isolate
When set, isolates transmit and receive data paths and ignores all
signaling on these buses.
10 ISO R/W 0
Restart Auto-Negotiation
When set, restarts the Auto-Negotiation process. Once the restart has
initiated, this bit is cleared by hardware.
9 RANEG R/W 0
Set Duplex Mode
Value Description
Enables the Full-Duplex mode of operation. This bit can be
set by software in a manual configuration process or by the
Auto-Negotiation process.
1
0 Enables the Half-Duplex mode of operation.
8 DUPLEX R/W 1
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Bit/Field Name Type Reset Description
Collision Test
When set, enables the Collision Test mode of operation. The COLT bit
asserts after the initiation of a transmission and de-asserts once the
transmission is halted.
7 COLT R/W 0
6:0 reserved R/W 0x00 Write as 0, ignore on read.
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Register 18: Ethernet PHY Management Register 1 – Status (MR1), address
0x01
This register enables software to determine the capabilities of the PHY and perform its initialization
and operation appropriately.
Ethernet PHY Management Register 1 – Status (MR1)
Base 0x4004.8000
Address 0x01
Type RO, reset 0x7849
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved 100X_F 100X_H 10T_F 10T_H reserved MFPS ANEGC RFAULT ANEGA LINK JAB EXTD
Type RO RO RO RO RO RO RO RO RO RO RO RC RO RO RC RO
Reset 0 1 1 1 1 0 0 0 0 1 0 0 1 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15 reserved RO 0
100BASE-TX Full-Duplex Mode
When set, indicates that the PHY is capable of supporting 100BASE-TX
Full-Duplex mode.
14 100X_F RO 1
100BASE-TX Half-Duplex Mode
When set, indicates that the PHY is capable of supporting 100BASE-TX
Half-Duplex mode.
13 100X_H RO 1
10BASE-T Full-Duplex Mode
When set, indicates that the PHY is capable of 10BASE-T Full-Duplex
mode.
12 10T_F RO 1
10BASE-T Half-Duplex Mode
When set, indicates that the PHY is capable of supporting 10BASE-T
Half-Duplex mode.
11 10T_H RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10:7 reserved RO 0
Management Frames with Preamble Suppressed
When set, indicates that the Management Interface is capable of
receiving management frames with the preamble suppressed.
6 MFPS RO 1
Auto-Negotiation Complete
When set, indicates that the Auto-Negotiation process has been
completed and that the extended registers defined by the
Auto-Negotiation protocol are valid.
5 ANEGC RO 0
Remote Fault
When set, indicates that a remote fault condition has been detected.
This bit remains set until it is read, even if the condition no longer exists.
4 RFAULT RC 0
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Bit/Field Name Type Reset Description
Auto-Negotiation
When set, indicates that the PHY has the ability to perform
Auto-Negotiation.
3 ANEGA RO 1
Link Made
When set, indicates that a valid link has been established by the PHY.
2 LINK RO 0
Jabber Condition
When set, indicates that a jabber condition has been detected by the
PHY. This bit remains set until it is read, even if the jabber condition no
longer exists.
1 JAB RC 0
Extended Capabilities
When set, indicates that the PHY provides an extended set of capabilities
that can be accessed through the extended register set.
0 EXTD RO 1
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Register 19: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2),
address 0x02
This register, along with MR3, provides a 32-bit value indicating the manufacturer, model, and
revision information.
Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2)
Base 0x4004.8000
Address 0x02
Type RO, reset 0x000E
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUI[21:6]
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
Bit/Field Name Type Reset Description
Organizationally Unique Identifier[21:6]
This field, along with the OUI[5:0] field in MR3, makes up the
Organizationally Unique Identifier indicating the PHY manufacturer.
15:0 OUI[21:6] RO 0x000E
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Register 20: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3),
address 0x03
This register, along with MR2, provides a 32-bit value indicating the manufacturer, model, and
revision information.
Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3)
Base 0x4004.8000
Address 0x03
Type RO, reset 0x7237
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUI[5:0] MN RN
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1
Bit/Field Name Type Reset Description
Organizationally Unique Identifier[5:0]
This field, along with the OUI[21:6] field in MR2, makes up the
Organizationally Unique Identifier indicating the PHY manufacturer.
15:10 OUI[5:0] RO 0x1C
Model Number
The MN field represents the Model Number of the PHY.
9:4 MN RO 0x23
Revision Number
The RN field represents the Revision Number of the PHY.
3:0 RN RO 0x7
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Register 21: Ethernet PHY Management Register 4 – Auto-Negotiation
Advertisement (MR4), address 0x04
This register provides the advertised abilities of the PHY used during Auto-Negotiation. Bits 8:5
represent the Technology Ability Field bits. This field can be overwritten by software to Auto-Negotiate
to an alternate common technology. Writing to this register has no effect until Auto-Negotiation is
re-initiated.
Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4)
Base 0x4004.8000
Address 0x04
Type R/W, reset 0x01E1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NP reserved RF reserved A3 A2 A1 A0 S[4:0]
Type RO RO R/W RO RO RO RO R/W R/W R/W R/W RO RO RO RO RO
Reset 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1
Bit/Field Name Type Reset Description
Next Page
When set, indicates the PHY is capable of Next Page exchanges to
provide more detailed information on the PHY’s capabilities.
15 NP RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14 reserved RO 0
Remote Fault
When set, indicates to the link partner that a Remote Fault condition
has been encountered.
13 RF R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12:9 reserved RO 0
Technology Ability Field[3]
When set, indicates that the PHY supports the 100Base-TX full-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated with the
RANEG bit in the MR0 register.
8 A3 R/W 1
Technology Ability Field[2]
When set, indicates that the PHY supports the 100Base-T half-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated.
7 A2 R/W 1
Technology Ability Field[1]
When set, indicates that the PHY supports the 10Base-T full-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated.
6 A1 R/W 1
Technology Ability Field[0]
When set, indicates that the PHY supports the 10Base-T half-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated.
5 A0 R/W 1
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Bit/Field Name Type Reset Description
Selector Field
The S[4:0] field encodes 32 possible messages for communicating
between PHYs. This field is hard-coded to 0x01, indicating that the
Stellaris® PHY is IEEE 802.3 compliant.
4:0 S[4:0] RO 0x01
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Register 22: Ethernet PHY Management Register 5 – Auto-Negotiation Link
Partner Base Page Ability (MR5), address 0x05
This register provides the advertised abilities of the link partner’s PHY that are received and stored
during Auto-Negotiation.
Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5)
Base 0x4004.8000
Address 0x05
Type RO, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NP ACK RF A[7:0] S[4:0]
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Next Page
When set, indicates that the link partner’s PHY is capable of Next page
exchanges to provide more detailed information on the PHY’s
capabilities.
15 NP RO 0
Acknowledge
When set, indicates that the device has successfully received the link
partner’s advertised abilities during Auto-Negotiation.
14 ACK RO 0
Remote Fault
Used as a standard transport mechanism for transmitting simple fault
information.
13 RF RO 0
Technology Ability Field
The A[7:0] field encodes individual technologies that are supported
by the PHY. See the MR4 register.
12:5 A[7:0] RO 0x00
Selector Field
The S[4:0] field encodes possible messages for communicating
between PHYs.
Value Description
0x00 Reserved
0x01 IEEE Std 802.3
0x02 IEEE Std 802.9 ISLAN-16T
0x03 IEEE Std 802.5
0x04 IEEE Std 1394
0x05–0x1F Reserved
4:0 S[4:0] RO 0x00
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Register 23: Ethernet PHY Management Register 6 – Auto-Negotiation
Expansion (MR6), address 0x06
This register enables software to determine the Auto-Negotiation and Next Page capabilities of the
PHY and the link partner after Auto-Negotiation.
Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6)
Base 0x4004.8000
Address 0x06
Type RO, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PDF LPNPA reserved PRX LPANEGA
Type RO RO RO RO RO RO RO RO RO RO RO RC RO RO RC RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:5 reserved RO 0x000
Parallel Detection Fault
When set, indicates that more than one technology has been detected
at link up. This bit is cleared when read.
4 PDF RC 0
Link Partner is Next Page Able
When set, indicates that the link partner is Next Page Able.
3 LPNPA RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2 reserved RO 0x000
New Page Received
When set, indicates that a New Page has been received from the link
partner and stored in the appropriate location. This bit remains set until
the register is read.
1 PRX RC 0
Link Partner is Auto-Negotiation Able
When set, indicates that the Link partner is Auto-Negotiation Able.
0 LPANEGA RO 0
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Register 24: Ethernet PHY Management Register 16 – Vendor-Specific (MR16),
address 0x10
This register enables software to configure the operation of vendor-specific modes of the PHY.
Ethernet PHY Management Register 16 – Vendor-Specific (MR16)
Base 0x4004.8000
Address 0x10
Type R/W, reset 0x0140
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPTR INPOL reserved TXHIM SQEI NL10 reserved APOL RVSPOL reserved PCSBP RXCC
Type R/W R/W RO R/W R/W R/W RO RO RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Repeater Mode
When set, enables the repeater mode of operation. In this mode,
full-duplex is not allowed and the Carrier Sense signal only responds
to receive activity. If the PHY is configured to 10Base-T mode, the SQE
test function is disabled.
15 RPTR R/W 0
Interrupt Polarity
Value Description
1 Sets the polarity of the PHY interrupt to be active High.
0 Sets the polarity of the PHY interrupt to active Low.
Important: Because the Media Access Controller expects active
Low interrupts from the PHY, this bit must always be
written with a 0 to ensure proper operation.
14 INPOL R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13 reserved RO 0
Transmit High Impedance Mode
When set, enables the transmitter High Impedance mode. In this mode,
the TXOP and TXON transmitter pins are put into a high impedance state.
The RXIP and RXIN pins remain fully functional.
12 TXHIM R/W 0
SQE Inhibit Testing
When set, prohibits 10Base-T SQE testing.
When 0, the SQE testing is performed by generating a Collision pulse
following the completion of the transmission of a frame.
11 SQEI R/W 0
Natural Loopback Mode
When set, enables the 10Base-T Natural Loopback mode. This causes
the transmission data received by the PHY to be looped back onto the
receive data path when 10Base-T mode is enabled.
10 NL10 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9:6 reserved RO 0x05
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Bit/Field Name Type Reset Description
Auto-Polarity Disable
When set, disables the PHY’s auto-polarity function.
If this bit is 0, the PHY automatically inverts the received signal due to
a wrong polarity connection during Auto-Negotiation if the PHY is in
10Base-T mode.
5 APOL R/W 0
Receive Data Polarity
This bit indicates whether the receive data pulses are being inverted.
If the APOL bit is 0, then the RVSPOL bit is read-only and indicates
whether the auto-polarity circuitry is reversing the polarity. In this case,
a 1 in the RVSPOL bit indicates that the receive data is inverted while a
0 indicates that the receive data is not inverted.
If the APOL bit is 1, then the RVSPOL bit is writable and software can
force the receive data to be inverted. Setting RVSPOL to 1 forces the
receive data to be inverted while a 0 does not invert the receive data.
4 RVSPOL R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
PCS Bypass
When set, enables the bypass of the PCS and scrambling/descrambling
functions in 100Base-TX mode. This mode is only valid when
Auto-Negotiation is disabled and 100Base-T mode is enabled.
1 PCSBP R/W 0
Receive Clock Control
When set, enables the Receive Clock Control power saving mode if the
PHY is configured in 100Base-TX mode. This mode shuts down the
receive clock when no data is being received from the physical medium
to save power. This mode should not be used when PCSBP is enabled
and is automatically disabled when the LOOPBK bit in the MR0 register
is set.
0 RXCC R/W 0
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Register 25: Ethernet PHY Management Register 17 – Interrupt Control/Status
(MR17), address 0x11
This register provides the means for controlling and observing the events, which trigger a PHY
interrupt in the MACRIS register. This register can also be used in a polling mode via the MII Serial
Interface as a means to observe key events within the PHY via one register address. Bits 0 through
7 are status bits, which are each set to logic 1 based on an event. These bits are cleared after the
register is read. Bits 8 through 15 of this register, when set to logic 1, enable their corresponding
bit in the lower byte to signal a PHY interrupt in the MACRIS register.
Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17)
Base 0x4004.8000
Address 0x11
Type R/W, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JABBER_IE RXER_IE PRX_IE PDF_IE LPACK_IELSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INTRXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT ANEGCOMP_INT
Type R/W R/W R/W R/W R/W R/W R/W R/W RC RC RC RC RC RC RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Jabber Interrupt Enable
When set, enables system interrupts when a Jabber condition is detected
by the PHY.
15 JABBER_IE R/W 0
Receive Error Interrupt Enable
When set, enables system interrupts when a receive error is detected
by the PHY.
14 RXER_IE R/W 0
Page Received Interrupt Enable
When set, enables system interrupts when a new page is received by
the PHY.
13 PRX_IE R/W 0
Parallel Detection Fault Interrupt Enable
When set, enables system interrupts when a Parallel Detection Fault is
detected by the PHY.
12 PDF_IE R/W 0
LP Acknowledge Interrupt Enable
When set, enables system interrupts when FLP bursts are received with
the Acknowledge bit during Auto-Negotiation.
11 LPACK_IE R/W 0
Link Status Change Interrupt Enable
When set, enables system interrupts when the Link Status changes
from OK to FAIL.
10 LSCHG_IE R/W 0
Remote Fault Interrupt Enable
When set, enables system interrupts when a Remote Fault condition is
signaled by the link partner.
9 RFAULT_IE R/W 0
Auto-Negotiation Complete Interrupt Enable
When set, enables system interrupts when the Auto-Negotiation
sequence has completed successfully.
8 ANEGCOMP_IE R/W 0
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Bit/Field Name Type Reset Description
Jabber Event Interrupt
When set, indicates that a Jabber event has been detected by the
10Base-T circuitry.
7 JABBER_INT RC 0
Receive Error Interrupt
When set, indicates that a receive error has been detected by the PHY.
6 RXER_INT RC 0
Page Receive Interrupt
When set, indicates that a new page has been received from the link
partner during Auto-Negotiation.
5 PRX_INT RC 0
Parallel Detection Fault Interrupt
When set, indicates that a Parallel Detection Fault has been detected
by the PHY during the Auto-Negotiation process.
4 PDF_INT RC 0
LP Acknowledge Interrupt
When set, indicates that an FLP burst has been received with the
Acknowledge bit set during Auto-Negotiation.
3 LPACK_INT RC 0
Link Status Change Interrupt
When set, indicates that the link status has changed from OK to FAIL.
2 LSCHG_INT RC 0
Remote Fault Interrupt
When set, indicates that a Remote Fault condition has been signaled
by the link partner.
1 RFAULT_INT RC 0
Auto-Negotiation Complete Interrupt
When set, indicates that the Auto-Negotiation sequence has completed
successfully.
0 ANEGCOMP_INT RC 0
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Register 26: Ethernet PHY Management Register 18 – Diagnostic (MR18),
address 0x12
This register enables software to diagnose the results of the previous Auto-Negotiation.
Ethernet PHY Management Register 18 – Diagnostic (MR18)
Base 0x4004.8000
Address 0x12
Type RO, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ANEGF DPLX RATE RXSD RX_LOCK reserved
Type RO RO RO RC RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
Auto-Negotiation Failure
When set, indicates that no common technology was found during
Auto-Negotiation and has failed. This bit remains set until read.
12 ANEGF RC 0
Duplex Mode
When set, indicates that Full-Duplex was the highest common
denominator found during the Auto-Negotiation process. Otherwise,
Half-Duplex was the highest common denominator found.
11 DPLX RO 0
Rate
When set, indicates that 100Base-TX was the highest common
denominator found during the Auto-Negotiation process. Otherwise,
10Base-TX was the highest common denominator found.
10 RATE RO 0
Receive Detection
When set, indicates that receive signal detection has occurred (in
100Base-TX mode) or that Manchester-encoded data has been detected
(in 10Base-T mode).
9 RXSD RO 0
Receive PLL Lock
When set, indicates that the Receive PLL has locked onto the receive
signal for the selected speed of operation (10Base-T or 100Base-TX).
8 RX_LOCK RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0 reserved RO 00
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Register 27: Ethernet PHY Management Register 19 – Transceiver Control
(MR19), address 0x13
This register enables software to set the gain of the transmit output to compensate for transformer
loss.
Ethernet PHY Management Register 19 – Transceiver Control (MR19)
Base 0x4004.8000
Address 0x13
Type R/W, reset 0x4000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXO[1:0] reserved
Type R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Transmit Amplitude Selection
The TXO[1:0] field sets the transmit output amplitude to account for
transmit transformer insertion loss.
Value Description
0x0 Gain set for 0.0dB of insertion loss
0x1 Gain set for 0.4dB of insertion loss
0x2 Gain set for 0.8dB of insertion loss
0x3 Gain set for 1.2dB of insertion loss
15:14 TXO[1:0] R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13:0 reserved RO 0x0
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Register 28: Ethernet PHY Management Register 23 – LED Configuration
(MR23), address 0x17
This register enables software to select the source that causes the LEDs to toggle.
Ethernet PHY Management Register 23 – LED Configuration (MR23)
Base 0x4004.8000
Address 0x17
Type R/W, reset 0x0010
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved LED1[3:0] LED0[3:0]
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8 reserved RO 0x0
LED1 Source
The LED1 field selects the source that toggles the LED1 signal.
Value Description
0x0 Link OK
0x1 RX or TX Activity (Default LED1)
0x2 TX Activity
0x3 RX Activity
0x4 Collision
0x5 100BASE-TX mode
0x6 10BASE-T mode
0x7 Full-Duplex
0x8 Link OK & Blink=RX or TX Activity
7:4 LED1[3:0] R/W 1
LED0 Source
The LED0 field selects the source that toggles the LED0 signal.
Value Description
0x0 Link OK (Default LED0)
0x1 RX or TX Activity
0x2 TX Activity
0x3 RX Activity
0x4 Collision
0x5 100BASE-TX mode
0x6 10BASE-T mode
0x7 Full-Duplex
0x8 Link OK & Blink=RX or TX Activity
3:0 LED0[3:0] R/W 0
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Register 29: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24),
address 0x18
This register enables software to control the behavior of the MDI/MDIX mux and its switching
capabilities.
Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24)
Base 0x4004.8000
Address 0x18
Type R/W, reset 0x00C0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PD_MODEAUTO_SW MDIX MDIX_CM MDIX_SD
Type RO RO RO RO RO RO RO RO R/W R/W R/W RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8 reserved RO 0x0
Parallel Detection Mode
When set, enables the Parallel Detection mode and allows auto-switching
to work when Auto-Negotiation is not enabled.
7 PD_MODE R/W 0
Auto-Switching Enable
When set, enables Auto-Switching of the MDI/MDIX mux.
6 AUTO_SW R/W 0
Auto-Switching Configuration
When set, indicates that the MDI/MDIX mux is in the crossover (MDIX)
configuration.
When 0, it indicates that the mux is in the pass-through (MDI)
configuration.
When the AUTO_SW bit is 1, the MDIX bit is read-only. When the
AUTO_SW bit is 0, the MDIX bit is read/write and can be configured
manually.
5 MDIX R/W 0
Auto-Switching Complete
When set, indicates that the auto-switching sequence has completed.
If 0, it indicates that the sequence has not completed or that
auto-switching is disabled.
4 MDIX_CM RO 0
Auto-Switching Seed
This field provides the initial seed for the switching algorithm. This seed
directly affects the number of attempts [5,4] respectively to write bits
[3:0].
A 0 sets the seed to 0x5.
3:0 MDIX_SD R/W 0
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18 Analog Comparators
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S8933 controller provides three independent integrated analog comparators that can be
configured to drive an output or generate an interrupt or ADC event.
Note: Not all comparators have the option to drive an output pin. See the Comparator Operating
Mode tables in “Functional Description” on page 495 for more information.
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
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18.1 Block Diagram
Figure 18-1. Analog Comparator Module Block Diagram
C2+
C2-
output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 2
ACSTAT2
ACCTL2
C1-
C1+ output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 1
ACSTAT1
ACCTL1
C1o
Voltage
Ref
ACREFCTL
output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 0
ACSTAT0
ACCTL0
C0+
internal
bus
C0-
C0o
trigger trigger
trigger trigger
trigger trigger
Interrupt Control
ACRIS
ACMIS
ACINTEN
interrupt
18.2 Functional Description
Important: It is recommended that the Digital-Input enable (the GPIODEN bit in the GPIO module)
for the analog input pin be disabled to prevent excessive current draw from the I/O
pads.
The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT.
VIN- < VIN+, VOUT = 1
VIN- > VIN+, VOUT = 0
As shown in Figure 18-2 on page 496, the input source for VIN- is an external input. In addition to
an external input, input sources for VIN+ can be the +ve input of comparator 0 or an internal reference.
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Figure 18-2. Structure of Comparator Unit
ACCTL ACSTAT
IntGen
2 TrigGen
1
0
CINV
output
-ve input
+ve input
interrupt
internal
bus
trigger
+ve input (alternate)
reference input
A comparator is configured through two status/control registers (ACCTL and ACSTAT ). The internal
reference is configured through one control register (ACREFCTL). Interrupt status and control is
configured through three registers (ACMIS, ACRIS, and ACINTEN). The operating modes of the
comparators are shown in the Comparator Operating Mode tables.
Typically, the comparator output is used internally to generate controller interrupts. It may also be
used to drive an external pin or generate an analog-to-digital converter (ADC) trigger.
Important: Certain register bit values must be set before using the analog comparators. The proper
pad configuration for the comparator input and output pins are described in the
Comparator Operating Mode tables.
Table 18-1. Comparator 0 Operating Modes
ACCNTL0 Comparator 0
ASRCP VIN- VIN+ Output Interrupt ADCTrigger
00 C0- C0+ C0o yes yes
01 C0- C0+ C0o yes yes
10 C0- Vref C0o yes yes
11 C0- reserved C0o yes yes
Table 18-2. Comparator 1 Operating Modes
ACCNTL1 Comparator 1
ASRCP VIN- VIN+ Output Interrupt ADCTrigger
00 C1- C1o/C1+ C1o/C1+ yes yes
01 C1- C0+ C1o/C1+ yes yes
10 C1- Vref C1o/C1+ yes yes
11 C1- reserved C1o/C1+ yes yes
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Table 18-3. Comparator 2 Operating Modes
ACCNTL2 Comparator 2
ASRCP VIN- VIN+ Output Interrupt ADCTrigger
00 C2- C2+ n/a yes yes
01 C2- C0+ n/a yes yes
10 C2- Vref n/a yes yes
11 C2- reserved n/a yes yes
18.2.1 Internal Reference Programming
The structure of the internal reference is shown in Figure 18-3 on page 497. This is controlled by a
single configuration register (ACREFCTL). Table 18-4 on page 497 shows the programming options
to develop specific internal reference values, to compare an external voltage against a particular
voltage generated internally.
Figure 18-3. Comparator Internal Reference Structure
8R R R
8R
R
•••
•••
0
Decoder
15 14 1
AVDD
EN
internal
reference
VREF
RNG
Table 18-4. Internal Reference Voltage and ACREFCTL Field Values
ACREFCTL Register Output Reference Voltage Based on VREF Field Value
EN Bit Value RNG Bit Value
0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and VREF=0
for the least noisy ground reference.
EN=0 RNG=X
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ACREFCTL Register Output Reference Voltage Based on VREF Field Value
EN Bit Value RNG Bit Value
Total resistance in ladder is 31 R.
The range of internal reference in this mode is 0.85-2.448 V.
EN=1 RNG=0
Total resistance in ladder is 23 R.
The range of internal reference for this mode is 0-2.152 V.
RNG=1
18.3 Initialization and Configuration
The following example shows how to configure an analog comparator to read back its output value
from an internal register.
1. Enable the analog comparator 0 clock by writing a value of 0x0010.0000 to the RCGC1 register
in the System Control module.
2. In the GPIO module, enable the GPIO port/pin associated with C0- as a GPIO input.
3. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the
value 0x0000.030C.
4. Configure comparator 0 to use the internal voltage reference and to not invert the output on the
C0o pin by writing the ACCTL0 register with the value of 0x0000.040C.
5. Delay for some time.
6. Read the comparator output value by reading the ACSTAT0 register’s OVAL value.
Change the level of the signal input on C0- to see the OVAL value change.
18.4 Register Map
Table 18-5 on page 499 lists the comparator registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Analog Comparator base address of 0x4003.C000.
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Table 18-5. Analog Comparators Register Map
See
Offset Name Type Reset Description page
0x00 ACMIS R/W1C 0x0000.0000 Analog Comparator Masked Interrupt Status 500
0x04 ACRIS RO 0x0000.0000 Analog Comparator Raw Interrupt Status 501
0x08 ACINTEN R/W 0x0000.0000 Analog Comparator Interrupt Enable 502
0x10 ACREFCTL R/W 0x0000.0000 Analog Comparator Reference Voltage Control 503
0x20 ACSTAT0 RO 0x0000.0000 Analog Comparator Status 0 504
0x24 ACCTL0 R/W 0x0000.0000 Analog Comparator Control 0 505
0x40 ACSTAT1 RO 0x0000.0000 Analog Comparator Status 1 504
0x44 ACCTL1 R/W 0x0000.0000 Analog Comparator Control 1 505
0x60 ACSTAT2 RO 0x0000.0000 Analog Comparator Status 2 504
0x64 ACCTL2 R/W 0x0000.0000 Analog Comparator Control 2 505
18.5 Register Descriptions
The remainder of this section lists and describes the Analog Comparator registers, in numerical
order by address offset.
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Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00
This register provides a summary of the interrupt status (masked) of the comparator.
Analog Comparator Masked Interrupt Status (ACMIS)
Base 0x4003.C000
Offset 0x00
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Comparator 2 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
2 IN2 R/W1C 0
Comparator 1 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
1 IN1 R/W1C 0
Comparator 0 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
0 IN0 R/W1C 0
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Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04
This register provides a summary of the interrupt status (raw) of the comparator.
Analog Comparator Raw Interrupt Status (ACRIS)
Base 0x4003.C000
Offset 0x04
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Comparator 2 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
2.
2 IN2 RO 0
Comparator 1 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
1.
1 IN1 RO 0
Comparator 0 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
0.
0 IN0 RO 0
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Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08
This register provides the interrupt enable for the comparator.
Analog Comparator Interrupt Enable (ACINTEN)
Base 0x4003.C000
Offset 0x08
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Comparator 2 Interrupt Enable
When set, enables the controller interrupt from the comparator 2 output
2 IN2 R/W 0
Comparator 1 Interrupt Enable
When set, enables the controller interrupt from the comparator 1 output.
1 IN1 R/W 0
Comparator 0 Interrupt Enable
When set, enables the controller interrupt from the comparator 0 output.
0 IN0 R/W 0
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Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset
0x10
This register specifies whether the resistor ladder is powered on as well as the range and tap.
Analog Comparator Reference Voltage Control (ACREFCTL)
Base 0x4003.C000
Offset 0x10
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EN RNG reserved VREF
Type RO RO RO RO RO RO R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0x00
Resistor Ladder Enable
The EN bit specifies whether the resistor ladder is powered on. If 0, the
resistor ladder is unpowered. If 1, the resistor ladder is connected to
the analog VDD.
This bit is reset to 0 so that the internal reference consumes the least
amount of power if not used and programmed.
9 EN R/W 0
Resistor Ladder Range
The RNG bit specifies the range of the resistor ladder. If 0, the resistor
ladder has a total resistance of 31 R. If 1, the resistor ladder has a total
resistance of 23 R.
8 RNG R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x00
Resistor Ladder Voltage Ref
The VREF bit field specifies the resistor ladder tap that is passed through
an analog multiplexer. The voltage corresponding to the tap position is
the internal reference voltage available for comparison. See Table
18-4 on page 497 for some output reference voltage examples.
3:0 VREF R/W 0x00
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Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60
These registers specify the current output value of the comparator.
Analog Comparator Status 0 (ACSTAT0)
Base 0x4003.C000
Offset 0x20
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OVAL reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Comparator Output Value
The OVAL bit specifies the current output value of the comparator.
1 OVAL RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64
These registers configure the comparator’s input and output.
Analog Comparator Control 0 (ACCTL0)
Base 0x4003.C000
Offset 0x24
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TOEN ASRCP reserved TSLVAL TSEN ISLVAL ISEN CINV reserved
Type RO RO RO RO R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Trigger Output Enable
The TOEN bit enables the ADC event transmission to the ADC. If 0, the
event is suppressed and not sent to the ADC. If 1, the event is
transmitted to the ADC.
11 TOEN R/W 0
Analog Source Positive
The ASRCP field specifies the source of input voltage to the VIN+ terminal
of the comparator. The encodings for this field are as follows:
Value Function
0x0 Pin value
0x1 Pin value of C0+
0x2 Internal voltage reference
0x3 Reserved
10:9 ASRCP R/W 0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8 reserved RO 0
Trigger Sense Level Value
The TSLVAL bit specifies the sense value of the input that generates
an ADC event if in Level Sense mode. If 0, an ADC event is generated
if the comparator output is Low. Otherwise, an ADC event is generated
if the comparator output is High.
7 TSLVAL R/W 0
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Bit/Field Name Type Reset Description
Trigger Sense
The TSEN field specifies the sense of the comparator output that
generates an ADC event. The sense conditioning is as follows:
Value Function
0x0 Level sense, see TSLVAL
0x1 Falling edge
0x2 Rising edge
0x3 Either edge
6:5 TSEN R/W 0x0
Interrupt Sense Level Value
The ISLVAL bit specifies the sense value of the input that generates
an interrupt if in Level Sense mode. If 0, an interrupt is generated if the
comparator output is Low. Otherwise, an interrupt is generated if the
comparator output is High.
4 ISLVAL R/W 0
Interrupt Sense
The ISEN field specifies the sense of the comparator output that
generates an interrupt. The sense conditioning is as follows:
Value Function
0x0 Level sense, see ISLVAL
0x1 Falling edge
0x2 Rising edge
0x3 Either edge
3:2 ISEN R/W 0x0
Comparator Output Invert
The CINV bit conditionally inverts the output of the comparator. If 0, the
output of the comparator is unchanged. If 1, the output of the comparator
is inverted prior to being processed by hardware.
1 CINV R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Analog Comparators
19 Pin Diagram
The LM3S8933 microcontroller pin diagrams are shown below.
Figure 19-1. 100-Pin LQFP Package Pin Diagram
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Figure 19-2. 108-Ball BGA Package Pin Diagram (Top View)
508 March 17, 2008
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Pin Diagram
20 Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register.
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
Table 20-1 on page 509 shows the pin-to-signal-name mapping, including functional characteristics
of the signals. Table 20-2 on page 513 lists the signals in alphabetical order by signal name.
Table 20-3 on page 517 groups the signals by functionality, except for GPIOs. Table 20-4 on page
519 lists the GPIO pins and their alternate functionality.
20.1 100-Pin LQFP Package Pin Tables
Table 20-1. Signals by Pin Number
Pin Number Pin Name Pin Type Buffer Type Description
1 ADC0 I Analog Analog-to-digital converter input 0.
2 ADC1 I Analog Analog-to-digital converter input 1.
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
3 VDDA - Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
4 GNDA - Power
5 ADC2 I Analog Analog-to-digital converter input 2.
6 ADC3 I Analog Analog-to-digital converter input 3.
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 μF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
7 LDO - Power
8 VDD - Power Positive supply for I/O and some logic.
9 GND - Power Ground reference for logic and I/O pins.
10 PD0 I/O TTL GPIO port D bit 0
CAN0Rx I TTL CAN module 0 receive
11 PD1 I/O TTL GPIO port D bit 1
CAN0Tx O TTL CAN module 0 transmit
12 PD2 I/O TTL GPIO port D bit 2
UART module 1 receive. When in IrDA mode,
this signal has IrDA modulation.
U1Rx I TTL
13 PD3 I/O TTL GPIO port D bit 3
UART module 1 transmit. When in IrDA mode,
this signal has IrDA modulation.
U1Tx O TTL
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Pin Number Pin Name Pin Type Buffer Type Description
Positive supply for most of the logic function,
including the processor core and most
peripherals.
14 VDD25 - Power
15 GND - Power Ground reference for logic and I/O pins.
16 XTALPPHY I TTL XTALP of the Ethernet PHY
17 XTALNPHY O TTL XTALN of the Ethernet PHY
18 NC - - No connect
19 NC - - No connect
20 VDD - Power Positive supply for I/O and some logic.
21 GND - Power Ground reference for logic and I/O pins.
22 PC7 I/O TTL GPIO port C bit 7
23 PC6 I/O TTL GPIO port C bit 6
24 PC5 I/O TTL GPIO port C bit 5
C1o O TTL Analog comparator 1 output
25 PC4 I/O TTL GPIO port C bit 4
26 PA0 I/O TTL GPIO port A bit 0
UART module 0 receive. When in IrDA mode,
this signal has IrDA modulation.
U0Rx I TTL
27 PA1 I/O TTL GPIO port A bit 1
UART module 0 transmit. When in IrDA mode,
this signal has IrDA modulation.
U0Tx O TTL
28 PA2 I/O TTL GPIO port A bit 2
SSI0Clk I/O TTL SSI module 0 clock
29 PA3 I/O TTL GPIO port A bit 3
SSI0Fss I/O TTL SSI module 0 frame
30 PA4 I/O TTL GPIO port A bit 4
SSI0Rx I TTL SSI module 0 receive
31 PA5 I/O TTL GPIO port A bit 5
SSI0Tx O TTL SSI module 0 transmit
32 VDD - Power Positive supply for I/O and some logic.
33 GND - Power Ground reference for logic and I/O pins.
34 PA6 I/O TTL GPIO port A bit 6
CCP1 I/O TTL Capture/Compare/PWM 1
35 PA7 I/O TTL GPIO port A bit 7
36 VCCPHY I TTL VCC of the Ethernet PHY
37 RXIN I Analog RXIN of the Ethernet PHY
Positive supply for most of the logic function,
including the processor core and most
peripherals.
38 VDD25 - Power
39 GND - Power Ground reference for logic and I/O pins.
40 RXIP I Analog RXIP of the Ethernet PHY
41 GNDPHY I TTL GND of the Ethernet PHY
42 GNDPHY I TTL GND of the Ethernet PHY
43 TXOP O Analog TXOP of the Ethernet PHY
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Signal Tables
Pin Number Pin Name Pin Type Buffer Type Description
44 VDD - Power Positive supply for I/O and some logic.
45 GND - Power Ground reference for logic and I/O pins.
46 TXON O Analog TXON of the Ethernet PHY
47 PF0 I/O TTL GPIO port F bit 0
Main oscillator crystal input or an external
clock reference input.
48 OSC0 I Analog
49 OSC1 O Analog Main oscillator crystal output.
An external input that brings the processor out
of hibernate mode when asserted.
50 WAKE I OD
An output that indicates the processor is in
hibernate mode.
51 HIB O TTL
Hibernation Module oscillator crystal input or
an external clock reference input. Note that
this is either a 4.19-MHz crystal or a
32.768-kHz oscillator for the Hibernation
Module RTC. See the CLKSEL bit in the
HIBCTL register.
52 XOSC0 I Analog
53 XOSC1 O Analog Hibernation Module oscillator crystal output.
54 GND - Power Ground reference for logic and I/O pins.
Power source for the Hibernation Module. It
is normally connected to the positive terminal
of a battery and serves as the battery
backup/Hibernation Module power-source
supply.
55 VBAT - Power
56 VDD - Power Positive supply for I/O and some logic.
57 GND - Power Ground reference for logic and I/O pins.
58 MDIO I/O TTL MDIO of the Ethernet PHY
59 PF3 I/O TTL GPIO port F bit 3
LED0 O TTL MII LED 0
60 PF2 I/O TTL GPIO port F bit 2
LED1 O TTL MII LED 1
61 PF1 I/O TTL GPIO port F bit 1
Positive supply for most of the logic function,
including the processor core and most
peripherals.
62 VDD25 - Power
63 GND - Power Ground reference for logic and I/O pins.
64 RST I TTL System reset input.
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
65 CMOD0 I/O TTL
66 PB0 I/O TTL GPIO port B bit 0
CCP0 I/O TTL Capture/Compare/PWM 0
67 PB1 I/O TTL GPIO port B bit 1
CCP2 I/O TTL Capture/Compare/PWM 2
68 VDD - Power Positive supply for I/O and some logic.
69 GND - Power Ground reference for logic and I/O pins.
70 PB2 I/O TTL GPIO port B bit 2
I2C0SCL I/O OD I2C module 0 clock
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Pin Number Pin Name Pin Type Buffer Type Description
71 PB3 I/O TTL GPIO port B bit 3
I2C0SDA I/O OD I2C module 0 data
72 NC - - No connect
73 NC - - No connect
74 NC - - No connect
75 NC - - No connect
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
76 CMOD1 I/O TTL
77 PC3 I/O TTL GPIO port C bit 3
TDO O TTL JTAG TDO and SWO
SWO O TTL JTAG TDO and SWO
78 PC2 I/O TTL GPIO port C bit 2
TDI I TTL JTAG TDI
79 PC1 I/O TTL GPIO port C bit 1
TMS I/O TTL JTAG TMS and SWDIO
SWDIO I/O TTL JTAG TMS and SWDIO
80 PC0 I/O TTL GPIO port C bit 0
TCK I TTL JTAG/SWD CLK
SWCLK I TTL JTAG/SWD CLK
81 VDD - Power Positive supply for I/O and some logic.
82 GND - Power Ground reference for logic and I/O pins.
83 VCCPHY I TTL VCC of the Ethernet PHY
84 VCCPHY I TTL VCC of the Ethernet PHY
85 GNDPHY I TTL GND of the Ethernet PHY
86 GNDPHY I TTL GND of the Ethernet PHY
87 GND - Power Ground reference for logic and I/O pins.
Positive supply for most of the logic function,
including the processor core and most
peripherals.
88 VDD25 - Power
89 PB7 I/O TTL GPIO port B bit 7
TRST I TTL JTAG TRSTn
90 PB6 I/O TTL GPIO port B bit 6
91 PB5 I/O TTL GPIO port B bit 5
92 PB4 I/O TTL GPIO port B bit 4
93 VDD - Power Positive supply for I/O and some logic.
94 GND - Power Ground reference for logic and I/O pins.
95 PD4 I/O TTL GPIO port D bit 4
CCP3 I/O TTL Capture/Compare/PWM 3
96 PD5 I/O TTL GPIO port D bit 5
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
97 GNDA - Power
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Signal Tables
Pin Number Pin Name Pin Type Buffer Type Description
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
98 VDDA - Power
99 PD6 I/O TTL GPIO port D bit 6
100 PD7 I/O TTL GPIO port D bit 7
C0o O TTL Analog comparator 0 output
Table 20-2. Signals by Signal Name
Pin Name Pin Number Pin Type Buffer Type Description
ADC0 1 I Analog Analog-to-digital converter input 0.
ADC1 2 I Analog Analog-to-digital converter input 1.
ADC2 5 I Analog Analog-to-digital converter input 2.
ADC3 6 I Analog Analog-to-digital converter input 3.
C0o 100 O TTL Analog comparator 0 output
C1o 24 O TTL Analog comparator 1 output
CAN0Rx 10 I TTL CAN module 0 receive
CAN0Tx 11 O TTL CAN module 0 transmit
CCP0 66 I/O TTL Capture/Compare/PWM 0
CCP1 34 I/O TTL Capture/Compare/PWM 1
CCP2 67 I/O TTL Capture/Compare/PWM 2
CCP3 95 I/O TTL Capture/Compare/PWM 3
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD0 65 I/O TTL
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1 76 I/O TTL
GND 9 - Power Ground reference for logic and I/O pins.
GND 15 - Power Ground reference for logic and I/O pins.
GND 21 - Power Ground reference for logic and I/O pins.
GND 33 - Power Ground reference for logic and I/O pins.
GND 39 - Power Ground reference for logic and I/O pins.
GND 45 - Power Ground reference for logic and I/O pins.
GND 54 - Power Ground reference for logic and I/O pins.
GND 57 - Power Ground reference for logic and I/O pins.
GND 63 - Power Ground reference for logic and I/O pins.
GND 69 - Power Ground reference for logic and I/O pins.
GND 82 - Power Ground reference for logic and I/O pins.
GND 87 - Power Ground reference for logic and I/O pins.
GND 94 - Power Ground reference for logic and I/O pins.
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
GNDA 4 - Power
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Pin Name Pin Number Pin Type Buffer Type Description
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
GNDA 97 - Power
GNDPHY 41 I TTL GND of the Ethernet PHY
GNDPHY 42 I TTL GND of the Ethernet PHY
GNDPHY 85 I TTL GND of the Ethernet PHY
GNDPHY 86 I TTL GND of the Ethernet PHY
An output that indicates the processor is in
hibernate mode.
HIB 51 O TTL
I2C0SCL 70 I/O OD I2C module 0 clock
I2C0SDA 71 I/O OD I2C module 0 data
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 μF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
LDO 7 - Power
LED0 59 O TTL MII LED 0
LED1 60 O TTL MII LED 1
MDIO 58 I/O TTL MDIO of the Ethernet PHY
NC 18 - - No connect
NC 19 - - No connect
NC 72 - - No connect
NC 73 - - No connect
NC 74 - - No connect
NC 75 - - No connect
Main oscillator crystal input or an external
clock reference input.
OSC0 48 I Analog
OSC1 49 O Analog Main oscillator crystal output.
PA0 26 I/O TTL GPIO port A bit 0
PA1 27 I/O TTL GPIO port A bit 1
PA2 28 I/O TTL GPIO port A bit 2
PA3 29 I/O TTL GPIO port A bit 3
PA4 30 I/O TTL GPIO port A bit 4
PA5 31 I/O TTL GPIO port A bit 5
PA6 34 I/O TTL GPIO port A bit 6
PA7 35 I/O TTL GPIO port A bit 7
PB0 66 I/O TTL GPIO port B bit 0
PB1 67 I/O TTL GPIO port B bit 1
PB2 70 I/O TTL GPIO port B bit 2
PB3 71 I/O TTL GPIO port B bit 3
PB4 92 I/O TTL GPIO port B bit 4
PB5 91 I/O TTL GPIO port B bit 5
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Signal Tables
Pin Name Pin Number Pin Type Buffer Type Description
PB6 90 I/O TTL GPIO port B bit 6
PB7 89 I/O TTL GPIO port B bit 7
PC0 80 I/O TTL GPIO port C bit 0
PC1 79 I/O TTL GPIO port C bit 1
PC2 78 I/O TTL GPIO port C bit 2
PC3 77 I/O TTL GPIO port C bit 3
PC4 25 I/O TTL GPIO port C bit 4
PC5 24 I/O TTL GPIO port C bit 5
PC6 23 I/O TTL GPIO port C bit 6
PC7 22 I/O TTL GPIO port C bit 7
PD0 10 I/O TTL GPIO port D bit 0
PD1 11 I/O TTL GPIO port D bit 1
PD2 12 I/O TTL GPIO port D bit 2
PD3 13 I/O TTL GPIO port D bit 3
PD4 95 I/O TTL GPIO port D bit 4
PD5 96 I/O TTL GPIO port D bit 5
PD6 99 I/O TTL GPIO port D bit 6
PD7 100 I/O TTL GPIO port D bit 7
PF0 47 I/O TTL GPIO port F bit 0
PF1 61 I/O TTL GPIO port F bit 1
PF2 60 I/O TTL GPIO port F bit 2
PF3 59 I/O TTL GPIO port F bit 3
RST 64 I TTL System reset input.
RXIN 37 I Analog RXIN of the Ethernet PHY
RXIP 40 I Analog RXIP of the Ethernet PHY
SSI0Clk 28 I/O TTL SSI module 0 clock
SSI0Fss 29 I/O TTL SSI module 0 frame
SSI0Rx 30 I TTL SSI module 0 receive
SSI0Tx 31 O TTL SSI module 0 transmit
SWCLK 80 I TTL JTAG/SWD CLK
SWDIO 79 I/O TTL JTAG TMS and SWDIO
SWO 77 O TTL JTAG TDO and SWO
TCK 80 I TTL JTAG/SWD CLK
TDI 78 I TTL JTAG TDI
TDO 77 O TTL JTAG TDO and SWO
TMS 79 I/O TTL JTAG TMS and SWDIO
TRST 89 I TTL JTAG TRSTn
TXON 46 O Analog TXON of the Ethernet PHY
TXOP 43 O Analog TXOP of the Ethernet PHY
UART module 0 receive. When in IrDA mode,
this signal has IrDA modulation.
U0Rx 26 I TTL
UART module 0 transmit. When in IrDA mode,
this signal has IrDA modulation.
U0Tx 27 O TTL
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LM3S8933 Microcontroller
Pin Name Pin Number Pin Type Buffer Type Description
UART module 1 receive. When in IrDA mode,
this signal has IrDA modulation.
U1Rx 12 I TTL
UART module 1 transmit. When in IrDA mode,
this signal has IrDA modulation.
U1Tx 13 O TTL
Power source for the Hibernation Module. It
is normally connected to the positive terminal
of a battery and serves as the battery
backup/Hibernation Module power-source
supply.
VBAT 55 - Power
VCCPHY 36 I TTL VCC of the Ethernet PHY
VCCPHY 83 I TTL VCC of the Ethernet PHY
VCCPHY 84 I TTL VCC of the Ethernet PHY
VDD 8 - Power Positive supply for I/O and some logic.
VDD 20 - Power Positive supply for I/O and some logic.
VDD 32 - Power Positive supply for I/O and some logic.
VDD 44 - Power Positive supply for I/O and some logic.
VDD 56 - Power Positive supply for I/O and some logic.
VDD 68 - Power Positive supply for I/O and some logic.
VDD 81 - Power Positive supply for I/O and some logic.
VDD 93 - Power Positive supply for I/O and some logic.
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 14 - Power
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 38 - Power
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 62 - Power
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 88 - Power
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
VDDA 3 - Power
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
VDDA 98 - Power
An external input that brings the processor out
of hibernate mode when asserted.
WAKE 50 I OD
Hibernation Module oscillator crystal input or
an external clock reference input. Note that
this is either a 4.19-MHz crystal or a
32.768-kHz oscillator for the Hibernation
Module RTC. See the CLKSEL bit in the
HIBCTL register.
XOSC0 52 I Analog
XOSC1 53 O Analog Hibernation Module oscillator crystal output.
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Signal Tables
Pin Name Pin Number Pin Type Buffer Type Description
XTALNPHY 17 O TTL XTALN of the Ethernet PHY
XTALPPHY 16 I TTL XTALP of the Ethernet PHY
Table 20-3. Signals by Function, Except for GPIO
Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
ADC ADC0 1 I Analog Analog-to-digital converter input 0.
ADC1 2 I Analog Analog-to-digital converter input 1.
ADC2 5 I Analog Analog-to-digital converter input 2.
ADC3 6 I Analog Analog-to-digital converter input 3.
Analog C0o 100 O TTL Analog comparator 0 output
Comparators C1o 24 O TTL Analog comparator 1 output
Controller Area CAN0Rx 10 I TTL CAN module 0 receive
Network CAN0Tx 11 O TTL CAN module 0 transmit
Ethernet PHY GNDPHY 41 I TTL GND of the Ethernet PHY
GNDPHY 42 I TTL GND of the Ethernet PHY
GNDPHY 85 I TTL GND of the Ethernet PHY
GNDPHY 86 I TTL GND of the Ethernet PHY
LED0 59 O TTL MII LED 0
LED1 60 O TTL MII LED 1
MDIO 58 I/O TTL MDIO of the Ethernet PHY
RXIN 37 I Analog RXIN of the Ethernet PHY
RXIP 40 I Analog RXIP of the Ethernet PHY
TXON 46 O Analog TXON of the Ethernet PHY
TXOP 43 O Analog TXOP of the Ethernet PHY
VCCPHY 36 I TTL VCC of the Ethernet PHY
VCCPHY 83 I TTL VCC of the Ethernet PHY
VCCPHY 84 I TTL VCC of the Ethernet PHY
XTALNPHY 17 O TTL XTALN of the Ethernet PHY
XTALPPHY 16 I TTL XTALP of the Ethernet PHY
General-Purpose CCP0 66 I/O TTL Capture/Compare/PWM 0
Timers CCP1 34 I/O TTL Capture/Compare/PWM 1
CCP2 67 I/O TTL Capture/Compare/PWM 2
CCP3 95 I/O TTL Capture/Compare/PWM 3
I2C I2C0SCL 70 I/O OD I2C module 0 clock
I2C0SDA 71 I/O OD I2C module 0 data
JTAG/SWD/SWO SWCLK 80 I TTL JTAG/SWD CLK
SWDIO 79 I/O TTL JTAG TMS and SWDIO
SWO 77 O TTL JTAG TDO and SWO
TCK 80 I TTL JTAG/SWD CLK
TDI 78 I TTL JTAG TDI
TDO 77 O TTL JTAG TDO and SWO
TMS 79 I/O TTL JTAG TMS and SWDIO
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Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
Power GND 9 - Power Ground reference for logic and I/O pins.
GND 15 - Power Ground reference for logic and I/O pins.
GND 21 - Power Ground reference for logic and I/O pins.
GND 33 - Power Ground reference for logic and I/O pins.
GND 39 - Power Ground reference for logic and I/O pins.
GND 45 - Power Ground reference for logic and I/O pins.
GND 54 - Power Ground reference for logic and I/O pins.
GND 57 - Power Ground reference for logic and I/O pins.
GND 63 - Power Ground reference for logic and I/O pins.
GND 69 - Power Ground reference for logic and I/O pins.
GND 82 - Power Ground reference for logic and I/O pins.
GND 87 - Power Ground reference for logic and I/O pins.
GND 94 - Power Ground reference for logic and I/O pins.
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
GNDA 4 - Power
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
GNDA 97 - Power
An output that indicates the processor is in
hibernate mode.
HIB 51 O TTL
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 μF or greater. When the on-chip LDO is
used to provide power to the logic, the LDO pin
must also be connected to the VDD25 pins at the
board level in addition to the decoupling
capacitor(s).
LDO 7 - Power
Power source for the Hibernation Module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation Module power-source supply.
VBAT 55 - Power
VDD 8 - Power Positive supply for I/O and some logic.
VDD 20 - Power Positive supply for I/O and some logic.
VDD 32 - Power Positive supply for I/O and some logic.
VDD 44 - Power Positive supply for I/O and some logic.
VDD 56 - Power Positive supply for I/O and some logic.
VDD 68 - Power Positive supply for I/O and some logic.
VDD 81 - Power Positive supply for I/O and some logic.
VDD 93 - Power Positive supply for I/O and some logic.
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 14 - Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 38 - Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 62 - Power
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Signal Tables
Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
VDD25 Positive supply for most of the logic function,
including the processor core and most peripherals.
88 - Power
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
VDDA 3 - Power
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
VDDA 98 - Power
An external input that brings the processor out of
hibernate mode when asserted.
WAKE 50 I OD
SSI SSI0Clk 28 I/O TTL SSI module 0 clock
SSI0Fss 29 I/O TTL SSI module 0 frame
SSI0Rx 30 I TTL SSI module 0 receive
SSI0Tx 31 O TTL SSI module 0 transmit
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
System Control & CMOD0 65 I/O TTL
Clocks
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1 76 I/O TTL
Main oscillator crystal input or an external clock
reference input.
OSC0 48 I Analog
OSC1 49 O Analog Main oscillator crystal output.
RST 64 I TTL System reset input.
TRST 89 I TTL JTAG TRSTn
Hibernation Module oscillator crystal input or an
external clock reference input. Note that this is
either a 4.19-MHz crystal or a 32.768-kHz oscillator
for the Hibernation Module RTC. See the CLKSEL
bit in the HIBCTL register.
XOSC0 52 I Analog
XOSC1 53 O Analog Hibernation Module oscillator crystal output.
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
UART U0Rx 26 I TTL
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U0Tx 27 O TTL
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
U1Rx 12 I TTL
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U1Tx 13 O TTL
Table 20-4. GPIO Pins and Alternate Functions
GPIO Pin Pin Number Multiplexed Function Multiplexed Function
PA0 26 U0Rx
PA1 27 U0Tx
PA2 28 SSI0Clk
PA3 29 SSI0Fss
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GPIO Pin Pin Number Multiplexed Function Multiplexed Function
PA4 30 SSI0Rx
PA5 31 SSI0Tx
PA6 34 CCP1
PA7 35
PB0 66 CCP0
PB1 67 CCP2
PB2 70 I2C0SCL
PB3 71 I2C0SDA
PB4 92
PB5 91
PB6 90
PB7 89 TRST
PC0 80 TCK SWCLK
PC1 79 TMS SWDIO
PC2 78 TDI
PC3 77 TDO SWO
PC4 25
PC5 24 C1o
PC6 23
PC7 22
PD0 10 CAN0Rx
PD1 11 CAN0Tx
PD2 12 U1Rx
PD3 13 U1Tx
PD4 95 CCP3
PD5 96
PD6 99
PD7 100 C0o
PF0 47
PF1 61
PF2 60 LED1
PF3 59 LED0
20.2 108-Pin BGA Package Pin Tables
Table 20-5. Signals by Pin Number
Pin Number Pin Name Pin Type Buffer Type Description
A1 ADC1 I Analog Analog-to-digital converter input 1.
A2 NC - - No connect
A3 NC - - No connect
A4 NC - - No connect
520 March 17, 2008
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Signal Tables
Pin Number Pin Name Pin Type Buffer Type Description
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
A5 GNDA - Power
A6 PB4 I/O TTL GPIO port B bit 4
C0- I Analog Analog comparator 0 negative input
A7 PB6 I/O TTL GPIO port B bit 6
C0+ I Analog Analog comparator 0 positive input
A8 PB7 I/O TTL GPIO port B bit 7
TRST I TTL JTAG TRSTn
A9 PC0 I/O TTL GPIO port C bit 0
TCK I TTL JTAG/SWD CLK
SWCLK I TTL JTAG/SWD CLK
A10 PC3 I/O TTL GPIO port C bit 3
TDO O TTL JTAG TDO and SWO
SWO O TTL JTAG TDO and SWO
A11 NC - - No connect
A12 NC - - No connect
B1 ADC0 I Analog Analog-to-digital converter input 0.
B2 ADC3 I Analog Analog-to-digital converter input 3.
B3 ADC2 I Analog Analog-to-digital converter input 2.
B4 NC - - No connect
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
B5 GNDA - Power
B6 GND - Power Ground reference for logic and I/O pins.
B7 PB5 I/O TTL GPIO port B bit 5
C1- I Analog Analog comparator 1 negative input
B8 PC2 I/O TTL GPIO port C bit 2
TDI I TTL JTAG TDI
B9 PC1 I/O TTL GPIO port C bit 1
TMS I/O TTL JTAG TMS and SWDIO
SWDIO I/O TTL JTAG TMS and SWDIO
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
B10 CMOD1 I/O TTL
B11 NC - - No connect
B12 NC - - No connect
C1 PE7 I/O TTL GPIO port E bit 7
C2 PE6 I/O TTL GPIO port E bit 6
Positive supply for most of the logic function,
including the processor core and most
peripherals.
C3 VDD25 - Power
C4 GND - Power Ground reference for logic and I/O pins.
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Pin Number Pin Name Pin Type Buffer Type Description
C5 GND - Power Ground reference for logic and I/O pins.
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
C6 VDDA - Power
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
C7 VDDA - Power
C8 GNDPHY I TTL GND of the Ethernet PHY
C9 GNDPHY I TTL GND of the Ethernet PHY
C10 VCCPHY I TTL VCC of the Ethernet PHY
C11 PB2 I/O TTL GPIO port B bit 2
I2C0SCL I/O OD I2C module 0 clock
C12 PB3 I/O TTL GPIO port B bit 3
I2C0SDA I/O OD I2C module 0 data
D1 PE4 I/O TTL GPIO port E bit 4
D2 PE5 I/O TTL GPIO port E bit 5
Positive supply for most of the logic function,
including the processor core and most
peripherals.
D3 VDD25 - Power
D10 VCCPHY I TTL VCC of the Ethernet PHY
D11 VCCPHY I TTL VCC of the Ethernet PHY
D12 PB1 I/O TTL GPIO port B bit 1
CCP2 I/O TTL Capture/Compare/PWM 2
E1 PD4 I/O TTL GPIO port D bit 4
CCP3 I/O TTL Capture/Compare/PWM 3
E2 PD5 I/O TTL GPIO port D bit 5
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 μF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
E3 LDO - Power
E10 VDD33 - Power
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
E11 CMOD0 I/O TTL
E12 PB0 I/O TTL GPIO port B bit 0
CCP0 I/O TTL Capture/Compare/PWM 0
F1 PD7 I/O TTL GPIO port D bit 7
C0o O TTL Analog comparator 0 output
F2 PD6 I/O TTL GPIO port D bit 6
Positive supply for most of the logic function,
including the processor core and most
peripherals.
F3 VDD25 - Power
522 March 17, 2008
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Signal Tables
Pin Number Pin Name Pin Type Buffer Type Description
F10 GND - Power Ground reference for logic and I/O pins.
F11 GND - Power Ground reference for logic and I/O pins.
F12 GND - Power Ground reference for logic and I/O pins.
G1 PD0 I/O TTL GPIO port D bit 0
CAN0Rx I TTL CAN module 0 receive
G2 PD1 I/O TTL GPIO port D bit 1
CAN0Tx O TTL CAN module 0 transmit
Positive supply for most of the logic function,
including the processor core and most
peripherals.
G3 VDD25 - Power
G10 VDD33 - Power
G11 VDD33 - Power
G12 VDD33 - Power
H1 PD3 I/O TTL GPIO port D bit 3
UART module 1 transmit. When in IrDA mode,
this signal has IrDA modulation.
U1Tx O TTL
H2 PD2 I/O TTL GPIO port D bit 2
UART module 1 receive. When in IrDA mode,
this signal has IrDA modulation.
U1Rx I TTL
H3 GND - Power Ground reference for logic and I/O pins.
H10 VDD33 - Power
H11 RST I TTL System reset input.
H12 PF1 I/O TTL GPIO port F bit 1
J1 XTALNPHY O TTL XTALN of the Ethernet PHY
J2 XTALPPHY I TTL XTALP of the Ethernet PHY
J3 GND - Power Ground reference for logic and I/O pins.
J10 GND - Power Ground reference for logic and I/O pins.
J11 PF2 I/O TTL GPIO port F bit 2
LED1 O TTL MII LED 1
J12 PF3 I/O TTL GPIO port F bit 3
LED0 O TTL MII LED 0
K1 NC - - No connect
K2 NC - - No connect
K3 GNDPHY I TTL GND of the Ethernet PHY
K4 GNDPHY I TTL GND of the Ethernet PHY
K5 GND - Power Ground reference for logic and I/O pins.
K6 GND - Power Ground reference for logic and I/O pins.
K7 VDD33 - Power
K8 VDD33 - Power
K9 VDD33 - Power
K10 GND - Power Ground reference for logic and I/O pins.
March 17, 2008 523
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LM3S8933 Microcontroller
Pin Number Pin Name Pin Type Buffer Type Description
Hibernation Module oscillator crystal input or
an external clock reference input. Note that
this is either a 4.19-MHz crystal or a
32.768-kHz oscillator for the Hibernation
Module RTC. See the CLKSEL bit in the
HIBCTL register.
K11 XOSC0 I Analog
K12 XOSC1 O Analog Hibernation Module oscillator crystal output.
L1 PC4 I/O TTL GPIO port C bit 4
L2 PC7 I/O TTL GPIO port C bit 7
C2- I Analog Analog comparator 2 negative input
L3 PA0 I/O TTL GPIO port A bit 0
UART module 0 receive. When in IrDA mode,
this signal has IrDA modulation.
U0Rx I TTL
L4 PA3 I/O TTL GPIO port A bit 3
SSI0Fss I/O TTL SSI module 0 frame
L5 PA4 I/O TTL GPIO port A bit 4
SSI0Rx I TTL SSI module 0 receive
L6 PA6 I/O TTL GPIO port A bit 6
CCP1 I/O TTL Capture/Compare/PWM 1
L7 RXIN I Analog RXIN of the Ethernet PHY
L8 TXON O Analog TXON of the Ethernet PHY
L9 MDIO I/O TTL MDIO of the Ethernet PHY
L10 GND - Power Ground reference for logic and I/O pins.
Main oscillator crystal input or an external
clock reference input.
L11 OSC0 I Analog
Power source for the Hibernation Module. It
is normally connected to the positive terminal
of a battery and serves as the battery
backup/Hibernation Module power-source
supply.
L12 VBAT - Power
M1 PC5 I/O TTL GPIO port C bit 5
C1+ I Analog Analog comparator positive input
C1o O TTL Analog comparator 1 output
M2 PC6 I/O TTL GPIO port C bit 6
C2+ I Analog Analog comparator positive input
M3 PA1 I/O TTL GPIO port A bit 1
UART module 0 transmit. When in IrDA mode,
this signal has IrDA modulation.
U0Tx O TTL
M4 PA2 I/O TTL GPIO port A bit 2
SSI0Clk I/O TTL SSI module 0 clock
M5 PA5 I/O TTL GPIO port A bit 5
SSI0Tx O TTL SSI module 0 transmit
M6 PA7 I/O TTL GPIO port A bit 7
M7 RXIP I Analog RXIP of the Ethernet PHY
M8 TXOP O Analog TXOP of the Ethernet PHY
M9 PF0 I/O TTL GPIO port F bit 0
524 March 17, 2008
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Signal Tables
Pin Number Pin Name Pin Type Buffer Type Description
An external input that brings the processor out
of hibernate mode when asserted.
M10 WAKE I OD
M11 OSC1 O Analog Main oscillator crystal output.
An output that indicates the processor is in
hibernate mode.
M12 HIB O TTL
Table 20-6. Signals by Signal Name
Pin Name Pin Number Pin Type Buffer Type Description
ADC0 B1 I Analog Analog-to-digital converter input 0.
ADC1 A1 I Analog Analog-to-digital converter input 1.
ADC2 B3 I Analog Analog-to-digital converter input 2.
ADC3 B2 I Analog Analog-to-digital converter input 3.
C0+ A7 I Analog Analog comparator 0 positive input
C0- A6 I Analog Analog comparator 0 negative input
C0o F1 O TTL Analog comparator 0 output
C1+ M1 I Analog Analog comparator positive input
C1- B7 I Analog Analog comparator 1 negative input
C1o M1 O TTL Analog comparator 1 output
C2+ M2 I Analog Analog comparator positive input
C2- L2 I Analog Analog comparator 2 negative input
CAN0Rx G1 I TTL CAN module 0 receive
CAN0Tx G2 O TTL CAN module 0 transmit
CCP0 E12 I/O TTL Capture/Compare/PWM 0
CCP1 L6 I/O TTL Capture/Compare/PWM 1
CCP2 D12 I/O TTL Capture/Compare/PWM 2
CCP3 E1 I/O TTL Capture/Compare/PWM 3
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD0 E11 I/O TTL
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1 B10 I/O TTL
GND C4 - Power Ground reference for logic and I/O pins.
GND C5 - Power Ground reference for logic and I/O pins.
GND H3 - Power Ground reference for logic and I/O pins.
GND J3 - Power Ground reference for logic and I/O pins.
GND K5 - Power Ground reference for logic and I/O pins.
GND K6 - Power Ground reference for logic and I/O pins.
GND L10 - Power Ground reference for logic and I/O pins.
GND K10 - Power Ground reference for logic and I/O pins.
GND J10 - Power Ground reference for logic and I/O pins.
GND F10 - Power Ground reference for logic and I/O pins.
GND F11 - Power Ground reference for logic and I/O pins.
GND B6 - Power Ground reference for logic and I/O pins.
GND F12 - Power Ground reference for logic and I/O pins.
March 17, 2008 525
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Pin Name Pin Number Pin Type Buffer Type Description
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
GNDA B5 - Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
GNDA A5 - Power
GNDPHY K3 I TTL GND of the Ethernet PHY
GNDPHY K4 I TTL GND of the Ethernet PHY
GNDPHY C8 I TTL GND of the Ethernet PHY
GNDPHY C9 I TTL GND of the Ethernet PHY
An output that indicates the processor is in
hibernate mode.
HIB M12 O TTL
I2C0SCL C11 I/O OD I2C module 0 clock
I2C0SDA C12 I/O OD I2C module 0 data
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 μF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
LDO E3 - Power
LED0 J12 O TTL MII LED 0
LED1 J11 O TTL MII LED 1
MDIO L9 I/O TTL MDIO of the Ethernet PHY
NC A2 - - No connect
NC A3 - - No connect
NC B4 - - No connect
NC A4 - - No connect
NC A11 - - No connect
NC B12 - - No connect
NC B11 - - No connect
NC A12 - - No connect
NC K1 - - No connect
NC K2 - - No connect
Main oscillator crystal input or an external
clock reference input.
OSC0 L11 I Analog
OSC1 M11 O Analog Main oscillator crystal output.
PA0 L3 I/O TTL GPIO port A bit 0
PA1 M3 I/O TTL GPIO port A bit 1
PA2 M4 I/O TTL GPIO port A bit 2
PA3 L4 I/O TTL GPIO port A bit 3
PA4 L5 I/O TTL GPIO port A bit 4
PA5 M5 I/O TTL GPIO port A bit 5
526 March 17, 2008
Preliminary
Signal Tables
Pin Name Pin Number Pin Type Buffer Type Description
PA6 L6 I/O TTL GPIO port A bit 6
PA7 M6 I/O TTL GPIO port A bit 7
PB0 E12 I/O TTL GPIO port B bit 0
PB1 D12 I/O TTL GPIO port B bit 1
PB2 C11 I/O TTL GPIO port B bit 2
PB3 C12 I/O TTL GPIO port B bit 3
PB4 A6 I/O TTL GPIO port B bit 4
PB5 B7 I/O TTL GPIO port B bit 5
PB6 A7 I/O TTL GPIO port B bit 6
PB7 A8 I/O TTL GPIO port B bit 7
PC0 A9 I/O TTL GPIO port C bit 0
PC1 B9 I/O TTL GPIO port C bit 1
PC2 B8 I/O TTL GPIO port C bit 2
PC3 A10 I/O TTL GPIO port C bit 3
PC4 L1 I/O TTL GPIO port C bit 4
PC5 M1 I/O TTL GPIO port C bit 5
PC6 M2 I/O TTL GPIO port C bit 6
PC7 L2 I/O TTL GPIO port C bit 7
PD0 G1 I/O TTL GPIO port D bit 0
PD1 G2 I/O TTL GPIO port D bit 1
PD2 H2 I/O TTL GPIO port D bit 2
PD3 H1 I/O TTL GPIO port D bit 3
PD4 E1 I/O TTL GPIO port D bit 4
PD5 E2 I/O TTL GPIO port D bit 5
PD6 F2 I/O TTL GPIO port D bit 6
PD7 F1 I/O TTL GPIO port D bit 7
PE4 D1 I/O TTL GPIO port E bit 4
PE5 D2 I/O TTL GPIO port E bit 5
PE6 C2 I/O TTL GPIO port E bit 6
PE7 C1 I/O TTL GPIO port E bit 7
PF0 M9 I/O TTL GPIO port F bit 0
PF1 H12 I/O TTL GPIO port F bit 1
PF2 J11 I/O TTL GPIO port F bit 2
PF3 J12 I/O TTL GPIO port F bit 3
RST H11 I TTL System reset input.
RXIN L7 I Analog RXIN of the Ethernet PHY
RXIP M7 I Analog RXIP of the Ethernet PHY
SSI0Clk M4 I/O TTL SSI module 0 clock
SSI0Fss L4 I/O TTL SSI module 0 frame
SSI0Rx L5 I TTL SSI module 0 receive
SSI0Tx M5 O TTL SSI module 0 transmit
SWCLK A9 I TTL JTAG/SWD CLK
March 17, 2008 527
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LM3S8933 Microcontroller
Pin Name Pin Number Pin Type Buffer Type Description
SWDIO B9 I/O TTL JTAG TMS and SWDIO
SWO A10 O TTL JTAG TDO and SWO
TCK A9 I TTL JTAG/SWD CLK
TDI B8 I TTL JTAG TDI
TDO A10 O TTL JTAG TDO and SWO
TMS B9 I/O TTL JTAG TMS and SWDIO
TRST A8 I TTL JTAG TRSTn
TXON L8 O Analog TXON of the Ethernet PHY
TXOP M8 O Analog TXOP of the Ethernet PHY
UART module 0 receive. When in IrDA mode,
this signal has IrDA modulation.
U0Rx L3 I TTL
UART module 0 transmit. When in IrDA mode,
this signal has IrDA modulation.
U0Tx M3 O TTL
UART module 1 receive. When in IrDA mode,
this signal has IrDA modulation.
U1Rx H2 I TTL
UART module 1 transmit. When in IrDA mode,
this signal has IrDA modulation.
U1Tx H1 O TTL
Power source for the Hibernation Module. It
is normally connected to the positive terminal
of a battery and serves as the battery
backup/Hibernation Module power-source
supply.
VBAT L12 - Power
VCCPHY C10 I TTL VCC of the Ethernet PHY
VCCPHY D10 I TTL VCC of the Ethernet PHY
VCCPHY D11 I TTL VCC of the Ethernet PHY
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 C3 - Power
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 D3 - Power
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 F3 - Power
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 G3 - Power
VDD33 K7 - Power
VDD33 G12 - Power
VDD33 K8 - Power
VDD33 K9 - Power
VDD33 H10 - Power
VDD33 G10 - Power
VDD33 E10 - Power
VDD33 G11 - Power
528 March 17, 2008
Preliminary
Signal Tables
Pin Name Pin Number Pin Type Buffer Type Description
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
VDDA C6 - Power
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
VDDA C7 - Power
An external input that brings the processor out
of hibernate mode when asserted.
WAKE M10 I OD
Hibernation Module oscillator crystal input or
an external clock reference input. Note that
this is either a 4.19-MHz crystal or a
32.768-kHz oscillator for the Hibernation
Module RTC. See the CLKSEL bit in the
HIBCTL register.
XOSC0 K11 I Analog
XOSC1 K12 O Analog Hibernation Module oscillator crystal output.
XTALNPHY J1 O TTL XTALN of the Ethernet PHY
XTALPPHY J2 I TTL XTALP of the Ethernet PHY
Table 20-7. Signals by Function, Except for GPIO
Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
ADC ADC0 B1 I Analog Analog-to-digital converter input 0.
ADC1 A1 I Analog Analog-to-digital converter input 1.
ADC2 B3 I Analog Analog-to-digital converter input 2.
ADC3 B2 I Analog Analog-to-digital converter input 3.
Analog C0+ A7 I Analog Analog comparator 0 positive input
Comparators C0- A6 I Analog Analog comparator 0 negative input
C0o F1 O TTL Analog comparator 0 output
C1+ M1 I Analog Analog comparator positive input
C1- B7 I Analog Analog comparator 1 negative input
C1o M1 O TTL Analog comparator 1 output
C2+ M2 I Analog Analog comparator positive input
C2- L2 I Analog Analog comparator 2 negative input
Controller Area CAN0Rx G1 I TTL CAN module 0 receive
Network CAN0Tx G2 O TTL CAN module 0 transmit
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Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
Ethernet PHY GNDPHY K3 I TTL GND of the Ethernet PHY
GNDPHY K4 I TTL GND of the Ethernet PHY
GNDPHY C8 I TTL GND of the Ethernet PHY
GNDPHY C9 I TTL GND of the Ethernet PHY
LED0 J12 O TTL MII LED 0
LED1 J11 O TTL MII LED 1
MDIO L9 I/O TTL MDIO of the Ethernet PHY
RXIN L7 I Analog RXIN of the Ethernet PHY
RXIP M7 I Analog RXIP of the Ethernet PHY
TXON L8 O Analog TXON of the Ethernet PHY
TXOP M8 O Analog TXOP of the Ethernet PHY
VCCPHY C10 I TTL VCC of the Ethernet PHY
VCCPHY D10 I TTL VCC of the Ethernet PHY
VCCPHY D11 I TTL VCC of the Ethernet PHY
XTALNPHY J1 O TTL XTALN of the Ethernet PHY
XTALPPHY J2 I TTL XTALP of the Ethernet PHY
General-Purpose CCP0 E12 I/O TTL Capture/Compare/PWM 0
Timers CCP1 L6 I/O TTL Capture/Compare/PWM 1
CCP2 D12 I/O TTL Capture/Compare/PWM 2
CCP3 E1 I/O TTL Capture/Compare/PWM 3
I2C I2C0SCL C11 I/O OD I2C module 0 clock
I2C0SDA C12 I/O OD I2C module 0 data
JTAG/SWD/SWO SWCLK A9 I TTL JTAG/SWD CLK
SWDIO B9 I/O TTL JTAG TMS and SWDIO
SWO A10 O TTL JTAG TDO and SWO
TCK A9 I TTL JTAG/SWD CLK
TDI B8 I TTL JTAG TDI
TDO A10 O TTL JTAG TDO and SWO
TMS B9 I/O TTL JTAG TMS and SWDIO
530 March 17, 2008
Preliminary
Signal Tables
Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
Power GND C4 - Power Ground reference for logic and I/O pins.
GND C5 - Power Ground reference for logic and I/O pins.
GND H3 - Power Ground reference for logic and I/O pins.
GND J3 - Power Ground reference for logic and I/O pins.
GND K5 - Power Ground reference for logic and I/O pins.
GND K6 - Power Ground reference for logic and I/O pins.
GND L10 - Power Ground reference for logic and I/O pins.
GND K10 - Power Ground reference for logic and I/O pins.
GND J10 - Power Ground reference for logic and I/O pins.
GND F10 - Power Ground reference for logic and I/O pins.
GND F11 - Power Ground reference for logic and I/O pins.
GND B6 - Power Ground reference for logic and I/O pins.
GND F12 - Power Ground reference for logic and I/O pins.
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
GNDA B5 - Power
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
GNDA A5 - Power
An output that indicates the processor is in
hibernate mode.
HIB M12 O TTL
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 μF or greater. When the on-chip LDO is
used to provide power to the logic, the LDO pin
must also be connected to the VDD25 pins at the
board level in addition to the decoupling
capacitor(s).
LDO E3 - Power
Power source for the Hibernation Module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation Module power-source supply.
VBAT L12 - Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 C3 - Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 D3 - Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 F3 - Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 G3 - Power
VDD33 K7 - Power
VDD33 G12 - Power
VDD33 K8 - Power
VDD33 K9 - Power
VDD33 H10 - Power
VDD33 G10 - Power
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LM3S8933 Microcontroller
Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
VDD33 E10 - Power
VDD33 G11 - Power
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
VDDA C6 - Power
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
VDDA C7 - Power
An external input that brings the processor out of
hibernate mode when asserted.
WAKE M10 I OD
SSI SSI0Clk M4 I/O TTL SSI module 0 clock
SSI0Fss L4 I/O TTL SSI module 0 frame
SSI0Rx L5 I TTL SSI module 0 receive
SSI0Tx M5 O TTL SSI module 0 transmit
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
System Control & CMOD0 E11 I/O TTL
Clocks
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1 B10 I/O TTL
Main oscillator crystal input or an external clock
reference input.
OSC0 L11 I Analog
OSC1 M11 O Analog Main oscillator crystal output.
RST H11 I TTL System reset input.
TRST A8 I TTL JTAG TRSTn
Hibernation Module oscillator crystal input or an
external clock reference input. Note that this is
either a 4.19-MHz crystal or a 32.768-kHz oscillator
for the Hibernation Module RTC. See the CLKSEL
bit in the HIBCTL register.
XOSC0 K11 I Analog
XOSC1 K12 O Analog Hibernation Module oscillator crystal output.
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
UART U0Rx L3 I TTL
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U0Tx M3 O TTL
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
U1Rx H2 I TTL
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U1Tx H1 O TTL
Table 20-8. GPIO Pins and Alternate Functions
GPIO Pin Pin Number Multiplexed Function Multiplexed Function
PA0 L3 U0Rx
PA1 M3 U0Tx
PA2 M4 SSI0Clk
PA3 L4 SSI0Fss
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Signal Tables
GPIO Pin Pin Number Multiplexed Function Multiplexed Function
PA4 L5 SSI0Rx
PA5 M5 SSI0Tx
PA6 L6 CCP1
PA7 M6
PB0 E12 CCP0
PB1 D12 CCP2
PB2 C11 I2C0SCL
PB3 C12 I2C0SDA
PB4 A6 C0-
PB5 B7 C1-
PB6 A7 C0+
PB7 A8 TRST
PC0 A9 TCK SWCLK
PC1 B9 TMS SWDIO
PC2 B8 TDI
PC3 A10 TDO SWO
PC4 L1
PC5 M1 C1+ C1o
PC6 M2 C2+
PC7 L2 C2-
PD0 G1 CAN0Rx
PD1 G2 CAN0Tx
PD2 H2 U1Rx
PD3 H1 U1Tx
PD4 E1 CCP3
PD5 E2
PD6 F2
PD7 F1 C0o
PE4 D1
PE5 D2
PE6 C2
PE7 C1
PF0 M9
PF1 H12
PF2 J11 LED1
PF3 J12 LED0
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21 Operating Characteristics
Table 21-1. Temperature Characteristics
Characteristica Symbol Value Unit
Industrial operating temperature range TA -40 to +85 °C
Extended operating temperature range TA -40 to +105 °C
a. Maximum storage temperature is 150°C.
Table 21-2. Thermal Characteristics
Characteristic Symbol Value Unit
Thermal resistance (junction to ambient)a ΘJA °C/W
Average junction temperatureb TJ TA + (PAVG • ΘJA) °C
a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator.
b. Power dissipation is a function of temperature.
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22 Electrical Characteristics
22.1 DC Characteristics
22.1.1 Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device.
Note: The device is not guaranteed to operate properly at the maximum ratings.
Table 22-1. Maximum Ratings
Characteristic Symbol Value Unit
a
Min Max
I/O supply voltage (VDD) VDD 0 4 V
Core supply voltage (VDD25) VDD25 0 4 V
Analog supply voltage (VDDA) VDDA 0 4 V
Battery supply voltage (VBAT) VBAT 0 4 V
Ethernet PHY supply voltage (VCCPHY) VCCPHY 0 4 V
Input voltage VIN -0.3 5.5 V
Maximum current per output pins I - 25 mA
a. Voltages are measured with respect to GND.
Important: This device contains circuitry to protect the inputs against damage due to high-static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are
connected to an appropriate logic voltage level (for example, either GND or VDD).
22.1.2 Recommended DC Operating Conditions
Table 22-2. Recommended DC Operating Conditions
Parameter Parameter Name Min Nom Max Unit
VDD I/O supply voltage 3.0 3.3 3.6 V
VDD25 Core supply voltage 2.25 2.5 2.75 V
VDDA Analog supply voltage 3.0 3.3 3.6 V
VBAT Battery supply voltage 2.3 3.0 3.6 V
VCCPHY Ethernet PHY supply voltage 3.0 3.3 3.6 V
VIH High-level input voltage 2.0 - 5.0 V
VIL Low-level input voltage -0.3 - 1.3 V
VSIH High-level input voltage for Schmitt trigger inputs 0.8 * VDD - VDD V
VSIL Low-level input voltage for Schmitt trigger inputs 0 - 0.2 * VDD V
VOH High-level output voltage 2.4 - - V
VOL Low-level output voltage - - 0.4 V
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Parameter Parameter Name Min Nom Max Unit
IOH High-level source current, VOH=2.4 V
2-mA Drive 2.0 - - mA
4-mA Drive 4.0 - - mA
8-mA Drive 8.0 - - mA
IOL Low-level sink current, VOL=0.4 V
2-mA Drive 2.0 - - mA
4-mA Drive 4.0 - - mA
8-mA Drive 8.0 - - mA
22.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics
Table 22-3. LDO Regulator Characteristics
Parameter Parameter Name Min Nom Max Unit
VLDOOUT Programmable internal (logic) power supply output value 2.25 2.5 2.75 V
Output voltage accuracy - 2% - %
tPON Power-on time - - 100 μs
tON Time on - - 200 μs
tOFF Time off - - 100 μs
VSTEP Step programming incremental voltage - 50 - mV
CLDO External filter capacitor size for internal power supply 1.0 - 3.0 μF
22.1.4 Power Specifications
The power measurements specified in the tables that follow are run on the core processor using
SRAM with the following specifications (except as noted):
■ VDD = 3.3 V
■ VDD25 = 2.50 V
■ VBAT = 3.0 V
■ VDDA = 3.3 V
■ VDDPHY = 3.3 V
■ Temperature = 25°C
■ Clock Source (MOSC) =3.579545 MHz Crystal Oscillator
■ Main oscillator (MOSC) = enabled
■ Internal oscillator (IOSC) = disabled
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Table 22-4. Detailed Power Specifications
3.3 V VDD, VDDA, 2.5 V VDD25 3.0 V VBAT Unit
VDDPHY
Parameter Conditions
Name
Parameter
Nom Max Nom Max Nom Max
VDD25 = 2.50 V 48 pendinga 108 pendinga 0 pendinga mA
Code= while(1){} executed in
Flash
Peripherals = All ON
System Clock = 50 MHz (with
PLL)
Run mode 1
(Flash loop)
IDD_RUN
VDD25 = 2.50 V 5 pendinga 52 pendinga 0 pendinga mA
Code= while(1){} executed in
Flash
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
Run mode 2
(Flash loop)
VDD25 = 2.50 V 48 pendinga 100 pendinga 0 pendinga mA
Code= while(1){} executed in
SRAM
Peripherals = All ON
System Clock = 50 MHz (with
PLL)
Run mode 1
(SRAM loop)
VDD25 = 2.50 V 5 pendinga 45 pendinga 0 pendinga mA
Code= while(1){} executed in
SRAM
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
Run mode 2
(SRAM loop)
VDD25 = 2.50 V 5 pendinga 16 pendinga 0 pendinga mA
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
IDD_SLEEP Sleep mode
LDO = 2.25 V 4.6 pendinga 0.21 pendinga 0 pendinga mA
Peripherals = All OFF
System Clock = IOSC30KHZ/64
Deep-Sleep
mode
IDD_DEEPSLEEP
VBAT = 3.0 V 0 pendinga 0 pendinga 16 pendinga μA
VDD = 0 V
VDD25 = 0 V
VDDA = 0 V
VDDPHY = 0 V
Peripherals = All OFF
System Clock = OFF
Hibernate Module = 32 kHz
Hibernate
mode
IDD_HIBERNATE
a. Pending characterization completion.
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22.1.5 Flash Memory Characteristics
Table 22-5. Flash Memory Characteristics
Parameter Parameter Name Min Nom Max Unit
PECYC Number of guaranteed program/erase cycles before failurea 10,000 100,000 - cycles
Data retention at average operating temperature of 85˚C (industrial) or 105˚C 10 - - years
(extended)
TRET
TPROG Word program time 20 - - μs
TERASE Page erase time 20 - - ms
TME Mass erase time 200 - - ms
a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1.
22.2 AC Characteristics
22.2.1 Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements. Timing
measurements are for 4-mA drive strength.
Figure 22-1. Load Conditions
CL = 50 pF
GND
pin
22.2.2 Clocks
Table 22-6. Phase Locked Loop (PLL) Characteristics
Parameter Parameter Name Min Nom Max Unit
fref_crystal Crystal referencea 3.579545 - 8.192 MHz
fref_ext External clock referencea 3.579545 - 8.192 MHz
fpll PLL frequencyb - 400 - MHz
TREADY PLL lock time - - 0.5 ms
a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration
(RCC) register.
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register.
Table 22-7. Clock Characteristics
Parameter Parameter Name Min Nom Max Unit
fIOSC Internal 12 MHz oscillator frequency 8.4 12 15.6 MHz
fIOSC30KHZ Internal 30 KHz oscillator frequency 21 30 39 KHz
fXOSC Hibernation module oscillator frequency - 4.194304 - MHz
fXOSC_XTAL Crystal reference for hibernation oscillator - 4.194304 - MHz
fXOSC_EXT External clock reference for hibernation module - 32.768 - KHz
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Parameter Parameter Name Min Nom Max Unit
fMOSC Main oscillator frequency 1 - 8 MHz
tMOSC_per Main oscillator period 125 - 1000 ns
Crystal reference using the main oscillator (PLL in BYPASS mode) 1 - 8 MHz
a
fref_crystal_bypass
fref_ext_bypass External clock reference (PLL in BYPASS mode)a 0 - 50 MHz
fsystem_clock System clock 0 - 50 MHz
a. The ADC must be clocked from the PLL or directly from a 14-MHz to 18-MHz clock source to operate properly.
Table 22-8. Crystal Characteristics
Parameter Name Value Units
Frequency 8 6 4 3.5 MHz
Frequency tolerance ±50 ±50 ±50 ±50 ppm
Aging ±5 ±5 ±5 ±5 ppm/yr
Oscillation mode Parallel Parallel Parallel Parallel
Temperature stability (-40°C to 85°C) ±25 ±25 ±25 ±25 ppm
Temperature stability (-40°C to 105°C) ±25 ±25 ±25 ±25 ppm
Motional capacitance (typ) 27.8 37.0 55.6 63.5 pF
Motional inductance (typ) 14.3 19.1 28.6 32.7 mH
Equivalent series resistance (max) 120 160 200 220 Ω
Shunt capacitance (max) 10 10 10 10 pF
Load capacitance (typ) 16 16 16 16 pF
Drive level (typ) 100 100 100 100 μW
22.2.3 Analog-to-Digital Converter
Table 22-9. ADC Characteristics
Parameter Parameter Name Min Nom Max Unit
VADCIN Maximum single-ended, full-scale analog input voltage - - 3.0 V
Minimum single-ended, full-scale analog input voltage - - 0 V
Maximum differential, full-scale analog input voltage - - 1.5 V
Minimum differential, full-scale analog input voltage - - -1.5 V
CADCIN Equivalent input capacitance - 1 - pF
N Resolution - 10 - bits
fADC ADC internal clock frequency 14 16 18 MHz
tADCCONV Conversion time - - 16 tADCcyclesa
f ADCCONV Conversion rate 875 1000 1125 k samples/s
INL Integral nonlinearity - - ±1 LSB
DNL Differential nonlinearity - - ±1 LSB
OFF Offset - - ±1 LSB
GAIN Gain - - ±1 LSB
a. tADC= 1/fADC clock
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22.2.4 Analog Comparator
Table 22-10. Analog Comparator Characteristics
Parameter Parameter Name Min Nom Max Unit
VOS Input offset voltage - ±10 ±25 mV
VCM Input common mode voltage range 0 - VDD-1.5 V
CMRR Common mode rejection ratio 50 - - dB
TRT Response time - - 1 μs
TMC Comparator mode change to Output Valid - - 10 μs
Table 22-11. Analog Comparator Voltage Reference Characteristics
Parameter Parameter Name Min Nom Max Unit
RHR Resolution high range - VDD/32 - LSB
RLR Resolution low range - VDD/24 - LSB
AHR Absolute accuracy high range - - ±1/2 LSB
ALR Absolute accuracy low range - - ±1/4 LSB
22.2.5 I2C
Table 22-12. I2C Characteristics
Parameter No. Parameter Parameter Name Min Nom Max Unit
I1a tSCH Start condition hold time 36 - - system clocks
I2a tLP Clock Low period 36 - - system clocks
I3b tSRT I2CSCL/I2CSDA rise time (VIL =0.5 V to V IH =2.4 V) - - (see note b) ns
I4a tDH Data hold time 2 - - system clocks
I5c tSFT I2CSCL/I2CSDA fall time (VIH =2.4 V to V IL =0.5 V) - 9 10 ns
I6a tHT Clock High time 24 - - system clocks
I7a tDS Data setup time 18 - - system clocks
Start condition setup time (for repeated start condition 36 - - system clocks
only)
I8a tSCSR
I9a tSCS Stop condition setup time 24 - - system clocks
a. Values depend on the value programmed into the TPR bit in the I2C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
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Figure 22-2. I2C Timing
I2CSCL
I2CSDA
I1
I2
I4
I6
I7 I8
I5
I3 I9
22.2.6 Ethernet Controller
Table 22-13. 100BASE-TX Transmitter Characteristicsa
Parameter Name Min Nom Max Unit
Peak output amplitude 950 - 1050 mVpk
Output amplitude symmetry 0.98 - 1.02 mVpk
Output overshoot - - 5 %
Rise/Fall time 3 - 5 ns
Rise/Fall time imbalance - - 500 ps
Duty cycle distortion - - - ps
Jitter - - 1.4 ns
a. Measured at the line side of the transformer.
Table 22-14. 100BASE-TX Transmitter Characteristics (informative)a
Parameter Name Min Nom Max Unit
Return loss 16 - - dB
Open-circuit inductance 350 - - μs
a. The specifications in this table are included for information only. They are mainly a function of the external transformer
and termination resistors used for measurements.
Table 22-15. 100BASE-TX Receiver Characteristics
Parameter Name Min Nom Max Unit
Signal detect assertion threshold 600 700 mVppd
Signal detect de-assertion threshold 350 425 - mVppd
Differential input resistance 20 - - kΩ
Jitter tolerance (pk-pk) 4 - - ns
Baseline wander tracking -75 - +75 %
Signal detect assertion time - - 1000 μs
Signal detect de-assertion time - - 4 μs
Table 22-16. 10BASE-T Transmitter Characteristicsa
Parameter Name Min Nom Max Unit
Peak differential output signal 2.2 - 2.8 V
Harmonic content 27 - - dB
Link pulse width - 100 - ns
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Parameter Name Min Nom Max Unit
300 - ns
350
Start-of-idle pulse width -
a. The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using
the procedures found in Clause 14 of IEEE 802.3.
Table 22-17. 10BASE-T Transmitter Characteristics (informative)a
Parameter Name Min Nom Max Unit
Output return loss 15 - - dB
Output impedance balance 29-17log(f/10) - - dB
Peak common-mode output voltage - - 50 mV
Common-mode rejection - - 100 mV
Common-mode rejection jitter - - 1 ns
a. The specifications in this table are included for information only. They are mainly a function of the external transformer
and termination resistors used for measurements.
Table 22-18. 10BASE-T Receiver Characteristics
Parameter Name Min Nom Max Unit
DLL phase acquisition time - 10 - BT
Jitter tolerance (pk-pk) 30 - - ns
Input squelched threshold 500 600 700 mVppd
Input unsquelched threshold 275 350 425 mVppd
Differential input resistance - 20 - kΩ
Bit error ratio - 10-10 - -
Common-mode rejection 25 - - V
Table 22-19. Isolation Transformersa
Name Value Condition
Turns ratio 1 CT : 1 CT +/- 5%
Open-circuit inductance 350 uH (min) @ 10 mV, 10 kHz
Leakage inductance 0.40 uH (max) @ 1 MHz (min)
Inter-winding capacitance 25 pF (max)
DC resistance 0.9 Ohm (max)
Insertion loss 0.4 dB (typ) 0-65 MHz
HIPOT 1500 Vrms
a. Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common-mode
chokes are recommended for exceeding FCC requirements. This table gives the recommended line transformer
characteristics.
Note: The 100Base-TX amplitude specifications assume a transformer loss of 0.4 dB. For the
transmit line transformer with higher insertion losses, up to 1.2 dB of insertion loss can be
compensated by selecting the appropriate setting in the Transmit Amplitude Selection (TXO)
bits in the MR19 register.
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Table 22-20. Ethernet Reference Crystala
Name Value Condition
Frequency 25.00000 MHz
Frequency tolerance ±50 PPM
Aging ±2 PPM/yr
Temperature stability (-40° to 85°) ±5 PPM
Temperature stability (-40° to 105°) ±5 PPM
Oscillation mode Parallel resonance, fundamental mode
Parameters at 25° C ±2° C; Drive level = 0.5 mW
Drive level (typ) 50-100 μW
Shunt capacitance (max) 10 pF
Motional capacitance (min) 10 fF
Serious resistance (max) 60 Ω
Spurious response (max) > 5 dB below main within 500 kHz
a. If the internal crystal oscillator is used, select a crystal with the following characteristics.
Figure 22-3. External XTLP Oscillator Characteristics
Tclkper
Tr
Tclkhi Tclklo
Tf
Table 22-21. External XTLP Oscillator Characteristics
Parameter Name Symbol Min Nom Max Unit
XTLN Input Low Voltage XTLNILV - - 0.8 -
XTLP Frequencya XTLPf - 25.0 - -
XTLP Periodb Tclkper - 40 - -
60 %
60
40 -
40
XTLPDC XTLP Duty Cycle
Rise/Fall Time Tr , Tf - - 4.0 ns
Absolute Jitter - - 0.1 ns
a. IEEE 802.3 frequency tolerance ±50 ppm.
b. IEEE 802.3 frequency tolerance ±50 ppm.
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22.2.7 Hibernation Module
The Hibernation Module requires special system implementation considerations since it is intended
to power-down all other sections of its host device. The system power-supply distribution and
interfaces of the system must be driven to 0 VDC or powered down with the same regulator controlled
by HIB.
The regulators controlled by HIB are expected to have a settling time of 250 μs or less.
Table 22-22. Hibernation Module Characteristics
Parameter No Parameter Parameter Name Min Nom Max Unit
H1 tHIB_LOW Internal 32.768 KHz clock reference rising edge to /HIB asserted - 200 - μs
H2 tHIB_HIGH Internal 32.768 KHz clock reference rising edge to /HIB deasserted - 30 - μs
H3 tWAKE_ASSERT /WAKE assertion time 62 - - μs
H4 tWAKETOHIB /WAKE assert to /HIB desassert 62 - 124 μs
H5 tXOSC_SETTLE XOSC settling timea 20 - - ms
H6 tHIB_REG_WRITE Time for a write to non-volatile registers in HIB module to complete 92 - - μs
H7 tHIB_TO_VDD HIB deassert to VDD and VDD25 at minimum operational level - - 250 μs
a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care
must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance).
Figure 22-4. Hibernation Module Timing
32.768 KHz
(internal)
/HIB
H4
H1
/WAKE
H2
H3
22.2.8 Synchronous Serial Interface (SSI)
Table 22-23. SSI Characteristics
Parameter No. Parameter Parameter Name Min Nom Max Unit
S1 tclk_per SSIClk cycle time 2 - 65024 system clocks
S2 tclk_high SSIClk high time - 1/2 - t clk_per
S3 tclk_low SSIClk low time - 1/2 - t clk_per
S4 tclkrf SSIClk rise/fall time - 7.4 26 ns
S5 tDMd Data from master valid delay time 0 - 20 ns
S6 tDMs Data from master setup time 20 - - ns
S7 tDMh Data from master hold time 40 - - ns
S8 tDSs Data from slave setup time 20 - - ns
S9 tDSh Data from slave hold time 40 - - ns
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Figure 22-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement
SSIClk
SSIFss
SSITx
SSIRx MSB LSB
S2
S3
S1
S4
4 to 16 bits
Figure 22-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer
0
SSIClk
SSIFss
SSITx
SSIRx
MSB LSB
MSB LSB
S2
S3
S1
8-bit control
4 to 16 bits output data
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Figure 22-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1
SSIClk
(SPO=1)
SSITx
(master)
SSIRx
(slave) LSB
SSIClk
(SPO=0)
S2
S1
S4
SSIFss
LSB
S3
MSB
S5
S6 S7
S8 S9
MSB
22.2.9 JTAG and Boundary Scan
Table 22-24. JTAG Characteristics
Parameter No. Parameter Parameter Name Min Nom Max Unit
J1 fTCK TCK operational clock frequency 0 - 10 MHz
J2 tTCK TCK operational clock period 100 - - ns
J3 tTCK_LOW TCK clock Low time - tTCK - ns
J4 tTCK_HIGH TCK clock High time - tTCK - ns
J5 tTCK_R TCK rise time 0 - 10 ns
J6 tTCK_F TCK fall time 0 - 10 ns
J7 tTMS_SU TMS setup time to TCK rise 20 - - ns
J8 tTMS_HLD TMS hold time from TCK rise 20 - - ns
J9 tTDI_SU TDI setup time to TCK rise 25 - - ns
J10 tTDI_HLD TDI hold time from TCK rise 25 - - ns
J11 TCK fall to Data Valid from High-Z 2-mA drive - 23 35 ns
t TDO_ZDV 4-mA drive 15 26 ns
8-mA drive 14 25 ns
8-mA drive with slew rate control 18 29 ns
J12 TCK fall to Data Valid from Data Valid 2-mA drive - 21 35 ns
t TDO_DV 4-mA drive 14 25 ns
8-mA drive 13 24 ns
8-mA drive with slew rate control 18 28 ns
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Parameter No. Parameter Parameter Name Min Nom Max Unit
J13 TCK fall to High-Z from Data Valid 2-mA drive - 9 11 ns
t TDO_DVZ 4-mA drive 7 9 ns
8-mA drive 6 8 ns
8-mA drive with slew rate control 7 9 ns
J14 tTRST TRST assertion time 100 - - ns
J15 tTRST_SU TRST setup time to TCK rise 10 - - ns
Figure 22-8. JTAG Test Clock Input Timing
TCK
J6 J5
J3 J4
J2
Figure 22-9. JTAG Test Access Port (TAP) Timing
TDO Output Valid
TCK
TDO Output Valid
J12
TDO
TDI
TMS
TDI Input Valid TDI Input Valid
J13
J9 J10
TMS Input Valid
J9 J10
TMS Input Valid
J11
J7 J8 J7 J8
Figure 22-10. JTAG TRST Timing
TCK
J14 J15
TRST
22.2.10 General-Purpose I/O
Note: All GPIOs are 5 V-tolerant.
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Table 22-25. GPIO Characteristics
Parameter Parameter Name Condition Min Nom Max Unit
tGPIOR GPIO Rise Time (from 20% to 80% of VDD) 2-mA drive - 17 26 ns
4-mA drive 9 13 ns
8-mA drive 6 9 ns
8-mA drive with slew rate control 10 12 ns
tGPIOF GPIO Fall Time (from 80% to 20% of VDD) 2-mA drive - 17 25 ns
4-mA drive 8 12 ns
8-mA drive 6 10 ns
8-mA drive with slew rate control 11 13 ns
22.2.11 Reset
Table 22-26. Reset Characteristics
Parameter No. Parameter Parameter Name Min Nom Max Unit
R1 VTH Reset threshold - 2.0 - V
R2 VBTH Brown-Out threshold 2.85 2.9 2.95 V
R3 TPOR Power-On Reset timeout - 10 - ms
R4 TBOR Brown-Out timeout - 500 - μs
R5 TIRPOR Internal reset timeout after POR 6 - 11 ms
R6 TIRBOR Internal reset timeout after BORa 0 - 1 μs
R7 TIRHWR Internal reset timeout after hardware reset (RST pin) 0 - 1 ms
R8 TIRSWR Internal reset timeout after software-initiated system reset a 2.5 - 20 μs
R9 TIRWDR Internal reset timeout after watchdog reseta 2.5 - 20 μs
R10 TVDDRISE Supply voltage (VDD) rise time (0V-3.3V) - - 100 ms
R11 TMIN Minimum RST pulse width 2 - - μs
a. 20 * t MOSC_per
Figure 22-11. External Reset Timing (RST)
RST
/Reset
(Internal)
R11 R7
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Figure 22-12. Power-On Reset Timing
VDD
/POR
(Internal)
/Reset
(Internal)
R3
R1
R5
Figure 22-13. Brown-Out Reset Timing
VDD
/BOR
(Internal)
/Reset
(Internal)
R2
R4
R6
Figure 22-14. Software Reset Timing
R8
SW Reset
/Reset
(Internal)
Figure 22-15. Watchdog Reset Timing
WDOG
Reset
(Internal)
/Reset
(Internal)
R9
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23 Package Information
Figure 23-1. 100-Pin LQFP Package
Note: The following notes apply to the package drawing.
1. All dimensions shown in mm.
2. Dimensions shown are nominal with tolerances indicated.
3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane.
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Package Information
Body +2.00 mm Footprint, 1.4 mm package thickness
Symbols Leads 100L
A Max. 1.60
A1 0.05 Min./0.15 Max.
A2 ±0.05 1.40
D ±0.20 16.00
D1 ±0.05 14.00
E ±0.20 16.00
E1 ±0.05 14.00
L ±0.15/-0.10 0.60
e Basic 0.50
b ±0.05 0.22
θ === 0˚~7˚
ddd Max. 0.08
ccc Max. 0.08
JEDEC Reference Drawing MS-026
Variation Designator BED
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Figure 23-2. 100-Ball BGA Package
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Package Information
Note: The following notes apply to the package drawing.
Symbols MIN NOM MAX
A 1.22 1.36 1.50
A1 0.29 0.34 0.39
A3 0.65 0.70 0.75
c 0.28 0.32 0.36
D 9.85 10.00 10.15
D1 8.80 BSC
E 9.85 10.00 10.15
E1 8.80 BSC
b 0.43 0.48 0.53
bbb .20
ddd .12
e 0.80 BSC
f - 0.60 -
M 12
n 108
REF: JEDEC MO-219F
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A Serial Flash Loader
A.1 Serial Flash Loader
The Stellaris® serial flash loader is a preprogrammed flash-resident utility used to download code
to the flash memory of a device without the use of a debug interface. The serial flash loader uses
a simple packet interface to provide synchronous communication with the device. The flash loader
runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used.
The two serial interfaces that can be used are the UART0 and SSI0 interfaces. For simplicity, both
the data format and communication protocol are identical for both serial interfaces.
A.2 Interfaces
Once communication with the flash loader is established via one of the serial interfaces, that interface
is used until the flash loader is reset or new code takes over. For example, once you start
communicating using the SSI port, communications with the flash loader via the UART are disabled
until the device is reset.
A.2.1 UART
The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial
format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is
automatically detected by the flash loader and can be any valid baud rate supported by the host
and the device. The auto detection sequence requires that the baud rate should be no more than
1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the
same as the hardware limitation for the maximum baud rate for any UART on a Stellaris® device
which is calculated as follows:
Max Baud Rate = System Clock Frequency / 16
In order to determine the baud rate, the serial flash loader needs to determine the relationship
between its own crystal frequency and the baud rate. This is enough information for the flash loader
to configure its UART to the same baud rate as the host. This automatic baud-rate detection allows
the host to use any valid baud rate that it wants to communicate with the device.
The method used to perform this automatic synchronization relies on the host sending the flash
loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can
use to calculate the ratios needed to program the UART to match the host’s baud rate. After the
host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader
returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received
after at least twice the time required to transfer the two bytes, the host can resend another pattern
of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader acknowledges that it has
received a synchronization pattern correctly. For example, the time to wait for data back from the
flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate
of 115200, this time is 2*(20/115200) or 0.35 ms.
A.2.2 SSI
The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications,
with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See “Frame
Formats” on page 339 in the SSI chapter for more information on formats for this transfer protocol.
Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI
clock can run. This allows the SSI clock to be at most 1/12 the crystal frequency of the board running
554 March 17, 2008
Preliminary
Serial Flash Loader
the flash loader. Since the host device is the master, the SSI on the flash loader device does not
need to determine the clock as it is provided directly by the host.
A.3 Packet Handling
All communications, with the exception of the UART auto-baud, are done via defined packets that
are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same
format for receiving and sending packets, including the method used to acknowledge successful or
unsuccessful reception of a packet.
A.3.1 Packet Format
All packets sent and received from the device use the following byte-packed format.
struct
{
unsigned char ucSize;
unsigned char ucCheckSum;
unsigned char Data[];
};
ucSize The first byte received holds the total size of the transfer including
the size and checksum bytes.
ucChecksum This holds a simple checksum of the bytes in the data buffer only.
The algorithm is Data[0]+Data[1]+…+ Data[ucSize-3].
Data This is the raw data intended for the device, which is formatted in
some form of command interface. There should be ucSize–2
bytes of data provided in this buffer to or from the device.
A.3.2 Sending Packets
The actual bytes of the packet can be sent individually or all at once; the only limitation is that
commands that cause flash memory access should limit the download sizes to prevent losing bytes
during flash programming. This limitation is discussed further in the section that describes the serial
flash loader command, COMMAND_SEND_DATA (see “COMMAND_SEND_DATA
(0x24)” on page 557).
Once the packet has been formatted correctly by the host, it should be sent out over the UART or
SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned
from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from
the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This
does not indicate that the actual contents of the command issued in the data portion of the packet
were valid, just that the packet was received correctly.
A.3.3 Receiving Packets
The flash loader sends a packet of data in the same format that it receives a packet. The flash loader
may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte
is the size of the packet followed by a checksum byte, and finally followed by the data itself. There
is no break in the data after the first non-zero byte is sent from the flash loader. Once the device
communicating with the flash loader receives all the bytes, it must either ACK or NAK the packet to
indicate that the transmission was successful. The appropriate response after sending a NAK to
the flash loader is to resend the command that failed and request the data again. If needed, the
host may send leading zeros before sending down the ACK/NAK signal to the flash loader, as the
March 17, 2008 555
Preliminary
LM3S8933 Microcontroller
flash loader only accepts the first non-zero data as a valid response. This zero padding is needed
by the SSI interface in order to receive data to or from the flash loader.
A.4 Commands
The next section defines the list of commands that can be sent to the flash loader. The first byte of
the data should always be one of the defined commands, followed by data or parameters as
determined by the command that is sent.
A.4.1 COMMAND_PING (0X20)
This command simply accepts the command and sets the global status to success. The format of
the packet is as follows:
Byte[0] = 0x03;
Byte[1] = checksum(Byte[2]);
Byte[2] = COMMAND_PING;
The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one
byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status,
the receipt of an ACK can be interpreted as a successful ping to the flash loader.
A.4.2 COMMAND_GET_STATUS (0x23)
This command returns the status of the last command that was issued. Typically, this command
should be sent after every command to ensure that the previous command was successful or to
properly respond to a failure. The command requires one byte in the data of the packet and should
be followed by reading a packet with one byte of data that contains a status code. The last step is
to ACK or NAK the received data so the flash loader knows that the data has been read.
Byte[0] = 0x03
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_GET_STATUS
A.4.3 COMMAND_DOWNLOAD (0x21)
This command is sent to the flash loader to indicate where to store data and how many bytes will
be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit
values that are both transferred MSB first. The first 32-bit value is the address to start programming
data into, while the second is the 32-bit size of the data that will be sent. This command also triggers
an erase of the full area to be programmed so this command takes longer than other commands.
This results in a longer time to receive the ACK/NAK back from the board. This command should
be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size
are valid for the device running the flash loader.
The format of the packet to send this command is a follows:
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_DOWNLOAD
Byte[3] = Program Address [31:24]
Byte[4] = Program Address [23:16]
Byte[5] = Program Address [15:8]
Byte[6] = Program Address [7:0]
Byte[7] = Program Size [31:24]
556 March 17, 2008
Preliminary
Serial Flash Loader
Byte[8] = Program Size [23:16]
Byte[9] = Program Size [15:8]
Byte[10] = Program Size [7:0]
A.4.4 COMMAND_SEND_DATA (0x24)
This command should only follow a COMMAND_DOWNLOAD command or another
COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands
automatically increment address and continue programming from the previous location. The caller
should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program
successfully and not overflow input buffers of the serial interfaces. The command terminates
programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been
received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to
ensure that the data was successfully programmed into the flash. If the flash loader sends a NAK
to this command, the flash loader does not increment the current address to allow retransmission
of the previous data.
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_SEND_DATA
Byte[3] = Data[0]
Byte[4] = Data[1]
Byte[5] = Data[2]
Byte[6] = Data[3]
Byte[7] = Data[4]
Byte[8] = Data[5]
Byte[9] = Data[6]
Byte[10] = Data[7]
A.4.5 COMMAND_RUN (0x22)
This command is used to tell the flash loader to execute from the address passed as the parameter
in this command. This command consists of a single 32-bit value that is interpreted as the address
to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK
signal back to the host device before actually executing the code at the given address. This allows
the host to know that the command was received successfully and the code is now running.
Byte[0] = 7
Byte[1] = checksum(Bytes[2:6])
Byte[2] = COMMAND_RUN
Byte[3] = Execute Address[31:24]
Byte[4] = Execute Address[23:16]
Byte[5] = Execute Address[15:8]
Byte[6] = Execute Address[7:0]
A.4.6 COMMAND_RESET (0x25)
This command is used to tell the flash loader device to reset. This is useful when downloading a
new image that overwrote the flash loader and wants to start from a full reset. Unlike the
COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set
up for the new code. It can also be used to reset the flash loader if a critical error occurs and the
host device wants to restart communication with the flash loader.
March 17, 2008 557
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LM3S8933 Microcontroller
Byte[0] = 3
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_RESET
The flash loader responds with an ACK signal back to the host device before actually executing the
software reset to the device running the flash loader. This allows the host to know that the command
was received successfully and the part will be reset.
558 March 17, 2008
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Serial Flash Loader
B Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
System Control
Base 0x400F.E000
DID0, type RO, offset 0x000, reset -
VER CLASS
MAJOR MINOR
PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD
BORIOR
LDOPCTL, type R/W, offset 0x034, reset 0x0000.0000
VADJ
RIS, type RO, offset 0x050, reset 0x0000.0000
PLLLRIS BORRIS
IMC, type R/W, offset 0x054, reset 0x0000.0000
PLLLIM BORIM
MISC, type R/W1C, offset 0x058, reset 0x0000.0000
PLLLMIS BORMIS
RESC, type R/W, offset 0x05C, reset -
LDO SW WDT BOR POR EXT
RCC, type R/W, offset 0x060, reset 0x0780.3AD1
ACG SYSDIV USESYSDIV
PWRDN BYPASS XTAL OSCSRC IOSCDIS MOSCDIS
PLLCFG, type RO, offset 0x064, reset -
F R
RCC2, type R/W, offset 0x070, reset 0x0780.2800
USERCC2 SYSDIV2
PWRDN2 BYPASS2 OSCSRC2
DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000
DSDIVORIDE
DSOSCSRC
DID1, type RO, offset 0x004, reset -
VER FAM PARTNO
PINCOUNT TEMP PKG ROHS QUAL
DC0, type RO, offset 0x008, reset 0x00FF.007F
SRAMSZ
FLASHSZ
DC1, type RO, offset 0x010, reset 0x0101.33FF
CAN0 ADC
MINSYSDIV MAXADCSPD MPU HIB TEMPSNS PLL WDT SWO SWD JTAG
DC2, type RO, offset 0x014, reset 0x070F.1013
COMP2 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0
I2C0 SSI0 UART1 UART0
DC3, type RO, offset 0x018, reset 0x0F0F.3FC0
CCP3 CCP2 CCP1 CCP0 ADC3 ADC2 ADC1 ADC0
C2PLUS C2MINUS C1O C1PLUS C1MINUS C0O C0PLUS C0MINUS
March 17, 2008 559
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LM3S8933 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DC4, type RO, offset 0x01C, reset 0x5100.007F
EPHY0 EMAC0 E1588
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
RCGC0, type R/W, offset 0x100, reset 0x00000040
CAN0 ADC
MAXADCSPD HIB WDT
SCGC0, type R/W, offset 0x110, reset 0x00000040
CAN0 ADC
MAXADCSPD HIB WDT
DCGC0, type R/W, offset 0x120, reset 0x00000040
CAN0 ADC
MAXADCSPD HIB WDT
RCGC1, type R/W, offset 0x104, reset 0x00000000
COMP2 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0
I2C0 SSI0 UART1 UART0
SCGC1, type R/W, offset 0x114, reset 0x00000000
COMP2 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0
I2C0 SSI0 UART1 UART0
DCGC1, type R/W, offset 0x124, reset 0x00000000
COMP2 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0
I2C0 SSI0 UART1 UART0
RCGC2, type R/W, offset 0x108, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
SCGC2, type R/W, offset 0x118, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
DCGC2, type R/W, offset 0x128, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
SRCR0, type R/W, offset 0x040, reset 0x00000000
CAN0 ADC
HIB WDT
SRCR1, type R/W, offset 0x044, reset 0x00000000
COMP2 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0
I2C0 SSI0 UART1 UART0
SRCR2, type R/W, offset 0x048, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Hibernation Module
Base 0x400F.C000
HIBRTCC, type RO, offset 0x000, reset 0x0000.0000
RTCC
RTCC
HIBRTCM0, type R/W, offset 0x004, reset 0xFFFF.FFFF
RTCM0
RTCM0
HIBRTCM1, type R/W, offset 0x008, reset 0xFFFF.FFFF
RTCM1
RTCM1
HIBRTCLD, type R/W, offset 0x00C, reset 0xFFFF.FFFF
RTCLD
RTCLD
560 March 17, 2008
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HIBCTL, type R/W, offset 0x010, reset 0x0000.0000
VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBREQ RTCEN
HIBIM, type R/W, offset 0x014, reset 0x0000.0000
EXTW LOWBAT RTCALT1 RTCALT0
HIBRIS, type RO, offset 0x018, reset 0x0000.0000
EXTW LOWBAT RTCALT1 RTCALT0
HIBMIS, type RO, offset 0x01C, reset 0x0000.0000
EXTW LOWBAT RTCALT1 RTCALT0
HIBIC, type R/W1C, offset 0x020, reset 0x0000.0000
EXTW LOWBAT RTCALT1 RTCALT0
HIBRTCT, type R/W, offset 0x024, reset 0x0000.7FFF
TRIM
HIBDATA, type R/W, offset 0x030-0x12C, reset 0x0000.0000
RTD
RTD
Internal Memory
Flash Control Offset
Base 0x400F.D000
FMA, type R/W, offset 0x000, reset 0x0000.0000
OFFSET
OFFSET
FMD, type R/W, offset 0x004, reset 0x0000.0000
DATA
DATA
FMC, type R/W, offset 0x008, reset 0x0000.0000
WRKEY
COMT MERASE ERASE WRITE
FCRIS, type RO, offset 0x00C, reset 0x0000.0000
PRIS ARIS
FCIM, type R/W, offset 0x010, reset 0x0000.0000
PMASK AMASK
FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000
PMISC AMISC
Internal Memory
System Control Offset
Base 0x400F.E000
USECRL, type R/W, offset 0x140, reset 0x31
USEC
FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
March 17, 2008 561
Preliminary
LM3S8933 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
USER_DBG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE
NW DATA
DATA DBG1 DBG0
USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF
NW DATA
DATA
USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF
NW DATA
DATA
FMPRE1, type R/W, offset 0x204, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE2, type R/W, offset 0x208, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE3, type R/W, offset 0x20C, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE2, type R/W, offset 0x408, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE3, type R/W, offset 0x40C, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
General-Purpose Input/Outputs (GPIOs)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIODATA, type R/W, offset 0x000, reset 0x0000.0000
DATA
GPIODIR, type R/W, offset 0x400, reset 0x0000.0000
DIR
GPIOIS, type R/W, offset 0x404, reset 0x0000.0000
IS
GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000
IBE
GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000
IEV
562 March 17, 2008
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOIM, type R/W, offset 0x410, reset 0x0000.0000
IME
GPIORIS, type RO, offset 0x414, reset 0x0000.0000
RIS
GPIOMIS, type RO, offset 0x418, reset 0x0000.0000
MIS
GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000
IC
GPIOAFSEL, type R/W, offset 0x420, reset -
AFSEL
GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF
DRV2
GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000
DRV4
GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000
DRV8
GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000
ODE
GPIOPUR, type R/W, offset 0x510, reset -
PUE
GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000
PDE
GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000
SRL
GPIODEN, type R/W, offset 0x51C, reset -
DEN
GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001
LOCK
LOCK
GPIOCR, type -, offset 0x524, reset -
CR
GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
March 17, 2008 563
Preliminary
LM3S8933 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061
PID0
GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
General-Purpose Timers
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000
GPTMCFG
GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000
TAAMS TACMR TAMR
GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000
TBAMS TBCMR TBMR
GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000
TBPWML TBOTE TBEVENT TBSTALL TBEN TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN
GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000
CBEIM CBMIM TBTOIM RTCIM CAEIM CAMIM TATOIM
GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000
CBERIS CBMRIS TBTORIS RTCRIS CAERIS CAMRIS TATORIS
564 March 17, 2008
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPTMMIS, type RO, offset 0x020, reset 0x0000.0000
CBEMIS CBMMIS TBTOMIS RTCMIS CAEMIS CAMMIS TATOMIS
GPTMICR, type W1C, offset 0x024, reset 0x0000.0000
CBECINT CBMCINT TBTOCINT RTCCINT CAECINT CAMCINT TATOCINT
GPTMTAILR, type R/W, offset 0x028, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
TAILRH
TAILRL
GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF
TBILRL
GPTMTAMATCHR, type R/W, offset 0x030, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
TAMRH
TAMRL
GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF
TBMRL
GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000
TAPSR
GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000
TBPSR
GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000
TAPSMR
GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000
TBPSMR
GPTMTAR, type RO, offset 0x048, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
TARH
TARL
GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF
TBRL
Watchdog Timer
Base 0x4000.0000
WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF
WDTLoad
WDTLoad
WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF
WDTValue
WDTValue
WDTCTL, type R/W, offset 0x008, reset 0x0000.0000
RESEN INTEN
WDTICR, type WO, offset 0x00C, reset -
WDTIntClr
WDTIntClr
WDTRIS, type RO, offset 0x010, reset 0x0000.0000
WDTRIS
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LM3S8933 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTMIS, type RO, offset 0x014, reset 0x0000.0000
WDTMIS
WDTTEST, type R/W, offset 0x418, reset 0x0000.0000
STALL
WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000
WDTLock
WDTLock
WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005
PID0
WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018
PID1
WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Analog-to-Digital Converter (ADC)
Base 0x4003.8000
ADCACTSS, type R/W, offset 0x000, reset 0x0000.0000
ASEN3 ASEN2 ASEN1 ASEN0
ADCRIS, type RO, offset 0x004, reset 0x0000.0000
INR3 INR2 INR1 INR0
566 March 17, 2008
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCIM, type R/W, offset 0x008, reset 0x0000.0000
MASK3 MASK2 MASK1 MASK0
ADCISC, type R/W1C, offset 0x00C, reset 0x0000.0000
IN3 IN2 IN1 IN0
ADCOSTAT, type R/W1C, offset 0x010, reset 0x0000.0000
OV3 OV2 OV1 OV0
ADCEMUX, type R/W, offset 0x014, reset 0x0000.0000
EM3 EM2 EM1 EM0
ADCUSTAT, type R/W1C, offset 0x018, reset 0x0000.0000
UV3 UV2 UV1 UV0
ADCSSPRI, type R/W, offset 0x020, reset 0x0000.3210
SS3 SS2 SS1 SS0
ADCPSSI, type WO, offset 0x028, reset -
SS3 SS2 SS1 SS0
ADCSAC, type R/W, offset 0x030, reset 0x0000.0000
AVG
ADCSSMUX0, type R/W, offset 0x040, reset 0x0000.0000
MUX7 MUX6 MUX5 MUX4
MUX3 MUX2 MUX1 MUX0
ADCSSCTL0, type R/W, offset 0x044, reset 0x0000.0000
TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
ADCSSFIFO0, type RO, offset 0x048, reset 0x0000.0000
DATA
ADCSSFIFO1, type RO, offset 0x068, reset 0x0000.0000
DATA
ADCSSFIFO2, type RO, offset 0x088, reset 0x0000.0000
DATA
ADCSSFIFO3, type RO, offset 0x0A8, reset 0x0000.0000
DATA
ADCSSFSTAT0, type RO, offset 0x04C, reset 0x0000.0100
FULL EMPTY HPTR TPTR
ADCSSFSTAT1, type RO, offset 0x06C, reset 0x0000.0100
FULL EMPTY HPTR TPTR
ADCSSFSTAT2, type RO, offset 0x08C, reset 0x0000.0100
FULL EMPTY HPTR TPTR
March 17, 2008 567
Preliminary
LM3S8933 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCSSFSTAT3, type RO, offset 0x0AC, reset 0x0000.0100
FULL EMPTY HPTR TPTR
ADCSSMUX1, type R/W, offset 0x060, reset 0x0000.0000
MUX3 MUX2 MUX1 MUX0
ADCSSMUX2, type R/W, offset 0x080, reset 0x0000.0000
MUX3 MUX2 MUX1 MUX0
ADCSSCTL1, type R/W, offset 0x064, reset 0x0000.0000
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
ADCSSCTL2, type R/W, offset 0x084, reset 0x0000.0000
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
ADCSSMUX3, type R/W, offset 0x0A0, reset 0x0000.0000
MUX0
ADCSSCTL3, type R/W, offset 0x0A4, reset 0x0000.0002
TS0 IE0 END0 D0
ADCTMLB, type R/W, offset 0x100, reset 0x0000.0000
LB
Universal Asynchronous Receivers/Transmitters (UARTs)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UARTDR, type R/W, offset 0x000, reset 0x0000.0000
OE BE PE FE DATA
UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000
OE BE PE FE
UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000
DATA
UARTFR, type RO, offset 0x018, reset 0x0000.0090
TXFE RXFF TXFF RXFE BUSY
UARTILPR, type R/W, offset 0x020, reset 0x0000.0000
ILPDVSR
UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000
DIVINT
UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000
DIVFRAC
UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000
SPS WLEN FEN STP2 EPS PEN BRK
568 March 17, 2008
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UARTCTL, type R/W, offset 0x030, reset 0x0000.0300
RXE TXE LBE SIRLP SIREN UARTEN
UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012
RXIFLSEL TXIFLSEL
UARTIM, type R/W, offset 0x038, reset 0x0000.0000
OEIM BEIM PEIM FEIM RTIM TXIM RXIM
UARTRIS, type RO, offset 0x03C, reset 0x0000.000F
OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS
UARTMIS, type RO, offset 0x040, reset 0x0000.0000
OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS
UARTICR, type W1C, offset 0x044, reset 0x0000.0000
OEIC BEIC PEIC FEIC RTIC TXIC RXIC
UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011
PID0
UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
March 17, 2008 569
Preliminary
LM3S8933 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Synchronous Serial Interface (SSI)
SSI0 base: 0x4000.8000
SSICR0, type R/W, offset 0x000, reset 0x0000.0000
SCR SPH SPO FRF DSS
SSICR1, type R/W, offset 0x004, reset 0x0000.0000
SOD MS SSE LBM
SSIDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
SSISR, type RO, offset 0x00C, reset 0x0000.0003
BSY RFF RNE TNF TFE
SSICPSR, type R/W, offset 0x010, reset 0x0000.0000
CPSDVSR
SSIIM, type R/W, offset 0x014, reset 0x0000.0000
TXIM RXIM RTIM RORIM
SSIRIS, type RO, offset 0x018, reset 0x0000.0008
TXRIS RXRIS RTRIS RORRIS
SSIMIS, type RO, offset 0x01C, reset 0x0000.0000
TXMIS RXMIS RTMIS RORMIS
SSIICR, type W1C, offset 0x020, reset 0x0000.0000
RTIC RORIC
SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022
PID0
SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
570 March 17, 2008
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Inter-Integrated Circuit (I2C) Interface
I2C Master
I2C Master 0 base: 0x4002.0000
I2CMSA, type R/W, offset 0x000, reset 0x0000.0000
SA R/S
I2CMCS, type RO, offset 0x004, reset 0x0000.0000
BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY
I2CMCS, type WO, offset 0x004, reset 0x0000.0000
ACK STOP START RUN
I2CMDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001
TPR
I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000
IM
I2CMRIS, type RO, offset 0x014, reset 0x0000.0000
RIS
I2CMMIS, type RO, offset 0x018, reset 0x0000.0000
MIS
I2CMICR, type WO, offset 0x01C, reset 0x0000.0000
IC
I2CMCR, type R/W, offset 0x020, reset 0x0000.0000
SFE MFE LPBK
March 17, 2008 571
Preliminary
LM3S8933 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Inter-Integrated Circuit (I2C) Interface
I2C Slave
I2C Slave 0 base: 0x4002.0800
I2CSOAR, type R/W, offset 0x000, reset 0x0000.0000
OAR
I2CSCSR, type RO, offset 0x004, reset 0x0000.0000
FBR TREQ RREQ
I2CSCSR, type WO, offset 0x004, reset 0x0000.0000
DA
I2CSDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
I2CSIMR, type R/W, offset 0x00C, reset 0x0000.0000
IM
I2CSRIS, type RO, offset 0x010, reset 0x0000.0000
RIS
I2CSMIS, type RO, offset 0x014, reset 0x0000.0000
MIS
I2CSICR, type WO, offset 0x018, reset 0x0000.0000
IC
Controller Area Network (CAN) Module
CAN0 base: 0x4004.0000
CANCTL, type R/W, offset 0x000, reset 0x0000.0001
Test CCE DAR EIE SIE IE INIT
CANSTS, type R/W, offset 0x004, reset 0x0000.0000
BOff EWarn EPass RxOK TxOK LEC
CANERR, type RO, offset 0x008, reset 0x0000.0000
RP REC TEC
CANBIT, type R/W, offset 0x00C, reset 0x0000.2301
TSeg2 TSeg1 SJW BRP
CANINT, type RO, offset 0x010, reset 0x0000.0000
IntId
CANTST, type R/W, offset 0x014, reset 0x0000.0000
Rx Tx LBack Silent Basic
CANBRPE, type R/W, offset 0x018, reset 0x0000.0000
BRPE
572 March 17, 2008
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CANIF1CRQ, type R/W, offset 0x020, reset 0x0000.0001
Busy MNUM
CANIF2CRQ, type R/W, offset 0x080, reset 0x0000.0001
Busy MNUM
CANIF1CMSK, type R/W, offset 0x024, reset 0x0000.0000
WRNRD Mask Arb Control ClrIntPnd NewDat DataA DataB
CANIF2CMSK, type R/W, offset 0x084, reset 0x0000.0000
WRNRD Mask Arb Control ClrIntPnd NewDat DataA DataB
CANIF1CMSK, type R/W, offset 0x024, reset 0x0000.0000
WRNRD Mask Arb Control TxRqst DataA DataB
CANIF2CMSK, type R/W, offset 0x084, reset 0x0000.0000
WRNRD Mask Arb Control TxRqst DataA DataB
CANIF1MSK1, type R/W, offset 0x028, reset 0x0000.FFFF
Msk
CANIF2MSK1, type R/W, offset 0x088, reset 0x0000.FFFF
Msk
CANIF1MSK2, type R/W, offset 0x02C, reset 0x0000.FFFF
MXtd MDir Msk
CANIF2MSK2, type R/W, offset 0x08C, reset 0x0000.FFFF
MXtd MDir Msk
CANIF1ARB1, type R/W, offset 0x030, reset 0x0000.0000
ID
CANIF2ARB1, type R/W, offset 0x090, reset 0x0000.0000
ID
CANIF1ARB2, type R/W, offset 0x034, reset 0x0000.0000
MsgVal Xtd Dir ID
CANIF2ARB2, type R/W, offset 0x094, reset 0x0000.0000
MsgVal Xtd Dir ID
CANIF1MCTL, type R/W, offset 0x038, reset 0x0000.0000
NewDat MsgLst IntPnd UMask TxIE RxIE RmtEn TxRqst EoB DLC
CANIF2MCTL, type R/W, offset 0x098, reset 0x0000.0000
NewDat MsgLst IntPnd UMask TxIE RxIE RmtEn TxRqst EoB DLC
CANIF1DA1, type R/W, offset 0x03C, reset 0x0000.0000
Data
March 17, 2008 573
Preliminary
LM3S8933 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CANIF1DA2, type R/W, offset 0x040, reset 0x0000.0000
Data
CANIF1DB1, type R/W, offset 0x044, reset 0x0000.0000
Data
CANIF1DB2, type R/W, offset 0x048, reset 0x0000.0000
Data
CANIF2DA1, type R/W, offset 0x09C, reset 0x0000.0000
Data
CANIF2DA2, type R/W, offset 0x0A0, reset 0x0000.0000
Data
CANIF2DB1, type R/W, offset 0x0A4, reset 0x0000.0000
Data
CANIF2DB2, type R/W, offset 0x0A8, reset 0x0000.0000
Data
CANTXRQ1, type RO, offset 0x100, reset 0x0000.0000
TxRqst
CANTXRQ2, type RO, offset 0x104, reset 0x0000.0000
TxRqst
CANNWDA1, type RO, offset 0x120, reset 0x0000.0000
NewDat
CANNWDA2, type RO, offset 0x124, reset 0x0000.0000
NewDat
CANMSG1INT, type RO, offset 0x140, reset 0x0000.0000
IntPnd
CANMSG2INT, type RO, offset 0x144, reset 0x0000.0000
IntPnd
CANMSG1VAL, type RO, offset 0x160, reset 0x0000.0000
MsgVal
CANMSG2VAL, type RO, offset 0x164, reset 0x0000.0000
MsgVal
Ethernet Controller
Ethernet MAC
Base 0x4004.8000
MACRIS, type RO, offset 0x000, reset 0x0000.0000
PHYINT MDINT RXER FOV TXEMP TXER RXINT
574 March 17, 2008
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACIACK, type W1C, offset 0x000, reset 0x0000.0000
PHYINT MDINT RXER FOV TXEMP TXER RXINT
MACIM, type R/W, offset 0x004, reset 0x0000.007F
PHYINTM MDINTM RXERM FOVM TXEMPM TXERM RXINTM
MACRCTL, type R/W, offset 0x008, reset 0x0000.0008
RSTFIFO BADCRC PRMS AMUL RXEN
MACTCTL, type R/W, offset 0x00C, reset 0x0000.0000
DUPLEX CRC PADEN TXEN
MACDATA, type RO, offset 0x010, reset 0x0000.0000
RXDATA
RXDATA
MACDATA, type WO, offset 0x010, reset 0x0000.0000
TXDATA
TXDATA
MACIA0, type R/W, offset 0x014, reset 0x0000.0000
MACOCT4 MACOCT3
MACOCT2 MACOCT1
MACIA1, type R/W, offset 0x018, reset 0x0000.0000
MACOCT6 MACOCT5
MACTHR, type R/W, offset 0x01C, reset 0x0000.003F
THRESH
MACMCTL, type R/W, offset 0x020, reset 0x0000.0000
REGADR WRITE START
MACMDV, type R/W, offset 0x024, reset 0x0000.0080
DIV
MACMTXD, type R/W, offset 0x02C, reset 0x0000.0000
MDTX
MACMRXD, type R/W, offset 0x030, reset 0x0000.0000
MDRX
MACNP, type RO, offset 0x034, reset 0x0000.0000
NPR
MACTR, type R/W, offset 0x038, reset 0x0000.0000
NEWTX
MACTS, type R/W, offset 0x03C, reset 0x0000.0000
TSEN
March 17, 2008 575
Preliminary
LM3S8933 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ethernet Controller
MII Management
Base 0x4004.8000
MR0, type R/W, address 0x00, reset 0x3100
RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT
MR1, type RO, address 0x01, reset 0x7849
100X_F 100X_H 10T_F 10T_H MFPS ANEGC RFAULT ANEGA LINK JAB EXTD
MR2, type RO, address 0x02, reset 0x000E
OUI[21:6]
MR3, type RO, address 0x03, reset 0x7237
OUI[5:0] MN RN
MR4, type R/W, address 0x04, reset 0x01E1
NP RF A3 A2 A1 A0 S[4:0]
MR5, type RO, address 0x05, reset 0x0000
NP ACK RF A[7:0] S[4:0]
MR6, type RO, address 0x06, reset 0x0000
PDF LPNPA PRX LPANEGA
MR16, type R/W, address 0x10, reset 0x0140
RPTR INPOL TXHIM SQEI NL10 APOL RVSPOL PCSBP RXCC
MR17, type R/W, address 0x11, reset 0x0000
JABBER_IE RXER_IE PRX_IE PDF_IE LPACK_IE LSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INT RXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT ANEGCOMP_INT
MR18, type RO, address 0x12, reset 0x0000
ANEGF DPLX RATE RXSD RX_LOCK
MR19, type R/W, address 0x13, reset 0x4000
TXO[1:0]
MR23, type R/W, address 0x17, reset 0x0010
LED1[3:0] LED0[3:0]
MR24, type R/W, address 0x18, reset 0x00C0
PD_MODE AUTO_SW MDIX MDIX_CM MDIX_SD
Analog Comparators
Base 0x4003.C000
ACMIS, type R/W1C, offset 0x00, reset 0x0000.0000
IN2 IN1 IN0
ACRIS, type RO, offset 0x04, reset 0x0000.0000
IN2 IN1 IN0
ACINTEN, type R/W, offset 0x08, reset 0x0000.0000
IN2 IN1 IN0
ACREFCTL, type R/W, offset 0x10, reset 0x0000.0000
EN RNG VREF
ACSTAT0, type RO, offset 0x20, reset 0x0000.0000
OVAL
ACSTAT1, type RO, offset 0x40, reset 0x0000.0000
OVAL
ACSTAT2, type RO, offset 0x60, reset 0x0000.0000
OVAL
576 March 17, 2008
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACCTL0, type R/W, offset 0x24, reset 0x0000.0000
TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV
ACCTL1, type R/W, offset 0x44, reset 0x0000.0000
TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV
ACCTL2, type R/W, offset 0x64, reset 0x0000.0000
TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV
March 17, 2008 577
Preliminary
LM3S8933 Microcontroller
C Ordering and Contact Information
C.1 Ordering Information
L M 3 S n n n n – g p p s s – r r m
Part Number
Temperature
Package
Speed
Revision
Shipping Medium
E=-40 C to 105 C
I = -40 C to 85 C
T = Tape-and-reel
Omitted = Default shipping (tray or tube)
Omitted = Default to current shipping
revision
A0 = First all-layer mask
A1 = Metal layers update to A0
A2 = Metal layers update to A1
B0 = Second all-layer mask revision
etc.
BZ = RoHS-compliant 108-ball BGA
QC = RoHS-compliant 100-pin LQFP
QN = RoHS-compliant 48-pin LQFP
RN = RoHS-compliant 28-pin SOIC
20 = 20 MHz
25 = 25 MHz
50 = 50 MHz
Table C-1. Part Ordering Information
Orderable Part Number Description
Stellaris® LM3S8933-IBZ50 LM3S8933 Microcontroller
Stellaris® LM3S8933-IBZ50 (T) LM3S8933 Microcontroller
Stellaris® LM3S8933-EQC50 LM3S8933 Microcontroller
Stellaris® LM3S8933-EQC50 (T) LM3S8933 Microcontroller
Stellaris® LM3S8933-IQC50 LM3S8933 Microcontroller
Stellaris® LM3S8933-IQC50 (T) LM3S8933 Microcontroller
C.2 Kits
The Luminary Micro Stellaris® Family provides the hardware and software tools that engineers need
to begin development quickly.
■ Reference Design Kits accelerate product development by providing ready-to-run hardware, and
comprehensive documentation including hardware design files:
http://www.luminarymicro.com/products/reference_design_kits/
■ Evaluation Kits provide a low-cost and effective means of evaluating Stellaris® microcontrollers
before purchase:
http://www.luminarymicro.com/products/kits.html
■ Development Kits provide you with all the tools you need to develop and prototype embedded
applications right out of the box:
http://www.luminarymicro.com/products/development_kits.html
See the Luminary Micro website for the latest tools available, or ask your Luminary Micro distributor.
578 March 17, 2008
Preliminary
Ordering and Contact Information
C.3 Company Information
Luminary Micro, Inc. designs, markets, and sells ARM Cortex-M3-based microcontrollers (MCUs).
Austin, Texas-based Luminary Micro is the lead partner for the Cortex-M3 processor, delivering the
world's first silicon implementation of the Cortex-M3 processor. Luminary Micro's introduction of the
Stellaris® family of products provides 32-bit performance for the same price as current 8- and 16-bit
microcontroller designs. With entry-level pricing at $1.00 for an ARM technology-based MCU,
Luminary Micro's Stellaris product line allows for standardization that eliminates future architectural
upgrades or software tool changes.
Luminary Micro, Inc.
108 Wild Basin, Suite 350
Austin, TX 78746
Main: +1-512-279-8800
Fax: +1-512-279-8879
http://www.luminarymicro.com
sales@luminarymicro.com
C.4 Support Information
For support on Luminary Micro products, contact:
support@luminarymicro.com +1-512-279-8800, ext. 3
March 17, 2008 579
Preliminary
LM3S8933 Microcontroller
Stellaris® LM3S2965 Microcontroller
DATA SHEET
Copyright © 2007-2011
Texas Instruments Incorporated
DS-LM3S2965-9102
TEXAS INSTRUMENTS-PRODUCTION DATA
Copyright
Copyright © 2007-2011 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments
Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the
property of others.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments Incorporated
108 Wild Basin, Suite 350
Austin, TX 78746
http://www.ti.com/stellaris
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
2 January 08, 2011
Texas Instruments-Production Data
Table of Contents
Revision History ............................................................................................................................. 25
About This Document .................................................................................................................... 31
Audience .............................................................................................................................................. 31
About This Manual ................................................................................................................................ 31
Related Documents ............................................................................................................................... 31
Documentation Conventions .................................................................................................................. 32
1 Architectural Overview .......................................................................................... 34
1.1 Product Features .......................................................................................................... 34
1.2 Target Applications ........................................................................................................ 43
1.3 High-Level Block Diagram ............................................................................................. 43
1.4 Functional Overview ...................................................................................................... 45
1.4.1 ARM Cortex™-M3 ......................................................................................................... 45
1.4.2 Motor Control Peripherals .............................................................................................. 46
1.4.3 Analog Peripherals ........................................................................................................ 47
1.4.4 Serial Communications Peripherals ................................................................................ 47
1.4.5 System Peripherals ....................................................................................................... 49
1.4.6 Memory Peripherals ...................................................................................................... 50
1.4.7 Additional Features ....................................................................................................... 50
1.4.8 Hardware Details .......................................................................................................... 51
2 The Cortex-M3 Processor ...................................................................................... 52
2.1 Block Diagram .............................................................................................................. 53
2.2 Overview ...................................................................................................................... 54
2.2.1 System-Level Interface .................................................................................................. 54
2.2.2 Integrated Configurable Debug ...................................................................................... 54
2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 55
2.2.4 Cortex-M3 System Component Details ........................................................................... 55
2.3 Programming Model ...................................................................................................... 56
2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 56
2.3.2 Stacks .......................................................................................................................... 56
2.3.3 Register Map ................................................................................................................ 57
2.3.4 Register Descriptions .................................................................................................... 58
2.3.5 Exceptions and Interrupts .............................................................................................. 71
2.3.6 Data Types ................................................................................................................... 71
2.4 Memory Model .............................................................................................................. 71
2.4.1 Memory Regions, Types and Attributes ........................................................................... 73
2.4.2 Memory System Ordering of Memory Accesses .............................................................. 73
2.4.3 Behavior of Memory Accesses ....................................................................................... 73
2.4.4 Software Ordering of Memory Accesses ......................................................................... 74
2.4.5 Bit-Banding ................................................................................................................... 75
2.4.6 Data Storage ................................................................................................................ 77
2.4.7 Synchronization Primitives ............................................................................................. 78
2.5 Exception Model ........................................................................................................... 79
2.5.1 Exception States ........................................................................................................... 80
2.5.2 Exception Types ............................................................................................................ 80
2.5.3 Exception Handlers ....................................................................................................... 83
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2.5.4 Vector Table .................................................................................................................. 83
2.5.5 Exception Priorities ....................................................................................................... 84
2.5.6 Interrupt Priority Grouping .............................................................................................. 85
2.5.7 Exception Entry and Return ........................................................................................... 85
2.6 Fault Handling .............................................................................................................. 87
2.6.1 Fault Types ................................................................................................................... 87
2.6.2 Fault Escalation and Hard Faults .................................................................................... 88
2.6.3 Fault Status Registers and Fault Address Registers ........................................................ 89
2.6.4 Lockup ......................................................................................................................... 89
2.7 Power Management ...................................................................................................... 89
2.7.1 Entering Sleep Modes ................................................................................................... 90
2.7.2 Wake Up from Sleep Mode ............................................................................................ 90
2.8 Instruction Set Summary ............................................................................................... 91
3 Cortex-M3 Peripherals ........................................................................................... 94
3.1 Functional Description ................................................................................................... 94
3.1.1 System Timer (SysTick) ................................................................................................. 94
3.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................... 95
3.1.3 System Control Block (SCB) .......................................................................................... 97
3.1.4 Memory Protection Unit (MPU) ....................................................................................... 97
3.2 Register Map .............................................................................................................. 102
3.3 System Timer (SysTick) Register Descriptions .............................................................. 104
3.4 NVIC Register Descriptions .......................................................................................... 108
3.5 System Control Block (SCB) Register Descriptions ........................................................ 121
3.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 148
4 JTAG Interface ...................................................................................................... 158
4.1 Block Diagram ............................................................................................................ 159
4.2 Functional Description ................................................................................................. 159
4.2.1 JTAG Interface Pins ..................................................................................................... 159
4.2.2 JTAG TAP Controller ................................................................................................... 161
4.2.3 Shift Registers ............................................................................................................ 162
4.2.4 Operational Considerations .......................................................................................... 162
4.3 Initialization and Configuration ..................................................................................... 165
4.4 Register Descriptions .................................................................................................. 165
4.4.1 Instruction Register (IR) ............................................................................................... 165
4.4.2 Data Registers ............................................................................................................ 167
5 System Control ..................................................................................................... 170
5.1 Functional Description ................................................................................................. 170
5.1.1 Device Identification .................................................................................................... 170
5.1.2 Reset Control .............................................................................................................. 170
5.1.3 Power Control ............................................................................................................. 174
5.1.4 Clock Control .............................................................................................................. 175
5.1.5 System Control ........................................................................................................... 180
5.2 Initialization and Configuration ..................................................................................... 181
5.3 Register Map .............................................................................................................. 181
5.4 Register Descriptions .................................................................................................. 183
6 Hibernation Module .............................................................................................. 236
6.1 Block Diagram ............................................................................................................ 237
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6.2 Functional Description ................................................................................................. 237
6.2.1 Register Access Timing ............................................................................................... 237
6.2.2 Clock Source .............................................................................................................. 238
6.2.3 Battery Management ................................................................................................... 239
6.2.4 Real-Time Clock .......................................................................................................... 240
6.2.5 Non-Volatile Memory ................................................................................................... 240
6.2.6 Power Control ............................................................................................................. 240
6.2.7 Initiating Hibernate ...................................................................................................... 241
6.2.8 Interrupts and Status ................................................................................................... 241
6.3 Initialization and Configuration ..................................................................................... 241
6.3.1 Initialization ................................................................................................................. 242
6.3.2 RTC Match Functionality (No Hibernation) .................................................................... 242
6.3.3 RTC Match/Wake-Up from Hibernation ......................................................................... 242
6.3.4 External Wake-Up from Hibernation .............................................................................. 242
6.3.5 RTC/External Wake-Up from Hibernation ...................................................................... 243
6.4 Register Map .............................................................................................................. 243
6.5 Register Descriptions .................................................................................................. 243
7 Internal Memory ................................................................................................... 256
7.1 Block Diagram ............................................................................................................ 256
7.2 Functional Description ................................................................................................. 256
7.2.1 SRAM Memory ............................................................................................................ 256
7.2.2 Flash Memory ............................................................................................................. 257
7.3 Flash Memory Initialization and Configuration ............................................................... 258
7.3.1 Flash Programming ..................................................................................................... 258
7.3.2 Nonvolatile Register Programming ............................................................................... 259
7.4 Register Map .............................................................................................................. 260
7.5 Flash Register Descriptions (Flash Control Offset) ......................................................... 261
7.6 Flash Register Descriptions (System Control Offset) ...................................................... 269
8 General-Purpose Input/Outputs (GPIOs) ........................................................... 282
8.1 Functional Description ................................................................................................. 282
8.1.1 Data Control ............................................................................................................... 283
8.1.2 Interrupt Control .......................................................................................................... 284
8.1.3 Mode Control .............................................................................................................. 285
8.1.4 Commit Control ........................................................................................................... 285
8.1.5 Pad Control ................................................................................................................. 285
8.1.6 Identification ............................................................................................................... 286
8.2 Initialization and Configuration ..................................................................................... 286
8.3 Register Map .............................................................................................................. 287
8.4 Register Descriptions .................................................................................................. 289
9 General-Purpose Timers ...................................................................................... 324
9.1 Block Diagram ............................................................................................................ 325
9.2 Functional Description ................................................................................................. 326
9.2.1 GPTM Reset Conditions .............................................................................................. 326
9.2.2 32-Bit Timer Operating Modes ...................................................................................... 326
9.2.3 16-Bit Timer Operating Modes ...................................................................................... 327
9.3 Initialization and Configuration ..................................................................................... 331
9.3.1 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 331
9.3.2 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 332
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9.3.3 16-Bit One-Shot/Periodic Timer Mode ........................................................................... 332
9.3.4 16-Bit Input Edge Count Mode ..................................................................................... 333
9.3.5 16-Bit Input Edge Timing Mode .................................................................................... 333
9.3.6 16-Bit PWM Mode ....................................................................................................... 334
9.4 Register Map .............................................................................................................. 334
9.5 Register Descriptions .................................................................................................. 335
10 Watchdog Timer ................................................................................................... 360
10.1 Block Diagram ............................................................................................................ 361
10.2 Functional Description ................................................................................................. 361
10.3 Initialization and Configuration ..................................................................................... 362
10.4 Register Map .............................................................................................................. 362
10.5 Register Descriptions .................................................................................................. 363
11 Analog-to-Digital Converter (ADC) ..................................................................... 384
11.1 Block Diagram ............................................................................................................ 384
11.2 Functional Description ................................................................................................. 385
11.2.1 Sample Sequencers .................................................................................................... 385
11.2.2 Module Control ............................................................................................................ 386
11.2.3 Hardware Sample Averaging Circuit ............................................................................. 387
11.2.4 Analog-to-Digital Converter .......................................................................................... 387
11.2.5 Differential Sampling ................................................................................................... 387
11.2.6 Test Modes ................................................................................................................. 389
11.2.7 Internal Temperature Sensor ........................................................................................ 390
11.3 Initialization and Configuration ..................................................................................... 390
11.3.1 Module Initialization ..................................................................................................... 390
11.3.2 Sample Sequencer Configuration ................................................................................. 391
11.4 Register Map .............................................................................................................. 391
11.5 Register Descriptions .................................................................................................. 392
12 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 420
12.1 Block Diagram ............................................................................................................ 421
12.2 Functional Description ................................................................................................. 421
12.2.1 Transmit/Receive Logic ............................................................................................... 421
12.2.2 Baud-Rate Generation ................................................................................................. 422
12.2.3 Data Transmission ...................................................................................................... 423
12.2.4 Serial IR (SIR) ............................................................................................................. 423
12.2.5 FIFO Operation ........................................................................................................... 424
12.2.6 Interrupts .................................................................................................................... 424
12.2.7 Loopback Operation .................................................................................................... 425
12.2.8 IrDA SIR block ............................................................................................................ 425
12.3 Initialization and Configuration ..................................................................................... 425
12.4 Register Map .............................................................................................................. 426
12.5 Register Descriptions .................................................................................................. 427
13 Synchronous Serial Interface (SSI) .................................................................... 461
13.1 Block Diagram ............................................................................................................ 461
13.2 Functional Description ................................................................................................. 462
13.2.1 Bit Rate Generation ..................................................................................................... 462
13.2.2 FIFO Operation ........................................................................................................... 462
13.2.3 Interrupts .................................................................................................................... 462
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13.2.4 Frame Formats ........................................................................................................... 463
13.3 Initialization and Configuration ..................................................................................... 470
13.4 Register Map .............................................................................................................. 471
13.5 Register Descriptions .................................................................................................. 472
14 Inter-Integrated Circuit (I2C) Interface ................................................................ 498
14.1 Block Diagram ............................................................................................................ 499
14.2 Functional Description ................................................................................................. 499
14.2.1 I2C Bus Functional Overview ........................................................................................ 499
14.2.2 Available Speed Modes ............................................................................................... 501
14.2.3 Interrupts .................................................................................................................... 502
14.2.4 Loopback Operation .................................................................................................... 503
14.2.5 Command Sequence Flow Charts ................................................................................ 503
14.3 Initialization and Configuration ..................................................................................... 510
14.4 Register Map .............................................................................................................. 511
14.5 Register Descriptions (I2C Master) ............................................................................... 512
14.6 Register Descriptions (I2C Slave) ................................................................................. 525
15 Controller Area Network (CAN) Module ............................................................. 534
15.1 Block Diagram ............................................................................................................ 535
15.2 Functional Description ................................................................................................. 535
15.2.1 Initialization ................................................................................................................. 536
15.2.2 Operation ................................................................................................................... 537
15.2.3 Transmitting Message Objects ..................................................................................... 538
15.2.4 Configuring a Transmit Message Object ........................................................................ 538
15.2.5 Updating a Transmit Message Object ........................................................................... 539
15.2.6 Accepting Received Message Objects .......................................................................... 540
15.2.7 Receiving a Data Frame .............................................................................................. 540
15.2.8 Receiving a Remote Frame .......................................................................................... 540
15.2.9 Receive/Transmit Priority ............................................................................................. 541
15.2.10 Configuring a Receive Message Object ........................................................................ 541
15.2.11 Handling of Received Message Objects ........................................................................ 542
15.2.12 Handling of Interrupts .................................................................................................. 545
15.2.13 Test Mode ................................................................................................................... 545
15.2.14 Bit Timing Configuration Error Considerations ............................................................... 547
15.2.15 Bit Time and Bit Rate ................................................................................................... 547
15.2.16 Calculating the Bit Timing Parameters .......................................................................... 549
15.3 Register Map .............................................................................................................. 552
15.4 CAN Register Descriptions .......................................................................................... 553
16 Analog Comparators ............................................................................................ 579
16.1 Block Diagram ............................................................................................................ 580
16.2 Functional Description ................................................................................................. 580
16.2.1 Internal Reference Programming .................................................................................. 581
16.3 Initialization and Configuration ..................................................................................... 582
16.4 Register Map .............................................................................................................. 582
16.5 Register Descriptions .................................................................................................. 583
17 Pulse Width Modulator (PWM) ............................................................................ 591
17.1 Block Diagram ............................................................................................................ 592
17.2 Functional Description ................................................................................................. 593
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17.2.1 PWM Timer ................................................................................................................. 593
17.2.2 PWM Comparators ...................................................................................................... 593
17.2.3 PWM Signal Generator ................................................................................................ 594
17.2.4 Dead-Band Generator ................................................................................................. 595
17.2.5 Interrupt/ADC-Trigger Selector ..................................................................................... 595
17.2.6 Synchronization Methods ............................................................................................ 596
17.2.7 Fault Conditions .......................................................................................................... 596
17.2.8 Output Control Block ................................................................................................... 596
17.3 Initialization and Configuration ..................................................................................... 596
17.4 Register Map .............................................................................................................. 597
17.5 Register Descriptions .................................................................................................. 599
18 Quadrature Encoder Interface (QEI) ................................................................... 629
18.1 Block Diagram ............................................................................................................ 629
18.2 Functional Description ................................................................................................. 630
18.3 Initialization and Configuration ..................................................................................... 632
18.4 Register Map .............................................................................................................. 633
18.5 Register Descriptions .................................................................................................. 633
19 Pin Diagram .......................................................................................................... 646
20 Signal Tables ........................................................................................................ 648
20.1 100-Pin LQFP Package Pin Tables ............................................................................... 648
20.2 108-Pin BGA Package Pin Tables ................................................................................ 662
20.3 Connections for Unused Signals ................................................................................... 676
21 Operating Characteristics ................................................................................... 678
22 Electrical Characteristics .................................................................................... 679
22.1 DC Characteristics ...................................................................................................... 679
22.1.1 Maximum Ratings ....................................................................................................... 679
22.1.2 Recommended DC Operating Conditions ...................................................................... 679
22.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................ 680
22.1.4 GPIO Module Characteristics ....................................................................................... 680
22.1.5 Power Specifications ................................................................................................... 680
22.1.6 Flash Memory Characteristics ...................................................................................... 682
22.1.7 Hibernation ................................................................................................................. 682
22.2 AC Characteristics ....................................................................................................... 682
22.2.1 Load Conditions .......................................................................................................... 682
22.2.2 Clocks ........................................................................................................................ 682
22.2.3 JTAG and Boundary Scan ............................................................................................ 684
22.2.4 Reset ......................................................................................................................... 685
22.2.5 Sleep Modes ............................................................................................................... 687
22.2.6 Hibernation Module ..................................................................................................... 687
22.2.7 General-Purpose I/O (GPIO) ........................................................................................ 688
22.2.8 Analog-to-Digital Converter .......................................................................................... 688
22.2.9 Synchronous Serial Interface (SSI) ............................................................................... 690
22.2.10 Inter-Integrated Circuit (I2C) Interface ........................................................................... 691
22.2.11 Analog Comparator ..................................................................................................... 692
A Serial Flash Loader .............................................................................................. 693
A.1 Serial Flash Loader ..................................................................................................... 693
A.2 Interfaces ................................................................................................................... 693
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A.2.1 UART ......................................................................................................................... 693
A.2.2 SSI ............................................................................................................................. 693
A.3 Packet Handling .......................................................................................................... 694
A.3.1 Packet Format ............................................................................................................ 694
A.3.2 Sending Packets ......................................................................................................... 694
A.3.3 Receiving Packets ....................................................................................................... 694
A.4 Commands ................................................................................................................. 695
A.4.1 COMMAND_PING (0X20) ............................................................................................ 695
A.4.2 COMMAND_GET_STATUS (0x23) ............................................................................... 695
A.4.3 COMMAND_DOWNLOAD (0x21) ................................................................................. 695
A.4.4 COMMAND_SEND_DATA (0x24) ................................................................................. 696
A.4.5 COMMAND_RUN (0x22) ............................................................................................. 696
A.4.6 COMMAND_RESET (0x25) ......................................................................................... 696
B Register Quick Reference ................................................................................... 698
C Ordering and Contact Information ..................................................................... 723
C.1 Ordering Information .................................................................................................... 723
C.2 Part Markings .............................................................................................................. 723
C.3 Kits ............................................................................................................................. 724
C.4 Support Information ..................................................................................................... 724
D Package Information ............................................................................................ 725
D.1 100-Pin LQFP Package ............................................................................................... 725
D.1.1 Package Dimensions ................................................................................................... 725
D.1.2 Tray Dimensions ......................................................................................................... 727
D.1.3 Tape and Reel Dimensions .......................................................................................... 727
D.2 108-Ball BGA Package ................................................................................................ 729
D.2.1 Package Dimensions ................................................................................................... 729
D.2.2 Tray Dimensions ......................................................................................................... 731
D.2.3 Tape and Reel Dimensions .......................................................................................... 732
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List of Figures
Figure 1-1. Stellaris LM3S2965 Microcontroller High-Level Block Diagram .............................. 44
Figure 2-1. CPU Block Diagram ............................................................................................. 54
Figure 2-2. TPIU Block Diagram ............................................................................................ 55
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 57
Figure 2-4. Bit-Band Mapping ................................................................................................ 77
Figure 2-5. Data Storage ....................................................................................................... 78
Figure 2-6. Vector table ......................................................................................................... 84
Figure 2-7. Exception Stack Frame ........................................................................................ 86
Figure 3-1. SRD Use Example ............................................................................................. 100
Figure 4-1. JTAG Module Block Diagram .............................................................................. 159
Figure 4-2. Test Access Port State Machine ......................................................................... 162
Figure 4-3. IDCODE Register Format ................................................................................... 168
Figure 4-4. BYPASS Register Format ................................................................................... 168
Figure 4-5. Boundary Scan Register Format ......................................................................... 169
Figure 5-1. Basic RST Configuration .................................................................................... 172
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 172
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 173
Figure 5-4. Power Architecture ............................................................................................ 175
Figure 5-5. Main Clock Tree ................................................................................................ 177
Figure 6-1. Hibernation Module Block Diagram ..................................................................... 237
Figure 6-2. Clock Source Using Crystal ................................................................................ 239
Figure 6-3. Clock Source Using Dedicated Oscillator ............................................................. 239
Figure 7-1. Flash Block Diagram .......................................................................................... 256
Figure 8-1. GPIO Port Block Diagram ................................................................................... 283
Figure 8-2. GPIODATA Write Example ................................................................................. 284
Figure 8-3. GPIODATA Read Example ................................................................................. 284
Figure 9-1. GPTM Module Block Diagram ............................................................................ 325
Figure 9-2. 16-Bit Input Edge Count Mode Example .............................................................. 329
Figure 9-3. 16-Bit Input Edge Time Mode Example ............................................................... 330
Figure 9-4. 16-Bit PWM Mode Example ................................................................................ 331
Figure 10-1. WDT Module Block Diagram .............................................................................. 361
Figure 11-1. ADC Module Block Diagram ............................................................................... 385
Figure 11-2. Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 388
Figure 11-3. Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 389
Figure 11-4. Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 389
Figure 11-5. Internal Temperature Sensor Characteristic ......................................................... 390
Figure 12-1. UART Module Block Diagram ............................................................................. 421
Figure 12-2. UART Character Frame ..................................................................................... 422
Figure 12-3. IrDA Data Modulation ......................................................................................... 424
Figure 13-1. SSI Module Block Diagram ................................................................................. 461
Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 464
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 464
Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 465
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 465
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 466
Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 467
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Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 467
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 468
Figure 13-10. MICROWIRE Frame Format (Single Frame) ........................................................ 469
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 470
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 470
Figure 14-1. I2C Block Diagram ............................................................................................. 499
Figure 14-2. I2C Bus Configuration ........................................................................................ 499
Figure 14-3. START and STOP Conditions ............................................................................. 500
Figure 14-4. Complete Data Transfer with a 7-Bit Address ....................................................... 500
Figure 14-5. R/S Bit in First Byte ............................................................................................ 500
Figure 14-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 501
Figure 14-7. Master Single SEND .......................................................................................... 504
Figure 14-8. Master Single RECEIVE ..................................................................................... 505
Figure 14-9. Master Burst SEND ........................................................................................... 506
Figure 14-10. Master Burst RECEIVE ...................................................................................... 507
Figure 14-11. Master Burst RECEIVE after Burst SEND ............................................................ 508
Figure 14-12. Master Burst SEND after Burst RECEIVE ............................................................ 509
Figure 14-13. Slave Command Sequence ................................................................................ 510
Figure 15-1. CAN Controller Block Diagram ............................................................................ 535
Figure 15-2. CAN Data/Remote Frame .................................................................................. 536
Figure 15-3. Message Objects in a FIFO Buffer ...................................................................... 544
Figure 15-4. CAN Bit Time .................................................................................................... 548
Figure 16-1. Analog Comparator Module Block Diagram ......................................................... 580
Figure 16-2. Structure of Comparator Unit .............................................................................. 581
Figure 16-3. Comparator Internal Reference Structure ............................................................ 581
Figure 17-1. PWM Unit Diagram ............................................................................................ 592
Figure 17-2. PWM Module Block Diagram .............................................................................. 593
Figure 17-3. PWM Count-Down Mode .................................................................................... 594
Figure 17-4. PWM Count-Up/Down Mode .............................................................................. 594
Figure 17-5. PWM Generation Example In Count-Up/Down Mode ........................................... 595
Figure 17-6. PWM Dead-Band Generator ............................................................................... 595
Figure 18-1. QEI Block Diagram ............................................................................................ 630
Figure 18-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 631
Figure 19-1. 100-Pin LQFP Package Pin Diagram .................................................................. 646
Figure 19-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 647
Figure 22-1. Load Conditions ................................................................................................ 682
Figure 22-2. JTAG Test Clock Input Timing ............................................................................. 685
Figure 22-3. JTAG Test Access Port (TAP) Timing .................................................................. 685
Figure 22-4. JTAG TRST Timing ............................................................................................ 685
Figure 22-5. External Reset Timing (RST) .............................................................................. 686
Figure 22-6. Power-On Reset Timing ..................................................................................... 686
Figure 22-7. Brown-Out Reset Timing .................................................................................... 686
Figure 22-8. Software Reset Timing ....................................................................................... 687
Figure 22-9. Watchdog Reset Timing ..................................................................................... 687
Figure 22-10. Hibernation Module Timing ................................................................................. 688
Figure 22-11. ADC Input Equivalency Diagram ......................................................................... 689
Figure 22-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 690
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Figure 22-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 691
Figure 22-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 691
Figure 22-15. I2C Timing ......................................................................................................... 692
Figure D-1. 100-Pin LQFP Package Dimensions ................................................................... 725
Figure D-2. 100-Pin LQFP Tray Dimensions .......................................................................... 727
Figure D-3. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 728
Figure D-4. 108-Ball BGA Package Dimensions .................................................................... 729
Figure D-5. 108-Ball BGA Tray Dimensions ........................................................................... 731
Figure D-6. 108-Ball BGA Tape and Reel Dimensions ............................................................ 732
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List of Tables
Table 1. Revision History .................................................................................................. 25
Table 2. Documentation Conventions ................................................................................ 32
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 57
Table 2-2. Processor Register Map ....................................................................................... 58
Table 2-3. PSR Register Combinations ................................................................................. 63
Table 2-4. Memory Map ....................................................................................................... 71
Table 2-5. Memory Access Behavior ..................................................................................... 74
Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 76
Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 76
Table 2-8. Exception Types .................................................................................................. 81
Table 2-9. Interrupts ............................................................................................................ 82
Table 2-10. Exception Return Behavior ................................................................................... 87
Table 2-11. Faults ................................................................................................................. 88
Table 2-12. Fault Status and Fault Address Registers .............................................................. 89
Table 2-13. Cortex-M3 Instruction Summary ........................................................................... 91
Table 3-1. Core Peripheral Register Regions ......................................................................... 94
Table 3-2. Memory Attributes Summary ................................................................................ 97
Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 100
Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 101
Table 3-5. AP Bit Field Encoding ........................................................................................ 101
Table 3-6. Memory Region Attributes for Stellaris Microcontrollers ........................................ 101
Table 3-7. Peripherals Register Map ................................................................................... 102
Table 3-8. Interrupt Priority Levels ...................................................................................... 127
Table 3-9. Example SIZE Field Values ................................................................................ 155
Table 4-1. JTAG Port Pins Reset State ............................................................................... 160
Table 4-2. JTAG Instruction Register Commands ................................................................. 165
Table 5-1. Reset Sources ................................................................................................... 170
Table 5-2. Clock Source Options ........................................................................................ 176
Table 5-3. Possible System Clock Frequencies Using the SYSDIV Field ............................... 178
Table 5-4. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 178
Table 5-5. System Control Register Map ............................................................................. 182
Table 5-6. RCC2 Fields that Override RCC fields ................................................................. 197
Table 6-1. Hibernation Module Register Map ....................................................................... 243
Table 7-1. Flash Protection Policy Combinations ................................................................. 257
Table 7-2. User-Programmable Flash Memory Resident Registers ....................................... 259
Table 7-3. Flash Register Map ............................................................................................ 260
Table 8-1. GPIO Pad Configuration Examples ..................................................................... 286
Table 8-2. GPIO Interrupt Configuration Example ................................................................ 286
Table 8-3. GPIO Register Map ........................................................................................... 288
Table 9-1. Available CCP Pins ............................................................................................ 325
Table 9-2. 16-Bit Timer With Prescaler Configurations ......................................................... 328
Table 9-3. Timers Register Map .......................................................................................... 334
Table 10-1. Watchdog Timer Register Map ............................................................................ 362
Table 11-1. Samples and FIFO Depth of Sequencers ............................................................ 385
Table 11-2. Differential Sampling Pairs ................................................................................. 387
Table 11-3. ADC Register Map ............................................................................................. 391
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Table 12-1. UART Register Map ........................................................................................... 427
Table 13-1. SSI Register Map .............................................................................................. 472
Table 14-1. Examples of I2C Master Timer Period versus Speed Mode ................................... 502
Table 14-2. Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 511
Table 14-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) .................................... 516
Table 15-1. CAN Protocol Ranges ........................................................................................ 548
Table 15-2. CANBIT Register Values .................................................................................... 548
Table 15-3. CAN Register Map ............................................................................................. 552
Table 16-1. Internal Reference Voltage and ACREFCTL Field Values ..................................... 581
Table 16-2. Analog Comparators Register Map ..................................................................... 583
Table 17-1. PWM Register Map ............................................................................................ 598
Table 18-1. QEI Register Map .............................................................................................. 633
Table 20-1. Signals by Pin Number ....................................................................................... 648
Table 20-2. Signals by Signal Name ..................................................................................... 652
Table 20-3. Signals by Function, Except for GPIO ................................................................. 657
Table 20-4. GPIO Pins and Alternate Functions ..................................................................... 660
Table 20-5. Signals by Pin Number ....................................................................................... 662
Table 20-6. Signals by Signal Name ..................................................................................... 666
Table 20-7. Signals by Function, Except for GPIO ................................................................. 671
Table 20-8. GPIO Pins and Alternate Functions ..................................................................... 674
Table 20-9. Connections for Unused Signals (100-pin LQFP) ................................................. 676
Table 20-10. Connections for Unused Signals, 108-pin BGA .................................................... 676
Table 21-1. Temperature Characteristics ............................................................................... 678
Table 21-2. Thermal Characteristics ..................................................................................... 678
Table 21-3. ESD Absolute Maximum Ratings ........................................................................ 678
Table 22-1. Maximum Ratings .............................................................................................. 679
Table 22-2. Recommended DC Operating Conditions ............................................................ 679
Table 22-3. LDO Regulator Characteristics ........................................................................... 680
Table 22-4. GPIO Module DC Characteristics ........................................................................ 680
Table 22-5. Detailed Power Specifications ............................................................................ 681
Table 22-6. Flash Memory Characteristics ............................................................................ 682
Table 22-7. Hibernation Module DC Characteristics ............................................................... 682
Table 22-8. Phase Locked Loop (PLL) Characteristics ........................................................... 682
Table 22-9. Actual PLL Frequency ........................................................................................ 683
Table 22-10. Clock Characteristics ......................................................................................... 683
Table 22-11. Crystal Characteristics ....................................................................................... 683
Table 22-12. System Clock Characteristics with ADC Operation ............................................... 684
Table 22-13. JTAG Characteristics ......................................................................................... 684
Table 22-14. Reset Characteristics ......................................................................................... 685
Table 22-15. Sleep Modes AC Characteristics ......................................................................... 687
Table 22-16. Hibernation Module AC Characteristics ............................................................... 687
Table 22-17. GPIO Characteristics ......................................................................................... 688
Table 22-18. ADC Characteristics ........................................................................................... 688
Table 22-19. ADC Module Internal Reference Characteristics .................................................. 689
Table 22-20. SSI Characteristics ............................................................................................ 690
Table 22-21. I2C Characteristics ............................................................................................. 691
Table 22-22. Analog Comparator Characteristics ..................................................................... 692
Table 22-23. Analog Comparator Voltage Reference Characteristics ........................................ 692
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Table C-1. Part Ordering Information ................................................................................... 723
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List of Registers
The Cortex-M3 Processor ............................................................................................................. 52
Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 59
Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 59
Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 59
Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 59
Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 59
Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 59
Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 59
Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 59
Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 59
Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 59
Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 59
Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 59
Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 59
Register 14: Stack Pointer (SP) ........................................................................................................... 60
Register 15: Link Register (LR) ............................................................................................................ 61
Register 16: Program Counter (PC) ..................................................................................................... 62
Register 17: Program Status Register (PSR) ........................................................................................ 63
Register 18: Priority Mask Register (PRIMASK) .................................................................................... 67
Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 68
Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 69
Register 21: Control Register (CONTROL) ........................................................................................... 70
Cortex-M3 Peripherals ................................................................................................................... 94
Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 105
Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 107
Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 108
Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 109
Register 5: Interrupt 32-43 Set Enable (EN1), offset 0x104 ................................................................ 110
Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 111
Register 7: Interrupt 32-43 Clear Enable (DIS1), offset 0x184 ............................................................ 112
Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 113
Register 9: Interrupt 32-43 Set Pending (PEND1), offset 0x204 ......................................................... 114
Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 115
Register 11: Interrupt 32-43 Clear Pending (UNPEND1), offset 0x284 .................................................. 116
Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 117
Register 13: Interrupt 32-43 Active Bit (ACTIVE1), offset 0x304 ........................................................... 118
Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 119
Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 119
Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 119
Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 119
Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 119
Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 119
Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 119
Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 119
Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 119
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Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 119
Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 119
Register 25: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 121
Register 26: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 122
Register 27: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 123
Register 28: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 126
Register 29: Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 127
Register 30: System Control (SYSCTRL), offset 0xD10 ....................................................................... 129
Register 31: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 131
Register 32: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 133
Register 33: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 134
Register 34: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 135
Register 35: System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 136
Register 36: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 140
Register 37: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 146
Register 38: Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 147
Register 39: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 148
Register 40: MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 149
Register 41: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 150
Register 42: MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 152
Register 43: MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 153
Register 44: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 153
Register 45: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 153
Register 46: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 153
Register 47: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 155
Register 48: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 155
Register 49: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 155
Register 50: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 155
System Control ............................................................................................................................ 170
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 184
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 186
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 187
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 188
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 189
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 190
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 191
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 192
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 196
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 197
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 199
Register 12: Device Identification 1 (DID1), offset 0x004 ..................................................................... 200
Register 13: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 202
Register 14: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 203
Register 15: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 205
Register 16: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 207
Register 17: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 209
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 210
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 212
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Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 214
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 216
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 219
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 222
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 225
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 227
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 229
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 231
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 233
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 235
Hibernation Module ..................................................................................................................... 236
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 244
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 245
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 246
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 247
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 248
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 250
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 251
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 252
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 253
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 254
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 255
Internal Memory ........................................................................................................................... 256
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 262
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 263
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 264
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 266
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 267
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 268
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 270
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 271
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 272
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 273
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 274
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 275
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 276
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 277
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 278
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 279
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 280
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 281
General-Purpose Input/Outputs (GPIOs) ................................................................................... 282
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 290
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 291
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 292
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 293
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 294
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 295
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Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 296
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 297
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 298
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 299
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 301
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 302
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 303
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 304
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 305
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 306
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 307
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 308
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 309
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 310
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 312
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 313
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 314
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 315
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 316
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 317
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 318
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 319
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 320
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 321
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 322
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 323
General-Purpose Timers ............................................................................................................. 324
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 336
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 337
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 339
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 341
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 344
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 346
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 347
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 348
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 350
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 351
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 352
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 353
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 354
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 355
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 356
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 357
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 358
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 359
Watchdog Timer ........................................................................................................................... 360
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 364
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 365
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Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 366
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 367
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 368
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 369
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 370
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 371
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 372
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 373
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 374
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 375
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 376
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 377
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 378
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 379
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 380
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 381
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 382
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 383
Analog-to-Digital Converter (ADC) ............................................................................................. 384
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 393
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 394
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 395
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 396
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 397
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 398
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 402
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 403
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 405
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 406
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 407
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 409
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 412
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 412
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 412
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 412
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 413
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 413
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 413
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 413
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 414
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 414
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 415
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 415
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 417
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 418
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 419
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 420
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 428
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Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 430
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 432
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 434
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 435
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 436
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 437
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 439
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 441
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 443
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 445
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 446
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 447
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 449
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 450
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 451
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 452
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 453
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 454
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 455
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 456
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 457
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 458
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 459
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 460
Synchronous Serial Interface (SSI) ............................................................................................ 461
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 473
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 475
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 477
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 478
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 480
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 481
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 483
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 484
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 485
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 486
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 487
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 488
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 489
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 490
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 491
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 492
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 493
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 494
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 495
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 496
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 497
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 498
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 513
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Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 514
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 518
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 519
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 520
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 521
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 522
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 523
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 524
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 526
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 527
Register 12: I2C Slave Data (I2CSDR), offset 0x808 ........................................................................... 529
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 530
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 531
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 532
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 533
Controller Area Network (CAN) Module ..................................................................................... 534
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 555
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 557
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 559
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 560
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 561
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 562
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 564
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 565
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 565
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 566
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 566
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 568
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 568
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 569
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 569
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 570
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 570
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 571
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 571
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 572
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 572
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 574
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 574
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 574
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 574
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 574
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 574
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 574
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 574
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 575
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 575
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Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 576
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 576
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 577
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 577
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 578
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 578
Analog Comparators ................................................................................................................... 579
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 584
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 585
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 586
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 587
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 588
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 588
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060 ..................................................... 588
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 589
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 589
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064 .................................................... 589
Pulse Width Modulator (PWM) .................................................................................................... 591
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 600
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 601
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 602
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 603
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 604
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 605
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 606
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 607
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 608
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 609
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 609
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 609
Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 611
Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 611
Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 611
Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 614
Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 614
Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 614
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 615
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 615
Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 615
Register 22: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 616
Register 23: PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 616
Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 616
Register 25: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 617
Register 26: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 617
Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 617
Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 618
Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 618
Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 618
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Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 619
Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 619
Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 619
Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 620
Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 620
Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 620
Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 623
Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 623
Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 623
Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 626
Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 626
Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 626
Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 627
Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 627
Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 627
Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 628
Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 628
Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................. 628
Quadrature Encoder Interface (QEI) .......................................................................................... 629
Register 1: QEI Control (QEICTL), offset 0x000 ................................................................................ 634
Register 2: QEI Status (QEISTAT), offset 0x004 ................................................................................ 636
Register 3: QEI Position (QEIPOS), offset 0x008 .............................................................................. 637
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... 638
Register 5: QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... 639
Register 6: QEI Timer (QEITIME), offset 0x014 ................................................................................. 640
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ............................................................. 641
Register 8: QEI Velocity (QEISPEED), offset 0x01C .......................................................................... 642
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................... 643
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............................................................. 644
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ..................................................... 645
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Table of Contents
Revision History
The revision history table notes changes made between the indicated revisions of the LM3S2965
data sheet.
Table 1. Revision History
Date Revision Description
■ In Application Interrupt and Reset Control (APINT) register, changed bit name from SYSRESETREQ
to SYSRESREQ.
■ Added DEBUG (Debug Priority) bit field to System Handler Priority 3 (SYSPRI3) register.
■ Added "Reset Sources" table to System Control chapter.
■ Removed mention of false-start bit detection in the UART chapter. This feature is not supported.
■ Added note that specific module clocks must be enabled before that module's registers can be
programmed. There must be a delay of 3 system clocks after the module clock is enabled before
any of that module's registers are accessed.
■ Changed I2C slave register base addresses and offsets to be relative to the I2C module base address
of 0x4002.0000 and 0x4002.1000, so register bases and offsets were changed for all I2C slave
registers. Note that the hw_i2c.h file in the StellarisWare Driver Library uses a base address of
0x4002.0800 and 0x4002.1800 for the I2C slave registers. Be aware when using registers with
offsets between 0x800 and 0x818 that StellarisWare uses the old slave base address for these
offsets.
■ Added GNDPHY and VCCPHY to Connections for Unused Signals tables.
■ Corrected nonlinearity and offset error parameters (EL, ED and EO) in ADC Characteristics table.
■ Added specification for maximum input voltage on a non-power pin when the microcontroller is
unpowered (VNON parameter in Maximum Ratings table).
■ Additional minor data sheet clarifications and corrections.
January 2011 9102
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Table 1. Revision History (continued)
Date Revision Description
■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two
new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was
added, including all the Cortex-M3 registers.
■ Changed register names to be consistent with StellarisWare® names: the Cortex-M3 Interrupt
Control and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and
the Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0)
register.
■ Added clarification of instruction execution during Flash operations.
■ Modified Figure 8-1 on page 283 to clarify operation of the GPIO inputs when used as an alternate
function.
■ Corrected GPIOAMSEL bit field in GPIO Analog Mode Select (GPIOAMSEL) register to be eight-bits
wide, bits[7:0].
■ Added caution not to apply a Low value to PB7 when debugging; a Low value on the pin causes
the JTAG controller to be reset, resulting in a loss of JTAG communication.
■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode.
■ In Electrical Characteristics chapter:
– Added ILKG parameter (GPIO input leakage current) to Table 22-4 on page 680.
– Corrected values for tCLKRF parameter (SSIClk rise/fall time) in Table 22-20 on page 690.
■ Added dimensions for Tray and Tape and Reel shipping mediums.
September 2010 7787
■ Corrected base address for SRAM in architectural overview chapter.
■ Clarified system clock operation, adding content to “Clock Control” on page 175.
■ Clarified CAN bit timing examples.
■ In Signal Tables chapter, added table "Connections for Unused Signals."
■ In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32.
■ In "Reset Characteristics" table, corrected value for supply voltage (VDD) rise time.
■ Additional minor data sheet clarifications and corrections.
June 2010 7393
■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed
field width to 7 bits.
■ Removed erroneous text about restoring the Flash Protection registers.
■ Added note about RST signal routing.
■ Clarified the function of the TnSTALL bit in the GPTMCTL register.
■ Additional minor data sheet clarifications and corrections.
April 2010 7007
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Revision History
Table 1. Revision History (continued)
Date Revision Description
■ In "System Control" section, clarified Debug Access Port operation after Sleep modes.
■ Clarified wording on Flash memory access errors.
■ Added section on Flash interrupts.
■ Changed the reset value of the ADC Sample Sequence Result FIFO n (ADCSSFIFOn) registers
to be indeterminate.
■ Clarified operation of SSI transmit FIFO.
■ Made these changes to the Operating Characteristics chapter:
– Added storage temperature ratings to "Temperature Characteristics" table
– Added "ESD Absolute Maximum Ratings" table
■ Made these changes to the Electrical Characteristics chapter:
– In "Flash Memory Characteristics" table, corrected Mass erase time
– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)
– In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time
January 2010 6712
■ Deleted MAXADCSPD bit field from DCGC0 register as it is not applicable in Deep-Sleep mode.
■ Removed erroneous reference to the WRC bit in the Hibernation chapter.
■ Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers
because the module resets in 32-bit mode.
■ Clarified PWM source for ADC triggering.
■ Clarified CAN bit timing and corrected examples.
■ Made these changes to the Electrical Characteristics chapter:
– Removed VSIH and VSIL parameters from Operating Conditions table.
– Added table showing actual PLL frequency depending on input crystal.
– Changed the name of the tHIB_REG_WRITE parameter to tHIB_REG_ACCESS.
– Revised ADC electrical specifications to clarify, including reorganizing and adding new data.
– Changed SSI set up and hold times to be expressed in system clocks, not ns.
October 2009 6462
July 2009 5920 Corrected ordering numbers.
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Table 1. Revision History (continued)
Date Revision Description
■ Clarified Power-on reset and RST pin operation; added new diagrams.
■ Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL)
registers.
■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.
■ Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1
registers.
■ Changed buffer type for WAKE pin to TTL and HIB pin to OD.
■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added EIR
(Internal voltage reference error) parameter.
■ Additional minor data sheet clarifications and corrections.
July 2009 5902
■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 164).
■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
of the output divisor.
■ Added "GPIO Module DC Characteristics" table (see Table 22-4 on page 680).
■ Additional minor data sheet clarifications and corrections.
April 2009 5367
■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.
■ Clarification added as to what happens when the SSI in slave mode is required to transmit but there
is no data in the TX FIFO.
■ Corrected bit timing examples in CAN chapter.
■ Additional minor data sheet clarifications and corrections.
January 2009 4660
■ Revised High-Level Block Diagram.
■ Additional minor data sheet clarifications and corrections were made.
November 2008 4283
■ Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG)
register.
■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the
Internal Memory chapter. The correct value is 0x0000.0006.
■ In the CAN chapter, major improvements were made including a rewrite of the conceptual information
and the addition of new figures to clarify how to use the Controller Area Network (CAN) module.
■ Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter.
October 2008 4149
■ Added note on clearing interrupts to Interrupts chapter.
■ Added Power Architecture diagram to System Control chapter.
■ Additional minor data sheet clarifications and corrections.
August 2008 3447
July 2008 3108 ■ Additional minor data sheet clarifications and corrections.
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Revision History
Table 1. Revision History (continued)
Date Revision Description
■ The 108-Ball BGA pin diagram and pin tables had an error. The following signals were erroneously
indicated as available and have now been changed to a No Connect (NC):
– Ball C1: Changed PE7 to NC
– Ball C2: Changed PE6 to NC
– Ball D2: Changed PE5 to NC
– Ball D1: Changed PE4 to NC
■ As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use
the LDO output as the source of VDD25 input.
■ Additional minor data sheet clarifications and corrections.
May 2008 2972
April 2008 2881 ■ The ΘJA value was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating
Characteristics chapter.
■ Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of
1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock.
■ Values for IDD_HIBERNATE were added to the "Detailed Power Specifications" table in the "Electrical
Characteristics" chapter.
■ The "Hibernation Module DC Electricals" table was added to the "Electrical Characteristics" chapter.
■ The TVDDRISE parameter in the "Reset Characteristics" table in the "Electrical Characteristics" chapter
was changed from a max of 100 to 250.
■ The maximum value on Core supply voltage (VDD25) in the "Maximum Ratings" table in the "Electrical
Characteristics" chapter was changed from 4 to 3.
■ The operational frequency of the internal 30-kHz oscillator clock source is 30 kHz ± 50% (prior data
sheets incorrectly noted it as 30 kHz ± 30%).
■ A value of 0x3 in bits 5:4 of the MISC register (OSCSRC) indicates the 30-KHz internal oscillator is
the input source for the oscillator. Prior data sheets incorrectly noted 0x3 as a reserved value.
■ The reset for bits 6:4 of the RCC2 register (OSCSRC2) is 0x1 (IOSC). Prior data sheets incorrectly
noted the reset was 0x0 (MOSC).
■ Two figures on clock source were added to the "Hibernation Module":
– Clock Source Using Crystal
– Clock Source Using Dedicated Oscillator
■ The following notes on battery management were added to the "Hibernation Module" chapter:
– Battery voltage is not measured while in Hibernate mode.
– System level factors may affect the accuracy of the low battery detect circuit. The designer
should consider battery type, discharge characteristics, and a test load during battery voltage
measurements.
■ A note on high-current applications was added to the GPIO chapter:
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
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Table 1. Revision History (continued)
Date Revision Description
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.
■ A note on Schmitt inputs was added to the GPIO chapter:
Pins configured as digital inputs are Schmitt-triggered.
■ The Buffer type on the WAKE pin changed from OD to - in the Signal Tables.
■ The "Differential Sampling Range" figures in the ADC chapter were clarified.
■ The last revision of the data sheet (revision 2550) introduced two errors that have now been corrected:
– The LQFP pin diagrams and pin tables were missing the comparator positive and negative input
pins.
– The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams.
■ Additional minor data sheet clarifications and corrections.
March 2008 2550 Started tracking revision history.
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Revision History
About This Document
This data sheet provides reference information for the LM3S2965 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following related documents are available on the Stellaris® web site at www.ti.com/stellaris:
■ Stellaris® Errata
■ ARM® Cortex™-M3 Errata
■ Cortex™-M3 Instruction Set Technical User's Manual
■ Stellaris® Graphics Library User's Guide
■ Stellaris® Peripheral Driver Library User's Guide
The following related documents are also referenced:
■ ARM® Debug Interface V5 Architecture Specification
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.
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Documentation Conventions
This document uses the conventions shown in Table 2 on page 32.
Table 2. Documentation Conventions
Notation Meaning
General Register Notation
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
REGISTER
bit A single bit in a register.
bit field Two or more consecutive and related bits.
A hexadecimal increment to a register's address, relative to that module's base address as specified
in Table 2-4 on page 71.
offset 0xnnn
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Register N
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
reserved
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
yy:xx
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Register Bit/Field
Types
RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO Software can read this field. Always write the chip reset value.
R/W Software can read or write this field.
R/WC Software can read or write this field. Writing to it with any value clears the register.
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1C
Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
R/W1S
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
W1C
WO Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field This value in the register bit diagram shows the bit/field value after any reset, unless noted.
Reset Value
0 Bit cleared to 0 on chip reset.
1 Bit set to 1 on chip reset.
- Nondeterministic.
Pin/Signal Notation
[ ] Pin alternate function; a pin defaults to the signal without the brackets.
pin Refers to the physical connection on the package.
signal Refers to the electrical signal encoding of a pin.
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About This Document
Table 2. Documentation Conventions (continued)
Notation Meaning
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
assert a signal
deassert a signal Change the value of the signal from the logically True state to the logically False state.
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
SIGNAL
Numbers
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
X
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
0x
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1 Architectural Overview
The Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings
high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These
pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit
devices, all in a package with a small footprint.
The Stellaris family offers efficient performance and extensive integration, favorably positioning the
device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris LM3S2000 series, designed for Controller Area Network (CAN) applications,
extends the Stellaris family with Bosch CAN networking technology, the golden standard in short-haul
industrial networks. The Stellaris LM3S2000 series also marks the first integration of CAN capabilities
with the revolutionary Cortex-M3 core.
The LM3S2965 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S2965 microcontroller features
a battery-backed Hibernation module to efficiently power down the LM3S2965 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S2965 microcontroller perfectly for
battery applications.
In addition, the LM3S2965 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S2965 microcontroller is code-compatible
to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise
needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network. See “Ordering and Contact
Information” on page 723 for ordering information for Stellaris family devices.
1.1 Product Features
The LM3S2965 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
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– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 42 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ ARM® Cortex™-M3 Processor Core
– Compact core.
– Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the
memory size usually associated with 8- and 16-bit devices; typically in the range of a few
kilobytes of memory for microcontroller class applications.
– Rapid application execution through Harvard architecture characterized by separate buses
for instruction and data.
– Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
– Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
– Memory protection unit (MPU) to provide a privileged mode of operation for complex
applications.
– Migration from the ARM7™ processor family for better performance and power efficiency.
– Full-featured debug solution
• Serial Wire JTAG Debug Port (SWJ-DP)
• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
• Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
• Instrumentation Trace Macrocell (ITM) for support of printf style debugging
• Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
– Optimized for single-cycle flash usage
– Three sleep modes with clock gating for low power
– Single-cycle multiply instruction and hardware divide
– Atomic operations
– ARM Thumb2 mixed 16-/32-bit instruction set
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– 1.25 DMIPS/MHz
■ JTAG
– IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
– Four-bit Instruction Register (IR) chain for storing JTAG instructions
– IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
– ARM additional instructions: APACC, DPACC and ABORT
– Integrated ARM Serial Wire Debug (SWD)
■ Hibernation
– System power control using discrete external regulator
– Dedicated pin for waking from an external signal
– Low-battery detection, signaling, and interrupt generation
– 32-bit real-time clock (RTC)
– Two 32-bit RTC match registers for timed wake-up and interrupt generation
– Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal
– RTC predivider trim for making fine adjustments to the clock rate
– 64 32-bit words of non-volatile memory
– Programmable interrupts for RTC match, external wake, and low battery events
■ Internal Memory
– 256 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 64 KB single-cycle SRAM
■ GPIOs
– 3-56 GPIOs, depending on configuration
– 5-V-tolerant in input configuration
– Programmable control for GPIO interrupts
• Interrupt generation masking
• Edge-triggered on rising, falling, or both
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• Level-sensitive on High or Low values
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Pins configured as digital inputs are Schmitt-triggered.
– Programmable control for GPIO pad configuration
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be
configured with an 18-mA pad drive for high-current applications
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ General-Purpose Timers
– Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit
timers/counters. Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
• To trigger analog-to-digital conversions
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes
only)
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
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• ADC event trigger
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ ADC
– Four analog input channels
– Single-ended and differential-input configurations
– On-chip internal temperature sensor
– Sample rate of one million samples/second
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Flexible trigger control
• Controller (software)
• Timers
• Analog Comparators
• PWM
• GPIO
– Hardware averaging of up to 64 samples for improved accuracy
– Converter uses an internal 3-V reference
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– Power and ground for the analog circuitry is separate from the digital power and ground
■ UART
– Three fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
– Programmable baud-rate generator allowing speeds up to 3.125 Mbps
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– Line-break generation and detection
– Fully programmable serial interface characteristics
• 5, 6, 7, or 8 data bits
• Even, odd, stick, or no-parity bit generation/detection
• 1 or 2 stop bit generation
– IrDA serial-IR (SIR) encoder/decoder providing
• Programmable use of IrDA Serial Infrared (SIR) or UART input/output
• Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
• Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
• Programmable internal clock generator enabling division of reference clock by 1 to 256
for low-power mode bit duration
■ Synchronous Serial Interface (SSI)
– Two SSI modules, each with the following features:
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ I2C
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– Two I2C modules, each with the following features:
– Devices on the I2C bus can be designated as either a master or a slave
• Supports both sending and receiving data as either a master or a slave
• Supports simultaneous master and slave operation
– Four I2C modes
• Master transmit
• Master receive
• Slave transmit
• Slave receive
– Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
– Master and slave interrupt generation
• Master generates interrupts when a transmit or receive operation completes (or aborts
due to an error)
• Slave generates interrupts when data has been sent or requested by a master
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ Controller Area Network (CAN)
– Two CAN modules, each with the following features:
– CAN protocol version 2.0 part A/B
– Bit rates up to 1 Mbps
– 32 message objects with individual identifier masks
– Maskable interrupt
– Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
– Programmable Loopback mode for self-test operation
– Programmable FIFO mode enables storage of multiple message objects
– Gluelessly attaches to an external CAN interface through the CANnTX and CANnRX signals
■ Analog Comparators
– Three independent integrated analog comparators
– Configurable for output to drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
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– Compare external pin input to external pin input or to internal programmable voltage reference
– Compare a test voltage against any one of these voltages
• An individual external reference voltage
• A shared single external reference voltage
• A shared internal reference voltage
■ PWM
– Three PWM generator blocks, each with one 16-bit counter, two PWM comparators, a PWM
signal generator, a dead-band generator, and an interrupt/ADC-trigger selector
– One fault input in hardware to promote low-latency shutdown
– One 16-bit counter
• Runs in Down or Up/Down mode
• Output frequency controlled by a 16-bit load value
• Load value updates can be synchronized
• Produces output signals at zero and load value
– Two PWM comparators
• Comparator value updates can be synchronized
• Produces output signals on match
– PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
• Produces two independent PWM signals
– Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge
• Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
• PWM output enable of each PWM signal
• Optional output inversion of each PWM signal (polarity control)
• Optional fault handling for each PWM signal
• Synchronization of timers in the PWM generator blocks
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• Synchronization of timer/comparator updates across the PWM generator blocks
• Interrupt status summary of the PWM generator blocks
– Can initiate an ADC sample sequence
■ QEI
– Two QEI modules, each with the following features:
– Position integrator that tracks the encoder position
– Velocity capture using built-in timer
– The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz for a 50-MHz system)
– Interrupt generation on:
• Index pulse
• Velocity-timer expiration
• Direction change
• Quadrature error detection
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Industrial and extended temperature 100-pin RoHS-compliant LQFP package
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■ Industrial-range 108-ball RoHS-compliant BGA package
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
1.3 High-Level Block Diagram
Figure 1-1 on page 44 depicts the features on the Stellaris LM3S2965 microcontroller.
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Figure 1-1. Stellaris LM3S2965 Microcontroller High-Level Block Diagram
LM3S2965
ARM®
Cortex™-M3
(50 MHz)
NVIC MPU
Flash
(256 KB)
DCode bus
ICode bus
JTAG/SWD
System
Control and
Clocks
Bus Matrix
System Bus
SRAM
(64 KB)
SYSTEM PERIPHERALS
Watchdog
Timer
(1)
Hibernation
Module
General-
Purpose
Timers (4)
GPIOs
(3-56)
SERIAL PERIPHERALS
UARTs
(3)
I2C
(2)
SSI
(2)
CAN
Controllers
(2)
ANALOG PERIPHERALS
ADC
Channels
(4)
Analog
Comparators
(3)
MOTION CONTROL PERIPHERALS
QEI
(2)
PWM
(6)
Advanced Peripheral Bus (APB)
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1.4 Functional Overview
The following sections provide an overview of the features of the LM3S2965 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 723.
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 52)
All members of the Stellaris product family, including the LM3S2965 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
1.4.1.2 Memory Map (see page 71)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S2965 controller can be found in Table 2-4 on page 71. Register addresses are given as a
hexadecimal increment, relative to the module's base address as shown in the memory map.
1.4.1.3 System Timer (SysTick) (see page 94)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.4 Nested Vectored Interrupt Controller (NVIC) (see page 95)
The LM3S2965 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM® Cortex™-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 42 interrupts.
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1.4.1.5 System Control Block (SCB) (see page 97)
The SCB provides system implementation information and system control, including configuration,
control, and reporting of system exceptions.
1.4.1.6 Memory Protection Unit (MPU) (see page 97)
The MPU supports the standard ARMv7 Protected Memory System Architecture (PMSA) model.
The MPU provides full support for protection regions, overlapping protection regions, access
permissions, and exporting memory attributes to the system.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S2965 controller features Pulse Width Modulation (PWM) outputs
and the Quadrature Encoder Interface (QEI).
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
On the LM3S2965, PWM motion control functionality can be achieved through:
■ Dedicated, flexible motion control hardware using the PWM pins
■ The motion control features of the general-purpose timers using the CCP pins
PWM Pins (see page 591)
The LM3S2965 PWM module consists of three PWM generator blocks and a control block. Each
PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a
PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control
block determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. The output of the PWM
generation blocks are managed by the output control block before being passed to the device pins.
CCP Pins (see page 330)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
Fault Pin (see page 596)
The LM3S2965 PWM module includes one fault-condition handling input to quickly provide low-latency
shutdown and prevent damage to the motor being controlled.
1.4.2.2 QEI (see page 629)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
The Stellaris quadrature encoder with index (QEI) module interprets the code produced by a
quadrature encoder wheel to integrate position over time and determine direction of rotation. In
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addition, it can capture a running estimate of the velocity of the encoder wheel. The LM3S2965
microcontroller includes two QEI modules, which enables control of two motors at the same time.
1.4.3 Analog Peripherals
To handle analog signals, the LM3S2965 microcontroller offers an Analog-to-Digital Converter
(ADC).
For support of analog signals, the LM3S2965 microcontroller offers three analog comparators.
1.4.3.1 ADC (see page 384)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The LM3S2965 ADC module features 10-bit conversion resolution and supports four input channels,
plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up
to eight analog input sources without controller intervention. Each sample sequence provides flexible
programming with fully configurable input source, trigger events, interrupt generation, and sequence
priority.
1.4.3.2 Analog Comparators (see page 579)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S2965 microcontroller provides three independent integrated analog comparators that can
be configured to drive an output or generate an interrupt or ADC event.
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
1.4.4 Serial Communications Peripherals
The LM3S2965 controller supports both asynchronous and synchronous serial communications
with:
■ Three fully programmable 16C550-type UARTs
■ Two SSI modules
■ Two I2C modules
■ Two CAN units
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1.4.4.1 UART (see page 420)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S2965 controller includes three fully programmable 16C550-type UARTs that support data
transfer speeds up to 3.125 Mbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and receive (RX) FIFOs reduce CPU interrupt service loading. The
UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.4.2 SSI (see page 461)
Synchronous Serial Interface (SSI) is a four-wire bi-directional full and low-speed communications
interface.
The LM3S2965 controller includes two SSI modules that provide the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
Each SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
Each SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
Each SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.4.3 I2C (see page 498)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL).
The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking
devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and
diagnostic purposes in product development and manufacture.
The LM3S2965 controller includes two I2C modules that provide the ability to communicate to other
IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write
and read) data.
Devices on the I2C bus can be designated as either a master or a slave. Each I2C module supports
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive,
Slave Transmit, and Slave Receive.
A Stellaris I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
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Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error). The I2C slave generates
interrupts when data has been sent or requested by a master.
1.4.4.4 Controller Area Network (see page 534)
Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair
wire. Originally created for automotive purposes, now it is used in many embedded control
applications (for example, industrial or medical). Bit rates up to 1Mb/s are possible at network lengths
below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kb/s at
500m).
A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis
of the identifier received whether it should process the message. The identifier also determines the
priority that the message enjoys in competition for bus access. Each CAN message can transmit
from 0 to 8 bytes of user information. The LM3S2965 includes two CAN units.
1.4.5 System Peripherals
1.4.5.1 Programmable GPIOs (see page 282)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris GPIO module is comprised of eight physical GPIO blocks, each corresponding to an
individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP
for Real-Time Microcontrollers specification) and supports 3-56 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal
Tables” on page 648 for the signals available to each GPIO pin).
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines. Pins configured as digital inputs are
Schmitt-triggered.
1.4.5.2 Four Programmable Timers (see page 324)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
Timers can also be used to trigger analog-to-digital (ADC) conversions.
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.5.3 Watchdog Timer (see page 360)
A watchdog timer can generate an interrupt or a reset when a time-out value is reached. The
watchdog timer is used to regain control when a system has failed due to a software error or to the
failure of an external device to respond in the expected way.
The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
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The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
1.4.6 Memory Peripherals
The LM3S2965 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.6.1 SRAM (see page 256)
The LM3S2965 static random access memory (SRAM) controller supports 64 KB SRAM. The internal
SRAM of the Stellaris devices starts at base address 0x2000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
1.4.6.2 Flash (see page 257)
The LM3S2965 Flash controller supports 256 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
1.4.7 Additional Features
1.4.7.1 JTAG TAP Controller (see page 158)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is composed of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core.
This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO
outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive
programming for the ARM, Stellaris, and unimplemented JTAG instructions.
1.4.7.2 System Control and Clocks (see page 170)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
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Architectural Overview
1.4.7.3 Hibernation Module (see page 236)
The Hibernation module provides logic to switch power off to the main processor and peripherals,
and to wake on external or time-based events. The Hibernation module includes power-sequencing
logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt
signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used
for saving state during hibernation.
1.4.8 Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 646
■ “Signal Tables” on page 648
■ “Operating Characteristics” on page 678
■ “Electrical Characteristics” on page 679
■ “Package Information” on page 725
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2 The Cortex-M3 Processor
The ARM® Cortex™-M3 processor provides a high-performance, low-cost platform that meets the
system requirements of minimal memory implementation, reduced pin count, and low power
consumption, while delivering outstanding computational performance and exceptional system
response to interrupts. Features include:
■ Compact core.
■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of
memory for microcontroller class applications.
■ Rapid application execution through Harvard architecture characterized by separate buses for
instruction and data.
■ Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.
■ Migration from the ARM7™ processor family for better performance and power efficiency.
■ Full-featured debug solution
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
■ Optimized for single-cycle flash usage
■ Three sleep modes with clock gating for low power
■ Single-cycle multiply instruction and hardware divide
■ Atomic operations
■ ARM Thumb2 mixed 16-/32-bit instruction set
■ 1.25 DMIPS/MHz
The Stellaris® family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motor control.
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This chapter provides information on the Stellaris implementation of the Cortex-M3 processor,
including the programming model, the memory model, the exception model, fault handling, and
power management.
For technical details on the instruction set, see the Cortex™-M3 Instruction Set Technical User's
Manual.
2.1 Block Diagram
The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor delivers
exceptional power efficiency through an efficient instruction set and extensively optimized design,
providing high-end processing hardware including single-cycle 32x32 multiplication and dedicated
hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly coupled
system components that reduce processor area while significantly improving interrupt handling and
system debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction
set, ensuring high code density and reduced program memory requirements. The Cortex-M3
instruction set provides the exceptional performance expected of a modern 32-bit architecture, with
the high code density of 8-bit and 16-bit microcontrollers.
The Cortex-M3 processor closely integrates a nested interrupt controller (NVIC), to deliver
industry-leading interrupt performance. The Stellaris NVIC includes a non-maskable interrupt (NMI)
and provides eight interrupt priority levels. The tight integration of the processor core and NVIC
provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency.
The hardware stacking of registers and the ability to suspend load-multiple and store-multiple
operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs
which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces
the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC
integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be
rapidly powered down.
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Figure 2-1. CPU Block Diagram
Private Peripheral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
Instrumentation
Trace Macrocell
Trace
Port
Interface
Unit
CM3 Core
Instructions Data
Flash
Patch and
Breakpoint
Memory
Protection
Unit
Debug
Access Port
Nested
Vectored
Interrupt
Controller
Serial Wire JTAG
Debug Port
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
ROM
Table
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex-M3
2.2 Overview
2.2.1 System-Level Interface
The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide
high-speed, low-latency memory accesses. The core supports unaligned data accesses and
implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and
thread-safe Boolean data handling.
The Cortex-M3 processor has a memory protection unit (MPU) that provides fine-grain memory
control, enabling applications to implement security privilege levels and separate code, data and
stack on a task-by-task basis.
2.2.2 Integrated Configurable Debug
The Cortex-M3 processor implements a complete hardware debug solution, providing high system
visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire
Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Stellaris
implementation replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and
JTAG debug ports into one module. See the ARM® Debug Interface V5 Architecture Specification
for details on SWJ-DP.
For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace
events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data
trace, and profiling information through a single pin.
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The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators
that debuggers can use. The comparators in the FPB also provide remap functions of up to eight
words in the program code in the CODE memory region. This enables applications stored in a
read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory.
If a patch is required, the application programs the FPB to remap a number of addresses. When
those addresses are accessed, the accesses are redirected to a remap table specified in the FPB
configuration.
For more information on the Cortex-M3 debug capabilities, see theARM® Debug Interface V5
Architecture Specification.
2.2.3 Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer, as shown in Figure 2-2 on page 55.
Figure 2-2. TPIU Block Diagram
ATB
Interface
Asynchronous FIFO
APB
Interface
Trace Out
(serializer)
Debug
ATB
Slave
Port
APB
Slave
Port
Serial Wire
Trace Port
(SWO)
2.2.4 Cortex-M3 System Component Details
The Cortex-M3 includes the following system components:
■ SysTick
A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer
or as a simple counter (see “System Timer (SysTick)” on page 94).
■ Nested Vectored Interrupt Controller (NVIC)
An embedded interrupt controller that supports low latency interrupt processing (see “Nested
Vectored Interrupt Controller (NVIC)” on page 95).
■ System Control Block (SCB)
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The programming model interface to the processor. The SCB provides system implementation
information and system control, including configuration, control, and reporting of system
exceptions( see “System Control Block (SCB)” on page 97).
■ Memory Protection Unit (MPU)
Improves system reliability by defining the memory attributes for different memory regions. The
MPU provides up to eight different regions and an optional predefined background region (see
“Memory Protection Unit (MPU)” on page 97).
2.3 Programming Model
This section describes the Cortex-M3 programming model. In addition to the individual core register
descriptions, information about the processor modes and privilege levels for software execution and
stacks is included.
2.3.1 Processor Mode and Privilege Levels for Software Execution
The Cortex-M3 has two modes of operation:
■ Thread mode
Used to execute application software. The processor enters Thread mode when it comes out of
reset.
■ Handler mode
Used to handle exceptions. When the processor has finished exception processing, it returns to
Thread mode.
In addition, the Cortex-M3 has two privilege levels:
■ Unprivileged
In this mode, software has the following restrictions:
– Limited access to the MSR and MRS instructions and no use of the CPS instruction
– No access to the system timer, NVIC, or system control block
– Possibly restricted access to memory or peripherals
■ Privileged
In this mode, software can use all the instructions and has access to all resources.
In Thread mode, the CONTROL register (see page 70) controls whether software execution is
privileged or unprivileged. In Handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software
execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor
call to transfer control to privileged software.
2.3.2 Stacks
The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked
item on the stack memory. When the processor pushes a new item onto the stack, it decrements
the stack pointer and then writes the item to the new memory location. The processor implements
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two stacks: the main stack and the process stack, with independent copies of the stack pointer (see
the SP register on page 60).
In Thread mode, the CONTROL register (see page 70) controls whether the processor uses the
main stack or the process stack. In Handler mode, the processor always uses the main stack. The
options for processor operations are shown in Table 2-1 on page 57.
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode Use Privilege Level Stack Used
Thread Applications Privileged or unprivileged a Main stack or process stack a
Handler Exception handlers Always privileged Main stack
a. See CONTROL (page 70).
2.3.3 Register Map
Figure 2-3 on page 57 shows the Cortex-M3 register set. Table 2-2 on page 58 lists the Core
registers. The core registers are not memory mapped and are accessed by register name, so the
base address is n/a (not applicable) and there is no offset.
Figure 2-3. Cortex-M3 Register Set
SP (R13)
LR (R14)
PC (R15)
R5
R6
R7
R0
R1
R3
R4
R2
R10
R11
R12
R8
R9
Low registers
High registers
PSP‡ MSP‡
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
General-purpose registers
Stack Pointer
Link Register
Program Counter
Program status register
Exception mask registers
CONTROL register
Special registers
‡Banked version of SP
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Table 2-2. Processor Register Map
See
Offset Name Type Reset Description page
- R0 R/W - Cortex General-Purpose Register 0 59
- R1 R/W - Cortex General-Purpose Register 1 59
- R2 R/W - Cortex General-Purpose Register 2 59
- R3 R/W - Cortex General-Purpose Register 3 59
- R4 R/W - Cortex General-Purpose Register 4 59
- R5 R/W - Cortex General-Purpose Register 5 59
- R6 R/W - Cortex General-Purpose Register 6 59
- R7 R/W - Cortex General-Purpose Register 7 59
- R8 R/W - Cortex General-Purpose Register 8 59
- R9 R/W - Cortex General-Purpose Register 9 59
- R10 R/W - Cortex General-Purpose Register 10 59
- R11 R/W - Cortex General-Purpose Register 11 59
- R12 R/W - Cortex General-Purpose Register 12 59
- SP R/W - Stack Pointer 60
- LR R/W 0xFFFF.FFFF Link Register 61
- PC R/W - Program Counter 62
- PSR R/W 0x0100.0000 Program Status Register 63
- PRIMASK R/W 0x0000.0000 Priority Mask Register 67
- FAULTMASK R/W 0x0000.0000 Fault Mask Register 68
- BASEPRI R/W 0x0000.0000 Base Priority Mask Register 69
- CONTROL R/W 0x0000.0000 Control Register 70
2.3.4 Register Descriptions
This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3 on page 57.
The core registers are not memory mapped and are accessed by register name rather than offset.
Note: The register type shown in the register descriptions refers to type during program execution
in Thread mode and Handler mode. Debug access can differ.
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Register 1: Cortex General-Purpose Register 0 (R0)
Register 2: Cortex General-Purpose Register 1 (R1)
Register 3: Cortex General-Purpose Register 2 (R2)
Register 4: Cortex General-Purpose Register 3 (R3)
Register 5: Cortex General-Purpose Register 4 (R4)
Register 6: Cortex General-Purpose Register 5 (R5)
Register 7: Cortex General-Purpose Register 6 (R6)
Register 8: Cortex General-Purpose Register 7 (R7)
Register 9: Cortex General-Purpose Register 8 (R8)
Register 10: Cortex General-Purpose Register 9 (R9)
Register 11: Cortex General-Purpose Register 10 (R10)
Register 12: Cortex General-Purpose Register 11 (R11)
Register 13: Cortex General-Purpose Register 12 (R12)
The Rn registers are 32-bit general-purpose registers for data operations and can be accessed
from either privileged or unprivileged mode.
Cortex General-Purpose Register 0 (R0)
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
31:0 DATA R/W - Register data.
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Register 14: Stack Pointer (SP)
The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes
depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear,
this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process
Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value
from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be
accessed in either privileged or unprivileged mode.
Stack Pointer (SP)
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SP
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SP
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
31:0 SP R/W - This field is the address of the stack pointer.
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Register 15: Link Register (LR)
The Link Register (LR) is register R14, and it stores the return information for subroutines, function
calls, and exceptions. LR can be accessed from either privileged or unprivileged mode.
EXC_RETURN is loaded into LR on exception entry. See Table 2-10 on page 87 for the values and
description.
Link Register (LR)
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINK
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINK
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
31:0 LINK R/W 0xFFFF.FFFF This field is the return address.
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Register 16: Program Counter (PC)
The Program Counter (PC) is register R15, and it contains the current program address. On reset,
the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit
0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register
can be accessed in either privileged or unprivileged mode.
Program Counter (PC)
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PC
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
31:0 PC R/W - This field is the current program address.
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Register 17: Program Status Register (PSR)
Note: This register is also referred to as xPSR.
The Program Status Register (PSR) has three functions, and the register bits are assigned to the
different functions:
■ Application Program Status Register (APSR), bits 31:27,
■ Execution Program Status Register (EPSR), bits 26:24, 15:10
■ Interrupt Program Status Register (IPSR), bits 5:0
The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register
can be accessed in either privileged or unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or
the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple
instruction. Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application software
are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine
the operation that faulted (see “Exception Entry and Return” on page 85).
IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
These registers can be accessed individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example, all of the
registers can be read using PSR with the MRS instruction, or APSR only can be written to using
APSR with the MSR instruction. page 63 shows the possible register combinations for the PSR. See
the MRS and MSR instruction descriptions in the Cortex™-M3 Instruction Set Technical User's Manual
for more information about how to access the program status registers.
Table 2-3. PSR Register Combinations
Register Type Combination
PSR R/Wa, b APSR, EPSR, and IPSR
IEPSR RO EPSR and IPSR
IAPSR R/Wa APSR and IPSR
EAPSR R/Wb APSR and EPSR
a. The processor ignores writes to the IPSR bits.
b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits.
Program Status Register (PSR)
Type R/W, reset 0x0100.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
N Z C V Q ICI / IT THUMB reserved
Type R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICI / IT reserved ISRNUM
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit/Field Name Type Reset Description
APSR Negative or Less Flag
Value Description
1 The previous operation result was negative or less than.
The previous operation result was positive, zero, greater than,
or equal.
0
The value of this bit is only meaningful when accessing PSR or APSR.
31 N R/W 0
APSR Zero Flag
Value Description
1 The previous operation result was zero.
0 The previous operation result was non-zero.
The value of this bit is only meaningful when accessing PSR or APSR.
30 Z R/W 0
APSR Carry or Borrow Flag
Value Description
The previous add operation resulted in a carry bit or the previous
subtract operation did not result in a borrow bit.
1
The previous add operation did not result in a carry bit or the
previous subtract operation resulted in a borrow bit.
0
The value of this bit is only meaningful when accessing PSR or APSR.
29 C R/W 0
APSR Overflow Flag
Value Description
1 The previous operation resulted in an overflow.
0 The previous operation did not result in an overflow.
The value of this bit is only meaningful when accessing PSR or APSR.
28 V R/W 0
APSR DSP Overflow and Saturation Flag
Value Description
1 DSP Overflow or saturation has occurred.
DSP overflow or saturation has not occurred since reset or since
the bit was last cleared.
0
The value of this bit is only meaningful when accessing PSR or APSR.
This bit is cleared by software using an MRS instruction.
27 Q R/W 0
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Bit/Field Name Type Reset Description
EPSR ICI / IT status
These bits, along with bits 15:10, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When EPSR holds the ICI execution state, bits 26:25 are zero.
The If-Then block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M3 Instruction Set Technical User's Manual
for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
26:25 ICI / IT RO 0x0
EPSR Thumb State
This bit indicates the Thumb state and should always be set.
The following can clear the THUMB bit:
■ The BLX, BX and POP{PC} instructions
■ Restoration from the stacked xPSR value on an exception return
■ Bit 0 of the vector value on an exception entry
Attempting to execute instructions when this bit is clear results in a fault
or lockup. See “Lockup” on page 89 for more information.
The value of this bit is only meaningful when accessing PSR or EPSR.
24 THUMB RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:16 reserved RO 0x00
EPSR ICI / IT status
These bits, along with bits 26:25, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When an interrupt occurs during the execution of an LDM, STM, PUSH
or POP instruction, the processor stops the load multiple or store multiple
instruction operation temporarily and stores the next register operand
in the multiple operation to bits 15:12. After servicing the interrupt, the
processor returns to the register pointed to by bits 15:12 and resumes
execution of the multiple load or store instruction. When EPSR holds
the ICI execution state, bits 11:10 are zero.
The If-Then block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M3 Instruction Set Technical User's Manual
for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
15:10 ICI / IT RO 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9:6 reserved RO 0x0
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Bit/Field Name Type Reset Description
IPSR ISR Number
This field contains the exception type number of the current Interrupt
Service Routine (ISR).
Value Description
0x00 Thread mode
0x01 Reserved
0x02 NMI
0x03 Hard fault
0x04 Memory management fault
0x05 Bus fault
0x06 Usage fault
0x07-0x0A Reserved
0x0B SVCall
0x0C Reserved for Debug
0x0D Reserved
0x0E PendSV
0x0F SysTick
0x10 Interrupt Vector 0
0x11 Interrupt Vector 1
... ...
0x3B Interrupt Vector 43
0x3C-0x3F Reserved
See “Exception Types” on page 80 for more information.
The value of this field is only meaningful when accessing PSR or IPSR.
5:0 ISRNUM RO 0x00
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Register 18: Priority Mask Register (PRIMASK)
The PRIMASK register prevents activation of all exceptions with programmable priority. Reset,
non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions
should be disabled when they might impact the timing of critical tasks. This register is only accessible
in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and
the CPS instruction may be used to change the value of the PRIMASK register. See the Cortex™-M3
Instruction Set Technical User's Manual for more information on these instructions. For more
information on exception priority levels, see “Exception Types” on page 80.
Priority Mask Register (PRIMASK)
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PRIMASK
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x0000.000
Priority Mask
Value Description
Prevents the activation of all exceptions with configurable
priority.
1
0 No effect.
0 PRIMASK R/W 0
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Register 19: Fault Mask Register (FAULTMASK)
The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt
(NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register
is only accessible in privileged mode. The MSR and MRS instructions are used to access the
FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK
register. See the Cortex™-M3 Instruction Set Technical User's Manual for more information on
these instructions. For more information on exception priority levels, see “Exception
Types” on page 80.
Fault Mask Register (FAULTMASK)
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved FAULTMASK
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x0000.000
Fault Mask
Value Description
1 Prevents the activation of all exceptions except for NMI.
0 No effect.
The processor clears the FAULTMASK bit on exit from any exception
handler except the NMI handler.
0 FAULTMASK R/W 0
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Register 20: Base Priority Mask Register (BASEPRI)
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is
set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority
level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of
critical tasks. This register is only accessible in privileged mode. For more information on exception
priority levels, see “Exception Types” on page 80.
Base Priority Mask Register (BASEPRI)
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BASEPRI reserved
Type RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0000.00
Base Priority
Any exception that has a programmable priority level with the same or
lower priority as the value of this field is masked. The PRIMASK register
can be used to mask all exceptions with programmable priority levels.
Higher priority exceptions have lower priority levels.
Value Description
0x0 All exceptions are unmasked.
0x1 All exceptions with priority level 1-7 are masked.
0x2 All exceptions with priority level 2-7 are masked.
0x3 All exceptions with priority level 3-7 are masked.
0x4 All exceptions with priority level 4-7 are masked.
0x5 All exceptions with priority level 5-7 are masked.
0x6 All exceptions with priority level 6-7 are masked.
0x7 All exceptions with priority level 7 are masked.
7:5 BASEPRI R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4:0 reserved RO 0x0
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Register 21: Control Register (CONTROL)
The CONTROL register controls the stack used and the privilege level for software execution when
the processor is in Thread mode. This register is only accessible in privileged mode.
Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the
CONTROL register when in Handler mode. The exception entry and return mechanisms automatically
update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 87).
In an OS environment, threads running in Thread mode should use the process stack and the kernel
and exception handlers should use the main stack. By default, Thread mode uses MSP. To switch
the stack pointer used in Thread mode to PSP, either use the MSR instruction to set the ASP bit, as
detailed in the Cortex™-M3 Instruction Set Technical User's Manual, or perform an exception return
to Thread mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 87.
Note: When changing the stack pointer, software must use an ISB instruction immediately after
the MSR instruction, ensuring that instructions after the ISB execute use the new stack
pointer. See the Cortex™-M3 Instruction Set Technical User's Manual.
Control Register (CONTROL)
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ASP TMPL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x0000.000
Active Stack Pointer
Value Description
1 PSP is the current stack pointer.
0 MSP is the current stack pointer
In Handler mode, this bit reads as zero and ignores writes. The
Cortex-M3 updates this bit automatically on exception return.
1 ASP R/W 0
Thread Mode Privilege Level
Value Description
1 Unprivileged software can be executed in Thread mode.
0 Only privileged software can be executed in Thread mode.
0 TMPL R/W 0
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2.3.5 Exceptions and Interrupts
The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested
Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the
normal flow of software control. The processor uses Handler mode to handle all exceptions except
for reset. See “Exception Entry and Return” on page 85 for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller
(NVIC)” on page 95 for more information.
2.3.6 Data Types
The Cortex-M3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports
64-bit data transfer instructions. All instruction and data memory accesses are little endian. See
“Memory Regions, Types and Attributes” on page 73 for more information.
2.4 Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the
bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable
memory.
The memory map for the LM3S2965 controller is provided in Table 2-4 on page 71. In this manual,
register addresses are given as a hexadecimal increment, relative to the module’s base address
as shown in the memory map.
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic
operations to bit data (see “Bit-Banding” on page 75).
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral
registers (see “Cortex-M3 Peripherals” on page 94).
Note: Within the memory map, all reserved space returns a bus fault when read or written.
Table 2-4. Memory Map
For details,
see page ...
Start End Description
Memory
0x0000.0000 0x0003.FFFF On-chip Flash 257
0x0004.0000 0x1FFF.FFFF Reserved -
0x2000.0000 0x2000.FFFF Bit-banded on-chip SRAM 256
0x2001.0000 0x21FF.FFFF Reserved -
0x2200.0000 0x221F.FFFF Bit-band alias of 0x2000.0000 through 0x200F.FFFF 256
0x2220.0000 0x3FFF.FFFF Reserved -
FiRM Peripherals
0x4000.0000 0x4000.0FFF Watchdog timer 0 363
0x4000.1000 0x4000.3FFF Reserved -
0x4000.4000 0x4000.4FFF GPIO Port A 289
0x4000.5000 0x4000.5FFF GPIO Port B 289
0x4000.6000 0x4000.6FFF GPIO Port C 289
0x4000.7000 0x4000.7FFF GPIO Port D 289
0x4000.8000 0x4000.8FFF SSI0 472
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Table 2-4. Memory Map (continued)
For details,
see page ...
Start End Description
0x4000.9000 0x4000.9FFF SSI1 472
0x4000.A000 0x4000.BFFF Reserved -
0x4000.C000 0x4000.CFFF UART0 427
0x4000.D000 0x4000.DFFF UART1 427
0x4000.E000 0x4000.EFFF UART2 427
0x4000.F000 0x4001.FFFF Reserved -
Peripherals
0x4002.0000 0x4002.0FFF I2C 0 512
0x4002.1000 0x4002.1FFF I2C 1 512
0x4002.2000 0x4002.3FFF Reserved -
0x4002.4000 0x4002.4FFF GPIO Port E 289
0x4002.5000 0x4002.5FFF GPIO Port F 289
0x4002.6000 0x4002.6FFF GPIO Port G 289
0x4002.7000 0x4002.7FFF GPIO Port H 289
0x4002.8000 0x4002.8FFF PWM 599
0x4002.9000 0x4002.BFFF Reserved -
0x4002.C000 0x4002.CFFF QEI0 633
0x4002.D000 0x4002.DFFF QEI1 633
0x4002.E000 0x4002.FFFF Reserved -
0x4003.0000 0x4003.0FFF Timer 0 335
0x4003.1000 0x4003.1FFF Timer 1 335
0x4003.2000 0x4003.2FFF Timer 2 335
0x4003.3000 0x4003.3FFF Timer 3 335
0x4003.4000 0x4003.7FFF Reserved -
0x4003.8000 0x4003.8FFF ADC0 392
0x4003.9000 0x4003.BFFF Reserved -
0x4003.C000 0x4003.CFFF Analog Comparators 579
0x4003.D000 0x4003.FFFF Reserved -
0x4004.0000 0x4004.0FFF CAN0 Controller 553
0x4004.1000 0x4004.1FFF CAN1 Controller 553
0x4004.2000 0x400F.BFFF Reserved -
0x400F.C000 0x400F.CFFF Hibernation Module 243
0x400F.D000 0x400F.DFFF Flash memory control 261
0x400F.E000 0x400F.EFFF System control 183
0x400F.F000 0x41FF.FFFF Reserved -
0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF -
0x4400.0000 0xDFFF.FFFF Reserved -
Private Peripheral Bus
0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM) 54
0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT) 54
0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB) 54
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Table 2-4. Memory Map (continued)
For details,
see page ...
Start End Description
0xE000.3000 0xE000.DFFF Reserved -
0xE000.E000 0xE000.EFFF Cortex-M3 Peripherals (SysTick, NVIC, SCB, and MPU) 79
0xE000.F000 0xE003.FFFF Reserved -
0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU) 55
0xE004.1000 0xFFFF.FFFF Reserved -
2.4.1 Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region
has a defined memory type, and some regions have additional memory attributes. The memory
type and attributes determine the behavior of accesses to the region.
The memory types are:
■ Normal: The processor can re-order transactions for efficiency and perform speculative reads.
■ Device: The processor preserves transaction order relative to other transactions to Device or
Strongly Ordered memory.
■ Strongly Ordered: The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.
2.4.2 Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing the order does not affect the behavior of the instruction sequence. Normally,
if correct program execution depends on two memory accesses completing in program order,
software must insert a memory barrier instruction between the memory access instructions (see
“Software Ordering of Memory Accesses” on page 74).
However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either
Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always
observed before A2.
2.4.3 Behavior of Memory Accesses
Table 2-5 on page 74 shows the behavior of accesses to each region in the memory map. See
“Memory Regions, Types and Attributes” on page 73 for more information on memory types and
the XN attribute. Stellaris devices may have reserved memory areas within the address ranges
shown below (refer to Table 2-4 on page 71 for more information).
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Table 2-5. Memory Access Behavior
Execute Description
Never
(XN)
Address Range Memory Region Memory Type
This executable region is for program code.
Data can also be stored here.
0x0000.0000 - 0x1FFF.FFFF Code Normal -
This executable region is for data. Code
can also be stored here. This region
includes bit band and bit band alias areas
(see Table 2-6 on page 76).
0x2000.0000 - 0x3FFF.FFFF SRAM Normal -
This region includes bit band and bit band
alias areas (see Table 2-7 on page 76).
0x4000.0000 - 0x5FFF.FFFF Peripheral Device XN
0x6000.0000 - 0x9FFF.FFFF External RAM Normal - This executable region is for data.
0xA000.0000 - 0xDFFF.FFFF External device Device XN This region is for external device memory.
This region includes the NVIC, system
timer, and system control block.
Strongly XN
Ordered
Private peripheral
bus
0xE000.0000- 0xE00F.FFFF
0xE010.0000- 0xFFFF.FFFF Reserved - - -
The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M3 has separate buses that can perform
instruction fetches and data accesses simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see “Memory Protection Unit (MPU)” on page 97.
The Cortex-M3 prefetches instructions ahead of execution and speculatively prefetches from branch
target addresses.
2.4.4 Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions for the following reasons:
■ The processor can reorder some memory accesses to improve efficiency, providing this does
not affect the behavior of the instruction sequence.
■ The processor has multiple bus interfaces.
■ Memory or devices in the memory map have different wait states.
■ Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Accesses” on page 73 describes the cases where the memory
system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is
critical, software must include memory barrier instructions to force that ordering. The Cortex-M3
has the following memory barrier instructions:
■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions
complete before subsequent memory transactions.
■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions
complete before subsequent instructions execute.
■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed
memory transactions is recognizable by subsequent instructions.
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Memory barrier instructions can be used in the following situations:
■ MPU programming
– If the MPU settings are changed and the change must be effective on the very next instruction,
use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of
context switching.
– Use an ISB instruction to ensure the new MPU setting takes effect immediately after
programming the MPU region or regions, if the MPU configuration code was accessed using
a branch or call. If the MPU configuration code is entered using exception mechanisms, then
an ISB instruction is not required.
■ Vector table
If the program changes an entry in the vector table and then enables the corresponding exception,
use a DMB instruction between the operations. The DMB instruction ensures that if the exception
is taken immediately after being enabled, the processor uses the new exception vector.
■ Self-modifying code
If a program contains self-modifying code, use an ISB instruction immediately after the code
modification in the program. The ISB instruction ensures subsequent instruction execution uses
the updated program.
■ Memory map switching
If the system contains a memory map switching mechanism, use a DSB instruction after switching
the memory map in the program. The DSB instruction ensures subsequent instruction execution
uses the updated memory map.
■ Dynamic exception priority change
When an exception priority has to change when the exception is pending or active, use DSB
instructions after the change. The change then takes effect on completion of the DSB instruction.
Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require
the use of DMB instructions.
For more information on the memory barrier instructions, see the Cortex™-M3 Instruction Set
Technical User's Manual.
2.4.5 Bit-Banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses
to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table
2-6 on page 76. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band
region, as shown in Table 2-7 on page 76. For the specific address range of the bit-band regions,
see Table 2-4 on page 71.
Note: A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in
the SRAM or peripheral bit-band region.
A word access to a bit band address results in a word access to the underlying memory,
and similarly for halfword and byte accesses. This allows bit band accesses to match the
access requirements of the underlying peripheral.
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Table 2-6. SRAM Memory Bit-Banding Regions
Address Range Memory Region Instruction and Data Accesses
Direct accesses to this memory range behave as SRAM memory
accesses, but this region is also bit addressable through bit-band
alias.
0x2000.0000 - 0x200F.FFFF SRAM bit-band region
Data accesses to this region are remapped to bit band region.
A write operation is performed as read-modify-write. Instruction
accesses are not remapped.
0x2200.0000 - 0x23FF.FFFF SRAM bit-band alias
Table 2-7. Peripheral Memory Bit-Banding Regions
Address Range Memory Region Instruction and Data Accesses
Direct accesses to this memory range behave as peripheral
memory accesses, but this region is also bit addressable through
bit-band alias.
0x4000.0000 - 0x400F.FFFF Peripheral bit-band region
Data accesses to this region are remapped to bit band region.
A write operation is performed as read-modify-write. Instruction
accesses are not permitted.
0x4200.0000 - 0x43FF.FFFF Peripheral bit-band alias
The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
bit_word_offset
The position of the target bit in the bit-band memory region.
bit_word_addr
The address of the word in the alias memory region that maps to the targeted bit.
bit_band_base
The starting address of the alias region.
byte_offset
The number of the byte in the bit-band region that contains the targeted bit.
bit_number
The bit position, 0-7, of the targeted bit.
Figure 2-4 on page 77 shows examples of bit-band mapping between the SRAM bit-band alias
region and the SRAM bit-band region:
■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4)
■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4)
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■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000:
0x2200.0000 = 0x2200.0000 + (0*32) + (0*4)
■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000:
0x2200.001C = 0x2200.0000+ (0*32) + (7*4)
Figure 2-4. Bit-Band Mapping
0x23FF.FFE4
0x2200.0004
0x23FF.FFFC 0x23FF.FFF8 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x23FF.FFE0
0x2200.001C 0x2200.0018 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 0x2200.0000
32-MB Alias Region
0
7 0
7 0
0x2000.0003 0x2000.0002 0x2000.0001 0x2000.0000
6 5 4 3 2 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1
0x200F.FFFF 0x200F.FFFE 0x200F.FFFD 0x200F.FFFC
1-MB SRAM Bit-Band Region
2.4.5.1 Directly Accessing an Alias Region
Writing to a word in the alias region updates a single bit in the bit-band region.
Bit 0 of the value written to a word in the alias region determines the value written to the targeted
bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a
value with bit 0 clear writes a 0 to the bit-band bit.
Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as
writing 0xFF. Writing 0x00 has the same effect as writing 0x0E.
When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band
region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set.
2.4.5.2 Directly Accessing a Bit-Band Region
“Behavior of Memory Accesses” on page 73 describes the behavior of direct byte, halfword, or word
accesses to the bit-band regions.
2.4.6 Data Storage
The processor views memory as a linear collection of bytes numbered in ascending order from zero.
For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data
is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the
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lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte.
Figure 2-5 on page 78 illustrates how data is stored.
Figure 2-5. Data Storage
Memory Register
Address A
A+1
lsbyte
msbyte
A+2
A+3
7 0
B3 B2 B1 B0
31 24 23 16 15 8 7 0
B0
B1
B2
B3
2.4.7 Synchronization Primitives
The Cortex-M3 instruction set includes pairs of synchronization primitives which provide a
non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use these primitives to perform a guaranteed read-modify-write memory
update sequence or for a semaphore mechanism.
A pair of synchronization primitives consists of:
■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests
exclusive access to that location.
■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and
returns a status bit to a register. If this status bit is clear, it indicates that the thread or process
gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates
that the thread or process did not gain exclusive access to the memory and no write is performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
■ The word instructions LDREX and STREX
■ The halfword instructions LDREXH and STREXH
■ The byte instructions LDREXB and STREXB
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform a guaranteed read-modify-write of a memory location, software must:
1. Use a Load-Exclusive instruction to read the value of the location.
2. Update the value, as required.
3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location,
and test the returned status bit. If the status bit is clear, the read-modify-write completed
successfully; if the status bit is set, no write was performed, which indicates that the value
returned at step 1 might be out of date. The software must retry the read-modify-write sequence.
Software can use the synchronization primitives to implement a semaphore as follows:
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1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the
semaphore is free.
2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore
address.
3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the
software has claimed the semaphore. However, if the Store-Exclusive failed, another process
might have claimed the semaphore after the software performed step 1.
The Cortex-M3 includes an exclusive access monitor that tags the fact that the processor has
executed a Load-Exclusive instruction. The processor removes its exclusive access tag if:
■ It executes a CLREX instruction.
■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
■ An exception occurs, which means the processor can resolve semaphore conflicts between
different threads.
For more information about the synchronization primitive instructions, see the Cortex™-M3 Instruction
Set Technical User's Manual.
2.5 Exception Model
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on
an exception and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The
processor supports tail-chaining, which enables back-to-back interrupts to be performed without the
overhead of state saving and restoration.
Table 2-8 on page 81 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 42 interrupts (listed in Table 2-9 on page 82).
Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn)
registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and
prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting
priority levels into preemption priorities and subpriorities. All the interrupt registers are described in
“Nested Vectored Interrupt Controller (NVIC)” on page 95.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset,
Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for
all the programmable priorities.
Important: After a write to clear an interrupt source, it may take several processor cycles for the
NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the
last action in an interrupt handler, it is possible for the interrupt handler to complete
while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This situation can be avoided by either clearing the interrupt source
at the beginning of the interrupt handler or by performing a read or write after the write
to clear the interrupt source (and flush the write buffer).
See “Nested Vectored Interrupt Controller (NVIC)” on page 95 for more information on exceptions
and interrupts.
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2.5.1 Exception States
Each exception is in one of the following states:
■ Inactive. The exception is not active and not pending.
■ Pending. The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.
■ Active. An exception that is being serviced by the processor but has not completed.
Note: An exception handler can interrupt the execution of another exception handler. In this
case, both exceptions are in the active state.
■ Active and Pending. The exception is being serviced by the processor, and there is a pending
exception from the same source.
2.5.2 Exception Types
The exception types are:
■ Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a
special form of exception. When reset is asserted, the operation of the processor stops, potentially
at any point in an instruction. When reset is deasserted, execution restarts from the address
provided by the reset entry in the vector table. Execution restarts as privileged execution in
Thread mode.
■ NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by
software using the Interrupt Control and State (INTCTRL) register. This exception has the
highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs
cannot be masked or prevented from activation by any other exception or preempted by any
exception other than reset.
■ Hard Fault. A hard fault is an exception that occurs because of an error during exception
processing, or because an exception cannot be managed by any other exception mechanism.
Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with
configurable priority.
■ Memory Management Fault. A memory management fault is an exception that occurs because
of a memory protection related fault, including access violation and no match. The MPU or the
fixed memory protection constraints determine this fault, for both instruction and data memory
transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory
regions, even if the MPU is disabled.
■ Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an
instruction or data memory transaction such as a prefetch fault or a memory access fault. This
fault can be enabled or disabled.
■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction
execution, such as:
– An undefined instruction
– An illegal unaligned access
– Invalid state on instruction execution
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– An error on exception return
An unaligned address on a word or halfword memory access or division by zero can cause a
usage fault when the core is properly configured.
■ SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an
OS environment, applications can use SVC instructions to access OS kernel functions and device
drivers.
■ Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception
is only active when enabled. This exception does not activate if it is a lower priority than the
current activation.
■ PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active. PendSV is
triggered using the Interrupt Control and State (INTCTRL) register.
■ SysTick. A SysTick exception is an exception that the system timer generates when it reaches
zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception
using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor
can use this exception as system tick.
■ Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by
a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to
instruction execution. In the system, peripherals use interrupts to communicate with the processor.
Table 2-9 on page 82 lists the interrupts on the LM3S2965 controller.
For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 2-8 on page 81 shows as having
configurable priority (see the SYSHNDCTRL register on page 136 and the DIS0 register on page 111).
For more information about hard faults, memory management faults, bus faults, and usage faults,
see “Fault Handling” on page 87.
Table 2-8. Exception Types
Vector Address or Activation
Offsetb
Vector Prioritya
Number
Exception Type
Stack top is loaded from the first
entry of the vector table on reset.
- 0 - 0x0000.0000
Reset 1 -3 (highest) 0x0000.0004 Asynchronous
Non-Maskable Interrupt 2 -2 0x0000.0008 Asynchronous
(NMI)
Hard Fault 3 -1 0x0000.000C -
Memory Management 4 programmablec 0x0000.0010 Synchronous
Synchronous when precise and
asynchronous when imprecise
Bus Fault 5 programmablec 0x0000.0014
Usage Fault 6 programmablec 0x0000.0018 Synchronous
- 7-10 - - Reserved
SVCall 11 programmablec 0x0000.002C Synchronous
Debug Monitor 12 programmablec 0x0000.0030 Synchronous
- 13 - - Reserved
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Table 2-8. Exception Types (continued)
Vector Address or Activation
Offsetb
Vector Prioritya
Number
Exception Type
PendSV 14 programmablec 0x0000.0038 Asynchronous
SysTick 15 programmablec 0x0000.003C Asynchronous
Interrupts 16 and above programmabled 0x0000.0040 and above Asynchronous
a. 0 is the default priority for all the programmable priorities.
b. See “Vector Table” on page 83.
c. See SYSPRI1 on page 133.
d. See PRIn registers on page 119.
Table 2-9. Interrupts
Vector Address or Description
Offset
Interrupt Number (Bit
in Interrupt Registers)
Vector Number
0x0000.0000 - Processor exceptions
0x0000.003C
0-15 -
16 0 0x0000.0040 GPIO Port A
17 1 0x0000.0044 GPIO Port B
18 2 0x0000.0048 GPIO Port C
19 3 0x0000.004C GPIO Port D
20 4 0x0000.0050 GPIO Port E
21 5 0x0000.0054 UART0
22 6 0x0000.0058 UART1
23 7 0x0000.005C SSI0
24 8 0x0000.0060 I2C0
25 9 - Reserved
26 10 0x0000.0068 PWM Generator 0
27 11 0x0000.006C PWM Generator 1
28 12 0x0000.0070 PWM Generator 2
29 13 0x0000.0074 QEI0
30 14 0x0000.0078 ADC0 Sequence 0
31 15 0x0000.007C ADC0 Sequence 1
32 16 0x0000.0080 ADC0 Sequence 2
33 17 0x0000.0084 ADC0 Sequence 3
34 18 0x0000.0088 Watchdog Timer 0
35 19 0x0000.008C Timer 0A
36 20 0x0000.0090 Timer 0B
37 21 0x0000.0094 Timer 1A
38 22 0x0000.0098 Timer 1B
39 23 0x0000.009C Timer 2A
40 24 0x0000.00A0 Timer 2B
41 25 0x0000.00A4 Analog Comparator 0
42 26 0x0000.00A8 Analog Comparator 1
43 27 0x0000.00AC Analog Comparator 2
44 28 0x0000.00B0 System Control
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Table 2-9. Interrupts (continued)
Vector Address or Description
Offset
Interrupt Number (Bit
in Interrupt Registers)
Vector Number
45 29 0x0000.00B4 Flash Memory Control
46 30 0x0000.00B8 GPIO Port F
47 31 0x0000.00BC GPIO Port G
48 32 0x0000.00C0 GPIO Port H
49 33 0x0000.00C4 UART2
50 34 0x0000.00C8 SSI1
51 35 0x0000.00CC Timer 3A
52 36 0x0000.00D0 Timer 3B
53 37 0x0000.00D4 I2C1
54 38 0x0000.00D8 QEI1
55 39 0x0000.00DC CAN0
56 40 0x0000.00E0 CAN1
57-58 41-42 - Reserved
59 43 0x0000.00EC Hibernation Module
2.5.3 Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
2.5.4 Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 81. Figure 2-6 on page 84 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
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Figure 2-6. Vector table
Initial SP value
Reset
Hard fault
NMI
Memory management fault
Usage fault
Bus fault
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
Reserved
SVCall
PendSV
Reserved for Debug
Systick
IRQ0
Reserved
0x002C
0x0038
0x003C
0x0040
Exception number Offset
2
3
4
5
6
11
12
14
15
16
18
13
7
10
1
Vector
...
8
9
IRQ1
IRQ2
0x0044
IRQ43
17
0x0048
0x004C
59
...
...
0x00EC
IRQ number
-14
-13
-12
-11
-10
-5
-2
-1
0
2
1
43
On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to
the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different
memory location, in the range 0x0000.0100 to 0x3FFF.FF00 (see “Vector Table” on page 83). Note
that when configuring the VTABLE register, the offset must be aligned on a 256-byte boundary.
2.5.5 Exception Priorities
As Table 2-8 on page 81 shows, all exceptions have an associated priority, with a lower priority
value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard
fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable
priority have a priority of 0. For information about configuring exception priorities, see page 133 and
page 119.
Note: Configurable priority values for the Stellaris implementation are in the range 0-7. This means
that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always
have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means
that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed
before IRQ[0].
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If multiple pending exceptions have the same priority, the pending exception with the lowest exception
number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same
priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a
higher priority exception occurs. If an exception occurs with the same priority as the exception being
handled, the handler is not preempted, irrespective of the exception number. However, the status
of the new interrupt changes to pending.
2.5.6 Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This
grouping divides each interrupt priority register entry into two fields:
■ An upper field that defines the group priority
■ A lower field that defines a subpriority within the group
Only the group priority determines preemption of interrupt exceptions. When the processor is
executing an interrupt exception handler, another interrupt with the same group priority as the
interrupt being handled does not preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order
in which they are processed. If multiple pending interrupts have the same group priority and
subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see
page 127.
2.5.7 Exception Entry and Return
Descriptions of exception handling use the following terms:
■ Preemption. When the processor is executing an exception handler, an exception can preempt
the exception handler if its priority is higher than the priority of the exception being handled. See
“Interrupt Priority Grouping” on page 85 for more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See
“Exception Entry” on page 86 more information.
■ Return. Return occurs when the exception handler is completed, and there is no pending
exception with sufficient priority to be serviced and the completed exception handler was not
handling a late-arriving exception. The processor pops the stack and restores the processor
state to the state it had before the interrupt occurred. See “Exception Return” on page 87 for
more information.
■ Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception
handler, if there is a pending exception that meets the requirements for exception entry, the
stack pop is skipped and control transfers to the new exception handler.
■ Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs
during state saving for a previous exception, the processor switches to handle the higher priority
exception and initiates the vector fetch for that exception. State saving is not affected by late
arrival because the state saved is the same for both exceptions. Therefore, the state saving
continues uninterrupted. The processor can accept a late arriving exception until the first instruction
of the exception handler of the original exception enters the execute stage of the processor. On
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return from the exception handler of the late-arriving exception, the normal tail-chaining rules
apply.
2.5.7.1 Exception Entry
Exception entry occurs when there is a pending exception with sufficient priority and either the
processor is in Thread mode or the new exception is of higher priority than the exception being
handled, in which case the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers
(see PRIMASK on page 67, FAULTMASK on page 68, and BASEPRI on page 69). An exception
with less priority than this is pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred to as
stacking and the structure of eight data words is referred to as stack frame.
Figure 2-7. Exception Stack Frame
Pre-IRQ top of stack
xPSR
PC
LR
R12
R3
R2
R1
R0
{aligner}
IRQ top of stack
...
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. Unless
stack alignment is disabled, the stack frame is aligned to a double-word address. If the STKALIGN
bit of the Configuration Control (CCR) register is set, stack align adjustment is performed during
stacking.
The stack frame includes the return address, which is the address of the next instruction in the
interrupted program. This value is restored to the PC at exception return so that the interrupted
program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception
handler start address from the vector table. When stacking is complete, the processor starts executing
the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR,
indicating which stack pointer corresponds to the stack frame and what operation mode the processor
was in before the entry occurred.
If no higher-priority exception occurs during exception entry, the processor starts executing the
exception handler and automatically changes the status of the corresponding pending interrupt to
active.
If another higher-priority exception occurs during exception entry, known as late arrival, the processor
starts executing the exception handler for this exception and does not change the pending status
of the earlier exception.
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2.5.7.2 Exception Return
Exception return occurs when the processor is in Handler mode and executes one of the following
instructions to load the EXC_RETURN value into the PC:
■ An LDM or POP instruction that loads the PC
■ A BX instruction using any register
■ An LDR instruction with the PC as the destination
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies
on this value to detect when the processor has completed an exception handler. The lowest four
bits of this value provide information on the return stack and processor mode. Table 2-10 on page 87
shows the EXC_RETURN values with a description of the exception return behavior.
EXC_RETURN bits 31:4 are all set. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.
Table 2-10. Exception Return Behavior
EXC_RETURN[31:0] Description
0xFFFF.FFF0 Reserved
Return to Handler mode.
Exception return uses state from MSP.
Execution uses MSP after return.
0xFFFF.FFF1
0xFFFF.FFF2 - 0xFFFF.FFF8 Reserved
Return to Thread mode.
Exception return uses state from MSP.
Execution uses MSP after return.
0xFFFF.FFF9
0xFFFF.FFFA - 0xFFFF.FFFC Reserved
Return to Thread mode.
Exception return uses state from PSP.
Execution uses PSP after return.
0xFFFF.FFFD
0xFFFF.FFFE - 0xFFFF.FFFF Reserved
2.6 Fault Handling
Faults are a subset of the exceptions (see “Exception Model” on page 79). The following conditions
generate a fault:
■ A bus error on an instruction fetch or vector table load or a data access.
■ An internally detected error such as an undefined instruction or an attempt to change state with
a BX instruction.
■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN).
■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region.
2.6.1 Fault Types
Table 2-11 on page 88 shows the types of fault, the handler used for the fault, the corresponding
fault status register, and the register bit that indicates the fault has occurred. See page 140 for more
information about the fault status registers.
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Table 2-11. Faults
Fault Handler Fault Status Register Bit Name
Bus error on a vector read Hard fault Hard Fault Status (HFAULTSTAT) VECT
Fault escalated to a hard fault Hard fault Hard Fault Status (HFAULTSTAT) FORCED
Memory Management Fault Status IERR a
(MFAULTSTAT)
Memory management
fault
MPU or default memory mismatch on
instruction access
Memory Management Fault Status DERR
(MFAULTSTAT)
Memory management
fault
MPU or default memory mismatch on
data access
Memory Management Fault Status MSTKE
(MFAULTSTAT)
Memory management
fault
MPU or default memory mismatch on
exception stacking
Memory Management Fault Status MUSTKE
(MFAULTSTAT)
Memory management
fault
MPU or default memory mismatch on
exception unstacking
Bus error during exception stacking Bus fault Bus Fault Status (BFAULTSTAT) BSTKE
Bus error during exception unstacking Bus fault Bus Fault Status (BFAULTSTAT) BUSTKE
Bus error during instruction prefetch Bus fault Bus Fault Status (BFAULTSTAT) IBUS
Precise data bus error Bus fault Bus Fault Status (BFAULTSTAT) PRECISE
Imprecise data bus error Bus fault Bus Fault Status (BFAULTSTAT) IMPRE
Attempt to access a coprocessor Usage fault Usage Fault Status (UFAULTSTAT) NOCP
Undefined instruction Usage fault Usage Fault Status (UFAULTSTAT) UNDEF
Attempt to enter an invalid instruction Usage fault Usage Fault Status (UFAULTSTAT) INVSTAT
set state b
Invalid EXC_RETURN value Usage fault Usage Fault Status (UFAULTSTAT) INVPC
Illegal unaligned load or store Usage fault Usage Fault Status (UFAULTSTAT) UNALIGN
Divide by 0 Usage fault Usage Fault Status (UFAULTSTAT) DIV0
a. Occurs on an access to an XN region even if the MPU is disabled.
b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction
with ICI continuation.
2.6.2 Fault Escalation and Hard Faults
All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on
page 133). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on
page 136).
Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another
fault handler as described in “Exception Model” on page 79.
In some situations, a fault with configurable priority is treated as a hard fault. This process is called
priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:
■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
fault occurs because a fault handler cannot preempt itself because it must have the same priority
as the current priority level.
■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This
situation happens because the handler for the new fault cannot preempt the currently executing
fault handler.
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■ An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
■ A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even
though the stack push for the handler failed. The fault handler operates but the stack contents are
corrupted.
Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.
2.6.3 Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused the
fault, as shown in Table 2-12 on page 89.
Table 2-12. Fault Status and Fault Address Registers
Handler Status Register Name Address Register Name Register Description
Hard fault Hard Fault Status (HFAULTSTAT) - page 146
page 140
page 147
Memory Management Fault
Address (MMADDR)
Memory Management Fault Status
(MFAULTSTAT)
Memory management
fault
page 140
page 148
Bus Fault Address
(FAULTADDR)
Bus fault Bus Fault Status (BFAULTSTAT)
Usage fault Usage Fault Status (UFAULTSTAT) - page 140
2.6.4 Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault
handlers. When the processor is in the lockup state, it does not execute any instructions. The
processor remains in lockup state until it is reset or an NMI occurs.
Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the
processor to leave the lockup state.
2.7 Power Management
The Cortex-M3 processor sleep modes reduce power consumption:
■ Sleep mode stops the processor clock.
■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory.
The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used
(see page 129). For more information about the behavior of the sleep modes, see “System
Control” on page 180.
This section describes the mechanisms for entering sleep mode and the conditions for waking up
from sleep mode, both of which apply to Sleep mode and Deep-sleep mode.
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2.7.1 Entering Sleep Modes
This section describes the mechanisms software can use to put the processor into one of the sleep
modes.
The system can generate spurious wake-up events, for example a debug operation wakes up the
processor. Therefore, software must be able to put the processor back into sleep mode after such
an event. A program might have an idle loop to put the processor back to sleep mode.
2.7.1.1 Wait for Interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up
condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 90). When the processor
executes a WFI instruction, it stops executing instructions and enters sleep mode. See the
Cortex™-M3 Instruction Set Technical User's Manual for more information.
2.7.1.2 Wait for Event
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit
event register. When the processor executes a WFE instruction, it checks the event register. If the
register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1,
the processor clears the register and continues executing instructions without entering sleep mode.
If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction.
Typically, this situation occurs if an SEV instruction has been executed. Software cannot access
this register directly.
See the Cortex™-M3 Instruction Set Technical User's Manual for more information.
2.7.1.3 Sleep-on-Exit
If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution
of an exception handler, it returns to Thread mode and immediately enters sleep mode. This
mechanism can be used in applications that only require the processor to run when an exception
occurs.
2.7.2 Wake Up from Sleep Mode
The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep
mode.
2.7.2.1 Wake Up from WFI or Sleep-on-Exit
Normally, the processor wakes up only when it detects an exception with sufficient priority to cause
exception entry. Some embedded systems might have to execute system restore tasks after the
processor wakes up and before executing an interrupt handler. Entry to the interrupt handler can
be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives that
is enabled and has a higher priority than current exception priority, the processor wakes up but does
not execute the interrupt handler until the processor clears PRIMASK. For more information about
PRIMASK and FAULTMASK, see page 67 and page 68.
2.7.2.2 Wake Up from WFE
The processor wakes up if it detects an exception with sufficient priority to cause exception entry.
In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers
an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about SYSCTRL, see page 129.
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2.8 Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 2-13 on page 91 lists the
supported instructions.
Note: In Table 2-13 on page 91:
■ Angle brackets, <>, enclose alternative forms of the operand
■ Braces, {}, enclose optional operands
■ The Operands column is not exhaustive
■ Op2 is a flexible second operand that can be either a register or a constant
■ Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions in
the Cortex™-M3 Instruction Set Technical User's Manual.
Table 2-13. Cortex-M3 Instruction Summary
Mnemonic Operands Brief Description Flags
ADC, ADCS {Rd,} Rn , Op2 Add with carry N,Z,C,V
ADD, ADDS {Rd,} Rn , Op2 Add N,Z,C,V
ADD, ADDW {Rd,} Rn , #imm12 Add N,Z,C,V
ADR Rd , label Load PC-relative address -
AND, ANDS {Rd ,} Rn , Op2 Logical AND N,Z,C
ASR, ASRS Rd , Rm , Arithmetic shift right N,Z,C
B label Branch -
BFC Rd , #lsb , #width Bit field clear -
BFI Rd , Rn , #lsb , #width Bit field insert -
BIC, BICS {Rd ,} Rn , Op2 Bit clear N,Z,C
BKPT #imm Breakpoint -
BL label Branch with link -
BLX Rm Branch indirect with link -
BX Rm Branch indirect -
CBNZ Rn , label Compare and branch if non-zero -
CBZ Rn , label Compare and branch if zero -
CLREX - Clear exclusive -
CLZ Rd , Rm Count leading zeros -
CMN Rn , Op2 Compare negative N,Z,C,V
CMP Rn , Op2 Compare N,Z,C,V
Change processor state, disable -
interrupts
CPSID iflags
Change processor state, enable -
interrupts
CPSIE iflags
DMB - Data memory barrier -
DSB - Data synchronization barrier -
EOR, EORS {Rd ,} Rn , Op2 Exclusive OR N,Z,C
ISB - Instruction synchronization barrier -
IT - If-Then condition block -
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Table 2-13. Cortex-M3 Instruction Summary (continued)
Mnemonic Operands Brief Description Flags
LDM Rn{!} , reglist Load multiple registers, increment after -
Load multiple registers, decrement -
before
LDMDB, LDMEA Rn{!} , reglist
LDMFD, LDMIA Rn{!} , reglist Load multiple registers, increment after -
LDR Rt , [ Rn {, #offset}] Load register with word -
LDRB, LDRBT Rt , [ Rn {, #offset}] Load register with byte -
LDRD Rt , Rt2 , [ Rn {, #offset}] Load register with two words -
LDREX Rt , [ Rn , #offset ] Load register exclusive -
LDREXB Rt, [Rn] Load register exclusive with byte -
LDREXH Rt , [Rn] Load register exclusive with halfword -
LDRH, LDRHT Rt , [ Rn{ , #offset}] Load register with halfword -
LDRSB, LDRSBT Rt , [ Rn{ , #offset}] Load register with signed byte -
LDRSH, LDRSHT Rt , [ Rn {, #offset}] Load register with signed halfword -
LDRT Rt , [ Rn {, #offset}] Load register with word -
LSL, LSLS Rd , Rm , Logical shift left N,Z,C
LSR, LSRS Rd , Rm , Logical shift right N,Z,C
MLA Rd , Rn , Rm, Ra Multiply with accumulate, 32-bit result -
MLS Rd , Rn , Rm, Ra Multiply and subtract, 32-bit result -
MOV, MOVS Rd , Op2 Move N,Z,C
MOV, MOVW Rd , #imm16 Move 16-bit constant N,Z,C
MOVT Rd , #imm16 Move top -
Move from special register to general -
register
MRS Rd , spec_reg
Move from general register to special N,Z,C,V
register
MSR spec_reg , Rn
MUL, MULS {Rd,}Rn , Rm Multiply, 32-bit result N,Z
MVN, MVNS Rd , Op2 Move NOT N,Z,C
NOP - No operation -
ORN, ORNS {Rd,} Rn , Op2 Logical OR NOT N,Z,C
ORR, ORRS {Rd,} Rn , Op2 Logical OR N,Z,C
POP reglist Pop registers from stack -
PUSH reglist Push registers onto stack -
RBIT Rd , Rn Reverse bits -
REV Rd , Rn Reverse byte order in a word -
REV16 Rd , Rn Reverse byte order in each halfword -
Reverse byte order in bottom halfword -
and sign extend
REVSH Rd , Rn
ROR, RORS Rd , Rm , Rotate right N,Z,C
RRX, RRXS Rd , Rm Rotate right with extend N,Z,C
RSB, RSBS {Rd,} Rn , Op2 Reverse subtract N,Z,C,V
SBC, SBCS {Rd,} Rn , Op2 Subtract with carry N,Z,C,V
SBFX Rd , Rn , #lsb , #width Signed bit field extract -
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Table 2-13. Cortex-M3 Instruction Summary (continued)
Mnemonic Operands Brief Description Flags
SDIV {Rd ,} Rn , Rm Signed divide -
SEV - Send event -
Signed multiply with accumulate -
(32x32+64), 64-bit result
SMLAL RdLo, RdHi, Rn, Rm
SMULL RdLo, RdHi, Rn, Rm Signed multiply (32x32), 64-bit result -
SSAT Rd, #n, Rm {,shift #s} Signed saturate Q
STM Rn{!} , reglist Store multiple registers, increment after -
Store multiple registers, decrement -
before
STMDB, STMEA Rn{!} , reglist
STMFD, STMIA Rn{!} , reglist Store multiple registers, increment after -
STR Rt , [ Rn {, #offset}] Store register word -
STRB, STRBT Rt , [ Rn {, #offset}] Store register byte -
STRD Rt , Rt2 , [ Rn {, #offset}] Store register two words -
STREX Rd , Rt , [ Rn , #offset ] Store register exclusive -
STREXB Rd , Rt , [Rn] Store register exclusive byte -
STREXH Rd , Rt , [Rn] Store register exclusive halfword -
STRH, STRHT Rt , [ Rn {, #offset}] Store register halfword -
STRSB, STRSBT Rt , [ Rn {, #offset}] Store register signed byte -
STRSH, STRSHT Rt , [ Rn {, #offset}] Store register signed halfword -
STRT Rt , [ Rn {, #offset}] Store register word -
SUB, SUBS {Rd,} Rn , Op2 Subtract N,Z,C,V
SUB, SUBW {Rd,} Rn , #imm12 Subtract 12-bit constant N,Z,C,V
SVC #imm Supervisor call -
SXTB {Rd,} Rm {,ROR #n} Sign extend a byte -
SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword -
TBB [Rn, Rm] Table branch byte -
TBH [Rn, Rm, LSL #1] Table branch halfword -
TEQ Rn, Op2 Test equivalence N,Z,C
TST Rn, Op2 Test N,Z,C
UBFX Rd , Rn , #lsb , #width Unsigned bit field extract -
UDIV {Rd,} Rn , Rm Unsigned divide -
Unsigned multiply with accumulate -
(32x32+32+32), 64-bit result
UMLAL RdLo, RdHi, Rn, Rm
UMULL RdLo, RdHi, Rn, Rm Unsigned multiply (32x 2), 64-bit result -
USAT Rd, #n, Rm {,shift #s} Unsigned saturate Q
UXTB {Rd,} Rm {,ROR #n} Zero extend a byte -
UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword -
WFE - Wait for event -
WFI - Wait for interrupt -
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3 Cortex-M3 Peripherals
This chapter provides information on the Stellaris® implementation of the Cortex-M3 processor
peripherals, including:
■ SysTick (see page 94)
Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible
control mechanism.
■ Nested Vectored Interrupt Controller (NVIC) (see page 95)
– Facilitates low-latency exception and interrupt handling
– Controls power management
– Implements system control registers
■ System Control Block (SCB) (see page 97)
Provides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
■ Memory Protection Unit (MPU) (see page 97)
Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU
provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
Table 3-1 on page 94 shows the address map of the Private Peripheral Bus (PPB). Some peripheral
register regions are split into two address regions, as indicated by two addresses listed.
Table 3-1. Core Peripheral Register Regions
Address Core Peripheral Description (see page ...)
0xE000.E010-0xE000.E01F System Timer 94
0xE000.E100-0xE000.E4EF Nested Vectored Interrupt Controller 95
0xE000.EF00-0xE000.EF03
0xE000.ED00-0xE000.ED3F System Control Block 97
0xE000.ED90-0xE000.EDB8 Memory Protection Unit 97
3.1 Functional Description
This chapter provides information on the Stellaris implementation of the Cortex-M3 processor
peripherals: SysTick, NVIC, SCB and MPU.
3.1.1 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example as:
■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine.
■ A high-speed alarm timer using the system clock.
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■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter used to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNT bit in the
STCTRL control and status register can be used to determine if an action completed within a
set duration, as part of a dynamic clock management control loop.
The timer consists of three registers:
■ SysTick Control and Status (STCTRL): A control and status counter to configure its clock,
enable the counter, enable the SysTick interrupt, and determine counter status.
■ SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the
counter's wrap value.
■ SysTick Current Value (STCURRENT): The current value of the counter.
When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps)
to the value in the STRELOAD register on the next clock edge, then decrements on subsequent
clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter
reaches zero, the COUNT status bit is set. The COUNT bit clears on reads.
Writing to the STCURRENT register clears the register and the COUNT status bit. The write does
not trigger the SysTick exception logic. On a read, the current value is the value of the register at
the time the register is accessed.
The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode,
the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick
registers.
Note: When the processor is halted for debugging, the counter does not decrement.
3.1.2 Nested Vectored Interrupt Controller (NVIC)
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses.
The NVIC supports:
■ 42 interrupts.
■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower
priority, so level 0 is the highest interrupt priority.
■ Low-latency exception and interrupt handling.
■ Level and pulse detection of interrupt signals.
■ Dynamic reprioritization of interrupts.
■ Grouping of priority values into group priority and subpriority fields.
■ Interrupt tail-chaining.
■ An external Non-maskable interrupt (NMI).
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The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead, providing low latency exception handling.
3.1.2.1 Level-Sensitive and Pulse Interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described
as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically
this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A
pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor
clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for
at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt
(see “Hardware and Software Control of Interrupts” on page 96 for more information). For a
level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR,
the interrupt becomes pending again, and the processor must execute its ISR again. As a result,
the peripheral can hold the interrupt signal asserted until it no longer needs servicing.
3.1.2.2 Hardware and Software Control of Interrupts
The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following
reasons:
■ The NVIC detects that the interrupt signal is High and the interrupt is not active.
■ The NVIC detects a rising edge on the interrupt signal.
■ Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit
in the PEND0 register on page 113 or SWTRIG on page 121.
A pending interrupt remains pending until one of the following:
■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending
to active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples
the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending,
which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the
interrupt changes to inactive.
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed
the state of the interrupt changes to pending and active. In this case, when the processor
returns from the ISR the state of the interrupt changes to pending, which might cause the
processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the processor
returns from the ISR the state of the interrupt changes to inactive.
■ Software writes to the corresponding interrupt clear-pending register bit
– For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt
does not change. Otherwise, the state of the interrupt changes to inactive.
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– For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending
or to active, if the state was active and pending.
3.1.3 System Control Block (SCB)
The System Control Block (SCB) provides system implementation information and system control,
including configuration, control, and reporting of the system exceptions.
3.1.4 Memory Protection Unit (MPU)
This section describes the Memory protection unit (MPU). The MPU divides the memory map into
a number of regions and defines the location, size, access permissions, and memory attributes of
each region. The MPU supports independent attribute settings for each region, overlapping regions,
and export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU
defines eight separate memory regions, 0-7, and a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any
region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
The Cortex-M3 MPU memory map is unified, meaning that instruction accesses and data accesses
have the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates
a memory management fault, causing a fault exception and possibly causing termination of the
process in an OS environment. In an OS environment, the kernel can update the MPU region setting
dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for
memory protection.
Configuration of MPU regions is based on memory types (see “Memory Regions, Types and
Attributes” on page 73 for more information).
Table 3-2 on page 97 shows the possible MPU region attributes. See the section called “MPU
Configuration for a Stellaris Microcontroller” on page 101 for guidelines for programming a
microcontroller implementation.
Table 3-2. Memory Attributes Summary
Memory Type Description
Strongly Ordered All accesses to Strongly Ordered memory occur in program order.
Device Memory-mapped peripherals
Normal Normal memory
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that
the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must
be accessed with aligned word accesses.
■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses.
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The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions
to prevent any previous region settings from affecting the new MPU setup.
3.1.4.1 Updating an MPU Region
To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU
Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can
be programmed separately or with a multiple-word write to program all of these registers. You can
use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using
an STM instruction.
Updating an MPU Region Using Separate Words
This example simple code configures one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R4, [R0, #0x4] ; Region Base Address
STRH R2, [R0, #0x8] ; Region Size and Enable
STRH R3, [R0, #0xA] ; Region Attribute
Disable a region before writing new region settings to the MPU if you have previously enabled the
region being changed. For example:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
BIC R2, R2, #1 ; Disable
STRH R2, [R0, #0x8] ; Region Size and Enable
STR R4, [R0, #0x4] ; Region Base Address
STRH R3, [R0, #0xA] ; Region Attribute
ORR R2, #1 ; Enable
STRH R2, [R0, #0x8] ; Region Size and Enable
Software must use memory barrier instructions:
■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that
might be affected by the change in MPU settings.
■ After MPU setup, if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by entering
an exception handler, or is followed by an exception return, because the exception entry and
exception return mechanism cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it accesses
the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region.
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For example, if all of the memory access behavior is intended to take effect immediately after the
programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is
required after changing MPU settings, such as at the end of context switch. An ISB is required if
the code that programs the MPU region or regions is entered using a branch or call. If the
programming sequence is entered using a return from exception, or by taking an exception, then
an ISB is not required.
Updating an MPU Region Using Multi-Word Writes
The MPU can be programmed directly using multi-word writes, depending how the information is
divided. Consider the following reprogramming:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable
An STM instruction can be used to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STM R0, {R1-R3} ; Region number, address, attribute, size and enable
This operation can be done in two words for pre-packed information, meaning that the MPU Region
Base Address (MPUBASE) register (see page 153) contains the required region number and has
the VALID bit set. This method can be used when the data is statically packed, for example in a
boot loader:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and region number combined
; with VALID (bit 4) set
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable
An STM instruction can be used to optimize this:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0,=MPUBASE ; 0xE000ED9C, MPU Region Base register
STM R0, {R1-R2} ; Region base address, region number and VALID bit,
; and Region Attribute, Size and Enable
Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding
bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 155) to
disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the
most-significant bit controls the last subregion. Disabling a subregion means another region
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overlapping the disabled range matches instead. If no other enabled region overlaps the disabled
subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD
field must be configured to 0x00, otherwise the MPU behavior is unpredictable.
Example of SRD Use
Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB.
To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for
region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 100 shows.
Figure 3-1. SRD Use Example
Region 1
Disabled subregion
Disabled subregion
Region 2, with
subregions
Base address of both regions
Offset from
base address
0
64KB
128KB
192KB
256KB
320KB
384KB
448KB
512KB
3.1.4.2 MPU Access Permission Attributes
The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to
the corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
Table 3-3 on page 100 shows the encodings for the TEX, C, B, and S access permission bits. All
encodings are shown for completeness, however the current implementation of the Cortex-M3 does
not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration
for a Stellaris Microcontroller” on page 101 for information on programming the MPU for Stellaris
implementations.
Table 3-3. TEX, S, C, and B Bit Field Encoding
TEX S C B Memory Type Shareability Other Attributes
000b xa 0 0 Strongly Ordered Shareable -
000 xa 0 1 Device Shareable -
Outer and inner
write-through. No write
allocate.
000 0 1 0 Normal Not shareable
000 1 1 0 Normal Shareable
000 0 1 1 Normal Not shareable
000 1 1 1 Normal Shareable
Outer and inner
noncacheable.
001 0 0 0 Normal Not shareable
001 1 0 0 Normal Shareable
001 xa 0 1 Reserved encoding - -
001 xa 1 0 Reserved encoding - -
Outer and inner
write-back. Write and
read allocate.
001 0 1 1 Normal Not shareable
001 1 1 1 Normal Shareable
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Table 3-3. TEX, S, C, and B Bit Field Encoding (continued)
TEX S C B Memory Type Shareability Other Attributes
010 xa 0 0 Device Not shareable Nonshared Device.
010 xa 0 1 Reserved encoding - -
010 xa 1 xa Reserved encoding - -
Cached memory (BB =
outer policy, AA = inner
policy).
See Table 3-4 for the
encoding of the AA and
BB bits.
1BB 0 A A Normal Not shareable
1BB 1 A A Normal Shareable
a. The MPU ignores the value of this bit.
Table 3-4 on page 101 shows the cache policy for memory attribute encodings with a TEX value in
the range of 0x4-0x7.
Table 3-4. Cache Policy for Memory Attribute Encoding
Encoding, AA or BB Corresponding Cache Policy
00 Non-cacheable
01 Write back, write and read allocate
10 Write through, no write allocate
11 Write back, no write allocate
Table 3-5 on page 101 shows the AP encodings in the MPUATTR register that define the access
permissions for privileged and unprivileged software.
Table 3-5. AP Bit Field Encoding
Unprivileged Description
Permissions
Privileged
Permissions
AP Bit Field
000 No access No access All accesses generate a permission fault.
001 R/W No access Access from privileged software only.
Writes by unprivileged software generate a
permission fault.
010 R/W RO
011 R/W R/W Full access.
100 Unpredictable Unpredictable Reserved.
101 RO No access Reads by privileged software only.
110 RO RO Read-only, by privileged or unprivileged software.
111 RO RO Read-only, by privileged or unprivileged software.
MPU Configuration for a Stellaris Microcontroller
Stellaris microcontrollers have only a single processor and no caches. As a result, the MPU should
be programmed as shown in Table 3-6 on page 101.
Table 3-6. Memory Region Attributes for Stellaris Microcontrollers
Memory Region TEX S C B Memory Type and Attributes
Flash memory 000b 0 1 0 Normal memory, non-shareable, write-through
Internal SRAM 000b 1 1 0 Normal memory, shareable, write-through
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Table 3-6. Memory Region Attributes for Stellaris Microcontrollers (continued)
Memory Region TEX S C B Memory Type and Attributes
Normal memory, shareable, write-back,
write-allocate
External SRAM 000b 1 1 1
Peripherals 000b 1 0 1 Device memory, shareable
In current Stellaris microcontroller implementations, the shareability and cache policy attributes do
not affect the system behavior. However, using these settings for the MPU regions can make the
application code more portable. The values given are for typical situations.
3.1.4.3 MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management
fault (see “Exceptions and Interrupts” on page 71 for more information). The MFAULTSTAT register
indicates the cause of the fault. See page 140 for more information.
3.2 Register Map
Table 3-7 on page 102 lists the Cortex-M3 Peripheral SysTick, NVIC, SCB, and MPU registers. The
offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals
base address of 0xE000.E000.
Note: Register spaces that are not used are reserved for future or internal use. Software should
not modify any reserved memory address.
Table 3-7. Peripherals Register Map
See
Offset Name Type Reset Description page
System Timer (SysTick) Registers
0x010 STCTRL R/W 0x0000.0000 SysTick Control and Status Register 105
0x014 STRELOAD R/W 0x0000.0000 SysTick Reload Value Register 107
0x018 STCURRENT R/WC 0x0000.0000 SysTick Current Value Register 108
Nested Vectored Interrupt Controller (NVIC) Registers
0x100 EN0 R/W 0x0000.0000 Interrupt 0-31 Set Enable 109
0x104 EN1 R/W 0x0000.0000 Interrupt 32-43 Set Enable 110
0x180 DIS0 R/W 0x0000.0000 Interrupt 0-31 Clear Enable 111
0x184 DIS1 R/W 0x0000.0000 Interrupt 32-43 Clear Enable 112
0x200 PEND0 R/W 0x0000.0000 Interrupt 0-31 Set Pending 113
0x204 PEND1 R/W 0x0000.0000 Interrupt 32-43 Set Pending 114
0x280 UNPEND0 R/W 0x0000.0000 Interrupt 0-31 Clear Pending 115
0x284 UNPEND1 R/W 0x0000.0000 Interrupt 32-43 Clear Pending 116
0x300 ACTIVE0 RO 0x0000.0000 Interrupt 0-31 Active Bit 117
0x304 ACTIVE1 RO 0x0000.0000 Interrupt 32-43 Active Bit 118
0x400 PRI0 R/W 0x0000.0000 Interrupt 0-3 Priority 119
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Table 3-7. Peripherals Register Map (continued)
See
Offset Name Type Reset Description page
0x404 PRI1 R/W 0x0000.0000 Interrupt 4-7 Priority 119
0x408 PRI2 R/W 0x0000.0000 Interrupt 8-11 Priority 119
0x40C PRI3 R/W 0x0000.0000 Interrupt 12-15 Priority 119
0x410 PRI4 R/W 0x0000.0000 Interrupt 16-19 Priority 119
0x414 PRI5 R/W 0x0000.0000 Interrupt 20-23 Priority 119
0x418 PRI6 R/W 0x0000.0000 Interrupt 24-27 Priority 119
0x41C PRI7 R/W 0x0000.0000 Interrupt 28-31 Priority 119
0x420 PRI8 R/W 0x0000.0000 Interrupt 32-35 Priority 119
0x424 PRI9 R/W 0x0000.0000 Interrupt 36-39 Priority 119
0x428 PRI10 R/W 0x0000.0000 Interrupt 40-43 Priority 119
0xF00 SWTRIG WO 0x0000.0000 Software Trigger Interrupt 121
System Control Block (SCB) Registers
0xD00 CPUID RO 0x411F.C231 CPU ID Base 122
0xD04 INTCTRL R/W 0x0000.0000 Interrupt Control and State 123
0xD08 VTABLE R/W 0x0000.0000 Vector Table Offset 126
0xD0C APINT R/W 0xFA05.0000 Application Interrupt and Reset Control 127
0xD10 SYSCTRL R/W 0x0000.0000 System Control 129
0xD14 CFGCTRL R/W 0x0000.0000 Configuration and Control 131
0xD18 SYSPRI1 R/W 0x0000.0000 System Handler Priority 1 133
0xD1C SYSPRI2 R/W 0x0000.0000 System Handler Priority 2 134
0xD20 SYSPRI3 R/W 0x0000.0000 System Handler Priority 3 135
0xD24 SYSHNDCTRL R/W 0x0000.0000 System Handler Control and State 136
0xD28 FAULTSTAT R/W1C 0x0000.0000 Configurable Fault Status 140
0xD2C HFAULTSTAT R/W1C 0x0000.0000 Hard Fault Status 146
0xD34 MMADDR R/W - Memory Management Fault Address 147
0xD38 FAULTADDR R/W - Bus Fault Address 148
Memory Protection Unit (MPU) Registers
0xD90 MPUTYPE RO 0x0000.0800 MPU Type 149
0xD94 MPUCTRL R/W 0x0000.0000 MPU Control 150
0xD98 MPUNUMBER R/W 0x0000.0000 MPU Region Number 152
0xD9C MPUBASE R/W 0x0000.0000 MPU Region Base Address 153
0xDA0 MPUATTR R/W 0x0000.0000 MPU Region Attribute and Size 155
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Table 3-7. Peripherals Register Map (continued)
See
Offset Name Type Reset Description page
0xDA4 MPUBASE1 R/W 0x0000.0000 MPU Region Base Address Alias 1 153
0xDA8 MPUATTR1 R/W 0x0000.0000 MPU Region Attribute and Size Alias 1 155
0xDAC MPUBASE2 R/W 0x0000.0000 MPU Region Base Address Alias 2 153
0xDB0 MPUATTR2 R/W 0x0000.0000 MPU Region Attribute and Size Alias 2 155
0xDB4 MPUBASE3 R/W 0x0000.0000 MPU Region Base Address Alias 3 153
0xDB8 MPUATTR3 R/W 0x0000.0000 MPU Region Attribute and Size Alias 3 155
3.3 System Timer (SysTick) Register Descriptions
This section lists and describes the System Timer registers, in numerical order by address offset.
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Register 1: SysTick Control and Status Register (STCTRL), offset 0x010
Note: This register can only be accessed from privileged mode.
The SysTick STCTRL register enables the SysTick features.
SysTick Control and Status Register (STCTRL)
Base 0xE000.E000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COUNT
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CLK_SRC INTEN ENABLE
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:17 reserved RO 0x000
Count Flag
Value Description
The SysTick timer has not counted to 0 since the last time
this bit was read.
0
The SysTick timer has counted to 0 since the last time
this bit was read.
1
This bit is cleared by a read of the register or if the STCURRENT register
is written with any value.
If read by the debugger using the DAP, this bit is cleared only if the
MasterType bit in the AHB-AP Control Register is clear. Otherwise,
the COUNT bit is not changed by the debugger read. See the ARM®
Debug Interface V5 Architecture Specification for more information on
MasterType.
16 COUNT RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:3 reserved RO 0x000
Clock Source
Value Description
External reference clock. (Not implemented for Stellaris
microcontrollers.)
0
1 System clock
Because an external reference clock is not implemented, this bit must
be set in order for SysTick to operate.
2 CLK_SRC R/W 0
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Bit/Field Name Type Reset Description
Interrupt Enable
Value Description
Interrupt generation is disabled. Software can use the
COUNT bit to determine if the counter has ever reached 0.
0
An interrupt is generated to the NVIC when SysTick counts
to 0.
1
1 INTEN R/W 0
Enable
Value Description
0 The counter is disabled.
Enables SysTick to operate in a multi-shot way. That is, the
counter loads the RELOAD value and begins counting down.
On reaching 0, the COUNT bit is set and an interrupt is
generated if enabled by INTEN. The counter then loads the
RELOAD value again and begins counting.
1
0 ENABLE R/W 0
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Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014
Note: This register can only be accessed from privileged mode.
Note: This register can only be accessed from privileged mode.
The STRELOAD register specifies the start value to load into the SysTick Current Value
(STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and
0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the
COUNT bit are activated when counting from 1 to 0.
SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock
pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required
every 100 clock pulses, 99 must be written into the RELOAD field.
SysTick Reload Value Register (STRELOAD)
Base 0xE000.E000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved RELOAD
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:24 reserved RO 0x00
Reload Value
Value to load into the SysTick Current Value (STCURRENT) register
when the counter reaches 0.
23:0 RELOAD R/W 0x00.0000
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Register 3: SysTick Current Value Register (STCURRENT), offset 0x018
Note: This register can only be accessed from privileged mode.
The STCURRENT register contains the current value of the SysTick counter.
SysTick Current Value Register (STCURRENT)
Base 0xE000.E000
Offset 0x018
Type R/WC, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved CURRENT
Type RO RO RO RO RO RO RO RO R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRENT
Type R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:24 reserved RO 0x00
Current Value
This field contains the current value at the time the register is accessed.
No read-modify-write protection is provided, so change with care.
This register is write-clear. Writing to it with any value clears the register.
Clearing this register also clears the COUNT bit of the STCTRL register.
23:0 CURRENT R/WC 0x00.0000
3.4 NVIC Register Descriptions
This section lists and describes the NVIC registers, in numerical order by address offset.
The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended
while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any
other unprivileged mode access causes a bus fault.
Ensure software uses correctly aligned register accesses. The processor does not support unaligned
accesses to NVIC registers.
An interrupt can enter the pending state even if it is disabled.
Before programming the VTABLE register to relocate the vector table, ensure the vector table
entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such
as interrupts. For more information, see page 126.
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Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100
Note: This register can only be accessed from privileged mode.
The EN0 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to
Interrupt 0; bit 31 corresponds to Interrupt 31.
See Table 2-9 on page 82 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 0-31 Set Enable (EN0)
Base 0xE000.E000
Offset 0x100
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Interrupt Enable
Value Description
On a read, indicates the interrupt is disabled.
On a write, no effect.
0
On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.
1
A bit can only be cleared by setting the corresponding INT[n] bit in
the DISn register.
31:0 INT R/W 0x0000.0000
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Register 5: Interrupt 32-43 Set Enable (EN1), offset 0x104
Note: This register can only be accessed from privileged mode.
The EN1 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to
Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 82 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 32-43 Set Enable (EN1)
Base 0xE000.E000
Offset 0x104
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved INT
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x0000.0
Interrupt Enable
Value Description
On a read, indicates the interrupt is disabled.
On a write, no effect.
0
On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.
1
A bit can only be cleared by setting the corresponding INT[n] bit in
the DIS1 register.
11:0 INT R/W 0x000
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Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180
Note: This register can only be accessed from privileged mode.
The DIS0 register disables interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt
31.
See Table 2-9 on page 82 for interrupt assignments.
Interrupt 0-31 Clear Enable (DIS0)
Base 0xE000.E000
Offset 0x180
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Interrupt Disable
Value Description
On a read, indicates the interrupt is disabled.
On a write, no effect.
0
On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN0
register, disabling interrupt [n].
1
31:0 INT R/W 0x0000.0000
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Register 7: Interrupt 32-43 Clear Enable (DIS1), offset 0x184
Note: This register can only be accessed from privileged mode.
The DIS1 register disables interrupts. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt
43. See Table 2-9 on page 82 for interrupt assignments.
Interrupt 32-43 Clear Enable (DIS1)
Base 0xE000.E000
Offset 0x184
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved INT
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x0000.0
Interrupt Disable
Value Description
On a read, indicates the interrupt is disabled.
On a write, no effect.
0
On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN1
register, disabling interrupt [n].
1
11:0 INT R/W 0x000
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Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200
Note: This register can only be accessed from privileged mode.
The PEND0 register forces interrupts into the pending state and shows which interrupts are pending.
Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31.
See Table 2-9 on page 82 for interrupt assignments.
Interrupt 0-31 Set Pending (PEND0)
Base 0xE000.E000
Offset 0x200
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Interrupt Set Pending
Value Description
On a read, indicates that the interrupt is not pending.
On a write, no effect.
0
On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.
1
If the corresponding interrupt is already pending, setting a bit has no
effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND0 register.
31:0 INT R/W 0x0000.0000
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Register 9: Interrupt 32-43 Set Pending (PEND1), offset 0x204
Note: This register can only be accessed from privileged mode.
The PEND1 register forces interrupts into the pending state and shows which interrupts are pending.
Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 82 for
interrupt assignments.
Interrupt 32-43 Set Pending (PEND1)
Base 0xE000.E000
Offset 0x204
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved INT
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x0000.0
Interrupt Set Pending
Value Description
On a read, indicates that the interrupt is not pending.
On a write, no effect.
0
On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.
1
If the corresponding interrupt is already pending, setting a bit has no
effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND1 register.
11:0 INT R/W 0x000
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Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280
Note: This register can only be accessed from privileged mode.
The UNPEND0 register shows which interrupts are pending and removes the pending state from
interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31.
See Table 2-9 on page 82 for interrupt assignments.
Interrupt 0-31 Clear Pending (UNPEND0)
Base 0xE000.E000
Offset 0x280
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Interrupt Clear Pending
Value Description
On a read, indicates that the interrupt is not pending.
On a write, no effect.
0
On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the PEND0
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.
1
31:0 INT R/W 0x0000.0000
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Register 11: Interrupt 32-43 Clear Pending (UNPEND1), offset 0x284
Note: This register can only be accessed from privileged mode.
The UNPEND1 register shows which interrupts are pending and removes the pending state from
interrupts. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table
2-9 on page 82 for interrupt assignments.
Interrupt 32-43 Clear Pending (UNPEND1)
Base 0xE000.E000
Offset 0x284
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved INT
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x0000.0
Interrupt Clear Pending
Value Description
On a read, indicates that the interrupt is not pending.
On a write, no effect.
0
On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the PEND1
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.
1
11:0 INT R/W 0x000
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Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300
Note: This register can only be accessed from privileged mode.
The ACTIVE0 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 0; bit 31
corresponds to Interrupt 31.
See Table 2-9 on page 82 for interrupt assignments.
Caution – Do not manually set or clear the bits in this register.
Interrupt 0-31 Active Bit (ACTIVE0)
Base 0xE000.E000
Offset 0x300
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Interrupt Active
Value Description
0 The corresponding interrupt is not active.
1 The corresponding interrupt is active, or active and pending.
31:0 INT RO 0x0000.0000
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Register 13: Interrupt 32-43 Active Bit (ACTIVE1), offset 0x304
Note: This register can only be accessed from privileged mode.
The ACTIVE1 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 32; bit
11 corresponds to Interrupt 43. See Table 2-9 on page 82 for interrupt assignments.
Caution – Do not manually set or clear the bits in this register.
Interrupt 32-43 Active Bit (ACTIVE1)
Base 0xE000.E000
Offset 0x304
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved INT
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x0000.0
Interrupt Active
Value Description
0 The corresponding interrupt is not active.
1 The corresponding interrupt is active, or active and pending.
11:0 INT RO 0x000
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Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400
Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404
Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408
Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C
Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410
Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414
Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418
Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C
Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420
Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424
Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428
Note: This register can only be accessed from privileged mode.
The PRIn registers provide 3-bit priority fields for each interrupt. These registers are byte accessible.
Each register holds four priority fields that are assigned to interrupts as follows:
PRIn Register Bit Field Interrupt
Bits 31:29 Interrupt [4n+3]
Bits 23:21 Interrupt [4n+2]
Bits 15:13 Interrupt [4n+1]
Bits 7:5 Interrupt [4n]
See Table 2-9 on page 82 for interrupt assignments.
Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP
field in the Application Interrupt and Reset Control (APINT) register (see page 127) indicates the
position of the binary point that splits the priority and subpriority fields .
These registers can only be accessed from privileged mode.
Interrupt 0-3 Priority (PRI0)
Base 0xE000.E000
Offset 0x400
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTD reserved INTC reserved
Type R/W R/W R/W RO RO RO RO RO R/W R/W R/W RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTB reserved INTA reserved
Type R/W R/W R/W RO RO RO RO RO R/W R/W R/W RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit/Field Name Type Reset Description
Interrupt Priority for Interrupt [4n+3]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+3], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
31:29 INTD R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28:24 reserved RO 0x0
Interrupt Priority for Interrupt [4n+2]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+2], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
23:21 INTC R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20:16 reserved RO 0x0
Interrupt Priority for Interrupt [4n+1]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+1], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
15:13 INTB R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12:8 reserved RO 0x0
Interrupt Priority for Interrupt [4n]
This field holds a priority value, 0-7, for the interrupt with the number
[4n], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
7:5 INTA R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4:0 reserved RO 0x0
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Register 25: Software Trigger Interrupt (SWTRIG), offset 0xF00
Note: Only privileged software can enable unprivileged access to the SWTRIG register.
Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI).
See Table 2-9 on page 82 for interrupt assignments.
When the MAINPEND bit in the Configuration and Control (CFGCTRL) register (see page 131) is
set, unprivileged software can access the SWTRIG register.
Software Trigger Interrupt (SWTRIG)
Base 0xE000.E000
Offset 0xF00
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved INTID
Type RO RO RO RO RO RO RO RO RO RO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x0000.00
Interrupt ID
This field holds the interrupt ID of the required SGI. For example, a value
of 0x3 generates an interrupt on IRQ3.
5:0 INTID WO 0x00
3.5 System Control Block (SCB) Register Descriptions
This section lists and describes the System Control Block (SCB) registers, in numerical order by
address offset. The SCB registers can only be accessed from privileged mode.
All registers must be accessed with aligned word accesses except for the FAULTSTAT and
SYSPRI1-SYSPRI3 registers, which can be accessed with byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to system control block registers.
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Register 26: CPU ID Base (CPUID), offset 0xD00
Note: This register can only be accessed from privileged mode.
The CPUID register contains the ARM® Cortex™-M3 processor part number, version, and
implementation information.
CPU ID Base (CPUID)
Base 0xE000.E000
Offset 0xD00
Type RO, reset 0x411F.C231
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IMP VAR CON
Type R0 R0 R0 R0 R0 R0 R0 R0 RO RO RO RO RO RO RO RO
Reset 0 1 0 0 0 0 0 1 0 0 0 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PARTNO REV
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Implementer Code
Value Description
0x41 ARM
31:24 IMP R0 0x41
Variant Number
Value Description
The rn value in the rnpn product revision identifier, for example,
the 1 in r1p1.
0x1
23:20 VAR RO 0x1
Constant
Value Description
0xF Always reads as 0xF.
19:16 CON RO 0xF
Part Number
Value Description
0xC23 Cortex-M3 processor.
15:4 PARTNO RO 0xC23
Revision Number
Value Description
The pn value in the rnpn product revision identifier, for example,
the 1 in r1p1.
0x1
3:0 REV RO 0x1
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Register 27: Interrupt Control and State (INTCTRL), offset 0xD04
Note: This register can only be accessed from privileged mode.
The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and
clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate
the exception number of the exception being processed, whether there are preempted active
exceptions, the exception number of the highest priority pending exception, and whether any interrupts
are pending.
When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and
UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits.
Interrupt Control and State (INTCTRL)
Base 0xE000.E000
Offset 0xD04
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NMISET reserved PENDSV UNPENDSV PENDSTSET PENDSTCLR reserved ISRPRE ISRPEND reserved VECPEND
Type R/W RO RO R/W WO R/W WO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VECPEND RETBASE reserved VECACT
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
NMI Set Pending
Value Description
On a read, indicates an NMI exception is not pending.
On a write, no effect.
0
On a read, indicates an NMI exception is pending.
On a write, changes the NMI exception state to pending.
1
Because NMI is the highest-priority exception, normally the processor
enters the NMI exception handler as soon as it registers the setting of
this bit, and clears this bit on entering the interrupt handler. A read of
this bit by the NMI exception handler returns 1 only if the NMI signal is
reasserted while the processor is executing that handler.
31 NMISET R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30:29 reserved RO 0x0
PendSV Set Pending
Value Description
On a read, indicates a PendSV exception is not pending.
On a write, no effect.
0
On a read, indicates a PendSV exception is pending.
On a write, changes the PendSV exception state to pending.
1
Setting this bit is the only way to set the PendSV exception state to
pending. This bit is cleared by writing a 1 to the UNPENDSV bit.
28 PENDSV R/W 0
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Bit/Field Name Type Reset Description
PendSV Clear Pending
Value Description
0 On a write, no effect.
On a write, removes the pending state from the PendSV
exception.
1
This bit is write only; on a register read, its value is unknown.
27 UNPENDSV WO 0
SysTick Set Pending
Value Description
On a read, indicates a SysTick exception is not pending.
On a write, no effect.
0
On a read, indicates a SysTick exception is pending.
On a write, changes the SysTick exception state to pending.
1
This bit is cleared by writing a 1 to the PENDSTCLR bit.
26 PENDSTSET R/W 0
SysTick Clear Pending
Value Description
0 On a write, no effect.
On a write, removes the pending state from the SysTick
exception.
1
This bit is write only; on a register read, its value is unknown.
25 PENDSTCLR WO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
24 reserved RO 0
Debug Interrupt Handling
Value Description
0 The release from halt does not take an interrupt.
1 The release from halt takes an interrupt.
This bit is only meaningful in Debug mode and reads as zero when the
processor is not in Debug mode.
23 ISRPRE RO 0
Interrupt Pending
Value Description
0 No interrupt is pending.
1 An interrupt is pending.
This bit provides status for all interrupts excluding NMI and Faults.
22 ISRPEND RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
21:18 reserved RO 0x0
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Bit/Field Name Type Reset Description
Interrupt Pending Vector Number
This field contains the exception number of the highest priority pending
enabled exception. The value indicated by this field includes the effect
of the BASEPRI and FAULTMASK registers, but not any effect of the
PRIMASK register.
Value Description
0x00 No exceptions are pending
0x01 Reserved
0x02 NMI
0x03 Hard fault
0x04 Memory management fault
0x05 Bus fault
0x06 Usage fault
0x07-0x0A Reserved
0x0B SVCall
0x0C Reserved for Debug
0x0D Reserved
0x0E PendSV
0x0F SysTick
0x10 Interrupt Vector 0
0x11 Interrupt Vector 1
... ...
0x3B Interrupt Vector 43
0x3C-0x3F Reserved
17:12 VECPEND RO 0x00
Return to Base
Value Description
0 There are preempted active exceptions to execute.
There are no active exceptions, or the currently executing
exception is the only active exception.
1
This bit provides status for all interrupts excluding NMI and Faults. This
bit only has meaning if the processor is currently executing an ISR (the
Interrupt Program Status (IPSR) register is non-zero).
11 RETBASE RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10:6 reserved RO 0x0
Interrupt Pending Vector Number
This field contains the active exception number. The exception numbers
can be found in the description for the VECPEND field. If this field is clear,
the processor is in Thread mode. This field contains the same value as
the ISRNUM field in the IPSR register.
Subtract 16 from this value to obtain the IRQ number required to index
into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn),
Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn),
and Interrupt Priority (PRIn) registers (see page 63).
5:0 VECACT RO 0x00
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Register 28: Vector Table Offset (VTABLE), offset 0xD08
Note: This register can only be accessed from privileged mode.
The VTABLE register indicates the offset of the vector table base address from memory address
0x0000.0000.
Vector Table Offset (VTABLE)
Base 0xE000.E000
Offset 0xD08
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved BASE OFFSET
Type RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET reserved
Type R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:30 reserved RO 0x0
Vector Table Base
Value Description
0 The vector table is in the code memory region.
1 The vector table is in the SRAM memory region.
29 BASE R/W 0
Vector Table Offset
When configuring the OFFSET field, the offset must be aligned to the
number of exception entries in the vector table. Because there are 43
interrupts, the minimum alignment is 64 words.
28:8 OFFSET R/W 0x000.00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0 reserved RO 0x00
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Register 29: Application Interrupt and Reset Control (APINT), offset 0xD0C
Note: This register can only be accessed from privileged mode.
The APINT register provides priority grouping control for the exception model, endian status for
data accesses, and reset control of the system. To write to this register, 0x05FA must be written to
the VECTKEY field, otherwise the write is ignored.
The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the
Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. Table
3-8 on page 127 shows how the PRIGROUP value controls this split. The bit numbers in the Group
Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the
INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29.
Note: Determining preemption of an exception uses only the group priority field.
Table 3-8. Interrupt Priority Levels
Group Subpriorities
Priorities
PRIGROUP Bit Field Binary Pointa Group Priority Field Subpriority Field
0x0 - 0x4 bxxx. [7:5] None 8 1
0x5 bxx.y [7:6] [5] 4 2
0x6 bx.yy [7] [6:5] 2 4
0x7 b.yyy None [7:5] 1 8
a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit.
Application Interrupt and Reset Control (APINT)
Base 0xE000.E000
Offset 0xD0C
Type R/W, reset 0xFA05.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VECTKEY
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDIANESS reserved PRIGROUP reserved SYSRESREQVECTCLRACT VECTRESET
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Register Key
This field is used to guard against accidental writes to this register.
0x05FA must be written to this field in order to change the bits in this
register. On a read, 0xFA05 is returned.
31:16 VECTKEY R/W 0xFA05
Data Endianess
The Stellaris implementation uses only little-endian mode so this is
cleared to 0.
15 ENDIANESS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14:11 reserved RO 0x0
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Bit/Field Name Type Reset Description
Interrupt Priority Grouping
This field determines the split of group priority from subpriority (see
Table 3-8 on page 127 for more information).
10:8 PRIGROUP R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:3 reserved RO 0x0
System Reset Request
Value Description
0 No effect.
Resets the core and all on-chip peripherals except the Debug
interface.
1
This bit is automatically cleared during the reset of the core and reads
as 0.
2 SYSRESREQ WO 0
Clear Active NMI / Fault
This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
1 VECTCLRACT WO 0
System Reset
This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
0 VECTRESET WO 0
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Register 30: System Control (SYSCTRL), offset 0xD10
Note: This register can only be accessed from privileged mode.
The SYSCTRL register controls features of entry to and exit from low-power state.
System Control (SYSCTRL)
Base 0xE000.E000
Offset 0xD10
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SEVONPEND reserved SLEEPDEEP SLEEPEXIT reserved
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO R/W R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 reserved RO 0x0000.00
Wake Up on Pending
Value Description
Only enabled interrupts or events can wake up the processor;
disabled interrupts are excluded.
0
Enabled events and all interrupts, including disabled interrupts,
can wake up the processor.
1
When an event or interrupt enters the pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting for an
event, the event is registered and affects the next WFE.
The processor also wakes up on execution of a SEV instruction or an
external event.
4 SEVONPEND R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
Deep Sleep Enable
Value Description
0 Use Sleep mode as the low power mode.
1 Use Deep-sleep mode as the low power mode.
2 SLEEPDEEP R/W 0
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Bit/Field Name Type Reset Description
Sleep on ISR Exit
Value Description
When returning from Handler mode to Thread mode, do not
sleep when returning to Thread mode.
0
When returning from Handler mode to Thread mode, enter sleep
or deep sleep on return from an ISR.
1
Setting this bit enables an interrupt-driven application to avoid returning
to an empty main application.
1 SLEEPEXIT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 31: Configuration and Control (CFGCTRL), offset 0xD14
Note: This register can only be accessed from privileged mode.
The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault
and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero
and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 121).
Configuration and Control (CFGCTRL)
Base 0xE000.E000
Offset 0xD14
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved STKALIGN BFHFNMIGN reserved DIV0 UNALIGNED reserved MAINPEND BASETHR
Type RO RO RO RO RO RO R/W R/W RO RO RO R/W R/W RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0x0000.00
Stack Alignment on Exception Entry
Value Description
0 The stack is 4-byte aligned.
1 The stack is 8-byte aligned.
On exception entry, the processor uses bit 9 of the stacked PSR to
indicate the stack alignment. On return from the exception, it uses this
stacked bit to restore the correct stack alignment.
9 STKALIGN R/W 0
Ignore Bus Fault in NMI and Fault
This bit enables handlers with priority -1 or -2 to ignore data bus faults
caused by load and store instructions. The setting of this bit applies to
the hard fault, NMI, and FAULTMASK escalated handlers.
Value Description
Data bus faults caused by load and store instructions cause a
lock-up.
0
Handlers running at priority -1 and -2 ignore data bus faults
caused by load and store instructions.
1
Set this bit only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect control path problems and fix them.
8 BFHFNMIGN R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5 reserved RO 0x0
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Bit/Field Name Type Reset Description
Trap on Divide by 0
This bit enables faulting or halting when the processor executes an
SDIV or UDIV instruction with a divisor of 0.
Value Description
Do not trap on divide by 0. A divide by zero returns a quotient
of 0.
0
1 Trap on divide by 0.
4 DIV0 R/W 0
Trap on Unaligned Access
Value Description
0 Do not trap on unaligned halfword and word accesses.
Trap on unaligned halfword and word accesses. An unaligned
access generates a usage fault.
1
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of whether UNALIGNED is set.
3 UNALIGNED R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2 reserved RO 0
Allow Main Interrupt Trigger
Value Description
0 Disables unprivileged software access to the SWTRIG register.
Enables unprivileged software access to the SWTRIG register
(see page 121).
1
1 MAINPEND R/W 0
Thread State Control
Value Description
The processor can enter Thread mode only when no exception
is active.
0
The processor can enter Thread mode from any level under the
control of an EXC_RETURN value (see “Exception
Return” on page 87 for more information).
1
0 BASETHR R/W 0
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Register 32: System Handler Priority 1 (SYSPRI1), offset 0xD18
Note: This register can only be accessed from privileged mode.
The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory
management fault exception handlers. This register is byte-accessible.
System Handler Priority 1 (SYSPRI1)
Base 0xE000.E000
Offset 0xD18
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved USAGE reserved
Type RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUS reserved MEM reserved
Type R/W R/W R/W RO RO RO RO RO R/W R/W R/W RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:24 reserved RO 0x00
Usage Fault Priority
This field configures the priority level of the usage fault. Configurable
priority values are in the range 0-7, with lower values having higher
priority.
23:21 USAGE R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20:16 reserved RO 0x0
Bus Fault Priority
This field configures the priority level of the bus fault. Configurable priority
values are in the range 0-7, with lower values having higher priority.
15:13 BUS R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12:8 reserved RO 0x0
Memory Management Fault Priority
This field configures the priority level of the memory management fault.
Configurable priority values are in the range 0-7, with lower values
having higher priority.
7:5 MEM R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4:0 reserved RO 0x0
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Register 33: System Handler Priority 2 (SYSPRI2), offset 0xD1C
Note: This register can only be accessed from privileged mode.
The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is
byte-accessible.
System Handler Priority 2 (SYSPRI2)
Base 0xE000.E000
Offset 0xD1C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SVC reserved
Type R/W R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
SVCall Priority
This field configures the priority level of SVCall. Configurable priority
values are in the range 0-7, with lower values having higher priority.
31:29 SVC R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28:0 reserved RO 0x000.0000
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Register 34: System Handler Priority 3 (SYSPRI3), offset 0xD20
Note: This register can only be accessed from privileged mode.
The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV
handlers. This register is byte-accessible.
System Handler Priority 3 (SYSPRI3)
Base 0xE000.E000
Offset 0xD20
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TICK reserved PENDSV reserved
Type R/W R/W R/W RO RO RO RO RO R/W R/W R/W RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DEBUG reserved
Type RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
SysTick Exception Priority
This field configures the priority level of the SysTick exception.
Configurable priority values are in the range 0-7, with lower values
having higher priority.
31:29 TICK R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28:24 reserved RO 0x0
PendSV Priority
This field configures the priority level of PendSV. Configurable priority
values are in the range 0-7, with lower values having higher priority.
23:21 PENDSV R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20:8 reserved RO 0x000
Debug Priority
This field configures the priority level of Debug. Configurable priority
values are in the range 0-7, with lower values having higher priority.
7:5 DEBUG R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4:0 reserved RO 0x0.0000
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Register 35: System Handler Control and State (SYSHNDCTRL), offset 0xD24
Note: This register can only be accessed from privileged mode.
The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the
usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status
of the system handlers.
If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as
a hard fault.
This register can be modified to change the pending or active status of system exceptions. An OS
kernel can write to the active bits to perform a context switch that changes the current exception
type.
Caution – Software that changes the value of an active bit in this register without correct adjustment
to the stacked content can cause the processor to generate a fault exception. Ensure software that writes
to this register retains and subsequently restores the current active status.
If the value of a bit in this register must be modified after enabling the system handlers, a
read-modify-write procedure must be used to ensure that only the required bit is modified.
System Handler Control and State (SYSHNDCTRL)
Base 0xE000.E000
Offset 0xD24
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved USAGE BUS MEM
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SVC BUSP MEMP USAGEP TICK PNDSV reserved MON SVCA reserved USGA reserved BUSA MEMA
Type R/W R/W R/W R/W R/W R/W RO R/W R/W RO RO RO R/W RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:19 reserved RO 0x000
Usage Fault Enable
Value Description
0 Disables the usage fault exception.
1 Enables the usage fault exception.
18 USAGE R/W 0
Bus Fault Enable
Value Description
0 Disables the bus fault exception.
1 Enables the bus fault exception.
17 BUS R/W 0
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Bit/Field Name Type Reset Description
Memory Management Fault Enable
Value Description
0 Disables the memory management fault exception.
1 Enables the memory management fault exception.
16 MEM R/W 0
SVC Call Pending
Value Description
0 An SVC call exception is not pending.
1 An SVC call exception is pending.
This bit can be modified to change the pending status of the SVC call
exception.
15 SVC R/W 0
Bus Fault Pending
Value Description
0 A bus fault exception is not pending.
1 A bus fault exception is pending.
This bit can be modified to change the pending status of the bus fault
exception.
14 BUSP R/W 0
Memory Management Fault Pending
Value Description
0 A memory management fault exception is not pending.
1 A memory management fault exception is pending.
This bit can be modified to change the pending status of the memory
management fault exception.
13 MEMP R/W 0
Usage Fault Pending
Value Description
0 A usage fault exception is not pending.
1 A usage fault exception is pending.
This bit can be modified to change the pending status of the usage fault
exception.
12 USAGEP R/W 0
SysTick Exception Active
Value Description
0 A SysTick exception is not active.
1 A SysTick exception is active.
This bit can be modified to change the active status of the SysTick
exception, however, see the Caution above before setting this bit.
11 TICK R/W 0
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Bit/Field Name Type Reset Description
PendSV Exception Active
Value Description
0 A PendSV exception is not active.
1 A PendSV exception is active.
This bit can be modified to change the active status of the PendSV
exception, however, see the Caution above before setting this bit.
10 PNDSV R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9 reserved RO 0
Debug Monitor Active
Value Description
0 The Debug monitor is not active.
1 The Debug monitor is active.
8 MON R/W 0
SVC Call Active
Value Description
0 SVC call is not active.
1 SVC call is active.
This bit can be modified to change the active status of the SVC call
exception, however, see the Caution above before setting this bit.
7 SVCA R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:4 reserved RO 0x0
Usage Fault Active
Value Description
0 Usage fault is not active.
1 Usage fault is active.
This bit can be modified to change the active status of the usage fault
exception, however, see the Caution above before setting this bit.
3 USGA R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2 reserved RO 0
Bus Fault Active
Value Description
0 Bus fault is not active.
1 Bus fault is active.
This bit can be modified to change the active status of the bus fault
exception, however, see the Caution above before setting this bit.
1 BUSA R/W 0
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Bit/Field Name Type Reset Description
Memory Management Fault Active
Value Description
0 Memory management fault is not active.
1 Memory management fault is active.
This bit can be modified to change the active status of the memory
management fault exception, however, see the Caution above before
setting this bit.
0 MEMA R/W 0
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Register 36: Configurable Fault Status (FAULTSTAT), offset 0xD28
Note: This register can only be accessed from privileged mode.
The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage
fault. Each of these functions is assigned to a subregister as follows:
■ Usage Fault Status (UFAULTSTAT), bits 31:16
■ Bus Fault Status (BFAULTSTAT), bits 15:8
■ Memory Management Fault Status (MFAULTSTAT), bits 7:0
FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows:
■ The complete FAULTSTAT register, with a word access to offset 0xD28
■ The MFAULTSTAT, with a byte access to offset 0xD28
■ The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28
■ The BFAULTSTAT, with a byte access to offset 0xD29
■ The UFAULTSTAT, with a halfword access to offset 0xD2A
Bits are cleared by writing a 1 to them.
In a fault handler, the true faulting address can be determined by:
1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address
(FAULTADDR) value.
2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the
MMADDR or FAULTADDR contents are valid.
Software must follow this sequence because another higher priority exception might change the
MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current
fault handler, the other fault might change the MMADDR or FAULTADDR value.
Configurable Fault Status (FAULTSTAT)
Base 0xE000.E000
Offset 0xD28
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved DIV0 UNALIGN reserved NOCP INVPC INVSTAT UNDEF
Type RO RO RO RO RO RO R/W1C R/W1C RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFARV reserved BSTKE BUSTKE IMPRE PRECISE IBUS MMARV reserved MSTKE MUSTKE reserved DERR IERR
Type R/W1C RO RO R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C RO RO R/W1C R/W1C RO R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:26 reserved RO 0x00
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Bit/Field Name Type Reset Description
Divide-by-Zero Usage Fault
Value Description
No divide-by-zero fault has occurred, or divide-by-zero trapping
is not enabled.
0
The processor has executed an SDIV or UDIV instruction with
a divisor of 0.
1
When this bit is set, the PC value stacked for the exception return points
to the instruction that performed the divide by zero.
Trapping on divide-by-zero is enabled by setting the DIV0 bit in the
Configuration and Control (CFGCTRL) register (see page 131).
This bit is cleared by writing a 1 to it.
25 DIV0 R/W1C 0
Unaligned Access Usage Fault
Value Description
No unaligned access fault has occurred, or unaligned access
trapping is not enabled.
0
1 The processor has made an unaligned memory access.
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of the configuration of this bit.
Trapping on unaligned access is enabled by setting the UNALIGNED bit
in the CFGCTRL register (see page 131).
This bit is cleared by writing a 1 to it.
24 UNALIGN R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:20 reserved RO 0x00
No Coprocessor Usage Fault
Value Description
A usage fault has not been caused by attempting to access a
coprocessor.
0
1 The processor has attempted to access a coprocessor.
This bit is cleared by writing a 1 to it.
19 NOCP R/W1C 0
Invalid PC Load Usage Fault
Value Description
A usage fault has not been caused by attempting to load an
invalid PC value.
0
The processor has attempted an illegal load of EXC_RETURN
to the PC as a result of an invalid context or an invalid
EXC_RETURN value.
1
When this bit is set, the PC value stacked for the exception return points
to the instruction that tried to perform the illegal load of the PC.
This bit is cleared by writing a 1 to it.
18 INVPC R/W1C 0
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Bit/Field Name Type Reset Description
Invalid State Usage Fault
Value Description
0 A usage fault has not been caused by an invalid state.
The processor has attempted to execute an instruction that
makes illegal use of the EPSR register.
1
When this bit is set, the PC value stacked for the exception return points
to the instruction that attempted the illegal use of the Execution
Program Status Register (EPSR) register.
This bit is not set if an undefined instruction uses the EPSR register.
This bit is cleared by writing a 1 to it.
17 INVSTAT R/W1C 0
Undefined Instruction Usage Fault
Value Description
0 A usage fault has not been caused by an undefined instruction.
The processor has attempted to execute an undefined
instruction.
1
When this bit is set, the PC value stacked for the exception return points
to the undefined instruction.
An undefined instruction is an instruction that the processor cannot
decode.
This bit is cleared by writing a 1 to it.
16 UNDEF R/W1C 0
Bus Fault Address Register Valid
Value Description
The value in the Bus Fault Address (FAULTADDR) register
is not a valid fault address.
0
1 The FAULTADDR register is holding a valid fault address.
This bit is set after a bus fault, where the address is known. Other faults
can clear this bit, such as a memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority,
the hard fault handler must clear this bit. This action prevents problems
if returning to a stacked active bus fault handler whose FAULTADDR
register value has been overwritten.
This bit is cleared by writing a 1 to it.
15 BFARV R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14:13 reserved RO 0
Stack Bus Fault
Value Description
0 No bus fault has occurred on stacking for exception entry.
Stacking for an exception entry has caused one or more bus
faults.
1
When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the FAULTADDR register.
This bit is cleared by writing a 1 to it.
12 BSTKE R/W1C 0
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Bit/Field Name Type Reset Description
Unstack Bus Fault
Value Description
No bus fault has occurred on unstacking for a return from
exception.
0
Unstacking for a return from exception has caused one or more
bus faults.
1
This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted from the failing return,
a new save is not performed, and a fault address is not written to the
FAULTADDR register.
This bit is cleared by writing a 1 to it.
11 BUSTKE R/W1C 0
Imprecise Data Bus Error
Value Description
0 An imprecise data bus error has not occurred.
A data bus error has occurred, but the return address in the
stack frame is not related to the instruction that caused the error.
1
When this bit is set, a fault address is not written to the FAULTADDR
register.
This fault is asynchronous. Therefore, if the fault is detected when the
priority of the current process is higher than the bus fault priority, the
bus fault becomes pending and becomes active only when the processor
returns from all higher-priority processes. If a precise fault occurs before
the processor enters the handler for the imprecise bus fault, the handler
detects that both the IMPRE bit is set and one of the precise fault status
bits is set.
This bit is cleared by writing a 1 to it.
10 IMPRE R/W1C 0
Precise Data Bus Error
Value Description
0 A precise data bus error has not occurred.
A data bus error has occurred, and the PC value stacked for
the exception return points to the instruction that caused the
fault.
1
When this bit is set, the fault address is written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.
9 PRECISE R/W1C 0
Instruction Bus Error
Value Description
0 An instruction bus error has not occurred.
1 An instruction bus error has occurred.
The processor detects the instruction bus error on prefetching an
instruction, but sets this bit only if it attempts to issue the faulting
instruction.
When this bit is set, a fault address is not written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.
8 IBUS R/W1C 0
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Bit/Field Name Type Reset Description
Memory Management Fault Address Register Valid
Value Description
The value in the Memory Management Fault Address
(MMADDR) register is not a valid fault address.
0
1 The MMADDR register is holding a valid fault address.
If a memory management fault occurs and is escalated to a hard fault
because of priority, the hard fault handler must clear this bit. This action
prevents problems if returning to a stacked active memory management
fault handler whose MMADDR register value has been overwritten.
This bit is cleared by writing a 1 to it.
7 MMARV R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:5 reserved RO 0
Stack Access Violation
Value Description
No memory management fault has occurred on stacking for
exception entry.
0
Stacking for an exception entry has caused one or more access
violations.
1
When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the MMADDR register.
This bit is cleared by writing a 1 to it.
4 MSTKE R/W1C 0
Unstack Access Violation
Value Description
No memory management fault has occurred on unstacking for
a return from exception.
0
Unstacking for a return from exception has caused one or more
access violations.
1
This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted from the failing return,
a new save is not performed, and a fault address is not written to the
MMADDR register.
This bit is cleared by writing a 1 to it.
3 MUSTKE R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2 reserved RO 0
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Bit/Field Name Type Reset Description
Data Access Violation
Value Description
0 A data access violation has not occurred.
The processor attempted a load or store at a location that does
not permit the operation.
1
When this bit is set, the PC value stacked for the exception return points
to the faulting instruction and the address of the attempted access is
written to the MMADDR register.
This bit is cleared by writing a 1 to it.
1 DERR R/W1C 0
Instruction Access Violation
Value Description
0 An instruction access violation has not occurred.
The processor attempted an instruction fetch from a location
that does not permit execution.
1
This fault occurs on any access to an XN region, even when the MPU
is disabled or not present.
When this bit is set, the PC value stacked for the exception return points
to the faulting instruction and the address of the attempted access is
not written to the MMADDR register.
This bit is cleared by writing a 1 to it.
0 IERR R/W1C 0
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Register 37: Hard Fault Status (HFAULTSTAT), offset 0xD2C
Note: This register can only be accessed from privileged mode.
The HFAULTSTAT register gives information about events that activate the hard fault handler.
Bits are cleared by writing a 1 to them.
Hard Fault Status (HFAULTSTAT)
Base 0xE000.E000
Offset 0xD2C
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG FORCED reserved
Type R/W1C R/W1C RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved VECT reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Debug Event
This bit is reserved for Debug use. This bit must be written as a 0,
otherwise behavior is unpredictable.
31 DBG R/W1C 0
Forced Hard Fault
Value Description
0 No forced hard fault has occurred.
A forced hard fault has been generated by escalation of a fault
with configurable priority that cannot be handled, either because
of priority or because it is disabled.
1
When this bit is set, the hard fault handler must read the other fault
status registers to find the cause of the fault.
This bit is cleared by writing a 1 to it.
30 FORCED R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29:2 reserved RO 0x00
Vector Table Read Fault
Value Description
0 No bus fault has occurred on a vector table read.
1 A bus fault occurred on a vector table read.
This error is always handled by the hard fault handler.
When this bit is set, the PC value stacked for the exception return points
to the instruction that was preempted by the exception.
This bit is cleared by writing a 1 to it.
1 VECT R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 38: Memory Management Fault Address (MMADDR), offset 0xD34
Note: This register can only be accessed from privileged mode.
The MMADDR register contains the address of the location that generated a memory management
fault. When an unaligned access faults, the address in the MMADDR register is the actual address
that faulted. Because a single read or write instruction can be split into multiple aligned accesses,
the fault address can be any address in the range of the requested access size. Bits in the Memory
Management Fault Status (MFAULTSTAT) register indicate the cause of the fault and whether
the value in the MMADDR register is valid (see page 140).
Memory Management Fault Address (MMADDR)
Base 0xE000.E000
Offset 0xD34
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Fault Address
When the MMARV bit of MFAULTSTAT is set, this field holds the address
of the location that generated the memory management fault.
31:0 ADDR R/W -
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Register 39: Bus Fault Address (FAULTADDR), offset 0xD38
Note: This register can only be accessed from privileged mode.
The FAULTADDR register contains the address of the location that generated a bus fault. When
an unaligned access faults, the address in the FAULTADDR register is the one requested by the
instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT)
register indicate the cause of the fault and whether the value in the FAULTADDR register is valid
(see page 140).
Bus Fault Address (FAULTADDR)
Base 0xE000.E000
Offset 0xD38
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Fault Address
When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the
address of the location that generated the bus fault.
31:0 ADDR R/W -
3.6 Memory Protection Unit (MPU) Register Descriptions
This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by
address offset.
The MPU registers can only be accessed from privileged mode.
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Register 40: MPU Type (MPUTYPE), offset 0xD90
Note: This register can only be accessed from privileged mode.
The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it
supports.
MPU Type (MPUTYPE)
Base 0xE000.E000
Offset 0xD90
Type RO, reset 0x0000.0800
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved IREGION
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DREGION reserved SEPARATE
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:24 reserved RO 0x00
Number of I Regions
This field indicates the number of supported MPU instruction regions.
This field always contains 0x00. The MPU memory map is unified and
is described by the DREGION field.
23:16 IREGION RO 0x00
Number of D Regions
Value Description
0x08 Indicates there are eight supported MPU data regions.
15:8 DREGION RO 0x08
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:1 reserved RO 0x00
Separate or Unified MPU
Value Description
0 Indicates the MPU is unified.
0 SEPARATE RO 0
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Register 41: MPU Control (MPUCTRL), offset 0xD94
Note: This register can only be accessed from privileged mode.
The MPUCTRL register enables the MPU, enables the default memory map background region,
and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask
Register (FAULTMASK) escalated handlers.
When the ENABLE and PRIVDEFEN bits are both set:
■ For privileged accesses, the default memory map is as described in “Memory Model” on page 71.
Any access by privileged software that does not address an enabled memory region behaves
as defined by the default memory map.
■ Any access by unprivileged software that does not address an enabled memory region causes
a memory management fault.
Execute Never (XN) and Strongly Ordered rules always apply to the System Control Space regardless
of the value of the ENABLE bit.
When the ENABLE bit is set, at least one region of the memory map must be enabled for the system
to function unless the PRIVDEFEN bit is set. If the PRIVDEFEN bit is set and no regions are enabled,
then only privileged software can operate.
When the ENABLE bit is clear, the system uses the default memory map, which has the same
memory attributes as if the MPU is not implemented (see Table 2-5 on page 74 for more information).
The default memory map applies to accesses from both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are always
permitted. Other areas are accessible based on regions and whether PRIVDEFEN is set.
Unless HFNMIENA is set, the MPU is not enabled when the processor is executing the handler for
an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or
NMI exception or when FAULTMASK is enabled. Setting the HFNMIENA bit enables the MPU when
operating with these two priorities.
MPU Control (MPUCTRL)
Base 0xE000.E000
Offset 0xD94
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PRIVDEFEN HFNMIENA ENABLE
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x0000.000
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Bit/Field Name Type Reset Description
MPU Default Region
This bit enables privileged software access to the default memory map.
Value Description
If the MPU is enabled, this bit disables use of the default memory
map. Any memory access to a location not covered by any
enabled region causes a fault.
0
If the MPU is enabled, this bit enables use of the default memory
map as a background region for privileged software accesses.
1
When this bit is set, the background region acts as if it is region number
-1. Any region that is defined and enabled has priority over this default
map.
If the MPU is disabled, the processor ignores this bit.
2 PRIVDEFEN R/W 0
MPU Enabled During Faults
This bit controls the operation of the MPU during hard fault, NMI, and
FAULTMASK handlers.
Value Description
The MPU is disabled during hard fault, NMI, and FAULTMASK
handlers, regardless of the value of the ENABLE bit.
0
The MPU is enabled during hard fault, NMI, and FAULTMASK
handlers.
1
When the MPU is disabled and this bit is set, the resulting behavior is
unpredictable.
1 HFNMIENA R/W 0
MPU Enable
Value Description
0 The MPU is disabled.
1 The MPU is enabled.
When the MPU is disabled and the HFNMIENA bit is set, the resulting
behavior is unpredictable.
0 ENABLE R/W 0
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Register 42: MPU Region Number (MPUNUMBER), offset 0xD98
Note: This register can only be accessed from privileged mode.
The MPUNUMBER register selects which memory region is referenced by the MPU Region Base
Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers. Normally, the
required region number should be written to this register before accessing the MPUBASE or the
MPUATTR register. However, the region number can be changed by writing to the MPUBASE
register with the VALID bit set (see page 153). This write updates the value of the REGION field.
MPU Region Number (MPUNUMBER)
Base 0xE000.E000
Offset 0xD98
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved NUMBER
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x0000.000
MPU Region to Access
This field indicates the MPU region referenced by the MPUBASE and
MPUATTR registers. The MPU supports eight memory regions.
2:0 NUMBER R/W 0x0
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Register 43: MPU Region Base Address (MPUBASE), offset 0xD9C
Register 44: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4
Register 45: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC
Register 46: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4
Note: This register can only be accessed from privileged mode.
The MPUBASE register defines the base address of the MPU region selected by the MPU Region
Number (MPUNUMBER) register and can update the value of the MPUNUMBER register. To
change the current region number and update the MPUNUMBER register, write the MPUBASE
register with the VALID bit set.
The ADDR field is bits 31:N of the MPUBASE register. Bits (N-1):5 are reserved. The region size,
as specified by the SIZE field in the MPU Region Attribute and Size (MPUATTR) register, defines
the value of N where:
N = Log2(Region size in bytes)
If the region size is configured to 4 GB in the MPUATTR register, there is no valid ADDR field. In
this case, the region occupies the complete memory map, and the base address is 0x0000.0000.
The base address is aligned to the size of the region. For example, a 64-KB region must be aligned
on a multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000.
MPU Region Base Address (MPUBASE)
Base 0xE000.E000
Offset 0xD9C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR VALID reserved REGION
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W WO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Base Address Mask
Bits 31:N in this field contain the region base address. The value of N
depends on the region size, as shown above. The remaining bits (N-1):5
are reserved.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 ADDR R/W 0x0000.000
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Bit/Field Name Type Reset Description
Region Number Valid
Value Description
The MPUNUMBER register is not changed and the processor
updates the base address for the region specified in the
MPUNUMBER register and ignores the value of the REGION
field.
0
The MPUNUMBER register is updated with the value of the
REGION field and the base address is updated for the region
specified in the REGION field.
1
This bit is always read as 0.
4 VALID WO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
Region Number
On a write, contains the value to be written to the MPUNUMBER register.
On a read, returns the current region number in the MPUNUMBER
register.
2:0 REGION R/W 0x0
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Register 47: MPU Region Attribute and Size (MPUATTR), offset 0xDA0
Register 48: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8
Register 49: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0
Register 50: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8
Note: This register can only be accessed from privileged mode.
The MPUATTR register defines the region size and memory attributes of the MPU region specified
by the MPU Region Number (MPUNUMBER) register and enables that region and any subregions.
The MPUATTR register is accessible using word or halfword accesses with the most-significant
halfword holding the region attributes and the least-significant halfword holds the region size and
the region and subregion enable bits.
The MPU access permission attribute bits, XN, AP, TEX, S, C, and B, control access to the
corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register
as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32 bytes, corresponding to a SIZE value of 4. Table
3-9 on page 155 gives example SIZE values with the corresponding region size and value of N in
the MPU Region Base Address (MPUBASE) register.
Table 3-9. Example SIZE Field Values
SIZE Encoding Region Size Value of Na Note
00100b (0x4) 32 B 5 Minimum permitted size
01001b (0x9) 1 KB 10 -
10011b (0x13) 1 MB 20 -
11101b (0x1D) 1 GB 30 -
No valid ADDR field inMPUBASE; the Maximum possible size
region occupies the complete
memory map.
11111b (0x1F) 4 GB
a. Refers to the N parameter in the MPUBASE register (see page 153).
MPU Region Attribute and Size (MPUATTR)
Base 0xE000.E000
Offset 0xDA0
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved XN reserved AP reserved TEX S C B
Type RO RO RO R/W RO R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRD reserved SIZE ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:29 reserved RO 0x00
Instruction Access Disable
Value Description
0 Instruction fetches are enabled.
1 Instruction fetches are disabled.
28 XN R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27 reserved RO 0
Access Privilege
For information on using this bit field, see Table 3-5 on page 101.
26:24 AP R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:22 reserved RO 0x0
Type Extension Mask
For information on using this bit field, see Table 3-3 on page 100.
21:19 TEX R/W 0x0
Shareable
For information on using this bit, see Table 3-3 on page 100.
18 S R/W 0
Cacheable
For information on using this bit, see Table 3-3 on page 100.
17 C R/W 0
Bufferable
For information on using this bit, see Table 3-3 on page 100.
16 B R/W 0
Subregion Disable Bits
Value Description
0 The corresponding subregion is enabled.
1 The corresponding subregion is disabled.
Region sizes of 128 bytes and less do not support subregions. When
writing the attributes for such a region, configure the SRD field as 0x00.
See the section called “Subregions” on page 99 for more information.
15:8 SRD R/W 0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0x0
Region Size Mask
The SIZE field defines the size of the MPU memory region specified by
the MPUNUMBER register. Refer to Table 3-9 on page 155 for more
information.
5:1 SIZE R/W 0x0
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Bit/Field Name Type Reset Description
Region Enable
Value Description
0 The region is disabled.
1 The region is enabled.
0 ENABLE R/W 0
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4 JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially
into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent
on the current state of the TAP controller. For detailed information on the operation of the JTAG
port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
The Stellaris® JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core.
This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO
outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive
programming for the ARM, Stellaris, and unimplemented JTAG instructions.
The Stellaris JTAG module has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM
JTAG controller.
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4.1 Block Diagram
Figure 4-1. JTAG Module Block Diagram
Instruction Register (IR)
TAP Controller
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TCK
TMS
TDI
TDO
Cortex-M3
Debug
Port
TRST
4.2 Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 159. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and
TMS inputs. The current state of the TAP controller depends on the current value of TRST and the
sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when
the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel
load registers. The current state of the TAP controller also determines whether the Instruction
Register (IR) chain or one of the Data Register (DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 4-2 on page 165 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 684 for JTAG timing diagrams.
4.2.1 JTAG Interface Pins
The JTAG interface consists of five standard pins: TRST,TCK, TMS, TDI, and TDO. These pins and
their associated reset state are given in Table 4-1 on page 160. Detailed information on each pin
follows.
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Table 4-1. JTAG Port Pins Reset State
Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value
TRST Input Enabled Disabled N/A N/A
TCK Input Enabled Disabled N/A N/A
TMS Input Enabled Disabled N/A N/A
TDI Input Enabled Disabled N/A N/A
TDO Output Enabled Disabled 2-mA driver High-Z
4.2.1.1 Test Reset Input (TRST)
The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP
controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the
Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters
the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction,
IDCODE.
By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled
on PB7/TRST; otherwise JTAG communication could be lost.
4.2.1.2 Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers
that are daisy-chained together can synchronously communicate serial test data between
components. During normal operation, TCK is driven by a free-running clock with a nominal 50%
duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK
is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction
and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no
clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down
resistors can be turned off to save internal power as long as the TCK pin is constantly being driven
by an external source.
4.2.1.3 Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered.
Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the
value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can
be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine
can be seen in its entirety in Figure 4-2 on page 162.
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost.
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4.2.1.4 Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on
the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling
edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost.
4.2.1.5 Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the
pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states.
4.2.2 JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 4-2 on page 162. The TAP controller
state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR)
or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module
to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed
information on the function of the TAP controller and the operations that occur in each state, please
refer to IEEE Standard 1149.1.
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Figure 4-2. Test Access Port State Machine
Test Logic Reset
Run Test Idle Select DR Scan Select IR Scan
Capture DR Capture IR
Shift DR Shift IR
Exit 1 DR Exit 1 IR
Exit 2 DR Exit 2 IR
Pause DR Pause IR
Update DR Update IR
1 1 1
1 1
1
1 1
1 1
1 1
1 1
1 0 1 0
0 0
0 0
0 0
0 0
0 0
0 0
0
0
4.2.3 Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 165.
4.2.4 Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG pins
can be programmed to be GPIOs, board configuration and reset conditions on these pins must be
considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the
method for switching between these two operational modes is described below.
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4.2.4.1 GPIO Functionality
When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting
GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate
hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and
PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging
or board-level testing, this provides five more GPIOs for use in the design.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins
to their GPIO functionality, the debugger may not have enough time to connect and halt the controller
before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be
avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and
PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register
(see page 299) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see
page 309) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see
page 310) have been set to 1.
Recovering a "Locked" Device
Note: The mass erase of the flash memory caused by the below sequence erases the entire flash
memory, regardless of the settings in the Flash Memory Protection Program Enable n
(FMPPEn) registers. Performing the sequence below does not affect the nonvolatile registers
discussed in “Nonvolatile Register Programming” on page 259.
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug sequence that can be used to recover the device. Performing
a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset
mass erases the flash memory. The sequence to recover the device is:
1. Assert and hold the RST signal.
2. Perform the JTAG-to-SWD switch sequence.
3. Perform the SWD-to-JTAG switch sequence.
4. Perform the JTAG-to-SWD switch sequence.
5. Perform the SWD-to-JTAG switch sequence.
6. Perform the JTAG-to-SWD switch sequence.
7. Perform the SWD-to-JTAG switch sequence.
8. Perform the JTAG-to-SWD switch sequence.
9. Perform the SWD-to-JTAG switch sequence.
10. Perform the JTAG-to-SWD switch sequence.
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11. Perform the SWD-to-JTAG switch sequence.
12. Release the RST signal.
13. Wait 400 ms.
14. Power-cycle the device.
The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug
(SWD)” on page 164. When performing switch sequences for the purpose of recovering the debug
capabilities of the device, only steps 1 and 2 of the switch sequence in the section called
“JTAG-to-SWD Switching” on page 164 must be performed.
4.2.4.2 Communication with JTAG/SWD
Because the debug clock and the system clock can be running at different frequencies, care must
be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state,
the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software
should check the ACK response to see if the previous operation has completed before initiating a
new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock
(TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have
to be checked.
4.2.4.3 ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the
TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller
through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic
Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run
Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states.
Stepping through this sequences of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Debug Interface V5 Architecture Specification.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
probability of this sequence occurring during normal operation of the TAP controller, it should not
affect normal performance of the JTAG interface.
JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send the switching preamble to the device. The 16-bit switch sequence
for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
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2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in SWD mode, before sending the switch sequence, the SWD goes into the line reset
state.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to JTAG mode is defined as b1110011100111100, transmitted LSB first. This can also
be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C.
3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic
Reset state.
4.3 Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. This is done by enabling the five JTAG
pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to
enabling the alternate functions, any other changes to the GPIO pad configurations on the five JTAG
pins (PB7 andPC[3:0]) should be reverted to their default settings.
4.4 Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The registers
can be broken down into two main categories: Instruction Registers and Data Registers.
4.4.1 Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG
TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct
states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the
chain and updated, they are interpreted as the current instruction. The decode of the Instruction
Register bits is shown in Table 4-2 on page 165. A detailed explanation of each instruction, along
with its associated Data Register, follows.
Table 4-2. JTAG Instruction Register Commands
IR[3:0] Instruction Description
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
0000 EXTEST
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction into the controller.
0001 INTEST
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Table 4-2. JTAG Instruction Register Commands (continued)
IR[3:0] Instruction Description
Captures the current I/O values and shifts the sampled values out of the
Boundary Scan Chain while new preload data is shifted in.
0010 SAMPLE / PRELOAD
1000 ABORT Shifts data into the ARM Debug Port Abort Register.
1010 DPACC Shifts data into and out of the ARM DP Access Register.
1011 APACC Shifts data into and out of the ARM AC Access Register.
Loads manufacturing information defined by the IEEE Standard 1149.1
into the IDCODE chain and shifts it out.
1110 IDCODE
1111 BYPASS Connects TDI to TDO through a single Shift Register chain.
Defaults to the BYPASS instruction to ensure that TDI is always connected
to TDO.
All Others Reserved
4.4.1.1 EXTEST Instruction
The EXTEST instruction is not associated with its own Data Register chain. The EXTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. This allows
tests to be developed that drive known values out of the controller, which can be used to verify
connectivity. While the EXTEST instruction is present in the Instruction Register, the Boundary Scan
Data Register can be accessed to sample and shift out the current data and load new data into the
Boundary Scan Data Register.
4.4.1.2 INTEST Instruction
The INTEST instruction is not associated with its own Data Register chain. The INTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. This allows tests
to be developed that drive known values into the controller, which can be used for testing. It is
important to note that although the RST input pin is on the Boundary Scan Data Register chain, it
is only observable. While the INTEXT instruction is present in the Instruction Register, the Boundary
Scan Data Register can be accessed to sample and shift out the current data and load new data
into the Boundary Scan Data Register.
4.4.1.3 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
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each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data
Register” on page 168 for more information.
4.4.1.4 ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. Please see the “ABORT Data Register” on page 169 for more
information.
4.4.1.5 DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. Please see “DPACC
Data Register” on page 169 for more information.
4.4.1.6 APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
Please see “APACC Data Register” on page 169 for more information.
4.4.1.7 IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure their input and output data streams. IDCODE is the default instruction that is loaded into
the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, TRST is asserted, or the
Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 168 for more
information.
4.4.1.8 BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 168 for
more information.
4.4.2 Data Registers
The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan,
APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed
in the following sections.
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4.4.2.1 IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-3 on page 168. The standard requires that every JTAG-compliant device implement either
the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This allows auto configuration test tools to determine which instruction is the default instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly, and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x3BA0.0477. This allows the debuggers to automatically configure
themselves to work correctly with the Cortex-M3 during debug.
Figure 4-3. IDCODE Register Format
Version Part Number Manufacturer ID 1
31 28 27 12 11 1 0
TDI TDO
4.4.2.2 BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-4 on page 168. The standard requires that every JTAG-compliant device implement either
the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This allows auto configuration test tools to determine which instruction is the default instruction.
Figure 4-4. BYPASS Register Format
TDI 0 TDO
0
4.4.2.3 Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 4-5 on page 169. Each GPIO
pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data
Register. Each GPIO pin has three associated digital signals that are included in the chain. These
signals are input, output, and output enable, and are arranged in that order as can be seen in the
figure.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.
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Figure 4-5. Boundary Scan Register Format
O TDO TDI O IN
E UT
O O IN
U E
T
O O IN
E UT
O O IN
U E
T
I
N ... ...
GPIO PB6 GPIO m RST GPIO m+1 GPIO n
4.4.2.4 APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
4.4.2.5 DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
4.4.2.6 ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
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5 System Control
System control determines the overall operation of the device. It provides information about the
device, controls the clocking to the core and individual peripherals, and handles reset detection and
reporting.
5.1 Functional Description
The System Control module provides the following capabilities:
■ Device identification (see “Device Identification” on page 170)
■ Local control, such as reset (see “Reset Control” on page 170), power (see “Power
Control” on page 174) and clock control (see “Clock Control” on page 175)
■ System control (Run, Sleep, and Deep-Sleep modes); see “System Control” on page 180
5.1.1 Device Identification
Several read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers.
5.1.2 Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
5.1.2.1 CMOD0 and CMOD1 Test-Mode Control Pins
Two pins, CMOD0 and CMOD1, are defined for internal use for testing the microcontroller during
manufacture. They have no end-user function and should not be used. The CMOD pins should be
connected to ground.
5.1.2.2 Reset Sources
The controller has five sources of reset:
1. External reset input pin (RST) assertion; see “External RST Pin” on page 171.
2. Power-on reset (POR); see “Power-On Reset (POR)” on page 171.
3. Internal brown-out (BOR) detector; see “Brown-Out Reset (BOR)” on page 173.
4. Software-initiated reset (with the software reset registers); see “Software Reset” on page 173.
5. A watchdog timer reset condition violation; see “Watchdog Timer Reset” on page 174.
Table 5-1 provides a summary of results of the various reset operations.
Table 5-1. Reset Sources
Reset Source Core Reset? JTAG Reset? On-Chip Peripherals Reset?
Power-On Reset Yes Yes Yes
RST Yes Pin Config Only Yes
Brown-Out Reset Yes No Yes
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Table 5-1. Reset Sources (continued)
Reset Source Core Reset? JTAG Reset? On-Chip Peripherals Reset?
Software System Request Yes No Yes
Reseta
Software Peripheral Reset No No Yesb
Watchdog Reset Yes No Yes
a. By using the SYSRESREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control (APINT) register
b. Programmable on a module-by-module basis using the Software Reset Control Registers.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator.
5.1.2.3 Power-On Reset (POR)
Note: The power-on reset also resets the JTAG controller. An external reset does not.
The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates
a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a
threshold value (VTH). The microcontroller must be operating within the specified operating parameters
when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the microcontroller
must reach 3.0 V within 10 msec of VDD crossing 2.0 V to guarantee proper operation. For applications
that require the use of an external reset signal to hold the microcontroller in reset longer than the
internal POR, the RST input may be used as discussed in “External RST Pin” on page 171.
The Power-On Reset sequence is as follows:
1. The microcontroller waits for internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset
timing is shown in Figure 22-6 on page 686.
5.1.2.4 External RST Pin
Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be
sure to place any components connected to the RST signal as close to the microcontroller
as possible.
If the application only uses the internal POR circuit, the RST input must be connected to the power
supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 172.
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Figure 5-1. Basic RST Configuration
PU
RST
Stellaris®
R
VDD
RPU = 0 to 100 kΩ
The external reset pin (RST) resets the microcontroller including the core and all the on-chip
peripherals except the JTAG TAP controller (see “JTAG Interface” on page 158). The external reset
sequence is as follows:
1. The external reset pin (RST) is asserted for the duration specified by TMIN and then de-asserted
(see “Reset” on page 685).
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
To improve noise immunity and/or to delay reset at power up, the RST input may be connected to
an RC network as shown in Figure 5-2 on page 172.
Figure 5-2. External Circuitry to Extend Power-On Reset
PU
C1
RST
Stellaris®
R
VDD
RPU = 1 kΩ to 100 kΩ
C1 = 1 nF to 10 μF
If the application requires the use of an external reset switch, Figure 5-3 on page 173 shows the
proper circuitry to use.
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Figure 5-3. Reset Circuit Controlled by Switch
PU
C1
RS
RST
Stellaris®
R
VDD
Typical RPU = 10 kΩ
Typical RS = 470 Ω
C1 = 10 nF
The RPU and C1 components define the power-on delay.
The external reset timing is shown in Figure 22-5 on page 686.
5.1.2.5 Brown-Out Reset (BOR)
A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops
below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may
generate a controller interrupt or a system reset.
Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset.
The brown-out reset is equivalent to an assertion of the external RST input and the reset is held
active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt
handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to
determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 22-7 on page 686.
5.1.2.6 Software Reset
Software can reset a specific peripheral or generate a reset to the entire system .
Peripherals can be individually reset by software via three registers that control reset signals to each
peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and
subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with
the encoding of the clock gating control for peripherals and on-chip functions (see “System
Control” on page 180). Note that all reset signals for all clocks of the specified unit are asserted as
a result of a software-initiated reset.
The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
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1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is deasserted and the controller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
The software-initiated system reset timing is shown in Figure 22-8 on page 687.
5.1.2.7 Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts
down to its zero state again before the first time-out interrupt is cleared, and the reset signal has
been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset
sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the controller loads from memory the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
The watchdog reset timing is shown in Figure 22-9 on page 687.
5.1.3 Power Control
The Stellaris® microcontroller provides an integrated LDO regulator that may be used to provide
power to the majority of the controller's internal logic. For power reduction, the LDO regulator provides
software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range
of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of
the VADJ field in the LDO Power Control (LDOPCTL) register.
Figure 5-4 on page 175 shows the power architecture.
Note: On the printed circuit board, use the LDO output as the source of VDD25 input. Do not use
an external regulator to supply the voltage to VDD25. In addition, the LDO requires decoupling
capacitors. See “On-Chip Low Drop-Out (LDO) Regulator Characteristics” on page 680.
VDDA must be supplied with 3.3 V, or the microcontroller does not function properly. VDDA
is the supply for all of the analog circuitry on the device, including the LDO and the clock
circuitry.
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Figure 5-4. Power Architecture
I/O Buffers
Analog circuits
Low-noise
LDO
Internal
Logic and PLL
GND
GND
GND
GND
GNDA
GND
GND
GND
GND
VDD
VDD
VDD
VDD
VDDA
VDDA
VDD25
VDD25
VDD25
VDD25
LDO
+3.3V
GNDA
5.1.4 Clock Control
System control determines the control of clocks in this part.
5.1.4.1 Fundamental Clock Sources
There are multiple clock sources for use in the device:
■ Internal Oscillator (IOSC). The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
Applications that do not depend on accurate clock sources may use this clock source to reduce
system cost. The internal oscillator is the clock source the device uses during and following POR.
If the main oscillator is required, software must enable the main oscillator following reset and
allow the main oscillator to stabilize before changing the clock reference.
■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being
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used, the crystal value must be one of the supported frequencies between 3.579545 MHz through
8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC
through the specified speed of the device. The supported crystals are listed in the XTAL bit field
in the RCC register (see page 192).
■ Internal 30-kHz Oscillator. The internal 30-kHz oscillator is similar to the internal oscillator,
except that it provides an operational frequency of 30 kHz ± 50%. It is intended for use during
Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal
switching and also allows the main oscillator to be powered down.
■ External Real-Time Oscillator. The external real-time oscillator provides a low-frequency,
accurate clock reference. It is intended to provide the system with a real-time clock source. The
real-time oscillator is part of the Hibernation Module (see “Hibernation Module” on page 236) and
may also provide an accurate source of Deep-Sleep or Hibernate mode power savings.
The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The
frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive).
Table 5-2 on page 176 shows how the various clock sources can be used in a system.
Table 5-2. Clock Source Options
Clock Source Drive PLL? Used as SysClk?
Internal Oscillator (12 MHz) No BYPASS = 1 Yes BYPASS = 1, OSCSRC = 0x1
Internal Oscillator divide by 4 (3 No BYPASS = 1 Yes BYPASS = 1, OSCSRC = 0x2
MHz)
BYPASS = 0, OSCSRC = Yes BYPASS = 1, OSCSRC = 0x0
0x0
Main Oscillator Yes
Internal 30-kHz Oscillator No BYPASS = 1 Yes BYPASS = 1, OSCSRC = 0x3
External Real-Time Oscillator No BYPASS = 1 Yes BYPASS = 1, OSCSRC2 = 0x7
5.1.4.2 Clock Configuration
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options. These registers control the following clock
functionality:
■ Source of clocks in sleep and deep-sleep modes
■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
■ Clock divisors
■ Crystal input selection
Figure 5-5 on page 177 shows the logic for the main clock tree. The peripheral blocks are driven by
the system clock signal and can be individually enabled/disabled. The ADC clock signal is
automatically divided down to 16 MHz for proper ADC operation. The PWM clock signal is a
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synchronous divide of the system clock to provide the PWM circuit with more range (set with PWMDIV
in RCC).
Note: When the ADC module is in operation, the system clock must be at least 16 MHz.
Figure 5-5. Main Clock Tree
PLL
Main OSC (400 MHz)
Internal
OSC
(12 MHz)
Internal
OSC
(30 kHz)
÷ 4
Hibernation
Module
(32.768 kHz) ÷ 25
PWRDN
ADC Clock
System Clock
XTALa
PWRDN b
MOSCDIS a
IOSCDISa
OSCSRCb,d
BYPASS b,d
SYSDIVb,d
USESYSDIV a,d
PWMDW a
USEPWMDIV a
PWM Clock
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
÷ 2
÷ 50 CAN Clock
Note: The figure above shows all features available on all Stellaris® Fury-class devices. Not all peripherals may be
available on this device.
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the
divisor is applied. Table 5-3 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
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The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 5-2 on page 176.
Table 5-3. Possible System Clock Frequencies Using the SYSDIV Field
Frequency Frequency (BYPASS=1) StellarisWare Parametera
(BYPASS=0)
SYSDIV Divisor
0x0 /1 reserved Clock source frequency/2 SYSCTL_SYSDIV_1b
0x1 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2
0x2 /3 reserved Clock source frequency/3 SYSCTL_SYSDIV_3
0x3 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4
0x4 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5
0x5 /6 33.33 MHz Clock source frequency/6 SYSCTL_SYSDIV_6
0x6 /7 28.57 MHz Clock source frequency/7 SYSCTL_SYSDIV_7
0x7 /8 25 MHz Clock source frequency/8 SYSCTL_SYSDIV_8
0x8 /9 22.22 MHz Clock source frequency/9 SYSCTL_SYSDIV_9
0x9 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10
0xA /11 18.18 MHz Clock source frequency/11 SYSCTL_SYSDIV_11
0xB /12 16.67 MHz Clock source frequency/12 SYSCTL_SYSDIV_12
0xC /13 15.38 MHz Clock source frequency/13 SYSCTL_SYSDIV_13
0xD /14 14.29 MHz Clock source frequency/14 SYSCTL_SYSDIV_14
0xE /15 13.33 MHz Clock source frequency/15 SYSCTL_SYSDIV_15
0xF /16 12.5 MHz (default) Clock source frequency/16 SYSCTL_SYSDIV_16
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register
so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for
improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is
predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding
plus 1. Table 5-4 shows how the SYSDIV2 encoding affects the system clock frequency, depending
on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list
of possible clock sources, see Table 5-2 on page 176.
Table 5-4. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
Frequency Frequency (BYPASS2=1) StellarisWare Parametera
(BYPASS2=0)
SYSDIV2 Divisor
0x00 /1 reserved Clock source frequency/2 SYSCTL_SYSDIV_1b
0x01 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2
0x02 /3 reserved Clock source frequency/3 SYSCTL_SYSDIV_3
0x03 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4
0x04 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5
0x05 /6 33.33 MHz Clock source frequency/6 SYSCTL_SYSDIV_6
0x06 /7 28.57 MHz Clock source frequency/7 SYSCTL_SYSDIV_7
0x07 /8 25 MHz Clock source frequency/8 SYSCTL_SYSDIV_8
0x08 /9 22.22 MHz Clock source frequency/9 SYSCTL_SYSDIV_9
0x09 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10
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Table 5-4. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
(continued)
Frequency Frequency (BYPASS2=1) StellarisWare Parametera
(BYPASS2=0)
SYSDIV2 Divisor
... ... ... ... ...
0x3F /64 3.125 MHz Clock source frequency/64 SYSCTL_SYSDIV_64
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
5.1.4.3 Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise,
the range of supported crystals is 1 to 8.192 MHz.
The XTAL bit in the RCC register (see page 192) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
5.1.4.4 Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software specifies the output divisor to set the system clock frequency, and enables the
main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the
application of the output divisor.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 196). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency. Table 22-9 on page 683 shows the actual PLL frequency and error for
a given crystal choice.
The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 192)
describes the available crystal choices and default programming of the PLLCFG register. Any time
the XTAL field changes, the new settings are translated and the internal PLL settings are updated.
To configure the external 32-kHz real-time oscillator as the PLL input reference, program the OSCRC2
field in the Run-Mode Clock Configuration 2 (RCC2) register to be 0x7.
5.1.4.5 PLL Modes
The PLL has two modes of operation: Normal and Power-Down
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 192 and page 197).
5.1.4.6 PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
22-8 on page 682). During the relock time, the affected PLL is not usable as a clock reference.
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PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■ Change in the PLL from Power-Down to Normal mode.
A counter is defined to measure the TREADY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is set
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). Hardware is provided to keep
the PLL from being used as a system clock until the TREADY condition is met after one of the two
changes above. It is the user's responsibility to have a stable clock source (like the main oscillator)
before the RCC/RCC2 register is switched to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the controller from the oscillator selected by the RCC/RCC2
register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software
can use many methods to ensure that the system is clocked from the main PLL, including periodically
polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock
interrupt.
5.1.5 System Control
For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep
mode, respectively.
There are four levels of operation for the device defined as:
■ Run Mode. In Run mode, the controller actively executes code. Run mode provides normal
operation of the processor and all of the peripherals that are currently enabled by the RCGCn
registers. The system clock can be any of the available clock sources including the PLL.
■ Sleep Mode. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the
processor and the memory subsystem are not clocked and therefore no longer execute code.
Sleep mode is entered by the Cortex-M3 core executing a WFI(Wait for Interrupt)
instruction. Any properly configured interrupt event in the system will bring the processor back
into Run mode. See “Power Management” on page 89 for more details.
Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
■ Deep-Sleep Mode. In Deep-Sleep mode, the clock frequency of the active peripherals may
change (depending on the Run mode clock configuration) in addition to the processor clock being
stopped. An interrupt returns the device to Run mode from one of the sleep modes; the sleep
modes are entered on request from the code. Deep-Sleep mode is entered by first writing the
Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing
a WFI instruction. Any properly configured interrupt event in the system will bring the processor
back into Run mode. See “Power Management” on page 89 for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up,
if necessary, and the main oscillator is powered down. If the PLL is running at the time of the
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WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active
RCC/RCC2 register, to be determined by the DSDIVORIDE setting in the DSLPCLKCFG register,
up to /16 or /64 respectively. When the Deep-Sleep exit event occurs, hardware brings the system
clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling
the clocks that had been stopped during the Deep-Sleep duration.
■ Hibernate Mode. In this mode, the power supplies are turned off to the main part of the device
and only the Hibernation module's circuitry is active. An external wake event or RTC event is
required to bring the device back to Run mode. The Cortex-M3 processor and peripherals outside
of the Hibernation module see a normal "power on" sequence and the processor starts running
code. It can determine that it has been restarted from Hibernate mode by inspecting the
Hibernation module registers.
Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a
low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals
have been restored to their run mode configuration. The DAP is usually enabled by software tools
accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs,
a Hard Fault is triggered when software accesses a peripheral with an invalid clock.
A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a
system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses
a peripheral register that might cause a fault. This loop can be removed for production software as the
DAP is most likely not enabled during normal execution.
Because the DAP is disabled by default (power on reset), the user can also power-cycle the device. The
DAP is not enabled unless it is enabled through the JTAG or SWD interface.
5.2 Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source and allows
for the new PLL configuration to be validated before switching the system clock to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
5.3 Register Map
Table 5-5 on page 182 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register's address, relative to the System Control base address of
0x400F.E000.
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Note: Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Table 5-5. System Control Register Map
See
Offset Name Type Reset Description page
0x000 DID0 RO - Device Identification 0 184
0x004 DID1 RO - Device Identification 1 200
0x008 DC0 RO 0x00FF.007F Device Capabilities 0 202
0x010 DC1 RO 0x0311.33FF Device Capabilities 1 203
0x014 DC2 RO 0x070F.5337 Device Capabilities 2 205
0x018 DC3 RO 0xBF0F.B7FF Device Capabilities 3 207
0x01C DC4 RO 0x0000.00FF Device Capabilities 4 209
0x030 PBORCTL R/W 0x0000.7FFD Brown-Out Reset Control 186
0x034 LDOPCTL R/W 0x0000.0000 LDO Power Control 187
0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 231
0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 233
0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 235
0x050 RIS RO 0x0000.0000 Raw Interrupt Status 188
0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 189
0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 190
0x05C RESC R/W - Reset Cause 191
0x060 RCC R/W 0x078E.3AD1 Run-Mode Clock Configuration 192
0x064 PLLCFG RO - XTAL to PLL Translation 196
0x070 RCC2 R/W 0x0780.2810 Run-Mode Clock Configuration 2 197
0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 210
0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 216
0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 225
0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 212
0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 219
0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 227
0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 214
0x124 DCGC1 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 222
0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 229
0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 199
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5.4 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
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Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the device.
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved VER reserved CLASS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJOR MINOR
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows:
Value Description
0x1 Second version of the DID0 register format.
30:28 VER RO 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:24 reserved RO 0x0
Device Class
The CLASS field value identifies the internal design from which all mask
sets are generated for all devices in a particular product line. The CLASS
field value is changed for new product lines, for changes in fab process
(for example, a remap or shrink), or any case where the MAJOR or MINOR
fields require differentiation from prior devices. The value of the CLASS
field is encoded as follows (all other encodings are reserved):
Value Description
0x1 Stellaris® Fury-class devices.
23:16 CLASS RO 0x1
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Bit/Field Name Type Reset Description
Major Revision
This field specifies the major revision number of the device. The major
revision reflects changes to base layers of the design. The major revision
number is indicated in the part number as a letter (A for first revision, B
for second, and so on). This field is encoded as follows:
Value Description
0x0 Revision A (initial device)
0x1 Revision B (first base layer revision)
0x2 Revision C (second base layer revision)
and so on.
15:8 MAJOR RO -
Minor Revision
This field specifies the minor revision number of the device. The minor
revision reflects changes to the metal layers of the design. The MINOR
field value is reset when the MAJOR field is changed. This field is numeric
and is encoded as follows:
Value Description
0x0 Initial device, or a major revision update.
0x1 First metal layer change.
0x2 Second metal layer change.
and so on.
7:0 MINOR RO -
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Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BORIOR reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x0
BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the controller. If set, a
reset is signaled. Otherwise, an interrupt is signaled.
1 BORIOR R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 3: LDO Power Control (LDOPCTL), offset 0x034
The VADJ field in this register adjusts the on-chip output voltage (VOUT).
LDO Power Control (LDOPCTL)
Base 0x400F.E000
Offset 0x034
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved VADJ
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0
LDO Output Voltage
This field sets the on-chip output voltage. The programming values for
the VADJ field are provided below.
Value VOUT (V)
0x00 2.50
0x01 2.45
0x02 2.40
0x03 2.35
0x04 2.30
0x05 2.25
0x06-0x3F Reserved
0x1B 2.75
0x1C 2.70
0x1D 2.65
0x1E 2.60
0x1F 2.55
5:0 VADJ R/W 0x0
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Register 4: Raw Interrupt Status (RIS), offset 0x050
Central location for system control raw interrupts. These are set and cleared by hardware.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLRIS reserved BORRIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Raw Interrupt Status
This bit is set when the PLL TREADY Timer asserts.
6 PLLLRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
Brown-Out Reset Raw Interrupt Status
This bit is the raw interrupt status for any brown-out conditions. If set,
a brown-out condition is currently active. This is an unregistered signal
from the brown-out detection circuit. An interrupt is reported if the BORIM
bit in the IMC register is set and the BORIOR bit in the PBORCTL register
is cleared.
1 BORRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 5: Interrupt Mask Control (IMC), offset 0x054
Central location for system control interrupt masks.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLIM reserved BORIM reserved
Type RO RO RO RO RO RO RO RO RO R/W RO RO RO RO R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Interrupt Mask
This bit specifies whether a PLL Lock interrupt is promoted to a controller
interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set;
otherwise, an interrupt is not generated.
6 PLLLIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
Brown-Out Reset Interrupt Mask
This bit specifies whether a brown-out condition is promoted to a
controller interrupt. If set, an interrupt is generated if BORRIS is set;
otherwise, an interrupt is not generated.
1 BORIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
On a read, this register gives the current masked status value of the corresponding interrupt. All of
the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register
(see page 188).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLMIS reserved BORMIS reserved
Type RO RO RO RO RO RO RO RO RO R/W1C RO RO RO RO R/W1C RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Masked Interrupt Status
This bit is set when the PLL TREADY timer asserts. The interrupt is cleared
by writing a 1 to this bit.
6 PLLLMIS R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
BOR Masked Interrupt Status
The BORMIS is simply the BORRIS ANDed with the mask value, BORIM.
1 BORMIS R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an power-on reset is the cause, in which
case, all bits other than POR in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SW WDT BOR POR EXT
Type RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 reserved RO 0
Software Reset
When set, indicates a software reset is the cause of the reset event.
4 SW R/W -
Watchdog Timer Reset
When set, indicates a watchdog reset is the cause of the reset event.
3 WDT R/W -
Brown-Out Reset
When set, indicates a brown-out reset is the cause of the reset event.
2 BOR R/W -
Power-On Reset
When set, indicates a power-on reset is the cause of the reset event.
1 POR R/W -
External Reset
When set, indicates an external reset (RST assertion) is the cause of
the reset event.
0 EXT R/W -
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Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x078E.3AD1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved ACG SYSDIV USESYSDIV reserved USEPWMDIV PWMDIV reserved
Type RO RO RO RO R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWRDN reserved BYPASS reserved XTAL OSCSRC reserved IOSCDIS MOSCDIS
Type RO RO R/W RO R/W RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W
Reset 0 0 1 1 1 0 1 0 1 1 0 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:28 reserved RO 0x0
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.
27 ACG R/W 0
System Clock Divisor
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS
bit in this register is configured). See Table 5-3 on page 178 for bit
encodings.
If the SYSDIV value is less than MINSYSDIV (see page 203), and the
PLL is being used, then the MINSYSDIV value is used as the divisor.
If the PLL is not being used, the SYSDIV value can be less than
MINSYSDIV.
26:23 SYSDIV R/W 0xF
Enable System Clock Divider
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2 field
in the RCC2 register is used as the system clock divider rather than the
SYSDIV field in this register.
22 USESYSDIV R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
21 reserved RO 0
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Bit/Field Name Type Reset Description
Enable PWM Clock Divisor
Use the PWM clock divider as the source for the PWM clock.
20 USEPWMDIV R/W 0
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. This clock
is only power 2 divide and rising edge is synchronous without phase
shift from the system clock.
Value Divisor
0x0 /2
0x1 /4
0x2 /8
0x3 /16
0x4 /32
0x5 /64
0x6 /64
0x7 /64 (default)
19:17 PWMDIV R/W 0x7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16:14 reserved RO 0
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
13 PWRDN R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12 reserved RO 1
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
See Table 5-3 on page 178 for programming guidelines.
Note: The ADC must be clocked from the PLL or directly from a
14-MHz to 18-MHz clock source to operate properly. While
the ADC works in a 14-18 MHz range, to maintain a 1 M
sample/second rate, the ADC must be provided a 16-MHz
clock source.
11 BYPASS R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10 reserved RO 0
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Bit/Field Name Type Reset Description
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below. Depending on the crystal used,
the PLL frequency may not be exactly 400 MHz (see Table
22-9 on page 683 for more information).
Crystal Frequency (MHz) Using
the PLL
Crystal Frequency (MHz) Not
Using the PLL
Value
0x0 1.000 reserved
0x1 1.8432 reserved
0x2 2.000 reserved
0x3 2.4576 reserved
0x4 3.579545 MHz
0x5 3.6864 MHz
0x6 4 MHz
0x7 4.096 MHz
0x8 4.9152 MHz
0x9 5 MHz
0xA 5.12 MHz
0xB 6 MHz (reset value)
0xC 6.144 MHz
0xD 7.3728 MHz
0xE 8 MHz
0xF 8.192 MHz
9:6 XTAL R/W 0xB
Oscillator Source
Selects the input source for the OSC. The values are:
Value Input Source
MOSC
Main oscillator
0x0
IOSC
Internal oscillator (default)
0x1
IOSC/4
Internal oscillator / 4
0x2
30 kHz
30-KHz internal oscillator
0x3
For additional oscillator sources, see the RCC2 register.
5:4 OSCSRC R/W 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0x0
Internal Oscillator Disable
0: Internal oscillator (IOSC) is enabled.
1: Internal oscillator is disabled.
1 IOSCDIS R/W 0
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Bit/Field Name Type Reset Description
Main Oscillator Disable
0: Main oscillator is enabled .
1: Main oscillator is disabled (default).
0 MOSCDIS R/W 1
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Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 192).
The PLL frequency is calculated using the PLLCFG field values, as follows:
PLLFreq = OSCFreq * F / (R + 1)
XTAL to PLL Translation (PLLCFG)
Base 0x400F.E000
Offset 0x064
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved F R
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x0
PLL F Value
This field specifies the value supplied to the PLL’s F input.
13:5 F RO -
PLL R Value
This field specifies the value supplied to the PLL’s R input.
4:0 R RO -
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Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields, as shown in Table 5-6, when the USERCC2
bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a
means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC
field is located at the same LSB bit position; however, some RCC2 fields are larger than the
corresponding RCC field.
Table 5-6. RCC2 Fields that Override RCC fields
RCC2 Field... Overrides RCC Field
SYSDIV2, bits[28:23] SYSDIV, bits[26:23]
PWRDN2, bit[13] PWRDN, bit[13]
BYPASS2, bit[11] BYPASS, bit[11]
OSCSRC2, bits[6:4] OSCSRC, bits[5:4]
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x0780.2810
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USERCC2 reserved SYSDIV2 reserved
Type R/W RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWRDN2 reserved BYPASS2 reserved OSCSRC2 reserved
Type RO RO R/W RO R/W RO RO RO RO R/W R/W R/W RO RO RO RO
Reset 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0
Bit/Field Name Type Reset Description
Use RCC2
When set, overrides the RCC register fields.
31 USERCC2 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30:29 reserved RO 0x0
System Clock Divisor
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS2
bit is configured). SYSDIV2 is used for the divisor when both the
USESYSDIV bit in the RCC register and the USERCC2 bit in this register
are set. See Table 5-4 on page 178 for programming guidelines.
28:23 SYSDIV2 R/W 0x0F
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:14 reserved RO 0x0
Power-Down PLL
When set, powers down the PLL.
13 PWRDN2 R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12 reserved RO 0
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Bit/Field Name Type Reset Description
Bypass PLL
When set, bypasses the PLL for the clock source.
See Table 5-4 on page 178 for programming guidelines.
11 BYPASS2 R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10:7 reserved RO 0x0
Oscillator Source
Selects the input source for the OSC. The values are:
Value Description
MOSC
Main oscillator
0x0
IOSC
Internal oscillator
0x1
IOSC/4
Internal oscillator / 4
0x2
30 kHz
30-kHz internal oscillator
0x3
0x4 Reserved
0x5 Reserved
0x6 Reserved
32 kHz
32.768-kHz external oscillator
0x7
6:4 OSCSRC2 R/W 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0
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Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved DSDIVORIDE reserved
Type RO RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DSOSCSRC reserved
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:29 reserved RO 0x0
Divider Field Override
6-bit system divider field to override when Deep-Sleep occurs with PLL
running.
28:23 DSDIVORIDE R/W 0x0F
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:7 reserved RO 0x0
Clock Source
Specifies the clock source during Deep-Sleep mode.
Value Description
MOSC
Use main oscillator as source.
0x0
IOSC
Use internal 12-MHz oscillator as source.
0x1
0x2 Reserved
30 kHz
Use 30-kHz internal oscillator as source.
0x3
0x4 Reserved
0x5 Reserved
0x6 Reserved
32 kHz
Use 32.768-kHz external oscillator as source.
0x7
6:4 DSOSCSRC R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0x0
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Register 12: Device Identification 1 (DID1), offset 0x004
This register identifies the device family, part number, temperature range, pin count, and package
type.
Device Identification 1 (DID1)
Base 0x400F.E000
Offset 0x004
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VER FAM PARTNO
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOUNT reserved TEMP PKG ROHS QUAL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 0 0 0 0 0 - - - - - 1 - -
Bit/Field Name Type Reset Description
DID1 Version
This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Value Description
0x1 Second version of the DID1 register format.
31:28 VER RO 0x1
Family
This field provides the family identification of the device within the
Luminary Micro product portfolio. The value is encoded as follows (all
other encodings are reserved):
Value Description
Stellaris family of microcontollers, that is, all devices with
external part numbers starting with LM3S.
0x0
27:24 FAM RO 0x0
Part Number
This field provides the part number of the device within the family. The
value is encoded as follows (all other encodings are reserved):
Value Description
0x55 LM3S2965
23:16 PARTNO RO 0x55
Package Pin Count
This field specifies the number of pins on the device package. The value
is encoded as follows (all other encodings are reserved):
Value Description
0x2 100-pin or 108-ball package
15:13 PINCOUNT RO 0x2
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12:8 reserved RO 0
Temperature Range
This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x0 Commercial temperature range (0°C to 70°C)
0x1 Industrial temperature range (-40°C to 85°C)
0x2 Extended temperature range (-40°C to 105°C)
7:5 TEMP RO -
Package Type
This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):
Value Description
0x0 SOIC package
0x1 LQFP package
0x2 BGA package
4:3 PKG RO -
RoHS-Compliance
This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.
2 ROHS RO 1
Qualification Status
This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x0 Engineering Sample (unqualified)
0x1 Pilot Production (unqualified)
0x2 Fully Qualified
1:0 QUAL RO -
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Register 13: Device Capabilities 0 (DC0), offset 0x008
This register is predefined by the part and can be used to verify features.
Device Capabilities 0 (DC0)
Base 0x400F.E000
Offset 0x008
Type RO, reset 0x00FF.007F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRAMSZ
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASHSZ
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
SRAM Size
Indicates the size of the on-chip SRAM memory.
Value Description
0x00FF 64 KB of SRAM
31:16 SRAMSZ RO 0x00FF
Flash Size
Indicates the size of the on-chip flash memory.
Value Description
0x007F 256 KB of Flash
15:0 FLASHSZ RO 0x007F
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Register 14: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: CANs, PWM,
ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the
maximum clock frequency and maximum ADC sample rate. The format of this register is consistent
with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control
register.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0311.33FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved CAN1 CAN0 reserved PWM reserved ADC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MINSYSDIV reserved MAXADCSPD MPU HIB TEMPSNS PLL WDT SWO SWD JTAG
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:26 reserved RO 0
CAN Module 1 Present
When set, indicates that CAN unit 1 is present.
25 CAN1 RO 1
CAN Module 0 Present
When set, indicates that CAN unit 0 is present.
24 CAN0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:21 reserved RO 0
PWM Module Present
When set, indicates that the PWM module is present.
20 PWM RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:17 reserved RO 0
ADC Module Present
When set, indicates that the ADC module is present.
16 ADC RO 1
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4.
15:12 MINSYSDIV RO 0x3
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0
Max ADC Speed
Indicates the maximum rate at which the ADC samples data.
Value Description
0x3 1M samples/second
9:8 MAXADCSPD RO 0x3
MPU Present
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the "Cortex-M3 Peripherals" chapter in the
Stellaris Data Sheet for details on the MPU.
7 MPU RO 1
Hibernation Module Present
When set, indicates that the Hibernation module is present.
6 HIB RO 1
Temp Sensor Present
When set, indicates that the on-chip temperature sensor is present.
5 TEMPSNS RO 1
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
4 PLL RO 1
Watchdog Timer Present
When set, indicates that a watchdog timer is present.
3 WDT RO 1
SWO Trace Port Present
When set, indicates that the Serial Wire Output (SWO) trace port is
present.
2 SWO RO 1
SWD Present
When set, indicates that the Serial Wire Debugger (SWD) is present.
1 SWD RO 1
JTAG Present
When set, indicates that the JTAG debugger interface is present.
0 JTAG RO 1
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Register 15: Device Capabilities 2 (DC2), offset 0x014
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register
is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software
reset control register.
Device Capabilities 2 (DC2)
Base 0x400F.E000
Offset 0x014
Type RO, reset 0x070F.5337
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C1 reserved I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved UART2 UART1 UART0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Present
When set, indicates that analog comparator 2 is present.
26 COMP2 RO 1
Analog Comparator 1 Present
When set, indicates that analog comparator 1 is present.
25 COMP1 RO 1
Analog Comparator 0 Present
When set, indicates that analog comparator 0 is present.
24 COMP0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:20 reserved RO 0
Timer 3 Present
When set, indicates that General-Purpose Timer module 3 is present.
19 TIMER3 RO 1
Timer 2 Present
When set, indicates that General-Purpose Timer module 2 is present.
18 TIMER2 RO 1
Timer 1 Present
When set, indicates that General-Purpose Timer module 1 is present.
17 TIMER1 RO 1
Timer 0 Present
When set, indicates that General-Purpose Timer module 0 is present.
16 TIMER0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15 reserved RO 0
I2C Module 1 Present
When set, indicates that I2C module 1 is present.
14 I2C1 RO 1
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13 reserved RO 0
I2C Module 0 Present
When set, indicates that I2C module 0 is present.
12 I2C0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0
QEI1 Present
When set, indicates that QEI module 1 is present.
9 QEI1 RO 1
QEI0 Present
When set, indicates that QEI module 0 is present.
8 QEI0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0
SSI1 Present
When set, indicates that SSI module 1 is present.
5 SSI1 RO 1
SSI0 Present
When set, indicates that SSI module 0 is present.
4 SSI0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
UART2 Present
When set, indicates that UART module 2 is present.
2 UART2 RO 1
UART1 Present
When set, indicates that UART module 1 is present.
1 UART1 RO 1
UART0 Present
When set, indicates that UART module 0 is present.
0 UART0 RO 1
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Register 16: Device Capabilities 3 (DC3), offset 0x018
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os.
Device Capabilities 3 (DC3)
Base 0x400F.E000
Offset 0x018
Type RO, reset 0xBF0F.B7FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
32KHZ reserved CCP5 CCP4 CCP3 CCP2 CCP1 CCP0 reserved ADC3 ADC2 ADC1 ADC0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWMFAULT reserved C2PLUS C2MINUS reserved C1PLUS C1MINUS C0O C0PLUS C0MINUS PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
32KHz Input Clock Available
When set, indicates an even CCP pin is present and can be used as a
32-KHz input clock.
31 32KHZ RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30 reserved RO 0
CCP5 Pin Present
When set, indicates that Capture/Compare/PWM pin 5 is present.
29 CCP5 RO 1
CCP4 Pin Present
When set, indicates that Capture/Compare/PWM pin 4 is present.
28 CCP4 RO 1
CCP3 Pin Present
When set, indicates that Capture/Compare/PWM pin 3 is present.
27 CCP3 RO 1
CCP2 Pin Present
When set, indicates that Capture/Compare/PWM pin 2 is present.
26 CCP2 RO 1
CCP1 Pin Present
When set, indicates that Capture/Compare/PWM pin 1 is present.
25 CCP1 RO 1
CCP0 Pin Present
When set, indicates that Capture/Compare/PWM pin 0 is present.
24 CCP0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:20 reserved RO 0
ADC3 Pin Present
When set, indicates that ADC pin 3 is present.
19 ADC3 RO 1
ADC2 Pin Present
When set, indicates that ADC pin 2 is present.
18 ADC2 RO 1
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Bit/Field Name Type Reset Description
ADC1 Pin Present
When set, indicates that ADC pin 1 is present.
17 ADC1 RO 1
ADC0 Pin Present
When set, indicates that ADC pin 0 is present.
16 ADC0 RO 1
PWM Fault Pin Present
When set, indicates that the PWM Fault pin is present.
15 PWMFAULT RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14 reserved RO 0
C2+ Pin Present
When set, indicates that the analog comparator 2 (+) input pin is present.
13 C2PLUS RO 1
C2- Pin Present
When set, indicates that the analog comparator 2 (-) input pin is present.
12 C2MINUS RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11 reserved RO 0
C1+ Pin Present
When set, indicates that the analog comparator 1 (+) input pin is present.
10 C1PLUS RO 1
C1- Pin Present
When set, indicates that the analog comparator 1 (-) input pin is present.
9 C1MINUS RO 1
C0o Pin Present
When set, indicates that the analog comparator 0 output pin is present.
8 C0O RO 1
C0+ Pin Present
When set, indicates that the analog comparator 0 (+) input pin is present.
7 C0PLUS RO 1
C0- Pin Present
When set, indicates that the analog comparator 0 (-) input pin is present.
6 C0MINUS RO 1
PWM5 Pin Present
When set, indicates that the PWM pin 5 is present.
5 PWM5 RO 1
PWM4 Pin Present
When set, indicates that the PWM pin 4 is present.
4 PWM4 RO 1
PWM3 Pin Present
When set, indicates that the PWM pin 3 is present.
3 PWM3 RO 1
PWM2 Pin Present
When set, indicates that the PWM pin 2 is present.
2 PWM2 RO 1
PWM1 Pin Present
When set, indicates that the PWM pin 1 is present.
1 PWM1 RO 1
PWM0 Pin Present
When set, indicates that the PWM pin 0 is present.
0 PWM0 RO 1
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Register 17: Device Capabilities 4 (DC4), offset 0x01C
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Ethernet MAC
and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2,
and DCGC2 clock control registers and the SRCR2 software reset control register.
Device Capabilities 4 (DC4)
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x0000.00FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
GPIO Port H Present
When set, indicates that GPIO Port H is present.
7 GPIOH RO 1
GPIO Port G Present
When set, indicates that GPIO Port G is present.
6 GPIOG RO 1
GPIO Port F Present
When set, indicates that GPIO Port F is present.
5 GPIOF RO 1
GPIO Port E Present
When set, indicates that GPIO Port E is present.
4 GPIOE RO 1
GPIO Port D Present
When set, indicates that GPIO Port D is present.
3 GPIOD RO 1
GPIO Port C Present
When set, indicates that GPIO Port C is present.
2 GPIOC RO 1
GPIO Port B Present
When set, indicates that GPIO Port B is present.
1 GPIOB RO 1
GPIO Port A Present
When set, indicates that GPIO Port A is present.
0 GPIOA RO 1
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Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 0 (RCGC0)
Base 0x400F.E000
Offset 0x100
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved CAN1 CAN0 reserved PWM reserved ADC
Type RO RO RO RO RO RO R/W R/W RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MAXADCSPD reserved HIB reserved WDT reserved
Type RO RO RO RO RO RO R/W R/W RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:26 reserved RO 0
CAN1 Clock Gating Control
This bit controls the clock gating for CAN unit 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
25 CAN1 R/W 0
CAN0 Clock Gating Control
This bit controls the clock gating for CAN unit 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
24 CAN0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:21 reserved RO 0
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:17 reserved RO 0
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Bit/Field Name Type Reset Description
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:10 reserved RO 0
ADC Sample Speed
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:
Value Description
0x3 1M samples/second
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second
9:8 MAXADCSPD R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.
6 HIB R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved CAN1 CAN0 reserved PWM reserved ADC
Type RO RO RO RO RO RO R/W R/W RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MAXADCSPD reserved HIB reserved WDT reserved
Type RO RO RO RO RO RO R/W R/W RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:26 reserved RO 0
CAN1 Clock Gating Control
This bit controls the clock gating for CAN unit 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
25 CAN1 R/W 0
CAN0 Clock Gating Control
This bit controls the clock gating for CAN unit 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
24 CAN0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:21 reserved RO 0
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:17 reserved RO 0
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Bit/Field Name Type Reset Description
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:10 reserved RO 0
ADC Sample Speed
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:
Value Description
0x3 1M samples/second
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second
9:8 MAXADCSPD R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.
6 HIB R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved CAN1 CAN0 reserved PWM reserved ADC
Type RO RO RO RO RO RO R/W R/W RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved HIB reserved WDT reserved
Type RO RO RO RO RO RO RO RO RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:26 reserved RO 0
CAN1 Clock Gating Control
This bit controls the clock gating for CAN unit 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
25 CAN1 R/W 0
CAN0 Clock Gating Control
This bit controls the clock gating for CAN unit 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
24 CAN0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:21 reserved RO 0
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:17 reserved RO 0
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Bit/Field Name Type Reset Description
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:7 reserved RO 0
HIB Clock Gating Control
This bit controls the clock gating for the Hibernation module. If set, the
unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled.
6 HIB R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 1 (RCGC1)
Base 0x400F.E000
Offset 0x104
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C1 reserved I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved UART2 UART1 UART0
Type RO R/W RO R/W RO RO R/W R/W RO RO R/W R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
26 COMP2 R/W 0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
25 COMP1 R/W 0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:20 reserved RO 0
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Bit/Field Name Type Reset Description
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
19 TIMER3 R/W 0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18 TIMER2 R/W 0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17 TIMER1 R/W 0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15 reserved RO 0
I2C1 Clock Gating Control
This bit controls the clock gating for I2C module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
14 I2C1 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13 reserved RO 0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
12 I2C0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0
QEI1 Clock Gating Control
This bit controls the clock gating for QEI module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
9 QEI1 R/W 0
QEI0 Clock Gating Control
This bit controls the clock gating for QEI module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
8 QEI0 R/W 0
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 SSI1 R/W 0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
2 UART2 R/W 0
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
1 UART1 R/W 0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0 UART0 R/W 0
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Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 1 (SCGC1)
Base 0x400F.E000
Offset 0x114
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C1 reserved I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved UART2 UART1 UART0
Type RO R/W RO R/W RO RO R/W R/W RO RO R/W R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
26 COMP2 R/W 0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
25 COMP1 R/W 0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:20 reserved RO 0
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Bit/Field Name Type Reset Description
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
19 TIMER3 R/W 0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18 TIMER2 R/W 0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17 TIMER1 R/W 0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15 reserved RO 0
I2C1 Clock Gating Control
This bit controls the clock gating for I2C module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
14 I2C1 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13 reserved RO 0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
12 I2C0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0
QEI1 Clock Gating Control
This bit controls the clock gating for QEI module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
9 QEI1 R/W 0
QEI0 Clock Gating Control
This bit controls the clock gating for QEI module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
8 QEI0 R/W 0
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 SSI1 R/W 0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
2 UART2 R/W 0
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
1 UART1 R/W 0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0 UART0 R/W 0
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Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C1 reserved I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved UART2 UART1 UART0
Type RO R/W RO R/W RO RO R/W R/W RO RO R/W R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
26 COMP2 R/W 0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
25 COMP1 R/W 0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:20 reserved RO 0
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System Control
Bit/Field Name Type Reset Description
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
19 TIMER3 R/W 0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18 TIMER2 R/W 0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17 TIMER1 R/W 0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15 reserved RO 0
I2C1 Clock Gating Control
This bit controls the clock gating for I2C module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
14 I2C1 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13 reserved RO 0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
12 I2C0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0
QEI1 Clock Gating Control
This bit controls the clock gating for QEI module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
9 QEI1 R/W 0
QEI0 Clock Gating Control
This bit controls the clock gating for QEI module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
8 QEI0 R/W 0
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 SSI1 R/W 0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
2 UART2 R/W 0
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
1 UART1 R/W 0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0 UART0 R/W 0
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System Control
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 2 (RCGC2)
Base 0x400F.E000
Offset 0x108
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
Port H Clock Gating Control
This bit controls the clock gating for Port H. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
7 GPIOH R/W 0
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
6 GPIOG R/W 0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 GPIOF R/W 0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 GPIOE R/W 0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3 GPIOD R/W 0
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Bit/Field Name Type Reset Description
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 GPIOC R/W 0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 GPIOB R/W 0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0 GPIOA R/W 0
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System Control
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset
0x118
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 2 (SCGC2)
Base 0x400F.E000
Offset 0x118
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
Port H Clock Gating Control
This bit controls the clock gating for Port H. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
7 GPIOH R/W 0
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
6 GPIOG R/W 0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 GPIOF R/W 0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 GPIOE R/W 0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3 GPIOD R/W 0
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Bit/Field Name Type Reset Description
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 GPIOC R/W 0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 GPIOB R/W 0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0 GPIOA R/W 0
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System Control
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
Port H Clock Gating Control
This bit controls the clock gating for Port H. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
7 GPIOH R/W 0
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
6 GPIOG R/W 0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 GPIOF R/W 0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 GPIOE R/W 0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3 GPIOD R/W 0
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Bit/Field Name Type Reset Description
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 GPIOC R/W 0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 GPIOB R/W 0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0 GPIOA R/W 0
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Register 27: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved CAN1 CAN0 reserved PWM reserved ADC
Type RO RO RO RO RO RO R/W R/W RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved HIB reserved WDT reserved
Type RO RO RO RO RO RO RO RO RO R/W RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:26 reserved RO 0
CAN1 Reset Control
Reset control for CAN unit 1.
25 CAN1 R/W 0
CAN0 Reset Control
Reset control for CAN unit 0.
24 CAN0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:21 reserved RO 0
PWM Reset Control
Reset control for PWM module.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:17 reserved RO 0
ADC0 Reset Control
Reset control for SAR ADC module 0.
16 ADC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:7 reserved RO 0
HIB Reset Control
Reset control for the Hibernation module.
6 HIB R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4 reserved RO 0
WDT Reset Control
Reset control for Watchdog unit.
3 WDT R/W 0
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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System Control
Register 28: Software Reset Control 1 (SRCR1), offset 0x044
Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved I2C1 reserved I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved UART2 UART1 UART0
Type RO R/W RO R/W RO RO R/W R/W RO RO R/W R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comp 2 Reset Control
Reset control for analog comparator 2.
26 COMP2 R/W 0
Analog Comp 1 Reset Control
Reset control for analog comparator 1.
25 COMP1 R/W 0
Analog Comp 0 Reset Control
Reset control for analog comparator 0.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:20 reserved RO 0
Timer 3 Reset Control
Reset control for General-Purpose Timer module 3.
19 TIMER3 R/W 0
Timer 2 Reset Control
Reset control for General-Purpose Timer module 2.
18 TIMER2 R/W 0
Timer 1 Reset Control
Reset control for General-Purpose Timer module 1.
17 TIMER1 R/W 0
Timer 0 Reset Control
Reset control for General-Purpose Timer module 0.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15 reserved RO 0
I2C1 Reset Control
Reset control for I2C unit 1.
14 I2C1 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13 reserved RO 0
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Bit/Field Name Type Reset Description
I2C0 Reset Control
Reset control for I2C unit 0.
12 I2C0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0
QEI1 Reset Control
Reset control for QEI unit 1.
9 QEI1 R/W 0
QEI0 Reset Control
Reset control for QEI unit 0.
8 QEI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0
SSI1 Reset Control
Reset control for SSI unit 1.
5 SSI1 R/W 0
SSI0 Reset Control
Reset control for SSI unit 0.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0
UART2 Reset Control
Reset control for UART unit 2.
2 UART2 R/W 0
UART1 Reset Control
Reset control for UART unit 1.
1 UART1 R/W 0
UART0 Reset Control
Reset control for UART unit 0.
0 UART0 R/W 0
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System Control
Register 29: Software Reset Control 2 (SRCR2), offset 0x048
Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register.
Software Reset Control 2 (SRCR2)
Base 0x400F.E000
Offset 0x048
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
Port H Reset Control
Reset control for GPIO Port H.
7 GPIOH R/W 0
Port G Reset Control
Reset control for GPIO Port G.
6 GPIOG R/W 0
Port F Reset Control
Reset control for GPIO Port F.
5 GPIOF R/W 0
Port E Reset Control
Reset control for GPIO Port E.
4 GPIOE R/W 0
Port D Reset Control
Reset control for GPIO Port D.
3 GPIOD R/W 0
Port C Reset Control
Reset control for GPIO Port C.
2 GPIOC R/W 0
Port B Reset Control
Reset control for GPIO Port B.
1 GPIOB R/W 0
Port A Reset Control
Reset control for GPIO Port A.
0 GPIOA R/W 0
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6 Hibernation Module
The Hibernation Module manages removal and restoration of power to provide a means for reducing
power consumption. When the processor and peripherals are idle, power can be completely removed
with only the Hibernation module remaining powered. Power can be restored based on an external
signal, or at a certain time using the built-in Real-Time Clock (RTC). The Hibernation module can
be independently supplied from a battery or an auxiliary power supply.
The Hibernation module has the following features:
■ System power control using discrete external regulator
■ Dedicated pin for waking from an external signal
■ Low-battery detection, signaling, and interrupt generation
■ 32-bit real-time clock (RTC)
■ Two 32-bit RTC match registers for timed wake-up and interrupt generation
■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal
■ RTC predivider trim for making fine adjustments to the clock rate
■ 64 32-bit words of non-volatile memory
■ Programmable interrupts for RTC match, external wake, and low battery events
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6.1 Block Diagram
Figure 6-1. Hibernation Module Block Diagram
HIBIM
HIBRIS
HIBMIS
HIBIC
HIBRTCT
Pre-Divider
/128
XOSC0
XOSC1
HIBCTL.CLK32EN
HIBCTL.CLKSEL
HIBRTCC
HIBRTCLD
HIBRTCM0
HIBRTCM1
RTC
Interrupts
Power
Sequence
Logic
MATCH0/1
WAKE
Interrupts
to CPU
Low Battery
Detect
LOWBAT
VDD
VBAT
HIB
HIBCTL.LOWBATEN HIBCTL.PWRCUT
HIBCTL.EXTWEN
HIBCTL.RTCWEN
HIBCTL.VABORT
Non-Volatile
Memory
64 words
HIBDATA
32.768 kHz
4.194304 MHz
6.2 Functional Description
The Hibernation module controls the power to the processor with an enable signal (HIB) that signals
an external voltage regulator to turn off.
The Hibernation module power source is determined dynamically. The supply voltage of the
Hibernation module is the larger of the main voltage source (VDD) or the battery/auxilliary voltage
source (VBAT). A voting circuit indicates the larger and an internal power switch selects the appropriate
voltage source. The Hibernation module also has a separate clock source to maintain a real-time
clock (RTC). Once in hibernation, the module signals an external voltage regulator to turn back on
the power when an external pin (WAKE) is asserted, or when the internal RTC reaches a certain
value. The Hibernation module can also detect when the battery voltage is low, and optionally
prevent hibernation when this occurs.
When waking from hibernation, the HIB signal is deasserted. The return of VDD causes a POR to
be executed. The time from when the WAKE signal is asserted to when code begins execution is
equal to the wake-up time (tWAKE_TO_HIB) plus the power-on reset time (TIRPOR).
6.2.1 Register Access Timing
Because the Hibernation module has an independent clocking domain, certain registers must be
written only with a timing gap between accesses. The delay time is tHIB_REG_WRITE, therefore software
must guarantee that a delay of tHIB_REG_WRITE is inserted between back-to-back writes to certain
Hibernation registers, or between a write followed by a read to those same registers. There is no
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restriction on timing for back-to-back reads from the Hibernation module. The following registers
are subject to this timing restriction:
■ Hibernation RTC Counter (HIBRTCC)
■ Hibernation RTC Match 0 (HIBRTCM0)
■ Hibernation RTC Match 1 (HIBRTCM1)
■ Hibernation RTC Load (HIBRTCLD)
■ Hibernation RTC Trim (HIBRTCT)
■ Hibernation Data (HIBDATA)
6.2.2 Clock Source
The Hibernation module must be clocked by an external source, even if the RTC feature is not used.
An external oscillator or crystal can be used for this purpose. To use a crystal, a 4.194304-MHz
crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to
produce the 32.768-kHz clock reference. For an alternate clock source, a 32.768-kHz oscillator can
be connected to the XOSC0 pin. See Figure 6-2 on page 239 and Figure 6-3 on page 239. Note that
these diagrams only show the connection to the Hibernation pins and not to the full system. See
“Hibernation Module” on page 687 for specific values.
The clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The type of clock
source is selected by setting the CLKSEL bit to 0 for a 4.194304-MHz clock source, and to 1 for a
32.768-kHz clock source. If the bit is set to 0, the 4.194304-MHz input clock is divided by 128,
resulting in a 32.768-kHz clock source. If a crystal is used for the clock source, the software must
leave a delay of tXOSC_SETTLE after setting the CLK32EN bit and before any other accesses to the
Hibernation module registers. The delay allows the crystal to power up and stabilize. If an oscillator
is used for the clock source, no delay is needed.
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Figure 6-2. Clock Source Using Crystal
Open drain
external wake
up circuit
3 V
Battery
GND
C1 C2
X1 RL
VBAT
EN
Input
Voltage
Regulator
or Switch
XOSC1
XOSC0
VDD
HIB
WAKE
IN OUT
Stellaris Microcontroller
RPU
Note: X1 = Crystal frequency is fXOSC_XTAL.
C1,2 = Capacitor value derived from crystal vendor load capacitance specifications.
RL = Load resistor is RXOSC_LOAD.
RPU = Pull-up resistor (1 M½).
See “Hibernation Module” on page 687 for specific parameter values.
Figure 6-3. Clock Source Using Dedicated Oscillator
Open drain
external wake
up circuit
EN
3 V
Battery
GND
Stellaris Microcontroller
Input
Voltage
Regulator
or Switch
Clock
Source
(fEXT_OSC)
N.C. XOSC1
XOSC0
VDD
HIB
WAKE VBAT
IN OUT
RPU
Note: RPU = Pull-up resistor (1 M½).
6.2.3 Battery Management
The Hibernation module can be independently powered by a battery or an auxiliary power source.
The module can monitor the voltage level of the battery and detect when the voltage drops below
VLOWBAT. When this happens, an interrupt can be generated. The module can also be configured
so that it will not go into Hibernate mode if the battery voltage drops below this threshold. Battery
voltage is not measured while in Hibernate mode.
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Important: System level factors may affect the accuracy of the low battery detect circuit. The
designer should consider battery type, discharge characteristics, and a test load during
battery voltage measurements.
Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher
voltage. Therefore, it is important to design the circuit to ensure that VDD is higher that VBAT under
nominal conditions or else the Hibernation module draws power from the battery even when VDD is
available.
The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN
bit of the HIBCTL register. In this configuration, the LOWBAT bit of the HIBRIS register will be set
when the battery level is low. If the VABORT bit is also set, then the module is prevented from entering
Hibernation mode when a low battery is detected. The module can also be configured to generate
an interrupt for the low-battery condition (see “Interrupts and Status” on page 241).
6.2.4 Real-Time Clock
The Hibernation module includes a 32-bit counter that increments once per second with a proper
clock source and configuration (see “Clock Source” on page 238). The 32.768-kHz clock signal is
fed into a predivider register which counts down the 32.768-kHz clock ticks to achieve a once per
second clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock
source by using the predivider trim register, HIBRTCT. This register has a nominal value of 0x7FFF,
and is used for one second out of every 64 seconds to divide the input clock. This allows the software
to make fine corrections to the clock rate by adjusting the predivider trim register up or down from
0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC
rate, and down from 0x7FFF in order to speed up the RTC rate.
The Hibernation module includes two 32-bit match registers that are compared to the value of the
RTC counter. The match registers can be used to wake the processor from hibernation mode, or
to generate an interrupt to the processor if it is not in hibernation.
The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be
set at any time by writing to the HIBRTCLD register. The predivider trim can be adjusted by reading
and writing the HIBRTCT register. The predivider uses this register once every 64 seconds to adjust
the clock rate. The two match registers can be set by writing to the HIBRTCM0 and HIBRTCM1
registers. The RTC can be configured to generate interrupts by using the interrupt registers (see
“Interrupts and Status” on page 241).
6.2.5 Non-Volatile Memory
The Hibernation module contains 64 32-bit words of memory which are retained during hibernation.
This memory is powered from the battery or auxiliary power supply during hibernation. The processor
software can save state information in this memory prior to hibernation, and can then recover the
state upon waking. The non-volatile memory can be accessed through the HIBDATA registers.
6.2.6 Power Control
Important: The Hibernation Module requires special system implementation considerations when
using HIB to control power, as it is intended to power-down all other sections of its host
device. All system signals and power supplies that connect to the chip must be driven
to 0 VDC or powered down with the same regulator controlled by HIB. See “Hibernation
Module” on page 687 for more details.
The Hibernation module controls power to the microcontroller through the use of the HIB pin. This
pin is intended to be connected to the enable signal of the external regulator(s) providing 3.3 V
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and/or 2.5 V to the microcontroller. When the HIB signal is asserted by the Hibernation module, the
external regulator is turned off and no longer powers the system. The Hibernation module remains
powered from the VBAT supply (which could be a battery or an auxiliary power source) until a Wake
event. Power to the device is restored by deasserting the HIB signal, which causes the external
regulator to turn power back on to the chip.
6.2.7 Initiating Hibernate
Hibernation mode is initiated by the microcontroller setting the HIBREQ bit of the HIBCTL register.
Prior to doing this, a wake-up condition must be configured, either from the external WAKE pin, or
by using an RTC match.
The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN
bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Either
one or both of these bits can be set prior to going into hibernation. The WAKE pin includes a weak
internal pull-up. Note that both the HIB and WAKE pins use the Hibernation module's internal power
supply as the logic 1 reference.
When the Hibernation module wakes, the microcontroller will see a normal power-on reset. Software
can detect that the power-on was due to a wake from hibernation by examining the raw interrupt
status register (see “Interrupts and Status” on page 241) and by looking for state data in the non-volatile
memory (see “Non-Volatile Memory” on page 240).
When the HIB signal deasserts, enabling the external regulator, the external regulator must reach
the operating voltage within tHIB_TO_VDD.
6.2.8 Interrupts and Status
The Hibernation module can generate interrupts when the following conditions occur:
■ Assertion of WAKE pin
■ RTC match
■ Low battery detected
All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate
module can only generate a single interrupt request to the controller at any given time. The software
interrupt handler can service multiple interrupt events by reading the HIBMIS register. Software can
also read the status of the Hibernation module at any time by reading the HIBRIS register which
shows all of the pending events. This register can be used at power-on to see if a wake condition
is pending, which indicates to the software that a hibernation wake occurred.
The events that can trigger an interrupt are configured by setting the appropriate bits in the HIBIM
register. Pending interrupts can be cleared by writing the corresponding bit in the HIBIC register.
6.3 Initialization and Configuration
The Hibernation module can be set in several different configurations. The following sections show
the recommended programming sequence for various scenarios. The examples below assume that
a 32.768-kHz oscillator is used, and thus always show bit 2 (CLKSEL) of the HIBCTL register set
to 1. If a 4.194304-MHz crystal is used instead, then the CLKSEL bit remains cleared. Because the
Hibernation module runs at 32.768 kHz and is asynchronous to the rest of the system, software
must allow a delay of tHIB_REG_WRITE after writes to certain registers (see “Register Access
Timing” on page 237). The registers that require a delay are listed in a note in “Register
Map” on page 243 as well as in each register description.
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6.3.1 Initialization
The Hibernation module clock source must be enabled first, even if the RTC feature is not used. If
a 4.194304-MHz crystal is used, perform the following steps:
1. Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128
input path.
2. Wait for a time of tXOSC_SETTLE for the crystal to power up and stabilize before performing any
other operations with the Hibernation module.
If a 32.678-kHz oscillator is used, then perform the following steps:
1. Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input.
2. No delay is necessary.
The above is only necessary when the entire system is initialized for the first time. If the processor
is powered due to a wake from hibernation, then the Hibernation module has already been powered
up and the above steps are not necessary. The software can detect that the Hibernation module
and clock are already powered by examining the CLK32EN bit of the HIBCTL register.
6.3.2 RTC Match Functionality (No Hibernation)
Use the following steps to implement the RTC match functionality of the Hibernation module:
1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the
HIBIM register at offset 0x014.
4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting.
6.3.3 RTC Match/Wake-Up from Hibernation
Use the following steps to implement the RTC match and wake-up functionality of the Hibernation
module:
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the
HIBCTL register at offset 0x010.
6.3.4 External Wake-Up from Hibernation
Use the following steps to implement the Hibernation module with the external WAKE pin as the
wake-up source for the microcontroller:
1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
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2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the
HIBCTL register at offset 0x010.
6.3.5 RTC/External Wake-Up from Hibernation
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F
to the HIBCTL register at offset 0x010.
6.4 Register Map
Table 6-1 on page 243 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000. Note that the Hibernation module clock must be enabled
before the registers can be programmed (see page 210). There must be a delay of 3 system clocks
after the Hibernation module clock is enabled before any Hibernation module registers are accessed.
Table 6-1. Hibernation Module Register Map
See
Offset Name Type Reset Description page
0x000 HIBRTCC RO 0x0000.0000 Hibernation RTC Counter 244
0x004 HIBRTCM0 R/W 0xFFFF.FFFF Hibernation RTC Match 0 245
0x008 HIBRTCM1 R/W 0xFFFF.FFFF Hibernation RTC Match 1 246
0x00C HIBRTCLD R/W 0xFFFF.FFFF Hibernation RTC Load 247
0x010 HIBCTL R/W 0x8000.0000 Hibernation Control 248
0x014 HIBIM R/W 0x0000.0000 Hibernation Interrupt Mask 250
0x018 HIBRIS RO 0x0000.0000 Hibernation Raw Interrupt Status 251
0x01C HIBMIS RO 0x0000.0000 Hibernation Masked Interrupt Status 252
0x020 HIBIC R/W1C 0x0000.0000 Hibernation Interrupt Clear 253
0x024 HIBRTCT R/W 0x0000.7FFF Hibernation RTC Trim 254
0x030- HIBDATA R/W - Hibernation Data 255
0x12C
6.5 Register Descriptions
The remainder of this section lists and describes the Hibernation module registers, in numerical
order by address offset.
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Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000
This register is the current 32-bit value of the RTC counter.
Hibernation RTC Counter (HIBRTCC)
Base 0x400F.C000
Offset 0x000
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
RTC Counter
A read returns the 32-bit counter value. This register is read-only. To
change the value, use the HIBRTCLD register.
31:0 RTCC RO 0x0000.0000
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Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004
This register is the 32-bit match 0 register for the RTC counter.
Hibernation RTC Match 0 (HIBRTCM0)
Base 0x400F.C000
Offset 0x004
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCM0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCM0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
RTC Match 0
A write loads the value into the RTC match register.
A read returns the current match value.
31:0 RTCM0 R/W 0xFFFF.FFFF
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Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008
This register is the 32-bit match 1 register for the RTC counter.
Hibernation RTC Match 1 (HIBRTCM1)
Base 0x400F.C000
Offset 0x008
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCM1
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCM1
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
RTC Match 1
A write loads the value into the RTC match register.
A read returns the current match value.
31:0 RTCM1 R/W 0xFFFF.FFFF
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Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C
This register is the 32-bit value loaded into the RTC counter.
Hibernation RTC Load (HIBRTCLD)
Base 0x400F.C000
Offset 0x00C
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCLD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCLD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
RTC Load
A write loads the current value into the RTC counter (RTCC).
A read returns the 32-bit load value.
31:0 RTCLD R/W 0xFFFF.FFFF
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Register 5: Hibernation Control (HIBCTL), offset 0x010
This register is the control register for the Hibernation module.
Hibernation Control (HIBCTL)
Base 0x400F.C000
Offset 0x010
Type R/W, reset 0x8000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBREQ RTCEN
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Power Cut Abort Enable
Value Description
0 Power cut occurs during a low-battery alert.
1 Power cut is aborted.
7 VABORT R/W 0
Clocking Enable
Value Description
0 Disabled
1 Enabled
This bit must be enabled to use the Hibernation module. If a crystal is
used, then software should wait 20 ms after setting this bit to allow the
crystal to power up and stabilize.
6 CLK32EN R/W 0
Low Battery Monitoring Enable
Value Description
0 Disabled
1 Enabled
When set, low battery voltage detection is enabled (VBAT < VLOWBAT).
5 LOWBATEN R/W 0
External WAKE Pin Enable
Value Description
0 Disabled
1 Enabled
When set, an external event on the WAKE pin will re-power the device.
4 PINWEN R/W 0
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Bit/Field Name Type Reset Description
RTC Wake-up Enable
Value Description
0 Disabled
1 Enabled
When set, an RTC match event (RTCM0 or RTCM1) will re-power the
device based on the RTC counter value matching the corresponding
match register 0 or 1.
3 RTCWEN R/W 0
Hibernation Module Clock Select
Value Description
Use Divide by 128 output. Use this value for a
4.194304-MHz crystal.
0
Use raw output. Use this value for a 32.768-kHz
oscillator.
1
2 CLKSEL R/W 0
Hibernation Request
Value Description
0 Disabled
1 Hibernation initiated
After a wake-up event, this bit is cleared by hardware.
1 HIBREQ R/W 0
RTC Timer Enable
Value Description
0 Disabled
1 Enabled
0 RTCEN R/W 0
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Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014
This register is the interrupt mask register for the Hibernation module interrupt sources.
Hibernation Interrupt Mask (HIBIM)
Base 0x400F.C000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
External Wake-Up Interrupt Mask
Value Description
0 Masked
1 Unmasked
3 EXTW R/W 0
Low Battery Voltage Interrupt Mask
Value Description
0 Masked
1 Unmasked
2 LOWBAT R/W 0
RTC Alert1 Interrupt Mask
Value Description
0 Masked
1 Unmasked
1 RTCALT1 R/W 0
RTC Alert0 Interrupt Mask
Value Description
0 Masked
1 Unmasked
0 RTCALT0 R/W 0
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Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018
This register is the raw interrupt status for the Hibernation module interrupt sources.
Hibernation Raw Interrupt Status (HIBRIS)
Base 0x400F.C000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
3 EXTW RO 0 External Wake-Up Raw Interrupt Status
2 LOWBAT RO 0 Low Battery Voltage Raw Interrupt Status
1 RTCALT1 RO 0 RTC Alert1 Raw Interrupt Status
0 RTCALT0 RO 0 RTC Alert0 Raw Interrupt Status
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Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C
This register is the masked interrupt status for the Hibernation module interrupt sources.
Hibernation Masked Interrupt Status (HIBMIS)
Base 0x400F.C000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
3 EXTW RO 0 External Wake-Up Masked Interrupt Status
2 LOWBAT RO 0 Low Battery Voltage Masked Interrupt Status
1 RTCALT1 RO 0 RTC Alert1 Masked Interrupt Status
0 RTCALT0 RO 0 RTC Alert0 Masked Interrupt Status
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Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020
This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources.
Hibernation Interrupt Clear (HIBIC)
Base 0x400F.C000
Offset 0x020
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EXTW LOWBAT RTCALT1 RTCALT0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000.0000
External Wake-Up Masked Interrupt Clear
Reads return an indeterminate value.
3 EXTW R/W1C 0
Low Battery Voltage Masked Interrupt Clear
Reads return an indeterminate value.
2 LOWBAT R/W1C 0
RTC Alert1 Masked Interrupt Clear
Reads return an indeterminate value.
1 RTCALT1 R/W1C 0
RTC Alert0 Masked Interrupt Clear
Reads return an indeterminate value.
0 RTCALT0 R/W1C 0
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Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024
This register contains the value that is used to trim the RTC clock predivider. It represents the
computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock
cycles.
Hibernation RTC Trim (HIBRTCT)
Base 0x400F.C000
Offset 0x024
Type R/W, reset 0x0000.7FFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
RTC Trim Value
This value is loaded into the RTC predivider every 64 seconds. It is used
to adjust the RTC rate to account for drift and inaccuracy in the clock
source. The compensation is made by software by adjusting the default
value of 0x7FFF up or down.
15:0 TRIM R/W 0x7FFF
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Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C
This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the
system processor in order to store any non-volatile state data and will not lose power during a power
cut operation.
Hibernation Data (HIBDATA)
Base 0x400F.C000
Offset 0x030-0x12C
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTD
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
31:0 RTD R/W - Hibernation Module NV Registers[63:0]
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7 Internal Memory
The LM3S2965 microcontroller comes with 64 KB of bit-banded SRAM and 256 KB of flash memory.
The flash controller provides a user-friendly interface, making flash programming a simple task.
Flash protection can be applied to the flash memory on a 2-KB block basis.
7.1 Block Diagram
Figure 7-1 on page 256 illustrates the Flash functions. The dashed boxes in the figure indicate
registers residing in the System Control module rather than the Flash Control module.
Figure 7-1. Flash Block Diagram
Flash Control
FMA
FMD
FCIM
FCMISC
Flash Array
Cortex-M3
Bridge
SRAM Array
System
Bus
Icode
Bus
Dcode
Bus
Flash Protection
FMPREn
FMPPEn
Flash Timing
USECRL
User Registers
USER_DBG
USER_REG0
USER_REG1
FMC
FCRIS
7.2 Functional Description
This section describes the functionality of the SRAM and Flash memories.
7.2.1 SRAM Memory
The internal SRAM of the Stellaris® devices is located at address 0x2000.0000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has
introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor,
certain regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
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With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, see “Bit-Banding” on page 75.
7.2.2 Flash Memory
The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be
programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB
blocks that can be individually protected. The protection allows blocks to be marked as read-only
or execute-only, providing different levels of code protection. Read-only blocks cannot be erased
or programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
See also “Serial Flash Loader” on page 693 for a preprogrammed flash-resident utility used to
download code to the flash memory of a device without the use of a debug interface.
7.2.2.1 Flash Memory Timing
The timing for the flash is automatically handled by the flash controller. However, in order to do so,
it must know the clock rate of the system in order to time its internal signals properly. The number
of clock cycles per microsecond must be provided to the flash controller for it to accomplish this
timing. It is software's responsibility to keep the flash controller updated with this information via the
USec Reload (USECRL) register.
On reset, the USECRL register is loaded with a value that configures the flash timing so that it works
with the maximum clock rate of the part. If software changes the system operating frequency, the
new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash
modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value
of 0x13 (20-1) must be written to the USECRL register.
7.2.2.2 Flash Memory Protection
The user is provided two forms of flash protection per 2-KB flash blocks in four pairs of 32-bit wide
registers. The protection policy for each form is controlled by individual bits (per policy per block)
in the FMPPEn and FMPREn registers.
■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed
(written) or erased. If cleared, the block may not be changed.
■ Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may
be executed or read by software or debuggers. If a bit is cleared, the corresponding block may
only be executed, and contents of the memory block are prohibited from being read as data.
The policies may be combined as shown in Table 7-1 on page 257.
Table 7-1. Flash Protection Policy Combinations
FMPPEn FMPREn Protection
Execute-only protection. The block may only be executed and may not be written or erased.
This mode is used to protect code.
0 0
The block may be written, erased or executed, but not read. This combination is unlikely to
be used.
1 0
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Table 7-1. Flash Protection Policy Combinations (continued)
FMPPEn FMPREn Protection
Read-only protection. The block may be read or executed but may not be written or erased.
This mode is used to lock the block from further modification while allowing any read or
execute access.
0 1
1 1 No protection. The block may be written, erased, executed or read.
A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited
and generates a bus fault. A Flash memory access that attempts to program or erase a
program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt
(by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software
developers of poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. These settings create a policy of open access and programmability. The register bits may
be changed by clearing the specific register bit. The changes are not permanent until the register
is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a
0 and not committed, it may be restored by executing a power-on reset sequence. The changes
are committed using the Flash Memory Control (FMC) register. Details on programming these bits
are discussed in “Nonvolatile Register Programming” on page 259.
7.2.2.3 Interrupts
The Flash memory controller can generate interrupts when the following conditions are observed:
■ Programming Interrupt - signals when a program or erase action is complete.
■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block
of memory that is protected by its corresponding FMPPEn bit.
The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller
Masked Interrupt Status (FCMIS) register (see page 267) by setting the corresponding MASK bits.
If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw
Interrupt Status (FCRIS) register (see page 266).
Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the
corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register
(see page 268).
7.3 Flash Memory Initialization and Configuration
7.3.1 Flash Programming
The Stellaris devices provide a user-friendly interface for flash programming. All erase/program
operations are handled via three registers: FMA, FMD, and FMC.
During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory
is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation
is complete. If instruction execution is required during a Flash memory operation, the code that is
executing must be placed in SRAM and executed from there while the flash operation is in progress.
7.3.1.1 To program a 32-bit word
1. Write source data to the FMD register.
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2. Write the target address to the FMA register.
3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register.
4. Poll the FMC register until the WRITE bit is cleared.
7.3.1.2 To perform an erase of a 1-KB page
1. Write the page address to the FMA register.
2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register.
3. Poll the FMC register until the ERASE bit is cleared.
7.3.1.3 To perform a mass erase of the flash
1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register.
2. Poll the FMC register until the MERASE bit is cleared.
7.3.2 Nonvolatile Register Programming
This section discusses how to update registers that are resident within the Flash memory itself.
These registers exist in a separate space from the main Flash memory array and are not affected
by an ERASE or MASS ERASE operation. The bits in these registers can be changed from 1 to 0
with a write operation. Prior to being committed, the register contents are unaffected by any reset
condition except power-on reset, which returns the register contents to the original value. By
committing the register values using the COMT bit in the FMC register, the register contents become
nonvolatile and are therefore retained following power cycling. Once the register contents are
committed, the contents are permanent, and they cannot be restored to their factory default values.
With the exception of the USER_DBG register, the settings in these registers can be tested before
committing them to Flash memory. For the USER_DBG register, the data to be written is loaded
into the FMD register before it is committed. The FMD register is read only and does not allow the
USER_DBG operation to be tried before committing it to nonvolatile memory.
Important: The Flash memory registers can only have bits changed from 1 to 0 by user programming
and can only be committed once. After being committed, these registers cannot be
restored to their factory default values.
In addition, the USER_REG0, USER_REG1, USER_REG2, USER_REG3, and USER_DBG registers
each use bit 31 (NW) to indicate that they have not been committed and bits in the register may be
changed from 1 to 0. These five registers can only be committed once whereas the Flash memory
protection registers may be committed multiple times. Table 7-2 on page 259 provides the FMA
address required for commitment of each of the registers and the source of the data to be written
when the FMC register is written with a value of 0xA442.0008. After writing the COMT bit, the user
may poll the FMC register to wait for the commit operation to complete.
Table 7-2. User-Programmable Flash Memory Resident Registers
Register to be Committed FMA Value Data Source
FMPRE0 0x0000.0000 FMPRE0
FMPRE1 0x0000.0002 FMPRE1
FMPRE2 0x0000.0004 FMPRE2
FMPRE3 0x0000.0006 FMPRE3
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Table 7-2. User-Programmable Flash Memory Resident Registers (continued)
Register to be Committed FMA Value Data Source
FMPPE0 0x0000.0001 FMPPE0
FMPPE1 0x0000.0003 FMPPE1
FMPPE2 0x0000.0005 FMPPE2
FMPPE3 0x0000.0007 FMPPE3
USER_REG0 0x8000.0000 USER_REG0
USER_REG1 0x8000.0001 USER_REG1
USER_REG2 0x8000.0002 USER_REG2
USER_REG3 0x8000.0003 USER_REG3
USER_DBG 0x7510.0000 FMD
7.4 Register Map
Table 7-3 on page 260 lists the Flash memory and control registers. The offset listed is a hexadecimal
increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC register
offsets are relative to the Flash memory control base address of 0x400F.D000. The Flash memory
protection register offsets are relative to the System Control base address of 0x400F.E000.
Table 7-3. Flash Register Map
See
Offset Name Type Reset Description page
Flash Memory Control Registers (Flash Control Offset)
0x000 FMA R/W 0x0000.0000 Flash Memory Address 262
0x004 FMD R/W 0x0000.0000 Flash Memory Data 263
0x008 FMC R/W 0x0000.0000 Flash Memory Control 264
0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 266
0x010 FCIM R/W 0x0000.0000 Flash Controller Interrupt Mask 267
0x014 FCMISC R/W1C 0x0000.0000 Flash Controller Masked Interrupt Status and Clear 268
Flash Memory Protection Registers (System Control Offset)
0x130 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 271
0x200 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 271
0x134 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 272
0x400 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 272
0x140 USECRL R/W 0x31 USec Reload 270
0x1D0 USER_DBG R/W 0xFFFF.FFFE User Debug 273
0x1E0 USER_REG0 R/W 0xFFFF.FFFF User Register 0 274
0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 275
0x204 FMPRE1 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 1 276
0x208 FMPRE2 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 2 277
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Table 7-3. Flash Register Map (continued)
See
Offset Name Type Reset Description page
0x20C FMPRE3 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 3 278
0x404 FMPPE1 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 1 279
0x408 FMPPE2 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 2 280
0x40C FMPPE3 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 3 281
7.5 Flash Register Descriptions (Flash Control Offset)
This section lists and describes the Flash Memory registers, in numerical order by address offset.
Registers in this section are relative to the Flash control base address of 0x400F.D000.
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Register 1: Flash Memory Address (FMA), offset 0x000
During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations, this register contains a 1 KB-aligned address and specifies
which page is erased. Note that the alignment requirements must be met by software or the results
of the operation are unpredictable.
Flash Memory Address (FMA)
Base 0x400F.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved OFFSET
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:18 reserved RO 0x0
Address Offset
Address offset in flash where operation is performed, except for
nonvolatile registers (see “Nonvolatile Register
Programming” on page 259 for details on values for this field).
17:0 OFFSET R/W 0x0
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Register 2: Flash Memory Data (FMD), offset 0x004
This register contains the data to be written during the programming cycle or read during the read
cycle. Note that the contents of this register are undefined for a read access of an execute-only
block. This register is not used during the erase cycles.
Flash Memory Data (FMD)
Base 0x400F.D000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Data Value
Data value for write operation.
31:0 DATA R/W 0x0
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Register 3: Flash Memory Control (FMC), offset 0x008
When this register is written, the flash controller initiates the appropriate access cycle for the location
specified by the Flash Memory Address (FMA) register (see page 262). If the access is a write
access, the data contained in the Flash Memory Data (FMD) register (see page 263) is written.
This is the final register written and initiates the memory operation. There are four control bits in the
lower byte of this register that, when set, initiate the memory operation. The most used of these
register bits are the ERASE and WRITE bits.
It is a programming error to write multiple control bits and the results of such an operation are
unpredictable.
Flash Memory Control (FMC)
Base 0x400F.D000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRKEY
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved COMT MERASE ERASE WRITE
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Flash Write Key
This field contains a write key, which is used to minimize the incidence
of accidental flash writes. The value 0xA442 must be written into this
field for a write to occur. Writes to the FMC register without this WRKEY
value are ignored. A read of this field returns the value 0.
31:16 WRKEY WO 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:4 reserved RO 0x0
Commit Register Value
Commit (write) of register value to nonvolatile storage. A write of 0 has
no effect on the state of this bit.
If read, the state of the previous commit access is provided. If the
previous commit access is complete, a 0 is returned; otherwise, if the
commit access is not complete, a 1 is returned.
This can take up to 50 μs.
3 COMT R/W 0
Mass Erase Flash Memory
If this bit is set, the flash main memory of the device is all erased. A
write of 0 has no effect on the state of this bit.
If read, the state of the previous mass erase access is provided. If the
previous mass erase access is complete, a 0 is returned; otherwise, if
the previous mass erase access is not complete, a 1 is returned.
This can take up to 250 ms.
2 MERASE R/W 0
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Bit/Field Name Type Reset Description
Erase a Page of Flash Memory
If this bit is set, the page of flash main memory as specified by the
contents of FMA is erased. A write of 0 has no effect on the state of this
bit.
If read, the state of the previous erase access is provided. If the previous
erase access is complete, a 0 is returned; otherwise, if the previous
erase access is not complete, a 1 is returned.
This can take up to 25 ms.
1 ERASE R/W 0
Write a Word into Flash Memory
If this bit is set, the data stored in FMD is written into the location as
specified by the contents of FMA. A write of 0 has no effect on the state
of this bit.
If read, the state of the previous write update is provided. If the previous
write access is complete, a 0 is returned; otherwise, if the write access
is not complete, a 1 is returned.
This can take up to 50 μs.
0 WRITE R/W 0
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Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled
if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Base 0x400F.D000
Offset 0x00C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PRIS ARIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x0
Programming Raw Interrupt Status
This bit provides status on programming cycles which are write or erase
actions generated through the FMC register bits (see page 264).
Value Description
1 The programming cycle has completed.
0 The programming cycle has not completed.
This status is sent to the interrupt controller when the PMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register.
1 PRIS RO 0
Access Raw Interrupt Status
Value Description
A program or erase action was attempted on a block of Flash
memory that contradicts the protection policy for that block as
set in the FMPPEn registers.
1
No access has tried to improperly program or erase the Flash
memory.
0
This status is sent to the interrupt controller when the AMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register.
0 ARIS RO 0
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Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the flash controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PMASK AMASK
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x0
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the interrupt controller.
Value Description
An interrupt is sent to the interrupt controller when the PRIS bit
is set.
1
The PRIS interrupt is suppressed and not sent to the interrupt
controller.
0
1 PMASK R/W 0
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
interrupt controller.
Value Description
An interrupt is sent to the interrupt controller when the ARIS bit
is set.
1
The ARIS interrupt is suppressed and not sent to the interrupt
controller.
0
0 AMASK R/W 0
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Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PMISC AMISC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x0
Programming Masked Interrupt Status and Clear
Value Description
When read, a 1 indicates that an unmasked interrupt was
signaled because a programming cycle completed.
Writing a 1 to this bit clears PMISC and also the PRIS bit in the
FCRIS register (see page 266).
1
When read, a 0 indicates that a programming cycle complete
interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
0
1 PMISC R/W1C 0
Access Masked Interrupt Status and Clear
Value Description
When read, a 1 indicates that an unmasked interrupt was
signaled because a program or erase action was attempted on
a block of Flash memory that contradicts the protection policy
for that block as set in the FMPPEn registers.
Writing a 1 to this bit clears AMISC and also the ARIS bit in the
FCRIS register (see page 266).
1
When read, a 0 indicates that no improper accesses have
occurred.
A write of 0 has no effect on the state of this bit.
0
0 AMISC R/W1C 0
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7.6 Flash Register Descriptions (System Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the System Control base address of
0x400F.E000.
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Register 7: USec Reload (USECRL), offset 0x140
Note: Offset is relative to System Control base address of 0x400F.E000
This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller.
The internal flash has specific minimum and maximum requirements on the length of time the high
voltage write pulse can be applied. It is required that this register contain the operating frequency
(in MHz -1) whenever the flash is being erased or programmed. The user is required to change this
value if the clocking conditions are changed for a flash erase/program operation.
USec Reload (USECRL)
Base 0x400F.E000
Offset 0x140
Type R/W, reset 0x31
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved USEC
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0
Microsecond Reload Value
MHz -1 of the controller clock when the flash is being erased or
programmed.
If the maximum system frequency is being used, USEC should be set to
0x31 (50 MHz) whenever the flash is being erased or programmed.
7:0 USEC R/W 0x31
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Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130
and 0x200
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. For additional information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 0 (FMPRE0)
Base 0x400F.E000
Offset 0x130 and 0x200
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable. Enables 2-KB Flash memory blocks to be executed
or read. The policies may be combined as shown in the table “Flash
Protection Policy Combinations”.
Value Description
Bits [31:0] each enable protection on a 2-KB block of
Flash memory up to the total of 64 KB.
0xFFFFFFFF
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset
0x134 and 0x400
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. For additional information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 0 (FMPPE0)
Base 0x400F.E000
Offset 0x134 and 0x400
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
Bits [31:0] each enable protection on a 2-KB block of
Flash memory up to the total of 64 KB.
0xFFFFFFFF
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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Register 10: User Debug (USER_DBG), offset 0x1D0
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides a write-once mechanism to disable external debugger access to the device
in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory
and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to
0 disables any external debugger access to the device permanently, starting with the next power-up
cycle of the device. The NW bit (bit 31) indicates that the register has not yet been committed and
is controlled through hardware to ensure that the register is only committed once. Prior to being
committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on
reset; any other type of reset does not affect this register. Once committed, this register cannot be
restored to the factory default value.
User Debug (USER_DBG)
Base 0x400F.E000
Offset 0x1D0
Type R/W, reset 0xFFFF.FFFE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NW DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA DBG1 DBG0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Bit/Field Name Type Reset Description
User Debug Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
31 NW R/W 1
User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
30:2 DATA R/W 0x1FFFFFFF
Debug Control 1
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
1 DBG1 R/W 1
Debug Control 0
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
0 DBG0 R/W 0
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Register 11: User Register 0 (USER_REG0), offset 0x1E0
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be committed
once. Bit 31 indicates that the register is available to be committed and is controlled through hardware
to ensure that the register is only committed once. Prior to being committed, bits can only be changed
from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not
affect this register. The write-once characteristics of this register are useful for keeping static
information like communication addresses that need to be unique per part and would otherwise
require an external EEPROM or other non-volatile device. Once committed, this register cannot be
restored to the factory default value.
User Register 0 (USER_REG0)
Base 0x400F.E000
Offset 0x1E0
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NW DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
31 NW R/W 1
User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
30:0 DATA R/W 0x7FFFFFFF
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Register 12: User Register 1 (USER_REG1), offset 0x1E4
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be committed
once. Bit 31 indicates that the register is available to be committed and is controlled through hardware
to ensure that the register is only committed once. Prior to being committed, bits can only be changed
from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not
affect this register. The write-once characteristics of this register are useful for keeping static
information like communication addresses that need to be unique per part and would otherwise
require an external EEPROM or other non-volatile device. Once committed, this register cannot be
restored to the factory default value.
User Register 1 (USER_REG1)
Base 0x400F.E000
Offset 0x1E4
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NW DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
31 NW R/W 1
User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
30:0 DATA R/W 0x7FFFFFFF
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Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. If the Flash memory size on the device is less than 64 KB, this register usually
reads as zeroes, but software should not rely on these bits to be zero. For additional information,
see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 1 (FMPRE1)
Base 0x400F.E000
Offset 0x204
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable. Enables 2-KB Flash memory blocks to be executed
or read. The policies may be combined as shown in the table “Flash
Protection Policy Combinations”.
Value Description
Bits [31:0] each enable protection on a 2-KB block of
Flash memory in memory range from 65 to 128 KB.
0xFFFFFFFF
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). For additional information, see the "Flash Memory
Protection" section.
Flash Memory Protection Read Enable 2 (FMPRE2)
Base 0x400F.E000
Offset 0x208
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 3 (FMPRE3)
Base 0x400F.E000
Offset 0x20C
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset
0x404
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. If the Flash memory size on the device is less than 64 KB, this register usually
reads as zeroes, but software should not rely on these bits to be zero. For additional information,
see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 1 (FMPPE1)
Base 0x400F.E000
Offset 0x404
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Value Description
Bits [31:0] each enable protection on a 2-KB block of
Flash memory in memory range from 65 to 128 KB.
0xFFFFFFFF
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset
0x408
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 2 (FMPPE2)
Base 0x400F.E000
Offset 0x408
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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Internal Memory
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset
0x40C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 3 (FMPPE3)
Base 0x400F.E000
Offset 0x40C
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 256 KB of flash.
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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8 General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of eight physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, Port H). The GPIO module supports
3-56 programmable input/output pins, depending on the peripherals being used.
The GPIO module has the following features:
■ 3-56 GPIOs, depending on configuration
■ 5-V-tolerant in input configuration
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ Bit masking in both read and write operations through address lines
■ Can initiate an ADC sample sequence
■ Pins configured as digital inputs are Schmitt-triggered.
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured
with an 18-mA pad drive for high-current applications
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
8.1 Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
While debugging systems where PB7 is being used as a GPIO, care must be taken to
ensure that a low value is not applied to the pin when the part is reset. Because PB7
reverts to the TRST function after reset, a Low value on the pin causes the JTAG
controller to be reset, resulting in a loss of JTAG communication.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
8-1 on page 283). The LM3S2965 microcontroller contains eight ports and thus eight of these physical
GPIO blocks.
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Figure 8-1. GPIO Port Block Diagram
Alternate Input
Alternate Output
Alternate Output Enable
Interrupt
GPIO Input
GPIO Output
GPIO Output Enable
Pad Output
Pad Output Enable
Package I/O Pin
GPIODATA
GPIODIR
Data
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
Interrupt
Control
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
Pad
Control
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
Identification Registers
GPIOAFSEL
Mode
Control
DEMUX MUX MUX
Digital
I/O Pad
Pad Input
GPIOLOCK
Commit
Control
GPIOCR
8.1.1 Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
8.1.1.1 Data Direction Operation
The GPIO Direction (GPIODIR) register (see page 291) is used to configure each individual pin as
an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and
the corresponding data register bit will capture and store the value on the GPIO port. When the data
direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit
will be driven out on the GPIO port.
8.1.1.2 Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 290) by using bits [9:2] of the address bus as a mask.
This allows software drivers to modify individual GPIO pins in a single instruction, without affecting
the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write
operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA
register covers 256 locations in the memory map.
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During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA
register is altered. If it is cleared to 0, it is left unchanged.
For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 8-2 on page 284, where u is data unchanged by the write.
Figure 8-2. GPIODATA Write Example
0 0 1 0 0 1 1 0 0
u u 1 u u 0 1 u
9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 1 1
7 6 5 4 3 2 1 0
GPIODATA
0xEB
0x098
ADDR[9:2]
0
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value.
For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-3 on page 284.
Figure 8-3. GPIODATA Read Example
0 0 1 1 0 0 0 1 0 0
0 0 1 1 0 0 0 0
9 8 7 6 5 4 3 2 1 0
1 0 1 1 1 1 1 0
7 6 5 4 3 2 1 0
Returned Value
GPIODATA
0x0C4
ADDR[9:2]
8.1.2 Interrupt Control
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source
holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:
■ GPIO Interrupt Sense (GPIOIS) register (see page 292)
■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 293)
■ GPIO Interrupt Event (GPIOIEV) register (see page 294)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 295).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 296 and page 297). As the name implies, the GPIOMIS register only shows interrupt
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conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a
GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not
only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC
Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC
conversion is initiated.
If no other PortB pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0)
register can disable the PortB interrupts, and the ADC interrupt can be used to read back the
converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on PB4,
and wait for the ADC interrupt or the ADC interrupt must be disabled in the EN0 register and the
PortB interrupt handler must poll the ADC registers until the conversion is completed. See page 109
for more information.
Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR)
register (see page 298).
When programming the following interrupt control registers, the interrupts should be masked (GPIOIM
set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can
generate a spurious interrupt if the corresponding bits are enabled.
8.1.3 Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is enabled
via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 299), the pin state is
controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO
mode, where the GPIODATA register is used to read/write the corresponding pins.
8.1.4 Commit Control
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and
PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register
(see page 299) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see
page 309) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see
page 310) have been set to 1.
8.1.5 Pad Control
The pad control registers allow for GPIO pad configuration by software based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength,
open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable.
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.
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8.1.6 Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
8.2 Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 8-1 on page 286
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 8-2 on page 286 shows how a rising edge interrupt would be configured for pin
2 of a GPIO port.
Table 8-1. GPIO Pad Configuration Examples
GPIO Register Bit Valuea
Configuration
AFSEL DIR ODR DEN PUR PDR DR2R DR4R DR8R SLR
Digital Input (GPIO) 0 0 0 1 ? ? X X X X
Digital Output (GPIO) 0 1 0 1 ? ? ? ? ? ?
Open Drain Output 0 1 1 1 X X ? ? ? ?
(GPIO)
Open Drain 1 X 1 1 X X ? ? ? ?
Input/Output (I2C)
Digital Input (Timer 1 X 0 1 ? ? X X X X
CCP)
Digital Input (QEI) 1 X 0 1 ? ? X X X X
Digital Output (PWM) 1 X 0 1 ? ? ? ? ? ?
Digital Output (Timer 1 X 0 1 ? ? ? ? ? ?
PWM)
Digital Input/Output 1 X 0 1 ? ? ? ? ? ?
(SSI)
Digital Input/Output 1 X 0 1 ? ? ? ? ? ?
(UART)
Analog Input 0 0 0 0 0 0 X X X X
(Comparator)
Digital Output 1 X 0 1 ? ? ? ? ? ?
(Comparator)
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
Table 8-2. GPIO Interrupt Configuration Example
Desired Pin 2 Bit Valuea
Interrupt
Event
Trigger
Register 7 6 5 4 3 2 1 0
0=edge X X X X X 0 X X
1=level
GPIOIS
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Table 8-2. GPIO Interrupt Configuration Example (continued)
Desired Pin 2 Bit Valuea
Interrupt
Event
Trigger
Register 7 6 5 4 3 2 1 0
0=single X X X X X 0 X X
edge
1=both
edges
GPIOIBE
0=Low level, X X X X X 1 X X
or negative
edge
1=High level,
or positive
edge
GPIOIEV
0=masked 0 0 0 0 0 1 0 0
1=not
masked
GPIOIM
a. X=Ignored (don’t care bit)
8.3 Register Map
Table 8-3 on page 288 lists the GPIO registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that GPIO port’s base address:
■ GPIO Port A: 0x4000.4000
■ GPIO Port B: 0x4000.5000
■ GPIO Port C: 0x4000.6000
■ GPIO Port D: 0x4000.7000
■ GPIO Port E: 0x4002.4000
■ GPIO Port F: 0x4002.5000
■ GPIO Port G: 0x4002.6000
■ GPIO Port H: 0x4002.7000
Note that the GPIO module clock must be enabled before the registers can be programmed (see
page 225). There must be a delay of 3 system clocks after the GPIO module clock is enabled before
any GPIO module registers are accessed.
Important: The GPIO registers in this chapter are duplicated in each GPIO block; however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to those unconnected bits has no effect, and reading those unconnected
bits returns no meaningful data.
Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are
0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and
PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default
reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
The default register type for the GPIOCR register is RO for all GPIO pins with the exception
of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because of this, the register type for
GPIO Port B7 and GPIO Port C[3:0] is R/W.
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The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the
exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port
is not accidentally programmed as a GPIO, these five pins default to non-committable.
Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while
the default reset value of GPIOCR for Port C is 0x0000.00F0.
Table 8-3. GPIO Register Map
See
Offset Name Type Reset Description page
0x000 GPIODATA R/W 0x0000.0000 GPIO Data 290
0x400 GPIODIR R/W 0x0000.0000 GPIO Direction 291
0x404 GPIOIS R/W 0x0000.0000 GPIO Interrupt Sense 292
0x408 GPIOIBE R/W 0x0000.0000 GPIO Interrupt Both Edges 293
0x40C GPIOIEV R/W 0x0000.0000 GPIO Interrupt Event 294
0x410 GPIOIM R/W 0x0000.0000 GPIO Interrupt Mask 295
0x414 GPIORIS RO 0x0000.0000 GPIO Raw Interrupt Status 296
0x418 GPIOMIS RO 0x0000.0000 GPIO Masked Interrupt Status 297
0x41C GPIOICR W1C 0x0000.0000 GPIO Interrupt Clear 298
0x420 GPIOAFSEL R/W - GPIO Alternate Function Select 299
0x500 GPIODR2R R/W 0x0000.00FF GPIO 2-mA Drive Select 301
0x504 GPIODR4R R/W 0x0000.0000 GPIO 4-mA Drive Select 302
0x508 GPIODR8R R/W 0x0000.0000 GPIO 8-mA Drive Select 303
0x50C GPIOODR R/W 0x0000.0000 GPIO Open Drain Select 304
0x510 GPIOPUR R/W - GPIO Pull-Up Select 305
0x514 GPIOPDR R/W 0x0000.0000 GPIO Pull-Down Select 306
0x518 GPIOSLR R/W 0x0000.0000 GPIO Slew Rate Control Select 307
0x51C GPIODEN R/W - GPIO Digital Enable 308
0x520 GPIOLOCK R/W 0x0000.0001 GPIO Lock 309
0x524 GPIOCR - - GPIO Commit 310
0xFD0 GPIOPeriphID4 RO 0x0000.0000 GPIO Peripheral Identification 4 312
0xFD4 GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 313
0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 314
0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 315
0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 316
0xFE4 GPIOPeriphID1 RO 0x0000.0000 GPIO Peripheral Identification 1 317
0xFE8 GPIOPeriphID2 RO 0x0000.0018 GPIO Peripheral Identification 2 318
0xFEC GPIOPeriphID3 RO 0x0000.0001 GPIO Peripheral Identification 3 319
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Table 8-3. GPIO Register Map (continued)
See
Offset Name Type Reset Description page
0xFF0 GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 320
0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 321
0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 322
0xFFC GPIOPCellID3 RO 0x0000.00B1 GPIO PrimeCell Identification 3 323
8.4 Register Descriptions
The remainder of this section lists and describes the GPIO registers, in numerical order by address
offset.
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Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 291).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from
the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause
the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the
corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
GPIO Data (GPIODATA)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Data
This register is virtually mapped to 256 locations in the address space.
To facilitate the reading and writing of data to these registers by
independent drivers, the data read from and the data written to the
registers are masked by the eight address lines ipaddr[9:2]. Reads
from this register return its current state. Writes to this register only affect
bits that are not masked by ipaddr[9:2] and are configured as
outputs. See “Data Register Operation” on page 283 for examples of
reads and writes.
7:0 DATA R/W 0x00
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Register 2: GPIO Direction (GPIODIR), offset 0x400
The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure
the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are
cleared by a reset, meaning all GPIO pins are inputs by default.
GPIO Direction (GPIODIR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x400
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DIR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Data Direction
The DIR values are defined as follows:
Value Description
0 Pins are inputs.
1 Pins are outputs.
7:0 DIR R/W 0x00
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Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the
corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits
are cleared by a reset.
GPIO Interrupt Sense (GPIOIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x404
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IS
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Sense
The IS values are defined as follows:
Value Description
0 Edge on corresponding pin is detected (edge-sensitive).
1 Level on corresponding pin is detected (level-sensitive).
7:0 IS R/W 0x00
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Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register (see page 292) is set to detect edges, bits set to High in GPIOIBE
configure the corresponding pin to detect both rising and falling edges, regardless of the
corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 294). Clearing a bit
configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.
GPIO Interrupt Both Edges (GPIOIBE)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x408
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IBE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Both Edges
The IBE values are defined as follows:
Value Description
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 294).
0
1 Both edges on the corresponding pin trigger an interrupt.
Note: Single edge is determined by the corresponding bit
in GPIOIEV.
7:0 IBE R/W 0x00
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Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C
The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the
corresponding pin to detect rising edges or high levels, depending on the corresponding bit value
in the GPIO Interrupt Sense (GPIOIS) register (see page 292). Clearing a bit configures the pin to
detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are
cleared by a reset.
GPIO Interrupt Event (GPIOIEV)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x40C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IEV
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Event
The IEV values are defined as follows:
Value Description
Falling edge or Low levels on corresponding pins trigger
interrupts.
0
Rising edge or High levels on corresponding pins trigger
interrupts.
1
7:0 IEV R/W 0x00
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Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding
pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables
interrupt triggering on that pin. All bits are cleared by a reset.
GPIO Interrupt Mask (GPIOIM)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x410
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IME
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Mask Enable
The IME values are defined as follows:
Value Description
0 Corresponding pin interrupt is masked.
1 Corresponding pin interrupt is not masked.
7:0 IME R/W 0x00
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Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the
status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the
requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask
(GPIOIM) register (see page 295). Bits read as zero indicate that corresponding input pins have not
initiated an interrupt. All bits are cleared by a reset.
GPIO Raw Interrupt Status (GPIORIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x414
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Raw Status
Reflects the status of interrupt trigger condition detection on pins (raw,
prior to masking).
The RIS values are defined as follows:
Value Description
0 Corresponding pin interrupt requirements not met.
1 Corresponding pin interrupt has met requirements.
7:0 RIS RO 0x00
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Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect
the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has
been generated, or the interrupt is masked.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not
only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC
Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC
conversion is initiated.
If no other PortB pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0)
register can disable the PortB interrupts, and the ADC interrupt can be used to read back the
converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on PB4,
and wait for the ADC interrupt or the ADC interrupt must be disabled in the EN0 register and the
PortB interrupt handler must poll the ADC registers until the conversion is completed. See page 109
for more information.
GPIOMIS is the state of the interrupt after masking.
GPIO Masked Interrupt Status (GPIOMIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x418
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Masked Interrupt Status
Masked value of interrupt due to corresponding pin.
The MIS values are defined as follows:
Value Description
0 Corresponding GPIO line interrupt not active.
1 Corresponding GPIO line asserting interrupt.
7:0 MIS RO 0x00
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Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt edge detection logic register. Writing a 0 has no effect.
GPIO Interrupt Clear (GPIOICR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x41C
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IC
Type RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Clear
The IC values are defined as follows:
Value Description
0 Corresponding interrupt is unaffected.
1 Corresponding interrupt is cleared.
7:0 IC W1C 0x00
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Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register
selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore
no GPIO line is set to hardware control by default.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and
PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register
(see page 299) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see
page 309) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see
page 310) have been set to 1.
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
While debugging systems where PB7 is being used as a GPIO, care must be taken to
ensure that a low value is not applied to the pin when the part is reset. Because PB7
reverts to the TRST function after reset, a Low value on the pin causes the JTAG
controller to be reset, resulting in a loss of JTAG communication.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
GPIO Alternate Function Select (GPIOAFSEL)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x420
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved AFSEL
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
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Bit/Field Name Type Reset Description
GPIO Alternate Function Select
The AFSEL values are defined as follows:
Value Description
0 Software control of corresponding GPIO line (GPIO mode).
Hardware control of corresponding GPIO line (alternate
hardware function).
1
Note: The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
7:0 AFSEL R/W -
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Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO
signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 2-mA Drive Select (GPIODR2R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x500
Type R/W, reset 0x0000.00FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DRV2
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad 2-mA Drive Enable
A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the
corresponding 2-mA enable bit. The change is effective on the second
clock cycle after the write.
7:0 DRV2 R/W 0xFF
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Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504
The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 4-mA Drive Select (GPIODR4R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x504
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DRV4
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad 4-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the
corresponding 4-mA enable bit. The change is effective on the second
clock cycle after the write.
7:0 DRV4 R/W 0x00
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Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R
register are automatically cleared by hardware.
GPIO 8-mA Drive Select (GPIODR8R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x508
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DRV8
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad 8-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the
corresponding 8-mA enable bit. The change is effective on the second
clock cycle after the write.
7:0 DRV8 R/W 0x00
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Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see
page 308). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R,
and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open-drain
input if the corresponding bit in the GPIODIR register is cleared. If open drain is selected while the
GPIO is configured as an input, the GPIO will remain an input and the open-drain selection has no
effect until the GPIO is changed to an output.
When using the I2C module, in addition to configuring the pin to open drain, the GPIO Alternate
Function Select (GPIOAFSEL) register bits for the I2C clock and data pins should be set to 1 (see
examples in “Initialization and Configuration” on page 286).
GPIO Open Drain Select (GPIOODR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x50C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ODE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad Open Drain Enable
The ODE values are defined as follows:
Value Description
0 Open drain configuration is disabled.
1 Open drain configuration is enabled.
7:0 ODE R/W 0x00
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Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up
resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 306).
GPIO Pull-Up Select (GPIOPUR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x510
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PUE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Pad Weak Pull-Up Enable
A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n]
enables. The change is effective on the second clock cycle after the
write.
Note: The default reset value for the GPIOAFSEL, GPIOPUR, and
GPIODEN registers are 0x0000.0000 for all GPIO pins, with
the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
These five pins default to JTAG/SWD functionality. Because
of this, the default reset value of these registers for GPIO Port
B is 0x0000.0080 while the default reset value for Port C is
0x0000.000F.
7:0 PUE R/W -
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Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak
pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 305).
GPIO Pull-Down Select (GPIOPDR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x514
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PDE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Pad Weak Pull-Down Enable
A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n]
enables. The change is effective on the second clock cycle after the
write.
7:0 PDE R/W 0x00
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General-Purpose Input/Outputs (GPIOs)
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
The GPIOSLR register is the slew rate control register. Slew rate control is only available when
using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see
page 303).
GPIO Slew Rate Control Select (GPIOSLR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x518
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SRL
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Slew Rate Limit Enable (8-mA drive only)
The SRL values are defined as follows:
Value Description
0 Slew rate control disabled.
1 Slew rate control enabled.
7:0 SRL R/W 0x00
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Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
Note: Pins configured as digital inputs are Schmitt-triggered.
The GPIODEN register is the digital enable register. By default, with the exception of the GPIO
signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven
(tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not
allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or
alternate function), the corresponding GPIODEN bit must be set.
GPIO Digital Enable (GPIODEN)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x51C
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DEN
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Digital Enable
The DEN values are defined as follows:
Value Description
0 Digital functions disabled.
1 Digital functions enabled.
Note: The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
7:0 DEN R/W -
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Register 19: GPIO Lock (GPIOLOCK), offset 0x520
The GPIOLOCK register enables write access to the GPIOCR register (see page 310). Writing
0x1ACC.E551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value
to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns
the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses
are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses
are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000.
GPIO Lock (GPIOLOCK)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x520
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
GPIO Lock
A write of the value 0x1ACC.E551 unlocks the GPIO Commit (GPIOCR)
register for write access.
A write of any other value or a write to the GPIOCR register reapplies
the lock, preventing any register updates. A read of this register returns
the following values:
Value Description
0x0000.0001 locked
0x0000.0000 unlocked
31:0 LOCK R/W 0x0000.0001
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Register 20: GPIO Commit (GPIOCR), offset 0x524
The GPIOCR register is the commit register. The value of the GPIOCR register determines which
bits of the GPIOAFSEL register are committed when a write to the GPIOAFSEL register is performed.
If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit in the
GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the GPIOCR
register is a one, the data being written to the corresponding bit of the GPIOAFSEL register will be
committed to the register and will reflect the new value.
The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked.
Writes to the GPIOCR register are ignored if the GPIOLOCK register is locked.
Important: This register is designed to prevent accidental programming of the registers that control
connectivity to the JTAG/SWD debug hardware. By initializing the bits of the GPIOCR
register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only be converted
to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and the
corresponding registers.
Because this protection is currently only implemented on the JTAG/SWD pins on PB7
and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0.
These bits are hardwired to 0x1, ensuring that it is always possible to commit new
values to the GPIOAFSELregister bits of these other pins.
GPIO Commit (GPIOCR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x524
Type -, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CR
Type RO RO RO RO RO RO RO RO - - - - - - - -
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
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Bit/Field Name Type Reset Description
GPIO Commit
On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL
bit to be set to its alternate function.
Note: The default register type for the GPIOCR register is RO for
all GPIO pins with the exception of the five JTAG/SWD pins
(PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because
of this, the register type for GPIO Port B7 and GPIO Port
C[3:0] is R/W.
The default reset value for the GPIOCR register is
0x0000.00FF for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the
JTAG port is not accidentally programmed as a GPIO, these
five pins default to non-committable. Because of this, the
default reset value of GPIOCR for GPIO Port B is
0x0000.007F while the default reset value of GPIOCR for Port
C is 0x0000.00F0.
7:0 CR - -
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Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 4 (GPIOPeriphID4)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID4 RO 0x00 GPIO Peripheral ID Register[7:0]
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Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 5 (GPIOPeriphID5)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID5 RO 0x00 GPIO Peripheral ID Register[15:8]
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Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 6 (GPIOPeriphID6)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID6 RO 0x00 GPIO Peripheral ID Register[23:16]
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Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 7 (GPIOPeriphID7)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID7 RO 0x00 GPIO Peripheral ID Register[31:24]
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Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 0 (GPIOPeriphID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFE0
Type RO, reset 0x0000.0061
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID0 RO 0x61
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Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 1 (GPIOPeriphID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID1 RO 0x00
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Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 2 (GPIOPeriphID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID2 RO 0x18
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Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 3 (GPIOPeriphID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID3 RO 0x01
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Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 0 (GPIOPCellID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
7:0 CID0 RO 0x0D
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Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 1 (GPIOPCellID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
7:0 CID1 RO 0xF0
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Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 2 (GPIOPCellID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
7:0 CID2 RO 0x05
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Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 3 (GPIOPCellID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
7:0 CID3 RO 0xB1
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9 General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris® General-Purpose Timer Module (GPTM) contains four GPTM blocks (Timer0, Timer1,
Timer 2, and Timer 3). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA
and TimerB) that can be configured to operate independently as timers or event counters, or
configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
In addition, timers can be used to trigger analog-to-digital conversions (ADC). The ADC trigger
signals from all of the general-purpose timers are ORed together before reaching the ADC module,
so only one timer should be used to trigger ADC events.
The GPT Module is one timing resource available on the Stellaris microcontrollers. Other timer
resources include the System Timer (SysTick) (see 94) and the PWM timer in the PWM module
(see “PWM Timer” on page 593).
The General-Purpose Timers provide the following features:
■ Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters.
Each GPTM can be configured to operate independently:
– As a single 32-bit timer
– As one 32-bit Real-Time Clock (RTC) to event capture
– For Pulse Width Modulation (PWM)
– To trigger analog-to-digital conversions
■ 32-bit Timer modes
– Programmable one-shot timer
– Programmable periodic timer
– Real-Time Clock when using an external 32.768-KHz clock as the input
– User-enabled stalling when the controller asserts CPU Halt flag during debug
– ADC event trigger
■ 16-bit Timer modes
– General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only)
– Programmable one-shot timer
– Programmable periodic timer
– User-enabled stalling when the controller asserts CPU Halt flag during debug
– ADC event trigger
■ 16-bit Input Capture modes
– Input edge count capture
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– Input edge time capture
■ 16-bit PWM mode
– Simple PWM mode with software-programmable output inversion of the PWM signal
9.1 Block Diagram
Note: In Figure 9-1 on page 325, the specific CCP pins available depend on the Stellaris device.
See Table 9-1 on page 325 for the available CCPs.
Figure 9-1. GPTM Module Block Diagram
TA Comparator
TB Comparator
GPTMTBR
GPTMAR
Clock / Edge
Detect
RTC Divider
Clock / Edge
Detect
TimerA
Interrupt
TimerB
Interrupt
System
Clock
0x0000 (Down Counter Modes)
0x0000 (Down Counter Modes)
32 KHz or
Even CCP Pin
Odd CCP Pin
En
En
TimerA Control
GPTMTAPMR
GPTMTAILR
GPTMTAMATCHR
GPTMTAPR
GPTMTAMR
TimerB Control
GPTMTBPMR
GPTMTBILR
GPTMTBMATCHR
GPTMTBPR
GPTMTBMR
Interrupt / Config
GPTMCFG
GPTMRIS
GPTMICR
GPTMMIS
GPTMIMR
GPTMCTL
Table 9-1. Available CCP Pins
Timer 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin
Timer 0 TimerA CCP0 -
TimerB - CCP1
Timer 1 TimerA CCP2 -
TimerB - CCP3
Timer 2 TimerA CCP4 -
TimerB - CCP5
Timer 3 TimerA - -
TimerB - -
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9.2 Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit
load/initialization registers and their associated control functions. The exact functionality of each
GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 336),
the GPTM TimerA Mode (GPTMTAMR) register (see page 337), and the GPTM TimerB Mode
(GPTMTBMR) register (see page 339). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
9.2.1 GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters TimerA and TimerB are initialized to
0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 350) and the GPTM TimerB Interval Load (GPTMTBILR) register
(see page 351). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale
(GPTMTAPR) register (see page 354) and the GPTM TimerB Prescale (GPTMTBPR) register (see
page 355).
9.2.2 32-Bit Timer Operating Modes
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configuration.
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 350
■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 351
■ GPTM TimerA (GPTMTAR) register [15:0], see page 358
■ GPTM TimerB (GPTMTBR) register [15:0], see page 359
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
9.2.2.1 32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB
registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is
determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register
(see page 337), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register.
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When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 341), the
timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the
timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to
be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If
configured as a periodic timer, it continues counting.
In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches
the 0x000.0000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status
(GPTMRIS) register (see page 346), and holds it until it is cleared by writing the GPTM Interrupt
Clear (GPTMICR) register (see page 348). If the time-out interrupt is enabled in the GPTM Interrupt
Mask (GPTMIMR) register (see page 344), the GPTM also sets the TATOMIS bit in the GPTM Masked
Interrupt Status (GPTMMIS) register (see page 347). The ADC trigger is enabled by setting the
TAOTE bit in GPTMCTL.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TASTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
9.2.2.2 32-Bit Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is
loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA
Match (GPTMTAMATCHR) register (see page 352) by the controller.
The input clock on an even CCP input is required to be 32.768 KHz in RTC mode. The clock signal
is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter.
When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its
preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until
either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs,
the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTMIMR, the
GPTM also sets the RTCMIS bit in GPTMMIS and generates a controller interrupt. The status flags
are cleared by writing the RTCCINT bit in GPTMICR.
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if
the RTCEN bit is set in GPTMCTL.
9.2.3 16-Bit Timer Operating Modes
The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration
(GPTMCFG) register (see page 336). This section describes each of the GPTM 16-bit modes of
operation. TimerA and TimerB have identical modes, so a single description is given using an n to
reference both.
9.2.3.1 16-Bit One-Shot/Periodic Timer Mode
In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with
an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The
selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR)
register.
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When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from
its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from
GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops
counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it
continues counting.
In addition to reloading the count value, the timer generates interrupts and triggers when it reaches
the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is
cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTMIMR, the GPTM
also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. The ADC trigger is
enabled by setting the TnOTE bit in the GPTMCTL register.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
The following example shows a variety of configurations for a 16-bit free running timer while using
the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period).
Table 9-2. 16-Bit Timer With Prescaler Configurations
Prescale #Clock (T c)a Max Time Units
00000000 1 1.3107 mS
00000001 2 2.6214 mS
00000010 3 3.9322 mS
------------ -- -- --
11111101 254 332.9229 mS
11111110 255 334.2336 mS
11111111 256 335.5443 mS
a. Tc is the clock period.
9.2.3.2 16-Bit Input Edge Count Mode
Note: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
Note: The prescaler is not available in 16-Bit Input Edge Count mode.
In Edge Count mode, the timer is configured as a down-counter capable of capturing three types
of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit
of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined
by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match
(GPTMTnMATCHR) register is configured so that the difference between the value in the
GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that
must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count
matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the
GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked).
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The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM
automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached,
all further events are ignored until TnEN is re-enabled by software.
Figure 9-2 on page 329 shows how input edge count mode works. In this case, the timer start value
is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so that
four edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit after
the current count matches the value in the GPTMTnMATCHR register.
Figure 9-2. 16-Bit Input Edge Count Mode Example
Input Signal
Timer stops,
flags
asserted
Timer reload
Count on next cycle Ignored Ignored
0x000A
0x0006
0x0007
0x0008
0x0009
9.2.3.3 16-Bit Input Edge Time Mode
Note: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
Note: The prescaler is not available in 16-Bit Input Edge Time mode.
In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value
loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of
either rising or falling edges, but not both. The timer is placed into Edge Time mode by setting the
TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined
by the TnEVENT fields of the GPTMCTL register.
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture.
When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR
register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and
the CnEMIS bit, if the interrupt is not masked).
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the
GPTMTnILR register.
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Figure 9-3 on page 330 shows how input edge timing mode works. In the diagram, it is assumed that
the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture
rising edge events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR
register, and is held there until another rising edge is detected (at which point the new count value
is loaded into GPTMTnR).
Figure 9-3. 16-Bit Input Edge Time Mode Example
GPTMTnR=Y
Input Signal
Time
Count
GPTMTnR=X GPTMTnR=Z
Z
X
Y
0xFFFF
9.2.3.4 16-Bit PWM Mode
Note: The prescaler is not available in 16-Bit PWM mode.
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
down-counter with a start value (and thus period) defined by GPTMTnILR. In this mode, the PWM
frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM
mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from
GPTMTnILR and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL
register. No interrupts or status bits are asserted in PWM mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTM Timern Match
Register (GPTMTnMATCHR). Software has the capability of inverting the output PWM signal by
setting the TnPWML bit in the GPTMCTL register.
Figure 9-4 on page 331 shows how to generate an output PWM with a 1-ms period and a 66% duty
cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML
=1 configuration). For this example, the start value is GPTMTnIRL=0xC350 and the match value is
GPTMTnMATCHR=0x411A.
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Figure 9-4. 16-Bit PWM Mode Example
Output
Signal
Time
Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR
0xC350
0x411A
TnPWML = 0
TnPWML = 1
TnEN set
9.3 Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0,
TIMER1, TIMER2, and TIMER3 bits in the RCGC1 register.
This section shows module initialization and configuration examples for each of the supported timer
modes.
9.3.1 32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0.
3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR).
5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
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7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
In One-Shot mode, the timer stops counting after step 7 on page 332. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
9.3.2 32-Bit Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on an even CCP input. To
enable the RTC feature, follow these steps:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1.
3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR).
4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired.
5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
When the timer count equals the value in the GPTMTAMATCHR register, the GPTM asserts the
RTCRIS bit in the GPTMRIS register and continues counting until Timer A is disabled or a hardware
reset. The interrupt is cleared by writing the RTCCINT bit in the GPTMICR register.
9.3.3 16-Bit One-Shot/Periodic Timer Mode
A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4.
3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register:
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register
(GPTMTnPR).
5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR).
6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start
counting.
8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
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In One-Shot mode, the timer stops counting after step 8 on page 332. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
9.3.4 16-Bit Input Edge Count Mode
A timer is configured to Input Edge Count mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.
4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register.
7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.
9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM
Interrupt Clear (GPTMICR) register.
In Input Edge Count Mode, the timer stops after the desired number of edge events has been
detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 333
through step 9 on page 333.
9.3.5 16-Bit Input Edge Timing Mode
A timer is configured to Input Edge Timing mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3.
4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting.
8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM
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Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timern (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
9.3.6 16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field
of the GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
9.4 Register Map
Table 9-3 on page 334 lists the GPTM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that timer’s base address:
■ Timer0: 0x4003.0000
■ Timer1: 0x4003.1000
■ Timer2: 0x4003.2000
■ Timer3: 0x4003.3000
Note that the Timer module clock must be enabled before the registers can be programmed (see
page 216). There must be a delay of 3 system clocks after the Timer module clock is enabled before
any Timer module registers are accessed.
Table 9-3. Timers Register Map
See
Offset Name Type Reset Description page
0x000 GPTMCFG R/W 0x0000.0000 GPTM Configuration 336
0x004 GPTMTAMR R/W 0x0000.0000 GPTM TimerA Mode 337
0x008 GPTMTBMR R/W 0x0000.0000 GPTM TimerB Mode 339
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Table 9-3. Timers Register Map (continued)
See
Offset Name Type Reset Description page
0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 341
0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 344
0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 346
0x020 GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 347
0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 348
0x028 GPTMTAILR R/W 0xFFFF.FFFF GPTM TimerA Interval Load 350
0x02C GPTMTBILR R/W 0x0000.FFFF GPTM TimerB Interval Load 351
0x030 GPTMTAMATCHR R/W 0xFFFF.FFFF GPTM TimerA Match 352
0x034 GPTMTBMATCHR R/W 0x0000.FFFF GPTM TimerB Match 353
0x038 GPTMTAPR R/W 0x0000.0000 GPTM TimerA Prescale 354
0x03C GPTMTBPR R/W 0x0000.0000 GPTM TimerB Prescale 355
0x040 GPTMTAPMR R/W 0x0000.0000 GPTM TimerA Prescale Match 356
0x044 GPTMTBPMR R/W 0x0000.0000 GPTM TimerB Prescale Match 357
0x048 GPTMTAR RO 0xFFFF.FFFF GPTM TimerA 358
0x04C GPTMTBR RO 0x0000.FFFF GPTM TimerB 359
9.5 Register Descriptions
The remainder of this section lists and describes the GPTM registers, in numerical order by address
offset.
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Register 1: GPTM Configuration (GPTMCFG), offset 0x000
This register configures the global operation of the GPTM module. The value written to this register
determines whether the GPTM is in 32- or 16-bit mode.
GPTM Configuration (GPTMCFG)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPTMCFG
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
GPTM Configuration
The GPTMCFG values are defined as follows:
Value Description
0x0 32-bit timer configuration.
0x1 32-bit real-time clock (RTC) counter configuration.
0x2 Reserved
0x3 Reserved
16-bit timer configuration, function is controlled by bits 1:0 of
GPTMTAMR and GPTMTBMR.
0x4-0x7
2:0 GPTMCFG R/W 0x0
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Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.
GPTM TimerA Mode (GPTMTAMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TAAMS TACMR TAMR
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
GPTM TimerA Alternate Mode Select
The TAAMS values are defined as follows:
Value Description
0 Capture mode is enabled.
1 PWM mode is enabled.
Note: To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.
3 TAAMS R/W 0
GPTM TimerA Capture Mode
The TACMR values are defined as follows:
Value Description
0 Edge-Count mode
1 Edge-Time mode
2 TACMR R/W 0
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Bit/Field Name Type Reset Description
GPTM TimerA Mode
The TAMR values are defined as follows:
Value Description
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
The Timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register (16-or 32-bit).
In 16-bit timer configuration, TAMR controls the 16-bit timer modes for
TimerA.
In 32-bit timer configuration, this register controls the mode and the
contents of GPTMTBMR are ignored.
1:0 TAMR R/W 0x0
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Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to
0x2.
GPTM TimerB Mode (GPTMTBMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBAMS TBCMR TBMR
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
GPTM TimerB Alternate Mode Select
The TBAMS values are defined as follows:
Value Description
0 Capture mode is enabled.
1 PWM mode is enabled.
Note: To enable PWM mode, you must also clear the TBCMR
bit and set the TBMR field to 0x2.
3 TBAMS R/W 0
GPTM TimerB Capture Mode
The TBCMR values are defined as follows:
Value Description
0 Edge-Count mode
1 Edge-Time mode
2 TBCMR R/W 0
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Bit/Field Name Type Reset Description
GPTM TimerB Mode
The TBMR values are defined as follows:
Value Description
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
The timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
In 16-bit timer configuration, these bits control the 16-bit timer modes
for TimerB.
In 32-bit timer configuration, this register’s contents are ignored and
GPTMTAMR is used.
1:0 TBMR R/W 0x0
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Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBPWML TBOTE reserved TBEVENT TBSTALL TBEN reserved TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN
Type RO R/W R/W RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:15 reserved RO 0x00
GPTM TimerB PWM Output Level
The TBPWML values are defined as follows:
Value Description
0 Output is unaffected.
1 Output is inverted.
14 TBPWML R/W 0
GPTM TimerB Output Trigger Enable
The TBOTE values are defined as follows:
Value Description
0 The output TimerB ADC trigger is disabled.
1 The output TimerB ADC trigger is enabled.
In addition, the ADC must be enabled and the timer selected as a trigger
source with the EMn bit in the ADCEMUX register (see page 398).
13 TBOTE R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12 reserved RO 0
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Bit/Field Name Type Reset Description
GPTM TimerB Event Mode
The TBEVENT values are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
11:10 TBEVENT R/W 0x0
GPTM Timer B Stall Enable
The TBSTALL values are defined as follows:
Value Description
Timer B continues counting while the processor is halted by the
debugger.
0
Timer B freezes counting while the processor is halted by the
debugger.
1
If the processor is executing normally, the TBSTALL bit is ignored.
9 TBSTALL R/W 0
GPTM TimerB Enable
The TBEN values are defined as follows:
Value Description
0 TimerB is disabled.
TimerB is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
8 TBEN R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
GPTM TimerA PWM Output Level
The TAPWML values are defined as follows:
Value Description
0 Output is unaffected.
1 Output is inverted.
6 TAPWML R/W 0
GPTM TimerA Output Trigger Enable
The TAOTE values are defined as follows:
Value Description
0 The output TimerA ADC trigger is disabled.
1 The output TimerA ADC trigger is enabled.
In addition, the ADC must be enabled and the timer selected as a trigger
source with the EMn bit in the ADCEMUX register (see page 398).
5 TAOTE R/W 0
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Bit/Field Name Type Reset Description
GPTM RTC Enable
The RTCEN values are defined as follows:
Value Description
0 RTC counting is disabled.
1 RTC counting is enabled.
4 RTCEN R/W 0
GPTM TimerA Event Mode
The TAEVENT values are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
3:2 TAEVENT R/W 0x0
GPTM Timer A Stall Enable
The TASTALL values are defined as follows:
Value Description
Timer A continues counting while the processor is halted by the
debugger.
0
Timer A freezes counting while the processor is halted by the
debugger.
1
If the processor is executing normally, the TASTALL bit is ignored.
1 TASTALL R/W 0
GPTM TimerA Enable
The TAEN values are defined as follows:
Value Description
0 TimerA is disabled.
TimerA is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
0 TAEN R/W 0
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Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables
the interrupt, while writing a 0 disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x018
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBEIM CBMIM TBTOIM reserved RTCIM CAEIM CAMIM TATOIM
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Interrupt Mask
The CBEIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
10 CBEIM R/W 0
GPTM CaptureB Match Interrupt Mask
The CBMIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
9 CBMIM R/W 0
GPTM TimerB Time-Out Interrupt Mask
The TBTOIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
8 TBTOIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0
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Bit/Field Name Type Reset Description
GPTM RTC Interrupt Mask
The RTCIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
3 RTCIM R/W 0
GPTM CaptureA Event Interrupt Mask
The CAEIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
2 CAEIM R/W 0
GPTM CaptureA Match Interrupt Mask
The CAMIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
1 CAMIM R/W 0
GPTM TimerA Time-Out Interrupt Mask
The TATOIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
0 TATOIM R/W 0
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Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBERIS CBMRIS TBTORIS reserved RTCRIS CAERIS CAMRIS TATORIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
10 CBERIS RO 0
GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
9 CBMRIS RO 0
GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
8 TBTORIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x0
GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
3 RTCRIS RO 0
GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
2 CAERIS RO 0
GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
1 CAMRIS RO 0
GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
0 TATORIS RO 0
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Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x020
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBEMIS CBMMIS TBTOMIS reserved RTCMIS CAEMIS CAMMIS TATOMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Masked Interrupt
This is the CaptureB event interrupt status after masking.
10 CBEMIS RO 0
GPTM CaptureB Match Masked Interrupt
This is the CaptureB match interrupt status after masking.
9 CBMMIS RO 0
GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
8 TBTOMIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x0
GPTM RTC Masked Interrupt
This is the RTC event interrupt status after masking.
3 RTCMIS RO 0
GPTM CaptureA Event Masked Interrupt
This is the CaptureA event interrupt status after masking.
2 CAEMIS RO 0
GPTM CaptureA Match Masked Interrupt
This is the CaptureA match interrupt status after masking.
1 CAMMIS RO 0
GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
0 TATOMIS RO 0
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Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x024
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBECINT CBMCINT TBTOCINT reserved RTCCINT CAECINT CAMCINT TATOCINT
Type RO RO RO RO RO W1C W1C W1C RO RO RO RO W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Interrupt Clear
The CBECINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
10 CBECINT W1C 0
GPTM CaptureB Match Interrupt Clear
The CBMCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
9 CBMCINT W1C 0
GPTM TimerB Time-Out Interrupt Clear
The TBTOCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
8 TBTOCINT W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x0
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Bit/Field Name Type Reset Description
GPTM RTC Interrupt Clear
The RTCCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
3 RTCCINT W1C 0
GPTM CaptureA Event Interrupt Clear
The CAECINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
2 CAECINT W1C 0
GPTM CaptureA Match Interrupt Clear
The CAMCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
1 CAMCINT W1C 0
GPTM TimerA Time-Out Interrupt Clear
The TATOCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
0 TATOCINT W1C 0
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Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028
This register is used to load the starting count value into the timer. When GPTM is configured to
one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond
to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
GPTM TimerA Interval Load (GPTMTAILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x028
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAILRH
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAILRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
GPTM TimerA Interval Load Register High
When configured for 32-bit mode via the GPTMCFG register, the GPTM
TimerB Interval Load (GPTMTBILR) register loads this value on a
write. A read returns the current value of GPTMTBILR.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBILR.
31:16 TAILRH R/W 0xFFFF
GPTM TimerA Interval Load Register Low
For both 16- and 32-bit modes, writing this field loads the counter for
TimerA. A read returns the current value of GPTMTAILR.
15:0 TAILRL R/W 0xFFFF
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Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C
This register is used to load the starting count value into TimerB. When the GPTM is configured to
a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes.
GPTM TimerB Interval Load (GPTMTBILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBILRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
GPTM TimerB Interval Load Register
When the GPTM is not configured as a 32-bit timer, a write to this field
updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads
return the current value of GPTMTBILR.
15:0 TBILRL R/W 0xFFFF
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Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerA Match (GPTMTAMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x030
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMRH
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
GPTM TimerA Match Register High
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the upper half of
GPTMTAR, to determine match events.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBMATCHR.
31:16 TAMRH R/W 0xFFFF
GPTM TimerA Match Register Low
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the lower half of
GPTMTAR, to determine match events.
When configured for PWM mode, this value along with GPTMTAILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTAILR
minus this value.
15:0 TAMRL R/W 0xFFFF
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Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034
This register is used in 16-bit PWM and Input Edge Count modes.
GPTM TimerB Match (GPTMTBMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x034
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBMRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
GPTM TimerB Match Register Low
When configured for PWM mode, this value along with GPTMTBILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTBILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTBILR
minus this value.
15:0 TBMRL R/W 0xFFFF
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Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerA Prescale (GPTMTAPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TAPSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerA Prescale
The register loads this value on a write. A read returns the current value
of the register.
Refer to Table 9-2 on page 328 for more details and an example.
7:0 TAPSR R/W 0x00
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Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerB Prescale (GPTMTBPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x03C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBPSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerB Prescale
The register loads this value on a write. A read returns the current value
of this register.
Refer to Table 9-2 on page 328 for more details and an example.
7:0 TBPSR R/W 0x00
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Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040
This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerA Prescale Match (GPTMTAPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x040
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TAPSMR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerA Prescale Match
This value is used alongside GPTMTAMATCHR to detect timer match
events while using a prescaler.
7:0 TAPSMR R/W 0x00
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Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044
This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerB Prescale Match (GPTMTBPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x044
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBPSMR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerB Prescale Match
This value is used alongside GPTMTBMATCHR to detect timer match
events while using a prescaler.
7:0 TBPSMR R/W 0x00
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Register 17: GPTM TimerA (GPTMTAR), offset 0x048
This register shows the current value of the TimerA counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the number of edges that have occurred.
GPTM TimerA (GPTMTAR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x048
Type RO, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TARH
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TARL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
GPTM TimerA Register High
If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the
GPTMCFG is in a 16-bit mode, this is read as zero.
31:16 TARH RO 0xFFFF
GPTM TimerA Register Low
A read returns the current value of the GPTM TimerA Count Register,
except in Input Edge-Count mode, when it returns the number of edges
that have occurred.
15:0 TARL RO 0xFFFF
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Register 18: GPTM TimerB (GPTMTBR), offset 0x04C
This register shows the current value of the TimerB counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the number of edges that have occurred.
GPTM TimerB (GPTMTBR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x04C
Type RO, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBRL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
GPTM TimerB
A read returns the current value of the GPTM TimerB Count Register,
except in Input Edge-Count mode, when it returns the number of edges
that have occurred.
15:0 TBRL RO 0xFFFF
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10 Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
The Stellaris® Watchdog Timer module has the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
■ User-enabled stalling when the controller asserts the CPU Halt flag during debug
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
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10.1 Block Diagram
Figure 10-1. WDT Module Block Diagram
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
WDTRIS
WDTMIS
WDTLOCK
WDTTEST
WDTLOAD
WDTVALUE
Comparator
32-Bit Down
Counter
0x00000000
Interrupt
System Clock
Identification Registers
WDTPCellID0 WDTPeriphID0 WDTPeriphID4
WDTPCellID1 WDTPeriphID1 WDTPeriphID5
WDTPCellID2 WDTPeriphID2 WDTPeriphID6
WDTPCellID3 WDTPeriphID3 WDTPeriphID7
10.2 Functional Description
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the
Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written,
which prevents the timer configuration from being inadvertently altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
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Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) register.
The Watchdog module interrupt and reset generation can be enabled or disabled as required. When
the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its
last state.
10.3 Initialization and Configuration
To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register.
The Watchdog Timer is configured using the following sequence:
1. Load the WDTLOAD register with the desired timer load value.
2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.
3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register.
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write
a value of 0x1ACC.E551.
10.4 Register Map
Table 10-1 on page 362 lists the Watchdog registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000.
Table 10-1. Watchdog Timer Register Map
See
Offset Name Type Reset Description page
0x000 WDTLOAD R/W 0xFFFF.FFFF Watchdog Load 364
0x004 WDTVALUE RO 0xFFFF.FFFF Watchdog Value 365
0x008 WDTCTL R/W 0x0000.0000 Watchdog Control 366
0x00C WDTICR WO - Watchdog Interrupt Clear 367
0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 368
0x014 WDTMIS RO 0x0000.0000 Watchdog Masked Interrupt Status 369
0x418 WDTTEST R/W 0x0000.0000 Watchdog Test 370
0xC00 WDTLOCK R/W 0x0000.0000 Watchdog Lock 371
0xFD0 WDTPeriphID4 RO 0x0000.0000 Watchdog Peripheral Identification 4 372
0xFD4 WDTPeriphID5 RO 0x0000.0000 Watchdog Peripheral Identification 5 373
0xFD8 WDTPeriphID6 RO 0x0000.0000 Watchdog Peripheral Identification 6 374
0xFDC WDTPeriphID7 RO 0x0000.0000 Watchdog Peripheral Identification 7 375
0xFE0 WDTPeriphID0 RO 0x0000.0005 Watchdog Peripheral Identification 0 376
0xFE4 WDTPeriphID1 RO 0x0000.0018 Watchdog Peripheral Identification 1 377
0xFE8 WDTPeriphID2 RO 0x0000.0018 Watchdog Peripheral Identification 2 378
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Table 10-1. Watchdog Timer Register Map (continued)
See
Offset Name Type Reset Description page
0xFEC WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 379
0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 380
0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 381
0xFF8 WDTPCellID2 RO 0x0000.0005 Watchdog PrimeCell Identification 2 382
0xFFC WDTPCellID3 RO 0x0000.00B1 Watchdog PrimeCell Identification 3 383
10.5 Register Descriptions
The remainder of this section lists and describes the WDT registers, in numerical order by address
offset.
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Register 1: Watchdog Load (WDTLOAD), offset 0x000
This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the
value is immediately loaded and the counter restarts counting down from the new value. If the
WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated.
Watchdog Load (WDTLOAD)
Base 0x4000.0000
Offset 0x000
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTLoad
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTLoad
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
31:0 WDTLoad R/W 0xFFFF.FFFF Watchdog Load Value
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Register 2: Watchdog Value (WDTVALUE), offset 0x004
This register contains the current count value of the timer.
Watchdog Value (WDTVALUE)
Base 0x4000.0000
Offset 0x004
Type RO, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTValue
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTValue
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Watchdog Value
Current value of the 32-bit down counter.
31:0 WDTValue RO 0xFFFF.FFFF
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Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.
Watchdog Control (WDTCTL)
Base 0x4000.0000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RESEN INTEN
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Watchdog Reset Enable
The RESEN values are defined as follows:
Value Description
0 Disabled.
1 Enable the Watchdog module reset output.
1 RESEN R/W 0
Watchdog Interrupt Enable
The INTEN values are defined as follows:
Value Description
Interrupt event disabled (once this bit is set, it can only be
cleared by a hardware reset).
0
1 Interrupt event enabled. Once enabled, all writes are ignored.
0 INTEN R/W 0
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Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C
This register is the interrupt clear register. A write of any value to this register clears the Watchdog
interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is
indeterminate.
Watchdog Interrupt Clear (WDTICR)
Base 0x4000.0000
Offset 0x00C
Type WO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTIntClr
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTIntClr
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
31:0 WDTIntClr WO - Watchdog Interrupt Clear
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Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010
This register is the raw interrupt status register. Watchdog interrupt events can be monitored via
this register if the controller interrupt is masked.
Watchdog Raw Interrupt Status (WDTRIS)
Base 0x4000.0000
Offset 0x010
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WDTRIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Watchdog Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of WDTINTR.
0 WDTRIS RO 0
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Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.
Watchdog Masked Interrupt Status (WDTMIS)
Base 0x4000.0000
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WDTMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Watchdog Masked Interrupt Status
Gives the masked interrupt state (after masking) of the WDTINTR
interrupt.
0 WDTMIS RO 0
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Register 7: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
Watchdog Test (WDTTEST)
Base 0x4000.0000
Offset 0x418
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved STALL reserved
Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:9 reserved RO 0x00
Watchdog Stall Enable
When set to 1, if the Stellaris microcontroller is stopped with a debugger,
the watchdog timer stops counting. Once the microcontroller is restarted,
the watchdog timer resumes counting.
8 STALL R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0 reserved RO 0x00
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Register 8: Watchdog Lock (WDTLOCK), offset 0xC00
Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing
any other value to the WDTLOCK register re-enables the locked state for register writes to all the
other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value
written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns
0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)).
Watchdog Lock (WDTLOCK)
Base 0x4000.0000
Offset 0xC00
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTLock
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTLock
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Watchdog Lock
A write of the value 0x1ACC.E551 unlocks the watchdog registers for
write access. A write of any other value reapplies the lock, preventing
any register updates.
A read of this register returns the following values:
Value Description
0x0000.0001 Locked
0x0000.0000 Unlocked
31:0 WDTLock R/W 0x0000
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Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 4 (WDTPeriphID4)
Base 0x4000.0000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID4 RO 0x00 WDT Peripheral ID Register[7:0]
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Watchdog Timer
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset
0xFD4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 5 (WDTPeriphID5)
Base 0x4000.0000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID5 RO 0x00 WDT Peripheral ID Register[15:8]
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Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset
0xFD8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 6 (WDTPeriphID6)
Base 0x4000.0000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID6 RO 0x00 WDT Peripheral ID Register[23:16]
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Watchdog Timer
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset
0xFDC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 7 (WDTPeriphID7)
Base 0x4000.0000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID7 RO 0x00 WDT Peripheral ID Register[31:24]
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Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset
0xFE0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 0 (WDTPeriphID0)
Base 0x4000.0000
Offset 0xFE0
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID0 RO 0x05 Watchdog Peripheral ID Register[7:0]
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Watchdog Timer
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset
0xFE4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 1 (WDTPeriphID1)
Base 0x4000.0000
Offset 0xFE4
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID1 RO 0x18 Watchdog Peripheral ID Register[15:8]
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Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset
0xFE8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 2 (WDTPeriphID2)
Base 0x4000.0000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID2 RO 0x18 Watchdog Peripheral ID Register[23:16]
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Watchdog Timer
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset
0xFEC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 3 (WDTPeriphID3)
Base 0x4000.0000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID3 RO 0x01 Watchdog Peripheral ID Register[31:24]
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Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 0 (WDTPCellID0)
Base 0x4000.0000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID0 RO 0x0D Watchdog PrimeCell ID Register[7:0]
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Watchdog Timer
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 1 (WDTPCellID1)
Base 0x4000.0000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID1 RO 0xF0 Watchdog PrimeCell ID Register[15:8]
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Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 2 (WDTPCellID2)
Base 0x4000.0000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID2 RO 0x05 Watchdog PrimeCell ID Register[23:16]
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Watchdog Timer
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 3 (WDTPCellID3)
Base 0x4000.0000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID3 RO 0xB1 Watchdog PrimeCell ID Register[31:24]
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11 Analog-to-Digital Converter (ADC)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The Stellaris® ADC module features 10-bit conversion resolution and supports four input channels,
plus an internal temperature sensor. The ADC module contains four programmable sequencer which
allows for the sampling of multiple analog input sources without controller intervention. Each sample
sequence provides flexible programming with fully configurable input source, trigger events, interrupt
generation, and sequence priority.
The Stellaris ADC module provides the following features:
■ Four analog input channels
■ Single-ended and differential-input configurations
■ On-chip internal temperature sensor
■ Sample rate of one million samples/second
■ Flexible, configurable analog-to-digital conversion
■ Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
■ Flexible trigger control
– Controller (software)
– Timers
– Analog Comparators
– PWM
– GPIO
■ Hardware averaging of up to 64 samples for improved accuracy
■ Converter uses an internal 3-V reference
■ Power and ground for the analog circuitry is separate from the digital power and ground
11.1 Block Diagram
Figure 11-1 on page 385 provides details on the internal configuration of the ADC controls and data
registers.
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Figure 11-1. ADC Module Block Diagram
Analog-to-Digital
Converter
ADCSSFSTAT0
ADCSSCTL0
ADCSSMUX0
Sample
Sequencer 0
ADCSSFSTAT1
ADCSSCTL1
ADCSSMUX1
Sample
Sequencer 1
ADCSSFSTAT2
ADCSSCTL2
ADCSSMUX2
Sample
Sequencer 2
ADCSSFSTAT3
ADCSSCTL3
ADCSSMUX3
Sample
Sequencer 3
ADCUSTAT
ADCOSTAT
ADCACTSS
Control/Status
ADCSSPRI
ADCISC
ADCRIS
ADCIM
Interrupt Control
Analog Inputs
SS0 Interrupt
SS1 Interrupt
SS2 Interrupt
SS3 Interrupt
ADCEMUX
ADCPSSI
Trigger Events
SS0
SS1
SS2
SS3
Comparator
GPIO (PB4)
Timer
PWM
Comparator
GPIO (PB4)
Timer
PWM
Comparator
GPIO (PB4)
Timer
PWM
Comparator
GPIO (PB4)
Timer
PWM
ADCSSFIFO0
ADCSSFIFO1
ADCSSFIFO2
ADCSSFIFO3
FIFO Block
Hardware Averager
ADCSAC
11.2 Functional Description
The Stellaris ADC collects sample data by using a programmable sequence-based approach instead
of the traditional single or double-sampling approaches found on many ADC modules. Each sample
sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the ADC
to collect data from multiple input sources without having to be re-configured or serviced by the
controller. The programming of each sample in the sample sequence includes parameters such as
the input source and mode (differential versus single-ended input), interrupt generation on sample
completion, and the indicator for the last sample in the sequence.
11.2.1 Sample Sequencers
The sampling control and data capture is handled by the sample sequencers. All of the sequencers
are identical in implementation except for the number of samples that can be captured and the depth
of the FIFO. Table 11-1 on page 385 shows the maximum number of samples that each sequencer
can capture and its corresponding FIFO depth. In this implementation, each FIFO entry is a 32-bit
word, with the lower 10 bits containing the conversion result.
Table 11-1. Samples and FIFO Depth of Sequencers
Sequencer Number of Samples Depth of FIFO
SS3 1 1
SS2 4 4
SS1 4 4
SS0 8 8
For a given sample sequence, each sample is defined by two 4-bit nibbles in the ADC Sample
Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control
(ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn
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nibbles select the input pin, while the ADCSSCTLn nibbles contain the sample control bits
corresponding to parameters such as temperature sensor selection, interrupt enable, end of
sequence, and differential input mode. Sample sequencers are enabled by setting the respective
ASENn bit in the ADC Active Sample Sequencer (ADCACTSS) register, and should be configured
before being enabled.
When configuring a sample sequence, multiple uses of the same input pin within the same sequence
is allowed. In the ADCSSCTLn register, the IEn bits can be set for any combination of samples,
allowing interrupts to be generated after every sample in the sequence if necessary. Also, the END
bit can be set at any point within a sample sequence. For example, if Sequencer 0 is used, the END
bit can be set in the nibble associated with the fifth sample, allowing Sequencer 0 to complete
execution of the sample sequence after the fifth sample.
After a sample sequence completes execution, the result data can be retrieved from the ADC
Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers
that read a single address to "pop" result data. For software debug purposes, the positions of the
FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn)
registers along with FULL and EMPTY status flags. Overflow and underflow conditions are monitored
using the ADCOSTAT and ADCUSTAT registers.
11.2.2 Module Control
Outside of the sample sequencers, the remainder of the control logic is responsible for tasks such
as:
■ Interrupt generation
■ Sequence prioritization
■ Trigger configuration
Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider
is configured automatically by hardware when the system XTAL is selected. The automatic clock
divider configuration targets 16.667 MHz operation for all Stellaris devices.
11.2.2.1 Interrupts
The register configurations of the sample sequencers dictate which events generate raw interrupts,
but do not have control over whether the interrupt is actually sent to the interrupt controller. The
ADC module's interrupt signals are controlled by the state of the MASK bits in the ADC Interrupt
Mask (ADCIM) register. Interrupt status can be viewed at two locations: the ADC Raw Interrupt
Status (ADCRIS) register, which shows the raw status of the various interrupt signals, and the ADC
Interrupt Status and Clear (ADCISC) register, which shows active interrupts that are enabled by
the ADCIM register. Sequencer interrupts are cleared by writing a 1 to the corresponding IN bit in
ADCISC.
11.2.2.2 Prioritization
When sampling events (triggers) happen concurrently, they are prioritized for processing by the
values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in
the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active sample
sequencer units with the same priority do not provide consistent results, so software must ensure
that all active sample sequencer units have a unique priority value.
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11.2.2.3 Sampling Events
Sample triggering for each sample sequencer is defined in the ADC Event Multiplexer Select
(ADCEMUX) register. The external peripheral triggering sources vary by Stellaris family member,
but all devices share the "Controller" and "Always" triggers. Software can initiate sampling by setting
the SSx bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register.
Care must be taken when using the "Always" trigger. If a sequence's priority is too high, it is possible
to starve other lower priority sequences.
11.2.3 Hardware Sample Averaging Circuit
Higher precision results can be generated using the hardware averaging circuit, however, the
improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged
to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the
number of samples in the averaging calculation. For example, if the averaging circuit is configured
to average 16 samples, the throughput is decreased by a factor of 16.
By default the averaging circuit is off and all data from the converter passes through to the sequencer
FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC)
register (see page 406). There is a single averaging circuit and all input channels receive the same
amount of averaging whether they are single-ended or differential.
11.2.4 Analog-to-Digital Converter
The converter itself generates a 10-bit output value for selected analog input. Special analog pads
are used to minimize the distortion on the input. An internal 3 V reference is used by the converter
resulting in sample values ranging from 0x000 at 0 V input to 0x3FF at 3 V input when in single-ended
input mode.
11.2.5 Differential Sampling
In addition to traditional single-ended sampling, the ADC module supports differential sampling of
two analog input channels. To enable differential sampling, software must set the Dn bit in the
ADCSSCTL0n register in a step's configuration nibble.
When a sequence step is configured for differential sampling, its corresponding value in the
ADCSSMUXn register must be set to one of the four differential pairs, numbered 0-3. Differential
pair 0 samples analog inputs 0 and 1; differential pair 1 samples analog inputs 2 and 3; and so on
(see Table 11-2 on page 387). The ADC does not support other differential pairings such as analog
input 0 with analog input 3. The number of differential pairs supported is dependent on the number
of analog inputs (see Table 11-2 on page 387).
Table 11-2. Differential Sampling Pairs
Differential Pair Analog Inputs
0 0 and 1
1 2 and 3
The voltage sampled in differential mode is the difference between the odd and even channels:
ΔV (differential voltage) = VIN_EVEN (even channels) – VIN_ODD (odd channels), therefore:
■ If ΔV = 0, then the conversion result = 0x1FF
■ If ΔV > 0, then the conversion result > 0x1FF (range is 0x1FF–0x3FF)
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■ If ΔV < 0, then the conversion result < 0x1FF (range is 0–0x1FF)
The differential pairs assign polarities to the analog inputs: the even-numbered input is always
positive, and the odd-numbered input is always negative. In order for a valid conversion result to
appear, the negative input must be in the range of ± 1.5 V of the positive input. If an analog input
is greater than 3 V or less than 0 V (the valid range for analog inputs), the input voltage is clipped,
meaning it appears as either 3 V or 0 V, respectively, to the ADC.
Figure 11-2 on page 388 shows an example of the negative input centered at 1.5 V. In this
configuration, the differential range spans from -1.5 V to 1.5 V. Figure 11-3 on page 389 shows an
example where the negative input is centered at -0.75 V, meaning inputs on the positive input
saturate past a differential voltage of -0.75 V since the input voltage is less than 0 V. Figure
11-4 on page 389 shows an example of the negative input centered at 2.25 V, where inputs on the
positive channel saturate past a differential voltage of 0.75 V since the input voltage would be greater
than 3 V.
Figure 11-2. Differential Sampling Range, VIN_ODD = 1.5 V
0 V 1.5 V 3.0 V
-1.5 V 0 V 1.5 V
VIN_EVEN
DV
VIN_ODD = 1.5 V
0x3FF
0x1FF
ADC Conversion Result
- Input Saturation
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Figure 11-3. Differential Sampling Range, VIN_ODD = 0.75 V
ADC Conversion Result
0x3FF
0x1FF
0x0FF
0 V +0.75 V +2.25 V VIN_EVEN
-1.5 V -0.75 V +1.5 V DV
- Input Saturation
Figure 11-4. Differential Sampling Range, VIN_ODD = 2.25 V
ADC Conversion Result
0x3FF
0x2FF
0x1FF
0.75 V 2.25 V 3.0 V VIN_EVEN
-1.5 V 0.75 V 1.5 V DV
- Input Saturation
11.2.6 Test Modes
There is a user-available test mode that allows for loopback operation within the digital portion of
the ADC module. This can be useful for debugging software without having to provide actual analog
stimulus. This mode is available through the ADC Test Mode Loopback (ADCTMLB) register (see
page 419).
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11.2.7 Internal Temperature Sensor
The temperature sensor serves two primary purposes: 1) to notify the system that internal temperature
is too high or low for reliable operation, and 2) to provide temperature measurements for calibration
of the Hibernate module RTC trim value.
The temperature sensor does not have a separate enable, since it also contains the bandgap
reference and must always be enabled. The reference is supplied to other analog modules; not just
the ADC.
The internal temperature sensor provides an analog temperature reading as well as a reference
voltage. The voltage at the output terminal SENSO is given by the following equation:
SENSO = 2.7 - ((T + 55) / 75)
This relation is shown in Figure 11-5 on page 390.
Figure 11-5. Internal Temperature Sensor Characteristic
11.3 Initialization and Configuration
In order for the ADC module to be used, the PLL must be enabled and using a supported crystal
frequency (see the RCC register). Using unsupported frequencies can cause faulty operation in the
ADC module.
11.3.1 Module Initialization
Initialization of the ADC module is a simple process with very few steps. The main steps include
enabling the clock to the ADC and reconfiguring the sample sequencer priorities (if needed).
The initialization sequence for the ADC is as follows:
1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC0 register (see page 210).
2. If required by the application, reconfigure the sample sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority, and Sample
Sequencer 3 as the lowest priority.
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11.3.2 Sample Sequencer Configuration
Configuration of the sample sequencers is slightly more complex than the module initialization since
each sample sequence is completely programmable.
The configuration for each sample sequencer should be as follows:
1. Ensure that the sample sequencer is disabled by writing a 0 to the corresponding ASENn bit in
the ADCACTSS register. Programming of the sample sequencers is allowed without having
them enabled. Disabling the sequencer during programming prevents erroneous execution if a
trigger event were to occur during the configuration process.
2. Configure the trigger event for the sample sequencer in the ADCEMUX register.
3. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn register.
4. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register.
6. Enable the sample sequencer logic by writing a 1 to the corresponding ASENn bit in the
ADCACTSS register.
11.4 Register Map
Table 11-3 on page 391 lists the ADC registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the ADC base address of 0x4003.8000.
Note that the ADC module clock must be enabled before the registers can be programmed (see
page 210). There must be a delay of 3 system clocks after the ADC module clock is enabled before
any ADC module registers are accessed.
Table 11-3. ADC Register Map
See
Offset Name Type Reset Description page
0x000 ADCACTSS R/W 0x0000.0000 ADC Active Sample Sequencer 393
0x004 ADCRIS RO 0x0000.0000 ADC Raw Interrupt Status 394
0x008 ADCIM R/W 0x0000.0000 ADC Interrupt Mask 395
0x00C ADCISC R/W1C 0x0000.0000 ADC Interrupt Status and Clear 396
0x010 ADCOSTAT R/W1C 0x0000.0000 ADC Overflow Status 397
0x014 ADCEMUX R/W 0x0000.0000 ADC Event Multiplexer Select 398
0x018 ADCUSTAT R/W1C 0x0000.0000 ADC Underflow Status 402
0x020 ADCSSPRI R/W 0x0000.3210 ADC Sample Sequencer Priority 403
0x028 ADCPSSI WO - ADC Processor Sample Sequence Initiate 405
0x030 ADCSAC R/W 0x0000.0000 ADC Sample Averaging Control 406
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Table 11-3. ADC Register Map (continued)
See
Offset Name Type Reset Description page
0x040 ADCSSMUX0 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 0 407
0x044 ADCSSCTL0 R/W 0x0000.0000 ADC Sample Sequence Control 0 409
0x048 ADCSSFIFO0 RO - ADC Sample Sequence Result FIFO 0 412
0x04C ADCSSFSTAT0 RO 0x0000.0100 ADC Sample Sequence FIFO 0 Status 413
0x060 ADCSSMUX1 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 1 414
0x064 ADCSSCTL1 R/W 0x0000.0000 ADC Sample Sequence Control 1 415
0x068 ADCSSFIFO1 RO - ADC Sample Sequence Result FIFO 1 412
0x06C ADCSSFSTAT1 RO 0x0000.0100 ADC Sample Sequence FIFO 1 Status 413
0x080 ADCSSMUX2 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 2 414
0x084 ADCSSCTL2 R/W 0x0000.0000 ADC Sample Sequence Control 2 415
0x088 ADCSSFIFO2 RO - ADC Sample Sequence Result FIFO 2 412
0x08C ADCSSFSTAT2 RO 0x0000.0100 ADC Sample Sequence FIFO 2 Status 413
0x0A0 ADCSSMUX3 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 3 417
0x0A4 ADCSSCTL3 R/W 0x0000.0002 ADC Sample Sequence Control 3 418
0x0A8 ADCSSFIFO3 RO - ADC Sample Sequence Result FIFO 3 412
0x0AC ADCSSFSTAT3 RO 0x0000.0100 ADC Sample Sequence FIFO 3 Status 413
0x100 ADCTMLB R/W 0x0000.0000 ADC Test Mode Loopback 419
11.5 Register Descriptions
The remainder of this section lists and describes the ADC registers, in numerical order by address
offset.
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Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000
This register controls the activation of the sample sequencers. Each sample sequencer can be
enabled or disabled independently.
ADC Active Sample Sequencer (ADCACTSS)
Base 0x4003.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ASEN3 ASEN2 ASEN1 ASEN0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x0000.000
ADC SS3 Enable
Specifies whether Sample Sequencer 3 is enabled. If set, the sample
sequence logic for Sequencer 3 is active. Otherwise, the sequencer is
inactive.
3 ASEN3 R/W 0
ADC SS2 Enable
Specifies whether Sample Sequencer 2 is enabled. If set, the sample
sequence logic for Sequencer 2 is active. Otherwise, the sequencer is
inactive.
2 ASEN2 R/W 0
ADC SS1 Enable
Specifies whether Sample Sequencer 1 is enabled. If set, the sample
sequence logic for Sequencer 1 is active. Otherwise, the sequencer is
inactive.
1 ASEN1 R/W 0
ADC SS0 Enable
Specifies whether Sample Sequencer 0 is enabled. If set, the sample
sequence logic for Sequencer 0 is active. Otherwise, the sequencer is
inactive.
0 ASEN0 R/W 0
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Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each sample sequencer. These bits may
be polled by software to look for interrupt conditions without having to generate controller interrupts.
ADC Raw Interrupt Status (ADCRIS)
Base 0x4003.8000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved INR3 INR2 INR1 INR0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000
SS3 Raw Interrupt Status
This bit is set by hardware when a sample with its respective
ADCSSCTL3 IE bit has completed conversion. This bit is cleared by
setting the IN3 bit in the ADCISC register.
3 INR3 RO 0
SS2 Raw Interrupt Status
This bit is set by hardware when a sample with its respective
ADCSSCTL2 IE bit has completed conversion. This bit is cleared by
setting the IN2 bit in the ADCISC register.
2 INR2 RO 0
SS1 Raw Interrupt Status
This bit is set by hardware when a sample with its respective
ADCSSCTL1 IE bit has completed conversion. This bit is cleared by
setting the IN1 bit in the ADCISC register.
1 INR1 RO 0
SS0 Raw Interrupt Status
This bit is set by hardware when a sample with its respective
ADCSSCTL0 IE bit has completed conversion. This bit is cleared by
setting the IN30 bit in the ADCISC register.
0 INR0 RO 0
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Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the sample sequencer raw interrupt signals are promoted to controller
interrupts. Each raw interrupt signal can be masked independently.
ADC Interrupt Mask (ADCIM)
Base 0x4003.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MASK3 MASK2 MASK1 MASK0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000
SS3 Interrupt Mask
When set, this bit allows the raw interrupt signal from Sample Sequencer
3 (ADCRIS register INR3 bit) to be promoted to a controller interrupt.
When clear, the status of Sample Sequencer 3 does not affect the SS3
interrupt status.
3 MASK3 R/W 0
SS2 Interrupt Mask
When set, this bit allows the raw interrupt signal from Sample Sequencer
2 (ADCRIS register INR2 bit) to be promoted to a controller interrupt.
When clear, the status of Sample Sequencer 2 does not affect the SS2
interrupt status.
2 MASK2 R/W 0
SS1 Interrupt Mask
When set, this bit allows the raw interrupt signal from Sample Sequencer
1 (ADCRIS register INR1 bit) to be promoted to a controller interrupt.
When clear, the status of Sample Sequencer 1 does not affect the SS1
interrupt status.
1 MASK1 R/W 0
SS0 Interrupt Mask
When set, this bit allows the raw interrupt signal from Sample Sequencer
0 (ADCRIS register INR0 bit) to be promoted to a controller interrupt.
When clear, the status of Sample Sequencer 0 does not affect the SS0
interrupt status.
0 MASK0 R/W 0
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Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C
This register provides the mechanism for clearing sample sequence interrupt conditions and shows
the status of controller interrupts generated by the sample sequencers. When read, each bit field
is the logical AND of the respective INR and MASK bits. Sample sequence nterrupts are cleared by
setting the corresponding bit position. If software is polling the ADCRIS instead of generating
interrupts, the sample sequence INR bits are still cleared via the ADCISC register, even if the IN
bit is not set.
ADC Interrupt Status and Clear (ADCISC)
Base 0x4003.8000
Offset 0x00C
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN3 IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x000
SS3 Interrupt Status and Clear
This bit is set when both the INR3 bit in the ADCRIS register and the
MASK3 bit in the ADCIM register are set, providing a level-based interrupt
to the controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR3
bit.
3 IN3 R/W1C 0
SS2 Interrupt Status and Clear
This bit is set when both the INR2 bit in the ADCRIS register and the
MASK2 bit in the ADCIM register are set, providing a level-based interrupt
to the controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR2
bit.
2 IN2 R/W1C 0
SS1 Interrupt Status and Clear
This bit is set when both the INR1 bit in the ADCRIS register and the
MASK1 bit in the ADCIM register are set, providing a level-based interrupt
to the controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR1
bit.
1 IN1 R/W1C 0
SS0 Interrupt Status and Clear
This bit is set when both the INR0 bit in the ADCRIS register and the
MASK0 bit in the ADCIM register are set, providing a level-based interrupt
to the controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INR0
bit.
0 IN0 R/W1C 0
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Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010
This register indicates overflow conditions in the sample sequencer FIFOs. Once the overflow
condition has been handled by software, the condition can be cleared by writing a 1 to the
corresponding bit position.
ADC Overflow Status (ADCOSTAT)
Base 0x4003.8000
Offset 0x010
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OV3 OV2 OV1 OV0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x0000.000
SS3 FIFO Overflow
When set, this bit specifies that the FIFO for Sample Sequencer 3 has
hit an overflow condition where the FIFO is full and a write was
requested. When an overflow is detected, the most recent write is
dropped.
This bit is cleared by writing a 1.
3 OV3 R/W1C 0
SS2 FIFO Overflow
When set, this bit specifies that the FIFO for Sample Sequencer 2 has
hit an overflow condition where the FIFO is full and a write was
requested. When an overflow is detected, the most recent write is
dropped.
This bit is cleared by writing a 1.
2 OV2 R/W1C 0
SS1 FIFO Overflow
When set, this bit specifies that the FIFO for Sample Sequencer 1 has
hit an overflow condition where the FIFO is full and a write was
requested. When an overflow is detected, the most recent write is
dropped.
This bit is cleared by writing a 1.
1 OV1 R/W1C 0
SS0 FIFO Overflow
When set, this bit specifies that the FIFO for Sample Sequencer 0 has
hit an overflow condition where the FIFO is full and a write was
requested. When an overflow is detected, the most recent write is
dropped.
This bit is cleared by writing a 1.
0 OV0 R/W1C 0
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Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014
The ADCEMUX selects the event (trigger) that initiates sampling for each sample sequencer. Each
sample sequencer can be configured with a unique trigger source.
ADC Event Multiplexer Select (ADCEMUX)
Base 0x4003.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM3 EM2 EM1 EM0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0
SS3 Trigger Select
This field selects the trigger source for Sample Sequencer 3.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
Timer
In addition, the trigger must be enabled with the TnOTE bit in
the GPTMCTL register (see page 341).
0x5
PWM0
The PWM module 0 trigger can be configured with the PWM0
Interrupt and Trigger Enable (PWM0INTEN) register, see
page 611.
0x6
PWM1
The PWM module 1 trigger can be configured with the
PWM1INTEN register, see page 611.
0x7
PWM2
The PWM module 2 trigger can be configured with the
PWM2INTEN register, see page 611.
0x8
0x9-0xE reserved
0xF Always (continuously sample)
15:12 EM3 R/W 0x0
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Bit/Field Name Type Reset Description
SS2 Trigger Select
This field selects the trigger source for Sample Sequencer 2.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
Timer
In addition, the trigger must be enabled with the TnOTE bit in
the GPTMCTL register (see page 341).
0x5
PWM0
The PWM module 0 trigger can be configured with the PWM0
Interrupt and Trigger Enable (PWM0INTEN) register, see
page 611.
0x6
PWM1
The PWM module 1 trigger can be configured with the
PWM1INTEN register, see page 611.
0x7
PWM2
The PWM module 2 trigger can be configured with the
PWM2INTEN register, see page 611.
0x8
0x9-0xE reserved
0xF Always (continuously sample)
11:8 EM2 R/W 0x0
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Bit/Field Name Type Reset Description
SS1 Trigger Select
This field selects the trigger source for Sample Sequencer 1.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
Timer
In addition, the trigger must be enabled with the TnOTE bit in
the GPTMCTL register (see page 341).
0x5
PWM0
The PWM module 0 trigger can be configured with the PWM0
Interrupt and Trigger Enable (PWM0INTEN) register, see
page 611.
0x6
PWM1
The PWM module 1 trigger can be configured with the
PWM1INTEN register, see page 611.
0x7
PWM2
The PWM module 2 trigger can be configured with the
PWM2INTEN register, see page 611.
0x8
0x9-0xE reserved
0xF Always (continuously sample)
7:4 EM1 R/W 0x0
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Bit/Field Name Type Reset Description
SS0 Trigger Select
This field selects the trigger source for Sample Sequencer 0.
The valid configurations for this field are:
Value Event
0x0 Controller (default)
0x1 Analog Comparator 0
0x2 Analog Comparator 1
0x3 Analog Comparator 2
0x4 External (GPIO PB4)
Timer
In addition, the trigger must be enabled with the TnOTE bit in
the GPTMCTL register (see page 341).
0x5
PWM0
The PWM module 0 trigger can be configured with the PWM0
Interrupt and Trigger Enable (PWM0INTEN) register, see
page 611.
0x6
PWM1
The PWM module 1 trigger can be configured with the
PWM1INTEN register, see page 611.
0x7
PWM2
The PWM module 2 trigger can be configured with the
PWM2INTEN register, see page 611.
0x8
0x9-0xE reserved
0xF Always (continuously sample)
3:0 EM0 R/W 0x0
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Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018
This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding
underflow condition is cleared by writing a 1 to the relevant bit position.
ADC Underflow Status (ADCUSTAT)
Base 0x4003.8000
Offset 0x018
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved UV3 UV2 UV1 UV0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x0000.000
SS3 FIFO Underflow
When set, this bit specifies that the FIFO for Sample Sequencer 3 has
hit an underflow condition where the FIFO is empty and a read was
requested. The problematic read does not move the FIFO pointers, and
0s are returned.
This bit is cleared by writing a 1.
3 UV3 R/W1C 0
SS2 FIFO Underflow
When set, this bit specifies that the FIFO for Sample Sequencer 2 has
hit an underflow condition where the FIFO is empty and a read was
requested. The problematic read does not move the FIFO pointers, and
0s are returned.
This bit is cleared by writing a 1.
2 UV2 R/W1C 0
SS1 FIFO Underflow
When set, this bit specifies that the FIFO for Sample Sequencer 1 has
hit an underflow condition where the FIFO is empty and a read was
requested. The problematic read does not move the FIFO pointers, and
0s are returned.
This bit is cleared by writing a 1.
1 UV1 R/W1C 0
SS0 FIFO Underflow
When set, this bit specifies that the FIFO for Sample Sequencer 0 has
hit an underflow condition where the FIFO is empty and a read was
requested. The problematic read does not move the FIFO pointers, and
0s are returned.
This bit is cleared by writing a 1.
0 UV0 R/W1C 0
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Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020
This register sets the priority for each of the sample sequencers. Out of reset, Sequencer 0 has the
highest priority, and Sequencer 3 has the lowest priority. When reconfiguring sequence priorities,
each sequence must have a unique priority for the ADC to operate properly.
ADC Sample Sequencer Priority (ADCSSPRI)
Base 0x4003.8000
Offset 0x020
Type R/W, reset 0x0000.3210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SS3 reserved SS2 reserved SS1 reserved SS0
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x0000.0
SS3 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 3. A priority encoding of 0 is highest
and 3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
13:12 SS3 R/W 0x3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0x0
SS2 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 2. A priority encoding of 0 is highest
and 3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
9:8 SS2 R/W 0x2
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0x0
SS1 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 1. A priority encoding of 0 is highest
and 3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
5:4 SS1 R/W 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0x0
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Bit/Field Name Type Reset Description
SS0 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 0. A priority encoding of 0 is highest
and 3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
1:0 SS0 R/W 0x0
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Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028
This register provides a mechanism for application software to initiate sampling in the sample
sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.
ADC Processor Sample Sequence Initiate (ADCPSSI)
Base 0x4003.8000
Offset 0x028
Type WO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SS3 SS2 SS1 SS0
Type RO RO RO RO RO RO RO RO RO RO RO RO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0
SS3 Initiate
When set, this bit triggers sampling on Sample Sequencer 3 if the
sequencer is enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.
3 SS3 WO -
SS2 Initiate
When set, this bit triggers sampling on Sample Sequencer 2 if the
sequencer is enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.
2 SS2 WO -
SS1 Initiate
When set, this bit triggers sampling on Sample Sequencer 1 if the
sequencer is enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.
1 SS1 WO -
SS0 Initiate
When set, this bit triggers sampling on Sample Sequencer 0 if the
sequencer is enabled in the ADCACTSS register.
Only a write by software is valid; a read of this register returns no
meaningful data.
0 SS0 WO -
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Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030
This register controls the amount of hardware averaging applied to conversion results. The final
conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified
ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6,
then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An
AVG = 7 provides unpredictable results.
ADC Sample Averaging Control (ADCSAC)
Base 0x4003.8000
Offset 0x030
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved AVG
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x0000.000
Hardware Averaging Control
Specifies the amount of hardware averaging that will be applied to ADC
samples. The AVG field can be any value between 0 and 6. Entering a
value of 7 creates unpredictable results.
Value Description
0x0 No hardware oversampling
0x1 2x hardware oversampling
0x2 4x hardware oversampling
0x3 8x hardware oversampling
0x4 16x hardware oversampling
0x5 32x hardware oversampling
0x6 64x hardware oversampling
0x7 Reserved
2:0 AVG R/W 0x0
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Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0),
offset 0x040
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 0. This register is 32 bits wide and contains information for eight possible
samples.
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0)
Base 0x4003.8000
Offset 0x040
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved MUX7 reserved MUX6 reserved MUX5 reserved MUX4
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:30 reserved RO 0
8th Sample Input Select
The MUX7 field is used during the eighth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion. The value set here indicates
the corresponding pin, for example, a value of 1 indicates the input is
ADC1.
29:28 MUX7 R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:26 reserved RO 0
7th Sample Input Select
The MUX6 field is used during the seventh sample of a sequence
executed with the sample sequencer. It specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
25:24 MUX6 R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:22 reserved RO 0
6th Sample Input Select
The MUX5 field is used during the sixth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
21:20 MUX5 R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:18 reserved RO 0
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Bit/Field Name Type Reset Description
5th Sample Input Select
The MUX4 field is used during the fifth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
17:16 MUX4 R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:14 reserved RO 0
4th Sample Input Select
The MUX3 field is used during the fourth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
13:12 MUX3 R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0
3rd Sample Input Select
The MUX72 field is used during the third sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
9:8 MUX2 R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0
2nd Sample Input Select
The MUX1 field is used during the second sample of a sequence
executed with the sample sequencer. It specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
5:4 MUX1 R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
1st Sample Input Select
The MUX0 field is used during the first sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
1:0 MUX0 R/W 0x0
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Analog-to-Digital Converter (ADC)
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044
This register contains the configuration information for each sample for a sequence executed with
a sample sequencer. When configuring a sample sequence, the END bit must be set at some point,
whether it be after the first sample, last sample, or any sample in between. This register is 32-bits
wide and contains information for eight possible samples.
ADC Sample Sequence Control 0 (ADCSSCTL0)
Base 0x4003.8000
Offset 0x044
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
8th Sample Temp Sensor Select
This bit is used during the eighth sample of the sample sequence and
and specifies the input source of the sample.
When set, the temperature sensor is read.
When clear, the input pin specified by the ADCSSMUX register is read.
31 TS7 R/W 0
8th Sample Interrupt Enable
This bit is used during the eighth sample of the sample sequence and
specifies whether the raw interrupt signal (INR0 bit) is asserted at the
end of the sample's conversion. If the MASK0 bit in the ADCIM register
is set, the interrupt is promoted to a controller-level interrupt.
When this bit is set, the raw interrupt is asserted.
When this bit is clear, the raw interrupt is not asserted.
It is legal to have multiple samples within a sequence generate interrupts.
30 IE7 R/W 0
8th Sample is End of Sequence
The END7 bit indicates that this is the last sample of the sequence. It is
possible to end the sequence on any sample position. Samples defined
after the sample containing a set END are not requested for conversion
even though the fields may be non-zero. It is required that software write
the END bit somewhere within the sequence. (Sample Sequencer 3,
which only has a single sample in the sequence, is hardwired to have
the END0 bit set.)
Setting this bit indicates that this sample is the last in the sequence.
29 END7 R/W 0
8th Sample Diff Input Select
The D7 bit indicates that the analog input is to be differentially sampled.
The corresponding ADCSSMUXx nibble must be set to the pair number
"i", where the paired inputs are "2i and 2i+1". The temperature sensor
does not have a differential option. When set, the analog inputs are
differentially sampled.
28 D7 R/W 0
7th Sample Temp Sensor Select
Same definition as TS7 but used during the seventh sample.
27 TS6 R/W 0
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Bit/Field Name Type Reset Description
7th Sample Interrupt Enable
Same definition as IE7 but used during the seventh sample.
26 IE6 R/W 0
7th Sample is End of Sequence
Same definition as END7 but used during the seventh sample.
25 END6 R/W 0
7th Sample Diff Input Select
Same definition as D7 but used during the seventh sample.
24 D6 R/W 0
6th Sample Temp Sensor Select
Same definition as TS7 but used during the sixth sample.
23 TS5 R/W 0
6th Sample Interrupt Enable
Same definition as IE7 but used during the sixth sample.
22 IE5 R/W 0
6th Sample is End of Sequence
Same definition as END7 but used during the sixth sample.
21 END5 R/W 0
6th Sample Diff Input Select
Same definition as D7 but used during the sixth sample.
20 D5 R/W 0
5th Sample Temp Sensor Select
Same definition as TS7 but used during the fifth sample.
19 TS4 R/W 0
5th Sample Interrupt Enable
Same definition as IE7 but used during the fifth sample.
18 IE4 R/W 0
5th Sample is End of Sequence
Same definition as END7 but used during the fifth sample.
17 END4 R/W 0
5th Sample Diff Input Select
Same definition as D7 but used during the fifth sample.
16 D4 R/W 0
4th Sample Temp Sensor Select
Same definition as TS7 but used during the fourth sample.
15 TS3 R/W 0
4th Sample Interrupt Enable
Same definition as IE7 but used during the fourth sample.
14 IE3 R/W 0
4th Sample is End of Sequence
Same definition as END7 but used during the fourth sample.
13 END3 R/W 0
4th Sample Diff Input Select
Same definition as D7 but used during the fourth sample.
12 D3 R/W 0
3rd Sample Temp Sensor Select
Same definition as TS7 but used during the third sample.
11 TS2 R/W 0
3rd Sample Interrupt Enable
Same definition as IE7 but used during the third sample.
10 IE2 R/W 0
3rd Sample is End of Sequence
Same definition as END7 but used during the third sample.
9 END2 R/W 0
3rd Sample Diff Input Select
Same definition as D7 but used during the third sample.
8 D2 R/W 0
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Bit/Field Name Type Reset Description
2nd Sample Temp Sensor Select
Same definition as TS7 but used during the second sample.
7 TS1 R/W 0
2nd Sample Interrupt Enable
Same definition as IE7 but used during the second sample.
6 IE1 R/W 0
2nd Sample is End of Sequence
Same definition as END7 but used during the second sample.
5 END1 R/W 0
2nd Sample Diff Input Select
Same definition as D7 but used during the second sample.
4 D1 R/W 0
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
3 TS0 R/W 0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
2 IE0 R/W 0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
1 END0 R/W 0
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0 D0 R/W 0
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Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset
0x0A8
Important: Use caution when reading this register. Performing a read may change bit status.
This register contains the conversion results for samples collected with the sample sequencer (the
ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1,
ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return
conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the
FIFO is not properly handled by software, overflow and underflow conditions are registered in the
ADCOSTAT and ADCUSTAT registers.
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0)
Base 0x4003.8000
Offset 0x048
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset - - - - - - - - - - - - - - - -
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO -
9:0 DATA RO - Conversion Result Data
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Analog-to-Digital Converter (ADC)
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset
0x04C
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset
0x06C
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset
0x08C
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset
0x0AC
This register provides a window into the sample sequencer, providing full/empty status information
as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty
FIFO. The ADCSSFSTAT0 register provides status on FIFO0, ADCSSFSTAT1 on FIFO1,
ADCSSFSTAT2 on FIFO2, and ADCSSFSTAT3 on FIFO3.
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0)
Base 0x4003.8000
Offset 0x04C
Type RO, reset 0x0000.0100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved FULL reserved EMPTY HPTR TPTR
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:13 reserved RO 0x0
FIFO Full
When set, this bit indicates that the FIFO is currently full.
12 FULL RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:9 reserved RO 0x0
FIFO Empty
When set, this bit indicates that the FIFO is currently empty.
8 EMPTY RO 1
FIFO Head Pointer
This field contains the current "head" pointer index for the FIFO, that is,
the next entry to be written.
7:4 HPTR RO 0x0
FIFO Tail Pointer
This field contains the current "tail" pointer index for the FIFO, that is,
the next entry to be read.
3:0 TPTR RO 0x0
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Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1),
offset 0x060
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2),
offset 0x080
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 1 or 2. These registers are 16-bits wide and contain information for four possible
samples. See the ADCSSMUX0 register on page 407 for detailed bit descriptions. The ADCSSMUX1
register affects Sample Sequencer 1 and the ADCSSMUX2 register affects Sample Sequencer 2.
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1)
Base 0x4003.8000
Offset 0x060
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0
Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x0000
13:12 MUX3 R/W 0x0 4th Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10 reserved RO 0
9:8 MUX2 R/W 0x0 3rd Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0
5:4 MUX1 R/W 0x0 2nd Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
1:0 MUX0 R/W 0x0 1st Sample Input Select
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Analog-to-Digital Converter (ADC)
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084
These registers contain the configuration information for each sample for a sequence executed with
Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set at some
point, whether it be after the first sample, last sample, or any sample in between. These registers
are 16-bits wide and contain information for four possible samples. See the ADCSSCTL0 register
on page 409 for detailed bit descriptions. The ADCSSCTL1 register configures Sample Sequencer
1 and the ADCSSCTL2 register configures Sample Sequencer 2.
ADC Sample Sequence Control 1 (ADCSSCTL1)
Base 0x4003.8000
Offset 0x064
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
4th Sample Temp Sensor Select
Same definition as TS7 but used during the fourth sample.
15 TS3 R/W 0
4th Sample Interrupt Enable
Same definition as IE7 but used during the fourth sample.
14 IE3 R/W 0
4th Sample is End of Sequence
Same definition as END7 but used during the fourth sample.
13 END3 R/W 0
4th Sample Diff Input Select
Same definition as D7 but used during the fourth sample.
12 D3 R/W 0
3rd Sample Temp Sensor Select
Same definition as TS7 but used during the third sample.
11 TS2 R/W 0
3rd Sample Interrupt Enable
Same definition as IE7 but used during the third sample.
10 IE2 R/W 0
3rd Sample is End of Sequence
Same definition as END7 but used during the third sample.
9 END2 R/W 0
3rd Sample Diff Input Select
Same definition as D7 but used during the third sample.
8 D2 R/W 0
2nd Sample Temp Sensor Select
Same definition as TS7 but used during the second sample.
7 TS1 R/W 0
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Bit/Field Name Type Reset Description
2nd Sample Interrupt Enable
Same definition as IE7 but used during the second sample.
6 IE1 R/W 0
2nd Sample is End of Sequence
Same definition as END7 but used during the second sample.
5 END1 R/W 0
2nd Sample Diff Input Select
Same definition as D7 but used during the second sample.
4 D1 R/W 0
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
3 TS0 R/W 0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
2 IE0 R/W 0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
1 END0 R/W 0
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0 D0 R/W 0
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Analog-to-Digital Converter (ADC)
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3),
offset 0x0A0
This register defines the analog input configuration for a sample executed with Sample Sequencer
3. This register is 4-bits wide and contains information for one possible sample. See the ADCSSMUX0
register on page 407 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3)
Base 0x4003.8000
Offset 0x0A0
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MUX0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x0000.000
1:0 MUX0 R/W 0 1st Sample Input Select
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Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4
This register contains the configuration information for a sample executed with Sample Sequencer
3. The END bit is always set since there is only one sample in this sequencer. This register is 4-bits
wide and contains information for one possible sample. See the ADCSSCTL0 register on page 409
for detailed bit descriptions.
ADC Sample Sequence Control 3 (ADCSSCTL3)
Base 0x4003.8000
Offset 0x0A4
Type R/W, reset 0x0000.0002
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TS0 IE0 END0 D0
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x0000.000
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
3 TS0 R/W 0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
2 IE0 R/W 0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
1 END0 R/W 1
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0 D0 R/W 0
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Analog-to-Digital Converter (ADC)
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100
This register provides loopback operation within the digital logic of the ADC, which can be useful in
debugging software without having to provide actual analog stimulus. This test mode is entered by
writing a value of 0x0000.0001 to this register. When data is read from the FIFO in loopback mode,
the read-only portion of this register is returned.
ADC Test Mode Loopback (ADCTMLB)
Base 0x4003.8000
Offset 0x100
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved LB
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x0000.000
Loopback Mode Enable
When set, forces a loopback within the digital block to provide information
on input and unique numbering. The ADCSSFIFOn registers do not
provide sample data, but instead provide the 10-bit loopback data as
shown below.
Bit/Field Name Description
Continuous Sample Counter
Continuous sample counter that is initialized to 0
and counts each sample as it processed. This
helps provide a unique value for the data received.
9:6 CNT
Continuation Sample Indicator
When set, indicates that this is a continuation
sample. For example, if two sequencers were to
run back-to-back, this indicates that the controller
kept continuously sampling at full rate.
5 CONT
Differential Sample Indicator
When set, indicates that this is a differential
sample.
4 DIFF
Temp Sensor Sample Indicator
When set, indicates that this is a temperature
sensor sample.
3 TS
Analog Input Indicator
Indicates which analog input is to be sampled.
2:0 MUX
0 LB R/W 0
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12 Universal Asynchronous Receivers/Transmitters
(UARTs)
Each Stellaris® Universal Asynchronous Receiver/Transmitter (UART) has the following features:
■ Three fully programmable 16C550-type UARTs with IrDA support
■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
■ Programmable baud-rate generator allowing speeds up to 3.125 Mbps
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Standard asynchronous communication bits for start, stop, and parity
■ Line-break generation and detection
■ Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
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Universal Asynchronous Receivers/Transmitters (UARTs)
12.1 Block Diagram
Figure 12-1. UART Module Block Diagram
TxFIFO
16 x 8
...
RxFIFO
16 x 8
...
Identification
Registers
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
Interrupt Control
UARTDR
Control/Status
Transmitter
(with SIR
Transmit
Baud Rate Encoder)
Generator
Receiver
(with SIR
Receive
Decoder)
UnTx
UnRx
System Clock
Interrupt
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
UARTIBRD
UARTFBRD
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
UARTILPR
12.2 Functional Description
Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 439). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected
to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
12.2.1 Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
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bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 12-2 on page 422 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 12-2. UART Character Frame
1
0 5-8 data bits
LSB MSB
Parity bit
if enabled
1-2
stop bits
UnTX
n
Start
12.2.2 Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 435) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 436). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.)
BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
where UARTSysClk is the system clock connected to the UART.
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register)
can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and
adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as
Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error
detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 437), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
■ UARTIBRD write, UARTFBRD write, and UARTLCRH write
■ UARTFBRD write, UARTIBRD write, and UARTLCRH write
■ UARTIBRD write and UARTLCRH write
■ UARTFBRD write and UARTLCRH write
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12.2.3 Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 432) is asserted as soon as
data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has
been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 (described in “Transmit/Receive Logic” on page 421).
The start bit is valid and recognized if UnRx is still low on the eighth cycle of Baud16, otherwise it
is ignored. After a valid start bit is detected, successive data bits are sampled on every 16th cycle
of Baud16 (that is, one bit period later) according to the programmed length of the data characters.
The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the
UARTLCRH register.
Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When
a full word is received, the data is stored in the receive FIFO, with any error bits associated with
that word.
12.2.4 Serial IR (SIR)
The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream, and half-duplex
serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to
provide a digital encoded output and decoded input to the UART. The UART signal pins can be
connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block
has two modes of operation:
■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the
selected baud rate bit period on the output pin, while logic one levels are transmitted as a static
LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light
for each zero. On the reception side, the incoming light pulses energize the photo transistor base
of the receiver, pulling its output LOW. This drives the UART input pin LOW.
■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the
period of the internally generated IrLPBaud16 signal (1.63 μs, assuming a nominal 1.8432 MHz
frequency) by changing the appropriate bit in the UARTCR register. See page 434 for more
information on IrDA low-power pulse-duration configuration.
Figure 12-3 on page 424 shows the UART transmit and receive signals, with and without IrDA
modulation.
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Figure 12-3. IrDA Data Modulation
0 1 0 1 0 0 1 1 0 1
Data bits
0 1 0 1 0 0 1 1 0 1
Start Data bits
bit
Start Stop
Bit period 3 Bit period
16
UnTx
UnTx with IrDA
UnRx with IrDA
UnRx
Stop
bit
In both normal and low-power IrDA modes:
■ During transmission, the UART data bit is used as the base for encoding
■ During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay
between transmission and reception. This delay must be generated by software because it is not
automatically supported by the UART. The delay is required because the infrared receiver electronics
might become biased, or even saturated from the optical power coupled from the adjacent transmitter
LED. This delay is known as latency, or receiver setup time.
If the application does not require the use of the UnRx signal, the GPIO pin that has the UnRx signal
as an alternate function must be configured as the UnRx signal and pulled High.
12.2.5 FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 428). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data
in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 437).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 432) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the
UARTRSR register shows overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 441). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For
example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt
after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the
½ mark.
12.2.6 Interrupts
The UART can generate interrupts when the following conditions are observed:
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■ Overrun Error
■ Break Error
■ Parity Error
■ Framing Error
■ Receive Timeout
■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)
■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 446).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM ) register (see page 443) by setting the corresponding IM bit to 1. If interrupts are
not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 445).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 447).
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data
is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO
becomes empty through reading all the data (or by reading the holding register), or when a 1 is
written to the corresponding bit in the UARTICR register.
12.2.7 Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 439). In loopback mode,
data transmitted on UnTx is received on the UnRx input.
12.2.8 IrDA SIR block
The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the
SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR
transceiver.
The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same
time. Transmission must be stopped before data can be received. The IrDA SIR physical layer
specifies a minimum 10-ms delay between transmission and reception.
12.3 Initialization and Configuration
To use the UARTs, the peripheral clock must be enabled by setting the UART0, UART1, or UART2
bits in the RCGC1 register.
This section discusses the steps that are required to use a UART module. For this example, the
UART clock is assumed to be 20 MHz and the desired UART configuration is:
■ 115200 baud rate
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■ Data length of 8 bits
■ One stop bit
■ No parity
■ FIFOs disabled
■ No interrupts
The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the
UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the
equation described in “Baud-Rate Generation” on page 422, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 435) should be set to 10.
The value to be loaded into the UARTFBRD register (see page 436) is calculated by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Enable the UART by setting the UARTEN bit in the UARTCTL register.
12.4 Register Map
Table 12-1 on page 427 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■ UART0: 0x4000.C000
■ UART1: 0x4000.D000
■ UART2: 0x4000.E000
Note that the UART module clock must be enabled before the registers can be programmed (see
page 216). There must be a delay of 3 system clocks after the UART module clock is enabled before
any UART module registers are accessed.
Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 439)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
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Table 12-1. UART Register Map
See
Offset Name Type Reset Description page
0x000 UARTDR R/W 0x0000.0000 UART Data 428
0x004 UARTRSR/UARTECR R/W 0x0000.0000 UART Receive Status/Error Clear 430
0x018 UARTFR RO 0x0000.0090 UART Flag 432
0x020 UARTILPR R/W 0x0000.0000 UART IrDA Low-Power Register 434
0x024 UARTIBRD R/W 0x0000.0000 UART Integer Baud-Rate Divisor 435
0x028 UARTFBRD R/W 0x0000.0000 UART Fractional Baud-Rate Divisor 436
0x02C UARTLCRH R/W 0x0000.0000 UART Line Control 437
0x030 UARTCTL R/W 0x0000.0300 UART Control 439
0x034 UARTIFLS R/W 0x0000.0012 UART Interrupt FIFO Level Select 441
0x038 UARTIM R/W 0x0000.0000 UART Interrupt Mask 443
0x03C UARTRIS RO 0x0000.000F UART Raw Interrupt Status 445
0x040 UARTMIS RO 0x0000.0000 UART Masked Interrupt Status 446
0x044 UARTICR W1C 0x0000.0000 UART Interrupt Clear 447
0xFD0 UARTPeriphID4 RO 0x0000.0000 UART Peripheral Identification 4 449
0xFD4 UARTPeriphID5 RO 0x0000.0000 UART Peripheral Identification 5 450
0xFD8 UARTPeriphID6 RO 0x0000.0000 UART Peripheral Identification 6 451
0xFDC UARTPeriphID7 RO 0x0000.0000 UART Peripheral Identification 7 452
0xFE0 UARTPeriphID0 RO 0x0000.0011 UART Peripheral Identification 0 453
0xFE4 UARTPeriphID1 RO 0x0000.0000 UART Peripheral Identification 1 454
0xFE8 UARTPeriphID2 RO 0x0000.0018 UART Peripheral Identification 2 455
0xFEC UARTPeriphID3 RO 0x0000.0001 UART Peripheral Identification 3 456
0xFF0 UARTPCellID0 RO 0x0000.000D UART PrimeCell Identification 0 457
0xFF4 UARTPCellID1 RO 0x0000.00F0 UART PrimeCell Identification 1 458
0xFF8 UARTPCellID2 RO 0x0000.0005 UART PrimeCell Identification 2 459
0xFFC UARTPCellID3 RO 0x0000.00B1 UART PrimeCell Identification 3 460
12.5 Register Descriptions
The remainder of this section lists and describes the UART registers, in numerical order by address
offset.
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Register 1: UART Data (UARTDR), offset 0x000
Important: Use caution when reading this register. Performing a read may change bit status.
This register is the data register (the interface to the FIFOs).
When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs
are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.
UART Data (UARTDR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OE BE PE FE DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0
UART Overrun Error
The OE values are defined as follows:
Value Description
0 There has been no data loss due to a FIFO overrun.
New data was received when the FIFO was full, resulting in
data loss.
1
11 OE RO 0
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the receive data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state) and the next valid start bit is received.
10 BE RO 0
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Bit/Field Name Type Reset Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
9 PE RO 0
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
8 FE RO 0
Data Transmitted or Received
When written, the data that is to be transmitted via the UART. When
read, the data that was received by the UART.
7:0 DATA R/W 0
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Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset
0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared to 0 on reset.
Reads
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OE BE PE FE
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0
UART Overrun Error
When this bit is set to 1, data is received and the FIFO is already full.
This bit is cleared to 0 by a write to UARTECR.
The FIFO contents remain valid since no further data is written when
the FIFO is full, only the contents of the shift register are overwritten.
The CPU must now read the data in order to empty the FIFO.
3 OE RO 0
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the received data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
2 BE RO 0
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Bit/Field Name Type Reset Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
1 PE RO 0
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
0 FE RO 0
Writes
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x004
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved WO 0
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
7:0 DATA WO 0
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Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.
UART Flag (UARTFR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x018
Type RO, reset 0x0000.0090
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXFE RXFF TXFF RXFE BUSY reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding
register is empty.
If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO
is empty.
7 TXFE RO 1
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is full.
If the FIFO is enabled, this bit is set when the receive FIFO is full.
6 RXFF RO 0
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding register
is full.
If the FIFO is enabled, this bit is set when the transmit FIFO is full.
5 TXFF RO 0
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is empty.
If the FIFO is enabled, this bit is set when the receive FIFO is empty.
4 RXFE RO 1
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Bit/Field Name Type Reset Description
UART Busy
When this bit is 1, the UART is busy transmitting data. This bit remains
set until the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
3 BUSY RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor
value used to derive the low-power SIR pulse width clock by dividing down the system clock (SysClk).
All the bits are cleared to 0 when reset.
The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power
divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode
is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is
calculated as follows:
ILPDVSR = SysClk / FIrLPBaud16
where FIrLPBaud16 is nominally 1.8432 MHz.
You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power
pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency
of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that
pulses greater than 1.4 μs are accepted as valid pulses.
Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
UART IrDA Low-Power Register (UARTILPR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ILPDVSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
IrDA Low-Power Divisor
This is an 8-bit low-power divisor value.
7:0 ILPDVSR R/W 0x00
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Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 422
for configuration details.
UART Integer Baud-Rate Divisor (UARTIBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x024
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVINT
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0
15:0 DIVINT R/W 0x0000 Integer Baud-Rate Divisor
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Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 422
for configuration details.
UART Fractional Baud-Rate Divisor (UARTFBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x028
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DIVFRAC
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
5:0 DIVFRAC R/W 0x000 Fractional Baud-Rate Divisor
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 7: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
UART Line Control (UARTLCRH)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x02C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SPS WLEN FEN STP2 EPS PEN BRK
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
7 SPS R/W 0
UART Word Length
The bits indicate the number of data bits transmitted or received in a
frame as follows:
Value Description
0x3 8 bits
0x2 7 bits
0x1 6 bits
0x0 5 bits (default)
6:5 WLEN R/W 0
UART Enable FIFOs
If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO
mode).
When cleared to 0, FIFOs are disabled (Character mode). The FIFOs
become 1-byte-deep holding registers.
4 FEN R/W 0
UART Two Stop Bits Select
If this bit is set to 1, two stop bits are transmitted at the end of a frame.
The receive logic does not check for two stop bits being received.
3 STP2 R/W 0
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Bit/Field Name Type Reset Description
UART Even Parity Select
If this bit is set to 1, even parity generation and checking is performed
during transmission and reception, which checks for an even number
of 1s in data and parity bits.
When cleared to 0, then odd parity is performed, which checks for an
odd number of 1s.
This bit has no effect when parity is disabled by the PEN bit.
2 EPS R/W 0
UART Parity Enable
If this bit is set to 1, parity checking and generation is enabled; otherwise,
parity is disabled and no parity bit is added to the data frame.
1 PEN R/W 0
UART Send Break
If this bit is set to 1, a Low level is continually output on the UnTX output,
after completing transmission of the current character. For the proper
execution of the break command, the software must set this bit for at
least two frames (character periods). For normal use, this bit must be
cleared to 0.
0 BRK R/W 0
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are written.
If the UART is disabled during a transmit or receive operation, the current transaction is completed
prior to the UART stopping.
Note: The UARTCTL register should not be changed while the UART is enabled or else the results
are unpredictable. The following sequence is recommended for making changes to the
UARTCTL register.
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by disabling bit 4 (FEN) in the line control register (UARTLCRH).
4. Reprogram the control register.
5. Enable the UART.
UART Control (UARTCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x030
Type R/W, reset 0x0000.0300
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RXE TXE LBE reserved SIRLP SIREN UARTEN
Type RO RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0
UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled. When
the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note: To enable reception, the UARTEN bit must also be set.
9 RXE R/W 1
UART Transmit Enable
If this bit is set to 1, the transmit section of the UART is enabled. When
the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note: To enable transmission, the UARTEN bit must also be set.
8 TXE R/W 1
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Bit/Field Name Type Reset Description
UART Loop Back Enable
If this bit is set to 1, the UnTX path is fed through the UnRX path.
7 LBE R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:3 reserved RO 0
UART SIR Low Power Mode
This bit selects the IrDA encoding mode. If this bit is cleared to 0,
low-level bits are transmitted as an active High pulse with a width of
3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted
with a pulse width which is 3 times the period of the IrLPBaud16 input
signal, regardless of the selected bit rate. Setting this bit uses less power,
but might reduce transmission distances. See page 434 for more
information.
2 SIRLP R/W 0
UART SIR Enable
If this bit is set to 1, the IrDA SIR block is enabled, and the UART will
transmit and receive data using SIR protocol.
1 SIREN R/W 0
UART Enable
If this bit is set to 1, the UART is enabled. When the UART is disabled
in the middle of transmission or reception, it completes the current
character before stopping.
0 UARTEN R/W 0
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.
UART Interrupt FIFO Level Select (UARTIFLS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x034
Type R/W, reset 0x0000.0012
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RXIFLSEL TXIFLSEL
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
Value Description
0x0 RX FIFO ≥ ⅛ full
0x1 RX FIFO ≥ ¼ full
0x2 RX FIFO ≥ ½ full (default)
0x3 RX FIFO ≥ ¾ full
0x4 RX FIFO ≥ ⅞ full
0x5-0x7 Reserved
5:3 RXIFLSEL R/W 0x2
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Bit/Field Name Type Reset Description
UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
Value Description
0x0 TX FIFO ≤ ⅞ empty
0x1 TX FIFO ≤ ¾ empty
0x2 TX FIFO ≤ ½ empty (default)
0x3 TX FIFO ≤ ¼ empty
0x4 TX FIFO ≤ ⅛ empty
0x5-0x7 Reserved
2:0 TXIFLSEL R/W 0x2
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to
a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a
0 prevents the raw interrupt signal from being sent to the interrupt controller.
UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OEIM BEIM PEIM FEIM RTIM TXIM RXIM reserved
Type RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
UART Overrun Error Interrupt Mask
On a read, the current mask for the OEIM interrupt is returned.
Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller.
10 OEIM R/W 0
UART Break Error Interrupt Mask
On a read, the current mask for the BEIM interrupt is returned.
Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller.
9 BEIM R/W 0
UART Parity Error Interrupt Mask
On a read, the current mask for the PEIM interrupt is returned.
Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller.
8 PEIM R/W 0
UART Framing Error Interrupt Mask
On a read, the current mask for the FEIM interrupt is returned.
Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller.
7 FEIM R/W 0
UART Receive Time-Out Interrupt Mask
On a read, the current mask for the RTIM interrupt is returned.
Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller.
6 RTIM R/W 0
UART Transmit Interrupt Mask
On a read, the current mask for the TXIM interrupt is returned.
Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller.
5 TXIM R/W 0
UART Receive Interrupt Mask
On a read, the current mask for the RXIM interrupt is returned.
Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller.
4 RXIM R/W 0
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0x00
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x03C
Type RO, reset 0x0000.000F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
UART Overrun Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
10 OERIS RO 0
UART Break Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
9 BERIS RO 0
UART Parity Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
8 PERIS RO 0
UART Framing Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
7 FERIS RO 0
UART Receive Time-Out Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
6 RTRIS RO 0
UART Transmit Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
5 TXRIS RO 0
UART Receive Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
4 RXRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0xF
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Stellaris® LM3S2965 Microcontroller
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x040
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
UART Overrun Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
10 OEMIS RO 0
UART Break Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
9 BEMIS RO 0
UART Parity Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
8 PEMIS RO 0
UART Framing Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
7 FEMIS RO 0
UART Receive Time-Out Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
6 RTMIS RO 0
UART Transmit Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
5 TXMIS RO 0
UART Receive Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
4 RXMIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x044
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OEIC BEIC PEIC FEIC RTIC TXIC RXIC reserved
Type RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
Overrun Error Interrupt Clear
The OEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
10 OEIC W1C 0
Break Error Interrupt Clear
The BEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
9 BEIC W1C 0
Parity Error Interrupt Clear
The PEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
8 PEIC W1C 0
Framing Error Interrupt Clear
The FEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
7 FEIC W1C 0
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Bit/Field Name Type Reset Description
Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
6 RTIC W1C 0
Transmit Interrupt Clear
The TXIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
5 TXIC W1C 0
Receive Interrupt Clear
The RXIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
4 RXIC W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0x00
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 4 (UARTPeriphID4)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID4 RO 0x0000
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Stellaris® LM3S2965 Microcontroller
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 5 (UARTPeriphID5)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID5 RO 0x0000
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 6 (UARTPeriphID6)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID6 RO 0x0000
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Stellaris® LM3S2965 Microcontroller
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 7 (UARTPeriphID7)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID7 RO 0x0000
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 0 (UARTPeriphID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE0
Type RO, reset 0x0000.0011
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID0 RO 0x11
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Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 1 (UARTPeriphID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID1 RO 0x00
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Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 2 (UARTPeriphID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID2 RO 0x18
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Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 3 (UARTPeriphID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID3 RO 0x01
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Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 0 (UARTPCellID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
7:0 CID0 RO 0x0D
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Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 1 (UARTPCellID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
7:0 CID1 RO 0xF0
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Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 2 (UARTPCellID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
7:0 CID2 RO 0x05
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Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 3 (UARTPCellID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
7:0 CID3 RO 0xB1
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13 Synchronous Serial Interface (SSI)
The Stellaris® microcontroller includes two Synchronous Serial Interface (SSI) modules. Each SSI
is a master or slave interface for synchronous serial communication with peripheral devices that
have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces.
Each Stellaris SSI module has the following features:
■ Two SSI modules, each with the following features:
■ Master or slave operation
■ Programmable clock bit rate and prescale
■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
13.1 Block Diagram
Figure 13-1. SSI Module Block Diagram
Transmit /
Receive
Logic
Clock
Prescaler
SSICPSR
SSICR0
SSICR1
SSISR
Interrupt Control
SSIIM
SSIMIS
SSIRIS
SSIICR
SSIDR
TxFIFO
8 x16
...
RxFIFO
8 x16
...
System Clock
SSITx
SSIRx
SSIClk
SSIFss
Interrupt
Identification
Registers
SSIPCellID0 0 SSIPeriphID 4
SSIPCellID1 1 SSIPeriphID 5
SSIPCellID2 2 SSIPeriphID 6
SSIPCellID3 SSIPeriphID 3 SSIPeriphID7
Control/ Status
SSIPeriphID
SSIPeriphID
SSIPeriphID
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13.2 Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes.
13.2.1 Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 480). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 473).
The frequency of the output clock SSIClk is defined by:
SSIClk = FSysClk / (CPSDVSR * (1 + SCR))
Note: For master mode, the system clock must be at least two times faster than the SSIClk. For
slave mode, the system clock must be at least 12 times faster than the SSIClk.
See “Synchronous Serial Interface (SSI)” on page 690 to view SSI timing parameters.
13.2.2 FIFO Operation
13.2.2.1 Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 477), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit
FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit
FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was
enabled using the SSI bit in the RGCG1 register, then 0 is transmitted. Care should be taken to
ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt
or a μDMA request when the FIFO is empty.
13.2.2.2 Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
13.2.3 Interrupts
The SSI can generate interrupts when the following conditions are observed:
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■ Transmit FIFO service
■ Receive FIFO service
■ Receive FIFO time-out
■ Receive FIFO overrun
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
can only generate a single interrupt request to the controller at any given time. You can mask each
of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask
(SSIIM) register (see page 481). Setting the appropriate mask bit to 1 enables the interrupt.
Provision of the individual outputs, as well as a combined interrupt output, allows use of either a
global interrupt service routine, or modular device drivers to handle interrupts. The transmit and
receive dynamic dataflow interrupts have been separated from the status interrupts so that data
can be read or written in response to the FIFO trigger levels. The status of the individual interrupt
sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status
(SSIMIS) registers (see page 483 and page 484, respectively).
13.2.4 Frame Formats
Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. There are three basic frame types that can be selected:
■ Texas Instruments synchronous serial
■ Freescale SPI
■ MICROWIRE
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and
latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique, which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
13.2.4.1 Texas Instruments Synchronous Serial Frame Format
Figure 13-2 on page 464 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
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Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer)
SSIClk
SSIFss
SSITx/SSIRx MSB LSB
4 to 16 bits
In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is
pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data
is shifted onto the SSIRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSIClk after the LSB has been latched.
Figure 13-3 on page 464 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer)
MSB LSB
SSIClk
SSIFss
SSITx/SSIRx
4 to 16 bits
13.2.4.2 Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk
pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not
being transferred.
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SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition
before the first data capture edge. When the SPH phase control bit is Low, data is captured on the
first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition.
13.2.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 13-4 on page 465 and Figure 13-5 on page 465.
Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx Q
SSITx MSB
MSB
LSB
LSB
4 to 16 bits
Note: Q is undefined.
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx LSB
SSITx MSB LSB
LSB MSB
MSB
MSB
LSB
4 to16 bits
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto
the SSIRx input line of the master. The master SSITx output pad is enabled.
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One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the
master and slave data have been set, the SSIClk master clock pin goes High after one further half
SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
13.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
13-6 on page 466, which covers both single and continuous transfers.
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1
SSIClk
SSIFss
SSIRx
SSITx
Q
MSB
MQSB
LSB
LSB
4 to 16 bits
Q
Note: Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After
a further one half SSIClk period, both master and slave valid data is enabled onto their respective
transmission lines. At the same time, the SSIClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned
to its idle High state one SSIClk period after the last bit has been captured.
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For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
13.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 13-7 on page 467 and Figure 13-8 on page 467.
Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSIRx
SSITx
MSB Q
MSB LSB
LSB
4 to 16 bits
Note: Q is undefined.
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSITx/SSIRx LSB MSB LSB MSB
4 to 16 bits
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low, which causes slave data to be immediately
transferred onto the SSIRx line of the master. The master SSITx output pad is enabled.
One half period later, valid master data is transferred to the SSITx line. Now that both the master
and slave data have been set, the SSIClk master clock pin becomes Low after one further half
SSIClk period. This means that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss
line is returned to its idle High state one SSIClk period after the last bit has been captured.
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However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
13.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
13-9 on page 468, which covers both single and continuous transfers.
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1
SSIClk
SSIFss
SSIRx
SSITx
Q
MSB
MSB
LSB
LSB
4 to 16 bits
Q
Note: Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled.
After a further one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until
the final bit of the last word has been captured, and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
13.2.4.7 MICROWIRE Frame Format
Figure 13-10 on page 469 shows the MICROWIRE frame format, again for a single frame. Figure
13-11 on page 470 shows the same format when back-to-back frames are transmitted.
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Figure 13-10. MICROWIRE Frame Format (Single Frame)
SSIClk
SSIFss
SSIRx 0
SSITx
8-bit control
4 to 16 bits
output data
LSB
MSB
MSB
LSB
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
full-duplex, using a master-slave message passing technique. Each serial transmission begins with
an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss
causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the
SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains
tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of
each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a
one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven
onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising
edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one
clock period after the last bit has been latched in the receive serial shifter, which causes the data
to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk
after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer.
However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs
back-to-back. The control byte of the next frame follows directly after the LSB of the received data
from the current frame. Each of the received values is transferred from the receive shifter on the
falling edge of SSIClk, after the LSB of the frame has been latched into the SSI.
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Figure 13-11. MICROWIRE Frame Format (Continuous Transfer)
SSIClk
SSIFss
SSIRx 0 MSB LSB
SSITx LSB LSB
MSB
4 to 16 bits
output data
8-bit control
MSB
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
Figure 13-12 on page 470 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
SSIClk
SSIFss
SSIRx
First RX data to be
sampled by SSI slave
tSetup=(2*tSSIClk)
tHold=tSSIClk
13.3 Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the clock prescale divisor by writing the SSICPSR register.
4. Write the SSICR0 register with the following configuration:
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■ Serial clock rate (SCR)
■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
■ The data size (DSS)
5. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
■ Master operation
■ Freescale SPI mode (SPO=1, SPH=1)
■ 1 Mbps bit rate
■ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is disabled.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
13.4 Register Map
Table 13-1 on page 472 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■ SSI0: 0x4000.8000
■ SSI1: 0x4000.9000
Note that the SSI module clock must be enabled before the registers can be programmed (see
page 216). There must be a delay of 3 system clocks after the SSI module clock is enabled before
any SSI module registers are accessed.
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
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Table 13-1. SSI Register Map
See
Offset Name Type Reset Description page
0x000 SSICR0 R/W 0x0000.0000 SSI Control 0 473
0x004 SSICR1 R/W 0x0000.0000 SSI Control 1 475
0x008 SSIDR R/W 0x0000.0000 SSI Data 477
0x00C SSISR RO 0x0000.0003 SSI Status 478
0x010 SSICPSR R/W 0x0000.0000 SSI Clock Prescale 480
0x014 SSIIM R/W 0x0000.0000 SSI Interrupt Mask 481
0x018 SSIRIS RO 0x0000.0008 SSI Raw Interrupt Status 483
0x01C SSIMIS RO 0x0000.0000 SSI Masked Interrupt Status 484
0x020 SSIICR W1C 0x0000.0000 SSI Interrupt Clear 485
0xFD0 SSIPeriphID4 RO 0x0000.0000 SSI Peripheral Identification 4 486
0xFD4 SSIPeriphID5 RO 0x0000.0000 SSI Peripheral Identification 5 487
0xFD8 SSIPeriphID6 RO 0x0000.0000 SSI Peripheral Identification 6 488
0xFDC SSIPeriphID7 RO 0x0000.0000 SSI Peripheral Identification 7 489
0xFE0 SSIPeriphID0 RO 0x0000.0022 SSI Peripheral Identification 0 490
0xFE4 SSIPeriphID1 RO 0x0000.0000 SSI Peripheral Identification 1 491
0xFE8 SSIPeriphID2 RO 0x0000.0018 SSI Peripheral Identification 2 492
0xFEC SSIPeriphID3 RO 0x0000.0001 SSI Peripheral Identification 3 493
0xFF0 SSIPCellID0 RO 0x0000.000D SSI PrimeCell Identification 0 494
0xFF4 SSIPCellID1 RO 0x0000.00F0 SSI PrimeCell Identification 1 495
0xFF8 SSIPCellID2 RO 0x0000.0005 SSI PrimeCell Identification 2 496
0xFFC SSIPCellID3 RO 0x0000.00B1 SSI PrimeCell Identification 3 497
13.5 Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
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Register 1: SSI Control 0 (SSICR0), offset 0x000
SSICR0 is control register 0 and contains bit fields that control various functions within the SSI
module. Functionality such as protocol mode, clock rate, and data size are configured in this register.
SSI Control 0 (SSICR0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCR SPH SPO FRF DSS
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
SSI Serial Clock Rate
The value SCR is used to generate the transmit and receive bit rate of
the SSI. The bit rate is:
BR=FSSIClk/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
15:8 SCR R/W 0x0000
SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. It has the most impact on the first bit transmitted by
either allowing or not allowing a clock transition before the first data
capture edge.
When the SPH bit is 0, data is captured on the first clock edge transition.
If SPH is 1, data is captured on the second clock edge transition.
7 SPH R/W 0
SSI Serial Clock Polarity
This bit is only applicable to the Freescale SPI Format.
When the SPO bit is 0, it produces a steady state Low value on the
SSIClk pin. If SPO is 1, a steady state High value is placed on the
SSIClk pin when data is not being transferred.
6 SPO R/W 0
SSI Frame Format Select
The FRF values are defined as follows:
Value Frame Format
0x0 Freescale SPI Frame Format
0x1 Texas Instruments Synchronous Serial Frame Format
0x2 MICROWIRE Frame Format
0x3 Reserved
5:4 FRF R/W 0x0
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Bit/Field Name Type Reset Description
SSI Data Size Select
The DSS values are defined as follows:
Value Data Size
0x0-0x2 Reserved
0x3 4-bit data
0x4 5-bit data
0x5 6-bit data
0x6 7-bit data
0x7 8-bit data
0x8 9-bit data
0x9 10-bit data
0xA 11-bit data
0xB 12-bit data
0xC 13-bit data
0xD 14-bit data
0xE 15-bit data
0xF 16-bit data
3:0 DSS R/W 0x00
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Register 2: SSI Control 1 (SSICR1), offset 0x004
SSICR1 is control register 1 and contains bit fields that control various functions within the SSI
module. Master and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SOD MS SSE LBM
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In multiple-slave
systems, it is possible for the SSI master to broadcast a message to all
slaves in the system while ensuring that only one slave drives data onto
the serial output line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD bit can be
configured so that the SSI slave does not drive the SSITx pin.
The SOD values are defined as follows:
Value Description
0 SSI can drive SSITx output in Slave Output mode.
1 SSI must not drive the SSITx output in Slave mode.
3 SOD R/W 0
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
SSI is disabled (SSE=0).
The MS values are defined as follows:
Value Description
0 Device configured as a master.
1 Device configured as a slave.
2 MS R/W 0
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Bit/Field Name Type Reset Description
SSI Synchronous Serial Port Enable
Setting this bit enables SSI operation.
The SSE values are defined as follows:
Value Description
0 SSI operation disabled.
1 SSI operation enabled.
Note: This bit must be set to 0 before any control registers
are reprogrammed.
1 SSE R/W 0
SSI Loopback Mode
Setting this bit enables Loopback Test mode.
The LBM values are defined as follows:
Value Description
0 Normal serial port operation enabled.
Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.
1
0 LBM R/W 0
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Register 3: SSI Data (SSIDR), offset 0x008
Important: Use caution when reading this register. Performing a read may change bit status.
SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO
(pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI
receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed
to by the current FIFO write pointer).
When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written
to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is
loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed
bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.
15:0 DATA R/W 0x0000
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Register 4: SSI Status (SSISR), offset 0x00C
SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x00C
Type RO, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BSY RFF RNE TNF TFE
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 reserved RO 0x00
SSI Busy Bit
The BSY values are defined as follows:
Value Description
0 SSI is idle.
SSI is currently transmitting and/or receiving a frame, or the
transmit FIFO is not empty.
1
4 BSY RO 0
SSI Receive FIFO Full
The RFF values are defined as follows:
Value Description
0 Receive FIFO is not full.
1 Receive FIFO is full.
3 RFF RO 0
SSI Receive FIFO Not Empty
The RNE values are defined as follows:
Value Description
0 Receive FIFO is empty.
1 Receive FIFO is not empty.
2 RNE RO 0
SSI Transmit FIFO Not Full
The TNF values are defined as follows:
Value Description
0 Transmit FIFO is full.
1 Transmit FIFO is not full.
1 TNF RO 1
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Bit/Field Name Type Reset Description
SSI Transmit FIFO Empty
The TFE values are defined as follows:
Value Description
0 Transmit FIFO is not empty.
1 Transmit FIFO is empty.
0 TFE R0 1
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Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
SSICPSR is the clock prescale register and specifies the division factor by which the system clock
must be internally divided before further use.
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CPSDVSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254, depending on the
frequency of SSIClk. The LSB always returns 0 on reads.
7:0 CPSDVSR R/W 0x00
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Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding
mask.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXIM RXIM RTIM RORIM
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SSI Transmit FIFO Interrupt Mask
The TXIM values are defined as follows:
Value Description
0 TX FIFO half-full or less condition interrupt is masked.
1 TX FIFO half-full or less condition interrupt is not masked.
3 TXIM R/W 0
SSI Receive FIFO Interrupt Mask
The RXIM values are defined as follows:
Value Description
0 RX FIFO half-full or more condition interrupt is masked.
1 RX FIFO half-full or more condition interrupt is not masked.
2 RXIM R/W 0
SSI Receive Time-Out Interrupt Mask
The RTIM values are defined as follows:
Value Description
0 RX FIFO time-out interrupt is masked.
1 RX FIFO time-out interrupt is not masked.
1 RTIM R/W 0
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Bit/Field Name Type Reset Description
SSI Receive Overrun Interrupt Mask
The RORIM values are defined as follows:
Value Description
0 RX FIFO overrun interrupt is masked.
1 RX FIFO overrun interrupt is not masked.
0 RORIM R/W 0
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Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x018
Type RO, reset 0x0000.0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXRIS RXRIS RTRIS RORRIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SSI Transmit FIFO Raw Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
3 TXRIS RO 1
SSI Receive FIFO Raw Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
2 RXRIS RO 0
SSI Receive Time-Out Raw Interrupt Status
Indicates that the receive time-out has occurred, when set.
1 RTRIS RO 0
SSI Receive Overrun Raw Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
0 RORRIS RO 0
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Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXMIS RXMIS RTMIS RORMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0
SSI Transmit FIFO Masked Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
3 TXMIS RO 0
SSI Receive FIFO Masked Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
2 RXMIS RO 0
SSI Receive Time-Out Masked Interrupt Status
Indicates that the receive time-out has occurred, when set.
1 RTMIS RO 0
SSI Receive Overrun Masked Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
0 RORMIS RO 0
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Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x020
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RTIC RORIC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
SSI Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
0 No effect on interrupt.
1 Clears interrupt.
1 RTIC W1C 0
SSI Receive Overrun Interrupt Clear
The RORIC values are defined as follows:
Value Description
0 No effect on interrupt.
1 Clears interrupt.
0 RORIC W1C 0
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Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 4 (SSIPeriphID4)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID4 RO 0x00
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Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 5 (SSIPeriphID5)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID5 RO 0x00
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Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 6 (SSIPeriphID6)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID6 RO 0x00
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Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 7 (SSIPeriphID7)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID7 RO 0x00
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Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 0 (SSIPeriphID0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE0
Type RO, reset 0x0000.0022
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID0 RO 0x22
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Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 1 (SSIPeriphID1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID1 RO 0x00
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Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 2 (SSIPeriphID2)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID2 RO 0x18
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Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 3 (SSIPeriphID3)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID3 RO 0x01
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Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 0 (SSIPCellID0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
7:0 CID0 RO 0x0D
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Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 1 (SSIPCellID1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
7:0 CID1 RO 0xF0
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Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 2 (SSIPCellID2)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
7:0 CID2 RO 0x05
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Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 3 (SSIPCellID3)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
7:0 CID3 RO 0xB1
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14 Inter-Integrated Circuit (I2C) Interface
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C
bus may also be used for system testing and diagnostic purposes in product development and
manufacture. The LM3S2965 microcontroller includes two I2C modules, providing the ability to
interact (both send and receive) with other I2C devices on the bus.
The Stellaris® I2C interface has the following features:
■ Two I2C modules, each with the following features:
■ Devices on the I2C bus can be designated as either a master or a slave
– Supports both sending and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I2C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been sent or requested by a master
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
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14.1 Block Diagram
Figure 14-1. I2C Block Diagram
I2C I/O Select
I2C Master Core
Interrupt
I2C Slave Core
I2CSCL
I2CSDA
I2CSDA
I2CSCL
I2CSDA
I2CSCL
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIM
I2CSRIS
I2CSMIS
I2CMMIS I2CSICR
I2C Control
14.2 Functional Description
Each I2C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I2C bus configuration is shown in Figure 14-2 on page 499.
See “Inter-Integrated Circuit (I2C) Interface” on page 691 for I2C timing diagrams.
Figure 14-2. I2C Bus Configuration
RPUP
StellarisTM
I2CSCL I2CSDA
RPUP
3rd Party Device
with I2C Interface
SCL SDA
I2C Bus
SCL
SDA
3rd Party Device
with I2C Interface
SCL SDA
14.2.1 I2C Bus Functional Overview
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 500) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
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14.2.1.1 START and STOP Conditions
The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP.
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition,
and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition.
The bus is considered busy after a START condition and free after a STOP condition. See Figure
14-3 on page 500.
Figure 14-3. START and STOP Conditions
START
condition
SDA
SCL
STOP
condition
SDA
SCL
14.2.1.2 Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 14-4 on page 500. After the START condition, a
slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction
bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates
a request for data (receive). A data transfer is always terminated by a STOP condition generated
by the master, however, a master can initiate communications with another device on the bus by
generating a repeated START condition and addressing another slave without first generating a
STOP condition. Various combinations of receive/send formats are then possible within a single
transfer.
Figure 14-4. Complete Data Transfer with a 7-Bit Address
Slave address Data
SDA MSB LSB R/S ACK MSB LSB ACK
SCL 1 2 7 8 9 1 2 7 8 9
The first seven bits of the first byte make up the slave address (see Figure 14-5 on page 500). The
eighth bit determines the direction of the message. A zero in the R/S position of the first byte means
that the master will write (send) data to the selected slave, and a one in this position means that
the master will receive data from the slave.
Figure 14-5. R/S Bit in First Byte
R/S
LSB
Slave address
MSB
14.2.1.3 Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is Low (see Figure 14-6 on page 501).
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Figure 14-6. Data Validity During Bit Transfer on the I2C Bus
Change
of data
allowed
Dataline
stable
SDA
SCL
14.2.1.4 Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data
validity requirements described in “Data Validity” on page 500.
When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Since the master controls the number of bytes in the transfer, it signals the end
of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave
transmitter must then release SDA to allow the master to generate the STOP or a repeated START
condition.
14.2.1.5 Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of
the competing master devices to place a '1' (High) on SDA while another master transmits a '0'
(Low) will switch off its data output stage and retire until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
14.2.2 Available Speed Modes
The I2C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP.
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see
page 519).
The I2C clock period is calculated as follows:
SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD
For example:
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CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/T = 333 Khz
Table 14-1 on page 502 gives examples of timer period, system clock, and speed mode (Standard
or Fast).
Table 14-1. Examples of I2C Master Timer Period versus Speed Mode
System Clock Timer Period Standard Mode Timer Period Fast Mode
4 MHz 0x01 100 Kbps - -
6 MHz 0x02 100 Kbps - -
12.5 MHz 0x06 89 Kbps 0x01 312 Kbps
16.7 MHz 0x08 93 Kbps 0x02 278 Kbps
20 MHz 0x09 100 Kbps 0x02 333 Kbps
25 MHz 0x0C 96.2 Kbps 0x03 312 Kbps
33 MHz 0x10 97.1 Kbps 0x04 330 Kbps
40 MHz 0x13 100 Kbps 0x04 400 Kbps
50 MHz 0x18 100 Kbps 0x06 357 Kbps
14.2.3 Interrupts
The I2C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master arbitration lost
■ Master transaction error
■ Slave transaction received
■ Slave transaction requested
There is a separate interrupt signal for the I2C master and I2C slave modules. While both modules
can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
14.2.3.1 I2C Master Interrupts
The I2C master module generates an interrupt when a transaction completes (either transmit or
receive), when arbitration is lost, or when an error occurs during a transaction. To enable the I2C
master interrupt, software must set the IM bit in the I2C Master Interrupt Mask (I2CMIMR) register.
When an interrupt condition is met, software must check the ERROR and ARBLST bits in the I2C
Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction
and to ensure that arbitration has not been lost. An error condition is asserted if the last transaction
wasn't acknowledged by the slave. If an error is not detected and the master has not lost arbitration,
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the application can proceed with the transfer. The interrupt is cleared by writing a 1 to the IC bit in
the I2C Master Interrupt Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Master Raw Interrupt Status (I2CMRIS) register.
14.2.3.2 I2C Slave Interrupts
The slave module can generate an interrupt when data has been received or requested. This interrupt
is enabled by writing a 1 to the DATAIM bit in the I2C Slave Interrupt Mask (I2CSIMR) register.
Software determines whether the module should write (transmit) or read (receive) data from the I2C
Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status
(I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received,
the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a 1 to the DATAIC bit
in the I2C Slave Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Slave Raw Interrupt Status (I2CSRIS) register.
14.2.4 Loopback Operation
The I2C modules can be placed into an internal loopback mode for diagnostic or debug work. This
is accomplished by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In
loopback mode, the SDA and SCL signals from the master and slave modules are tied together.
14.2.5 Command Sequence Flow Charts
This section details the steps required to perform the various I2C transfer types in both master and
slave mode.
14.2.5.1 I2C Master Command Sequences
The figures that follow show the command sequences available for the I2C master.
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Figure 14-7. Master Single SEND
Idle
Write Slave
Address to
I2CMSA
Write data to
I2CMDR
Read I2CMCS
Sequence
may be
omitted in a
Single Master
system
BUSBSY bit=0? NO
Write ---0-111 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
Error Service
Idle
YES
NO
NO
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Figure 14-8. Master Single RECEIVE
Idle
Write Slave
Address to
I2CMSA
Read I2CMCS
Sequence may be
omitted in a Single
Master system
BUSBSY bit=0? NO
Write ---00111 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
Error Service
Idle
NO
NO
Read data from
I2CMDR
YES
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Figure 14-9. Master Burst SEND
Idle
Write Slave
Address to
I2CMSA
Write data to
I2CMDR
Read I2CMCS
BUSBSY bit=0?
YES
Write ---0-011 to
I2CMCS
NO
Read I2CMCS
BUSY bit=0?
YES
ERROR bit=0?
YES
Write data to ARBLST bit=1?
I2CMDR
Write ---0-100 to
Index=n? I2CMCS
NO
Error Service
Idle
YES
Write ---0-001 to
I2CMCS
Write ---0-101 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
NO
Idle
YES
Error Service NO
NO
NO
NO
Sequence
may be
omitted in a
Single Master
system
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Figure 14-10. Master Burst RECEIVE
Idle
Write Slave
Address to
I2CMSA
Read I2CMCS
BUSBSY bit=0? NO
Write ---01011 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0? NO
ERROR bit=0?
YES
ARBLST bit=1?
Write ---0-100 to
I2CMCS
NO
Error Service
YES
Idle
Read data from
I2CMDR
Index=m-1?
Write ---00101 to
I2CMCS
YES
Idle
Read data from
Error Service I2CMDR
ERROR bit=0?
YES
Write ---01001 to
I2CMCS
Read I2CMCS
BUSY bit=0? NO
YES
Sequence
may be
omitted in a
Single Master
system
NO
NO
NO
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Figure 14-11. Master Burst RECEIVE after Burst SEND
Idle
Master operates in
Master Transmit mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---01011 to
I2CMCS
Master operates in
Master Receive mode
Idle
Repeated START
condition is generated
with changing data
direction
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Figure 14-12. Master Burst SEND after Burst RECEIVE
Idle
Master operates in
Master Receive mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---0-011 to
I2CMCS
Master operates in
Master Transmit mode
Idle
Repeated START
condition is generated
with changing data
direction
14.2.5.2 I2C Slave Command Sequences
Figure 14-13 on page 510 presents the command sequence available for the I2C slave.
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Figure 14-13. Slave Command Sequence
Idle
Write OWN Slave
Address to
I2CSOAR
Write -------1 to
I2CSCSR
Read I2CSCSR
RREQ bit=1?
Read data from
I2CSDR
YES
TREQ bit=1? NO
Write data to
I2CSDR
YES
NO
FBR is
also valid
14.3 Initialization and Configuration
The following example shows how to configure the I2C module to send a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation.
4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020.
5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:
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TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1;
TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
6. Specify the slave address of the master and that the next operation will be a Send by writing
the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired
data.
8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with
a value of 0x0000.0007 (STOP, START, RUN).
9. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
14.4 Register Map
Table 14-2 on page 511 lists the I2C registers. All addresses given are relative to the I2C base
addresses for the master and slave:
■ I2C 0: 0x4002.0000
■ I2C 1: 0x4002.1000
Note that the I2C module clock must be enabled before the registers can be programmed (see
page 216). There must be a delay of 3 system clocks after the I2C module clock is enabled before
any I2C module registers are accessed.
The hw_i2c.h file in the StellarisWare® Driver Library uses a base address of 0x800 for the I2C slave
registers. Be aware when using registers with offsets between 0x800 and 0x818 that StellarisWare
uses an offset between 0x000 and 0x018 with the slave base address.
Table 14-2. Inter-Integrated Circuit (I2C) Interface Register Map
See
Offset Name Type Reset Description page
I2C Master
0x000 I2CMSA R/W 0x0000.0000 I2C Master Slave Address 513
0x004 I2CMCS R/W 0x0000.0000 I2C Master Control/Status 514
0x008 I2CMDR R/W 0x0000.0000 I2C Master Data 518
0x00C I2CMTPR R/W 0x0000.0001 I2C Master Timer Period 519
0x010 I2CMIMR R/W 0x0000.0000 I2C Master Interrupt Mask 520
0x014 I2CMRIS RO 0x0000.0000 I2C Master Raw Interrupt Status 521
0x018 I2CMMIS RO 0x0000.0000 I2C Master Masked Interrupt Status 522
0x01C I2CMICR WO 0x0000.0000 I2C Master Interrupt Clear 523
0x020 I2CMCR R/W 0x0000.0000 I2C Master Configuration 524
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Table 14-2. Inter-Integrated Circuit (I2C) Interface Register Map (continued)
See
Offset Name Type Reset Description page
I2C Slave
0x800 I2CSOAR R/W 0x0000.0000 I2C Slave Own Address 526
0x804 I2CSCSR RO 0x0000.0000 I2C Slave Control/Status 527
0x808 I2CSDR R/W 0x0000.0000 I2C Slave Data 529
0x80C I2CSIMR R/W 0x0000.0000 I2C Slave Interrupt Mask 530
0x810 I2CSRIS RO 0x0000.0000 I2C Slave Raw Interrupt Status 531
0x814 I2CSMIS RO 0x0000.0000 I2C Slave Masked Interrupt Status 532
0x818 I2CSICR WO 0x0000.0000 I2C Slave Interrupt Clear 533
14.5 Register Descriptions (I2C Master)
The remainder of this section lists and describes the I2C master registers, in numerical order by
address offset. See also “Register Descriptions (I2C Slave)” on page 525.
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Register 1: I2C Master Slave Address (I2CMSA), offset 0x000
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Send (Low).
I2C Master Slave Address (I2CMSA)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SA R/S
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
I2C Slave Address
This field specifies bits A6 through A0 of the slave address.
7:1 SA R/W 0
Receive/Send
The R/S bit specifies if the next operation is a Receive (High) or Send
(Low).
Value Description
0 Send.
1 Receive.
0 R/S R/W 0
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Register 2: I2C Master Control/Status (I2CMCS), offset 0x004
This register accesses four control bits when written, and accesses seven status bits when read.
The status register consists of seven bits, which when read determine the state of the I2C bus
controller.
The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes
the generation of the START, or REPEATED START condition.
The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst.
To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with
the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1),
STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed
(or aborted due an error), the interrupt pin becomes active and the data may be read from the
I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set
normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after
each byte. This bit must be reset when the I2C bus controller requires no further data to be sent
from the slave transmitter.
Reads
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x00
Bus Busy
This bit specifies the state of the I2C bus. If set, the bus is busy;
otherwise, the bus is idle. The bit changes based on the START and
STOP conditions.
6 BUSBSY RO 0
I2C Idle
This bit specifies the I2C controller state. If set, the controller is idle;
otherwise the controller is not idle.
5 IDLE RO 0
Arbitration Lost
This bit specifies the result of bus arbitration. If set, the controller lost
arbitration; otherwise, the controller won arbitration.
4 ARBLST RO 0
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Bit/Field Name Type Reset Description
Acknowledge Data
This bit specifies the result of the last data operation. If set, the
transmitted data was not acknowledged; otherwise, the data was
acknowledged.
3 DATACK RO 0
Acknowledge Address
This bit specifies the result of the last address operation. If set, the
transmitted address was not acknowledged; otherwise, the address was
acknowledged.
2 ADRACK RO 0
Error
This bit specifies the result of the last bus operation. If set, an error
occurred on the last operation; otherwise, no error was detected. The
error can be from the slave address not being acknowledged or the
transmit data not being acknowledged.
1 ERROR RO 0
I2C Busy
This bit specifies the state of the controller. If set, the controller is busy;
otherwise, the controller is idle. When the BUSY bit is set, the other status
bits are not valid.
0 BUSY RO 0
Writes
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x004
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ACK STOP START RUN
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved WO 0x00
Data Acknowledge Enable
When set, causes received data byte to be acknowledged automatically
by the master. See field decoding in Table 14-3 on page 516.
3 ACK WO 0
Generate STOP
When set, causes the generation of the STOP condition. See field
decoding in Table 14-3 on page 516.
2 STOP WO 0
Generate START
When set, causes the generation of a START or repeated START
condition. See field decoding in Table 14-3 on page 516.
1 START WO 0
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Bit/Field Name Type Reset Description
I2C Master Enable
When set, allows the master to send or receive data. See field decoding
in Table 14-3 on page 516.
0 RUN WO 0
Table 14-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3)
Description
Current I2CMSA[0] I2CMCS[3:0]
State R/S ACK STOP START RUN
START condition followed by SEND (master goes to the
Master Transmit state).
0 Xa 0 1 1
Idle
START condition followed by a SEND and STOP
condition (master remains in Idle state).
0 X 1 1 1
START condition followed by RECEIVE operation with
negative ACK (master goes to the Master Receive state).
1 0 0 1 1
START condition followed by RECEIVE and STOP
condition (master remains in Idle state).
1 0 1 1 1
START condition followed by RECEIVE (master goes
to the Master Receive state).
1 1 0 1 1
1 1 1 1 1 Illegal.
All other combinations not listed are non-operations. NOP.
SEND operation (master remains in Master Transmit
state).
X X 0 0 1
Master
Transmit
X X 1 0 0 STOP condition (master goes to Idle state).
SEND followed by STOP condition (master goes to Idle
state).
X X 1 0 1
Repeated START condition followed by a SEND (master
remains in Master Transmit state).
0 X 0 1 1
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
0 X 1 1 1
Repeated START condition followed by a RECEIVE
operation with a negative ACK (master goes to Master
Receive state).
1 0 0 1 1
Repeated START condition followed by a SEND and
STOP condition (master goes to Idle state).
1 0 1 1 1
Repeated START condition followed by RECEIVE
(master goes to Master Receive state).
1 1 0 1 1
1 1 1 1 1 Illegal.
All other combinations not listed are non-operations. NOP.
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Table 14-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) (continued)
Description
Current I2CMSA[0] I2CMCS[3:0]
State R/S ACK STOP START RUN
RECEIVE operation with negative ACK (master remains
in Master Receive state).
X 0 0 0 1
Master
Receive
X X 1 0 0 STOP condition (master goes to Idle state).b
RECEIVE followed by STOP condition (master goes to
Idle state).
X 0 1 0 1
RECEIVE operation (master remains in Master Receive
state).
X 1 0 0 1
X 1 1 0 1 Illegal.
Repeated START condition followed by RECEIVE
operation with a negative ACK (master remains in Master
Receive state).
1 0 0 1 1
Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
1 0 1 1 1
Repeated START condition followed by RECEIVE
(master remains in Master Receive state).
1 1 0 1 1
Repeated START condition followed by SEND (master
goes to Master Transmit state).
0 X 0 1 1
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
0 X 1 1 1
All other combinations not listed are non-operations. NOP.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.
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Register 3: I2C Master Data (I2CMDR), offset 0x008
Important: Use caution when reading this register. Performing a read may change bit status.
This register contains the data to be transmitted when in the Master Transmit state, and the data
received when in the Master Receive state.
I2C Master Data (I2CMDR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Data Transferred
Data transferred during transaction.
7:0 DATA R/W 0x00
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Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C
This register specifies the period of the SCL clock.
Caution – Take care not to set bit 7 when accessing this register as unpredictable behavior can occur.
I2C Master Timer Period (I2CMTPR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x00C
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TPR
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x00
SCL Clock Period
This field specifies the period of the SCL clock.
SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD
where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the Timer Period register value (range of 1 to 127).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
6:0 TPR R/W 0x1
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Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IM
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Interrupt Mask
This bit controls whether a raw interrupt is promoted to a controller
interrupt. If set, the interrupt is not masked and the interrupt is promoted;
otherwise, the interrupt is masked.
0 IM R/W 0
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Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014
This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Raw Interrupt Status
This bit specifies the raw interrupt state (prior to masking) of the I2C
master block. If set, an interrupt is pending; otherwise, an interrupt is
not pending.
0 RIS RO 0
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Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018
This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Masked Interrupt Status
This bit specifies the raw interrupt state (after masking) of the I2C master
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.
0 MIS RO 0
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Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C
This register clears the raw interrupt.
I2C Master Interrupt Clear (I2CMICR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x01C
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Interrupt Clear
This bit controls the clearing of the raw interrupt. A write of 1 clears the
interrupt; otherwise, a write of 0 has no affect on the interrupt state. A
read of this register returns no meaningful data.
0 IC WO 0
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Register 9: I2C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
I2C Master Configuration (I2CMCR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SFE MFE reserved LPBK
Type RO RO RO RO RO RO RO RO RO RO R/W R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
I2C Slave Function Enable
This bit specifies whether the interface may operate in Slave mode. If
set, Slave mode is enabled; otherwise, Slave mode is disabled.
5 SFE R/W 0
I2C Master Function Enable
This bit specifies whether the interface may operate in Master mode. If
set, Master mode is enabled; otherwise, Master mode is disabled and
the interface clock is disabled.
4 MFE R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:1 reserved RO 0x00
I2C Loopback
This bit specifies whether the interface is operating normally or in
Loopback mode. If set, the device is put in a test mode loopback
configuration; otherwise, the device operates normally.
0 LPBK R/W 0
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14.6 Register Descriptions (I2C Slave)
The remainder of this section lists and describes the I2C slave registers, in numerical order by
address offset. See also “Register Descriptions (I2C Master)” on page 512.
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Register 10: I2C Slave Own Address (I2CSOAR), offset 0x800
This register consists of seven address bits that identify the Stellaris I2C device on the I2C bus.
I2C Slave Own Address (I2CSOAR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x800
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OAR
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x00
I2C Slave Own Address
This field specifies bits A6 through A0 of the slave address.
6:0 OAR R/W 0x00
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Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x804
This register accesses one control bit when written, and three status bits when read.
The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First
Byte Received (FBR) bit is set only after the Stellaris device detects its own slave address and
receives the first data byte from the I2C master. The Receive Request (RREQ) bit indicates that
the Stellaris I2C device has received a data byte from an I2C master. Read one data byte from the
I2C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit
indicates that the Stellaris I2C device is addressed as a Slave Transmitter. Write one data byte into
the I2C Slave Data (I2CSDR) register to clear the TREQ bit.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
Stellaris I2C slave operation.
Reads
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x804
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved FBR TREQ RREQ
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
First Byte Received
Indicates that the first byte following the slave’s own address is received.
This bit is only valid when the RREQ bit is set, and is automatically cleared
when data has been read from the I2CSDR register.
Note: This bit is not used for slave transmit operations.
2 FBR RO 0
Transmit Request
This bit specifies the state of the I2C slave with regards to outstanding
transmit requests. If set, the I2C unit has been addressed as a slave
transmitter and uses clock stretching to delay the master until data has
been written to the I2CSDR register. Otherwise, there is no outstanding
transmit request.
1 TREQ RO 0
Receive Request
This bit specifies the status of the I2C slave with regards to outstanding
receive requests. If set, the I2C unit has outstanding receive data from
the I2C master and uses clock stretching to delay the master until the
data has been read from the I2CSDR register. Otherwise, no receive
data is outstanding.
0 RREQ RO 0
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Writes
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x804
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Device Active
Value Description
0 Disables the I2C slave operation.
1 Enables the I2C slave operation.
0 DA WO 0
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Register 12: I2C Slave Data (I2CSDR), offset 0x808
Important: Use caution when reading this register. Performing a read may change bit status.
This register contains the data to be transmitted when in the Slave Transmit state, and the data
received when in the Slave Receive state.
I2C Slave Data (I2CSDR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x808
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Data for Transfer
This field contains the data for transfer during a slave receive or transmit
operation.
7:0 DATA R/W 0x0
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Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x80C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATAIM
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Data Interrupt Mask
This bit controls whether the raw interrupt for data received and data
requested is promoted to a controller interrupt. If set, the interrupt is not
masked and the interrupt is promoted; otherwise, the interrupt is masked.
0 DATAIM R/W 0
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Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810
This register specifies whether an interrupt is pending.
I2C Slave Raw Interrupt Status (I2CSRIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x810
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATARIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Data Raw Interrupt Status
This bit specifies the raw interrupt state for data received and data
requested (prior to masking) of the I2C slave block. If set, an interrupt
is pending; otherwise, an interrupt is not pending.
0 DATARIS RO 0
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Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x814
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATAMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Data Masked Interrupt Status
This bit specifies the interrupt state for data received and data requested
(after masking) of the I2C slave block. If set, an interrupt was signaled;
otherwise, an interrupt has not been generated since the bit was last
cleared.
0 DATAMIS RO 0
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Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x818
This register clears the raw interrupt. A read of this register returns no meaningful data.
I2C Slave Interrupt Clear (I2CSICR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x818
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATAIC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Data Interrupt Clear
This bit controls the clearing of the raw interrupt for data received and
data requested. When set, it clears the DATARIS interrupt bit; otherwise,
it has no effect on the DATARIS bit value.
0 DATAIC WO 0
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15 Controller Area Network (CAN) Module
Controller Area Network (CAN) is a multicast, shared serial bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically-noisy
environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair
wire. Originally created for automotive purposes, it is also used in many embedded control
applications (such as industrial and medical). Bit rates up to 1Mbps are possible at network lengths
less than 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at
500 meters).
Each Stellaris® CAN controller supports the following features:
■ Two CAN modules, each with the following features:
■ CAN protocol version 2.0 part A/B
■ Bit rates up to 1 Mbps
■ 32 message objects with individual identifier masks
■ Maskable interrupt
■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
■ Programmable Loopback mode for self-test operation
■ Programmable FIFO mode enables storage of multiple message objects
■ Gluelessly attaches to an external CAN interface through the CANnTX and CANnRX signals
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15.1 Block Diagram
Figure 15-1. CAN Controller Block Diagram
CAN Control
CAN Core
Message Object
Registers
CANNWDA2
CANMSG1INT
CANMSG2INT
CANMSG1VAL
CANMSG2VAL
CAN Tx
CANINT
CANTST
CANBRPE
CANBIT
APB
Interface
ABP
Pins
Message RAM
32 Message Objects
CANERR
CANCTL
CANSTS
CANIF2ARB2
CANIF2MCTL
CANIF2DA1
CAN Interface 2
CANIF2DA2
CANIF2DB1
CANIF2DB2
CANIF2ARB1
CANIF2MSK2
CANIF2CRQ
CANIF2CMSK
CANIF2MSK1
CAN Interface 1
CANIF1CRQ
CANIF1CMSK
CANIF1MSK1
CANIF1MSK2
CANIF1ARB1
CANIF1ARB2
CANIF1MCTL
CANIF1DA1
CANIF1DA2
CANIF1DB1
CANIF1DB2
CAN Rx
CANNWDA1
CANTXRQ1
CANTXRQ2
15.2 Functional Description
The Stellaris CAN controller conforms to the CAN protocol version 2.0 (parts A and B). Message
transfers that include data, remote, error, and overload frames with an 11-bit identifier (standard)
or a 29-bit identifier (extended) are supported. Transfer rates can be programmed up to 1 Mbps.
The CAN module consists of three major parts:
■ CAN protocol controller and message handler
■ Message memory
■ CAN register interface
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A data frame contains data for transmission, whereas a remote frame contains no data and is used
to request the transmission of a specific message object. The CAN data/remote frame is constructed
as shown in Figure 15-2 on page 536.
Figure 15-2. CAN Data/Remote Frame
Number
Of Bits
SOF
EOP IFS Bus
Idle
1 11 or 29 1 6 0 . . . 64 15 1 1 1 7 3
ACK
Control Data Field
Field
RTR
Message Delimiter
Bus
Idle
Bit Stuffing
CAN Data Frame
Arbitration Field
CRC Sequence
CRC
Field
Acknowledgement
Field
End of
Frame
Field
Interframe
Field
Start
Of Frame
Remote
Transmission
Request
Delimiter
Bits
CRC
Sequence
The protocol controller transfers and receives the serial data from the CAN bus and passes the data
on to the message handler. The message handler then loads this information into the appropriate
message object based on the current filtering and identifiers in the message object memory. The
message handler is also responsible for generating interrupts based on events on the CAN bus.
The message object memory is a set of 32 identical memory blocks that hold the current configuration,
status, and actual data for each message object. These are accessed via either of the CAN message
object register interfaces.
The message memory is not directly accessible in the Stellaris memory map, so the Stellaris CAN
controller provides an interface to communicate with the message memory via two CAN interface
register sets for communicating with the message objects. As there is no direct access to the
message object memory, these two interfaces must be used to read or write to each message object.
The two message object interfaces allow parallel access to the CAN controller message objects
when multiple objects may have new information that must be processed. In general, one interface
is used for transmit data and one for receive data.
15.2.1 Initialization
Software initialization is started by setting the INIT bit in the CAN Control (CANCTL) register (with
software or by a hardware reset) or by going bus-off, which occurs when the transmitter's error
counter exceeds a count of 255. While INIT is set, all message transfers to and from the CAN bus
are stopped and the CANnTX signal is held High. Entering the initialization state does not change
the configuration of the CAN controller, the message objects, or the error counters. However, some
configuration registers are only accessible while in the initialization state.
To initialize the CAN controller, set the CAN Bit Timing (CANBIT) register and configure each
message object. If a message object is not needed, label it as not valid by clearing the MSGVAL bit
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in the CAN IFn Arbitration 2 (CANIFnARB2) register. Otherwise, the whole message object must
be initialized, as the fields of the message object may not have valid information, causing unexpected
results. Both the INIT and CCE bits in the CANCTL register must be set in order to access the
CANBIT register and the CAN Baud Rate Prescaler Extension (CANBRPE) register to configure
the bit timing. To leave the initialization state, the INIT bit must be cleared. Afterwards, the internal
Bit Stream Processor (BSP) synchronizes itself to the data transfer on the CAN bus by waiting for
the occurrence of a sequence of 11 consecutive recessive bits (indicating a bus idle condition)
before it takes part in bus activities and starts message transfers. Message object initialization does
not require the CAN to be in the initialization state and can be done on the fly. However, message
objects should all be configured to particular identifiers or set to not valid before message transfer
starts. To change the configuration of a message object during normal operation, clear the MSGVAL
bit in the CANIFnARB2 register to indicate that the message object is not valid during the change.
When the configuration is completed, set the MSGVAL bit again to indicate that the message object
is once again valid.
15.2.2 Operation
There are two sets of CAN Interface Registers (CANIF1x and CANIF2x), which are used to access
the message objects in the Message RAM. The CAN controller coordinates transfers to and from
the Message RAM to and from the registers. The two sets are independent and identical and can
be used to queue transactions. Generally, one interface is used to transmit data and one is used to
receive data.
Once the CAN module is initialized and the INIT bit in the CANCTL register is cleared, the CAN
module synchronizes itself to the CAN bus and starts the message transfer. As each message is
received, it goes through the message handler's filtering process, and if it passes through the filter,
is stored in the message object specified by the MNUM bit in the CAN IFn Command Request
(CANIFnCRQ) register. The whole message (including all arbitration bits, data-length code, and
eight data bytes) is stored in the message object. If the Identifier Mask (the MSK bits in the CAN IFn
Mask 1 and CAN IFn Mask 2 (CANIFnMSKn) registers) is used, the arbitration bits that are masked
to "don't care" may be overwritten in the message object.
The CPU may read or write each message at any time via the CAN Interface Registers. The message
handler guarantees data consistency in case of concurrent accesses.
The transmission of message objects is under the control of the software that is managing the CAN
hardware. These can be message objects used for one-time data transfers, or permanent message
objects used to respond in a more periodic manner. Permanent message objects have all arbitration
and control set up, and only the data bytes are updated. At the start of transmission, the appropriate
TXRQST bit in the CAN Transmission Request n (CANTXRQn) register and the NEWDAT bit in the
CAN New Data n (CANNWDAn) register are set. If several transmit messages are assigned to the
same message object (when the number of message objects is not sufficient), the whole message
object has to be configured before the transmission of this message is requested.
The transmission of any number of message objects may be requested at the same time; they are
transmitted according to their internal priority, which is based on the message identifier (MNUM) for
the message object, with 1 being the highest priority and 32 being the lowest priority. Messages
may be updated or set to not valid any time, even when their requested transmission is still pending.
The old data is discarded when a message is updated before its pending transmission has started.
Depending on the configuration of the message object, the transmission of a message may be
requested autonomously by the reception of a remote frame with a matching identifier.
Transmission can be automatically started by the reception of a matching remote frame. To enable
this mode, set the RMTEN bit in the CAN IFn Message Control (CANIFnMCTL) register. A matching
received remote frame causes the TXRQST bit to be set and the message object automatically
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transfers its data or generates an interrupt indicating a remote frame was requested. This can be
strictly a single message identifier, or it can be a range of values specified in the message object.
The CAN mask registers, CANIFnMSKn, configure which groups of frames are identified as remote
frame requests. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the
CANIFnMSKn register to filter which frames are identified as a remote frame request. The MXTD
bit in the CANIFnMSK2 register should be set if a remote frame request is expected to be triggered
by 29-bit extended identifiers.
15.2.3 Transmitting Message Objects
If the internal transmit shift register of the CAN module is ready for loading, and if there is no data
transfer occurring between the CAN Interface Registers and message RAM, the valid message
object with the highest priority that has a pending transmission request is loaded into the transmit
shift register by the message handler and the transmission is started. The message object's NEWDAT
bit in the CANNWDAn register is cleared. After a successful transmission, and if no new data was
written to the message object since the start of the transmission, the TXRQST bit in the CANTXRQn
register is cleared. If the CAN controller is set up to interrupt upon a successful transmission of a
message object, (the TXIE bit in the CAN IFn Message Control (CANIFnMCTL) register is set),
the INTPND bit in the CANIFnMCTL register is set after a successful transmission. If the CAN
module has lost the arbitration or if an error occurred during the transmission, the message is
re-transmitted as soon as the CAN bus is free again. If, meanwhile, the transmission of a message
with higher priority has been requested, the messages are transmitted in the order of their priority.
15.2.4 Configuring a Transmit Message Object
The following steps illustrate how to configure a transmit message object.
1. In the CAN IFn Command Mask (CANIFnCMASK) register:
■ Set the WRNRD bit to specify a write to the CANIFnCMASK register; specify whether to
transfer the IDMASK, DIR, and MXTD of the message object into the CAN IFn registers using
the MASK bit
■ Specify whether to transfer the ID, DIR, XTD, and MSGVAL of the message object into the
interface registers using the ARB bit
■ Specify whether to transfer the control bits into the interface registers using the CONTROL
bit
■ Specify whether to clear the INTPND bit in the CANIFnMCTL register using the CLRINTPND
bit
■ Specify whether to clear the NEWDAT bit in the CANNWDAn register using the NEWDAT bit
■ Specify which bits to transfer using the DATAA and DATAB bits
2. In the CANIFnMSK1 register, use the MSK[15:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[15:0] in this
register are used for bits [15:0] of the 29-bit message identifier and are not used for an 11-bit
identifier. A value of 0x00 enables all messages to pass through the acceptance filtering. Also
note that in order for these bits to be used for acceptance filtering, they must be enabled by
setting the UMASK bit in the CANIFnMCTL register.
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3. In the CANIFnMSK2 register, use the MSK[12:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used
for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of
the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and
DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the
acceptance filtering. Also note that in order for these bits to be used for acceptance filtering,
they must be enabled by setting the UMASK bit in the CANIFnMCTL register.
4. For a 29-bit identifier, configure ID[15:0] in the CANIFnARB1 register to are used for bits
[15:0] of the message identifier and ID[12:0] in the CANIFnARB2 register to are used for
bits [28:16] of the message identifier. Set the XTD bit to indicate an extended identifier; set the
DIR bit to indicate transmit; and set the MSGVAL bit to indicate that the message object is valid.
5. For an 11-bit identifier, disregard the CANIFnARB1 register and configure ID[12:2] in the
CANIFnARB2 register to are used for bits [10:0] of the message identifier. Clear the XTD bit to
indicate a standard identifier; set the DIR bit to indicate transmit; and set the MSGVAL bit to
indicate that the message object is valid.
6. In the CANIFnMCTL register:
■ Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the
CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering
■ Optionally set the TXIE bit to enable the INTPND bit to be set after a successful transmission
■ Optionally set the RMTEN bit to enable the TXRQST bit to be set upon the reception of a
matching remote frame allowing automatic transmission
■ Set the EOB bit for a single message object;
■ Set the DLC[3:0] field to specify the size of the data frame. Take care during this
configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits.
7. Load the data to be transmitted into the CAN IFn Data (CANIFnDA1, CANIFnDA2, CANIFnDB1,
CANIFnDB2) or (CANIFnDATAA and CANIFnDATAB) registers. Byte 0 of the CAN data frame
is stored in DATA[7:0] in the CANIFnDA1 register.
8. Program the number of the message object to be transmitted in the MNUM field in the CAN IFn
Command Request (CANIFnCRQ) register.
9. When everything is properly configured, set the TXRQST bit in the CANIFnMCTL register. Once
this bit is set, the message object is available to be transmitted, depending on priority and bus
availability. Note that setting the RMTEN bit in the CANIFnMCTL register can also start message
transmission if a matching remote frame has been received.
15.2.5 Updating a Transmit Message Object
The CPU may update the data bytes of a Transmit Message Object any time via the CAN Interface
Registers and neither the MSGVAL bit in the CANIFnARB2 register nor the TXRQST bits in the
CANIFnMCTL register have to be cleared before the update.
Even if only some of the data bytes are to be updated, all four bytes of the corresponding
CANIFnDAn/CANIFnDBn register have to be valid before the content of that register is transferred
to the message object. Either the CPU must write all four bytes into the CANIFnDAn/CANIFnDBn
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register or the message object is transferred to the CANIFnDAn/CANIFnDBn register before the
CPU writes the new data bytes.
In order to only update the data in a message object, the WRNRD, DATAA and DATAB bits in the
CANIFnMSKn register are set, followed by writing the updated data into CANIFnDA1, CANIFnDA2,
CANIFnDB1, and CANIFnDB2 registers, and then the number of the message object is written to
the MNUM field in the CAN IFn Command Request (CANIFnCRQ) register. To begin transmission
of the new data as soon as possible, set the TXRQST bit in the CANIFnMSKn register.
To prevent the clearing of the TXRQST bit in the CANIFnMCTL register at the end of a transmission
that may already be in progress while the data is updated, the NEWDAT and TXRQST bits have to be
set at the same time in the CANIFnMCTL register. When these bits are set at the same time, NEWDAT
is cleared as soon as the new transmission has started.
15.2.6 Accepting Received Message Objects
When the arbitration and control field (the ID and XTD bits in the CANIFnARB2 and the RMTEN and
DLC[3:0] bits of the CANIFnMCTL register) of an incoming message is completely shifted into
the CAN controller, the message handling capability of the controller starts scanning the message
RAM for a matching valid message object. To scan the message RAM for a matching message
object, the controller uses the acceptance filtering programmed through the mask bits in the
CANIFnMSKn register and enabled using the UMASK bit in the CANIFnMCTL register. Each valid
message object, starting with object 1, is compared with the incoming message to locate a matching
message object in the message RAM. If a match occurs, the scanning is stopped and the message
handler proceeds depending on whether it is a data frame or remote frame that was received.
15.2.7 Receiving a Data Frame
The message handler stores the message from the CAN controller receive shift register into the
matching message object in the message RAM. The data bytes, all arbitration bits, and the DLC bits
are all stored into the corresponding message object. In this manner, the data bytes are connected
with the identifier even if arbitration masks are used. The NEWDAT bit of the CANIFnMCTL register
is set to indicate that new data has been received. The CPU should clear this bit when it reads the
message object to indicate to the controller that the message has been received, and the buffer is
free to receive more messages. If the CAN controller receives a message and the NEWDAT bit is
already set, the MSGLST bit in the CANIFnMCTL register is set to indicate that the previous data
was lost. If the system requires an interrupt upon successful reception of a frame, the RXIE bit of
the CANIFnMCTL register should be set. In this case, the INTPND bit of the same register is set,
causing the CANINT register to point to the message object that just received a message. The
TXRQST bit of this message object should be cleared to prevent the transmission of a remote frame.
15.2.8 Receiving a Remote Frame
A remote frame contains no data, but instead specifies which object should be transmitted. When
a remote frame is received, three different configurations of the matching message object have to
be considered:
Configuration in CANIFnMCTL Description
At the reception of a matching remote frame, the TXRQST bit of this
message object is set. The rest of the message object remains
unchanged, and the controller automatically transfers the data in
the message object as soon as possible.
■ DIR = 1 (direction = transmit); programmed in the
CANIFnARB2 register
■ RMTEN = 1 (set the TXRQST bit of the
CANIFnMCTL register at reception of the frame
to enable transmission)
■ UMASK = 1 or 0
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Configuration in CANIFnMCTL Description
At the reception of a matching remote frame, the TXRQST bit of this
message object remains unchanged, and the remote frame is
ignored. This remote frame is disabled, the data is not transferred
and there is no indication that the remote frame ever happened.
■ DIR = 1 (direction = transmit); programmed in the
CANIFnARB2 register
■ RMTEN = 0 (do not change the TXRQST bit of the
CANIFnMCTL register at reception of the frame)
■ UMASK = 0 (ignore mask in the CANIFnMSKn
register)
At the reception of a matching remote frame, the TXRQST bit of this
message object is cleared. The arbitration and control field (ID +
XTD + RMTEN + DLC) from the shift register is stored into the
message object in the message RAM and the NEWDAT bit of this
message object is set. The data field of the message object remains
unchanged; the remote frame is treated similar to a received data
frame. This is useful for a remote data request from another CAN
device for which the Stellaris controller does not have readily
available data. The software must fill the data and answer the frame
manually.
■ DIR = 1 (direction = transmit); programmed in the
CANIFnARB2 register
■ RMTEN = 0 (do not change the TXRQST bit of the
CANIFnMCTL register at reception of the frame)
■ UMASK = 1 (use mask (MSK, MXTD, and MDIR in
the CANIFnMSKn register) for acceptance filtering)
15.2.9 Receive/Transmit Priority
The receive/transmit priority for the message objects is controlled by the message number. Message
object 1 has the highest priority, while message object 32 has the lowest priority. If more than one
transmission request is pending, the message objects are transmitted in order based on the message
object with the lowest message number. This should not be confused with the message identifier
as that priority is enforced by the CAN bus. This means that if message object 1 and message object
2 both have valid messages that need to be transmitted, message object 1 will always be transmitted
first regardless of the message identifier in the message object itself.
15.2.10 Configuring a Receive Message Object
The following steps illustrate how to configure a receive message object.
1. Program the CAN IFn Command Mask (CANIFnCMASK) register as described in the
“Configuring a Transmit Message Object” on page 538 section, except that the WRNRD bit is set
to specify a write to the message RAM.
2. Program the CANIFnMSK1and CANIFnMSK2 registers as described in the “Configuring a
Transmit Message Object” on page 538 section to configure which bits are used for acceptance
filtering. Note that in order for these bits to be used for acceptance filtering, they must be enabled
by setting the UMASK bit in the CANIFnMCTL register.
3. In the CANIFnMSK2 register, use the MSK[12:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used
for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of
the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and
DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the
acceptance filtering. Also note that in order for these bits to be used for acceptance filtering,
they must be enabled by setting the UMASK bit in the CANIFnMCTL register.
4. Program the CANIFnARB1 and CANIFnARB2 registers as described in the “Configuring a
Transmit Message Object” on page 538 section to program XTD and ID bits for the message
identifier to be received; set the MSGVAL bit to indicate a valid message; and clear the DIR bit
to specify receive.
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5. In the CANIFnMCTL register:
■ Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the
CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering
■ Optionally set the RXIE bit to enable the INTPND bit to be set after a successful reception
■ Clear the RMTEN bit to leave the TXRQST bit unchanged
■ Set the EOB bit for a single message object
■ Set the DLC[3:0] field to specify the size of the data frame
Take care during this configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits.
6. Program the number of the message object to be received in the MNUM field in the CAN IFn
Command Request (CANIFnCRQ) register. Reception of the message object begins as soon
as a matching frame is available on the CAN bus.
When the message handler stores a data frame in the message object, it stores the received Data
Length Code and eight data bytes in the CANIFnDA1, CANIFnDA2, CANIFnDB1, and CANIFnDB2
register. Byte 0 of the CAN data frame is stored in DATA[7:0] in the CANIFnDA1 register. If the
Data Length Code is less than 8, the remaining bytes of the message object are overwritten by
unspecified values.
The CAN mask registers can be used to allow groups of data frames to be received by a message
object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are received by
a message object. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the
CANIFnMSKn register to filter which frames are received. The MXTD bit in the CANIFnMSK2 register
should be set if only 29-bit extended identifiers are expected by this message object.
15.2.11 Handling of Received Message Objects
The CPU may read a received message any time via the CAN Interface registers because the data
consistency is guaranteed by the message handler state machine.
Typically, the CPU first writes 0x007F to the CANIFnCMSK register and then writes the number of
the message object to the CANIFnCRQ register. That combination transfers the whole received
message from the message RAM into the Message Buffer registers (CANIFnMSKn, CANIFnARBn,
and CANIFnMCTL). Additionally, the NEWDAT and INTPND bits are cleared in the message RAM,
acknowledging that the message has been read and clearing the pending interrupt generated by
this message object.
If the message object uses masks for acceptance filtering, the CANIFnARBn registers show the
full, unmasked ID for the received message.
The NEWDAT bit in the CANIFnMCTL register shows whether a new message has been received
since the last time this message object was read. The MSGLST bit in the CANIFnMCTL register
shows whether more than one message has been received since the last time this message object
was read. MSGLST is not automatically cleared, and should be cleared by software after reading its
status.
Using a remote frame, the CPU may request new data from another CAN node on the CAN bus.
Setting the TXRQST bit of a receive object causes the transmission of a remote frame with the receive
object's identifier. This remote frame triggers the other CAN node to start the transmission of the
matching data frame. If the matching data frame is received before the remote frame could be
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transmitted, the TXRQST bit is automatically reset. This prevents the possible loss of data when the
other device on the CAN bus has already transmitted the data slightly earlier than expected.
15.2.11.1 Configuration of a FIFO Buffer
With the exception of the EOB bit in the CANIFnMCTL register, the configuration of receive message
objects belonging to a FIFO buffer is the same as the configuration of a single receive message
object (see “Configuring a Receive Message Object” on page 541). To concatenate two or more
message objects into a FIFO buffer, the identifiers and masks (if used) of these message objects
have to be programmed to matching values. Due to the implicit priority of the message objects, the
message object with the lowest message object number is the first message object in a FIFO buffer.
The EOB bit of all message objects of a FIFO buffer except the last one must be cleared. The EOB
bit of the last message object of a FIFO buffer is set, indicating it is the last entry in the buffer.
15.2.11.2 Reception of Messages with FIFO Buffers
Received messages with identifiers matching to a FIFO buffer are stored starting with the message
object with the lowest message number. When a message is stored into a message object of a
FIFO buffer, the NEWDAT of the CANIFnMCTL register bit of this message object is set. By setting
NEWDAT while EOB is clear, the message object is locked and cannot be written to by the message
handler until the CPU has cleared the NEWDAT bit. Messages are stored into a FIFO buffer until the
last message object of this FIFO buffer is reached. If none of the preceding message objects has
been released by clearing the NEWDAT bit, all further messages for this FIFO buffer will be written
into the last message object of the FIFO buffer and therefore overwrite previous messages.
15.2.11.3 Reading from a FIFO Buffer
When the CPU transfers the contents of a message object from a FIFO buffer by writing its number
to the CANIFnCRQ, the TXRQST and CLRINTPND bits in the CANIFnCMSK register should be set
such that the NEWDAT and INTPEND bits in the CANIFnMCTL register are cleared after the read.
The values of these bits in the CANIFnMCTL register always reflect the status of the message
object before the bits are cleared. To assure the correct function of a FIFO buffer, the CPU should
read out the message objects starting with the message object with the lowest message number.
When reading from the FIFO buffer, the user should be aware that a new received message could
be placed in the location of any message object for which the NEWDAT bit of the CANIFnMCTL
register. As a result, the order of the received messages in the FIFO is not guaranteed. Figure
15-3 on page 544 shows how a set of message objects which are concatenated to a FIFO Buffer
can be handled by the CPU.
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Figure 15-3. Message Objects in a FIFO Buffer
START
No
Yes
Write MNUM to IFn Command Request
(Read Message to IFn Registers,
Reset NEWDAT = 0,
Reset INTPND = 0
MNUM = Interrupt Pointer
Read IFn Message Control
Read Data from IFn Data A,B
NEWDAT = 1
EOB = 1
Read Interrupt Pointer
Status Change
Interrupt Handling
END
Message Interrupt
Yes
MNUM = MNUM + 1
Case Interrupt Pointer else
0x0000 0x8000
No
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15.2.12 Handling of Interrupts
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding their chronological order. The status interrupt has the highest
priority. Among the message interrupts, the message object's interrupt with the lowest message
number has the highest priority. A message interrupt is cleared by clearing the message object's
INTPND bit in the CANIFnMCTL register or by reading the CAN Status (CANSTS) register. The
status Interrupt is cleared by reading the CANSTS register.
The interrupt identifier INTID in the CANINT register indicates the cause of the interrupt. When no
interrupt is pending, the register reads as 0x0000. If the value of the INTID field is different from 0,
then there is an interrupt pending. If the IE bit is set in the CANCTL register, the interrupt line to
the CPU is active. The interrupt line remains active until the INTID field is 0, meaning that all interrupt
sources have been cleared (the cause of the interrupt is reset), or until IE is cleared, which disables
interrupts from the CAN controller.
The INTID field of the CANINT register points to the pending message interrupt with the highest
interrupt priority. The SIE bit in the CANCTL register controls whether a change of the RXOK, TXOK,
and LEC bits in the CANSTS register can cause an interrupt. The EIE bit in the CANCTLregister
controls whether a change of the BOFF and EWARN bits in the CANSTS can cause an interrupt. The
IE bit in the CANCTL controls whether any interrupt from the CAN controller actually generates an
interrupt to the microcontroller's interrupt controller. The CANINT register is updated even when
the IE bit in the CANCTL register is clear, but the interrupt will not be indicated to the CPU.
A value of 0x8000 in the CANINT register indicates that an interrupt is pending because the CAN
module has updated, but not necessarily changed, the CANSTS , indicating that either an error or
status interrupt has been generated. A write access to the CANSTS register can clear the RXOK,
TXOK, and LEC bits in that same register; however, the only way to clear the source of a status
interrupt is to read the CANSTS register.
There are two ways to determine the source of an interrupt during interrupt handling. The first is to
read the INTID bit in the CANINT register to determine the highest priority interrupt that is pending,
and the second is to read the CAN Message Interrupt Pending (CANMSGnINT) register to see
all of the message objects that have pending interrupts.
An interrupt service routine reading the message that is the source of the interrupt may read the
message and clear the message object's INTPND bit at the same time by setting the CLRINTPND
bit in the CANIFnCMSK register. Once the INTPND bit has been cleared, the CANINT register
contains the message number for the next message object with a pending interrupt.
15.2.13 Test Mode
A Test Mode is provided, which allows various diagnostics to be performed. Test Mode is entered
by setting the TEST bit CANCTL register. Once in Test Mode, the TX[1:0], LBACK, SILENT and
BASIC bits in the CAN Test (CANTST) register can be used to put the CAN controller into the
various diagnostic modes. The RX bit in the CANTST register allows monitoring of the CANnRX
signal. All CANTST register functions are disabled when the TEST bit is cleared.
15.2.13.1 Silent Mode
Silent Mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission
of dominant bits (Acknowledge Bits, Error Frames). The CAN Controller is put in Silent Mode setting
the SILENT bit in the CANTST register. In Silent Mode, the CAN controller is able to receive valid
data frames and valid remote frames, but it sends only recessive bits on the CAN bus and it cannot
start a transmission. If the CAN Controller is required to send a dominant bit (ACK bit, overload flag,
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or active error flag), the bit is rerouted internally so that the CAN Controller monitors this dominant
bit, although the CAN bus remains in recessive state.
15.2.13.2 Loopback Mode
Loopback mode is useful for self-test functions. In Loopback Mode, the CAN Controller internally
routes the CANnTX signal on to the CANnRX signal and treats its own transmitted messages as
received messages and stores them (if they pass acceptance filtering) into the message buffer. The
CAN Controller is put in Loopback Mode by setting the LBACK bit in the CANTST register. To be
independent from external stimulation, the CAN Controller ignores acknowledge errors (a recessive
bit sampled in the acknowledge slot of a data/remote frame) in Loopback Mode. The actual value
of the CANnRX signal is disregarded by the CAN Controller. The transmitted messages can be
monitored on the CANnTX signal.
15.2.13.3 Loopback Combined with Silent Mode
Loopback Mode and Silent Mode can be combined to allow the CAN Controller to be tested without
affecting a running CAN system connected to the CANnTX and CANnRX signals. In this mode, the
CANnRX signal is disconnected from the CAN Controller and the CANnTX signal is held recessive.
This mode is enabled by setting both the LBACK and SILENT bits in the CANTST register.
15.2.13.4 Basic Mode
Basic Mode allows the CAN Controller to be operated without the Message RAM. In Basic Mode,
The CANIF1 registers are used as the transmit buffer. The transmission of the contents of the IF1
registers is requested by setting the BUSY bit of the CANIF1CRQ register. The CANIF1 registers
are locked while the BUSY bit is set. The BUSY bit indicates that a transmission is pending. As soon
the CAN bus is idle, the CANIF1 registers are loaded into the shift register of the CAN Controller
and transmission is started. When the transmission has completed, the BUSY bit is cleared and the
locked CANIF1 registers are released. A pending transmission can be aborted at any time by clearing
the BUSY bit in the CANIF1CRQ register while the CANIF1 registers are locked. If the CPU has
cleared the BUSY bit, a possible retransmission in case of lost arbitration or an error is disabled.
The CANIF2 Registers are used as a receive buffer. After the reception of a message, the contents
of the shift register is stored into the CANIF2 registers, without any acceptance filtering. Additionally,
the actual contents of the shift register can be monitored during the message transfer. Each time a
read message object is initiated by setting the BUSY bit of the CANIF2CRQ register, the contents
of the shift register are stored into the CANIF2 registers.
In Basic Mode, all message-object-related control and status bits and of the control bits of the
CANIFnCMSK registers are not evaluated. The message number of the CANIFnCRQ registers is
also not evaluated. In the CANIF2MCTL register, the NEWDAT and MSGLST bits retain their function,
the DLC[3:0] field shows the received DLC, the other control bits are cleared.
Basic Mode is enabled by setting the BASIC bit in the CANTST register.
15.2.13.5 Transmit Control
Software can directly override control of the CANnTX signal in four different ways.
■ CANnTX is controlled by the CAN Controller
■ The sample point is driven on the CANnTX signal to monitor the bit timing
■ CANnTX drives a low value
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■ CANnTX drives a high value
The last two functions, combined with the readable CAN receive pin CANnRX, can be used to check
the physical layer of the CAN bus.
The Transmit Control function is enabled by programming the TX[1:0] field in the CANTST register.
The three test functions for the CANnTX signal interfere with all CAN protocol functions. TX[1:0]
must be cleared when CAN message transfer or Loopback Mode, Silent Mode, or Basic Mode are
selected.
15.2.14 Bit Timing Configuration Error Considerations
Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the
performance of a CAN network can be reduced significantly. In many cases, the CAN bit
synchronization amends a faulty configuration of the CAN bit timing to such a degree that only
occasionally an error frame is generated. In the case of arbitration, however, when two or more
CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the
transmitters to become error passive. The analysis of such sporadic errors requires a detailed
knowledge of the CAN bit synchronization inside a CAN node and of the CAN nodes' interaction on
the CAN bus.
15.2.15 Bit Time and Bit Rate
The CAN system supports bit rates in the range of lower than 1 Kbps up to 1000 Kbps. Each member
of the CAN network has its own clock generator. The timing parameter of the bit time can be
configured individually for each CAN node, creating a common bit rate even though the CAN nodes'
oscillator periods may be different.
Because of small variations in frequency caused by changes in temperature or voltage and by
deteriorating components, these oscillators are not absolutely stable. As long as the variations
remain inside a specific oscillator's tolerance range, the CAN nodes are able to compensate for the
different bit rates by periodically resynchronizing to the bit stream.
According to the CAN specification, the bit time is divided into four segments (see Figure
15-4 on page 548): the Synchronization Segment, the Propagation Time Segment, the Phase Buffer
Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific, programmable
number of time quanta (see Table 15-1 on page 548). The length of the time quantum (tq), which is
the basic time unit of the bit time, is defined by the CAN controller's input clock (fsys) and the Baud
Rate Prescaler (BRP):
tq = BRP / fsys
The fsys input clock is 8 MHz.
The Synchronization Segment Sync is that part of the bit time where edges of the CAN bus level
are expected to occur; the distance between an edge that occurs outside of Sync and the Sync is
called the phase error of that edge.
The Propagation Time Segment Prop is intended to compensate for the physical delay times within
the CAN network.
The Phase Buffer Segments Phase1 and Phase2 surround the Sample Point.
The (Re-)Synchronization Jump Width (SJW) defines how far a resynchronization may move the
Sample Point inside the limits defined by the Phase Buffer Segments to compensate for edge phase
errors.
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A given bit rate may be met by different bit-time configurations, but for the proper function of the
CAN network, the physical delay times and the oscillator's tolerance range have to be considered.
Figure 15-4. CAN Bit Time
Sync Prop Phase2
Sample
Point
1 Time
Quantum
( t qq )
Nominal CAN Bit Time
a. TSEG1 = Prop + Phase1
b. TSEG2 = Phase2
c. Phase1 = Phase2 or Phase1 + 1 = Phase2
TSEG1a TSEG2b
Phase1 c
Table 15-1. CAN Protocol Rangesa
Parameter Range Remark
Defines the length of the time quantum tq. The CANBRPE register can
be used to extend the range to 1024.
BRP [1 .. 64]
Sync 1 tq Fixed length, synchronization of bus input to system clock
Prop [1 .. 8] tq Compensates for the physical delay times
Phase1 [1 .. 8] tq May be lengthened temporarily by synchronization
Phase2 [1 .. 8] tq May be shortened temporarily by synchronization
SJW [1 .. 4] tq May not be longer than either Phase Buffer Segment
a. This table describes the minimum programmable ranges required by the CAN protocol.
The bit timing configuration is programmed in two register bytes in the CANBIT register. In the
CANBIT register, the four components TSEG2, TSEG1, SJW, and BRP have to be programmed to a
numerical value that is one less than its functional value; so instead of values in the range of [1..n],
values in the range of [0..n-1] are programmed. That way, for example, SJW (functional range of
[1..4]) is represented by only two bits in the SJW bit field. Table 15-2 shows the relationship between
the CANBIT register values and the parameters.
Table 15-2. CANBIT Register Values
CANBIT Register Field Setting
TSEG2 Phase2 - 1
TSEG1 Prop + Phase1 - 1
SJW SJW - 1
BRP BRP
Therefore, the length of the bit time is (programmed values):
[TSEG1 + TSEG2 + 3] × tq
or (functional values):
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[Sync + Prop + Phase1 + Phase2] × tq
The data in the CANBIT register is the configuration input of the CAN protocol controller. The baud
rate prescaler (configured by the BRP field) defines the length of the time quantum, the basic time
unit of the bit time; the bit timing logic (configured by TSEG1, TSEG2, and SJW) defines the number
of time quanta in the bit time.
The processing of the bit time, the calculation of the position of the sample point, and occasional
synchronizations are controlled by the CAN controller and are evaluated once per time quantum.
The CAN controller translates messages to and from frames. In addition, the controller generates
and discards the enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks
the CRC code, performs the error management, and decides which type of synchronization is to be
used. The bit value is received or transmitted at the sample point. The information processing time
(IPT) is the time after the sample point needed to calculate the next bit to be transmitted on the CAN
bus. The IPT includes any of the following: retrieving the next data bit, handling a CRC bit, determining
if bit stuffing is required, generating an error flag or simply going idle.
The IPT is application-specific but may not be longer than 2 tq; the CAN's IPT is 0 tq. Its length is
the lower limit of the programmed length of Phase2. In case of synchronization, Phase2 may be
shortened to a value less than IPT, which does not affect bus timing.
15.2.16 Calculating the Bit Timing Parameters
Usually, the calculation of the bit timing configuration starts with a required bit rate or bit time. The
resulting bit time (1/bit rate) must be an integer multiple of the system clock period.
The bit time may consist of 4 to 25 time quanta. Several combinations may lead to the required bit
time, allowing iterations of the following steps.
The first part of the bit time to be defined is Prop. Its length depends on the delay times measured
in the system. A maximum bus length as well as a maximum node delay has to be defined for
expandable CAN bus systems. The resulting time for Prop is converted into time quanta (rounded
up to the nearest integer multiple of tq).
Sync is 1 tq long (fixed), which leaves (bit time - Prop - 1) tq for the two Phase Buffer Segments. If
the number of remaining tq is even, the Phase Buffer Segments have the same length, that is,
Phase2 = Phase1, else Phase2 = Phase1 + 1.
The minimum nominal length of Phase2 has to be regarded as well. Phase2 may not be shorter
than the CAN controller's Information Processing Time, which is, depending on the actual
implementation, in the range of [0..2] tq.
The length of the synchronization jump width is set to the least of 4, Phase1 or Phase2.
The oscillator tolerance range necessary for the resulting configuration is calculated by the formula
given below:
(1 − df) × fnom ≤ fosc ≤ (1 + df) × fnom
( )
2 (13 _ 2)
_ 1, _ 2 min
tbit Phase Seg
Phase seg Phase seg
df
× × −
≤
df max = 2 × df × fnom
where:
■ df = Maximum tolerance of oscillator frequency
■ fosc = Actual oscillator frequency
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■ fnom = Nominal oscillator frequency
Max(i1mu−mdfrfeq)u×enfcyntoolmera≤ncefomsucst ta≤ke(1int+o adcfco)un×t tfhneofomllowing formulas:
( )
2 (13 _ 2)
_ 1, _ 2 min
tbit Phase Seg
Phase seg Phase seg
df
× × −
≤
df max = 2 × df × fnom
(1 − df) × fnom ≤ fosc ≤ (1 + df) × fnom
( )
2 (13 _ 2)
_ 1, _ 2 min
tbit Phase Seg
Phase seg Phase seg
df
× × −
≤
df max = 2 × df × fnom
where:
■ Phase1 and Phase2 are from Table 15-1 on page 548
■ tbit = Bit Time
■ dfmax = Maximum difference between two oscillators
If more than one configuration is possible, that configuration allowing the highest oscillator tolerance
range should be chosen.
CAN nodes with different system clocks require different configurations to come to the same bit
rate. The calculation of the propagation time in the CAN network, based on the nodes with the
longest delay times, is done once for the whole network.
The CAN system's oscillator tolerance range is limited by the node with the lowest tolerance range.
The calculation may show that bus length or bit rate have to be decreased or that the oscillator
frequencies' stability has to be increased in order to find a protocol-compliant configuration of the
CAN bit timing.
15.2.16.1 Example for Bit Timing at High Baud Rate
In this example, the frequency of CAN clock is 8 MHz, and the bit rate is 1 Mbps.
bit time = 1 μs = n * tq = 8 * tq
tq = 125 ns
tq = (Baud rate Prescaler)/CAN Clock
Baud rate Prescaler = tq * CAN Clock
Baud rate Prescaler = 125E-9 * 8E6 = 1
tSync = 1 * tq = 125 ns \\fixed at 1 time quanta
delay of bus driver 50 ns
delay of receiver circuit 30 ns
delay of bus line (40m) 220 ns
tProp 375 ns = 3 * tq \\375 is next integer multiple of tq
bit time = tSync + tTSeg1 + tTSeg2 = 8 * tq
bit time = tSync + tProp + tPhase 1 + tPhase2
tPhase 1 + tPhase2 = bit time - tSync - tProp
tPhase 1 + tPhase2 = (8 * tq) - (1 * tq) - (3 * tq)
tPhase 1 + tPhase2 = 4 * tq
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tPhase1 = 2 * tq
tPhase2 = 2 * tq \\tPhase2 = tPhase1
tTSeg1 = tProp + tPhase1
tTSeg1 = (3 * tq) + (2 * tq)
tTSeg1 = 5 * tq
tTSeg2 = tPhase2
tTSeg2 = (Information Processing Time + 2) × tq
tTSeg2 = 2 * tq \\Assumes IPT=0
tSJW = 2 * tq \\Least of 4, Phase1 and Phase2 = 1
In the above example, the bit field values for the CANBIT register are:
= TSeg2 -1
= 2-1
= 1
TSEG2
= TSeg1 -1
= 5-1
= 4
TSEG1
= SJW -1
= 2-1
= 1
SJW
= Baud rate prescaler - 1
= 1-1
=0
BRP
The final value programmed into the CANBIT register = 0x1440.
15.2.16.2 Example for Bit Timing at Low Baud Rate
In this example, the frequency of the CAN clock is 8 MHz, and the bit rate is 100 Kbps.
bit time = 10 μs = n * tq = 10 * tq
tq = 1 μs
tq = (Baud rate Prescaler)/CAN Clock
Baud rate Prescaler = tq * CAN Clock
Baud rate Prescaler = 1E-6 * 8E6 = 8
tSync = 1 * tq = 1 μs \\fixed at 1 time quanta
delay of bus driver 200 ns
delay of receiver circuit 80 ns
delay of bus line (40m) 220 ns
tProp 1 μs = 1 * tq \\1 μs is next integer multiple of tq
bit time = tSync + tTSeg1 + tTSeg2 = 10 * tq
bit time = tSync + tProp + tPhase 1 + tPhase2
tPhase 1 + tPhase2 = bit time - tSync - tProp
tPhase 1 + tPhase2 = (10 * tq) - (1 * tq) - (1 * tq)
tPhase 1 + tPhase2 = 8 * tq
tPhase1 = 4 * tq
tPhase2 = 4 * tq \\tPhase2 = tPhase1
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tTSeg1 = tProp + tPhase1
tTSeg1 = (1 * tq) + (4 * tq)
tTSeg1 = 5 * tq
tTSeg2 = tPhase2
tTSeg2 = (Information Processing Time + 4) * tq
tTSeg2 = 4 * tq \\Assumes IPT=0
tSJW = 4 * tq \\Least of 4, Phase1, and Phase2
= TSeg2 -1
= 4-1
= 3
TSEG2
= TSeg1 -1
= 5-1
= 4
TSEG1
= SJW -1
= 4-1
= 3
SJW
= Baud rate prescaler - 1
= 8-1
= 7
BRP
The final value programmed into the CANBIT register = 0x34C7.
15.3 Register Map
Table 15-3 on page 552 lists the registers. All addresses given are relative to the CAN base address
of:
■ CAN0: 0x4004.0000
■ CAN1: 0x4004.1000
Note that the CAN module clock must be enabled before the registers can be programmed (see
page 210). There must be a delay of 3 system clocks after the CAN module clock is enabled before
any CAN module registers are accessed.
Table 15-3. CAN Register Map
See
Offset Name Type Reset Description page
0x000 CANCTL R/W 0x0000.0001 CAN Control 555
0x004 CANSTS R/W 0x0000.0000 CAN Status 557
0x008 CANERR RO 0x0000.0000 CAN Error Counter 559
0x00C CANBIT R/W 0x0000.2301 CAN Bit Timing 560
0x010 CANINT RO 0x0000.0000 CAN Interrupt 561
0x014 CANTST R/W 0x0000.0000 CAN Test 562
0x018 CANBRPE R/W 0x0000.0000 CAN Baud Rate Prescaler Extension 564
0x020 CANIF1CRQ R/W 0x0000.0001 CAN IF1 Command Request 565
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Table 15-3. CAN Register Map (continued)
See
Offset Name Type Reset Description page
0x024 CANIF1CMSK R/W 0x0000.0000 CAN IF1 Command Mask 566
0x028 CANIF1MSK1 R/W 0x0000.FFFF CAN IF1 Mask 1 568
0x02C CANIF1MSK2 R/W 0x0000.FFFF CAN IF1 Mask 2 569
0x030 CANIF1ARB1 R/W 0x0000.0000 CAN IF1 Arbitration 1 570
0x034 CANIF1ARB2 R/W 0x0000.0000 CAN IF1 Arbitration 2 571
0x038 CANIF1MCTL R/W 0x0000.0000 CAN IF1 Message Control 572
0x03C CANIF1DA1 R/W 0x0000.0000 CAN IF1 Data A1 574
0x040 CANIF1DA2 R/W 0x0000.0000 CAN IF1 Data A2 574
0x044 CANIF1DB1 R/W 0x0000.0000 CAN IF1 Data B1 574
0x048 CANIF1DB2 R/W 0x0000.0000 CAN IF1 Data B2 574
0x080 CANIF2CRQ R/W 0x0000.0001 CAN IF2 Command Request 565
0x084 CANIF2CMSK R/W 0x0000.0000 CAN IF2 Command Mask 566
0x088 CANIF2MSK1 R/W 0x0000.FFFF CAN IF2 Mask 1 568
0x08C CANIF2MSK2 R/W 0x0000.FFFF CAN IF2 Mask 2 569
0x090 CANIF2ARB1 R/W 0x0000.0000 CAN IF2 Arbitration 1 570
0x094 CANIF2ARB2 R/W 0x0000.0000 CAN IF2 Arbitration 2 571
0x098 CANIF2MCTL R/W 0x0000.0000 CAN IF2 Message Control 572
0x09C CANIF2DA1 R/W 0x0000.0000 CAN IF2 Data A1 574
0x0A0 CANIF2DA2 R/W 0x0000.0000 CAN IF2 Data A2 574
0x0A4 CANIF2DB1 R/W 0x0000.0000 CAN IF2 Data B1 574
0x0A8 CANIF2DB2 R/W 0x0000.0000 CAN IF2 Data B2 574
0x100 CANTXRQ1 RO 0x0000.0000 CAN Transmission Request 1 575
0x104 CANTXRQ2 RO 0x0000.0000 CAN Transmission Request 2 575
0x120 CANNWDA1 RO 0x0000.0000 CAN New Data 1 576
0x124 CANNWDA2 RO 0x0000.0000 CAN New Data 2 576
0x140 CANMSG1INT RO 0x0000.0000 CAN Message 1 Interrupt Pending 577
0x144 CANMSG2INT RO 0x0000.0000 CAN Message 2 Interrupt Pending 577
0x160 CANMSG1VAL RO 0x0000.0000 CAN Message 1 Valid 578
0x164 CANMSG2VAL RO 0x0000.0000 CAN Message 2 Valid 578
15.4 CAN Register Descriptions
The remainder of this section lists and describes the CAN registers, in numerical order by address
offset. There are two sets of Interface Registers that are used to access the Message Objects in
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the Message RAM: CANIF1x and CANIF2x. The function of the two sets are identical and are used
to queue transactions.
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Register 1: CAN Control (CANCTL), offset 0x000
This control register initializes the module and enables test mode and interrupts.
The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting
or clearing INIT. If the device goes bus-off, it sets INIT, stopping all bus activities. Once INIT
has been cleared by the CPU, the device then waits for 129 occurrences of Bus Idle (129 * 11
consecutive High bits) before resuming normal operations. At the end of the bus-off recovery
sequence, the Error Management Counters are reset.
During the waiting time after INIT is cleared, each time a sequence of 11 High bits has been
monitored, a BITERROR0 code is written to the CANSTS register (the LEC field = 0x5), enabling
the CPU to readily check whether the CAN bus is stuck Low or continuously disturbed, and to monitor
the proceeding of the bus-off recovery sequence.
CAN Control (CANCTL)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x000
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TEST CCE DAR reserved EIE SIE IE INIT
Type RO RO RO RO RO RO RO RO R/W R/W R/W RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0000.00
Test Mode Enable
0: Normal operation
1: Test mode
7 TEST R/W 0
Configuration Change Enable
0: Do not allow write access to the CANBIT register.
1: Allow write access to the CANBIT register if the INIT bit is 1.
6 CCE R/W 0
Disable Automatic-Retransmission
0: Auto-retransmission of disturbed messages is enabled.
1: Auto-retransmission is disabled.
5 DAR R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4 reserved RO 0
Error Interrupt Enable
0: Disabled. No error status interrupt is generated.
1: Enabled. A change in the BOFF or EWARN bits in the CANSTS register
generates an interrupt.
3 EIE R/W 0
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Bit/Field Name Type Reset Description
Status Interrupt Enable
0: Disabled. No status interrupt is generated.
1: Enabled. An interrupt is generated when a message has successfully
been transmitted or received, or a CAN bus error has been detected. A
change in the TXOK, RXOK or LEC bits in the CANSTS register generates
an interrupt.
2 SIE R/W 0
CAN Interrupt Enable
0: Interrupts disabled.
1: Interrupts enabled.
1 IE R/W 0
Initialization
0: Normal operation.
1: Initialization started.
0 INIT R/W 1
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Register 2: CAN Status (CANSTS), offset 0x004
Important: Use caution when reading this register. Performing a read may change bit status.
The status register contains information for interrupt servicing such as Bus-Off, error count threshold,
and error types.
The LEC field holds the code that indicates the type of the last error to occur on the CAN bus. This
field is cleared when a message has been transferred (reception or transmission) without error. The
unused error code 7 may be written by the CPU to manually set this field to an invalid error so that
it can be checked for a change later.
An error interrupt is generated by the BOFF and EWARN bits and a status interrupt is generated by
the RXOK, TXOK, and LEC bits, if the corresponding enable bits in the CAN Control (CANCTL)
register are set. A change of the EPASS bit or a write to the RXOK, TXOK, or LEC bits does not
generate an interrupt.
Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register, if it is
pending.
CAN Status (CANSTS)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BOFF EWARN EPASS RXOK TXOK LEC
Type RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0000.00
Bus-Off Status
0: CAN controller is not in bus-off state.
1: CAN controller is in bus-off state.
7 BOFF RO 0
Warning Status
0: Both error counters are below the error warning limit of 96.
1: At least one of the error counters has reached the error warning limit
of 96.
6 EWARN RO 0
Error Passive
0: The CAN module is in the Error Active state, that is, the receive or
transmit error count is less than or equal to 127.
1: The CAN module is in the Error Passive state, that is, the receive or
transmit error count is greater than 127.
5 EPASS RO 0
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Bit/Field Name Type Reset Description
Received a Message Successfully
0: Since this bit was last cleared, no message has been successfully
received.
1: Since this bit was last cleared, a message has been successfully
received, independent of the result of the acceptance filtering.
This bit is never cleared by the CAN module.
4 RXOK R/W 0
Transmitted a Message Successfully
0: Since this bit was last cleared, no message has been successfully
transmitted.
1: Since this bit was last cleared, a message has been successfully
transmitted error-free and acknowledged by at least one other node.
This bit is never cleared by the CAN module.
3 TXOK R/W 0
Last Error Code
This is the type of the last error to occur on the CAN bus.
Value Definition
0x0 No Error
Stuff Error
More than 5 equal bits in a sequence have occurred in a part
of a received message where this is not allowed.
0x1
Format Error
A fixed format part of the received frame has the wrong
format.
0x2
ACK Error
The message transmitted was not acknowledged by another
node.
0x3
Bit 1 Error
When a message is transmitted, the CAN controller monitors
the data lines to detect any conflicts. When the arbitration
field is transmitted, data conflicts are a part of the arbitration
protocol. When other frame fields are transmitted, data
conflicts are considered errors.
A Bit 1 Error indicates that the device wanted to send a High
level (logical 1) but the monitored bus value was Low (logical
0).
0x4
Bit 0 Error
A Bit 0 Error indicates that the device wanted to send a Low
level (logical 0), but the monitored bus value was High (logical
1).
During bus-off recovery, this status is set each time a
sequence of 11 High bits has been monitored. This enables
the CPU to monitor the proceeding of the bus-off recovery
sequence without any disturbances to the bus.
0x5
CRC Error
The CRC checksum was incorrect in the received message,
indicating that the calculated value received did not match
the calculated CRC of the data.
0x6
No Event
When the LEC bit shows this value, no CAN bus event was
detected since the CPU wrote this value to LEC.
0x7
2:0 LEC R/W 0x0
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Register 3: CAN Error Counter (CANERR), offset 0x008
This register contains the error counter values, which can be used to analyze the cause of an error.
CAN Error Counter (CANERR)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x008
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RP REC TEC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Received Error Passive
0: The Receive Error counter is below the Error Passive level (127 or
less).
1: The Receive Error counter has reached the Error Passive level (128
or greater).
15 RP RO 0
Receive Error Counter
State of the receiver error counter (0 to 127).
14:8 REC RO 0x00
Transmit Error Counter
State of the transmit error counter (0 to 255).
7:0 TEC RO 0x00
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Register 4: CAN Bit Timing (CANBIT), offset 0x00C
This register is used to program the bit width and bit quantum. Values are programmed to the system
clock frequency. This register is write-enabled by setting the CCE and INIT bits in the CANCTL
register. See “Bit Time and Bit Rate” on page 547 for more information.
CAN Bit Timing (CANBIT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x00C
Type R/W, reset 0x0000.2301
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TSEG2 TSEG1 SJW BRP
Type RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:15 reserved RO 0x0000
Time Segment after Sample Point
0x00-0x07: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, a reset value of 0x2 defines that there is 3 (2+1) bit
time quanta defined for Phase_Seg2 (see Figure 15-4 on page 548).
The bit time quanta is defined by the BRP field.
14:12 TSEG2 R/W 0x2
Time Segment Before Sample Point
0x00-0x0F: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, the reset value of 0x3 defines that there is 4 (3+1) bit
time quanta defined for Phase_Seg1 (see Figure 15-4 on page 548).
The bit time quanta is define by the BRP field.
11:8 TSEG1 R/W 0x3
(Re)Synchronization Jump Width
0x00-0x03: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
During the start of frame (SOF), if the CAN controller detects a phase
error (misalignment), it can adjust the length of TSEG2 or TSEG1 by the
value in SJW. So the reset value of 0 adjusts the length by 1 bit time
quanta.
7:6 SJW R/W 0x0
Baud Rate Prescaler
The value by which the oscillator frequency is divided for generating the
bit time quanta. The bit time is built up from a multiple of this quantum.
0x00-0x03F: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
BRP defines the number of CAN clock periods that make up 1 bit time
quanta, so the reset value is 2 bit time quanta (1+1).
The CANBRPE register can be used to further divide the bit time.
5:0 BRP R/W 0x1
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Register 5: CAN Interrupt (CANINT), offset 0x010
This register indicates the source of the interrupt.
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding the order in which the interrupts occurred. An interrupt remains
pending until the CPU has cleared it. If the INTID field is not 0x0000 (the default) and the IE bit in
the CANCTL register is set, the interrupt is active. The interrupt line remains active until the INTID
field is cleared by reading the CANSTS register, or until the IE bit in the CANCTL register is cleared.
Note: Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register,
if it is pending.
CAN Interrupt (CANINT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x010
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTID
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Interrupt Identifier
The number in this field indicates the source of the interrupt.
Value Definition
0x0000 No interrupt pending
Number of the message object that
caused the interrupt
0x0001-0x0020
0x0021-0x7FFF Reserved
0x8000 Status Interrupt
0x8001-0xFFFF Reserved
15:0 INTID RO 0x0000
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Register 6: CAN Test (CANTST), offset 0x014
This is the test mode register for self-test and external pin access. It is write-enabled by setting the
TEST bit in the CANCTL register. Different test functions may be combined, however, CAN transfers
will be affected if the TX bits in this register are not zero.
CAN Test (CANTST)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RX TX LBACK SILENT BASIC reserved
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0000.00
Receive Observation
Displays the value on the CANnRx pin.
7 RX RO 0
Transmit Control
Overrides control of the CANnTx pin.
Value Description
CAN Module Control
CANnTx is controlled by the CAN module; default
operation
0x0
Sample Point
The sample point is driven on the CANnTx signal. This
mode is useful to monitor bit timing.
0x1
Driven Low
CANnTx drives a low value. This mode is useful for
checking the physical layer of the CAN bus.
0x2
Driven High
CANnTx drives a high value. This mode is useful for
checking the physical layer of the CAN bus.
0x3
6:5 TX R/W 0x0
Loopback Mode
0: Disabled.
1: Enabled. In loopback mode, the data from the transmitter is routed
into the receiver. Any data on the receive input is ignored.
4 LBACK R/W 0
Silent Mode
Do not transmit data; monitor the bus. Also known as Bus Monitor mode.
0: Disabled.
1: Enabled.
3 SILENT R/W 0
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Bit/Field Name Type Reset Description
Basic Mode
0: Disabled.
1: Use CANIF1 registers as transmit buffer, and use CANIF2 registers
as receive buffer.
2 BASIC R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1:0 reserved RO 0x0
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Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018
This register is used to further divide the bit time set with the BRP bit in the CANBIT register. It is
write-enabled by setting the CCE bit in the CANCTL register.
CAN Baud Rate Prescaler Extension (CANBRPE)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x018
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BRPE
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x0000.000
Baud Rate Prescaler Extension
0x00-0x0F: Extend the BRP bit in the CANBIT register to values up to
1023. The actual interpretation by the hardware is one more than the
value programmed by BRPE (MSBs) and BRP (LSBs).
3:0 BRPE R/W 0x0
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Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080
A message transfer is started as soon as there is a write of the message object number to the MNUM
field when the TXRQST bit in the CANIF1MCTL register is set. With this write operation, the BUSY
bit is automatically set to indicate that a transfer between the CAN Interface Registers and the
internal message RAM is in progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer
between the interface register and the message RAM completes, which then clears the BUSY bit.
CAN IF1 Command Request (CANIF1CRQ)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x020
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY reserved MNUM
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Busy Flag
0: Cleared when read/write action has finished.
1: Set when a write occurs to the message number in this register.
15 BUSY RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14:6 reserved RO 0x00
Message Number
Selects one of the 32 message objects in the message RAM for data
transfer. The message objects are numbered from 1 to 32.
Value Description
Reserved
0 is not a valid message number; it is interpreted
as 0x20, or object 32.
0x00
Message Number
Indicates specified message object 1 to 32.
0x01-0x20
Reserved
Not a valid message number; values are shifted and
it is interpreted as 0x01-0x1F.
0x21-0x3F
5:0 MNUM R/W 0x01
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Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084
Reading the Command Mask registers provides status for various functions. Writing to the Command
Mask registers specifies the transfer direction and selects which buffer registers are the source or
target of the data transfer.
Note that when a read from the message object buffer occurs when the WRNRD bit is clear and the
CLRINTPND and/or NEWDAT bits are set, the interrupt pending and/or new data flags in the message
object buffer are cleared.
CAN IF1 Command Mask (CANIF1CMSK)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x024
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAA DATAB NEWDAT /
TXRQST
reserved WRNRD MASK ARB CONTROL CLRINTPND
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0000.00
Write, Not Read
Transfer the message object address specified by the CAN Command
Request (CANIFnCRQ) register to the CAN message buffer registers.
Note: Interrupt pending and new data conditions in the message
buffer can be cleared by reading from the buffer (WRNRD = 0)
when the CLRINTPND and/or NEWDAT bits are set.
7 WRNRD R/W 0
Access Mask Bits
0: Mask bits unchanged.
1: Transfer IDMASK + DIR + MXTD of the message object into the
Interface registers.
6 MASK R/W 0
Access Arbitration Bits
0: Arbitration bits unchanged.
1: Transfer ID + DIR + XTD + MSGVAL of the message object into the
Interface registers.
5 ARB R/W 0
Access Control Bits
0: Control bits unchanged.
1: Transfer control bits from the CANIFnMCTL register into the Interface
registers.
4 CONTROL R/W 0
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Bit/Field Name Type Reset Description
Clear Interrupt Pending Bit
If WRNRD is set, this bit controls whether the INTPND bit in the
CANIFnMCTL register is changed.
0: The INTPND bit in the message object remains unchanged.
1: The INTPND bit is cleared in the message object.
If WRNRD is clear and this bit is clear, the interrupt pending status is
transferred from the message buffer into the CANIFnMCTL register.
If WRNRD is clear and this bit is set, the interrupt pending status is cleared
in the message buffer. Note that the value of this bit that is transferred
to the CANIFnMCTL register always reflects the status of the bits before
clearing.
3 CLRINTPND R/W 0
NEWDAT / TXRQST Bit
If WRNRD is set, this bit can act as a TXRQST bit and request a
transmission. Note that when this bit is set, the TXRQST bit in the
CANIFnMCTL register is ignored.
0: Transmission is not requested
1: Begin a transmission
If WRNRD is clear and this bit is clear, the value of the new data status
is transferred from the message buffer into the CANIFnMCTL register.
If WRNRD is clear and this bit is set, the new data status is cleared in the
message buffer. Note that the value of this bit that is transferred to the
CANIFnMCTL register always reflects the status of the bits before
clearing.
2 NEWDAT / TXRQST R/W 0
Access Data Byte 0 to 3
When WRNRD = 1:
0: Data bytes 0-3 are unchanged.
1: Transfer data bytes 0-3 in message object to CANIFnDA1 and
CANIFnDA2.
When WRNRD = 0:
0: Data bytes 0-3 are unchanged.
1: Transfer data bytes 0-3 in CANIFnDA1 and CANIFnDA2 to the
message object.
1 DATAA R/W 0
Access Data Byte 4 to 7
When WRNRD = 1:
0: Data bytes 4-7 are unchanged.
1: Transfer data bytes 4-7 in message object to CANIFnDB1 and
CANIFnDB2.
When WRNRD = 0:
0: Data bytes 4-7 are unchanged.
1: Transfer data bytes 4-7 in CANIFnDB1 and CANIFnDB2 to the
message object.
0 DATAB R/W 0
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Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088
The mask information provided in this register accompanies the data (CANIFnDAn), arbitration
information (CANIFnARBn), and control information (CANIFnMCTL) to the message object in the
message RAM. The mask is used with the ID bit in the CANIFnARBn register for acceptance
filtering. Additional mask information is contained in the CANIFnMSK2 register.
CAN IF1 Mask 1 (CANIF1MSK1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x028
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Identifier Mask
When using a 29-bit identifier, these bits are used for bits [15:0] of the
ID. The MSK field in the CANIFnMSK2 register are used for bits [28:16]
of the ID. When using an 11-bit identifier, these bits are ignored.
0: The corresponding identifier field (ID) in the message object cannot
inhibit the match in acceptance filtering.
1: The corresponding identifier field (ID) is used for acceptance filtering.
15:0 MSK R/W 0xFFFF
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Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C
This register holds extended mask information that accompanies the CANIFnMSK1 register.
CAN IF1 Mask 2 (CANIF1MSK2)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MXTD MDIR reserved MSK
Type R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Mask Extended Identifier
0: The extended identifier bit (XTD in the CANIFnARB2 register) has
no effect on the acceptance filtering.
1: The extended identifier bit XTD is used for acceptance filtering.
15 MXTD R/W 0x1
Mask Message Direction
0: The message direction bit (DIR in the CANIFnARB2 register) has
no effect for acceptance filtering.
1: The message direction bit DIR is used for acceptance filtering.
14 MDIR R/W 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13 reserved RO 0x1
Identifier Mask
When using a 29-bit identifier, these bits are used for bits [28:16] of the
ID. The MSK field in the CANIFnMSK1 register are used for bits [15:0]
of the ID. When using an 11-bit identifier, MSK[12:2] are used for bits
[10:0] of the ID.
0: The corresponding identifier field (ID) in the message object cannot
inhibit the match in acceptance filtering.
1: The corresponding identifier field (ID) is used for acceptance filtering.
12:0 MSK R/W 0xFF
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Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090
These registers hold the identifiers for acceptance filtering.
CAN IF1 Arbitration 1 (CANIF1ARB1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x030
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Message Identifier
This bit field is used with the ID field in the CANIFnARB2 register to
create the message identifier.
When using a 29-bit identifier, bits 15:0 of the CANIFnARB1 register
are [15:0] of the ID, while bits 12:0 of the CANIFnARB2 register are
[28:16] of the ID.
When using an 11-bit identifier, these bits are not used.
15:0 ID R/W 0x0000
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Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094
These registers hold information for acceptance filtering.
CAN IF1 Arbitration 2 (CANIF1ARB2)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x034
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSGVAL XTD DIR ID
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Message Valid
0: The message object is ignored by the message handler.
1: The message object is configured and ready to be considered by the
message handler within the CAN controller.
All unused message objects should have this bit cleared during
initialization and before clearing the INIT bit in the CANCTL register.
The MSGVAL bit must also be cleared before any of the following bits
are modified or if the message object is no longer required: the ID fields
in the CANIFnARBn registers, the XTD and DIR bits in the CANIFnARB2
register, or the DLC field in the CANIFnMCTL register.
15 MSGVAL R/W 0
Extended Identifier
0: An 11-bit Standard Identifier is used for this message object.
1: A 29-bit Extended Identifier is used for this message object.
14 XTD R/W 0
Message Direction
0: Receive. When the TXRQST bit in the CANIFnMCTL register is set,
a remote frame with the identifier of this message object is received.
On reception of a data frame with matching identifier, that message is
stored in this message object.
1: Transmit. When the TXRQST bit in the CANIFnMCTL register is set,
the respective message object is transmitted as a data frame. On
reception of a remote frame with matching identifier, the TXRQST bit of
this message object is set (if RMTEN=1).
13 DIR R/W 0
Message Identifier
This bit field is used with the ID field in the CANIFnARB2 register to
create the message identifier.
When using a 29-bit identifier, ID[15:0] of the CANIFnARB1 register
are [15:0] of the ID, while these bits, ID[12:0], are [28:16] of the ID.
When using an 11-bit identifier, ID[12:2] are used for bits [10:0] of
the ID. The ID field in the CANIFnARB1 register is ignored.
12:0 ID R/W 0x000
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Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098
This register holds the control information associated with the message object to be sent to the
Message RAM.
CAN IF1 Message Control (CANIF1MCTL)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NEWDAT MSGLST INTPND UMASK TXIE RXIE RMTEN TXRQST EOB reserved DLC
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
New Data
0: No new data has been written into the data portion of this message
object by the message handler since the last time this flag was cleared
by the CPU.
1: The message handler or the CPU has written new data into the data
portion of this message object.
15 NEWDAT R/W 0
Message Lost
0 : No message was lost since the last time this bit was cleared by the
CPU.
1: The message handler stored a new message into this object when
NEWDAT was set; the CPU has lost a message.
This bit is only valid for message objects when the DIR bit in the
CANIFnARB2 register clear (receive).
14 MSGLST R/W 0
Interrupt Pending
0: This message object is not the source of an interrupt.
1: This message object is the source of an interrupt. The interrupt
identifier in the CANINT register points to this message object if there
is not another interrupt source with a higher priority.
13 INTPND R/W 0
Use Acceptance Mask
0: Mask ignored.
1: Use mask (MSK, MXTD, and MDIR bits in the CANIFnMSKn registers)
for acceptance filtering.
12 UMASK R/W 0
Transmit Interrupt Enable
0: The INTPND bit in the CANIFnMCTL register is unchanged after a
successful transmission of a frame.
1: The INTPND bit in the CANIFnMCTL register is set after a successful
transmission of a frame.
11 TXIE R/W 0
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Bit/Field Name Type Reset Description
Receive Interrupt Enable
0: The INTPND bit in the CANIFnMCTL register is unchanged after a
successful reception of a frame.
1: The INTPND bit in the CANIFnMCTL register is set after a successful
reception of a frame.
10 RXIE R/W 0
Remote Enable
0: At the reception of a remote frame, the TXRQST bit in the
CANIFnMCTL register is left unchanged.
1: At the reception of a remote frame, the TXRQST bit in the
CANIFnMCTL register is set.
9 RMTEN R/W 0
Transmit Request
0: This message object is not waiting for transmission.
1: The transmission of this message object is requested and is not yet
done.
8 TXRQST R/W 0
End of Buffer
0: Message object belongs to a FIFO Buffer and is not the last message
object of that FIFO Buffer.
1: Single message object or last message object of a FIFO Buffer.
This bit is used to concatenate two or more message objects (up to 32)
to build a FIFO buffer. For a single message object (thus not belonging
to a FIFO buffer), this bit must be set.
7 EOB R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:4 reserved RO 0x0
Data Length Code
Value Description
0x0-0x8 Specifies the number of bytes in the data frame.
0x9-0xF Defaults to a data frame with 8 bytes.
The DLC field in the CANIFnMCTL register of a message object must
be defined the same as in all the corresponding objects with the same
identifier at other nodes. When the message handler stores a data frame,
it writes DLC to the value given by the received message.
3:0 DLC R/W 0x0
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Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8
These registers contain the data to be sent or that has been received. In a CAN data frame, data
byte 0 is the first byte to be transmitted or received and data byte 7 is the last byte to be transmitted
or received. In CAN's serial bit stream, the MSB of each byte is transmitted first.
CAN IF1 Data A1 (CANIF1DA1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x03C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Data
The CANIFnDA1 registers contain data bytes 1 and 0; CANIFnDA2
data bytes 3 and 2; CANIFnDB1 data bytes 5 and 4; and CANIFnDB2
data bytes 7 and 6.
15:0 DATA R/W 0x0000
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Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104
The CANTXRQ1 and CANTXRQ2 registers hold the TXRQST bits of the 32 message objects. By
reading out these bits, the CPU can check which message object has a transmission request pending.
The TXRQST bit of a specific message object can be changed by three sources: (1) the CPU via the
CANIFnMCTL register, (2) the message handler state machine after the reception of a remote
frame, or (3) the message handler state machine after a successful transmission.
The CANTXRQ1 register contains the TXRQST bits of the first 16 message objects in the message
RAM; the CANTXRQ2 register contains the TXRQST bits of the second 16 message objects.
CAN Transmission Request 1 (CANTXRQ1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x100
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXRQST
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Transmission Request Bits
0: The corresponding message object is not waiting for transmission.
1: The transmission of the corresponding message object is requested
and is not yet done.
15:0 TXRQST RO 0x0000
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Register 32: CAN New Data 1 (CANNWDA1), offset 0x120
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124
The CANNWDA1 and CANNWDA2 registers hold the NEWDAT bits of the 32 message objects. By
reading these bits, the CPU can check which message object has its data portion updated. The
NEWDAT bit of a specific message object can be changed by three sources: (1) the CPU via the
CANIFnMCTL register, (2) the message handler state machine after the reception of a data frame,
or (3) the message handler state machine after a successful transmission.
The CANNWDA1 register contains the NEWDAT bits of the first 16 message objects in the message
RAM; the CANNWDA2 register contains the NEWDAT bits of the second 16 message objects.
CAN New Data 1 (CANNWDA1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x120
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NEWDAT
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
New Data Bits
0: No new data has been written into the data portion of the
corresponding message object by the message handler since the last
time this flag was cleared by the CPU.
1: The message handler or the CPU has written new data into the data
portion of the corresponding message object.
15:0 NEWDAT RO 0x0000
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Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144
The CANMSG1INT and CANMSG2INT registers hold the INTPND bits of the 32 message objects.
By reading these bits, the CPU can check which message object has an interrupt pending. The
INTPND bit of a specific message object can be changed through two sources: (1) the CPU via the
CANIFnMCTL register, or (2) the message handler state machine after the reception or transmission
of a frame.
This field is also encoded in the CANINT register.
The CANMSG1INT register contains the INTPND bits of the first 16 message objects in the message
RAM; the CANMSG2INT register contains the INTPND bits of the second 16 message objects.
CAN Message 1 Interrupt Pending (CANMSG1INT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x140
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTPND
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Interrupt Pending Bits
0: The corresponding message object is not the source of an interrupt.
1: The corresponding message object is the source of an interrupt.
15:0 INTPND RO 0x0000
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Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164
The CANMSG1VAL and CANMSG2VAL registers hold the MSGVAL bits of the 32 message objects.
By reading these bits, the CPU can check which message object is valid. The message value of a
specific message object can be changed with the CANIFnMCTL register.
The CANMSG1VAL register contains the MSGVAL bits of the first 16 message objects in the message
RAM; the CANMSG2VAL register contains the MSGVAL bits of the second 16 message objects in
the message RAM.
CAN Message 1 Valid (CANMSG1VAL)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x160
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSGVAL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
Message Valid Bits
0: The corresponding message object is not configured and is ignored
by the message handler.
1: The corresponding message object is configured and should be
considered by the message handler.
15:0 MSGVAL RO 0x0000
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16 Analog Comparators
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
Note: Not all comparators have the option to drive an output pin.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
The Stellaris® Analog Comparators module has the following features:
■ Three independent integrated analog comparators
■ Configurable for output to drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
■ Compare external pin input to external pin input or to internal programmable voltage reference
■ Compare a test voltage against any one of these voltages
– An individual external reference voltage
– A shared single external reference voltage
– A shared internal reference voltage
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16.1 Block Diagram
Figure 16-1. Analog Comparator Module Block Diagram
C2+
C2-
output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 2
ACSTAT2
ACCTL2
C1-
C1+ output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 1
ACSTAT1
ACCTL1
Voltage
Ref
ACREFCTL
output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 0
ACSTAT0
ACCTL0
C0+
internal
bus
C0-
C0o
trigger trigger
trigger trigger
trigger trigger
Interrupt Control
ACRIS
ACMIS
ACINTEN
interrupt
16.2 Functional Description
Important: It is recommended that the Digital-Input enable (the GPIODEN bit in the GPIO module)
for the analog input pin be disabled to prevent excessive current draw from the I/O
pads.
The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT.
VIN- < VIN+, VOUT = 1
VIN- > VIN+, VOUT = 0
As shown in Figure 16-2 on page 581, the input source for VIN- is an external input. In addition to
an external input, input sources for VIN+ can be the +ve input of comparator 0 or an internal reference.
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Figure 16-2. Structure of Comparator Unit
ACCTL
CINV
internal
bus
interrupt
trigger
TrigGen
output
ACSTAT
IntGen
- ve input
1
+ ve input (alternate)
0
+ ve input
2
reference input
A comparator is configured through two status/control registers (ACCTL and ACSTAT ). The internal
reference is configured through one control register (ACREFCTL). Interrupt status and control is
configured through three registers (ACMIS, ACRIS, and ACINTEN).
Typically, the comparator output is used internally to generate controller interrupts. It may also be
used to drive an external pin or generate an analog-to-digital converter (ADC) trigger.
Important: The ASRCP bits in the ACCTLn register must be set before using the analog
comparators.
16.2.1 Internal Reference Programming
The structure of the internal reference is shown in Figure 16-3 on page 581. This is controlled by a
single configuration register (ACREFCTL). Table 16-1 on page 581 shows the programming options
to develop specific internal reference values, to compare an external voltage against a particular
voltage generated internally.
Figure 16-3. Comparator Internal Reference Structure
8R R R
8R
R
•••
•••
0
Decoder
15 14 1
AVDD
EN
internal
reference
VREF
RNG
Table 16-1. Internal Reference Voltage and ACREFCTL Field Values
Output Reference Voltage Based on VREF Field Value
ACREFCTL Register
EN Bit Value RNG Bit Value
0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and
VREF=0 for the least noisy ground reference.
EN=0 RNG=X
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Table 16-1. Internal Reference Voltage and ACREFCTL Field Values (continued)
Output Reference Voltage Based on VREF Field Value
ACREFCTL Register
EN Bit Value RNG Bit Value
Total resistance in ladder is 31 R.
The range of internal reference in this mode is 0.85-2.448 V.
RNG=0
EN=1
Total resistance in ladder is 23 R.
The range of internal reference for this mode is 0-2.152 V.
RNG=1
16.3 Initialization and Configuration
The following example shows how to configure an analog comparator to read back its output value
from an internal register.
1. Enable the analog comparator 0 clock by writing a value of 0x0010.0000 to the RCGC1 register
in the System Control module.
2. In the GPIO module, enable the GPIO port/pin associated with C0- as a GPIO input.
3. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the
value 0x0000.030C.
4. Configure comparator 0 to use the internal voltage reference and to not invert the output by
writing the ACCTL0 register with the value of 0x0000.040C.
5. Delay for some time.
6. Read the comparator output value by reading the ACSTAT0 register’s OVAL value.
Change the level of the signal input on C0- to see the OVAL value change.
16.4 Register Map
Table 16-2 on page 583 lists the comparator registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Analog Comparator base address of 0x4003.C000.
Note that the analog comparator module clock must be enabled before the registers can be
programmed (see page 216). There must be a delay of 3 system clocks after the ADC module clock
is enabled before any ADC module registers are accessed.
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Table 16-2. Analog Comparators Register Map
See
Offset Name Type Reset Description page
0x000 ACMIS R/W1C 0x0000.0000 Analog Comparator Masked Interrupt Status 584
0x004 ACRIS RO 0x0000.0000 Analog Comparator Raw Interrupt Status 585
0x008 ACINTEN R/W 0x0000.0000 Analog Comparator Interrupt Enable 586
0x010 ACREFCTL R/W 0x0000.0000 Analog Comparator Reference Voltage Control 587
0x020 ACSTAT0 RO 0x0000.0000 Analog Comparator Status 0 588
0x024 ACCTL0 R/W 0x0000.0000 Analog Comparator Control 0 589
0x040 ACSTAT1 RO 0x0000.0000 Analog Comparator Status 1 588
0x044 ACCTL1 R/W 0x0000.0000 Analog Comparator Control 1 589
0x060 ACSTAT2 RO 0x0000.0000 Analog Comparator Status 2 588
0x064 ACCTL2 R/W 0x0000.0000 Analog Comparator Control 2 589
16.5 Register Descriptions
The remainder of this section lists and describes the Analog Comparator registers, in numerical
order by address offset.
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Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000
This register provides a summary of the interrupt status (masked) of the comparator.
Analog Comparator Masked Interrupt Status (ACMIS)
Base 0x4003.C000
Offset 0x000
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Comparator 2 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
2 IN2 R/W1C 0
Comparator 1 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
1 IN1 R/W1C 0
Comparator 0 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
0 IN0 R/W1C 0
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Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004
This register provides a summary of the interrupt status (raw) of the comparator.
Analog Comparator Raw Interrupt Status (ACRIS)
Base 0x4003.C000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Comparator 2 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
2.
2 IN2 RO 0
Comparator 1 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
1.
1 IN1 RO 0
Comparator 0 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
0.
0 IN0 RO 0
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Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008
This register provides the interrupt enable for the comparator.
Analog Comparator Interrupt Enable (ACINTEN)
Base 0x4003.C000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Comparator 2 Interrupt Enable
When set, enables the controller interrupt from the comparator 2 output
2 IN2 R/W 0
Comparator 1 Interrupt Enable
When set, enables the controller interrupt from the comparator 1 output.
1 IN1 R/W 0
Comparator 0 Interrupt Enable
When set, enables the controller interrupt from the comparator 0 output.
0 IN0 R/W 0
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Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset
0x010
This register specifies whether the resistor ladder is powered on as well as the range and tap.
Analog Comparator Reference Voltage Control (ACREFCTL)
Base 0x4003.C000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EN RNG reserved VREF
Type RO RO RO RO RO RO R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0x00
Resistor Ladder Enable
The EN bit specifies whether the resistor ladder is powered on. If 0, the
resistor ladder is unpowered. If 1, the resistor ladder is connected to
the analog VDD.
This bit is reset to 0 so that the internal reference consumes the least
amount of power if not used and programmed.
9 EN R/W 0
Resistor Ladder Range
The RNG bit specifies the range of the resistor ladder. If 0, the resistor
ladder has a total resistance of 31 R. If 1, the resistor ladder has a total
resistance of 23 R.
8 RNG R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x00
Resistor Ladder Voltage Ref
The VREF bit field specifies the resistor ladder tap that is passed through
an analog multiplexer. The voltage corresponding to the tap position is
the internal reference voltage available for comparison. See Table
16-1 on page 581 for some output reference voltage examples.
3:0 VREF R/W 0x00
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Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060
These registers specify the current output value of the comparator.
Analog Comparator Status 0 (ACSTAT0)
Base 0x4003.C000
Offset 0x020
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OVAL reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Comparator Output Value
The OVAL bit specifies the current output value of the comparator.
1 OVAL RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064
These registers configure the comparator’s input and output.
Analog Comparator Control 0 (ACCTL0)
Base 0x4003.C000
Offset 0x024
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TOEN ASRCP reserved TSLVAL TSEN ISLVAL ISEN CINV reserved
Type RO RO RO RO R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Trigger Output Enable
The TOEN bit enables the ADC event transmission to the ADC. If 0, the
event is suppressed and not sent to the ADC. If 1, the event is
transmitted to the ADC.
11 TOEN R/W 0
Analog Source Positive
The ASRCP field specifies the source of input voltage to the VIN+ terminal
of the comparator. The encodings for this field are as follows:
Value Function
0x0 Pin value
0x1 Pin value of C0+
0x2 Internal voltage reference
0x3 Reserved
10:9 ASRCP R/W 0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8 reserved RO 0
Trigger Sense Level Value
The TSLVAL bit specifies the sense value of the input that generates
an ADC event if in Level Sense mode. If 0, an ADC event is generated
if the comparator output is Low. Otherwise, an ADC event is generated
if the comparator output is High.
7 TSLVAL R/W 0
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Bit/Field Name Type Reset Description
Trigger Sense
The TSEN field specifies the sense of the comparator output that
generates an ADC event. The sense conditioning is as follows:
Value Function
0x0 Level sense, see TSLVAL
0x1 Falling edge
0x2 Rising edge
0x3 Either edge
6:5 TSEN R/W 0x0
Interrupt Sense Level Value
The ISLVAL bit specifies the sense value of the input that generates
an interrupt if in Level Sense mode. If 0, an interrupt is generated if the
comparator output is Low. Otherwise, an interrupt is generated if the
comparator output is High.
4 ISLVAL R/W 0
Interrupt Sense
The ISEN field specifies the sense of the comparator output that
generates an interrupt. The sense conditioning is as follows:
Value Function
0x0 Level sense, see ISLVAL
0x1 Falling edge
0x2 Rising edge
0x3 Either edge
3:2 ISEN R/W 0x0
Comparator Output Invert
The CINV bit conditionally inverts the output of the comparator. If 0, the
output of the comparator is unchanged. If 1, the output of the comparator
is inverted prior to being processed by hardware.
1 CINV R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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17 Pulse Width Modulator (PWM)
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
The Stellaris® PWM module consists of three PWM generator blocks and a control block. The control
block determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals
(other than being based on the same timer and therefore having the same frequency) or a single
pair of complementary signals with dead-band delays inserted. The output of the PWM generation
blocks are managed by the output control block before being passed to the device pins.
The Stellaris PWM module provides a great deal of flexibility. It can generate simple PWM signals,
such as those required by a simple charge pump. It can also generate paired PWM signals with
dead-band delays, such as those required by a half-H bridge driver. Three generator blocks can
also generate the full six channels of gate controls required by a 3-phase inverter bridge.
Each Stellaris PWM module has the following features:
■ Three PWM generator blocks, each with one 16-bit counter, two PWM comparators, a PWM
signal generator, a dead-band generator, and an interrupt/ADC-trigger selector
■ One fault input in hardware to promote low-latency shutdown
■ One 16-bit counter
– Runs in Down or Up/Down mode
– Output frequency controlled by a 16-bit load value
– Load value updates can be synchronized
– Produces output signals at zero and load value
■ Two PWM comparators
– Comparator value updates can be synchronized
– Produces output signals on match
■ PWM generator
– Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
– Produces two independent PWM signals
■ Dead-band generator
– Produces two PWM signals with programmable dead-band delays suitable for driving a half-H
bridge
– Can be bypassed, leaving input PWM signals unmodified
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■ Flexible output control block with PWM output enable of each PWM signal
– PWM output enable of each PWM signal
– Optional output inversion of each PWM signal (polarity control)
– Optional fault handling for each PWM signal
– Synchronization of timers in the PWM generator blocks
– Synchronization of timer/comparator updates across the PWM generator blocks
– Interrupt status summary of the PWM generator blocks
■ Can initiate an ADC sample sequence
17.1 Block Diagram
Figure 17-1 on page 592 provides the Stellaris PWM module unit diagram and Figure 17-2 on page 593
provides a more detailed diagram of a Stellaris PWM generator. The LM3S2965 controller contains
three generator blocks (PWM0, PWM1, and PWM2) and generates six independent PWM signals
or three paired PWM signals with dead-band delays inserted.
Figure 17-1. PWM Unit Diagram
PWMINTEN
Interrupt
PWMRIS
PWMISC
PWMCTL
Control and
Status
PWMSYNC
PWMSTATUS
PWM
Generator 0
PWM
Generator 1
PWM
Generator 2
PWM 0
PWM 1
PWM 2
PWM 3
PWM 4
PWM 5
PWM
Output
Control
Logic
PWM Clock
System Clock
Interrupts
Triggers
PWM0_A
PWM0_B
PWM1_A
PWM1_B
PWM2_A
PWM2_B
PWM0_Fault
PWM1_Fault
PWM2_Fault
Fault
PWMENABLE
Output
PWMINVERT
PWMFAULT
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Figure 17-2. PWM Module Block Diagram
PWMnCMPA
Comparators
PWMnCMPB
PWMnLOAD
Timer
PWMnCOUNT
PWMnDBCTL
Dead-Band
Generator
PWMnDBRISE
PWMnDBFALL
PWMnCTL
Control
PWM Clock
PWM Generator Block
Signal
Generator
PWMnGENA
PWMnGENB
PWMnINTEN
Interrupt and
Trigger
Generator
PWMnRIS
PWMnISC
Fault(s)
PWMn_A
PWMn_B
Interrupts /
Triggers
PWMn_Fault
cmp A
cmp B
zero
load
dir
PWMnFLTSRC0
Fault
Condition
PWMnMINFLTPER
PWMnFLTSEN
PWMnFLTSTAT0
17.2 Functional Description
17.2.1 PWM Timer
The timer in each PWM generator runs in one of two modes: Count-Down mode or Count-Up/Down
mode. In Count-Down mode, the timer counts from the load value to zero, goes back to the load
value, and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the
load value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode
is used for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used
for generating center-aligned PWM signals.
The timers output three signals that are used in the PWM generation process: the direction signal
(this is always Low in Count-Down mode, but alternates between Low and High in Count-Up/Down
mode), a single-clock-cycle-width High pulse when the counter is zero, and a single-clock-cycle-width
High pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero
pulse is immediately followed by the load pulse.
17.2.2 PWM Comparators
There are two comparators in each PWM generator that monitor the value of the counter; when
either match the counter, they output a single-clock-cycle-width High pulse. When in Count-Up/Down
mode, these comparators match both when counting up and when counting down; they are therefore
qualified by the counter direction signal. These qualified pulses are used in the PWM generation
process. If either comparator match value is greater than the counter load value, then that comparator
never outputs a High pulse.
Figure 17-3 on page 594 shows the behavior of the counter and the relationship of these pulses
when the counter is in Count-Down mode. Figure 17-4 on page 594 shows the behavior of the counter
and the relationship of these pulses when the counter is in Count-Up/Down mode.
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Figure 17-3. PWM Count-Down Mode
Load
Zero
CompB
CompA
Load
Zero
B
A
Dir
ADown
BDown
Figure 17-4. PWM Count-Up/Down Mode
Load
Zero
CompB
CompA
Load
Zero
B
A
Dir
BUp
AUp ADown
BDown
17.2.3 PWM Signal Generator
The PWM generator takes these pulses (qualified by the direction signal), and generates two PWM
signals. In Count-Down mode, there are four events that can affect the PWM signal: zero, load,
match A down, and match B down. In Count-Up/Down mode, there are six events that can affect
the PWM signal: zero, load, match A down, match A up, match B down, and match B up. The match
A or match B events are ignored when they coincide with the zero or load events. If the match A
and match B events coincide, the first signal, PWMA, is generated based only on the match A event,
and the second signal, PWMB, is generated based only on the match B event.
For each event, the effect on each output PWM signal is programmable: it can be left alone (ignoring
the event), it can be toggled, it can be driven Low, or it can be driven High. These actions can be
used to generate a pair of PWM signals of various positions and duty cycles, which do or do not
overlap. Figure 17-5 on page 595 shows the use of Count-Up/Down mode to generate a pair of
center-aligned, overlapped PWM signals that have different duty cycles.
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Figure 17-5. PWM Generation Example In Count-Up/Down Mode
Load
Zero
CompB
CompA
PWMB
PWMA
In this example, the first generator is set to drive High on match A up, drive Low on match A down,
and ignore the other four events. The second generator is set to drive High on match B up, drive
Low on match B down, and ignore the other four events. Changing the value of comparator A
changes the duty cycle of the PWMA signal, and changing the value of comparator B changes the
duty cycle of the PWMB signal.
17.2.4 Dead-Band Generator
The two PWM signals produced by the PWM generator are passed to the dead-band generator. If
disabled, the PWM signals simply pass through unmodified. If enabled, the second PWM signal is
lost and two PWM signals are generated based on the first PWM signal. The first output PWM signal
is the input signal with the rising edge delayed by a programmable amount. The second output
PWM signal is the inversion of the input signal with a programmable delay added between the falling
edge of the input signal and the rising edge of this new signal.
This is therefore a pair of active High signals where one is always High, except for a programmable
amount of time at transitions where both are Low. These signals are therefore suitable for driving
a half-H bridge, with the dead-band delays preventing shoot-through current from damaging the
power electronics. Figure 17-6 on page 595 shows the effect of the dead-band generator on an input
PWM signal.
Figure 17-6. PWM Dead-Band Generator
Input
PWMA
PWMB
Rising Edge
Delay
Falling Edge
Delay
17.2.5 Interrupt/ADC-Trigger Selector
The PWM generator also takes the same four (or six) counter events and uses them to generate
an interrupt or an ADC trigger. Any of these events or a set of these events can be selected as a
source for an interrupt; when any of the selected events occur, an interrupt is generated. Additionally,
the same event, a different event, the same set of events, or a different set of events can be selected
as a source for an ADC trigger; when any of these selected events occur, an ADC trigger pulse is
generated. The selection of events allows the interrupt or ADC trigger to occur at a specific position
within the PWM signal. Note that interrupts and ADC triggers are based on the raw events; delays
in the PWM signal edges caused by the dead-band generator are not taken into account.
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17.2.6 Synchronization Methods
There is a global reset capability that can synchronously reset any or all of the counters in the PWM
generators. If multiple PWM generators are configured with the same counter load value, this can
be used to guarantee that they also have the same count value (this does imply that the PWM
generators must be configured before they are synchronized). With this, more than two PWM signals
can be produced with a known relationship between the edges of those signals since the counters
always have the same values.
The counter load values and comparator match values of the PWM generator can be updated in
two ways. The first is immediate update mode, where a new value is used as soon as the counter
reaches zero. By waiting for the counter to reach zero, a guaranteed behavior is defined, and overly
short or overly long output PWM pulses are prevented.
The other update method is synchronous, where the new value is not used until a global synchronized
update signal is asserted, at which point the new value is used as soon as the counter reaches
zero. This second mode allows multiple items in multiple PWM generators to be updated
simultaneously without odd effects during the update; everything runs from the old values until a
point at which they all run from the new values. The Update mode of the load and comparator match
values can be individually configured in each PWM generator block. It typically makes sense to use
the synchronous update mechanism across PWM generator blocks when the timers in those blocks
are synchronized, though this is not required in order for this mechanism to function properly.
17.2.7 Fault Conditions
There are two external conditions that affect the PWM block; the signal input on the Fault pin and
the stalling of the controller by a debugger. There are two mechanisms available to handle such
conditions: the output signals can be forced into an inactive state and/or the PWM timers can be
stopped.
Each output signal has a fault bit. If set, a fault input signal causes the corresponding output signal
to go into the inactive state. If the inactive state is a safe condition for the signal to be in for an
extended period of time, this keeps the output signal from driving the outside world in a dangerous
manner during the fault condition. A fault condition can also generate a controller interrupt.
Each PWM generator can also be configured to stop counting during a stall condition. The user can
select for the counters to run until they reach zero then stop, or to continue counting and reloading.
A stall condition does not generate a controller interrupt.
17.2.8 Output Control Block
With each PWM generator block producing two raw PWM signals, the output control block takes
care of the final conditioning of the PWM signals before they go to the pins. Via a single register,
the set of PWM signals that are actually enabled to the pins can be modified; this can be used, for
example, to perform commutation of a brushless DC motor with a single register write (and without
modifying the individual PWM generators, which are modified by the feedback control loop). Similarly,
fault control can disable any of the PWM signals as well. A final inversion can be applied to any of
the PWM signals, making them active Low instead of the default active High.
17.3 Initialization and Configuration
The following example shows how to initialize the PWM Generator 0 with a 25-KHz frequency, and
with a 25% duty cycle on the PWM0 pin and a 75% duty cycle on the PWM1 pin. This example assumes
the system clock is 20 MHz.
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1. Enable the PWM clock by writing a value of 0x0010.0000 to the RCGC0 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register.
4. Configure the Run-Mode Clock Configuration (RCC) register in the System Control module
to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000).
5. Configure the PWM generator for countdown mode with immediate updates to the parameters.
■ Write the PWM0CTL register with a value of 0x0000.0000.
■ Write the PWM0GENA register with a value of 0x0000.008C.
■ Write the PWM0GENB register with a value of 0x0000.080C.
6. Set the period. For a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM
clock source is 10 MHz; the system clock divided by 2. This translates to 400 clock ticks per
period. Use this value to set the PWM0LOAD register. In Count-Down mode, set the Load field
in the PWM0LOAD register to the requested period minus one.
■ Write the PWM0LOAD register with a value of 0x0000.018F.
7. Set the pulse width of the PWM0 pin for a 25% duty cycle.
■ Write the PWM0CMPA register with a value of 0x0000.012B.
8. Set the pulse width of the PWM1 pin for a 75% duty cycle.
■ Write the PWM0CMPB register with a value of 0x0000.0063.
9. Start the timers in PWM generator 0.
■ Write the PWM0CTL register with a value of 0x0000.0001.
10. Enable PWM outputs.
■ Write the PWMENABLE register with a value of 0x0000.0003.
17.4 Register Map
Table 17-1 on page 598 lists the PWM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the PWM base address of 0x4002.8000. Note that the PWM module
clock must be enabled before the registers can be programmed (see page 210). There must be a
delay of 3 system clocks after the PWM module clock is enabled before any PWM module registers
are accessed.
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Table 17-1. PWM Register Map
See
Offset Name Type Reset Description page
0x000 PWMCTL R/W 0x0000.0000 PWM Master Control 600
0x004 PWMSYNC R/W 0x0000.0000 PWM Time Base Sync 601
0x008 PWMENABLE R/W 0x0000.0000 PWM Output Enable 602
0x00C PWMINVERT R/W 0x0000.0000 PWM Output Inversion 603
0x010 PWMFAULT R/W 0x0000.0000 PWM Output Fault 604
0x014 PWMINTEN R/W 0x0000.0000 PWM Interrupt Enable 605
0x018 PWMRIS RO 0x0000.0000 PWM Raw Interrupt Status 606
0x01C PWMISC R/W1C 0x0000.0000 PWM Interrupt Status and Clear 607
0x020 PWMSTATUS RO 0x0000.0000 PWM Status 608
0x040 PWM0CTL R/W 0x0000.0000 PWM0 Control 609
0x044 PWM0INTEN R/W 0x0000.0000 PWM0 Interrupt and Trigger Enable 611
0x048 PWM0RIS RO 0x0000.0000 PWM0 Raw Interrupt Status 614
0x04C PWM0ISC R/W1C 0x0000.0000 PWM0 Interrupt Status and Clear 615
0x050 PWM0LOAD R/W 0x0000.0000 PWM0 Load 616
0x054 PWM0COUNT RO 0x0000.0000 PWM0 Counter 617
0x058 PWM0CMPA R/W 0x0000.0000 PWM0 Compare A 618
0x05C PWM0CMPB R/W 0x0000.0000 PWM0 Compare B 619
0x060 PWM0GENA R/W 0x0000.0000 PWM0 Generator A Control 620
0x064 PWM0GENB R/W 0x0000.0000 PWM0 Generator B Control 623
0x068 PWM0DBCTL R/W 0x0000.0000 PWM0 Dead-Band Control 626
0x06C PWM0DBRISE R/W 0x0000.0000 PWM0 Dead-Band Rising-Edge Delay 627
0x070 PWM0DBFALL R/W 0x0000.0000 PWM0 Dead-Band Falling-Edge-Delay 628
0x080 PWM1CTL R/W 0x0000.0000 PWM1 Control 609
0x084 PWM1INTEN R/W 0x0000.0000 PWM1 Interrupt and Trigger Enable 611
0x088 PWM1RIS RO 0x0000.0000 PWM1 Raw Interrupt Status 614
0x08C PWM1ISC R/W1C 0x0000.0000 PWM1 Interrupt Status and Clear 615
0x090 PWM1LOAD R/W 0x0000.0000 PWM1 Load 616
0x094 PWM1COUNT RO 0x0000.0000 PWM1 Counter 617
0x098 PWM1CMPA R/W 0x0000.0000 PWM1 Compare A 618
0x09C PWM1CMPB R/W 0x0000.0000 PWM1 Compare B 619
0x0A0 PWM1GENA R/W 0x0000.0000 PWM1 Generator A Control 620
0x0A4 PWM1GENB R/W 0x0000.0000 PWM1 Generator B Control 623
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Table 17-1. PWM Register Map (continued)
See
Offset Name Type Reset Description page
0x0A8 PWM1DBCTL R/W 0x0000.0000 PWM1 Dead-Band Control 626
0x0AC PWM1DBRISE R/W 0x0000.0000 PWM1 Dead-Band Rising-Edge Delay 627
0x0B0 PWM1DBFALL R/W 0x0000.0000 PWM1 Dead-Band Falling-Edge-Delay 628
0x0C0 PWM2CTL R/W 0x0000.0000 PWM2 Control 609
0x0C4 PWM2INTEN R/W 0x0000.0000 PWM2 Interrupt and Trigger Enable 611
0x0C8 PWM2RIS RO 0x0000.0000 PWM2 Raw Interrupt Status 614
0x0CC PWM2ISC R/W1C 0x0000.0000 PWM2 Interrupt Status and Clear 615
0x0D0 PWM2LOAD R/W 0x0000.0000 PWM2 Load 616
0x0D4 PWM2COUNT RO 0x0000.0000 PWM2 Counter 617
0x0D8 PWM2CMPA R/W 0x0000.0000 PWM2 Compare A 618
0x0DC PWM2CMPB R/W 0x0000.0000 PWM2 Compare B 619
0x0E0 PWM2GENA R/W 0x0000.0000 PWM2 Generator A Control 620
0x0E4 PWM2GENB R/W 0x0000.0000 PWM2 Generator B Control 623
0x0E8 PWM2DBCTL R/W 0x0000.0000 PWM2 Dead-Band Control 626
0x0EC PWM2DBRISE R/W 0x0000.0000 PWM2 Dead-Band Rising-Edge Delay 627
0x0F0 PWM2DBFALL R/W 0x0000.0000 PWM2 Dead-Band Falling-Edge-Delay 628
17.5 Register Descriptions
The remainder of this section lists and describes the PWM registers, in numerical order by address
offset.
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Register 1: PWM Master Control (PWMCTL), offset 0x000
This register provides master control over the PWM generation blocks.
PWM Master Control (PWMCTL)
Base 0x4002.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GlobalSync2 GlobalSync1 GlobalSync0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Update PWM Generator 2
Same as GlobalSync0 but for PWM generator 2.
2 GlobalSync2 R/W 0
Update PWM Generator 1
Same as GlobalSync0 but for PWM generator 1.
1 GlobalSync1 R/W 0
Update PWM Generator 0
Setting this bit causes any queued update to a load or comparator
register in PWM generator 0 to be applied the next time the
corresponding counter becomes zero. This bit automatically clears when
the updates have completed; it cannot be cleared by software.
0 GlobalSync0 R/W 0
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Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004
This register provides a method to perform synchronization of the counters in the PWM generation
blocks. Writing a bit in this register to 1 causes the specified counter to reset back to 0; writing
multiple bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred;
reading them back as zero indicates that the synchronization has completed.
PWM Time Base Sync (PWMSYNC)
Base 0x4002.8000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Sync2 Sync1 Sync0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Reset Generator 2 Counter
Performs a reset of the PWM generator 2 counter.
2 Sync2 R/W 0
Reset Generator 1 Counter
Performs a reset of the PWM generator 1 counter.
1 Sync1 R/W 0
Reset Generator 0 Counter
Performs a reset of the PWM generator 0 counter.
0 Sync0 R/W 0
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Register 3: PWM Output Enable (PWMENABLE), offset 0x008
This register provides a master control of which generated PWM signals are output to device pins.
By disabling a PWM output, the generation process can continue (for example, when the time bases
are synchronized) without driving PWM signals to the pins. When bits in this register are set, the
corresponding PWM signal is passed through to the output stage, which is controlled by the
PWMINVERT register. When bits are not set, the PWM signal is replaced by a zero value which is
also passed to the output stage.
PWM Output Enable (PWMENABLE)
Base 0x4002.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWM5En PWM4En PWM3En PWM2En PWM1En PWM0En
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
PWM5 Output Enable
When set, allows the generated PWM5 signal to be passed to the device
pin.
5 PWM5En R/W 0
PWM4 Output Enable
When set, allows the generated PWM4 signal to be passed to the device
pin.
4 PWM4En R/W 0
PWM3 Output Enable
When set, allows the generated PWM3 signal to be passed to the device
pin.
3 PWM3En R/W 0
PWM2 Output Enable
When set, allows the generated PWM2 signal to be passed to the device
pin.
2 PWM2En R/W 0
PWM1 Output Enable
When set, allows the generated PWM1 signal to be passed to the device
pin.
1 PWM1En R/W 0
PWM0 Output Enable
When set, allows the generated PWM0 signal to be passed to the device
pin.
0 PWM0En R/W 0
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Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C
This register provides a master control of the polarity of the PWM signals on the device pins. The
PWM signals generated by the PWM generator are active High; they can optionally be made active
Low via this register. Disabled PWM channels are also passed through the output inverter (if so
configured) so that inactive channels maintain the correct polarity.
PWM Output Inversion (PWMINVERT)
Base 0x4002.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWM5Inv PWM4Inv PWM3Inv PWM2Inv PWM1Inv PWM0Inv
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
Invert PWM5 Signal
When set, the generated PWM5 signal is inverted.
5 PWM5Inv R/W 0
Invert PWM4 Signal
When set, the generated PWM4 signal is inverted.
4 PWM4Inv R/W 0
Invert PWM3 Signal
When set, the generated PWM3 signal is inverted.
3 PWM3Inv R/W 0
Invert PWM2 Signal
When set, the generated PWM2 signal is inverted.
2 PWM2Inv R/W 0
Invert PWM1 Signal
When set, the generated PWM1 signal is inverted.
1 PWM1Inv R/W 0
Invert PWM0 Signal
When set, the generated PWM0 signal is inverted.
0 PWM0Inv R/W 0
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Register 5: PWM Output Fault (PWMFAULT), offset 0x010
This register controls the behavior of the PWM outputs in the presence of fault conditions. Both the
fault inputs and debug events are considered fault conditions. On a fault condition, each PWM signal
can be passed through unmodified or driven Low. For outputs that are configured for pass-through,
the debug event handling on the corresponding PWM generator also determines if the PWM signal
continues to be generated.
Fault condition control occurs before the output inverter, so PWM signals driven Low on fault are
inverted if the channel is configured for inversion (therefore, the pin is driven High on a fault condition).
PWM Output Fault (PWMFAULT)
Base 0x4002.8000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Fault5 Fault4 Fault3 Fault2 Fault1 Fault0
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
PWM5 Fault
When set, the PWM5 output signal is driven Low on a fault condition.
5 Fault5 R/W 0
PWM4 Fault
When set, the PWM4 output signal is driven Low on a fault condition.
4 Fault4 R/W 0
PWM3 Fault
When set, the PWM3 output signal is driven Low on a fault condition.
3 Fault3 R/W 0
PWM2 Fault
When set, the PWM2 output signal is driven Low on a fault condition.
2 Fault2 R/W 0
PWM1 Fault
When set, the PWM1 output signal is driven Low on a fault condition.
1 Fault1 R/W 0
PWM0 Fault
When set, the PWM0 output signal is driven Low on a fault condition.
0 Fault0 R/W 0
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Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014
This register controls the global interrupt generation capabilities of the PWM module. The events
that can cause an interrupt are the fault input and the individual interrupts from the PWM generators.
PWM Interrupt Enable (PWMINTEN)
Base 0x4002.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved IntFault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntPWM2 IntPWM1 IntPWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:17 reserved RO 0x00
Fault Interrupt Enable
When set, an interrupt occurs when the fault input is asserted.
16 IntFault R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:3 reserved RO 0x00
PWM2 Interrupt Enable
When set, an interrupt occurs when the PWM generator 2 block asserts
an interrupt.
2 IntPWM2 R/W 0
PWM1 Interrupt Enable
When set, an interrupt occurs when the PWM generator 1 block asserts
an interrupt.
1 IntPWM1 R/W 0
PWM0 Interrupt Enable
When set, an interrupt occurs when the PWM generator 0 block asserts
an interrupt.
0 IntPWM0 R/W 0
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Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller. The fault interrupt is latched on detection;
it must be cleared through the PWM Interrupt Status and Clear (PWMISC) register (see page 607).
The PWM generator interrupts simply reflect the status of the PWM generators; they are cleared
via the interrupt status register in the PWM generator blocks. Bits set to 1 indicate the events that
are active; zero bits indicate that the event in question is not active.
PWM Raw Interrupt Status (PWMRIS)
Base 0x4002.8000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved IntFault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntPWM2 IntPWM1 IntPWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:17 reserved RO 0x00
Fault Interrupt Asserted
Indicates that the fault input is asserting.
16 IntFault RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:3 reserved RO 0x00
PWM2 Interrupt Asserted
Indicates that the PWM generator 2 block is asserting its interrupt.
2 IntPWM2 RO 0
PWM1 Interrupt Asserted
Indicates that the PWM generator 1 block is asserting its interrupt.
1 IntPWM1 RO 0
PWM0 Interrupt Asserted
Indicates that the PWM generator 0 block is asserting its interrupt.
0 IntPWM0 RO 0
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Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C
This register provides a summary of the interrupt status of the individual PWM generator blocks. A
bit set to 1 indicates that the corresponding generator block is asserting an interrupt. The individual
interrupt status registers in each block must be consulted to determine the reason for the interrupt,
and used to clear the interrupt. For the fault interrupt, a write of 1 to that bit position clears the latched
interrupt status.
PWM Interrupt Status and Clear (PWMISC)
Base 0x4002.8000
Offset 0x01C
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved IntFault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntPWM2 IntPWM1 IntPWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:17 reserved RO 0x00
Fault Interrupt Asserted
Indicates that the fault input is asserting an interrupt.
16 IntFault R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:3 reserved RO 0x00
PWM2 Interrupt Status
Indicates if the PWM generator 2 block is asserting an interrupt.
2 IntPWM2 RO 0
PWM1 Interrupt Status
Indicates if the PWM generator 1 block is asserting an interrupt.
1 IntPWM1 RO 0
PWM0 Interrupt Status
Indicates if the PWM generator 0 block is asserting an interrupt.
0 IntPWM0 RO 0
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Register 9: PWM Status (PWMSTATUS), offset 0x020
This register provides the status of the FAULT input signal.
PWM Status (PWMSTATUS)
Base 0x4002.8000
Offset 0x020
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Fault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Fault Interrupt Status
When set, indicates the fault input is asserted.
0 Fault RO 0
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Pulse Width Modulator (PWM)
Register 10: PWM0 Control (PWM0CTL), offset 0x040
Register 11: PWM1 Control (PWM1CTL), offset 0x080
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0
These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator
0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable
mode are all controlled via these registers. The blocks produce the PWM signals, which can be
either two independent PWM signals (from the same counter), or a paired set of PWM signals with
dead-band delays added.
The PWM0 block produces the PWM0 and PWM1 outputs, the PWM1 block produces the PWM2 and
PWM3 outputs, and the PWM2 block produces the PWM4 and PWM5 outputs.
PWM0 Control (PWM0CTL)
Base 0x4002.8000
Offset 0x040
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CmpBUpd CmpAUpd LoadUpd Debug Mode Enable
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
Comparator B Update Mode
Same as CmpAUpd but for the comparator B register.
5 CmpBUpd R/W 0
Comparator A Update Mode
The Update mode for the comparator A register. When not set, updates
to the register are reflected to the comparator the next time the counter
is 0. When set, updates to the register are delayed until the next time
the counter is 0 after a synchronous update has been requested through
the PWM Master Control (PWMCTL) register (see page 600).
4 CmpAUpd R/W 0
Load Register Update Mode
The Update mode for the load register. When not set, updates to the
register are reflected to the counter the next time the counter is 0. When
set, updates to the register are delayed until the next time the counter
is 0 after a synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
3 LoadUpd R/W 0
Debug Mode
The behavior of the counter in Debug mode. When not set, the counter
stops running when it next reaches 0, and continues running again when
no longer in Debug mode. When set, the counter always runs.
2 Debug R/W 0
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Bit/Field Name Type Reset Description
Counter Mode
The mode for the counter. When not set, the counter counts down from
the load value to 0 and then wraps back to the load value (Count-Down
mode). When set, the counter counts up from 0 to the load value, back
down to 0, and then repeats (Count-Up/Down mode).
1 Mode R/W 0
PWM Block Enable
Master enable for the PWM generation block. When not set, the entire
block is disabled and not clocked. When set, the block is enabled and
produces PWM signals.
0 Enable R/W 0
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Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044
Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084
Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4
These registers control the interrupt and ADC trigger generation capabilities of the PWM generators
(PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an
interrupt or an ADC trigger are:
■ The counter being equal to the load register
■ The counter being equal to zero
■ The counter being equal to the comparator A register while counting up
■ The counter being equal to the comparator A register while counting down
■ The counter being equal to the comparator B register while counting up
■ The counter being equal to the comparator B register while counting down
Any combination of these events can generate either an interrupt, or an ADC trigger; though no
determination can be made as to the actual event that caused an ADC trigger if more than one is
specified.
PWM0 Interrupt and Trigger Enable (PWM0INTEN)
Base 0x4002.8000
Offset 0x044
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero reserved IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
Type RO RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x00
Trigger for Counter=Comparator B Down
Value Description
An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPB register value while counting down.
1
0 No ADC trigger is output.
13 TrCmpBD R/W 0
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Bit/Field Name Type Reset Description
Trigger for Counter=Comparator B Up
Value Description
An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPB register value while counting up.
1
0 No ADC trigger is output.
12 TrCmpBU R/W 0
Trigger for Counter=Comparator A Down
Value Description
An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPA register value while counting down.
1
0 No ADC trigger is output.
11 TrCmpAD R/W 0
Trigger for Counter=Comparator A Up
Value Description
An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPA register value while counting up.
1
0 No ADC trigger is output.
10 TrCmpAU R/W 0
Trigger for Counter=Load
Value Description
An ADC trigger pulse is output when the counter matches the
PWMnLOAD register.
1
0 No ADC trigger is output.
9 TrCntLoad R/W 0
Trigger for Counter=0
Value Description
1 An ADC trigger pulse is output when the counter is 0.
0 No ADC trigger is output.
8 TrCntZero R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:6 reserved RO 0x0
Interrupt for Counter=Comparator B Down
Value Description
A raw interrupt occurs when the counter matches the value in
the PWMnCMPB register value while counting down.
1
0 No interrupt.
5 IntCmpBD R/W 0
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Pulse Width Modulator (PWM)
Bit/Field Name Type Reset Description
Interrupt for Counter=Comparator B Up
Value Description
A raw interrupt occurs when the counter matches the value in
the PWMnCMPB register value while counting up.
1
0 No interrupt.
4 IntCmpBU R/W 0
Interrupt for Counter=Comparator A Down
Value Description
A raw interrupt occurs when the counter matches the value in
the PWMnCMPA register value while counting down.
1
0 No interrupt.
3 IntCmpAD R/W 0
Interrupt for Counter=Comparator A Up
Value Description
A raw interrupt occurs when the counter matches the value in
the PWMnCMPA register value while counting up.
1
0 No interrupt.
2 IntCmpAU R/W 0
Interrupt for Counter=Load
Value Description
A raw interrupt occurs when the counter matches the value in
the PWMnLOAD register value.
1
0 No interrupt.
1 IntCntLoad R/W 0
Interrupt for Counter=0
Value Description
1 A raw interrupt occurs when the counter is zero.
0 No interrupt.
0 IntCntZero R/W 0
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Stellaris® LM3S2965 Microcontroller
Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048
Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088
Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8
These registers provide the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0
block, and so on). Bits set to 1 indicate the latched events that have occurred; bits set to 0 indicate
that the event in question has not occurred.
PWM0 Raw Interrupt Status (PWM0RIS)
Base 0x4002.8000
Offset 0x048
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
Comparator B Down Interrupt Status
Indicates that the counter has matched the comparator B value while
counting down.
5 IntCmpBD RO 0
Comparator B Up Interrupt Status
Indicates that the counter has matched the comparator B value while
counting up.
4 IntCmpBU RO 0
Comparator A Down Interrupt Status
Indicates that the counter has matched the comparator A value while
counting down.
3 IntCmpAD RO 0
Comparator A Up Interrupt Status
Indicates that the counter has matched the comparator A value while
counting up.
2 IntCmpAU RO 0
Counter=Load Interrupt Status
Indicates that the counter has matched the PWMnLOAD register.
1 IntCntLoad RO 0
Counter=0 Interrupt Status
Indicates that the counter has matched 0.
0 IntCntZero RO 0
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Pulse Width Modulator (PWM)
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C
Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC
These registers provide the current set of interrupt sources that are asserted to the controller
(PWM0ISC controls the PWM generator 0 block, and so on). Bits set to 1 indicate the latched events
that have occurred; bits set to 0 indicate that the event in question has not occurred. These are
R/W1C registers; writing a 1 to a bit position clears the corresponding interrupt reason.
PWM0 Interrupt Status and Clear (PWM0ISC)
Base 0x4002.8000
Offset 0x04C
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
Type RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
Comparator B Down Interrupt
Indicates that the counter has matched the comparator B value while
counting down.
5 IntCmpBD R/W1C 0
Comparator B Up Interrupt
Indicates that the counter has matched the comparator B value while
counting up.
4 IntCmpBU R/W1C 0
Comparator A Down Interrupt
Indicates that the counter has matched the comparator A value while
counting down.
3 IntCmpAD R/W1C 0
Comparator A Up Interrupt
Indicates that the counter has matched the comparator A value while
counting up.
2 IntCmpAU R/W1C 0
Counter=Load Interrupt
Indicates that the counter has matched the PWMnLOAD register.
1 IntCntLoad R/W1C 0
Counter=0 Interrupt
Indicates that the counter has matched 0.
0 IntCntZero R/W1C 0
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Register 22: PWM0 Load (PWM0LOAD), offset 0x050
Register 23: PWM1 Load (PWM1LOAD), offset 0x090
Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0
These registers contain the load value for the PWM counter (PWM0LOAD controls the PWM
generator 0 block, and so on). Based on the counter mode, either this value is loaded into the counter
after it reaches zero, or it is the limit of up-counting after which the counter decrements back to zero.
If the Load Value Update mode is immediate, this value is used the next time the counter reaches
zero; if the mode is synchronous, it is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 600).
If this register is re-written before the actual update occurs, the previous value is never used and is
lost.
PWM0 Load (PWM0LOAD)
Base 0x4002.8000
Offset 0x050
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Load
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Counter Load Value
The counter load value.
15:0 Load R/W 0
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Pulse Width Modulator (PWM)
Register 25: PWM0 Counter (PWM0COUNT), offset 0x054
Register 26: PWM1 Counter (PWM1COUNT), offset 0x094
Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4
These registers contain the current value of the PWM counter (PWM0COUNT is the value of the
PWM generator 0 block, and so on). When this value matches the load register, a pulse is output;
this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers, see
page 620 and page 623) or drive an interrupt or ADC trigger (via the PWMnINTEN register, see
page 611). A pulse with the same capabilities is generated when this value is zero.
PWM0 Counter (PWM0COUNT)
Base 0x4002.8000
Offset 0x054
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Count
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Counter Value
The current value of the counter.
15:0 Count RO 0x00
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Stellaris® LM3S2965 Microcontroller
Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058
Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098
Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8
These registers contain a value to be compared against the counter (PWM0CMPA controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this
can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an
interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than
the PWMnLOAD register (see page 616), then no pulse is ever output.
If the comparator A update mode is immediate (based on the CmpAUpd bit in the PWMnCTL register),
this 16-bit CompA value is used the next time the counter reaches zero. If the update mode is
synchronous, it is used the next time the counter reaches zero after a synchronous update has been
requested through the PWM Master Control (PWMCTL) register (see page 600). If this register is
rewritten before the actual update occurs, the previous value is never used and is lost.
PWM0 Compare A (PWM0CMPA)
Base 0x4002.8000
Offset 0x058
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CompA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Comparator A Value
The value to be compared against the counter.
15:0 CompA R/W 0x00
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Pulse Width Modulator (PWM)
Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C
Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C
Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC
These registers contain a value to be compared against the counter (PWM0CMPB controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this
can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an
interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than
the PWMnLOAD register, no pulse is ever output.
If the comparator B update mode is immediate (based on the CmpBUpd bit in the PWMnCTL register),
this 16-bit CompB value is used the next time the counter reaches zero. If the update mode is
synchronous, it is used the next time the counter reaches zero after a synchronous update has been
requested through the PWM Master Control (PWMCTL) register (see page 600). If this register is
rewritten before the actual update occurs, the previous value is never used and is lost.
PWM0 Compare B (PWM0CMPB)
Base 0x4002.8000
Offset 0x05C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CompB
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Comparator B Value
The value to be compared against the counter.
15:0 CompB R/W 0x00
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Stellaris® LM3S2965 Microcontroller
Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060
Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0
Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0
These registers control the generation of the PWMnA signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENA controls the PWM generator 0 block, and so on). When the counter is running in
Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six
occur. These events provide great flexibility in the positioning and duty cycle of the PWM signal that
is produced.
The PWM0GENA register controls generation of the PWM0A signal; PWM1GENA, the PWM1A signal;
and PWM2GENA, the PWM2A signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare A action is taken and the compare B action is ignored.
PWM0 Generator A Control (PWM0GENA)
Base 0x4002.8000
Offset 0x060
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Action for Comparator B Down
The action to be taken when the counter matches comparator B while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
11:10 ActCmpBD R/W 0x0
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Pulse Width Modulator (PWM)
Bit/Field Name Type Reset Description
Action for Comparator B Up
The action to be taken when the counter matches comparator B while
counting up. Occurs only when the Mode bit in the PWMnCTL register
(see page 609) is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
9:8 ActCmpBU R/W 0x0
Action for Comparator A Down
The action to be taken when the counter matches comparator A while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
7:6 ActCmpAD R/W 0x0
Action for Comparator A Up
The action to be taken when the counter matches comparator A while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
5:4 ActCmpAU R/W 0x0
Action for Counter=Load
The action to be taken when the counter matches the load value.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
3:2 ActLoad R/W 0x0
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Stellaris® LM3S2965 Microcontroller
Bit/Field Name Type Reset Description
Action for Counter=0
The action to be taken when the counter is zero.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
1:0 ActZero R/W 0x0
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Pulse Width Modulator (PWM)
Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064
Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4
Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4
These registers control the generation of the PWMnB signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENB controls the PWM generator 0 block, and so on). When the counter is running in
Down mode, only four of these events occur; when running in Up/Down mode, all six occur. These
events provide great flexibility in the positioning and duty cycle of the PWM signal that is produced.
The PWM0GENB register controls generation of the PWM0B signal; PWM1GENB, the PWM1B signal;
and PWM2GENB, the PWM2B signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare B action is taken and the compare A action is ignored.
PWM0 Generator B Control (PWM0GENB)
Base 0x4002.8000
Offset 0x064
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Action for Comparator B Down
The action to be taken when the counter matches comparator B while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
11:10 ActCmpBD R/W 0x0
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Stellaris® LM3S2965 Microcontroller
Bit/Field Name Type Reset Description
Action for Comparator B Up
The action to be taken when the counter matches comparator B while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
9:8 ActCmpBU R/W 0x0
Action for Comparator A Down
The action to be taken when the counter matches comparator A while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
7:6 ActCmpAD R/W 0x0
Action for Comparator A Up
The action to be taken when the counter matches comparator A while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
5:4 ActCmpAU R/W 0x0
Action for Counter=Load
The action to be taken when the counter matches the load value.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
3:2 ActLoad R/W 0x0
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Pulse Width Modulator (PWM)
Bit/Field Name Type Reset Description
Action for Counter=0
The action to be taken when the counter is 0.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
1:0 ActZero R/W 0x0
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Stellaris® LM3S2965 Microcontroller
Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068
Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8
Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8
The PWM0DBCTL register controls the dead-band generator, which produces the PWM0 and PWM1
signals based on the PWM0A and PWM0B signals. When disabled, the PWM0A signal passes through
to the PWM0 signal and the PWM0B signal passes through to the PWM1 signal. When enabled and
inverting the resulting waveform, the PWM0B signal is ignored; the PWM0 signal is generated by
delaying the rising edge(s) of the PWM0A signal by the value in the PWM0DBRISE register (see
page 627), and the PWM1 signal is generated by delaying the falling edge(s) of the PWM0A signal by
the value in the PWM0DBFALL register (see page 628). In a similar manner, PWM2 and PWM3 are
produced from the PWM1A and PWM1B signals, and PWM4 and PWM5 are produced from the PWM2A
and PWM2B signals.
PWM0 Dead-Band Control (PWM0DBCTL)
Base 0x4002.8000
Offset 0x068
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Enable
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Dead-Band Generator Enable
When set, the dead-band generator inserts dead bands into the output
signals; when clear, it simply passes the PWM signals through.
0 Enable R/W 0
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Pulse Width Modulator (PWM)
Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset
0x06C
Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset
0x0AC
Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset
0x0EC
The PWM0DBRISE register contains the number of clock ticks to delay the rising edge of the PWM0A
signal when generating the PWM0 signal. If the dead-band generator is disabled through the
PWMnDBCTL register, the PWM0DBRISE register is ignored. If the value of this register is larger
than the width of a High pulse on the input PWM signal, the rising-edge delay consumes the entire
High time of the signal, resulting in no High time on the output. Care must be taken to ensure that
the input High time always exceeds the rising-edge delay. In a similar manner, PWM2 is generated
from PWM1A with its rising edge delayed and PWM4 is produced from PWM2A with its rising edge
delayed.
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE)
Base 0x4002.8000
Offset 0x06C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RiseDelay
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Dead-Band Rise Delay
The number of clock ticks to delay the rising edge.
11:0 RiseDelay R/W 0
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Stellaris® LM3S2965 Microcontroller
Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset
0x070
Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset
0x0B0
Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset
0x0F0
The PWM0DBFALL register contains the number of clock ticks to delay the falling edge of the
PWM0A signal when generating the PWM1 signal. If the dead-band generator is disabled, this register
is ignored. If the value of this register is larger than the width of a Low pulse on the input PWM
signal, the falling-edge delay consumes the entire Low time of the signal, resulting in no Low time
on the output. Care must be taken to ensure that the input Low time always exceeds the falling-edge
delay. In a similar manner, PWM3 is generated from PWM1A with its falling edge delayed and PWM5
is produced from PWM2A with its falling edge delayed.
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL)
Base 0x4002.8000
Offset 0x070
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved FallDelay
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Dead-Band Fall Delay
The number of clock ticks to delay the falling edge.
11:0 FallDelay R/W 0x00
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18 Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
The LM3S2965 microcontroller includes two quadrature encoder interface (QEI) modules. Each
QEI module interprets the code produced by a quadrature encoder wheel to integrate position over
time and determine direction of rotation. In addition, it can capture a running estimate of the velocity
of the encoder wheel.
Each Stellaris® quadrature encoder has the following features:
■ Two QEI modules, each with the following features:
■ Position integrator that tracks the encoder position
■ Velocity capture using built-in timer
■ The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz for a 50-MHz system)
■ Interrupt generation on:
– Index pulse
– Velocity-timer expiration
– Direction change
– Quadrature error detection
18.1 Block Diagram
Figure 18-1 on page 630 provides a block diagram of a Stellaris QEI module.
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Figure 18-1. QEI Block Diagram
Quadrature
Encoder
Velocity
Predivider
Interrupt Control
QEIINTEN
QEIRIS
QEIISC
Position Integrator
QEIMAXPOS
QEIPOS
Velocity Accumulator
QEICOUNT
QEISPEED
Velocity Timer
QEILOAD
QEITIME
PhA
PhB
IDX
clk
dir
Interrupt
Control & Status
QEICTL
QEISTAT
18.2 Functional Description
The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate
position over time and determine direction of rotation. In addition, it can capture a running estimate
of the velocity of the encoder wheel.
The position integrator and velocity capture can be independently enabled, though the position
integrator must be enabled before the velocity capture can be enabled. The two phase signals, PhA
and PhB, can be swapped before being interpreted by the QEI module to change the meaning of
forward and backward, and to correct for miswiring of the system. Alternatively, the phase signals
can be interpreted as a clock and direction signal as output by some encoders.
The QEI module supports two modes of signal operation: quadrature phase mode and clock/direction
mode. In quadrature phase mode, the encoder produces two clocks that are 90 degrees out of
phase; the edge relationship is used to determine the direction of rotation. In clock/direction mode,
the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction
of rotation. This mode is determined by the SigMode bit of the QEI Control (QEICTL) register (see
page 634).
When the QEI module is set to use the quadrature phase mode (SigMode bit equals zero), the
capture mode for the position integrator can be set to update the position counter on every edge of
the PhA signal or to update on every edge of both PhA and PhB. Updating the position counter on
every PhA and PhB provides more positional resolution at the cost of less range in the positional
counter.
When edges on PhA lead edges on PhB , the position counter is incremented. When edges on PhB
lead edges on PhA , the position counter is decremented. When a rising and falling edge pair is
seen on one of the phases without any edges on the other, the direction of rotation has changed.
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The positional counter is automatically reset on one of two conditions: sensing the index pulse or
reaching the maximum position value. Which mode is determined by the ResMode bit of the QEI
Control (QEICTL) register.
When ResMode is 1, the positional counter is reset when the index pulse is sensed. This limits the
positional counter to the values [0:N-1], where N is the number of phase edges in a full revolution
of the encoder wheel. The QEIMAXPOS register must be programmed with N-1 so that the reverse
direction from position 0 can move the position counter to N-1. In this mode, the position register
contains the absolute position of the encoder relative to the index (or home) position once an index
pulse has been seen.
When ResMode is 0, the positional counter is constrained to the range [0:M], where M is the
programmable maximum value. The index pulse is ignored by the positional counter in this mode.
The velocity capture has a configurable timer and a count register. It counts the number of phase
edges (using the same configuration as for the position integrator) in a given time period. The edge
count from the previous time period is available to the controller via the QEISPEED register, while
the edge count for the current time period is being accumulated in the QEICOUNT register. As soon
as the current time period is complete, the total number of edges counted in that time period is made
available in the QEISPEED register (losing the previous value), the QEICOUNT is reset to 0, and
counting commences on a new time period. The number of edges counted in a given time period
is directly proportional to the velocity of the encoder.
Figure 18-2 on page 631 shows how the Stellaris quadrature encoder converts the phase input signals
into clock pulses, the direction signal, and how the velocity predivider operates (in Divide by 4 mode).
Figure 18-2. Quadrature Encoder and Velocity Predivider Operation
-1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+1 +1 +1 +1 +1 +1 +1 +1
PhA
PhB
clk
clkdiv
dir
pos
rel
The period of the timer is configurable by specifying the load value for the timer in the QEILOAD
register. When the timer reaches zero, an interrupt can be triggered, and the hardware reloads the
timer with the QEILOAD value and continues to count down. At lower encoder speeds, a longer
timer period is needed to be able to capture enough edges to have a meaningful result. At higher
encoder speeds, both a shorter timer period and/or the velocity predivider can be used.
The following equation converts the velocity counter value into an rpm value:
rpm = (clock * (2 ^ VelDiv) * Speed * 60) ÷ (Load * ppr * edges)
where:
clock is the controller clock rate
ppr is the number of pulses per revolution of the physical encoder
edges is 2 or 4, based on the capture mode set in the QEICTL register (2 for CapMode set to 0 and
4 for CapMode set to 1)
For example, consider a motor running at 600 rpm. A 2048 pulse per revolution quadrature encoder
is attached to the motor, producing 8192 phase edges per revolution. With a velocity predivider of
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÷1 (VelDiv set to 0) and clocking on both PhA and PhB edges, this results in 81,920 pulses per
second (the motor turns 10 times per second). If the timer were clocked at 10,000 Hz, and the load
value was 2,500 (¼ of a second), it would count 20,480 pulses per update. Using the above equation:
rpm = (10000 * 1 * 20480 * 60) ÷ (2500 * 2048 * 4) = 600 rpm
Now, consider that the motor is sped up to 3000 rpm. This results in 409,600 pulses per second,
or 102,400 every ¼ of a second. Again, the above equation gives:
rpm = (10000 * 1 * 102400 * 60) ÷ (2500 * 2048 * 4) = 3000 rpm
Care must be taken when evaluating this equation since intermediate values may exceed the capacity
of a 32-bit integer. In the above examples, the clock is 10,000 and the divider is 2,500; both could
be predivided by 100 (at compile time if they are constants) and therefore be 100 and 25. In fact, if
they were compile-time constants, they could also be reduced to a simple multiply by 4, cancelled
by the ÷4 for the edge-count factor.
Important: Reducing constant factors at compile time is the best way to control the intermediate
values of this equation, as well as reducing the processing requirement of computing
this equation.
The division can be avoided by selecting a timer load value such that the divisor is a power of 2; a
simple shift can therefore be done in place of the division. For encoders with a power of 2 pulses
per revolution, this is a simple matter of selecting a power of 2 load value. For other encoders, a
load value must be selected such that the product is very close to a power of two. For example, a
100 pulse per revolution encoder could use a load value of 82, resulting in 32,800 as the divisor,
which is 0.09% above 214; in this case a shift by 15 would be an adequate approximation of the
divide in most cases. If absolute accuracy were required, the controller’s divide instruction could be
used.
The QEI module can produce a controller interrupt on several events: phase error, direction change,
reception of the index pulse, and expiration of the velocity timer. Standard masking, raw interrupt
status, interrupt status, and interrupt clear capabilities are provided.
18.3 Initialization and Configuration
The following example shows how to configure the Quadrature Encoder module to read back an
absolute position:
1. Enable the QEI clock by writing a value of 0x0000.0100 to the RCGC1 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register.
4. Configure the quadrature encoder to capture edges on both signals and maintain an absolute
position by resetting on index pulses. Using a 1000-line encoder at four edges per line, there
are 4000 pulses per revolution; therefore, set the maximum position to 3999 (0xF9F) since the
count is zero-based.
■ Write the QEICTL register with the value of 0x0000.0018.
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■ Write the QEIMAXPOS register with the value of 0x0000.0F9F.
5. Enable the quadrature encoder by setting bit 0 of the QEICTL register.
6. Delay for some time.
7. Read the encoder position by reading the QEIPOS register value.
18.4 Register Map
Table 18-1 on page 633 lists the QEI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the module’s base address:
■ QEI0: 0x4002.C000
■ QEI1: 0x4002.D000
Note that the QEI module clock must be enabled before the registers can be programmed (see
page 216). There must be a delay of 3 system clocks after the QEI module clock is enabled before
any QEI module registers are accessed.
Table 18-1. QEI Register Map
See
Offset Name Type Reset Description page
0x000 QEICTL R/W 0x0000.0000 QEI Control 634
0x004 QEISTAT RO 0x0000.0000 QEI Status 636
0x008 QEIPOS R/W 0x0000.0000 QEI Position 637
0x00C QEIMAXPOS R/W 0x0000.0000 QEI Maximum Position 638
0x010 QEILOAD R/W 0x0000.0000 QEI Timer Load 639
0x014 QEITIME RO 0x0000.0000 QEI Timer 640
0x018 QEICOUNT RO 0x0000.0000 QEI Velocity Counter 641
0x01C QEISPEED RO 0x0000.0000 QEI Velocity 642
0x020 QEIINTEN R/W 0x0000.0000 QEI Interrupt Enable 643
0x024 QEIRIS RO 0x0000.0000 QEI Raw Interrupt Status 644
0x028 QEIISC R/W1C 0x0000.0000 QEI Interrupt Status and Clear 645
18.5 Register Descriptions
The remainder of this section lists and describes the QEI registers, in numerical order by address
offset.
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Register 1: QEI Control (QEICTL), offset 0x000
This register contains the configuration of the QEI module. Separate enables are provided for the
quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in
order to capture the velocity, but the velocity does not need to be captured in applications that do
not need it. The phase signal interpretation, phase swap, Position Update mode, Position Reset
mode, and velocity predivider are all set via this register.
QEI Control (QEICTL)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved STALLEN INVI INVB INVA VelDiv VelEn ResMode CapMode SigMode Swap Enable
Type RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:13 reserved RO 0x00
Stall QEI
When set, the QEI stalls when the microcontroller asserts Halt.
12 STALLEN R/W 0
Invert Index Pulse
When set , the input Index Pulse is inverted.
11 INVI R/W 0
Invert PhB
When set, the PhB input is inverted.
10 INVB R/W 0
Invert PhA
When set, the PhA input is inverted.
9 INVA R/W 0
Predivide Velocity
A predivider of the input quadrature pulses before being applied to the
QEICOUNT accumulator. This field can be set to the following values:
Value Predivider
0x0 ÷1
0x1 ÷2
0x2 ÷4
0x3 ÷8
0x4 ÷16
0x5 ÷32
0x6 ÷64
0x7 ÷128
8:6 VelDiv R/W 0x0
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Bit/Field Name Type Reset Description
Capture Velocity
When set, enables capture of the velocity of the quadrature encoder.
5 VelEn R/W 0
Reset Mode
The Reset mode for the position counter. When 0, the position counter
is reset when it reaches the maximum; when 1, the position counter is
reset when the index pulse is captured.
4 ResMode R/W 0
Capture Mode
The Capture mode defines the phase edges that are counted in the
position. When 0, only the PhA edges are counted; when 1, the PhA
and PhB edges are counted, providing twice the positional resolution
but half the range.
3 CapMode R/W 0
Signal Mode
When 1, the PhA and PhB signals are clock and direction; when 0, they
are quadrature phase signals.
2 SigMode R/W 0
Swap Signals
Swaps the PhA and PhB signals.
1 Swap R/W 0
Enable QEI
Enables the quadrature encoder module.
0 Enable R/W 0
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Register 2: QEI Status (QEISTAT), offset 0x004
This register provides status about the operation of the QEI module.
QEI Status (QEISTAT)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Direction Error
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Direction of Rotation
Indicates the direction the encoder is rotating.
The Direction values are defined as follows:
Value Description
0 Forward rotation
1 Reverse rotation
1 Direction RO 0
Error Detected
Indicates that an error was detected in the gray code sequence (that is,
both signals changing at the same time).
0 Error RO 0
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Register 3: QEI Position (QEIPOS), offset 0x008
This register contains the current value of the position integrator. Its value is updated by inputs on
the QEI phase inputs, and can be set to a specific value by writing to it.
QEI Position (QEIPOS)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Position
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Position
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Current Position Integrator Value
The current value of the position integrator.
31:0 Position R/W 0x00
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Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C
This register contains the maximum value of the position integrator. When moving forward, the
position register resets to zero when it increments past this value. When moving backward, the
position register resets to this value when it decrements from zero.
QEI Maximum Position (QEIMAXPOS)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MaxPos
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MaxPos
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Maximum Position Integrator Value
The maximum value of the position integrator.
31:0 MaxPos R/W 0x00
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Register 5: QEI Timer Load (QEILOAD), offset 0x010
This register contains the load value for the velocity timer. Since this value is loaded into the timer
the clock cycle after the timer is zero, this value should be one less than the number of clocks in
the desired period. So, for example, to have 2000 clocks per timer period, this register should contain
1999.
QEI Timer Load (QEILOAD)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Load
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Load
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Velocity Timer Load Value
The load value for the velocity timer.
31:0 Load R/W 0x00
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Register 6: QEI Timer (QEITIME), offset 0x014
This register contains the current value of the velocity timer. This counter does not increment when
VelEn in QEICTL is 0.
QEI Timer (QEITIME)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Time
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Time
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Velocity Timer Current Value
The current value of the velocity timer.
31:0 Time RO 0x00
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Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018
This register contains the running count of velocity pulses for the current time period. Since this is
a running total, the time period to which it applies cannot be known with precision (that is, a read of
this register does not necessarily correspond to the time returned by the QEITIME register since
there is a small window of time between the two reads, during which time either value may have
changed). The QEISPEED register should be used to determine the actual encoder velocity; this
register is provided for information purposes only. This counter does not increment when VelEn in
QEICTL is 0.
QEI Velocity Counter (QEICOUNT)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Count
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Count
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Velocity Pulse Count
The running total of encoder pulses during this velocity timer period.
31:0 Count RO 0x00
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Register 8: QEI Velocity (QEISPEED), offset 0x01C
This register contains the most recently measured velocity of the quadrature encoder. This
corresponds to the number of velocity pulses counted in the previous velocity timer period. This
register does not update when VelEn in QEICTL is 0.
QEI Velocity (QEISPEED)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Speed
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Speed
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Velocity
The measured speed of the quadrature encoder in pulses per period.
31:0 Speed RO 0x00
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Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020
This register contains enables for each of the QEI module’s interrupts. An interrupt is asserted to
the controller if its corresponding bit in this register is set to 1.
QEI Interrupt Enable (QEIINTEN)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntError IntDir IntTimer IntIndex
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
Phase Error Interrupt Enable
When 1, an interrupt occurs when a phase error is detected.
3 IntError R/W 0
Direction Change Interrupt Enable
When 1, an interrupt occurs when the direction changes.
2 IntDir R/W 0
Timer Expires Interrupt Enable
When 1, an interrupt occurs when the velocity timer expires.
1 IntTimer R/W 0
Index Pulse Detected Interrupt Enable
When 1, an interrupt occurs when the index pulse is detected.
0 IntIndex R/W 0
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Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (this is set through the QEIINTEN register).
Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in
question has not occurred.
QEI Raw Interrupt Status (QEIRIS)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x024
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntError IntDir IntTimer IntIndex
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
Phase Error Detected
Indicates that a phase error was detected.
3 IntError RO 0
Direction Change Detected
Indicates that the direction has changed.
2 IntDir RO 0
Velocity Timer Expired
Indicates that the velocity timer has expired.
1 IntTimer RO 0
Index Pulse Asserted
Indicates that the index pulse has occurred.
0 IntIndex RO 0
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Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028
This register provides the current set of interrupt sources that are asserted to the controller. Bits set
to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question
has not occurred. This is a R/W1C register; writing a 1 to a bit position clears the corresponding
interrupt reason.
QEI Interrupt Status and Clear (QEIISC)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x028
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntError IntDir IntTimer IntIndex
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
Phase Error Interrupt
Indicates that a phase error was detected.
3 IntError R/W1C 0
Direction Change Interrupt
Indicates that the direction has changed.
2 IntDir R/W1C 0
Velocity Timer Expired Interrupt
Indicates that the velocity timer has expired.
1 IntTimer R/W1C 0
Index Pulse Interrupt
Indicates that the index pulse has occurred.
0 IntIndex R/W1C 0
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19 Pin Diagram
The LM3S2965 microcontroller pin diagrams are shown below.
Figure 19-1. 100-Pin LQFP Package Pin Diagram
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Pin Diagram
Figure 19-2. 108-Ball BGA Package Pin Diagram (Top View)
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20 Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register.
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
Table 20-1 on page 648 shows the pin-to-signal-name mapping, including functional characteristics
of the signals. Table 20-2 on page 652 lists the signals in alphabetical order by signal name.
Table 20-3 on page 657 groups the signals by functionality, except for GPIOs. Table 20-4 on page 660
lists the GPIO pins and their alternate functionality.
Note: All digital inputs are Schmitt triggered.
20.1 100-Pin LQFP Package Pin Tables
Table 20-1. Signals by Pin Number
Pin Number Pin Name Pin Type Buffer Typea Description
1 ADC0 I Analog Analog-to-digital converter input 0.
2 ADC1 I Analog Analog-to-digital converter input 1.
The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
VDDA - Power
3
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
GNDA - Power
4
5 ADC2 I Analog Analog-to-digital converter input 2.
6 ADC3 I Analog Analog-to-digital converter input 3.
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 μF or greater. When the
on-chip LDO is used to provide power to the logic, the LDO pin
must also be connected to the VDD25 pins at the board level in
addition to the decoupling capacitor(s).
LDO - Power
7
8 VDD - Power Positive supply for I/O and some logic.
9 GND - Power Ground reference for logic and I/O pins.
PD0 I/O TTL GPIO port D bit 0.
10
CAN0Rx I TTL CAN module 0 receive.
PD1 I/O TTL GPIO port D bit 1.
11
CAN0Tx O TTL CAN module 0 transmit.
PD2 I/O TTL GPIO port D bit 2.
12 UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
U1Rx I TTL
PD3 I/O TTL GPIO port D bit 3.
13 UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
U1Tx O TTL
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Table 20-1. Signals by Pin Number (continued)
Pin Number Pin Name Pin Type Buffer Typea Description
Positive supply for most of the logic function, including the
processor core and most peripherals.
VDD25 - Power 14
15 GND - Power Ground reference for logic and I/O pins.
PG3 I/O TTL GPIO port G bit 3.
16
PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0.
PG2 I/O TTL GPIO port G bit 2.
17
PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0.
PG1 I/O TTL GPIO port G bit 1.
18 UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
U2Tx O TTL
PG0 I/O TTL GPIO port G bit 0.
19 UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
U2Rx I TTL
20 VDD - Power Positive supply for I/O and some logic.
21 GND - Power Ground reference for logic and I/O pins.
PC7 I/O TTL GPIO port C bit 7.
22
C2- I Analog Analog comparator 2 negative input.
PC6 I/O TTL GPIO port C bit 6.
23
C2+ I Analog Analog comparator 2 positive input.
PC5 I/O TTL GPIO port C bit 5.
24
C1+ I Analog Analog comparator 1 positive input.
PC4 I/O TTL GPIO port C bit 4.
25
PhA0 I TTL QEI module 0 phase A.
PA0 I/O TTL GPIO port A bit 0.
26 UART module 0 receive. When in IrDA mode, this signal has IrDA
modulation.
U0Rx I TTL
PA1 I/O TTL GPIO port A bit 1.
27 UART module 0 transmit. When in IrDA mode, this signal has IrDA
modulation.
U0Tx O TTL
PA2 I/O TTL GPIO port A bit 2.
28
SSI0Clk I/O TTL SSI module 0 clock.
PA3 I/O TTL GPIO port A bit 3.
29
SSI0Fss I/O TTL SSI module 0 frame.
PA4 I/O TTL GPIO port A bit 4.
30
SSI0Rx I TTL SSI module 0 receive.
PA5 I/O TTL GPIO port A bit 5.
31
SSI0Tx O TTL SSI module 0 transmit.
32 VDD - Power Positive supply for I/O and some logic.
33 GND - Power Ground reference for logic and I/O pins.
PA6 I/O TTL GPIO port A bit 6.
34
I2C1SCL I/O OD I2C module 1 clock.
PA7 I/O TTL GPIO port A bit 7.
35
I2C1SDA I/O OD I2C module 1 data.
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Table 20-1. Signals by Pin Number (continued)
Pin Number Pin Name Pin Type Buffer Typea Description
PG7 I/O TTL GPIO port G bit 7.
36
PhB1 I TTL QEI module 1 phase B.
PG6 I/O TTL GPIO port G bit 6.
37
PhA1 I TTL QEI module 1 phase A.
Positive supply for most of the logic function, including the
processor core and most peripherals.
VDD25 - Power 38
39 GND - Power Ground reference for logic and I/O pins.
PG5 I/O TTL GPIO port G bit 5.
40
CCP5 I/O TTL Capture/Compare/PWM 5.
41 PG4 I/O TTL GPIO port G bit 4.
42 PF7 I/O TTL GPIO port F bit 7.
PF6 I/O TTL GPIO port F bit 6.
43
CCP1 I/O TTL Capture/Compare/PWM 1.
44 VDD - Power Positive supply for I/O and some logic.
45 GND - Power Ground reference for logic and I/O pins.
46 PF5 I/O TTL GPIO port F bit 5.
PF0 I/O TTL GPIO port F bit 0.
47
CAN1Rx I TTL CAN module 1 receive.
48 OSC0 I Analog Main oscillator crystal input or an external clock reference input.
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
OSC1 O Analog 49
An external input that brings the processor out of Hibernate mode
when asserted.
WAKE I TTL 50
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
HIB O OD 51
Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a 32.768-kHz
oscillator for the Hibernation module RTC.
XOSC0 I Analog
52
Hibernation module oscillator crystal output. Leave unconnected
when using a single-ended clock source.
XOSC1 O Analog 53
54 GND - Power Ground reference for logic and I/O pins.
Power source for the Hibernation module. It is normally connected
to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
VBAT - Power
55
56 VDD - Power Positive supply for I/O and some logic.
57 GND - Power Ground reference for logic and I/O pins.
PF4 I/O TTL GPIO port F bit 4.
58
C0o O TTL Analog comparator 0 output.
PF3 I/O TTL GPIO port F bit 3.
59
PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2.
PF2 I/O TTL GPIO port F bit 2.
60
PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2.
PF1 I/O TTL GPIO port F bit 1.
61
CAN1Tx O TTL CAN module 1 transmit.
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Table 20-1. Signals by Pin Number (continued)
Pin Number Pin Name Pin Type Buffer Typea Description
Positive supply for most of the logic function, including the
processor core and most peripherals.
VDD25 - Power 62
63 GND - Power Ground reference for logic and I/O pins.
64 RST I TTL System reset input.
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
CMOD0 I TTL 65
PB0 I/O TTL GPIO port B bit 0.
66
CCP0 I/O TTL Capture/Compare/PWM 0.
PB1 I/O TTL GPIO port B bit 1.
67
CCP2 I/O TTL Capture/Compare/PWM 2.
68 VDD - Power Positive supply for I/O and some logic.
69 GND - Power Ground reference for logic and I/O pins.
PB2 I/O TTL GPIO port B bit 2.
70
I2C0SCL I/O OD I2C module 0 clock.
PB3 I/O TTL GPIO port B bit 3.
71
I2C0SDA I/O OD I2C module 0 data.
PE0 I/O TTL GPIO port E bit 0.
72
SSI1Clk I/O TTL SSI module 1 clock.
PE1 I/O TTL GPIO port E bit 1.
73
SSI1Fss I/O TTL SSI module 1 frame.
PE2 I/O TTL GPIO port E bit 2.
74
SSI1Rx I TTL SSI module 1 receive.
PE3 I/O TTL GPIO port E bit 3.
75
SSI1Tx O TTL SSI module 1 transmit.
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
CMOD1 I TTL 76
PC3 I/O TTL GPIO port C bit 3.
77 SWO O TTL JTAG TDO and SWO.
TDO O TTL JTAG TDO and SWO.
PC2 I/O TTL GPIO port C bit 2.
78
TDI I TTL JTAG TDI.
PC1 I/O TTL GPIO port C bit 1.
79 SWDIO I/O TTL JTAG TMS and SWDIO.
TMS I/O TTL JTAG TMS and SWDIO.
PC0 I/O TTL GPIO port C bit 0.
80 SWCLK I TTL JTAG/SWD CLK.
TCK I TTL JTAG/SWD CLK.
81 VDD - Power Positive supply for I/O and some logic.
82 GND - Power Ground reference for logic and I/O pins.
PH3 I/O TTL GPIO port H bit 3.
83
PhB0 I TTL QEI module 0 phase B.
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Table 20-1. Signals by Pin Number (continued)
Pin Number Pin Name Pin Type Buffer Typea Description
PH2 I/O TTL GPIO port H bit 2.
84
IDX1 I TTL QEI module 1 index.
PH1 I/O TTL GPIO port H bit 1.
85
PWM3 O TTL PWM 3. This signal is controlled by PWM Generator 1.
PH0 I/O TTL GPIO port H bit 0.
86
PWM2 O TTL PWM 2. This signal is controlled by PWM Generator 1.
87 GND - Power Ground reference for logic and I/O pins.
Positive supply for most of the logic function, including the
processor core and most peripherals.
VDD25 - Power 88
PB7 I/O TTL GPIO port B bit 7.
89
TRST I TTL JTAG TRST.
PB6 I/O TTL GPIO port B bit 6.
90
C0+ I Analog Analog comparator 0 positive input.
PB5 I/O TTL GPIO port B bit 5.
91
C1- I Analog Analog comparator 1 negative input.
PB4 I/O TTL GPIO port B bit 4.
92
C0- I Analog Analog comparator 0 negative input.
93 VDD - Power Positive supply for I/O and some logic.
94 GND - Power Ground reference for logic and I/O pins.
PD4 I/O TTL GPIO port D bit 4.
95
CCP3 I/O TTL Capture/Compare/PWM 3.
PD5 I/O TTL GPIO port D bit 5.
96
CCP4 I/O TTL Capture/Compare/PWM 4.
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
GNDA - Power
97
The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
VDDA - Power
98
PD6 I/O TTL GPIO port D bit 6.
99
Fault I TTL PWM Fault.
PD7 I/O TTL GPIO port D bit 7.
100
IDX0 I TTL QEI module 0 index.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 20-2. Signals by Signal Name
Pin Name Pin Number Pin Type Buffer Typea Description
ADC0 1 I Analog Analog-to-digital converter input 0.
ADC1 2 I Analog Analog-to-digital converter input 1.
ADC2 5 I Analog Analog-to-digital converter input 2.
ADC3 6 I Analog Analog-to-digital converter input 3.
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Table 20-2. Signals by Signal Name (continued)
Pin Name Pin Number Pin Type Buffer Typea Description
C0+ 90 I Analog Analog comparator 0 positive input.
C0- 92 I Analog Analog comparator 0 negative input.
C0o 58 O TTL Analog comparator 0 output.
C1+ 24 I Analog Analog comparator 1 positive input.
C1- 91 I Analog Analog comparator 1 negative input.
C2+ 23 I Analog Analog comparator 2 positive input.
C2- 22 I Analog Analog comparator 2 negative input.
CAN0Rx 10 I TTL CAN module 0 receive.
CAN0Tx 11 O TTL CAN module 0 transmit.
CAN1Rx 47 I TTL CAN module 1 receive.
CAN1Tx 61 O TTL CAN module 1 transmit.
CCP0 66 I/O TTL Capture/Compare/PWM 0.
CCP1 43 I/O TTL Capture/Compare/PWM 1.
CCP2 67 I/O TTL Capture/Compare/PWM 2.
CCP3 95 I/O TTL Capture/Compare/PWM 3.
CCP4 96 I/O TTL Capture/Compare/PWM 4.
CCP5 40 I/O TTL Capture/Compare/PWM 5.
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
CMOD0 65 I TTL
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
CMOD1 76 I TTL
Fault 99 I TTL PWM Fault.
9 - Power Ground reference for logic and I/O pins.
15
21
33
39
45
54
57
63
69
82
87
94
GND
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to
minimize the electrical noise contained on VDD from affecting
the analog functions.
4 - Power
97
GNDA
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
HIB 51 O OD
I2C0SCL 70 I/O OD I2C module 0 clock.
I2C0SDA 71 I/O OD I2C module 0 data.
I2C1SCL 34 I/O OD I2C module 1 clock.
I2C1SDA 35 I/O OD I2C module 1 data.
IDX0 100 I TTL QEI module 0 index.
IDX1 84 I TTL QEI module 1 index.
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Table 20-2. Signals by Signal Name (continued)
Pin Name Pin Number Pin Type Buffer Typea Description
Low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 μF or
greater. When the on-chip LDO is used to provide power to
the logic, the LDO pin must also be connected to the VDD25
pins at the board level in addition to the decoupling
capacitor(s).
LDO 7 - Power
Main oscillator crystal input or an external clock reference
input.
OSC0 48 I Analog
Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
OSC1 49 O Analog
PA0 26 I/O TTL GPIO port A bit 0.
PA1 27 I/O TTL GPIO port A bit 1.
PA2 28 I/O TTL GPIO port A bit 2.
PA3 29 I/O TTL GPIO port A bit 3.
PA4 30 I/O TTL GPIO port A bit 4.
PA5 31 I/O TTL GPIO port A bit 5.
PA6 34 I/O TTL GPIO port A bit 6.
PA7 35 I/O TTL GPIO port A bit 7.
PB0 66 I/O TTL GPIO port B bit 0.
PB1 67 I/O TTL GPIO port B bit 1.
PB2 70 I/O TTL GPIO port B bit 2.
PB3 71 I/O TTL GPIO port B bit 3.
PB4 92 I/O TTL GPIO port B bit 4.
PB5 91 I/O TTL GPIO port B bit 5.
PB6 90 I/O TTL GPIO port B bit 6.
PB7 89 I/O TTL GPIO port B bit 7.
PC0 80 I/O TTL GPIO port C bit 0.
PC1 79 I/O TTL GPIO port C bit 1.
PC2 78 I/O TTL GPIO port C bit 2.
PC3 77 I/O TTL GPIO port C bit 3.
PC4 25 I/O TTL GPIO port C bit 4.
PC5 24 I/O TTL GPIO port C bit 5.
PC6 23 I/O TTL GPIO port C bit 6.
PC7 22 I/O TTL GPIO port C bit 7.
PD0 10 I/O TTL GPIO port D bit 0.
PD1 11 I/O TTL GPIO port D bit 1.
PD2 12 I/O TTL GPIO port D bit 2.
PD3 13 I/O TTL GPIO port D bit 3.
PD4 95 I/O TTL GPIO port D bit 4.
PD5 96 I/O TTL GPIO port D bit 5.
PD6 99 I/O TTL GPIO port D bit 6.
PD7 100 I/O TTL GPIO port D bit 7.
PE0 72 I/O TTL GPIO port E bit 0.
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Table 20-2. Signals by Signal Name (continued)
Pin Name Pin Number Pin Type Buffer Typea Description
PE1 73 I/O TTL GPIO port E bit 1.
PE2 74 I/O TTL GPIO port E bit 2.
PE3 75 I/O TTL GPIO port E bit 3.
PF0 47 I/O TTL GPIO port F bit 0.
PF1 61 I/O TTL GPIO port F bit 1.
PF2 60 I/O TTL GPIO port F bit 2.
PF3 59 I/O TTL GPIO port F bit 3.
PF4 58 I/O TTL GPIO port F bit 4.
PF5 46 I/O TTL GPIO port F bit 5.
PF6 43 I/O TTL GPIO port F bit 6.
PF7 42 I/O TTL GPIO port F bit 7.
PG0 19 I/O TTL GPIO port G bit 0.
PG1 18 I/O TTL GPIO port G bit 1.
PG2 17 I/O TTL GPIO port G bit 2.
PG3 16 I/O TTL GPIO port G bit 3.
PG4 41 I/O TTL GPIO port G bit 4.
PG5 40 I/O TTL GPIO port G bit 5.
PG6 37 I/O TTL GPIO port G bit 6.
PG7 36 I/O TTL GPIO port G bit 7.
PH0 86 I/O TTL GPIO port H bit 0.
PH1 85 I/O TTL GPIO port H bit 1.
PH2 84 I/O TTL GPIO port H bit 2.
PH3 83 I/O TTL GPIO port H bit 3.
PhA0 25 I TTL QEI module 0 phase A.
PhA1 37 I TTL QEI module 1 phase A.
PhB0 83 I TTL QEI module 0 phase B.
PhB1 36 I TTL QEI module 1 phase B.
PWM0 17 O TTL PWM 0. This signal is controlled by PWM Generator 0.
PWM1 16 O TTL PWM 1. This signal is controlled by PWM Generator 0.
PWM2 86 O TTL PWM 2. This signal is controlled by PWM Generator 1.
PWM3 85 O TTL PWM 3. This signal is controlled by PWM Generator 1.
PWM4 60 O TTL PWM 4. This signal is controlled by PWM Generator 2.
PWM5 59 O TTL PWM 5. This signal is controlled by PWM Generator 2.
RST 64 I TTL System reset input.
SSI0Clk 28 I/O TTL SSI module 0 clock.
SSI0Fss 29 I/O TTL SSI module 0 frame.
SSI0Rx 30 I TTL SSI module 0 receive.
SSI0Tx 31 O TTL SSI module 0 transmit.
SSI1Clk 72 I/O TTL SSI module 1 clock.
SSI1Fss 73 I/O TTL SSI module 1 frame.
SSI1Rx 74 I TTL SSI module 1 receive.
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Table 20-2. Signals by Signal Name (continued)
Pin Name Pin Number Pin Type Buffer Typea Description
SSI1Tx 75 O TTL SSI module 1 transmit.
SWCLK 80 I TTL JTAG/SWD CLK.
SWDIO 79 I/O TTL JTAG TMS and SWDIO.
SWO 77 O TTL JTAG TDO and SWO.
TCK 80 I TTL JTAG/SWD CLK.
TDI 78 I TTL JTAG TDI.
TDO 77 O TTL JTAG TDO and SWO.
TMS 79 I/O TTL JTAG TMS and SWDIO.
TRST 89 I TTL JTAG TRST.
UART module 0 receive. When in IrDA mode, this signal has
IrDA modulation.
U0Rx 26 I TTL
UART module 0 transmit. When in IrDA mode, this signal has
IrDA modulation.
U0Tx 27 O TTL
UART module 1 receive. When in IrDA mode, this signal has
IrDA modulation.
U1Rx 12 I TTL
UART module 1 transmit. When in IrDA mode, this signal has
IrDA modulation.
U1Tx 13 O TTL
UART module 2 receive. When in IrDA mode, this signal has
IrDA modulation.
U2Rx 19 I TTL
UART module 2 transmit. When in IrDA mode, this signal has
IrDA modulation.
U2Tx 18 O TTL
Power source for the Hibernation module. It is normally
connected to the positive terminal of a battery and serves as
the battery backup/Hibernation module power-source supply.
VBAT 55 - Power
8 - Power Positive supply for I/O and some logic.
20
32
44
56
68
81
93
VDD
Positive supply for most of the logic function, including the
processor core and most peripherals.
14 - Power
38
62
88
VDD25
The positive supply (3.3 V) for the analog circuits (ADC,
Analog Comparators, etc.). These are separated from VDD
to minimize the electrical noise contained on VDD from
affecting the analog functions. VDDA pins must be connected
to 3.3 V, regardless of system implementation.
3 - Power
98
VDDA
An external input that brings the processor out of Hibernate
mode when asserted.
WAKE 50 I TTL
Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a
32.768-kHz oscillator for the Hibernation module RTC.
XOSC0 52 I Analog
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock source.
XOSC1 53 O Analog
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
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Table 20-3. Signals by Function, Except for GPIO
Function Pin Name Pin Number Pin Type Buffer Typea Description
ADC0 1 I Analog Analog-to-digital converter input 0.
ADC
ADC1 2 I Analog Analog-to-digital converter input 1.
ADC2 5 I Analog Analog-to-digital converter input 2.
ADC3 6 I Analog Analog-to-digital converter input 3.
C0+ 90 I Analog Analog comparator 0 positive input.
Analog Comparators
C0- 92 I Analog Analog comparator 0 negative input.
C0o 58 O TTL Analog comparator 0 output.
C1+ 24 I Analog Analog comparator 1 positive input.
C1- 91 I Analog Analog comparator 1 negative input.
C2+ 23 I Analog Analog comparator 2 positive input.
C2- 22 I Analog Analog comparator 2 negative input.
CAN0Rx 10 I TTL CAN module 0 receive.
Controller Area
Network
CAN0Tx 11 O TTL CAN module 0 transmit.
CAN1Rx 47 I TTL CAN module 1 receive.
CAN1Tx 61 O TTL CAN module 1 transmit.
CCP0 66 I/O TTL Capture/Compare/PWM 0.
General-Purpose
Timers
CCP1 43 I/O TTL Capture/Compare/PWM 1.
CCP2 67 I/O TTL Capture/Compare/PWM 2.
CCP3 95 I/O TTL Capture/Compare/PWM 3.
CCP4 96 I/O TTL Capture/Compare/PWM 4.
CCP5 40 I/O TTL Capture/Compare/PWM 5.
An open-drain output with internal pull-up that
indicates the processor is in Hibernate mode.
HIB 51 O OD
Hibernate
Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
VBAT 55 - Power
An external input that brings the processor out of
Hibernate mode when asserted.
WAKE 50 I TTL
Hibernation module oscillator crystal input or an
external clock reference input. Note that this is
either a crystal or a 32.768-kHz oscillator for the
Hibernation module RTC.
XOSC0 52 I Analog
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock
source.
XOSC1 53 O Analog
I2C0SCL 70 I/O OD I2C module 0 clock.
I2C
I2C0SDA 71 I/O OD I2C module 0 data.
I2C1SCL 34 I/O OD I2C module 1 clock.
I2C1SDA 35 I/O OD I2C module 1 data.
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Table 20-3. Signals by Function, Except for GPIO (continued)
Function Pin Name Pin Number Pin Type Buffer Typea Description
SWCLK 80 I TTL JTAG/SWD CLK.
JTAG/SWD/SWO
SWDIO 79 I/O TTL JTAG TMS and SWDIO.
SWO 77 O TTL JTAG TDO and SWO.
TCK 80 I TTL JTAG/SWD CLK.
TDI 78 I TTL JTAG TDI.
TDO 77 O TTL JTAG TDO and SWO.
TMS 79 I/O TTL JTAG TMS and SWDIO.
TRST 89 I TTL JTAG TRST.
Fault 99 I TTL PWM Fault.
PWM
PWM 0. This signal is controlled by PWM Generator
0.
PWM0 17 O TTL
PWM 1. This signal is controlled by PWM Generator
0.
PWM1 16 O TTL
PWM 2. This signal is controlled by PWM Generator
1.
PWM2 86 O TTL
PWM 3. This signal is controlled by PWM Generator
1.
PWM3 85 O TTL
PWM 4. This signal is controlled by PWM Generator
2.
PWM4 60 O TTL
PWM 5. This signal is controlled by PWM Generator
2.
PWM5 59 O TTL
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Table 20-3. Signals by Function, Except for GPIO (continued)
Function Pin Name Pin Number Pin Type Buffer Typea Description
9 - Power Ground reference for logic and I/O pins.
15
21
33
39
45
54
57
63
69
82
87
94
GND
Power
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
4 - Power
97
GNDA
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 μF or greater. When the on-chip LDO is
used to provide power to the logic, the LDO pin must
also be connected to the VDD25 pins at the board
level in addition to the decoupling capacitor(s).
LDO 7 - Power
8 - Power Positive supply for I/O and some logic.
20
32
44
56
68
81
93
VDD
Positive supply for most of the logic function,
including the processor core and most peripherals.
14 - Power
38
62
88
VDD25
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V,
regardless of system implementation.
3 - Power
98
VDDA
IDX0 100 I TTL QEI module 0 index.
QEI
IDX1 84 I TTL QEI module 1 index.
PhA0 25 I TTL QEI module 0 phase A.
PhA1 37 I TTL QEI module 1 phase A.
PhB0 83 I TTL QEI module 0 phase B.
PhB1 36 I TTL QEI module 1 phase B.
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Table 20-3. Signals by Function, Except for GPIO (continued)
Function Pin Name Pin Number Pin Type Buffer Typea Description
SSI0Clk 28 I/O TTL SSI module 0 clock.
SSI
SSI0Fss 29 I/O TTL SSI module 0 frame.
SSI0Rx 30 I TTL SSI module 0 receive.
SSI0Tx 31 O TTL SSI module 0 transmit.
SSI1Clk 72 I/O TTL SSI module 1 clock.
SSI1Fss 73 I/O TTL SSI module 1 frame.
SSI1Rx 74 I TTL SSI module 1 receive.
SSI1Tx 75 O TTL SSI module 1 transmit.
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD0 65 I TTL
System Control &
Clocks
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1 76 I TTL
Main oscillator crystal input or an external clock
reference input.
OSC0 48 I Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
OSC1 49 O Analog
RST 64 I TTL System reset input.
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
U0Rx 26 I TTL
UART
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U0Tx 27 O TTL
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
U1Rx 12 I TTL
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U1Tx 13 O TTL
UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
U2Rx 19 I TTL
UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Tx 18 O TTL
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 20-4. GPIO Pins and Alternate Functions
IO Pin Number Multiplexed Function Multiplexed Function
PA0 26 U0Rx
PA1 27 U0Tx
PA2 28 SSI0Clk
PA3 29 SSI0Fss
PA4 30 SSI0Rx
PA5 31 SSI0Tx
PA6 34 I2C1SCL
PA7 35 I2C1SDA
PB0 66 CCP0
PB1 67 CCP2
PB2 70 I2C0SCL
PB3 71 I2C0SDA
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Table 20-4. GPIO Pins and Alternate Functions (continued)
IO Pin Number Multiplexed Function Multiplexed Function
PB4 92 C0-
PB5 91 C1-
PB6 90 C0+
PB7 89 TRST
PC0 80 TCK SWCLK
PC1 79 TMS SWDIO
PC2 78 TDI
PC3 77 TDO SWO
PC4 25 PhA0
PC5 24 C1+
PC6 23 C2+
PC7 22 C2-
PD0 10 CAN0Rx
PD1 11 CAN0Tx
PD2 12 U1Rx
PD3 13 U1Tx
PD4 95 CCP3
PD5 96 CCP4
PD6 99 Fault
PD7 100 IDX0
PE0 72 SSI1Clk
PE1 73 SSI1Fss
PE2 74 SSI1Rx
PE3 75 SSI1Tx
PF0 47 CAN1Rx
PF1 61 CAN1Tx
PF2 60 PWM4
PF3 59 PWM5
PF4 58 C0o
PF5 46
PF6 43 CCP1
PF7 42
PG0 19 U2Rx
PG1 18 U2Tx
PG2 17 PWM0
PG3 16 PWM1
PG4 41
PG5 40 CCP5
PG6 37 PhA1
PG7 36 PhB1
PH0 86 PWM2
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Table 20-4. GPIO Pins and Alternate Functions (continued)
IO Pin Number Multiplexed Function Multiplexed Function
PH1 85 PWM3
PH2 84 IDX1
PH3 83 PhB0
20.2 108-Pin BGA Package Pin Tables
Table 20-5. Signals by Pin Number
Pin Number Pin Name Pin Type Buffer Typea Description
A1 ADC1 I Analog Analog-to-digital converter input 1.
A2 NC - - No connect. Leave the pin electrically unconnected/isolated.
A3 NC - - No connect. Leave the pin electrically unconnected/isolated.
A4 NC - - No connect. Leave the pin electrically unconnected/isolated.
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
GNDA - Power
A5
PB4 I/O TTL GPIO port B bit 4.
A6
C0- I Analog Analog comparator 0 negative input.
PB6 I/O TTL GPIO port B bit 6.
A7
C0+ I Analog Analog comparator 0 positive input.
PB7 I/O TTL GPIO port B bit 7.
A8
TRST I TTL JTAG TRST.
PC0 I/O TTL GPIO port C bit 0.
A9 SWCLK I TTL JTAG/SWD CLK.
TCK I TTL JTAG/SWD CLK.
PC3 I/O TTL GPIO port C bit 3.
A10 SWO O TTL JTAG TDO and SWO.
TDO O TTL JTAG TDO and SWO.
PE0 I/O TTL GPIO port E bit 0.
A11
SSI1Clk I/O TTL SSI module 1 clock.
PE3 I/O TTL GPIO port E bit 3.
A12
SSI1Tx O TTL SSI module 1 transmit.
B1 ADC0 I Analog Analog-to-digital converter input 0.
B2 ADC3 I Analog Analog-to-digital converter input 3.
B3 ADC2 I Analog Analog-to-digital converter input 2.
B4 NC - - No connect. Leave the pin electrically unconnected/isolated.
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
GNDA - Power
B5
B6 GND - Power Ground reference for logic and I/O pins.
PB5 I/O TTL GPIO port B bit 5.
B7
C1- I Analog Analog comparator 1 negative input.
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Table 20-5. Signals by Pin Number (continued)
Pin Number Pin Name Pin Type Buffer Typea Description
PC2 I/O TTL GPIO port C bit 2.
B8
TDI I TTL JTAG TDI.
PC1 I/O TTL GPIO port C bit 1.
B9 SWDIO I/O TTL JTAG TMS and SWDIO.
TMS I/O TTL JTAG TMS and SWDIO.
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
CMOD1 I TTL B10
PE2 I/O TTL GPIO port E bit 2.
B11
SSI1Rx I TTL SSI module 1 receive.
PE1 I/O TTL GPIO port E bit 1.
B12
SSI1Fss I/O TTL SSI module 1 frame.
C1 NC - - No connect. Leave the pin electrically unconnected/isolated.
C2 NC - - No connect. Leave the pin electrically unconnected/isolated.
Positive supply for most of the logic function, including the
processor core and most peripherals.
VDD25 - Power C3
C4 GND - Power Ground reference for logic and I/O pins.
C5 GND - Power Ground reference for logic and I/O pins.
The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
VDDA - Power
C6
The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
VDDA - Power
C7
PH1 I/O TTL GPIO port H bit 1.
C8
PWM3 O TTL PWM 3. This signal is controlled by PWM Generator 1.
PH0 I/O TTL GPIO port H bit 0.
C9
PWM2 O TTL PWM 2. This signal is controlled by PWM Generator 1.
PG7 I/O TTL GPIO port G bit 7.
C10
PhB1 I TTL QEI module 1 phase B.
PB2 I/O TTL GPIO port B bit 2.
C11
I2C0SCL I/O OD I2C module 0 clock.
PB3 I/O TTL GPIO port B bit 3.
C12
I2C0SDA I/O OD I2C module 0 data.
D1 NC - - No connect. Leave the pin electrically unconnected/isolated.
D2 NC - - No connect. Leave the pin electrically unconnected/isolated.
Positive supply for most of the logic function, including the
processor core and most peripherals.
VDD25 - Power D3
PH3 I/O TTL GPIO port H bit 3.
D10
PhB0 I TTL QEI module 0 phase B.
PH2 I/O TTL GPIO port H bit 2.
D11
IDX1 I TTL QEI module 1 index.
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Table 20-5. Signals by Pin Number (continued)
Pin Number Pin Name Pin Type Buffer Typea Description
PB1 I/O TTL GPIO port B bit 1.
D12
CCP2 I/O TTL Capture/Compare/PWM 2.
PD4 I/O TTL GPIO port D bit 4.
E1
CCP3 I/O TTL Capture/Compare/PWM 3.
PD5 I/O TTL GPIO port D bit 5.
E2
CCP4 I/O TTL Capture/Compare/PWM 4.
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 μF or greater. When the
on-chip LDO is used to provide power to the logic, the LDO pin
must also be connected to the VDD25 pins at the board level in
addition to the decoupling capacitor(s).
LDO - Power
E3
E10 VDD33 - Power Positive supply for I/O and some logic.
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
CMOD0 I TTL E11
PB0 I/O TTL GPIO port B bit 0.
E12
CCP0 I/O TTL Capture/Compare/PWM 0.
PD7 I/O TTL GPIO port D bit 7.
F1
IDX0 I TTL QEI module 0 index.
PD6 I/O TTL GPIO port D bit 6.
F2
Fault I TTL PWM Fault.
Positive supply for most of the logic function, including the
processor core and most peripherals.
VDD25 - Power F3
F10 GND - Power Ground reference for logic and I/O pins.
F11 GND - Power Ground reference for logic and I/O pins.
F12 GND - Power Ground reference for logic and I/O pins.
PD0 I/O TTL GPIO port D bit 0.
G1
CAN0Rx I TTL CAN module 0 receive.
PD1 I/O TTL GPIO port D bit 1.
G2
CAN0Tx O TTL CAN module 0 transmit.
Positive supply for most of the logic function, including the
processor core and most peripherals.
VDD25 - Power G3
G10 VDD33 - Power Positive supply for I/O and some logic.
G11 VDD33 - Power Positive supply for I/O and some logic.
G12 VDD33 - Power Positive supply for I/O and some logic.
PD3 I/O TTL GPIO port D bit 3.
H1 UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
U1Tx O TTL
PD2 I/O TTL GPIO port D bit 2.
H2 UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
U1Rx I TTL
H3 GND - Power Ground reference for logic and I/O pins.
H10 VDD33 - Power Positive supply for I/O and some logic.
H11 RST I TTL System reset input.
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Table 20-5. Signals by Pin Number (continued)
Pin Number Pin Name Pin Type Buffer Typea Description
PF1 I/O TTL GPIO port F bit 1.
H12
CAN1Tx O TTL CAN module 1 transmit.
PG2 I/O TTL GPIO port G bit 2.
J1
PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0.
PG3 I/O TTL GPIO port G bit 3.
J2
PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0.
J3 GND - Power Ground reference for logic and I/O pins.
J10 GND - Power Ground reference for logic and I/O pins.
PF2 I/O TTL GPIO port F bit 2.
J11
PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2.
PF3 I/O TTL GPIO port F bit 3.
J12
PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2.
PG0 I/O TTL GPIO port G bit 0.
K1 UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
U2Rx I TTL
PG1 I/O TTL GPIO port G bit 1.
K2 UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
U2Tx O TTL
K3 PG4 I/O TTL GPIO port G bit 4.
K4 PF7 I/O TTL GPIO port F bit 7.
K5 GND - Power Ground reference for logic and I/O pins.
K6 GND - Power Ground reference for logic and I/O pins.
K7 VDD33 - Power Positive supply for I/O and some logic.
K8 VDD33 - Power Positive supply for I/O and some logic.
K9 VDD33 - Power Positive supply for I/O and some logic.
K10 GND - Power Ground reference for logic and I/O pins.
Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a 32.768-kHz
oscillator for the Hibernation module RTC.
XOSC0 I Analog
K11
Hibernation module oscillator crystal output. Leave unconnected
when using a single-ended clock source.
XOSC1 O Analog K12
PC4 I/O TTL GPIO port C bit 4.
L1
PhA0 I TTL QEI module 0 phase A.
PC7 I/O TTL GPIO port C bit 7.
L2
C2- I Analog Analog comparator 2 negative input.
PA0 I/O TTL GPIO port A bit 0.
L3 UART module 0 receive. When in IrDA mode, this signal has IrDA
modulation.
U0Rx I TTL
PA3 I/O TTL GPIO port A bit 3.
L4
SSI0Fss I/O TTL SSI module 0 frame.
PA4 I/O TTL GPIO port A bit 4.
L5
SSI0Rx I TTL SSI module 0 receive.
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Table 20-5. Signals by Pin Number (continued)
Pin Number Pin Name Pin Type Buffer Typea Description
PA6 I/O TTL GPIO port A bit 6.
L6
I2C1SCL I/O OD I2C module 1 clock.
PG6 I/O TTL GPIO port G bit 6.
L7
PhA1 I TTL QEI module 1 phase A.
L8 PF5 I/O TTL GPIO port F bit 5.
PF4 I/O TTL GPIO port F bit 4.
L9
C0o O TTL Analog comparator 0 output.
L10 GND - Power Ground reference for logic and I/O pins.
L11 OSC0 I Analog Main oscillator crystal input or an external clock reference input.
Power source for the Hibernation module. It is normally connected
to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
VBAT - Power
L12
PC5 I/O TTL GPIO port C bit 5.
M1
C1+ I Analog Analog comparator 1 positive input.
PC6 I/O TTL GPIO port C bit 6.
M2
C2+ I Analog Analog comparator 2 positive input.
PA1 I/O TTL GPIO port A bit 1.
M3 UART module 0 transmit. When in IrDA mode, this signal has IrDA
modulation.
U0Tx O TTL
PA2 I/O TTL GPIO port A bit 2.
M4
SSI0Clk I/O TTL SSI module 0 clock.
PA5 I/O TTL GPIO port A bit 5.
M5
SSI0Tx O TTL SSI module 0 transmit.
PA7 I/O TTL GPIO port A bit 7.
M6
I2C1SDA I/O OD I2C module 1 data.
PG5 I/O TTL GPIO port G bit 5.
M7
CCP5 I/O TTL Capture/Compare/PWM 5.
PF6 I/O TTL GPIO port F bit 6.
M8
CCP1 I/O TTL Capture/Compare/PWM 1.
PF0 I/O TTL GPIO port F bit 0.
M9
CAN1Rx I TTL CAN module 1 receive.
An external input that brings the processor out of Hibernate mode
when asserted.
WAKE I TTL M10
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
OSC1 O Analog M11
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
HIB O OD M12
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 20-6. Signals by Signal Name
Pin Name Pin Number Pin Type Buffer Typea Description
ADC0 B1 I Analog Analog-to-digital converter input 0.
ADC1 A1 I Analog Analog-to-digital converter input 1.
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Table 20-6. Signals by Signal Name (continued)
Pin Name Pin Number Pin Type Buffer Typea Description
ADC2 B3 I Analog Analog-to-digital converter input 2.
ADC3 B2 I Analog Analog-to-digital converter input 3.
C0+ A7 I Analog Analog comparator 0 positive input.
C0- A6 I Analog Analog comparator 0 negative input.
C0o L9 O TTL Analog comparator 0 output.
C1+ M1 I Analog Analog comparator 1 positive input.
C1- B7 I Analog Analog comparator 1 negative input.
C2+ M2 I Analog Analog comparator 2 positive input.
C2- L2 I Analog Analog comparator 2 negative input.
CAN0Rx G1 I TTL CAN module 0 receive.
CAN0Tx G2 O TTL CAN module 0 transmit.
CAN1Rx M9 I TTL CAN module 1 receive.
CAN1Tx H12 O TTL CAN module 1 transmit.
CCP0 E12 I/O TTL Capture/Compare/PWM 0.
CCP1 M8 I/O TTL Capture/Compare/PWM 1.
CCP2 D12 I/O TTL Capture/Compare/PWM 2.
CCP3 E1 I/O TTL Capture/Compare/PWM 3.
CCP4 E2 I/O TTL Capture/Compare/PWM 4.
CCP5 M7 I/O TTL Capture/Compare/PWM 5.
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
CMOD0 E11 I TTL
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
CMOD1 B10 I TTL
Fault F2 I TTL PWM Fault.
B6 - Power Ground reference for logic and I/O pins.
C4
C5
F10
F11
F12
H3
J3
J10
K5
K6
K10
L10
GND
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to
minimize the electrical noise contained on VDD from affecting
the analog functions.
A5 - Power
B5
GNDA
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
HIB M12 O OD
I2C0SCL C11 I/O OD I2C module 0 clock.
I2C0SDA C12 I/O OD I2C module 0 data.
I2C1SCL L6 I/O OD I2C module 1 clock.
I2C1SDA M6 I/O OD I2C module 1 data.
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Table 20-6. Signals by Signal Name (continued)
Pin Name Pin Number Pin Type Buffer Typea Description
IDX0 F1 I TTL QEI module 0 index.
IDX1 D11 I TTL QEI module 1 index.
Low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 μF or
greater. When the on-chip LDO is used to provide power to
the logic, the LDO pin must also be connected to the VDD25
pins at the board level in addition to the decoupling
capacitor(s).
LDO E3 - Power
A2 - - No connect. Leave the pin electrically unconnected/isolated.
A3
A4
B4
C1
C2
D1
D2
NC
Main oscillator crystal input or an external clock reference
input.
OSC0 L11 I Analog
Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
OSC1 M11 O Analog
PA0 L3 I/O TTL GPIO port A bit 0.
PA1 M3 I/O TTL GPIO port A bit 1.
PA2 M4 I/O TTL GPIO port A bit 2.
PA3 L4 I/O TTL GPIO port A bit 3.
PA4 L5 I/O TTL GPIO port A bit 4.
PA5 M5 I/O TTL GPIO port A bit 5.
PA6 L6 I/O TTL GPIO port A bit 6.
PA7 M6 I/O TTL GPIO port A bit 7.
PB0 E12 I/O TTL GPIO port B bit 0.
PB1 D12 I/O TTL GPIO port B bit 1.
PB2 C11 I/O TTL GPIO port B bit 2.
PB3 C12 I/O TTL GPIO port B bit 3.
PB4 A6 I/O TTL GPIO port B bit 4.
PB5 B7 I/O TTL GPIO port B bit 5.
PB6 A7 I/O TTL GPIO port B bit 6.
PB7 A8 I/O TTL GPIO port B bit 7.
PC0 A9 I/O TTL GPIO port C bit 0.
PC1 B9 I/O TTL GPIO port C bit 1.
PC2 B8 I/O TTL GPIO port C bit 2.
PC3 A10 I/O TTL GPIO port C bit 3.
PC4 L1 I/O TTL GPIO port C bit 4.
PC5 M1 I/O TTL GPIO port C bit 5.
PC6 M2 I/O TTL GPIO port C bit 6.
PC7 L2 I/O TTL GPIO port C bit 7.
PD0 G1 I/O TTL GPIO port D bit 0.
PD1 G2 I/O TTL GPIO port D bit 1.
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Table 20-6. Signals by Signal Name (continued)
Pin Name Pin Number Pin Type Buffer Typea Description
PD2 H2 I/O TTL GPIO port D bit 2.
PD3 H1 I/O TTL GPIO port D bit 3.
PD4 E1 I/O TTL GPIO port D bit 4.
PD5 E2 I/O TTL GPIO port D bit 5.
PD6 F2 I/O TTL GPIO port D bit 6.
PD7 F1 I/O TTL GPIO port D bit 7.
PE0 A11 I/O TTL GPIO port E bit 0.
PE1 B12 I/O TTL GPIO port E bit 1.
PE2 B11 I/O TTL GPIO port E bit 2.
PE3 A12 I/O TTL GPIO port E bit 3.
PF0 M9 I/O TTL GPIO port F bit 0.
PF1 H12 I/O TTL GPIO port F bit 1.
PF2 J11 I/O TTL GPIO port F bit 2.
PF3 J12 I/O TTL GPIO port F bit 3.
PF4 L9 I/O TTL GPIO port F bit 4.
PF5 L8 I/O TTL GPIO port F bit 5.
PF6 M8 I/O TTL GPIO port F bit 6.
PF7 K4 I/O TTL GPIO port F bit 7.
PG0 K1 I/O TTL GPIO port G bit 0.
PG1 K2 I/O TTL GPIO port G bit 1.
PG2 J1 I/O TTL GPIO port G bit 2.
PG3 J2 I/O TTL GPIO port G bit 3.
PG4 K3 I/O TTL GPIO port G bit 4.
PG5 M7 I/O TTL GPIO port G bit 5.
PG6 L7 I/O TTL GPIO port G bit 6.
PG7 C10 I/O TTL GPIO port G bit 7.
PH0 C9 I/O TTL GPIO port H bit 0.
PH1 C8 I/O TTL GPIO port H bit 1.
PH2 D11 I/O TTL GPIO port H bit 2.
PH3 D10 I/O TTL GPIO port H bit 3.
PhA0 L1 I TTL QEI module 0 phase A.
PhA1 L7 I TTL QEI module 1 phase A.
PhB0 D10 I TTL QEI module 0 phase B.
PhB1 C10 I TTL QEI module 1 phase B.
PWM0 J1 O TTL PWM 0. This signal is controlled by PWM Generator 0.
PWM1 J2 O TTL PWM 1. This signal is controlled by PWM Generator 0.
PWM2 C9 O TTL PWM 2. This signal is controlled by PWM Generator 1.
PWM3 C8 O TTL PWM 3. This signal is controlled by PWM Generator 1.
PWM4 J11 O TTL PWM 4. This signal is controlled by PWM Generator 2.
PWM5 J12 O TTL PWM 5. This signal is controlled by PWM Generator 2.
RST H11 I TTL System reset input.
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Table 20-6. Signals by Signal Name (continued)
Pin Name Pin Number Pin Type Buffer Typea Description
SSI0Clk M4 I/O TTL SSI module 0 clock.
SSI0Fss L4 I/O TTL SSI module 0 frame.
SSI0Rx L5 I TTL SSI module 0 receive.
SSI0Tx M5 O TTL SSI module 0 transmit.
SSI1Clk A11 I/O TTL SSI module 1 clock.
SSI1Fss B12 I/O TTL SSI module 1 frame.
SSI1Rx B11 I TTL SSI module 1 receive.
SSI1Tx A12 O TTL SSI module 1 transmit.
SWCLK A9 I TTL JTAG/SWD CLK.
SWDIO B9 I/O TTL JTAG TMS and SWDIO.
SWO A10 O TTL JTAG TDO and SWO.
TCK A9 I TTL JTAG/SWD CLK.
TDI B8 I TTL JTAG TDI.
TDO A10 O TTL JTAG TDO and SWO.
TMS B9 I/O TTL JTAG TMS and SWDIO.
TRST A8 I TTL JTAG TRST.
UART module 0 receive. When in IrDA mode, this signal has
IrDA modulation.
U0Rx L3 I TTL
UART module 0 transmit. When in IrDA mode, this signal has
IrDA modulation.
U0Tx M3 O TTL
UART module 1 receive. When in IrDA mode, this signal has
IrDA modulation.
U1Rx H2 I TTL
UART module 1 transmit. When in IrDA mode, this signal has
IrDA modulation.
U1Tx H1 O TTL
UART module 2 receive. When in IrDA mode, this signal has
IrDA modulation.
U2Rx K1 I TTL
UART module 2 transmit. When in IrDA mode, this signal has
IrDA modulation.
U2Tx K2 O TTL
Power source for the Hibernation module. It is normally
connected to the positive terminal of a battery and serves as
the battery backup/Hibernation module power-source supply.
VBAT L12 - Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
C3 - Power
D3
F3
G3
VDD25
E10 - Power Positive supply for I/O and some logic.
G10
G11
G12
H10
K7
K8
K9
VDD33
The positive supply (3.3 V) for the analog circuits (ADC,
Analog Comparators, etc.). These are separated from VDD
to minimize the electrical noise contained on VDD from
affecting the analog functions. VDDA pins must be connected
to 3.3 V, regardless of system implementation.
C6 - Power
C7
VDDA
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Table 20-6. Signals by Signal Name (continued)
Pin Name Pin Number Pin Type Buffer Typea Description
An external input that brings the processor out of Hibernate
mode when asserted.
WAKE M10 I TTL
Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a
32.768-kHz oscillator for the Hibernation module RTC.
XOSC0 K11 I Analog
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock source.
XOSC1 K12 O Analog
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 20-7. Signals by Function, Except for GPIO
Function Pin Name Pin Number Pin Type Buffer Typea Description
ADC0 B1 I Analog Analog-to-digital converter input 0.
ADC
ADC1 A1 I Analog Analog-to-digital converter input 1.
ADC2 B3 I Analog Analog-to-digital converter input 2.
ADC3 B2 I Analog Analog-to-digital converter input 3.
C0+ A7 I Analog Analog comparator 0 positive input.
Analog Comparators
C0- A6 I Analog Analog comparator 0 negative input.
C0o L9 O TTL Analog comparator 0 output.
C1+ M1 I Analog Analog comparator 1 positive input.
C1- B7 I Analog Analog comparator 1 negative input.
C2+ M2 I Analog Analog comparator 2 positive input.
C2- L2 I Analog Analog comparator 2 negative input.
CAN0Rx G1 I TTL CAN module 0 receive.
Controller Area
Network
CAN0Tx G2 O TTL CAN module 0 transmit.
CAN1Rx M9 I TTL CAN module 1 receive.
CAN1Tx H12 O TTL CAN module 1 transmit.
CCP0 E12 I/O TTL Capture/Compare/PWM 0.
General-Purpose
Timers
CCP1 M8 I/O TTL Capture/Compare/PWM 1.
CCP2 D12 I/O TTL Capture/Compare/PWM 2.
CCP3 E1 I/O TTL Capture/Compare/PWM 3.
CCP4 E2 I/O TTL Capture/Compare/PWM 4.
CCP5 M7 I/O TTL Capture/Compare/PWM 5.
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Table 20-7. Signals by Function, Except for GPIO (continued)
Function Pin Name Pin Number Pin Type Buffer Typea Description
An open-drain output with internal pull-up that
indicates the processor is in Hibernate mode.
HIB M12 O OD
Hibernate
Power source for the Hibernation module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation module power-source supply.
VBAT L12 - Power
An external input that brings the processor out of
Hibernate mode when asserted.
WAKE M10 I TTL
Hibernation module oscillator crystal input or an
external clock reference input. Note that this is
either a crystal or a 32.768-kHz oscillator for the
Hibernation module RTC.
XOSC0 K11 I Analog
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock
source.
XOSC1 K12 O Analog
I2C0SCL C11 I/O OD I2C module 0 clock.
I2C
I2C0SDA C12 I/O OD I2C module 0 data.
I2C1SCL L6 I/O OD I2C module 1 clock.
I2C1SDA M6 I/O OD I2C module 1 data.
SWCLK A9 I TTL JTAG/SWD CLK.
JTAG/SWD/SWO
SWDIO B9 I/O TTL JTAG TMS and SWDIO.
SWO A10 O TTL JTAG TDO and SWO.
TCK A9 I TTL JTAG/SWD CLK.
TDI B8 I TTL JTAG TDI.
TDO A10 O TTL JTAG TDO and SWO.
TMS B9 I/O TTL JTAG TMS and SWDIO.
TRST A8 I TTL JTAG TRST.
Fault F2 I TTL PWM Fault.
PWM
PWM 0. This signal is controlled by PWM Generator
0.
PWM0 J1 O TTL
PWM 1. This signal is controlled by PWM Generator
0.
PWM1 J2 O TTL
PWM 2. This signal is controlled by PWM Generator
1.
PWM2 C9 O TTL
PWM 3. This signal is controlled by PWM Generator
1.
PWM3 C8 O TTL
PWM 4. This signal is controlled by PWM Generator
2.
PWM4 J11 O TTL
PWM 5. This signal is controlled by PWM Generator
2.
PWM5 J12 O TTL
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Table 20-7. Signals by Function, Except for GPIO (continued)
Function Pin Name Pin Number Pin Type Buffer Typea Description
B6 - Power Ground reference for logic and I/O pins.
C4
C5
F10
F11
F12
H3
J3
J10
K5
K6
K10
L10
GND
Power
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
A5 - Power
B5
GNDA
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 μF or greater. When the on-chip LDO is
used to provide power to the logic, the LDO pin must
also be connected to the VDD25 pins at the board
level in addition to the decoupling capacitor(s).
LDO E3 - Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
C3 - Power
D3
F3
G3
VDD25
E10 - Power Positive supply for I/O and some logic.
G10
G11
G12
H10
K7
K8
K9
VDD33
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V,
regardless of system implementation.
C6 - Power
C7
VDDA
IDX0 F1 I TTL QEI module 0 index.
QEI
IDX1 D11 I TTL QEI module 1 index.
PhA0 L1 I TTL QEI module 0 phase A.
PhA1 L7 I TTL QEI module 1 phase A.
PhB0 D10 I TTL QEI module 0 phase B.
PhB1 C10 I TTL QEI module 1 phase B.
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Table 20-7. Signals by Function, Except for GPIO (continued)
Function Pin Name Pin Number Pin Type Buffer Typea Description
SSI0Clk M4 I/O TTL SSI module 0 clock.
SSI
SSI0Fss L4 I/O TTL SSI module 0 frame.
SSI0Rx L5 I TTL SSI module 0 receive.
SSI0Tx M5 O TTL SSI module 0 transmit.
SSI1Clk A11 I/O TTL SSI module 1 clock.
SSI1Fss B12 I/O TTL SSI module 1 frame.
SSI1Rx B11 I TTL SSI module 1 receive.
SSI1Tx A12 O TTL SSI module 1 transmit.
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD0 E11 I TTL
System Control &
Clocks
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1 B10 I TTL
Main oscillator crystal input or an external clock
reference input.
OSC0 L11 I Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
OSC1 M11 O Analog
RST H11 I TTL System reset input.
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
U0Rx L3 I TTL
UART
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U0Tx M3 O TTL
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
U1Rx H2 I TTL
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U1Tx H1 O TTL
UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
U2Rx K1 I TTL
UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Tx K2 O TTL
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 20-8. GPIO Pins and Alternate Functions
IO Pin Number Multiplexed Function Multiplexed Function
PA0 L3 U0Rx
PA1 M3 U0Tx
PA2 M4 SSI0Clk
PA3 L4 SSI0Fss
PA4 L5 SSI0Rx
PA5 M5 SSI0Tx
PA6 L6 I2C1SCL
PA7 M6 I2C1SDA
PB0 E12 CCP0
PB1 D12 CCP2
PB2 C11 I2C0SCL
PB3 C12 I2C0SDA
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Table 20-8. GPIO Pins and Alternate Functions (continued)
IO Pin Number Multiplexed Function Multiplexed Function
PB4 A6 C0-
PB5 B7 C1-
PB6 A7 C0+
PB7 A8 TRST
PC0 A9 TCK SWCLK
PC1 B9 TMS SWDIO
PC2 B8 TDI
PC3 A10 TDO SWO
PC4 L1 PhA0
PC5 M1 C1+
PC6 M2 C2+
PC7 L2 C2-
PD0 G1 CAN0Rx
PD1 G2 CAN0Tx
PD2 H2 U1Rx
PD3 H1 U1Tx
PD4 E1 CCP3
PD5 E2 CCP4
PD6 F2 Fault
PD7 F1 IDX0
PE0 A11 SSI1Clk
PE1 B12 SSI1Fss
PE2 B11 SSI1Rx
PE3 A12 SSI1Tx
PF0 M9 CAN1Rx
PF1 H12 CAN1Tx
PF2 J11 PWM4
PF3 J12 PWM5
PF4 L9 C0o
PF5 L8
PF6 M8 CCP1
PF7 K4
PG0 K1 U2Rx
PG1 K2 U2Tx
PG2 J1 PWM0
PG3 J2 PWM1
PG4 K3
PG5 M7 CCP5
PG6 L7 PhA1
PG7 C10 PhB1
PH0 C9 PWM2
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Table 20-8. GPIO Pins and Alternate Functions (continued)
IO Pin Number Multiplexed Function Multiplexed Function
PH1 C8 PWM3
PH2 D11 IDX1
PH3 D10 PhB0
20.3 Connections for Unused Signals
Table 20-9 on page 676 show how to handle signals for functions that are not used in a particular
system implementation for devices that are in a 100-pin LQFP package. Two options are shown in
the table: an acceptable practice and a preferred practice for reduced power consumption and
improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it
is important that the clock to the module is never enabled by setting the corresponding bit in the
RCGCx register.
Table 20-9. Connections for Unused Signals (100-pin LQFP)
Function Signal Name Pin Number Acceptable Practice Preferred Practice
1 NC GNDA
2
3
4
ADC0
ADC1
ADC2
ADC3
ADC
GPIO All unused GPIOs - NC GND
HIB 51 NC NC
Hibernate
VBAT 55 NC GND
WAKE 50 NC GND
XOSC0 52 NC GND
XOSC1 53 NC NC
No Connects NC - NC NC
OSC0 48 NC GND
System Control OSC1 49 NC NC
Connect through a capacitor to
GND as close to pin as possible
Pull up as shown in Figure
5-1 on page 172
RST 48
Table 20-10 on page 676 show how to handle signals for functions that are not used in a particular
system implementation for devices that are in a 108-pin BGA package. Two options are shown in
the table: an acceptable practice and a preferred practice for reduced power consumption and
improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it
is important that the clock to the module is never enabled by setting the corresponding bit in the
RCGCx register.
Table 20-10. Connections for Unused Signals, 108-pin BGA
Function Signal Name Pin Number Acceptable Practice Preferred Practice
B1 NC GNDA
A1
B3
B2
ADC0
ADC1
ADC2
ADC3
ADC
GPIO All unused GPIOs - NC GND
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Table 20-10. Connections for Unused Signals, 108-pin BGA (continued)
Function Signal Name Pin Number Acceptable Practice Preferred Practice
HIB M12 NC NC
Hibernate
VBAT L12 NC GND
WAKE M10 NC GND
XOSC0 K11 NC GND
XOSC1 K12 NC NC
No Connects NC - NC NC
OSC0 L11 NC GND
System Control
OSC1 M11 NC NC
Connect through a capacitor
to GND as close to pin as
possible
Pull up as shown in Figure
5-1 on page 172
RST H11
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21 Operating Characteristics
Table 21-1. Temperature Characteristics
Characteristic Symbol Value Unit
Industrial operating temperature range TA -40 to +85 °C
Extended operating temperature range TA -40 to +105 °C
Unpowered storage temperature range TS -65 to +150 °C
Table 21-2. Thermal Characteristics
Characteristic Symbol Value Unit
Thermal resistance (junction to ambient)a ΘJA 32 °C/W
Junction temperatureb TJ TA + (P • ΘJA) °C
a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator.
b. Power dissipation is a function of temperature.
Table 21-3. ESD Absolute Maximum Ratingsa
Parameter Name Min Nom Max Unit
VESDHBM - - 2.0 kV
VESDCDM - - 1.0 kV
VESDMM - - 100 V
a. All Stellaris parts are ESD tested following the JEDEC standard.
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22 Electrical Characteristics
22.1 DC Characteristics
22.1.1 Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device.
Note: The device is not guaranteed to operate properly at the maximum ratings.
Table 22-1. Maximum Ratings
Unit
Value
Characteristic Symbol
a
Min Max
I/O supply voltage (VDD) VDD 0 4 V
Core supply voltage (VDD25) VDD25 0 3 V
Analog supply voltage (VDDA) VDDA 0 4 V
Battery supply voltage (VBAT) VBAT 0 4 V
Input voltage VIN -0.3 5.5 V
Maximum current per output pins I - 25 mA
Maximum input voltage on a non-power pin when the VNON - 300 mV
microcontroller is unpowered
a. Voltages are measured with respect to GND.
Important: This device contains circuitry to protect the inputs against damage due to high-static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are
connected to an appropriate logic voltage level (for example, either GND or VDD).
22.1.2 Recommended DC Operating Conditions
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.
Table 22-2. Recommended DC Operating Conditions
Parameter Parameter Name Min Nom Max Unit
VDD I/O supply voltage 3.0 3.3 3.6 V
VDD25 Core supply voltage 2.25 2.5 2.75 V
VDDA Analog supply voltage 3.0 3.3 3.6 V
VBAT Battery supply voltage 2.3 3.0 3.6 V
VIH High-level input voltage 2.0 - 5.0 V
VIL Low-level input voltage -0.3 - 1.3 V
VOH High-level output voltage 2.4 - - V
a
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Table 22-2. Recommended DC Operating Conditions (continued)
Parameter Parameter Name Min Nom Max Unit
VOL Low-level output voltage - - 0.4 V
a
High-level source current, VOH=2.4 V
IOH
2-mA Drive 2.0 - - mA
4-mA Drive 4.0 - - mA
8-mA Drive 8.0 - - mA
Low-level sink current, VOL=0.4 V
IOL
2-mA Drive 2.0 - - mA
4-mA Drive 4.0 - - mA
8-mA Drive 8.0 - - mA
a. VOL and VOH shift to 1.2 V when using high-current GPIOs.
22.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics
Table 22-3. LDO Regulator Characteristics
Parameter Parameter Name Min Nom Max Unit
Programmable internal (logic) power supply 2.25 2.5 2.75 V
VLDOOUT output value
Output voltage accuracy - 2% - %
tPON Power-on time - - 100 μs
tON Time on - - 200 μs
tOFF Time off - - 100 μs
VSTEP Step programming incremental voltage - 50 - mV
External filter capacitor size for internal power 1.0 - 3.0 μF
supply
CLDO
22.1.4 GPIO Module Characteristics
Table 22-4. GPIO Module DC Characteristics
Parameter Parameter Name Min Nom Max Unit
RGPIOPU GPIO internal pull-up resistor 50 - 110 kΩ
RGPIOPD GPIO internal pull-down resistor 55 - 180 kΩ
ILKG GPIO input leakage currenta - - 2 μA
a. The leakage current is measured with GND or VDD applied to the corresponding pin(s). The leakage of digital port pins is
measured individually. The port pin is configured as an input and the pullup/pulldown resistor is disabled.
22.1.5 Power Specifications
The power measurements specified in the tables that follow are run on the core processor using
SRAM with the following specifications (except as noted):
■ VDD = 3.3 V
■ VDD25 = 2.50 V
■ VBAT = 3.0 V
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■ VDDA = 3.3 V
■ Temperature = 25°C
■ Clock Source (MOSC) =3.579545 MHz Crystal Oscillator
■ Main oscillator (MOSC) = enabled
■ Internal oscillator (IOSC) = disabled
Table 22-5. Detailed Power Specifications
Unit
3.3 V VDD, 2.5 V VDD25 3.0 V VBAT
Parameter Conditions VDDA
Parameter Name
Nom Max Nom Max Nom Max
VDD25 = 2.50 V 3 pendinga 108 pendinga 0 pendinga mA
Code= while(1){} executed in
Flash
Peripherals = All ON
System Clock = 50 MHz (with
PLL)
Run mode 1
(Flash loop)
IDD_RUN
VDD25 = 2.50 V 0 pendinga 53 pendinga 0 pendinga mA
Code= while(1){} executed in
Flash
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
Run mode 2
(Flash loop)
VDD25 = 2.50 V 3 pendinga 102 pendinga 0 pendinga mA
Code= while(1){} executed in
SRAM
Peripherals = All ON
System Clock = 50 MHz (with
PLL)
Run mode 1
(SRAM loop)
VDD25 = 2.50 V 0 pendinga 47 pendinga 0 pendinga mA
Code= while(1){} executed in
SRAM
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
Run mode 2
(SRAM loop)
VDD25 = 2.50 V 0 pendinga 17 pendinga 0 pendinga mA
Peripherals = All OFF
System Clock = 50 MHz (with
PLL)
IDD_SLEEP Sleep mode
LDO = 2.25 V 0.14 pendinga 0.18 pendinga 0 pendinga mA
Peripherals = All OFF
System Clock = IOSC30KHZ/64
Deep-Sleep
mode
IDD_DEEPSLEEP
VBAT = 3.0 V 0 0 0 0 16 pendinga μA
VDD = 0 V
VDD25 = 0 V
VDDA = 0 V
Peripherals = All OFF
System Clock = OFF
Hibernate Module = 32 kHz
Hibernate
mode
IDD_HIBERNATE
a. Pending characterization completion.
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22.1.6 Flash Memory Characteristics
Table 22-6. Flash Memory Characteristics
Parameter Parameter Name Min Nom Max Unit
Number of guaranteed program/erase cycles 10,000 100,000 - cycles
before failurea
PECYC
Data retention at average operating temperature 10 - - years
of 85˚C (industrial) or 105˚C (extended)
TRET
TPROG Word program time 20 - - μs
TERASE Page erase time 20 - - ms
TME Mass erase time - - 250 ms
a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1.
22.1.7 Hibernation
Table 22-7. Hibernation Module DC Characteristics
Parameter Parameter Name Value Unit
VLOWBAT Low battery detect voltage 2.35 V
RWAKEPU WAKE internal pull-up resistor 200 kΩ
22.2 AC Characteristics
22.2.1 Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements. Timing
measurements are for 4-mA drive strength.
Figure 22-1. Load Conditions
CL = 50 pF
GND
pin
22.2.2 Clocks
Table 22-8. Phase Locked Loop (PLL) Characteristics
Parameter Parameter Name Min Nom Max Unit
fref_crystal Crystal referencea 3.579545 - 8.192 MHz
fref_ext External clock referencea 3.579545 - 8.192 MHz
fpll PLL frequencyb - 400 - MHz
TREADY PLL lock time - - 0.5 ms
a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration
(RCC) register.
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register.
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Table 22-9 on page 683 shows the actual frequency of the PLL based on the crystal frequency used
(defined by the XTAL field in the RCC register).
Table 22-9. Actual PLL Frequency
XTAL Crystal Frequency (MHz) PLL Frequency (MHz) Error
0x4 3.5795 400.904 0.0023%
0x5 3.6864 398.1312 0.0047%
0x6 4.0 400 -
0x7 4.096 401.408 0.0035%
0x8 4.9152 398.1312 0.0047%
0x9 5.0 400 -
0xA 5.12 399.36 0.0016%
0xB 6.0 400 -
0xC 6.144 399.36 0.0016%
0xD 7.3728 398.1312 0.0047%
0xE 8.0 400 0.0047%
0xF 8.192 398.6773333 0.0033%
Table 22-10. Clock Characteristics
Parameter Parameter Name Min Nom Max Unit
fIOSC Internal 12 MHz oscillator frequency 8.4 12 15.6 MHz
fIOSC30KHZ Internal 30 KHz oscillator frequency 15 30 45 KHz
fXOSC Hibernation module oscillator frequency - 4.194304 - MHz
fXOSC_XTAL Crystal reference for hibernation oscillator - 4.194304 - MHz
External clock reference for hibernation - 32.768 - KHz
module
fXOSC_EXT
fMOSC Main oscillator frequency 1 - 8.192 MHz
tMOSC_per Main oscillator period 125 - 1000 ns
Crystal reference using the main oscillator 1 - 8.192 MHz
(PLL in BYPASS mode)a
fref_crystal_bypass
External clock reference (PLL in BYPASS 0 - 50 MHz
mode)a
fref_ext_bypass
fsystem_clock System clock 0 - 50 MHz
a. The ADC must be clocked from the PLL or directly from a 16-MHz clock source to operate properly.
Table 22-11. Crystal Characteristics
Parameter Name Value Units
Frequency 8 6 4 3.5 MHz
Frequency tolerance ±50 ±50 ±50 ±50 ppm
Aging ±5 ±5 ±5 ±5 ppm/yr
Oscillation mode Parallel Parallel Parallel Parallel -
Temperature stability (-40°C to 85°C) ±25 ±25 ±25 ±25 ppm
Temperature stability (-40°C to 105°C) ±25 ±25 ±25 ±25 ppm
Motional capacitance (typ) 27.8 37.0 55.6 63.5 pF
Motional inductance (typ) 14.3 19.1 28.6 32.7 mH
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Table 22-11. Crystal Characteristics (continued)
Parameter Name Value Units
Equivalent series resistance (max) 120 160 200 220 Ω
Shunt capacitance (max) 10 10 10 10 pF
Load capacitance (typ) 16 16 16 16 pF
Drive level (typ) 100 100 100 100 μW
22.2.2.1 System Clock Specifications with ADC Operation
Table 22-12. System Clock Characteristics with ADC Operation
Parameter Parameter Name Min Nom Max Unit
System clock frequency when the ADC module is 16 - - MHz
operating (when PLL is bypassed)
fsysadc
22.2.3 JTAG and Boundary Scan
Table 22-13. JTAG Characteristics
Parameter Parameter Parameter Name Min Nom Max Unit
No.
J1 fTCK TCK operational clock frequency 0 - 10 MHz
J2 tTCK TCK operational clock period 100 - - ns
J3 tTCK_LOW TCK clock Low time - tTCK - ns
J4 tTCK_HIGH TCK clock High time - tTCK - ns
J5 tTCK_R TCK rise time 0 - 10 ns
J6 tTCK_F TCK fall time 0 - 10 ns
J7 tTMS_SU TMS setup time to TCK rise 20 - - ns
J8 tTMS_HLD TMS hold time from TCK rise 20 - - ns
J9 tTDI_SU TDI setup time to TCK rise 25 - - ns
J10 tTDI_HLD TDI hold time from TCK rise 25 - - ns
23 35 ns
-
2-mA drive
TCK fall to Data
Valid from High-Z
J11
t TDO_ZDV
4-mA drive 15 26 ns
8-mA drive 14 25 ns
8-mA drive with slew rate control 18 29 ns
21 35 ns
-
2-mA drive
TCK fall to Data
Valid from Data
Valid
J12
t TDO_DV
4-mA drive 14 25 ns
8-mA drive 13 24 ns
8-mA drive with slew rate control 18 28 ns
9 11 ns
-
2-mA drive
TCK fall to High-Z
from Data Valid
J13
t TDO_DVZ
4-mA drive 7 9 ns
8-mA drive 6 8 ns
8-mA drive with slew rate control 7 9 ns
J14 tTRST TRST assertion time 100 - - ns
J15 tTRST_SU TRST setup time to TCK rise 10 - - ns
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Figure 22-2. JTAG Test Clock Input Timing
TCK
J6 J5
J3 J4
J2
Figure 22-3. JTAG Test Access Port (TAP) Timing
TDO Output Valid
TCK
TDO Output Valid
J12
TDO
TDI
TMS
TDI Input Valid TDI Input Valid
J13
J9 J10
TMS Input Valid
J9 J10
TMS Input Valid
J11
J7 J8 J7 J8
Figure 22-4. JTAG TRST Timing
TCK
J14 J15
TRST
22.2.4 Reset
Table 22-14. Reset Characteristics
Parameter Parameter Parameter Name Min Nom Max Unit
No.
R1 VTH Reset threshold - 2.0 - V
R2 VBTH Brown-Out threshold 2.85 2.9 2.95 V
R3 TPOR Power-On Reset timeout - 10 - ms
R4 TBOR Brown-Out timeout - 500 - μs
R5 TIRPOR Internal reset timeout after POR 6 - 11 ms
R6 TIRBOR Internal reset timeout after BORa 0 - 1 μs
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Table 22-14. Reset Characteristics (continued)
Parameter Parameter Parameter Name Min Nom Max Unit
No.
Internal reset timeout after hardware reset 0 - 1 ms
(RST pin)
R7 TIRHWR
Internal reset timeout after software-initiated 2.5 - 20 μs
system reset a
R8 TIRSWR
R9 TIRWDR Internal reset timeout after watchdog reseta 2.5 - 20 μs
Supply voltage (VDD) rise time (0V-3.3V), - - 100 ms
power on reset
R10 TVDDRISE
Supply voltage (VDD) rise time (0V-3.3V), - - 250 μs
waking from hibernation
R11 TMIN Minimum RST pulse width 2 - - μs
a. 20 * t MOSC_per
Figure 22-5. External Reset Timing (RST)
RST
/Reset
(Internal)
R11 R7
Figure 22-6. Power-On Reset Timing
VDD
/POR
(Internal)
/Reset
(Internal)
R3
R1
R5
Figure 22-7. Brown-Out Reset Timing
VDD
/BOR
(Internal)
/Reset
(Internal)
R2
R4
R6
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Figure 22-8. Software Reset Timing
R8
SW Reset
/Reset
(Internal)
Figure 22-9. Watchdog Reset Timing
WDOG
Reset
(Internal)
/Reset
(Internal)
R9
22.2.5 Sleep Modes
Table 22-15. Sleep Modes AC Characteristicsa
Parameter No Parameter Parameter Name Min Nom Max Unit
Time to wake from interrupt in sleep or - - 7 system clocks
deep-sleep mode, not using the PLL
D1 tWAKE_S
Time to wake from interrupt in sleep or - - TREADY ms
deep-sleep mode when using the PLL
D2 tWAKE_PLL_S
a. Values in this table assume the IOSC is the clock source during sleep or deep-sleep mode.
22.2.6 Hibernation Module
The Hibernation Module requires special system implementation considerations since it is intended
to power-down all other sections of its host device. The system power-supply distribution and
interfaces to the device must be driven to 0 VDC or powered down with the same external voltage
regulator controlled by HIB.
The external voltage regulators controlled by HIB must have a settling time of 250 μs or less.
Table 22-16. Hibernation Module AC Characteristics
Parameter Parameter Parameter Name Min Nom Max Unit
No
Internal 32.768 KHz clock reference rising - 200 - μs
edge to /HIB asserted
H1 tHIB_LOW
Internal 32.768 KHz clock reference rising - 30 - μs
edge to /HIB deasserted
H2 tHIB_HIGH
H3 tWAKE_ASSERT /WAKE assertion time 62 - - μs
H4 tWAKETOHIB /WAKE assert to /HIB desassert 62 - 124 μs
H5 tXOSC_SETTLE XOSC settling timea 20 - - ms
Access time to or from a non-volatile register 92 - - μs
in HIB module to complete
H6 tHIB_REG_ACCESS
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Table 22-16. Hibernation Module AC Characteristics (continued)
Parameter Parameter Parameter Name Min Nom Max Unit
No
HIB deassert to VDD and VDD25 at minimum - - 250 μs
operational level
H7 tHIB_TO_VDD
a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care
must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance).
Figure 22-10. Hibernation Module Timing
32.768 KHz
(internal)
HIB
H4
H1
WAKE
H2
H3
22.2.7 General-Purpose I/O (GPIO)
Note: All GPIOs are 5 V-tolerant.
Table 22-17. GPIO Characteristics
Parameter Parameter Name Condition Min Nom Max Unit
17 26 ns
-
2-mA drive
GPIO Rise Time
(from 20% to 80%
of VDD)
tGPIOR
4-mA drive 9 13 ns
8-mA drive 6 9 ns
8-mA drive with slew rate control 10 12 ns
17 25 ns
-
2-mA drive
GPIO Fall Time
(from 80% to 20%
of VDD)
tGPIOF
4-mA drive 8 12 ns
8-mA drive 6 10 ns
8-mA drive with slew rate control 11 13 ns
22.2.8 Analog-to-Digital Converter
Table 22-18. ADC Characteristicsa
Parameter Parameter Name Min Nom Max Unit
Maximum single-ended, full-scale analog input - - 3.0 V
voltage
VADCIN
Minimum single-ended, full-scale analog input 0.0 - - V
voltage
Maximumdifferential, full-scale analog input voltage - - 1.5 V
Minimum differential, full-scale analog input voltage 0.0 - - V
N Resolution 10 bits
fADC ADC internal clock frequencyb 14 16 18 MHz
tADCCONV Conversion timec μs
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Table 22-18. ADC Characteristics (continued)
Parameter Parameter Name Min Nom Max Unit
f ADCCONV Conversion ratec k samples/s
tLT Latency from trigger to start of conversion - 2 - system clocks
IL ADC input leakage - - ±3.0 μA
RADC ADC equivalent resistance - - 10 kΩ
CADC ADC equivalent capacitance 0.9 1.0 1.1 pF
EL Integral nonlinearity error - - ±3 LSB
ED Differential nonlinearity error - - ±2 LSB
EO Offset error - - +6d LSB
EG Full-scale gain error - - ±3 LSB
ETS Temperature sensor accuracy - - ±5 °C
a. The ADC reference voltage is 3.0 V. This reference voltage is internally generated from the 3.3 VDDA supply by a band
gap circuit.
b. The ADC must be clocked from the PLL or directly from an external clock source to operate properly.
c. The conversion time and rate scale from the specified number if the ADC internal clock frequency is any value other than
16 MHz.
d. The offset error listed above is the conversion result with 0 V applied to the ADC input.
Figure 22-11. ADC Input Equivalency Diagram
Stellaris® Microcontroller
Sample and hold
ADC converter
CADC
RADC
VDD
10-bit
converter
VIN IL
Table 22-19. ADC Module Internal Reference Characteristics
Parameter Parameter Name Min Nom Max Unit
VREFI Internal voltage reference for ADC - 3.0 - V
EIR Internal voltage reference error - - ±2.5 %
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22.2.9 Synchronous Serial Interface (SSI)
Table 22-20. SSI Characteristics
Parameter Parameter Parameter Name Min Nom Max Unit
No.
S1 tclk_per SSIClk cycle time 2 - 65024 system clocks
S2 tclk_high SSIClk high time - 0.5 - t clk_per
S3 tclk_low SSIClk low time - 0.5 - t clk_per
S4 tclkrf SSIClk rise/fall timea - 6 10 ns
S5 tDMd Data from master valid delay time 0 - 1 system clocks
S6 tDMs Data from master setup time 1 - - system clocks
S7 tDMh Data from master hold time 2 - - system clocks
S8 tDSs Data from slave setup time 1 - - system clocks
S9 tDSh Data from slave hold time 2 - - system clocks
a. Note that the delays shown are using 8-mA drive strength.
Figure 22-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement
SSIClk
SSIFss
SSITx
SSIRx MSB LSB
S2
S3
S1
S4
4 to 16 bits
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Figure 22-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer
0
SSIClk
SSIFss
SSITx
SSIRx
MSB LSB
MSB LSB
S2
S3
S1
8-bit control
4 to 16 bits output data
Figure 22-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1
SSIClk
(SPO=1)
SSITx
(master)
SSIRx
(slave) LSB
SSIClk
(SPO=0)
S2
S1
S4
SSIFss
LSB
S3
MSB
S5
S6 S7
S8 S9
MSB
22.2.10 Inter-Integrated Circuit (I2C) Interface
Table 22-21. I2C Characteristics
Parameter Parameter Parameter Name Min Nom Max Unit
No.
I1a tSCH Start condition hold time 36 - - system clocks
I2a tLP Clock Low period 36 - - system clocks
(see note ns
b)
I2CSCL/I2CSDA rise time (VIL =0.5 V - -
to V IH =2.4 V)
I3b tSRT
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Table 22-21. I2C Characteristics (continued)
Parameter Parameter Parameter Name Min Nom Max Unit
No.
I4a tDH Data hold time 2 - - system clocks
I2CSCL/I2CSDA fall time (VIH =2.4 V - 9 10 ns
to V IL =0.5 V)
I5c tSFT
I6a tHT Clock High time 24 - - system clocks
I7a tDS Data setup time 18 - - system clocks
Start condition setup time (for repeated 36 - - system clocks
start condition only)
I8a tSCSR
I9a tSCS Stop condition setup time 24 - - system clocks
a. Values depend on the value programmed into the TPR bit in the I2C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
Figure 22-15. I2C Timing
I2CSCL
I2CSDA
I1
I2
I4
I6
I7 I8
I5
I3 I9
22.2.11 Analog Comparator
Table 22-22. Analog Comparator Characteristics
Parameter Parameter Name Min Nom Max Unit
VOS Input offset voltage - ±10 ±25 mV
VCM Input common mode voltage range 0 - VDD-1.5 V
CMRR Common mode rejection ratio 50 - - dB
TRT Response time - - 1 μs
TMC Comparator mode change to Output Valid - - 10 μs
Table 22-23. Analog Comparator Voltage Reference Characteristics
Parameter Parameter Name Min Nom Max Unit
RHR Resolution high range - VDD/31 - LSB
RLR Resolution low range - VDD/23 - LSB
AHR Absolute accuracy high range - - ±1/2 LSB
ALR Absolute accuracy low range - - ±1/4 LSB
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A Serial Flash Loader
A.1 Serial Flash Loader
The Stellaris® serial flash loader is a preprogrammed flash-resident utility used to download code
to the flash memory of a device without the use of a debug interface. The serial flash loader uses
a simple packet interface to provide synchronous communication with the device. The flash loader
runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used.
The two serial interfaces that can be used are the UART0 and SSI0 interfaces. For simplicity, both
the data format and communication protocol are identical for both serial interfaces.
A.2 Interfaces
Once communication with the flash loader is established via one of the serial interfaces, that interface
is used until the flash loader is reset or new code takes over. For example, once you start
communicating using the SSI port, communications with the flash loader via the UART are disabled
until the device is reset.
A.2.1 UART
The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial
format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is
automatically detected by the flash loader and can be any valid baud rate supported by the host
and the device. The auto detection sequence requires that the baud rate should be no more than
1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the
same as the hardware limitation for the maximum baud rate for any UART on a Stellaris device
which is calculated as follows:
Max Baud Rate = System Clock Frequency / 16
In order to determine the baud rate, the serial flash loader needs to determine the relationship
between its own crystal frequency and the baud rate. This is enough information for the flash loader
to configure its UART to the same baud rate as the host. This automatic baud-rate detection allows
the host to use any valid baud rate that it wants to communicate with the device.
The method used to perform this automatic synchronization relies on the host sending the flash
loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can
use to calculate the ratios needed to program the UART to match the host’s baud rate. After the
host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader
returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received
after at least twice the time required to transfer the two bytes, the host can resend another pattern
of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader acknowledges that it has
received a synchronization pattern correctly. For example, the time to wait for data back from the
flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate
of 115200, this time is 2*(20/115200) or 0.35 ms.
A.2.2 SSI
The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications,
with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See “Frame
Formats” on page 463 in the SSI chapter for more information on formats for this transfer protocol.
Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI
clock can run. This allows the SSI clock to be at most 1/12 the crystal frequency of the board running
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the flash loader. Since the host device is the master, the SSI on the flash loader device does not
need to determine the clock as it is provided directly by the host.
A.3 Packet Handling
All communications, with the exception of the UART auto-baud, are done via defined packets that
are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same
format for receiving and sending packets, including the method used to acknowledge successful or
unsuccessful reception of a packet.
A.3.1 Packet Format
All packets sent and received from the device use the following byte-packed format.
struct
{
unsigned char ucSize;
unsigned char ucCheckSum;
unsigned char Data[];
};
ucSize The first byte received holds the total size of the transfer including
the size and checksum bytes.
ucChecksum This holds a simple checksum of the bytes in the data buffer only.
The algorithm is Data[0]+Data[1]+…+ Data[ucSize-3].
Data This is the raw data intended for the device, which is formatted in
some form of command interface. There should be ucSize–2
bytes of data provided in this buffer to or from the device.
A.3.2 Sending Packets
The actual bytes of the packet can be sent individually or all at once; the only limitation is that
commands that cause flash memory access should limit the download sizes to prevent losing bytes
during flash programming. This limitation is discussed further in the section that describes the serial
flash loader command, COMMAND_SEND_DATA (see “COMMAND_SEND_DATA
(0x24)” on page 696).
Once the packet has been formatted correctly by the host, it should be sent out over the UART or
SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned
from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from
the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This
does not indicate that the actual contents of the command issued in the data portion of the packet
were valid, just that the packet was received correctly.
A.3.3 Receiving Packets
The flash loader sends a packet of data in the same format that it receives a packet. The flash loader
may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte
is the size of the packet followed by a checksum byte, and finally followed by the data itself. There
is no break in the data after the first non-zero byte is sent from the flash loader. Once the device
communicating with the flash loader receives all the bytes, it must either ACK or NAK the packet to
indicate that the transmission was successful. The appropriate response after sending a NAK to
the flash loader is to resend the command that failed and request the data again. If needed, the
host may send leading zeros before sending down the ACK/NAK signal to the flash loader, as the
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flash loader only accepts the first non-zero data as a valid response. This zero padding is needed
by the SSI interface in order to receive data to or from the flash loader.
A.4 Commands
The next section defines the list of commands that can be sent to the flash loader. The first byte of
the data should always be one of the defined commands, followed by data or parameters as
determined by the command that is sent.
A.4.1 COMMAND_PING (0X20)
This command simply accepts the command and sets the global status to success. The format of
the packet is as follows:
Byte[0] = 0x03;
Byte[1] = checksum(Byte[2]);
Byte[2] = COMMAND_PING;
The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one
byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status,
the receipt of an ACK can be interpreted as a successful ping to the flash loader.
A.4.2 COMMAND_GET_STATUS (0x23)
This command returns the status of the last command that was issued. Typically, this command
should be sent after every command to ensure that the previous command was successful or to
properly respond to a failure. The command requires one byte in the data of the packet and should
be followed by reading a packet with one byte of data that contains a status code. The last step is
to ACK or NAK the received data so the flash loader knows that the data has been read.
Byte[0] = 0x03
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_GET_STATUS
A.4.3 COMMAND_DOWNLOAD (0x21)
This command is sent to the flash loader to indicate where to store data and how many bytes will
be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit
values that are both transferred MSB first. The first 32-bit value is the address to start programming
data into, while the second is the 32-bit size of the data that will be sent. This command also triggers
an erase of the full area to be programmed so this command takes longer than other commands.
This results in a longer time to receive the ACK/NAK back from the board. This command should
be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size
are valid for the device running the flash loader.
The format of the packet to send this command is a follows:
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_DOWNLOAD
Byte[3] = Program Address [31:24]
Byte[4] = Program Address [23:16]
Byte[5] = Program Address [15:8]
Byte[6] = Program Address [7:0]
Byte[7] = Program Size [31:24]
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Byte[8] = Program Size [23:16]
Byte[9] = Program Size [15:8]
Byte[10] = Program Size [7:0]
A.4.4 COMMAND_SEND_DATA (0x24)
This command should only follow a COMMAND_DOWNLOAD command or another
COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands
automatically increment address and continue programming from the previous location. The caller
should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program
successfully and not overflow input buffers of the serial interfaces. The command terminates
programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been
received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to
ensure that the data was successfully programmed into the flash. If the flash loader sends a NAK
to this command, the flash loader does not increment the current address to allow retransmission
of the previous data.
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_SEND_DATA
Byte[3] = Data[0]
Byte[4] = Data[1]
Byte[5] = Data[2]
Byte[6] = Data[3]
Byte[7] = Data[4]
Byte[8] = Data[5]
Byte[9] = Data[6]
Byte[10] = Data[7]
A.4.5 COMMAND_RUN (0x22)
This command is used to tell the flash loader to execute from the address passed as the parameter
in this command. This command consists of a single 32-bit value that is interpreted as the address
to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK
signal back to the host device before actually executing the code at the given address. This allows
the host to know that the command was received successfully and the code is now running.
Byte[0] = 7
Byte[1] = checksum(Bytes[2:6])
Byte[2] = COMMAND_RUN
Byte[3] = Execute Address[31:24]
Byte[4] = Execute Address[23:16]
Byte[5] = Execute Address[15:8]
Byte[6] = Execute Address[7:0]
A.4.6 COMMAND_RESET (0x25)
This command is used to tell the flash loader device to reset. This is useful when downloading a
new image that overwrote the flash loader and wants to start from a full reset. Unlike the
COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set
up for the new code. It can also be used to reset the flash loader if a critical error occurs and the
host device wants to restart communication with the flash loader.
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Byte[0] = 3
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_RESET
The flash loader responds with an ACK signal back to the host device before actually executing the
software reset to the device running the flash loader. This allows the host to know that the command
was received successfully and the part will be reset.
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B Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
The Cortex-M3 Processor
R0, type R/W, , reset - (see page 59)
DATA
DATA
R1, type R/W, , reset - (see page 59)
DATA
DATA
R2, type R/W, , reset - (see page 59)
DATA
DATA
R3, type R/W, , reset - (see page 59)
DATA
DATA
R4, type R/W, , reset - (see page 59)
DATA
DATA
R5, type R/W, , reset - (see page 59)
DATA
DATA
R6, type R/W, , reset - (see page 59)
DATA
DATA
R7, type R/W, , reset - (see page 59)
DATA
DATA
R8, type R/W, , reset - (see page 59)
DATA
DATA
R9, type R/W, , reset - (see page 59)
DATA
DATA
R10, type R/W, , reset - (see page 59)
DATA
DATA
R11, type R/W, , reset - (see page 59)
DATA
DATA
R12, type R/W, , reset - (see page 59)
DATA
DATA
SP, type R/W, , reset - (see page 60)
SP
SP
LR, type R/W, , reset 0xFFFF.FFFF (see page 61)
LINK
LINK
PC, type R/W, , reset - (see page 62)
PC
PC
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Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSR, type R/W, , reset 0x0100.0000 (see page 63)
N Z C V Q ICI / IT THUMB
ICI / IT ISRNUM
PRIMASK, type R/W, , reset 0x0000.0000 (see page 67)
PRIMASK
FAULTMASK, type R/W, , reset 0x0000.0000 (see page 68)
FAULTMASK
BASEPRI, type R/W, , reset 0x0000.0000 (see page 69)
BASEPRI
CONTROL, type R/W, , reset 0x0000.0000 (see page 70)
ASP TMPL
Cortex-M3 Peripherals
System Timer (SysTick) Registers
Base 0xE000.E000
STCTRL, type R/W, offset 0x010, reset 0x0000.0000
COUNT
CLK_SRC INTEN ENABLE
STRELOAD, type R/W, offset 0x014, reset 0x0000.0000
RELOAD
RELOAD
STCURRENT, type R/WC, offset 0x018, reset 0x0000.0000
CURRENT
CURRENT
Cortex-M3 Peripherals
Nested Vectored Interrupt Controller (NVIC) Registers
Base 0xE000.E000
EN0, type R/W, offset 0x100, reset 0x0000.0000
INT
INT
EN1, type R/W, offset 0x104, reset 0x0000.0000
INT
DIS0, type R/W, offset 0x180, reset 0x0000.0000
INT
INT
DIS1, type R/W, offset 0x184, reset 0x0000.0000
INT
PEND0, type R/W, offset 0x200, reset 0x0000.0000
INT
INT
PEND1, type R/W, offset 0x204, reset 0x0000.0000
INT
UNPEND0, type R/W, offset 0x280, reset 0x0000.0000
INT
INT
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNPEND1, type R/W, offset 0x284, reset 0x0000.0000
INT
ACTIVE0, type RO, offset 0x300, reset 0x0000.0000
INT
INT
ACTIVE1, type RO, offset 0x304, reset 0x0000.0000
INT
PRI0, type R/W, offset 0x400, reset 0x0000.0000
INTD INTC
INTB INTA
PRI1, type R/W, offset 0x404, reset 0x0000.0000
INTD INTC
INTB INTA
PRI2, type R/W, offset 0x408, reset 0x0000.0000
INTD INTC
INTB INTA
PRI3, type R/W, offset 0x40C, reset 0x0000.0000
INTD INTC
INTB INTA
PRI4, type R/W, offset 0x410, reset 0x0000.0000
INTD INTC
INTB INTA
PRI5, type R/W, offset 0x414, reset 0x0000.0000
INTD INTC
INTB INTA
PRI6, type R/W, offset 0x418, reset 0x0000.0000
INTD INTC
INTB INTA
PRI7, type R/W, offset 0x41C, reset 0x0000.0000
INTD INTC
INTB INTA
PRI8, type R/W, offset 0x420, reset 0x0000.0000
INTD INTC
INTB INTA
PRI9, type R/W, offset 0x424, reset 0x0000.0000
INTD INTC
INTB INTA
PRI10, type R/W, offset 0x428, reset 0x0000.0000
INTD INTC
INTB INTA
SWTRIG, type WO, offset 0xF00, reset 0x0000.0000
INTID
Cortex-M3 Peripherals
System Control Block (SCB) Registers
Base 0xE000.E000
CPUID, type RO, offset 0xD00, reset 0x411F.C231
IMP VAR CON
PARTNO REV
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Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTCTRL, type R/W, offset 0xD04, reset 0x0000.0000
NMISET PENDSV UNPENDSV PENDSTSET PENDSTCLR ISRPRE ISRPEND VECPEND
VECPEND RETBASE VECACT
VTABLE, type R/W, offset 0xD08, reset 0x0000.0000
BASE OFFSET
OFFSET
APINT, type R/W, offset 0xD0C, reset 0xFA05.0000
VECTKEY
ENDIANESS PRIGROUP SYSRESREQ VECTCLRACT VECTRESET
SYSCTRL, type R/W, offset 0xD10, reset 0x0000.0000
SEVONPEND SLEEPDEEP SLEEPEXIT
CFGCTRL, type R/W, offset 0xD14, reset 0x0000.0000
STKALIGN BFHFNMIGN DIV0 UNALIGNED MAINPEND BASETHR
SYSPRI1, type R/W, offset 0xD18, reset 0x0000.0000
USAGE
BUS MEM
SYSPRI2, type R/W, offset 0xD1C, reset 0x0000.0000
SVC
SYSPRI3, type R/W, offset 0xD20, reset 0x0000.0000
TICK PENDSV
DEBUG
SYSHNDCTRL, type R/W, offset 0xD24, reset 0x0000.0000
USAGE BUS MEM
SVC BUSP MEMP USAGEP TICK PNDSV MON SVCA USGA BUSA MEMA
FAULTSTAT, type R/W1C, offset 0xD28, reset 0x0000.0000
DIV0 UNALIGN NOCP INVPC INVSTAT UNDEF
BFARV BSTKE BUSTKE IMPRE PRECISE IBUS MMARV MSTKE MUSTKE DERR IERR
HFAULTSTAT, type R/W1C, offset 0xD2C, reset 0x0000.0000
DBG FORCED
VECT
MMADDR, type R/W, offset 0xD34, reset -
ADDR
ADDR
FAULTADDR, type R/W, offset 0xD38, reset -
ADDR
ADDR
Cortex-M3 Peripherals
Memory Protection Unit (MPU) Registers
Base 0xE000.E000
MPUTYPE, type RO, offset 0xD90, reset 0x0000.0800
IREGION
DREGION SEPARATE
MPUCTRL, type R/W, offset 0xD94, reset 0x0000.0000
PRIVDEFEN HFNMIENA ENABLE
MPUNUMBER, type R/W, offset 0xD98, reset 0x0000.0000
NUMBER
January 08, 2011 701
Texas Instruments-Production Data
Stellaris® LM3S2965 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPUBASE, type R/W, offset 0xD9C, reset 0x0000.0000
ADDR
ADDR VALID REGION
MPUBASE1, type R/W, offset 0xDA4, reset 0x0000.0000
ADDR
ADDR VALID REGION
MPUBASE2, type R/W, offset 0xDAC, reset 0x0000.0000
ADDR
ADDR VALID REGION
MPUBASE3, type R/W, offset 0xDB4, reset 0x0000.0000
ADDR
ADDR VALID REGION
MPUATTR, type R/W, offset 0xDA0, reset 0x0000.0000
XN AP TEX S C B
SRD SIZE ENABLE
MPUATTR1, type R/W, offset 0xDA8, reset 0x0000.0000
XN AP TEX S C B
SRD SIZE ENABLE
MPUATTR2, type R/W, offset 0xDB0, reset 0x0000.0000
XN AP TEX S C B
SRD SIZE ENABLE
MPUATTR3, type R/W, offset 0xDB8, reset 0x0000.0000
XN AP TEX S C B
SRD SIZE ENABLE
System Control
Base 0x400F.E000
DID0, type RO, offset 0x000, reset - (see page 184)
VER CLASS
MAJOR MINOR
PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD (see page 186)
BORIOR
LDOPCTL, type R/W, offset 0x034, reset 0x0000.0000 (see page 187)
VADJ
RIS, type RO, offset 0x050, reset 0x0000.0000 (see page 188)
PLLLRIS BORRIS
IMC, type R/W, offset 0x054, reset 0x0000.0000 (see page 189)
PLLLIM BORIM
MISC, type R/W1C, offset 0x058, reset 0x0000.0000 (see page 190)
PLLLMIS BORMIS
RESC, type R/W, offset 0x05C, reset - (see page 191)
SW WDT BOR POR EXT
RCC, type R/W, offset 0x060, reset 0x078E.3AD1 (see page 192)
ACG SYSDIV USESYSDIV USEPWMDIV PWMDIV
PWRDN BYPASS XTAL OSCSRC IOSCDIS MOSCDIS
PLLCFG, type RO, offset 0x064, reset - (see page 196)
F R
702 January 08, 2011
Texas Instruments-Production Data
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCC2, type R/W, offset 0x070, reset 0x0780.2810 (see page 197)
USERCC2 SYSDIV2
PWRDN2 BYPASS2 OSCSRC2
DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000 (see page 199)
DSDIVORIDE
DSOSCSRC
DID1, type RO, offset 0x004, reset - (see page 200)
VER FAM PARTNO
PINCOUNT TEMP PKG ROHS QUAL
DC0, type RO, offset 0x008, reset 0x00FF.007F (see page 202)
SRAMSZ
FLASHSZ
DC1, type RO, offset 0x010, reset 0x0311.33FF (see page 203)
CAN1 CAN0 PWM ADC
MINSYSDIV MAXADCSPD MPU HIB TEMPSNS PLL WDT SWO SWD JTAG
DC2, type RO, offset 0x014, reset 0x070F.5337 (see page 205)
COMP2 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0
I2C1 I2C0 QEI1 QEI0 SSI1 SSI0 UART2 UART1 UART0
DC3, type RO, offset 0x018, reset 0xBF0F.B7FF (see page 207)
32KHZ CCP5 CCP4 CCP3 CCP2 CCP1 CCP0 ADC3 ADC2 ADC1 ADC0
PWMFAULT C2PLUS C2MINUS C1PLUS C1MINUS C0O C0PLUS C0MINUS PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
DC4, type RO, offset 0x01C, reset 0x0000.00FF (see page 209)
GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
RCGC0, type R/W, offset 0x100, reset 0x00000040 (see page 210)
CAN1 CAN0 PWM ADC
MAXADCSPD HIB WDT
SCGC0, type R/W, offset 0x110, reset 0x00000040 (see page 212)
CAN1 CAN0 PWM ADC
MAXADCSPD HIB WDT
DCGC0, type R/W, offset 0x120, reset 0x00000040 (see page 214)
CAN1 CAN0 PWM ADC
HIB WDT
RCGC1, type R/W, offset 0x104, reset 0x00000000 (see page 216)
COMP2 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0
I2C1 I2C0 QEI1 QEI0 SSI1 SSI0 UART2 UART1 UART0
SCGC1, type R/W, offset 0x114, reset 0x00000000 (see page 219)
COMP2 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0
I2C1 I2C0 QEI1 QEI0 SSI1 SSI0 UART2 UART1 UART0
DCGC1, type R/W, offset 0x124, reset 0x00000000 (see page 222)
COMP2 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0
I2C1 I2C0 QEI1 QEI0 SSI1 SSI0 UART2 UART1 UART0
RCGC2, type R/W, offset 0x108, reset 0x00000000 (see page 225)
GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
SCGC2, type R/W, offset 0x118, reset 0x00000000 (see page 227)
GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
DCGC2, type R/W, offset 0x128, reset 0x00000000 (see page 229)
GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
January 08, 2011 703
Texas Instruments-Production Data
Stellaris® LM3S2965 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRCR0, type R/W, offset 0x040, reset 0x00000000 (see page 231)
CAN1 CAN0 PWM ADC
HIB WDT
SRCR1, type R/W, offset 0x044, reset 0x00000000 (see page 233)
COMP2 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0
I2C1 I2C0 QEI1 QEI0 SSI1 SSI0 UART2 UART1 UART0
SRCR2, type R/W, offset 0x048, reset 0x00000000 (see page 235)
GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Hibernation Module
Base 0x400F.C000
HIBRTCC, type RO, offset 0x000, reset 0x0000.0000 (see page 244)
RTCC
RTCC
HIBRTCM0, type R/W, offset 0x004, reset 0xFFFF.FFFF (see page 245)
RTCM0
RTCM0
HIBRTCM1, type R/W, offset 0x008, reset 0xFFFF.FFFF (see page 246)
RTCM1
RTCM1
HIBRTCLD, type R/W, offset 0x00C, reset 0xFFFF.FFFF (see page 247)
RTCLD
RTCLD
HIBCTL, type R/W, offset 0x010, reset 0x8000.0000 (see page 248)
VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBREQ RTCEN
HIBIM, type R/W, offset 0x014, reset 0x0000.0000 (see page 250)
EXTW LOWBAT RTCALT1 RTCALT0
HIBRIS, type RO, offset 0x018, reset 0x0000.0000 (see page 251)
EXTW LOWBAT RTCALT1 RTCALT0
HIBMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 252)
EXTW LOWBAT RTCALT1 RTCALT0
HIBIC, type R/W1C, offset 0x020, reset 0x0000.0000 (see page 253)
EXTW LOWBAT RTCALT1 RTCALT0
HIBRTCT, type R/W, offset 0x024, reset 0x0000.7FFF (see page 254)
TRIM
HIBDATA, type R/W, offset 0x030-0x12C, reset - (see page 255)
RTD
RTD
Internal Memory
Flash Memory Control Registers (Flash Control Offset)
Base 0x400F.D000
FMA, type R/W, offset 0x000, reset 0x0000.0000
OFFSET
OFFSET
704 January 08, 2011
Texas Instruments-Production Data
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMD, type R/W, offset 0x004, reset 0x0000.0000
DATA
DATA
FMC, type R/W, offset 0x008, reset 0x0000.0000
WRKEY
COMT MERASE ERASE WRITE
FCRIS, type RO, offset 0x00C, reset 0x0000.0000
PRIS ARIS
FCIM, type R/W, offset 0x010, reset 0x0000.0000
PMASK AMASK
FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000
PMISC AMISC
Internal Memory
Flash Memory Protection Registers (System Control Offset)
Base 0x400F.E000
USECRL, type R/W, offset 0x140, reset 0x31
USEC
FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
USER_DBG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE
NW DATA
DATA DBG1 DBG0
USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF
NW DATA
DATA
USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF
NW DATA
DATA
FMPRE1, type R/W, offset 0x204, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE2, type R/W, offset 0x208, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE3, type R/W, offset 0x20C, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE2, type R/W, offset 0x408, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
January 08, 2011 705
Texas Instruments-Production Data
Stellaris® LM3S2965 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMPPE3, type R/W, offset 0x40C, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
General-Purpose Input/Outputs (GPIOs)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
GPIODATA, type R/W, offset 0x000, reset 0x0000.0000 (see page 290)
DATA
GPIODIR, type R/W, offset 0x400, reset 0x0000.0000 (see page 291)
DIR
GPIOIS, type R/W, offset 0x404, reset 0x0000.0000 (see page 292)
IS
GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000 (see page 293)
IBE
GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000 (see page 294)
IEV
GPIOIM, type R/W, offset 0x410, reset 0x0000.0000 (see page 295)
IME
GPIORIS, type RO, offset 0x414, reset 0x0000.0000 (see page 296)
RIS
GPIOMIS, type RO, offset 0x418, reset 0x0000.0000 (see page 297)
MIS
GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000 (see page 298)
IC
GPIOAFSEL, type R/W, offset 0x420, reset - (see page 299)
AFSEL
GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF (see page 301)
DRV2
GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000 (see page 302)
DRV4
GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000 (see page 303)
DRV8
GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000 (see page 304)
ODE
706 January 08, 2011
Texas Instruments-Production Data
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOPUR, type R/W, offset 0x510, reset - (see page 305)
PUE
GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000 (see page 306)
PDE
GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000 (see page 307)
SRL
GPIODEN, type R/W, offset 0x51C, reset - (see page 308)
DEN
GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001 (see page 309)
LOCK
LOCK
GPIOCR, type -, offset 0x524, reset - (see page 310)
CR
GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 312)
PID4
GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 313)
PID5
GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 314)
PID6
GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 315)
PID7
GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061 (see page 316)
PID0
GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 317)
PID1
GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 318)
PID2
GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 319)
PID3
GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 320)
CID0
GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 321)
CID1
GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 322)
CID2
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Texas Instruments-Production Data
Stellaris® LM3S2965 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 323)
CID3
General-Purpose Timers
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000 (see page 336)
GPTMCFG
GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000 (see page 337)
TAAMS TACMR TAMR
GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000 (see page 339)
TBAMS TBCMR TBMR
GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000 (see page 341)
TBPWML TBOTE TBEVENT TBSTALL TBEN TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN
GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000 (see page 344)
CBEIM CBMIM TBTOIM RTCIM CAEIM CAMIM TATOIM
GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 346)
CBERIS CBMRIS TBTORIS RTCRIS CAERIS CAMRIS TATORIS
GPTMMIS, type RO, offset 0x020, reset 0x0000.0000 (see page 347)
CBEMIS CBMMIS TBTOMIS RTCMIS CAEMIS CAMMIS TATOMIS
GPTMICR, type W1C, offset 0x024, reset 0x0000.0000 (see page 348)
CBECINT CBMCINT TBTOCINT RTCCINT CAECINT CAMCINT TATOCINT
GPTMTAILR, type R/W, offset 0x028, reset 0xFFFF.FFFF (see page 350)
TAILRH
TAILRL
GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF (see page 351)
TBILRL
GPTMTAMATCHR, type R/W, offset 0x030, reset 0xFFFF.FFFF (see page 352)
TAMRH
TAMRL
GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF (see page 353)
TBMRL
GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000 (see page 354)
TAPSR
GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000 (see page 355)
TBPSR
GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000 (see page 356)
TAPSMR
708 January 08, 2011
Texas Instruments-Production Data
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000 (see page 357)
TBPSMR
GPTMTAR, type RO, offset 0x048, reset 0xFFFF.FFFF (see page 358)
TARH
TARL
GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF (see page 359)
TBRL
Watchdog Timer
Base 0x4000.0000
WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF (see page 364)
WDTLoad
WDTLoad
WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF (see page 365)
WDTValue
WDTValue
WDTCTL, type R/W, offset 0x008, reset 0x0000.0000 (see page 366)
RESEN INTEN
WDTICR, type WO, offset 0x00C, reset - (see page 367)
WDTIntClr
WDTIntClr
WDTRIS, type RO, offset 0x010, reset 0x0000.0000 (see page 368)
WDTRIS
WDTMIS, type RO, offset 0x014, reset 0x0000.0000 (see page 369)
WDTMIS
WDTTEST, type R/W, offset 0x418, reset 0x0000.0000 (see page 370)
STALL
WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000 (see page 371)
WDTLock
WDTLock
WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 372)
PID4
WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 373)
PID5
WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 374)
PID6
WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 375)
PID7
WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005 (see page 376)
PID0
WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018 (see page 377)
PID1
January 08, 2011 709
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 378)
PID2
WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 379)
PID3
WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 380)
CID0
WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 381)
CID1
WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 382)
CID2
WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 383)
CID3
Analog-to-Digital Converter (ADC)
Base 0x4003.8000
ADCACTSS, type R/W, offset 0x000, reset 0x0000.0000 (see page 393)
ASEN3 ASEN2 ASEN1 ASEN0
ADCRIS, type RO, offset 0x004, reset 0x0000.0000 (see page 394)
INR3 INR2 INR1 INR0
ADCIM, type R/W, offset 0x008, reset 0x0000.0000 (see page 395)
MASK3 MASK2 MASK1 MASK0
ADCISC, type R/W1C, offset 0x00C, reset 0x0000.0000 (see page 396)
IN3 IN2 IN1 IN0
ADCOSTAT, type R/W1C, offset 0x010, reset 0x0000.0000 (see page 397)
OV3 OV2 OV1 OV0
ADCEMUX, type R/W, offset 0x014, reset 0x0000.0000 (see page 398)
EM3 EM2 EM1 EM0
ADCUSTAT, type R/W1C, offset 0x018, reset 0x0000.0000 (see page 402)
UV3 UV2 UV1 UV0
ADCSSPRI, type R/W, offset 0x020, reset 0x0000.3210 (see page 403)
SS3 SS2 SS1 SS0
ADCPSSI, type WO, offset 0x028, reset - (see page 405)
SS3 SS2 SS1 SS0
ADCSAC, type R/W, offset 0x030, reset 0x0000.0000 (see page 406)
AVG
ADCSSMUX0, type R/W, offset 0x040, reset 0x0000.0000 (see page 407)
MUX7 MUX6 MUX5 MUX4
MUX3 MUX2 MUX1 MUX0
710 January 08, 2011
Texas Instruments-Production Data
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCSSCTL0, type R/W, offset 0x044, reset 0x0000.0000 (see page 409)
TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
ADCSSFIFO0, type RO, offset 0x048, reset - (see page 412)
DATA
ADCSSFIFO1, type RO, offset 0x068, reset - (see page 412)
DATA
ADCSSFIFO2, type RO, offset 0x088, reset - (see page 412)
DATA
ADCSSFIFO3, type RO, offset 0x0A8, reset - (see page 412)
DATA
ADCSSFSTAT0, type RO, offset 0x04C, reset 0x0000.0100 (see page 413)
FULL EMPTY HPTR TPTR
ADCSSFSTAT1, type RO, offset 0x06C, reset 0x0000.0100 (see page 413)
FULL EMPTY HPTR TPTR
ADCSSFSTAT2, type RO, offset 0x08C, reset 0x0000.0100 (see page 413)
FULL EMPTY HPTR TPTR
ADCSSFSTAT3, type RO, offset 0x0AC, reset 0x0000.0100 (see page 413)
FULL EMPTY HPTR TPTR
ADCSSMUX1, type R/W, offset 0x060, reset 0x0000.0000 (see page 414)
MUX3 MUX2 MUX1 MUX0
ADCSSMUX2, type R/W, offset 0x080, reset 0x0000.0000 (see page 414)
MUX3 MUX2 MUX1 MUX0
ADCSSCTL1, type R/W, offset 0x064, reset 0x0000.0000 (see page 415)
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
ADCSSCTL2, type R/W, offset 0x084, reset 0x0000.0000 (see page 415)
TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0
ADCSSMUX3, type R/W, offset 0x0A0, reset 0x0000.0000 (see page 417)
MUX0
ADCSSCTL3, type R/W, offset 0x0A4, reset 0x0000.0002 (see page 418)
TS0 IE0 END0 D0
ADCTMLB, type R/W, offset 0x100, reset 0x0000.0000 (see page 419)
LB
January 08, 2011 711
Texas Instruments-Production Data
Stellaris® LM3S2965 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Universal Asynchronous Receivers/Transmitters (UARTs)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UARTDR, type R/W, offset 0x000, reset 0x0000.0000 (see page 428)
OE BE PE FE DATA
UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000 (Reads) (see page 430)
OE BE PE FE
UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000 (Writes) (see page 430)
DATA
UARTFR, type RO, offset 0x018, reset 0x0000.0090 (see page 432)
TXFE RXFF TXFF RXFE BUSY
UARTILPR, type R/W, offset 0x020, reset 0x0000.0000 (see page 434)
ILPDVSR
UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000 (see page 435)
DIVINT
UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000 (see page 436)
DIVFRAC
UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000 (see page 437)
SPS WLEN FEN STP2 EPS PEN BRK
UARTCTL, type R/W, offset 0x030, reset 0x0000.0300 (see page 439)
RXE TXE LBE SIRLP SIREN UARTEN
UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012 (see page 441)
RXIFLSEL TXIFLSEL
UARTIM, type R/W, offset 0x038, reset 0x0000.0000 (see page 443)
OEIM BEIM PEIM FEIM RTIM TXIM RXIM
UARTRIS, type RO, offset 0x03C, reset 0x0000.000F (see page 445)
OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS
UARTMIS, type RO, offset 0x040, reset 0x0000.0000 (see page 446)
OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS
UARTICR, type W1C, offset 0x044, reset 0x0000.0000 (see page 447)
OEIC BEIC PEIC FEIC RTIC TXIC RXIC
UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 449)
PID4
UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 450)
PID5
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Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 451)
PID6
UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 452)
PID7
UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011 (see page 453)
PID0
UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 454)
PID1
UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 455)
PID2
UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 456)
PID3
UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 457)
CID0
UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 458)
CID1
UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 459)
CID2
UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 460)
CID3
Synchronous Serial Interface (SSI)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSICR0, type R/W, offset 0x000, reset 0x0000.0000 (see page 473)
SCR SPH SPO FRF DSS
SSICR1, type R/W, offset 0x004, reset 0x0000.0000 (see page 475)
SOD MS SSE LBM
SSIDR, type R/W, offset 0x008, reset 0x0000.0000 (see page 477)
DATA
SSISR, type RO, offset 0x00C, reset 0x0000.0003 (see page 478)
BSY RFF RNE TNF TFE
SSICPSR, type R/W, offset 0x010, reset 0x0000.0000 (see page 480)
CPSDVSR
SSIIM, type R/W, offset 0x014, reset 0x0000.0000 (see page 481)
TXIM RXIM RTIM RORIM
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSIRIS, type RO, offset 0x018, reset 0x0000.0008 (see page 483)
TXRIS RXRIS RTRIS RORRIS
SSIMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 484)
TXMIS RXMIS RTMIS RORMIS
SSIICR, type W1C, offset 0x020, reset 0x0000.0000 (see page 485)
RTIC RORIC
SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 486)
PID4
SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 487)
PID5
SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 488)
PID6
SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 489)
PID7
SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022 (see page 490)
PID0
SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 491)
PID1
SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 492)
PID2
SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 493)
PID3
SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 494)
CID0
SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 495)
CID1
SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 496)
CID2
SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 497)
CID3
Inter-Integrated Circuit (I2C) Interface
I2C Master
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2CMSA, type R/W, offset 0x000, reset 0x0000.0000
SA R/S
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Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2CMCS, type RO, offset 0x004, reset 0x0000.0000 (Reads)
BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY
I2CMCS, type WO, offset 0x004, reset 0x0000.0000 (Writes)
ACK STOP START RUN
I2CMDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001
TPR
I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000
IM
I2CMRIS, type RO, offset 0x014, reset 0x0000.0000
RIS
I2CMMIS, type RO, offset 0x018, reset 0x0000.0000
MIS
I2CMICR, type WO, offset 0x01C, reset 0x0000.0000
IC
I2CMCR, type R/W, offset 0x020, reset 0x0000.0000
SFE MFE LPBK
Inter-Integrated Circuit (I2C) Interface
I2C Slave
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2CSOAR, type R/W, offset 0x800, reset 0x0000.0000
OAR
I2CSCSR, type RO, offset 0x804, reset 0x0000.0000 (Reads)
FBR TREQ RREQ
I2CSCSR, type WO, offset 0x804, reset 0x0000.0000 (Writes)
DA
I2CSDR, type R/W, offset 0x808, reset 0x0000.0000
DATA
I2CSIMR, type R/W, offset 0x80C, reset 0x0000.0000
DATAIM
I2CSRIS, type RO, offset 0x810, reset 0x0000.0000
DATARIS
I2CSMIS, type RO, offset 0x814, reset 0x0000.0000
DATAMIS
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2CSICR, type WO, offset 0x818, reset 0x0000.0000
DATAIC
Controller Area Network (CAN) Module
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CANCTL, type R/W, offset 0x000, reset 0x0000.0001 (see page 555)
TEST CCE DAR EIE SIE IE INIT
CANSTS, type R/W, offset 0x004, reset 0x0000.0000 (see page 557)
BOFF EWARN EPASS RXOK TXOK LEC
CANERR, type RO, offset 0x008, reset 0x0000.0000 (see page 559)
RP REC TEC
CANBIT, type R/W, offset 0x00C, reset 0x0000.2301 (see page 560)
TSEG2 TSEG1 SJW BRP
CANINT, type RO, offset 0x010, reset 0x0000.0000 (see page 561)
INTID
CANTST, type R/W, offset 0x014, reset 0x0000.0000 (see page 562)
RX TX LBACK SILENT BASIC
CANBRPE, type R/W, offset 0x018, reset 0x0000.0000 (see page 564)
BRPE
CANIF1CRQ, type R/W, offset 0x020, reset 0x0000.0001 (see page 565)
BUSY MNUM
CANIF2CRQ, type R/W, offset 0x080, reset 0x0000.0001 (see page 565)
BUSY MNUM
CANIF1CMSK, type R/W, offset 0x024, reset 0x0000.0000 (see page 566)
DATAA DATAB NEWDAT /
TXRQST
WRNRD MASK ARB CONTROL CLRINTPND
CANIF2CMSK, type R/W, offset 0x084, reset 0x0000.0000 (see page 566)
DATAA DATAB NEWDAT /
TXRQST
WRNRD MASK ARB CONTROL CLRINTPND
CANIF1MSK1, type R/W, offset 0x028, reset 0x0000.FFFF (see page 568)
MSK
CANIF2MSK1, type R/W, offset 0x088, reset 0x0000.FFFF (see page 568)
MSK
CANIF1MSK2, type R/W, offset 0x02C, reset 0x0000.FFFF (see page 569)
MXTD MDIR MSK
CANIF2MSK2, type R/W, offset 0x08C, reset 0x0000.FFFF (see page 569)
MXTD MDIR MSK
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Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CANIF1ARB1, type R/W, offset 0x030, reset 0x0000.0000 (see page 570)
ID
CANIF2ARB1, type R/W, offset 0x090, reset 0x0000.0000 (see page 570)
ID
CANIF1ARB2, type R/W, offset 0x034, reset 0x0000.0000 (see page 571)
MSGVAL XTD DIR ID
CANIF2ARB2, type R/W, offset 0x094, reset 0x0000.0000 (see page 571)
MSGVAL XTD DIR ID
CANIF1MCTL, type R/W, offset 0x038, reset 0x0000.0000 (see page 572)
NEWDAT MSGLST INTPND UMASK TXIE RXIE RMTEN TXRQST EOB DLC
CANIF2MCTL, type R/W, offset 0x098, reset 0x0000.0000 (see page 572)
NEWDAT MSGLST INTPND UMASK TXIE RXIE RMTEN TXRQST EOB DLC
CANIF1DA1, type R/W, offset 0x03C, reset 0x0000.0000 (see page 574)
DATA
CANIF1DA2, type R/W, offset 0x040, reset 0x0000.0000 (see page 574)
DATA
CANIF1DB1, type R/W, offset 0x044, reset 0x0000.0000 (see page 574)
DATA
CANIF1DB2, type R/W, offset 0x048, reset 0x0000.0000 (see page 574)
DATA
CANIF2DA1, type R/W, offset 0x09C, reset 0x0000.0000 (see page 574)
DATA
CANIF2DA2, type R/W, offset 0x0A0, reset 0x0000.0000 (see page 574)
DATA
CANIF2DB1, type R/W, offset 0x0A4, reset 0x0000.0000 (see page 574)
DATA
CANIF2DB2, type R/W, offset 0x0A8, reset 0x0000.0000 (see page 574)
DATA
CANTXRQ1, type RO, offset 0x100, reset 0x0000.0000 (see page 575)
TXRQST
CANTXRQ2, type RO, offset 0x104, reset 0x0000.0000 (see page 575)
TXRQST
CANNWDA1, type RO, offset 0x120, reset 0x0000.0000 (see page 576)
NEWDAT
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Stellaris® LM3S2965 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CANNWDA2, type RO, offset 0x124, reset 0x0000.0000 (see page 576)
NEWDAT
CANMSG1INT, type RO, offset 0x140, reset 0x0000.0000 (see page 577)
INTPND
CANMSG2INT, type RO, offset 0x144, reset 0x0000.0000 (see page 577)
INTPND
CANMSG1VAL, type RO, offset 0x160, reset 0x0000.0000 (see page 578)
MSGVAL
CANMSG2VAL, type RO, offset 0x164, reset 0x0000.0000 (see page 578)
MSGVAL
Analog Comparators
Base 0x4003.C000
ACMIS, type R/W1C, offset 0x000, reset 0x0000.0000 (see page 584)
IN2 IN1 IN0
ACRIS, type RO, offset 0x004, reset 0x0000.0000 (see page 585)
IN2 IN1 IN0
ACINTEN, type R/W, offset 0x008, reset 0x0000.0000 (see page 586)
IN2 IN1 IN0
ACREFCTL, type R/W, offset 0x010, reset 0x0000.0000 (see page 587)
EN RNG VREF
ACSTAT0, type RO, offset 0x020, reset 0x0000.0000 (see page 588)
OVAL
ACSTAT1, type RO, offset 0x040, reset 0x0000.0000 (see page 588)
OVAL
ACSTAT2, type RO, offset 0x060, reset 0x0000.0000 (see page 588)
OVAL
ACCTL0, type R/W, offset 0x024, reset 0x0000.0000 (see page 589)
TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV
ACCTL1, type R/W, offset 0x044, reset 0x0000.0000 (see page 589)
TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV
ACCTL2, type R/W, offset 0x064, reset 0x0000.0000 (see page 589)
TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV
Pulse Width Modulator (PWM)
Base 0x4002.8000
PWMCTL, type R/W, offset 0x000, reset 0x0000.0000 (see page 600)
GlobalSync2 GlobalSync1 GlobalSync0
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Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWMSYNC, type R/W, offset 0x004, reset 0x0000.0000 (see page 601)
Sync2 Sync1 Sync0
PWMENABLE, type R/W, offset 0x008, reset 0x0000.0000 (see page 602)
PWM5En PWM4En PWM3En PWM2En PWM1En PWM0En
PWMINVERT, type R/W, offset 0x00C, reset 0x0000.0000 (see page 603)
PWM5Inv PWM4Inv PWM3Inv PWM2Inv PWM1Inv PWM0Inv
PWMFAULT, type R/W, offset 0x010, reset 0x0000.0000 (see page 604)
Fault5 Fault4 Fault3 Fault2 Fault1 Fault0
PWMINTEN, type R/W, offset 0x014, reset 0x0000.0000 (see page 605)
IntFault
IntPWM2 IntPWM1 IntPWM0
PWMRIS, type RO, offset 0x018, reset 0x0000.0000 (see page 606)
IntFault
IntPWM2 IntPWM1 IntPWM0
PWMISC, type R/W1C, offset 0x01C, reset 0x0000.0000 (see page 607)
IntFault
IntPWM2 IntPWM1 IntPWM0
PWMSTATUS, type RO, offset 0x020, reset 0x0000.0000 (see page 608)
Fault
PWM0CTL, type R/W, offset 0x040, reset 0x0000.0000 (see page 609)
CmpBUpd CmpAUpd LoadUpd Debug Mode Enable
PWM1CTL, type R/W, offset 0x080, reset 0x0000.0000 (see page 609)
CmpBUpd CmpAUpd LoadUpd Debug Mode Enable
PWM2CTL, type R/W, offset 0x0C0, reset 0x0000.0000 (see page 609)
CmpBUpd CmpAUpd LoadUpd Debug Mode Enable
PWM0INTEN, type R/W, offset 0x044, reset 0x0000.0000 (see page 611)
TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM1INTEN, type R/W, offset 0x084, reset 0x0000.0000 (see page 611)
TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM2INTEN, type R/W, offset 0x0C4, reset 0x0000.0000 (see page 611)
TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM0RIS, type RO, offset 0x048, reset 0x0000.0000 (see page 614)
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM1RIS, type RO, offset 0x088, reset 0x0000.0000 (see page 614)
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM2RIS, type RO, offset 0x0C8, reset 0x0000.0000 (see page 614)
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM0ISC, type R/W1C, offset 0x04C, reset 0x0000.0000 (see page 615)
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM1ISC, type R/W1C, offset 0x08C, reset 0x0000.0000 (see page 615)
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM2ISC, type R/W1C, offset 0x0CC, reset 0x0000.0000 (see page 615)
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM0LOAD, type R/W, offset 0x050, reset 0x0000.0000 (see page 616)
Load
PWM1LOAD, type R/W, offset 0x090, reset 0x0000.0000 (see page 616)
Load
PWM2LOAD, type R/W, offset 0x0D0, reset 0x0000.0000 (see page 616)
Load
PWM0COUNT, type RO, offset 0x054, reset 0x0000.0000 (see page 617)
Count
PWM1COUNT, type RO, offset 0x094, reset 0x0000.0000 (see page 617)
Count
PWM2COUNT, type RO, offset 0x0D4, reset 0x0000.0000 (see page 617)
Count
PWM0CMPA, type R/W, offset 0x058, reset 0x0000.0000 (see page 618)
CompA
PWM1CMPA, type R/W, offset 0x098, reset 0x0000.0000 (see page 618)
CompA
PWM2CMPA, type R/W, offset 0x0D8, reset 0x0000.0000 (see page 618)
CompA
PWM0CMPB, type R/W, offset 0x05C, reset 0x0000.0000 (see page 619)
CompB
PWM1CMPB, type R/W, offset 0x09C, reset 0x0000.0000 (see page 619)
CompB
PWM2CMPB, type R/W, offset 0x0DC, reset 0x0000.0000 (see page 619)
CompB
PWM0GENA, type R/W, offset 0x060, reset 0x0000.0000 (see page 620)
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
PWM1GENA, type R/W, offset 0x0A0, reset 0x0000.0000 (see page 620)
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
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Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM2GENA, type R/W, offset 0x0E0, reset 0x0000.0000 (see page 620)
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
PWM0GENB, type R/W, offset 0x064, reset 0x0000.0000 (see page 623)
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
PWM1GENB, type R/W, offset 0x0A4, reset 0x0000.0000 (see page 623)
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
PWM2GENB, type R/W, offset 0x0E4, reset 0x0000.0000 (see page 623)
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
PWM0DBCTL, type R/W, offset 0x068, reset 0x0000.0000 (see page 626)
Enable
PWM1DBCTL, type R/W, offset 0x0A8, reset 0x0000.0000 (see page 626)
Enable
PWM2DBCTL, type R/W, offset 0x0E8, reset 0x0000.0000 (see page 626)
Enable
PWM0DBRISE, type R/W, offset 0x06C, reset 0x0000.0000 (see page 627)
RiseDelay
PWM1DBRISE, type R/W, offset 0x0AC, reset 0x0000.0000 (see page 627)
RiseDelay
PWM2DBRISE, type R/W, offset 0x0EC, reset 0x0000.0000 (see page 627)
RiseDelay
PWM0DBFALL, type R/W, offset 0x070, reset 0x0000.0000 (see page 628)
FallDelay
PWM1DBFALL, type R/W, offset 0x0B0, reset 0x0000.0000 (see page 628)
FallDelay
PWM2DBFALL, type R/W, offset 0x0F0, reset 0x0000.0000 (see page 628)
FallDelay
Quadrature Encoder Interface (QEI)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
QEICTL, type R/W, offset 0x000, reset 0x0000.0000 (see page 634)
STALLEN INVI INVB INVA VelDiv VelEn ResMode CapMode SigMode Swap Enable
QEISTAT, type RO, offset 0x004, reset 0x0000.0000 (see page 636)
Direction Error
QEIPOS, type R/W, offset 0x008, reset 0x0000.0000 (see page 637)
Position
Position
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QEIMAXPOS, type R/W, offset 0x00C, reset 0x0000.0000 (see page 638)
MaxPos
MaxPos
QEILOAD, type R/W, offset 0x010, reset 0x0000.0000 (see page 639)
Load
Load
QEITIME, type RO, offset 0x014, reset 0x0000.0000 (see page 640)
Time
Time
QEICOUNT, type RO, offset 0x018, reset 0x0000.0000 (see page 641)
Count
Count
QEISPEED, type RO, offset 0x01C, reset 0x0000.0000 (see page 642)
Speed
Speed
QEIINTEN, type R/W, offset 0x020, reset 0x0000.0000 (see page 643)
IntError IntDir IntTimer IntIndex
QEIRIS, type RO, offset 0x024, reset 0x0000.0000 (see page 644)
IntError IntDir IntTimer IntIndex
QEIISC, type R/W1C, offset 0x028, reset 0x0000.0000 (see page 645)
IntError IntDir IntTimer IntIndex
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Register Quick Reference
C Ordering and Contact Information
C.1 Ordering Information
L M 3 S n n n n – g p p s s – r r m
Part Number
Temperature
Package Speed
Revision
Shipping Medium
E = –40°C to +105°C
I = –40°C to +85°C
T = Tape-and-reel
Omitted = Default shipping (tray or tube)
BZ = 108-ball BGA
QC = 100-pin LQFP
QN = 48-pin LQFP
QR = 64-pin LQFP
GZ = 48-pin QFN
20 = 20 MHz
25 = 25 MHz
50 = 50 MHz
80 = 80 MHz
nnn = Sandstorm-class parts
nnnn = All other Stellaris® parts
Table C-1. Part Ordering Information
Orderable Part Number Description
Stellaris® LM3S2965-IBZ50-A2 LM3S2965 Microcontroller Industrial Temperature 108-ball BGA
Stellaris LM3S2965 Microcontroller Industrial Temperature 108-ball BGA
Tape-and-reel
LM3S2965-IBZ50-A2T
LM3S2965-EQC50-A2 Stellaris LM3S2965 Microcontroller Extended Temperature 100-pin LQFP
Stellaris LM3S2965 Microcontroller Extended Temperature 100-pin LQFP
Tape-and-reel
LM3S2965-EQC50-A2T
LM3S2965-IQC50-A2 Stellaris LM3S2965 Microcontroller Industrial Temperature 100-pin LQFP
Stellaris LM3S2965 Microcontroller Industrial Temperature 100-pin LQFP
Tape-and-reel
LM3S2965-IQC50-A2T
C.2 Part Markings
The Stellaris microcontrollers are marked with an identifying number. This code contains the following
information:
■ The first line indicates the part number. In the example figure below, this is the LM3S6965.
■ In the second line, the first seven characters indicate the temperature, package, speed, and
revision. In the example below, this is an Industrial temperature (I), 100-pin LQFP package (QC),
50-MHz (50), revision A2 (A2) device.
■ The remaining characters contain internal tracking numbers.
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Stellaris® LM3S2965 Microcontroller
C.3 Kits
The Stellaris Family provides the hardware and software tools that engineers need to begin
development quickly.
■ Reference Design Kits accelerate product development by providing ready-to-run hardware and
comprehensive documentation including hardware design files
■ Evaluation Kits provide a low-cost and effective means of evaluating Stellaris microcontrollers
before purchase
■ Development Kits provide you with all the tools you need to develop and prototype embedded
applications right out of the box
See the website at www.ti.com/stellaris for the latest tools available, or ask your distributor.
C.4 Support Information
For support on Stellaris products, contact the TI Worldwide Product Information Center nearest you:
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm.
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Ordering and Contact Information
D Package Information
D.1 100-Pin LQFP Package
D.1.1 Package Dimensions
Figure D-1. 100-Pin LQFP Package Dimensions
Note: The following notes apply to the package drawing.
1. All dimensions shown in mm.
2. Dimensions shown are nominal with tolerances indicated.
3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane.
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Stellaris® LM3S2965 Microcontroller
Body +2.00 mm Footprint, 1.4 mm package thickness
Symbols Leads 100L
A Max. 1.60
A1 - 0.05 Min./0.15 Max.
A2 ±0.05 1.40
D ±0.20 16.00
D1 ±0.05 14.00
E ±0.20 16.00
E1 ±0.05 14.00
L +0.15/-0.10 0.60
e Basic 0.50
b +0.05 0.22
θ - 0˚-7˚
ddd Max. 0.08
ccc Max. 0.08
JEDEC Reference Drawing MS-026
Variation Designator BED
726 January 08, 2011
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Package Information
D.1.2 Tray Dimensions
Figure D-2. 100-Pin LQFP Tray Dimensions
D.1.3 Tape and Reel Dimensions
Note: In the figure that follows, pin 1 is located in the top right corner of the device.
January 08, 2011 727
Texas Instruments-Production Data
Stellaris® LM3S2965 Microcontroller
Figure D-3. 100-Pin LQFP Tape and Reel Dimensions
PRINTED ON
MUST NOT BE REPRODUCED WITHOUT WRITTEN
PERMISSION FROM SUMICARRIER (S) PTE LTD
06.01.2003
THIS IS A COMPUTER GENERATED
UNCONTROLLED DOCUMENT
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06.01.2003
06.01.2003
06.01.2003
728 January 08, 2011
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D.2 108-Ball BGA Package
D.2.1 Package Dimensions
Figure D-4. 108-Ball BGA Package Dimensions
January 08, 2011 729
Texas Instruments-Production Data
Stellaris® LM3S2965 Microcontroller
Note: The following notes apply to the package drawing.
Symbols MIN NOM MAX
A 1.22 1.36 1.50
A1 0.29 0.34 0.39
A3 0.65 0.70 0.75
c 0.28 0.32 0.36
D 9.85 10.00 10.15
D1 8.80 BSC
E 9.85 10.00 10.15
E1 8.80 BSC
b 0.43 0.48 0.53
bbb .20
ddd .12
e 0.80 BSC
f - 0.60 -
M 12
n 108
REF: JEDEC MO-219F
730 January 08, 2011
Texas Instruments-Production Data
Package Information
D.2.2 Tray Dimensions
Figure D-5. 108-Ball BGA Tray Dimensions
January 08, 2011 731
Texas Instruments-Production Data
Stellaris® LM3S2965 Microcontroller
D.2.3 Tape and Reel Dimensions
Figure D-6. 108-Ball BGA Tape and Reel Dimensions
C-PAK PTE LTD
732 January 08, 2011
Texas Instruments-Production Data
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LM3S6110 Microcontroller
DATA SHEET
DS-LM3S6110-1972 Copyright © 2007 Luminary Micro, Inc.
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Copyright © 2007 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of
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http://www.luminarymicro.com
2 November 30, 2007
Preliminary
Table of Contents
About This Document .................................................................................................................... 17
Audience .............................................................................................................................................. 17
About This Manual ................................................................................................................................ 17
Related Documents ............................................................................................................................... 17
Documentation Conventions .................................................................................................................. 17
1 Architectural Overview ...................................................................................................... 19
1.1 Product Features ...................................................................................................................... 19
1.2 Target Applications .................................................................................................................... 24
1.3 High-Level Block Diagram ......................................................................................................... 24
1.4 Functional Overview .................................................................................................................. 25
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 26
1.4.2 Motor Control Peripherals .......................................................................................................... 26
1.4.3 Analog Peripherals .................................................................................................................... 27
1.4.4 Serial Communications Peripherals ............................................................................................ 27
1.4.5 System Peripherals ................................................................................................................... 28
1.4.6 Memory Peripherals .................................................................................................................. 29
1.4.7 Additional Features ................................................................................................................... 30
1.4.8 Hardware Details ...................................................................................................................... 30
2 ARM Cortex-M3 Processor Core ...................................................................................... 31
2.1 Block Diagram .......................................................................................................................... 32
2.2 Functional Description ............................................................................................................... 32
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 32
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 33
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 33
2.2.4 ROM Table ............................................................................................................................... 33
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 33
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 33
3 Memory Map ....................................................................................................................... 37
4 Interrupts ............................................................................................................................ 39
5 JTAG Interface .................................................................................................................... 41
5.1 Block Diagram .......................................................................................................................... 42
5.2 Functional Description ............................................................................................................... 42
5.2.1 JTAG Interface Pins .................................................................................................................. 43
5.2.2 JTAG TAP Controller ................................................................................................................. 44
5.2.3 Shift Registers .......................................................................................................................... 45
5.2.4 Operational Considerations ........................................................................................................ 45
5.3 Initialization and Configuration ................................................................................................... 48
5.4 Register Descriptions ................................................................................................................ 48
5.4.1 Instruction Register (IR) ............................................................................................................. 48
5.4.2 Data Registers .......................................................................................................................... 50
6 System Control ................................................................................................................... 52
6.1 Functional Description ............................................................................................................... 52
6.1.1 Device Identification .................................................................................................................. 52
6.1.2 Reset Control ............................................................................................................................ 52
November 30, 2007 3
Preliminary
LM3S6110 Microcontroller
6.1.3 Power Control ........................................................................................................................... 55
6.1.4 Clock Control ............................................................................................................................ 55
6.1.5 System Control ......................................................................................................................... 57
6.2 Initialization and Configuration ................................................................................................... 57
6.3 Register Map ............................................................................................................................ 58
6.4 Register Descriptions ................................................................................................................ 59
7 Internal Memory ............................................................................................................... 107
7.1 Block Diagram ........................................................................................................................ 107
7.2 Functional Description ............................................................................................................. 107
7.2.1 SRAM Memory ........................................................................................................................ 107
7.2.2 Flash Memory ......................................................................................................................... 108
7.3 Flash Memory Initialization and Configuration ........................................................................... 109
7.3.1 Flash Programming ................................................................................................................. 109
7.3.2 Nonvolatile Register Programming ........................................................................................... 110
7.4 Register Map .......................................................................................................................... 110
7.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 111
7.6 Flash Register Descriptions (System Control Offset) .................................................................. 118
8 General-Purpose Input/Outputs (GPIOs) ....................................................................... 131
8.1 Functional Description ............................................................................................................. 131
8.1.1 Data Control ........................................................................................................................... 132
8.1.2 Interrupt Control ...................................................................................................................... 133
8.1.3 Mode Control .......................................................................................................................... 134
8.1.4 Commit Control ....................................................................................................................... 134
8.1.5 Pad Control ............................................................................................................................. 134
8.1.6 Identification ........................................................................................................................... 134
8.2 Initialization and Configuration ................................................................................................. 134
8.3 Register Map .......................................................................................................................... 135
8.4 Register Descriptions .............................................................................................................. 137
9 General-Purpose Timers ................................................................................................. 172
9.1 Block Diagram ........................................................................................................................ 172
9.2 Functional Description ............................................................................................................. 173
9.2.1 GPTM Reset Conditions .......................................................................................................... 173
9.2.2 32-Bit Timer Operating Modes .................................................................................................. 174
9.2.3 16-Bit Timer Operating Modes .................................................................................................. 175
9.3 Initialization and Configuration ................................................................................................. 179
9.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 179
9.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 180
9.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 180
9.3.4 16-Bit Input Edge Count Mode ................................................................................................. 181
9.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 181
9.3.6 16-Bit PWM Mode ................................................................................................................... 182
9.4 Register Map .......................................................................................................................... 182
9.5 Register Descriptions .............................................................................................................. 183
10 Watchdog Timer ............................................................................................................... 208
10.1 Block Diagram ........................................................................................................................ 208
10.2 Functional Description ............................................................................................................. 208
10.3 Initialization and Configuration ................................................................................................. 209
4 November 30, 2007
Preliminary
Table of Contents
10.4 Register Map .......................................................................................................................... 209
10.5 Register Descriptions .............................................................................................................. 210
11 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 231
11.1 Block Diagram ........................................................................................................................ 232
11.2 Functional Description ............................................................................................................. 232
11.2.1 Transmit/Receive Logic ........................................................................................................... 232
11.2.2 Baud-Rate Generation ............................................................................................................. 233
11.2.3 Data Transmission .................................................................................................................. 234
11.2.4 Serial IR (SIR) ......................................................................................................................... 234
11.2.5 FIFO Operation ....................................................................................................................... 235
11.2.6 Interrupts ................................................................................................................................ 235
11.2.7 Loopback Operation ................................................................................................................ 236
11.2.8 IrDA SIR block ........................................................................................................................ 236
11.3 Initialization and Configuration ................................................................................................. 236
11.4 Register Map .......................................................................................................................... 237
11.5 Register Descriptions .............................................................................................................. 238
12 Synchronous Serial Interface (SSI) ................................................................................ 272
12.1 Block Diagram ........................................................................................................................ 272
12.2 Functional Description ............................................................................................................. 272
12.2.1 Bit Rate Generation ................................................................................................................. 273
12.2.2 FIFO Operation ....................................................................................................................... 273
12.2.3 Interrupts ................................................................................................................................ 273
12.2.4 Frame Formats ....................................................................................................................... 274
12.3 Initialization and Configuration ................................................................................................. 281
12.4 Register Map .......................................................................................................................... 282
12.5 Register Descriptions .............................................................................................................. 283
13 Ethernet Controller .......................................................................................................... 309
13.1 Block Diagram ........................................................................................................................ 310
13.2 Functional Description ............................................................................................................. 310
13.2.1 Internal MII Operation .............................................................................................................. 310
13.2.2 PHY Configuration/Operation ................................................................................................... 311
13.2.3 MAC Configuration/Operation .................................................................................................. 312
13.2.4 Interrupts ................................................................................................................................ 314
13.3 Initialization and Configuration ................................................................................................. 315
13.4 Ethernet Register Map ............................................................................................................. 315
13.5 Ethernet MAC Register Descriptions ......................................................................................... 317
13.6 MII Management Register Descriptions ..................................................................................... 334
14 Analog Comparators ....................................................................................................... 353
14.1 Block Diagram ........................................................................................................................ 354
14.2 Functional Description ............................................................................................................. 354
14.2.1 Internal Reference Programming .............................................................................................. 356
14.3 Initialization and Configuration ................................................................................................. 357
14.4 Register Map .......................................................................................................................... 357
14.5 Register Descriptions .............................................................................................................. 358
15 Pulse Width Modulator (PWM) ........................................................................................ 366
15.1 Block Diagram ........................................................................................................................ 366
15.2 Functional Description ............................................................................................................. 366
November 30, 2007 5
Preliminary
LM3S6110 Microcontroller
15.2.1 PWM Timer ............................................................................................................................. 366
15.2.2 PWM Comparators .................................................................................................................. 367
15.2.3 PWM Signal Generator ............................................................................................................ 368
15.2.4 Dead-Band Generator ............................................................................................................. 369
15.2.5 Interrupt Selector ..................................................................................................................... 369
15.2.6 Synchronization Methods ......................................................................................................... 369
15.2.7 Fault Conditions ...................................................................................................................... 369
15.2.8 Output Control Block ............................................................................................................... 370
15.3 Initialization and Configuration ................................................................................................. 370
15.4 Register Map .......................................................................................................................... 371
15.5 Register Descriptions .............................................................................................................. 372
16 Pin Diagram ...................................................................................................................... 401
17 Signal Tables .................................................................................................................... 402
18 Operating Characteristics ............................................................................................... 414
19 Electrical Characteristics ................................................................................................ 415
19.1 DC Characteristics .................................................................................................................. 415
19.1.1 Maximum Ratings ................................................................................................................... 415
19.1.2 Recommended DC Operating Conditions .................................................................................. 415
19.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 416
19.1.4 Power Specifications ............................................................................................................... 416
19.1.5 Flash Memory Characteristics .................................................................................................. 417
19.2 AC Characteristics ................................................................................................................... 418
19.2.1 Load Conditions ...................................................................................................................... 418
19.2.2 Clocks .................................................................................................................................... 418
19.2.3 Analog Comparator ................................................................................................................. 419
19.2.4 Ethernet Controller .................................................................................................................. 419
19.2.5 Synchronous Serial Interface (SSI) ........................................................................................... 422
19.2.6 JTAG and Boundary Scan ........................................................................................................ 424
19.2.7 General-Purpose I/O ............................................................................................................... 425
19.2.8 Reset ..................................................................................................................................... 426
20 Package Information ........................................................................................................ 428
A Serial Flash Loader .......................................................................................................... 430
A.1 Serial Flash Loader ................................................................................................................. 430
A.2 Interfaces ............................................................................................................................... 430
A.2.1 UART ..................................................................................................................................... 430
A.2.2 SSI ......................................................................................................................................... 430
A.3 Packet Handling ...................................................................................................................... 431
A.3.1 Packet Format ........................................................................................................................ 431
A.3.2 Sending Packets ..................................................................................................................... 431
A.3.3 Receiving Packets ................................................................................................................... 431
A.4 Commands ............................................................................................................................. 432
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 432
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 432
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 432
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 433
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 433
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 433
6 November 30, 2007
Preliminary
Table of Contents
B Register Quick Reference ............................................................................................... 435
C Ordering and Contact Information ................................................................................. 449
C.1 Ordering Information ................................................................................................................ 449
C.2 Kits ......................................................................................................................................... 449
C.3 Company Information .............................................................................................................. 449
C.4 Support Information ................................................................................................................. 450
November 30, 2007 7
Preliminary
LM3S6110 Microcontroller
List of Figures
Figure 1-1. Stellaris® 6000 Series High-Level Block Diagram ............................................................... 25
Figure 2-1. CPU Block Diagram ......................................................................................................... 32
Figure 2-2. TPIU Block Diagram ........................................................................................................ 33
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 42
Figure 5-2. Test Access Port State Machine ....................................................................................... 45
Figure 5-3. IDCODE Register Format ................................................................................................. 50
Figure 5-4. BYPASS Register Format ................................................................................................ 51
Figure 5-5. Boundary Scan Register Format ....................................................................................... 51
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 53
Figure 7-1. Flash Block Diagram ...................................................................................................... 107
Figure 8-1. GPIO Port Block Diagram ............................................................................................... 132
Figure 8-2. GPIODATA Write Example ............................................................................................. 133
Figure 8-3. GPIODATA Read Example ............................................................................................. 133
Figure 9-1. GPTM Module Block Diagram ........................................................................................ 173
Figure 9-2. 16-Bit Input Edge Count Mode Example .......................................................................... 177
Figure 9-3. 16-Bit Input Edge Time Mode Example ........................................................................... 178
Figure 9-4. 16-Bit PWM Mode Example ............................................................................................ 179
Figure 10-1. WDT Module Block Diagram .......................................................................................... 208
Figure 11-1. UART Module Block Diagram ......................................................................................... 232
Figure 11-2. UART Character Frame ................................................................................................. 233
Figure 11-3. IrDA Data Modulation ..................................................................................................... 235
Figure 12-1. SSI Module Block Diagram ............................................................................................. 272
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 275
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 275
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 276
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 276
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 277
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 278
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 278
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 279
Figure 12-10. MICROWIRE Frame Format (Single Frame) .................................................................... 280
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 281
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 281
Figure 13-1. Ethernet Controller Block Diagram .................................................................................. 310
Figure 13-2. Ethernet Controller ......................................................................................................... 310
Figure 13-3. Ethernet Frame ............................................................................................................. 312
Figure 14-1. Analog Comparator Module Block Diagram ..................................................................... 354
Figure 14-2. Structure of Comparator Unit .......................................................................................... 355
Figure 14-3. Comparator Internal Reference Structure ........................................................................ 356
Figure 15-1. PWM Module Block Diagram .......................................................................................... 366
Figure 15-2. PWM Count-Down Mode ................................................................................................ 367
Figure 15-3. PWM Count-Up/Down Mode .......................................................................................... 368
Figure 15-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 368
Figure 15-5. PWM Dead-Band Generator ........................................................................................... 369
Figure 16-1. Pin Connection Diagram ................................................................................................ 401
Figure 19-1. Load Conditions ............................................................................................................ 418
8 November 30, 2007
Preliminary
Table of Contents
Figure 19-2. External XTLP Oscillator Characteristics ......................................................................... 422
Figure 19-3. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 423
Figure 19-4. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 423
Figure 19-5. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 424
Figure 19-6. JTAG Test Clock Input Timing ......................................................................................... 425
Figure 19-7. JTAG Test Access Port (TAP) Timing .............................................................................. 425
Figure 19-8. JTAG TRST Timing ........................................................................................................ 425
Figure 19-9. External Reset Timing (RST) .......................................................................................... 426
Figure 19-10. Power-On Reset Timing ................................................................................................. 427
Figure 19-11. Brown-Out Reset Timing ................................................................................................ 427
Figure 19-12. Software Reset Timing ................................................................................................... 427
Figure 19-13. Watchdog Reset Timing ................................................................................................. 427
Figure 20-1. 100-Pin LQFP Package .................................................................................................. 428
November 30, 2007 9
Preliminary
LM3S6110 Microcontroller
List of Tables
Table 1. Documentation Conventions ............................................................................................ 17
Table 3-1. Memory Map ................................................................................................................... 37
Table 4-1. Exception Types .............................................................................................................. 39
Table 4-2. Interrupts ........................................................................................................................ 40
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 43
Table 5-2. JTAG Instruction Register Commands ............................................................................... 48
Table 6-1. System Control Register Map ........................................................................................... 58
Table 7-1. Flash Protection Policy Combinations ............................................................................. 109
Table 7-2. Flash Resident Registers ............................................................................................... 110
Table 7-3. Flash Register Map ........................................................................................................ 110
Table 8-1. GPIO Pad Configuration Examples ................................................................................. 134
Table 8-2. GPIO Interrupt Configuration Example ............................................................................ 135
Table 8-3. GPIO Register Map ....................................................................................................... 136
Table 9-1. Available CCP Pins ........................................................................................................ 173
Table 9-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 176
Table 9-3. Timers Register Map ...................................................................................................... 182
Table 10-1. Watchdog Timer Register Map ........................................................................................ 209
Table 11-1. UART Register Map ....................................................................................................... 237
Table 12-1. SSI Register Map .......................................................................................................... 282
Table 13-1. TX & RX FIFO Organization ........................................................................................... 313
Table 13-2. Ethernet Register Map ................................................................................................... 316
Table 14-1. Comparator 0 Operating Modes ...................................................................................... 355
Table 14-2. Comparator 1 Operating Modes ..................................................................................... 355
Table 14-3. Comparator 2 Operating Modes ...................................................................................... 356
Table 14-4. Internal Reference Voltage and ACREFCTL Field Values ................................................. 356
Table 14-5. Analog Comparators Register Map ................................................................................. 358
Table 15-1. PWM Register Map ........................................................................................................ 371
Table 17-1. Signals by Pin Number ................................................................................................... 402
Table 17-2. Signals by Signal Name ................................................................................................. 406
Table 17-3. Signals by Function, Except for GPIO ............................................................................. 409
Table 17-4. GPIO Pins and Alternate Functions ................................................................................. 412
Table 18-1. Temperature Characteristics ........................................................................................... 414
Table 18-2. Thermal Characteristics ................................................................................................. 414
Table 19-1. Maximum Ratings .......................................................................................................... 415
Table 19-2. Recommended DC Operating Conditions ........................................................................ 415
Table 19-3. LDO Regulator Characteristics ....................................................................................... 416
Table 19-4. Detailed Power Specifications ........................................................................................ 417
Table 19-5. Flash Memory Characteristics ........................................................................................ 417
Table 19-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 418
Table 19-7. Clock Characteristics ..................................................................................................... 418
Table 19-8. Crystal Characteristics ................................................................................................... 418
Table 19-9. Analog Comparator Characteristics ................................................................................. 419
Table 19-10. Analog Comparator Voltage Reference Characteristics .................................................... 419
Table 19-11. 100BASE-TX Transmitter Characteristics ........................................................................ 419
Table 19-12. 100BASE-TX Transmitter Characteristics (informative) ..................................................... 419
Table 19-13. 100BASE-TX Receiver Characteristics ............................................................................ 420
10 November 30, 2007
Preliminary
Table of Contents
Table 19-14. 10BASE-T Transmitter Characteristics ............................................................................ 420
Table 19-15. 10BASE-T Transmitter Characteristics (informative) ......................................................... 420
Table 19-16. 10BASE-T Receiver Characteristics ................................................................................ 420
Table 19-17. Isolation Transformers ................................................................................................... 420
Table 19-18. Ethernet Reference Crystal ............................................................................................ 421
Table 19-19. External XTLP Oscillator Characteristics ......................................................................... 422
Table 19-20. SSI Characteristics ........................................................................................................ 422
Table 19-21. JTAG Characteristics ..................................................................................................... 424
Table 19-22. GPIO Characteristics ..................................................................................................... 426
Table 19-23. Reset Characteristics ..................................................................................................... 426
Table C-1. Part Ordering Information ............................................................................................... 449
November 30, 2007 11
Preliminary
LM3S6110 Microcontroller
List of Registers
System Control .............................................................................................................................. 52
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 60
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 62
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 63
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 64
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 65
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 66
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 67
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 68
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 72
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 73
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 75
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 76
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 78
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 79
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 81
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 83
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 85
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 87
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 88
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 89
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 90
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 92
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ......................... 94
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 .................................... 96
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 .................................. 98
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 100
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 102
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 103
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 105
Internal Memory ........................................................................................................................... 107
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 112
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 113
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 114
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 116
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 117
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 118
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 119
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 120
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 121
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 122
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 123
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 124
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 125
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 126
12 November 30, 2007
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Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 127
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 128
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 129
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 130
General-Purpose Input/Outputs (GPIOs) ................................................................................... 131
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 138
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 139
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 140
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 141
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 142
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 143
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 144
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 145
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 146
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 147
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 149
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 150
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 151
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 152
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 153
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 154
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 155
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 156
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 157
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 158
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 160
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 161
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 162
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 163
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 164
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 165
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 166
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 167
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 168
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 169
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 170
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 171
General-Purpose Timers ............................................................................................................. 172
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 184
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 185
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 187
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 189
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 192
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 194
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 195
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 196
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 198
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 199
November 30, 2007 13
Preliminary
LM3S6110 Microcontroller
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 200
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 201
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 202
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 203
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 204
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 205
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 206
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 207
Watchdog Timer ........................................................................................................................... 208
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 211
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 212
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 213
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 214
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 215
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 216
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 217
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 218
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 219
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 220
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 221
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 222
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 223
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 224
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 225
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 226
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 227
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 228
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 229
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 230
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 231
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 239
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 241
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 243
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 245
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 246
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 247
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 248
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 250
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 252
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 254
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 256
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 257
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 258
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 260
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 261
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 262
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 263
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 264
14 November 30, 2007
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Table of Contents
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 265
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 266
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 267
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 268
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 269
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 270
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 271
Synchronous Serial Interface (SSI) ............................................................................................ 272
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 284
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 286
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 288
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 289
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 291
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 292
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 294
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 295
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 296
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 297
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 298
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 299
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 300
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 301
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 302
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 303
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 304
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 305
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 306
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 307
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 308
Ethernet Controller ...................................................................................................................... 309
Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 318
Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 320
Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 321
Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 322
Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 323
Register 6: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 324
Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 326
Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 327
Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 328
Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 329
Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 330
Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 331
Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 332
Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 333
Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 334
Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 335
Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 337
Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 339
November 30, 2007 15
Preliminary
LM3S6110 Microcontroller
Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 340
Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 341
Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 343
Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 344
Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 345
Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address
0x11 .............................................................................................................................. 347
Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 349
Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 350
Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 351
Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 352
Analog Comparators ................................................................................................................... 353
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 359
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 360
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 361
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 362
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 363
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 363
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60 ....................................................... 363
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 364
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 364
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64 ...................................................... 364
Pulse Width Modulator (PWM) .................................................................................................... 366
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 373
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 374
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 375
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 376
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 377
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 378
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 379
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 380
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 381
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 382
Register 11: PWM0 Interrupt Enable (PWM0INTEN), offset 0x044 ...................................................... 384
Register 12: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 386
Register 13: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 387
Register 14: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 388
Register 15: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 389
Register 16: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 390
Register 17: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 391
Register 18: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 392
Register 19: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 395
Register 20: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 398
Register 21: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 399
Register 22: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 400
16 November 30, 2007
Preliminary
Table of Contents
About This Document
This data sheet provides reference information for the LM3S6110 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■ ARM® Cortex™-M3 Technical Reference Manual
■ ARM® CoreSight Technical Reference Manual
■ ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 17.
Table 1. Documentation Conventions
Notation Meaning
General Register Notation
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
REGISTER
bit A single bit in a register.
bit field Two or more consecutive and related bits.
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 37.
offset 0xnnn
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Register N
November 30, 2007 17
Preliminary
LM3S6110 Microcontroller
Notation Meaning
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
reserved
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
yy:xx
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Register Bit/Field
Types
RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO Software can read this field. Always write the chip reset value.
R/W Software can read or write this field.
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1C
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
W1C
WO Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field This value in the register bit diagram shows the bit/field value after any reset, unless noted.
Reset Value
0 Bit cleared to 0 on chip reset.
1 Bit set to 1 on chip reset.
- Nondeterministic.
Pin/Signal Notation
[ ] Pin alternate function; a pin defaults to the signal without the brackets.
pin Refers to the physical connection on the package.
signal Refers to the electrical signal encoding of a pin.
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
assert a signal
deassert a signal Change the value of the signal from the logically True state to the logically False state.
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
SIGNAL
Numbers
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
X
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
0x
18 November 30, 2007
Preliminary
About This Document
1 Architectural Overview
The Luminary Micro Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The Stellaris® family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris® LM3S1000 series extends the Stellaris® family with larger on-chip
memories, enhanced power management, and expanded I/O and control capabilities. The Stellaris®
LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris
family with Bosch CAN networking technology, the golden standard in short-haul industrial networks.
The Stellaris® LM3S2000 series also marks the first integration of CAN capabilities with the
revolutionary Cortex-M3 core. The Stellaris® LM3S6000 series combines both a 10/100 Ethernet
Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated
connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC
and PHY available in an ARM architecture MCU. The Stellaris® LM3S8000 series combines Bosch
Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and
Physical (PHY) layer.
The LM3S6110 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
In addition, the LM3S6110 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S6110 microcontroller is code-compatible
to all members of the extensive Stellaris® family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
1.1 Product Features
The LM3S6110 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 25-MHz operation
– Hardware-division and single-cycle-multiplication
November 30, 2007 19
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LM3S6110 Microcontroller
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 24 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
– 64 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 16 KB single-cycle SRAM
■ General-Purpose Timers
– Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
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Architectural Overview
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ 10/100 Ethernet Controller
– Conforms to the IEEE 802.3-2002 Specification
– Full- and half-duplex for both 100 Mbps and 10 Mbps operation
– Integrated 10/100 Mbps Transceiver (PHY)
– Automatic MDI/MDI-X cross-over correction
– Programmable MAC address
– Power-saving and power-down modes
■ Synchronous Serial Interface (SSI)
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Fully programmable 16C550-type UART with IrDA support
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LM3S6110 Microcontroller
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator with fractional divider
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ Analog Comparators
– Three independent integrated analog comparators
– Configurable for output to: drive an output pin or generate an interrupt
– Compare external pin input to external pin input or to internal programmable voltage reference
■ PWM
– One PWM generator blocks, each with one 16-bit counter, two comparators, a PWM generator,
and a dead-band generator
– One 16-bit counter
• Runs in Down or Up/Down mode
• Output frequency controlled by a 16-bit load value
• Load value updates can be synchronized
• Produces output signals at zero and load value
– Two PWM comparators
• Comparator value updates can be synchronized
• Produces output signals on match
– PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
• Produces two independent PWM signals
– Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge
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• Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
• PWM output enable of each PWM signal
• Optional output inversion of each PWM signal (polarity control)
• Optional fault handling for each PWM signal
• Synchronization of timers in the PWM generator blocks
• Synchronization of timer/comparator updates across the PWM generator blocks
• Interrupt status summary of the PWM generator blocks
■ GPIOs
– 8-35 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
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LM3S6110 Microcontroller
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial-range 100-pin RoHS-compliant LQFP package
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
1.3 High-Level Block Diagram
Figure 1-1 on page 25 represents the full set of features in the Stellaris® 6000 series of devices;
not all features may be available on the LM3S6110 microcontroller.
24 November 30, 2007
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Architectural Overview
Figure 1-1. Stellaris® 6000 Series High-Level Block Diagram
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S6110 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 449.
November 30, 2007 25
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LM3S6110 Microcontroller
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 31)
All members of the Stellaris® product family, including the LM3S6110 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 31 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S6110 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 24 interrupts.
“Interrupts” on page 39 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S6110 controller features Pulse Width Modulation (PWM) outputs.
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
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On the LM3S6110, PWM motion control functionality can be achieved through:
■ Dedicated, flexible motion control hardware using the PWM pins
■ The motion control features of the general-purpose timers using the CCP pins
PWM Pins (see page 366)
The LM3S6110 PWM module consists of one PWM generator blocks and a control block. Each
PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a
PWM signal generator, a dead-band generator, and an interrupt. The control block determines the
polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. The output of the PWM
generation blocks are managed by the output control block before being passed to the device pins.
CCP Pins (see page 178)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.3 Analog Peripherals
For support of analog signals, the LM3S6110 microcontroller offers three analog comparators.
1.4.3.1 Analog Comparators (see page 353)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S6110 microcontroller provides three independent integrated analog comparators that can
be configured to drive an output or generate an interrupt .
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts to cause it to start
capturing a sample sequence.
1.4.4 Serial Communications Peripherals
The LM3S6110 controller supports both asynchronous and synchronous serial communications
with:
■ One fully programmable 16C550-type UART
■ One SSI module
■ Ethernet controller
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LM3S6110 Microcontroller
1.4.4.1 UART (see page 231)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S6110 controller includes one fully programmable 16C550-type UARTthat supports data
transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.4.2 SSI (see page 272)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S6110 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.4.3 Ethernet Controller (see page 309)
Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet
has been standardized as IEEE 802.3. It defines a number of wiring and signaling standards for the
physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer,
and a common addressing format.
The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and
network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3
specifications and fully supports 10BASE-T and 100BASE-TX standards. In addition, the Ethernet
Controller supports automatic MDI/MDI-X cross-over correction.
1.4.5 System Peripherals
1.4.5.1 Programmable GPIOs (see page 131)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris® GPIO module is composed of seven physical GPIO blocks, each corresponding to
an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation
IP for Real-Time Microcontrollers specification) and supports 8-35 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page
402 for the signals available to each GPIO pin).
28 November 30, 2007
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The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines.
1.4.5.2 Three Programmable Timers (see page 172)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris® General-Purpose Timer Module (GPTM) contains three GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.5.3 Watchdog Timer (see page 208)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
The Stellaris® Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
1.4.6 Memory Peripherals
The LM3S6110 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.6.1 SRAM (see page 107)
The LM3S6110 static random access memory (SRAM) controller supports 16 KB SRAM. The internal
SRAM of the Stellaris® devices is located at offset 0x0000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
1.4.6.2 Flash (see page 108)
The LM3S6110 Flash controller supports 64 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
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LM3S6110 Microcontroller
1.4.7 Additional Features
1.4.7.1 Memory Map (see page 37)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S6110 controller can be found in “Memory Map” on page 37. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
1.4.7.2 JTAG TAP Controller (see page 41)
The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the
Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG
data registers can be used to test the interconnects of assembled printed circuit boards, obtain
manufacturing information on the components, and observe and/or control the inputs and outputs
of the controller during normal operation. The JTAG port provides a high degree of testability and
chip-level access at a low cost.
The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
1.4.7.3 System Control and Clocks (see page 52)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
1.4.8 Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 401
■ “Signal Tables” on page 402
■ “Operating Characteristics” on page 414
■ “Electrical Characteristics” on page 415
■ “Package Information” on page 428
30 November 30, 2007
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Architectural Overview
2 ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that
meets the needs of minimal memory implementation, reduced pin count, and low power consumption,
while delivering outstanding computational performance and exceptional system response to
interrupts. Features include:
■ Compact core.
■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of
memory for microcontroller class applications.
■ Rapid application execution through Harvard architecture characterized by separate buses for
instruction and data.
■ Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.
■ Migration from the ARM7™ processor family for better performance and power efficiency.
■ Full-featured debug solution with a:
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
The Stellaris® family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motors.
For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference
Manual.
November 30, 2007 31
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LM3S6110 Microcontroller
2.1 Block Diagram
Figure 2-1. CPU Block Diagram
Private Peripheral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
Instrumentation
Trace Macrocell
Trace
Port
Interface
Unit
CM3 Core
Instructions Data
Flash
Patch and
Breakpoint
Memory
Protection
Unit
Adv. High-
Perf. Bus
Access Port
Nested
Vectored
Interrupt
Controller
Serial Wire JTAG
Debug Port
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
ROM
Table
Private
Peripheral
Bus
(external)
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex-M3
2.2 Functional Description
Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
This section describes the Stellaris® implementation.
Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 32. As
noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are
flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested
Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.
2.2.1 Serial Wire and JTAG Debug
Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the
ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris® devices.
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
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ARM Cortex-M3 Processor Core
2.2.2 Embedded Trace Macrocell (ETM)
ETM was not implemented in the Stellaris® devices. This means Chapters 15 and 16 of the ARM®
Cortex™-M3 Technical Reference Manual can be ignored.
2.2.3 Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer. The Stellaris® devices have implemented TPIU as shown in Figure 2-2 on page 33.
This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference
Manual, however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
ATB
Interface
Asynchronous FIFO
APB
Interface
Trace Out
(serializer)
Debug
ATB
Slave
Port
APB
Slave
Port
Serial Wire
Trace Port
(SWO)
2.2.4 ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
2.2.5 Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S6110 controller and supports the standard
ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for
protection regions, overlapping protection regions, access permissions, and exporting memory
attributes to the system.
2.2.6 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
■ Facilitates low-latency exception and interrupt handling
■ Controls power management
■ Implements system control registers
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LM3S6110 Microcontroller
The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of
priority. The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge
of the stacked (nested) interrupts to enable tail-chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode
if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference
Manual). Any other user-mode access causes a bus fault.
All NVIC registers are accessible using byte, halfword, and word unless otherwise stated.
All NVIC registers and system debug registers are little endian regardless of the endianness state
of the processor.
2.2.6.1 Interrupts
The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts
and interrupt priorities. The LM3S6110 microcontroller supports 24 interrupts with eight priority
levels.
2.2.6.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
Functional Description
The timer consists of three registers:
■ A control and status counter to configure its clock, enable the counter, enable the SysTick
interrupt, and determine counter status.
■ The reload value for the counter, used to provide the counter's wrap value.
■ The current value of the counter.
A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris® devices.
When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value
in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks.
Writing a value of zero to the Reload Value register disables the counter on the next wrap. When
the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
34 November 30, 2007
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ARM Cortex-M3 Processor Core
Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write
does not trigger the SysTick exception logic. On a read, the current value is the value of the register
at the time the register is accessed.
If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect
to a reference clock. The reference clock can be the core clock or an external clock source.
SysTick Control and Status Register
Use the SysTick Control and Status Register to enable the SysTick features. The reset is
0x0000.0000.
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
31:17 reserved RO 0
Returns 1 if timer counted to 0 since last time this was read. Clears on read by
application. If read by the debugger using the DAP, this bit is cleared on read-only
if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the
COUNTFLAG bit is not changed by the debugger read.
16 COUNTFLAG R/W 0
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
15:3 reserved RO 0
0 = external reference clock. (Not implemented for Stellaris microcontrollers.)
1 = core clock.
If no reference clock is provided, it is held at 1 and so gives the same time as the
core clock. The core clock must be at least 2.5 times faster than the reference clock.
If it is not, the count values are unpredictable.
2 CLKSOURCE R/W 0
1 = counting down to 0 pends the SysTick handler.
0 = counting down to 0 does not pend the SysTick handler. Software can use the
COUNTFLAG to determine if ever counted to 0.
1 TICKINT R/W 0
1 = counter operates in a multi-shot way. That is, counter loads with the Reload
value and then begins counting down. On reaching 0, it sets the COUNTFLAG to
1 and optionally pends the SysTick handler, based on TICKINT. It then loads the
Reload value again, and begins counting.
0 = counter disabled.
0 ENABLE R/W 0
SysTick Reload Value Register
Use the SysTick Reload Value Register to specify the start value to load into the current value
register when the counter reaches 0. It can be any value between 1 and 0x00FF.FFFF. A start value
of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated
when counting from 1 to 0.
Therefore, as a multi-shot timer, repeated over and over, it fires every N+1 clock pulse, where N is
any value from 1 to 0x00FF.FFFF. So, if the tick interrupt is required every 100 clock pulses, 99
must be written into the RELOAD. If a new value is written on each tick interrupt, so treated as single
shot, then the actual count down must be written. For example, if a tick is next required after 400
clock pulses, 400 must be written into the RELOAD.
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a read-modify-write
operation.
31:24 reserved RO 0
November 30, 2007 35
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LM3S6110 Microcontroller
Bit/Field Name Type Reset Description
23:0 RELOAD W1C - Value to load into the SysTick Current Value Register when the counter reaches 0.
SysTick Current Value Register
Use the SysTick Current Value Register to find the current value in the register.
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
31:24 reserved RO 0
Current value at the time the register is accessed. No read-modify-write protection is
provided, so change with care.
This register is write-clear. Writing to it with any value clears the register to 0. Clearing
this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
23:0 CURRENT W1C -
SysTick Calibration Value Register
The SysTick Calibration Value register is not implemented.
36 November 30, 2007
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ARM Cortex-M3 Processor Core
3 Memory Map
The memory map for the LM3S6110 controller is provided in Table 3-1 on page 37.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Important: In Table 3-1 on page 37, addresses not listed are reserved.
Table 3-1. Memory Mapa
For details on
registers, see
page ...
Start End Description
Memory
0x0000.0000 0x0000.FFFF On-chip flash b 111
0x2000.0000 0x2000.3FFF Bit-banded on-chip SRAMc 111
0x2010.0000 0x21FF.FFFF Reserved non-bit-banded SRAM space -
0x2200.0000 0x23FF.FFFF Bit-band alias of 0x2000.0000 through 0x200F.FFFF 107
0x2400.0000 0x3FFF.FFFF Reserved non-bit-banded SRAM space -
FiRM Peripherals
0x4000.0000 0x4000.0FFF Watchdog timer 210
0x4000.4000 0x4000.4FFF GPIO Port A 137
0x4000.5000 0x4000.5FFF GPIO Port B 137
0x4000.6000 0x4000.6FFF GPIO Port C 137
0x4000.7000 0x4000.7FFF GPIO Port D 137
0x4000.8000 0x4000.8FFF SSI0 283
0x4000.C000 0x4000.CFFF UART0 238
Peripherals
0x4002.4000 0x4002.4FFF GPIO Port E 137
0x4002.5000 0x4002.5FFF GPIO Port F 137
0x4002.6000 0x4002.6FFF GPIO Port G 137
0x4002.8000 0x4002.8FFF PWM 372
0x4003.0000 0x4003.0FFF Timer0 183
0x4003.1000 0x4003.1FFF Timer1 183
0x4003.2000 0x4003.2FFF Timer2 183
0x4003.C000 0x4003.CFFF Analog Comparators 353
0x4004.8000 0x4004.8FFF Ethernet Controller 317
0x400F.D000 0x400F.DFFF Flash control 111
0x400F.E000 0x400F.EFFF System control 59
0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF -
Private Peripheral Bus
November 30, 2007 37
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LM3S6110 Microcontroller
For details on
registers, see
page ...
Start End Description
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM)
0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT)
0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB)
0xE000.3000 0xE000.DFFF Reserved
0xE000.E000 0xE000.EFFF Nested Vectored Interrupt Controller (NVIC)
0xE000.F000 0xE003.FFFF Reserved
0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU)
0xE004.1000 0xE004.1FFF Reserved -
0xE004.2000 0xE00F.FFFF Reserved -
0xE010.0000 0xFFFF.FFFF Reserved for vendor peripherals -
a. All reserved space returns a bus fault when read or written.
b. The unavailable flash will bus fault throughout this range.
c. The unavailable SRAM will bus fault throughout this range.
38 November 30, 2007
Preliminary
Memory Map
4 Interrupts
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions. All exceptions are handled in Handler Mode. The processor state is
automatically stored to the stack on an exception, and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which
enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back
interrupts to be performed without the overhead of state saving and restoration.
Table 4-1 on page 39 lists all the exceptions. Software can set eight priority levels on seven of these
exceptions (system handlers) as well as on 24 interrupts (listed in Table 4-2 on page 40).
Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts
are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt
Priority registers. You can also group priorities by splitting priority levels into pre-emption priorities
and subpriorities. All the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt
Controller” in the ARM® Cortex™-M3 Technical Reference Manual.
Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and
a Hard Fault. Note that 0 is the default priority for all the settable priorities.
If you assign the same priority level to two or more interrupts, their hardware priority (the lower the
position number) determines the order in which the processor activates them. For example, if both
GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority.
See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM®
Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts.
Note: In Table 4-2 on page 40 interrupts not listed are reserved.
Table 4-1. Exception Types
Exception Type Position Prioritya Description
- 0 - Stack top is loaded from first entry of vector table on reset.
Invoked on power up and warm reset. On first instruction, drops to lowest
priority (and then is called the base level of activation). This is
asynchronous.
Reset 1 -3 (highest)
Cannot be stopped or preempted by any exception but reset. This is
asynchronous.
An NMI is only producible by software, using the NVIC Interrupt Control
State register.
Non-Maskable 2 -2
Interrupt (NMI)
All classes of Fault, when the fault cannot activate due to priority or the
configurable fault handler has been disabled. This is synchronous.
Hard Fault 3 -1
MPU mismatch, including access violation and no match. This is
synchronous.
The priority of this exception can be changed.
Memory Management 4 settable
Pre-fetch fault, memory access fault, and other address/memory related
faults. This is synchronous when precise and asynchronous when
imprecise.
You can enable or disable this fault.
Bus Fault 5 settable
Usage fault, such as undefined instruction executed or illegal state
transition attempt. This is synchronous.
Usage Fault 6 settable
- 7-10 - Reserved.
SVCall 11 settable System service call with SVC instruction. This is synchronous.
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LM3S6110 Microcontroller
Exception Type Position Prioritya Description
Debug monitor (when not halting). This is synchronous, but only active
when enabled. It does not activate if lower priority than the current
activation.
Debug Monitor 12 settable
- 13 - Reserved.
Pendable request for system service. This is asynchronous and only
pended by software.
PendSV 14 settable
SysTick 15 settable System tick timer has fired. This is asynchronous.
Asserted from outside the ARM Cortex-M3 core and fed through the NVIC
(prioritized). These are all asynchronous. Table 4-2 on page 40 lists the
interrupts on the LM3S6110 controller.
16 and settable
above
Interrupts
a. 0 is the default priority for all the settable priorities.
Table 4-2. Interrupts
Interrupt (Bit in Interrupt Registers) Description
0 GPIO Port A
1 GPIO Port B
2 GPIO Port C
3 GPIO Port D
4 GPIO Port E
5 UART0
7 SSI0
9 PWM Fault
10 PWM Generator 0
18 Watchdog timer
19 Timer0 A
20 Timer0 B
21 Timer1 A
22 Timer1 B
23 Timer2 A
24 Timer2 B
25 Analog Comparator 0
26 Analog Comparator 1
27 Analog Comparator 2
28 System Control
29 Flash Control
30 GPIO Port F
31 GPIO Port G
42 Ethernet Controller
40 November 30, 2007
Preliminary
Interrupts
5 JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
The JTAG module has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions:
– BYPASS instruction
– IDCODE instruction
– SAMPLE/PRELOAD instruction
– EXTEST instruction
– INTEST instruction
■ ARM additional instructions:
– APACC instruction
– DPACC instruction
– ABORT instruction
■ Integrated ARM Serial Wire Debug (SWD)
See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG
controller.
November 30, 2007 41
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LM3S6110 Microcontroller
5.1 Block Diagram
Figure 5-1. JTAG Module Block Diagram
Instruction Register (IR)
TAP Controller
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TRST
TCK
TMS
TDI
TDO
Cortex-M3
Debug
Port
5.2 Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 42. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and
TMS inputs. The current state of the TAP controller depends on the current value of TRST and the
sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when
the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel
load registers. The current state of the TAP controller also determines whether the Instruction
Register (IR) chain or one of the Data Register (DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 5-2 on page 48 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 424 for JTAG timing diagrams.
42 November 30, 2007
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JTAG Interface
5.2.1 JTAG Interface Pins
The JTAG interface consists of five standard pins: TRST, TCK, TMS, TDI, and TDO. These pins and
their associated reset state are given in Table 5-1 on page 43. Detailed information on each pin
follows.
Table 5-1. JTAG Port Pins Reset State
Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value
TRST Input Enabled Disabled N/A N/A
TCK Input Enabled Disabled N/A N/A
TMS Input Enabled Disabled N/A N/A
TDI Input Enabled Disabled N/A N/A
TDO Output Enabled Disabled 2-mA driver High-Z
5.2.1.1 Test Reset Input (TRST)
The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP
controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the
Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters
the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction,
IDCODE.
By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled
on PB7/TRST; otherwise JTAG communication could be lost.
5.2.1.2 Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers
that are daisy-chained together can synchronously communicate serial test data between
components. During normal operation, TCK is driven by a free-running clock with a nominal 50%
duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK
is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction
and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no
clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down
resistors can be turned off to save internal power as long as the TCK pin is constantly being driven
by an external source.
5.2.1.3 Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered.
Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the
value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can
be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine
can be seen in its entirety in Figure 5-2 on page 45.
November 30, 2007 43
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LM3S6110 Microcontroller
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost.
5.2.1.4 Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on
the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling
edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost.
5.2.1.5 Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the
pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states.
5.2.2 JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 5-2 on page 45. The TAP controller
state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR)
or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module
to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed
information on the function of the TAP controller and the operations that occur in each state, please
refer to IEEE Standard 1149.1.
44 November 30, 2007
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JTAG Interface
Figure 5-2. Test Access Port State Machine
Test Logic Reset
Run Test Idle Select DR Scan Select IR Scan
Capture DR Capture IR
Shift DR Shift IR
Exit 1 DR Exit 1 IR
Exit 2 DR Exit 2 IR
Pause DR Pause IR
Update DR Update IR
1 1 1
1 1
1
1 1
1 1
1 1
1 1
1 0 1 0
0 0
0 0
0 0
0 0
0 0
0 0
0
0
5.2.3 Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 48.
5.2.4 Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG pins
can be programmed to be GPIOs, board configuration and reset conditions on these pins must be
considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the
method for switching between these two operational modes is described below.
November 30, 2007 45
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LM3S6110 Microcontroller
5.2.4.1 GPIO Functionality
When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting
GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate
hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and
PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging
or board-level testing, this provides five more GPIOs for use in the design.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors,
and apply RST or power-cycle the part.
In addition, it is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 147) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 157) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 158) have been set to 1.
Recovering a "Locked" Device
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug sequence that can be used to recover the device. Performing
a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset
mass erases the flash memory. The sequence to recover the device is:
1. Assert and hold the RST signal.
2. Perform the JTAG-to-SWD switch sequence.
3. Perform the SWD-to-JTAG switch sequence.
4. Perform the JTAG-to-SWD switch sequence.
5. Perform the SWD-to-JTAG switch sequence.
6. Perform the JTAG-to-SWD switch sequence.
7. Perform the SWD-to-JTAG switch sequence.
8. Perform the JTAG-to-SWD switch sequence.
9. Perform the SWD-to-JTAG switch sequence.
10. Perform the JTAG-to-SWD switch sequence.
11. Perform the SWD-to-JTAG switch sequence.
46 November 30, 2007
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JTAG Interface
12. Release the RST signal.
The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug
(SWD)” on page 47. When performing switch sequences for the purpose of recovering the debug
capabilities of the device, only steps 1 and 2 of the switch sequence need to be performed.
5.2.4.2 ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller
in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the
following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test
Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run
Test Idle, Select DR, Select IR, and Test Logic Reset states.
Stepping through this sequences of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
probability of this sequence occurring during normal operation of the TAP controller, it should not
affect normal performance of the JTAG interface.
JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in SWD mode, before sending the switch sequence, the SWD goes into the line reset
state.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to JTAG mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
November 30, 2007 47
Preliminary
LM3S6110 Microcontroller
2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C.
3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic
Reset state.
5.3 Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. This is done by enabling the five JTAG
pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register.
5.4 Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The registers
can be broken down into two main categories: Instruction Registers and Data Registers.
5.4.1 Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register
connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct
states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the
chain and updated, they are interpreted as the current instruction. The decode of the Instruction
Register bits is shown in Table 5-2 on page 48. A detailed explanation of each instruction, along
with its associated Data Register, follows.
Table 5-2. JTAG Instruction Register Commands
IR[3:0] Instruction Description
Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD
instruction onto the pads.
0000 EXTEST
Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD
instruction into the controller.
0001 INTEST
Captures the current I/O values and shifts the sampled values out of the Boundary Scan
Chain while new preload data is shifted in.
0010 SAMPLE / PRELOAD
1000 ABORT Shifts data into the ARM Debug Port Abort Register.
1010 DPACC Shifts data into and out of the ARM DP Access Register.
1011 APACC Shifts data into and out of the ARM AC Access Register.
Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE
chain and shifts it out.
1110 IDCODE
1111 BYPASS Connects TDI to TDO through a single Shift Register chain.
All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO.
5.4.1.1 EXTEST Instruction
The EXTEST instruction does not have an associated Data Register chain. The EXTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. This allows
48 November 30, 2007
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tests to be developed that drive known values out of the controller, which can be used to verify
connectivity.
5.4.1.2 INTEST Instruction
The INTEST instruction does not have an associated Data Register chain. The INTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. This allows tests
to be developed that drive known values into the controller, which can be used for testing. It is
important to note that although the RST input pin is on the Boundary Scan Data Register chain, it
is only observable.
5.4.1.3 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data
Register” on page 51 for more information.
5.4.1.4 ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. Please see the “ABORT Data Register” on page 51 for more
information.
5.4.1.5 DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. Please see “DPACC
Data Register” on page 51 for more information.
5.4.1.6 APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
Please see “APACC Data Register” on page 51 for more information.
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LM3S6110 Microcontroller
5.4.1.7 IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure their input and output data streams. IDCODE is the default instruction that is loaded into
the JTAG Instruction Register when a power-on-reset (POR) is asserted, TRST is asserted, or the
Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 50 for more
information.
5.4.1.8 BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 50 for
more information.
5.4.2 Data Registers
The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan,
APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed
in the following sections.
5.4.2.1 IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-3 on page 50. The standard requires that every JTAG-compliant device implement either
the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This allows auto configuration test tools to determine which instruction is the default instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly, and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x3BA00477. This value indicates an ARM Cortex-M3, Version 1
processor. This allows the debuggers to automatically configure themselves to work correctly with
the Cortex-M3 during debug.
Figure 5-3. IDCODE Register Format
5.4.2.2 BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-4 on page 51. The standard requires that every JTAG-compliant device implement either
the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This allows auto configuration test tools to determine which instruction is the default instruction.
50 November 30, 2007
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Figure 5-4. BYPASS Register Format
5.4.2.3 Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 51. Each GPIO
pin, in a counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data
Register. Each GPIO pin has three associated digital signals that are included in the chain. These
signals are input, output, and output enable, and are arranged in that order as can be seen in the
figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because
the reset pin is always an input, only the input signal is included in the Data Register chain.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.
Figure 5-5. Boundary Scan Register Format
O TDO TDI O IN
E UT
O O IN
U E
T
O O IN
E UT
O O IN
U E
T
I
N ... ...
GPIO PB6 GPIO m RST GPIO m+1 GPIO n
For detailed information on the order of the input, output, and output enable bits for each of the
GPIO ports, please refer to the Stellaris® Family Boundary Scan Description Language (BSDL) files,
downloadable from www.luminarymicro.com.
5.4.2.4 APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.5 DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.6 ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
November 30, 2007 51
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LM3S6110 Microcontroller
6 System Control
System control determines the overall operation of the device. It provides information about the
device, controls the clocking to the core and individual peripherals, and handles reset detection and
reporting.
6.1 Functional Description
The System Control module provides the following capabilities:
■ Device identification, see “Device Identification” on page 52
■ Local control, such as reset (see “Reset Control” on page 52), power (see “Power
Control” on page 55) and clock control (see “Clock Control” on page 55)
■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 57
6.1.1 Device Identification
Seven read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers.
6.1.2 Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
6.1.2.1 CMOD0 and CMOD1 Test-Mode Control Pins
Two pins, CMOD0 and CMOD1, are defined for use by Luminary Micro for testing the devices during
manufacture. They have no end-user function and should not be used. The CMOD pins should be
connected to ground.
6.1.2.2 Reset Sources
The controller has five sources of reset:
1. External reset input pin (RST) assertion, see “RST Pin Assertion” on page 52.
2. Power-on reset (POR), see “Power-On Reset (POR)” on page 53.
3. Internal brown-out (BOR) detector, see “Brown-Out Reset (BOR)” on page 53.
4. Software-initiated reset (with the software reset registers), see “Software Reset” on page 54.
5. A watchdog timer reset condition violation, see “Watchdog Timer Reset” on page 54.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator.
6.1.2.3 RST Pin Assertion
The external reset pin (RST) resets the controller. This resets the core and all the peripherals except
the JTAG TAP controller (see “JTAG Interface” on page 41). The external reset sequence is as
follows:
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1. The external reset pin (RST) is asserted and then de-asserted.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
A few clocks cycles from RST de-assertion to the start of the reset sequence is necessary for
synchronization.
The external reset timing is shown in Figure 19-9 on page 426.
6.1.2.4 Power-On Reset (POR)
The Power-On Reset (POR) circuit monitors the power supply voltage (VDD). The POR circuit
generates a reset signal to the internal logic when the power supply ramp reaches a threshold value
(VTH). If the application only uses the POR circuit, the RST input needs to be connected to the power
supply (VDD) through a pull-up resistor (1K to 10K Ω).
The device must be operating within the specified operating parameters at the point when the on-chip
power-on reset pulse is complete. The 3.3-V power supply to the device must reach 3.0 V within
10 msec of it crossing 2.0 V to guarantee proper operation. For applications that require the use of
an external reset to hold the device in reset longer than the internal POR, the RST input may be
used with the circuit as shown in Figure 6-1 on page 53.
Figure 6-1. External Circuitry to Extend Reset
R1
C1
R2
RST
Stellaris
D1
The R1 and C1 components define the power-on delay. The R2 resistor mitigates any leakage from
the RST input. The diode (D1) discharges C1 rapidly when the power supply is turned off.
The Power-On Reset sequence is as follows:
1. The controller waits for the later of external reset (RST) or internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing
is shown in Figure 19-10 on page 427.
Note: The power-on reset also resets the JTAG controller. An external reset does not.
6.1.2.5 Brown-Out Reset (BOR)
A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops
below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may
generate a controller interrupt or a system reset.
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LM3S6110 Microcontroller
Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset.
The brown-out reset is equivelent to an assertion of the external RST input and the reset is held
active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt
handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to
determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 19-11 on page 427.
6.1.2.6 Software Reset
Software can reset a specific peripheral or generate a reset to the entire system .
Peripherals can be individually reset by software via three registers that control reset signals to each
peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and
subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with
the encoding of the clock gating control for peripherals and on-chip functions (see “System
Control” on page 57). Note that all reset signals for all clocks of the specified unit are asserted as
a result of a software-initiated reset.
The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is deasserted and the controller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
The software-initiated system reset timing is shown in Figure 19-12 on page 427.
6.1.2.7 Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts
down to its zero state again before the first time-out interrupt is cleared, and the reset signal has
been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset
sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the controller loads from memory the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
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The watchdog reset timing is shown in Figure 19-13 on page 427.
6.1.3 Power Control
The Stellaris® microcontroller provides an integrated LDO regulator that may be used to provide
power to the majority of the controller's internal logic. The LDO regulator provides software a
mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V
to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ
field in the LDO Power Control (LDOPCTL) register.
Note: The use of the LDO is optional. The internal logic may be supplied by the on-chip LDO or
by an external regulator. If the LDO is used, the LDO output pin is connected to the VDD25
pins on the printed circuit board. The LDO requires decoupling capacitors on the printed
circuit board. If an external regulator is used, it is strongly recommended that the external
regulator supply the controller only and not be shared with other devices on the printed
circuit board.
6.1.4 Clock Control
System control determines the control of clocks in this part.
6.1.4.1 Fundamental Clock Sources
There are four clock sources for use in the device:
■ Internal Oscillator (IOSC): The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
Applications that do not depend on accurate clock sources may use this clock source to reduce
system cost. The internal oscillator is the clock source the device uses during and following POR.
If the main oscillator is required, software must enable the main oscillator following reset and
allow the main oscillator to stabilize before changing the clock reference.
■ Main Oscillator: The main oscillator provides a frequency-accurate clock source by one of two
means: an external single-ended clock source is connected to the OSC0 input pin, or an external
crystal is connected across the OSC0 input and OSC1 output pins. The crystal value allowed
depends on whether the main oscillator is used as the clock reference source to the PLL. If so,
the crystal must be one of the supported frequencies between 3.579545 MHz through 8.192
MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC
through the specified speed of the device. The supported crystals are listed in the XTAL bit in
the RCC register (see page 68).
■ Internal 30-kHz Oscillator: The internal 30-kHz oscillator is similar to the internal oscillator,
except that it provides an operational frequency of 30 kHz ± 30%. It is intended for use during
Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal
switching and also allows the main oscillator to be powered down.
The internal system clock (sysclk), is derived from any of the four sources plus two others: the output
of the internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The frequency of the
PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive).
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
November 30, 2007 55
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LM3S6110 Microcontroller
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options.
6.1.4.2 Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise,
the range of supported crystals is 1 to 8.192 MHz.
The XTAL bit in the RCC register (see page 68) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
6.1.4.3 PLL Frequency Configuration
The PLL is disabled by default during power-on reset and is enabled later by software if required.
Software configures the PLL input reference clock source, specifies the output divisor to set the
system clock frequency, and enables the PLL to drive the output.
If the main oscillator provides the clock reference to the PLL, the translation provided by hardware
and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG)
register (see page 72). The internal translation provides a translation within ± 1% of the targeted
PLL VCO frequency.
The Crystal Value field (XTAL) on page 68 describes the available crystal choices and default
programming of the PLLCFG register. The crystal number is written into the XTAL field of the
Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings
are translated and the internal PLL settings are updated.
6.1.4.4 PLL Modes
The PLL has two modes of operation: Normal and Power-Down
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 68 and page 73).
6.1.4.5 PLL Operation
If the PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
19-6 on page 418). During this time, the PLL is not usable as a clock reference.
The PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■ Change in the PLL from Power-Down to Normal mode.
A counter is defined to measure the TREADY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is set
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). . Hardware is provided to
keep the PLL from being used as a system clock until the TREADY condition is met after one of the
56 November 30, 2007
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System Control
two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator)
before the RCC/RCC2 register is switched to use the PLL.
6.1.5 System Control
For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep
mode, respectively.
In Run mode, the processor executes code. In Sleep mode, the clock frequency of the active
peripherals is unchanged, but the processor is not clocked and therefore no longer executes code.
In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the
Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns
the device to Run mode from one of the sleep modes; the sleep modes are entered on request from
the code. Each mode is described in more detail below.
There are four levels of operation for the device defined as:
■ Run Mode. Run mode provides normal operation of the processor and all of the peripherals that
are currently enabled by the RCGCn registers. The system clock can be any of the available
clock sources including the PLL.
■ Sleep Mode. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for
Interrupt) instruction. Any properly configured interrupt event in the system will bring the
processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3
Technical Reference Manual for more details.
In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked.
Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
■ Deep-Sleep Mode. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in
the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any
properly configured interrupt event in the system will bring the processor back into Run mode.
See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual
for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up,
if necessary, and the main oscillator is powered down. If the PLL is running at the time of the
WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active
RCC/RCC2 register to be /16 or /64, respectively. When the Deep-Sleep exit event occurs,
hardware brings the system clock back to the source and frequency it had at the onset of
Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep
duration.
6.2 Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
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LM3S6110 Microcontroller
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source (using the
main oscillator or internal oscillator) and allows for the new PLL configuration to be validated
before switching the system clock to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
6.3 Register Map
Table 6-1 on page 58 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use by Luminary Micro, Inc. Software should not modify any reserved memory
address.
Table 6-1. System Control Register Map
See
Offset Name Type Reset Description page
0x000 DID0 RO - Device Identification 0 60
0x004 DID1 RO - Device Identification 1 76
0x008 DC0 RO 0x003F.001F Device Capabilities 0 78
0x010 DC1 RO 0x0010.709F Device Capabilities 1 79
0x014 DC2 RO 0x0707.0011 Device Capabilities 2 81
0x018 DC3 RO 0x0F00.B7C3 Device Capabilities 3 83
0x01C DC4 RO 0x5000.007F Device Capabilities 4 85
0x030 PBORCTL R/W 0x0000.7FFD Brown-Out Reset Control 62
0x034 LDOPCTL R/W 0x0000.0000 LDO Power Control 63
0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 102
0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 103
0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 105
0x050 RIS RO 0x0000.0000 Raw Interrupt Status 64
0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 65
0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 66
0x05C RESC R/W - Reset Cause 67
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See
Offset Name Type Reset Description page
0x060 RCC R/W 0x07AE.3AD1 Run-Mode Clock Configuration 68
0x064 PLLCFG RO - XTAL to PLL Translation 72
0x070 RCC2 R/W 0x0780.2800 Run-Mode Clock Configuration 2 73
0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 87
0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 90
0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 96
0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 88
0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 92
0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 98
0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 89
0x124 DCGC1 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 94
0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 100
0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 75
6.4 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
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LM3S6110 Microcontroller
Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the device.
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved VER reserved CLASS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJOR MINOR
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows:
Value Description
First revision of the DID0 register format, for Stellaris®
Fury-class devices .
0x1
30:28 VER RO 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:24 reserved RO 0x0
Device Class
The CLASS field value identifies the internal design from which all mask
sets are generated for all devices in a particular product line. The CLASS
field value is changed for new product lines, for changes in fab process
(for example, a remap or shrink), or any case where the MAJOR or MINOR
fields require differentiation from prior devices. The value of the CLASS
field is encoded as follows (all other encodings are reserved):
Value Description
0x0 Stellaris® Sandstorm-class devices.
0x1 Stellaris® Fury-class devices.
23:16 CLASS RO 0x1
60 November 30, 2007
Preliminary
System Control
Bit/Field Name Type Reset Description
Major Revision
This field specifies the major revision number of the device. The major
revision reflects changes to base layers of the design. The major revision
number is indicated in the part number as a letter (A for first revision, B
for second, and so on). This field is encoded as follows:
Value Description
0x0 Revision A (initial device)
0x1 Revision B (first base layer revision)
0x2 Revision C (second base layer revision)
and so on.
15:8 MAJOR RO -
Minor Revision
This field specifies the minor revision number of the device. The minor
revision reflects changes to the metal layers of the design. The MINOR
field value is reset when the MAJOR field is changed. This field is numeric
and is encoded as follows:
Value Description
0x0 Initial device, or a major revision update.
0x1 First metal layer change.
0x2 Second metal layer change.
and so on.
7:0 MINOR RO -
November 30, 2007 61
Preliminary
LM3S6110 Microcontroller
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BORIOR reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x0
BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the controller. If set, a
reset is signaled. Otherwise, an interrupt is signaled.
1 BORIOR R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
62 November 30, 2007
Preliminary
System Control
Register 3: LDO Power Control (LDOPCTL), offset 0x034
The VADJ field in this register adjusts the on-chip output voltage (VOUT).
LDO Power Control (LDOPCTL)
Base 0x400F.E000
Offset 0x034
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved VADJ
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0
LDO Output Voltage
This field sets the on-chip output voltage. The programming values for
the VADJ field are provided below.
Value VOUT (V)
0x00 2.50
0x01 2.45
0x02 2.40
0x03 2.35
0x04 2.30
0x05 2.25
0x06-0x3F Reserved
0x1B 2.75
0x1C 2.70
0x1D 2.65
0x1E 2.60
0x1F 2.55
5:0 VADJ R/W 0x0
November 30, 2007 63
Preliminary
LM3S6110 Microcontroller
Register 4: Raw Interrupt Status (RIS), offset 0x050
Central location for system control raw interrupts. These are set and cleared by hardware.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLRIS reserved BORRIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Raw Interrupt Status
This bit is set when the PLL TREADY Timer asserts.
6 PLLLRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
Brown-Out Reset Raw Interrupt Status
This bit is the raw interrupt status for any brown-out conditions. If set,
a brown-out condition is currently active. This is an unregistered signal
from the brown-out detection circuit. An interrupt is reported if the BORIM
bit in the IMC register is set and the BORIOR bit in the PBORCTL register
is cleared.
1 BORRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
64 November 30, 2007
Preliminary
System Control
Register 5: Interrupt Mask Control (IMC), offset 0x054
Central location for system control interrupt masks.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLIM reserved BORIM reserved
Type RO RO RO RO RO RO RO RO RO R/W RO RO RO RO R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Interrupt Mask
This bit specifies whether a current limit detection is promoted to a
controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS
is set; otherwise, an interrupt is not generated.
6 PLLLIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
Brown-Out Reset Interrupt Mask
This bit specifies whether a brown-out condition is promoted to a
controller interrupt. If set, an interrupt is generated if BORRIS is set;
otherwise, an interrupt is not generated.
1 BORIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
November 30, 2007 65
Preliminary
LM3S6110 Microcontroller
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
Central location for system control result of RIS AND IMC to generate an interrupt to the controller.
All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS
register (see page 64).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PLLLMIS reserved BORMIS reserved
Type RO RO RO RO RO RO RO RO RO R/W1C RO RO RO RO R/W1C RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0
PLL Lock Masked Interrupt Status
This bit is set when the PLL TREADY timer asserts. The interrupt is cleared
by writing a 1 to this bit.
6 PLLLMIS R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
BOR Masked Interrupt Status
The BORMIS is simply the BORRIS ANDed with the mask value, BORIM.
1 BORMIS R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
66 November 30, 2007
Preliminary
System Control
Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an external reset is the cause, and then
all the other bits in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved LDO SW WDT BOR POR EXT
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0
LDO Reset
When set, indicates the LDO circuit has lost regulation and has
generated a reset event.
5 LDO R/W -
Software Reset
When set, indicates a software reset is the cause of the reset event.
4 SW R/W -
Watchdog Timer Reset
When set, indicates a watchdog reset is the cause of the reset event.
3 WDT R/W -
Brown-Out Reset
When set, indicates a brown-out reset is the cause of the reset event.
2 BOR R/W -
Power-On Reset
When set, indicates a power-on reset is the cause of the reset event.
1 POR R/W -
External Reset
When set, indicates an external reset (RST assertion) is the cause of
the reset event.
0 EXT R/W -
November 30, 2007 67
Preliminary
LM3S6110 Microcontroller
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x07AE.3AD1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved ACG SYSDIV USESYSDIV reserved USEPWMDIV PWMDIV reserved
Type RO RO RO RO R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWRDN reserved BYPASS reserved XTAL OSCSRC reserved IOSCDIS MOSCDIS
Type RO RO R/W RO R/W RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W
Reset 0 0 1 1 1 0 1 0 1 1 0 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:28 reserved RO 0x0
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.
27 ACG R/W 0
68 November 30, 2007
Preliminary
System Control
Bit/Field Name Type Reset Description
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
Value Divisor (BYPASS=1) Frequency (BYPASS=0)
0x0 reserved reserved
0x1 /2 reserved
0x2 /3 reserved
0x3 /4 reserved
0x4 /5 reserved
0x5 /6 reserved
0x6 /7 reserved
0x7 /8 25 MHz
0x8 /9 22.22 MHz
0x9 /10 20 MHz
0xA /11 18.18 MHz
0xB /12 16.67 MHz
0xC /13 15.38 MHz
0xD /14 14.29 MHz
0xE /15 13.33 MHz
0xF /16 12.5 MHz (default)
When reading the Run-Mode Clock Configuration (RCC) register (see
page 68), the SYSDIV value is MINSYSDIV if a lower divider was
requested and the PLL is being used. This lower value is allowed to
divide a non-PLL source.
26:23 SYSDIV R/W 0xF
Enable System Clock Divider
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
22 USESYSDIV R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
21 reserved RO 0
Enable PWM Clock Divisor
Use the PWM clock divider as the source for the PWM clock.
20 USEPWMDIV R/W 0
November 30, 2007 69
Preliminary
LM3S6110 Microcontroller
Bit/Field Name Type Reset Description
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. This clock
is only power 2 divide and rising edge is synchronous without phase
shift from the system clock.
Value Divisor
0x0 /2
0x1 /4
0x2 /8
0x3 /16
0x4 /32
0x5 /64
0x6 /64
0x7 /64 (default)
19:17 PWMDIV R/W 0x7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16:14 reserved RO 0
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
13 PWRDN R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12 reserved RO 1
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
11 BYPASS R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10 reserved RO 0
70 November 30, 2007
Preliminary
System Control
Bit/Field Name Type Reset Description
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below.
Crystal Frequency (MHz)
Using the PLL
Crystal Frequency (MHz)
Not Using the PLL
Value
0x0 1.000 reserved
0x1 1.8432 reserved
0x2 2.000 reserved
0x3 2.4576 reserved
0x4 3.579545 MHz
0x5 3.6864 MHz
0x6 4 MHz
0x7 4.096 MHz
0x8 4.9152 MHz
0x9 5 MHz
0xA 5.12 MHz
0xB 6 MHz (reset value)
0xC 6.144 MHz
0xD 7.3728 MHz
0xE 8 MHz
0xF 8.192 MHz
9:6 XTAL R/W 0xB
Oscillator Source
Picks among the four input sources for the OSC. The values are:
Value Input Source
0x0 Main oscillator (default)
0x1 Internal oscillator (default)
0x2 Internal oscillator / 4 (this is necessary if used as input to PLL)
0x3 reserved
5:4 OSCSRC R/W 0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0x0
Internal Oscillator Disable
0: Internal oscillator (IOSC) is enabled.
1: Internal oscillator is disabled.
1 IOSCDIS R/W 0
Main Oscillator Disable
0: Main oscillator is enabled.
1: Main oscillator is disabled (default).
0 MOSCDIS R/W 1
November 30, 2007 71
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LM3S6110 Microcontroller
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 68).
The PLL frequency is calculated using the PLLCFG field values, as follows:
PLLFreq = OSCFreq * F / (R + 1)
XTAL to PLL Translation (PLLCFG)
Base 0x400F.E000
Offset 0x064
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved F R
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:14 reserved RO 0x0
PLL F Value
This field specifies the value supplied to the PLL’s F input.
13:5 F RO -
PLL R Value
This field specifies the value supplied to the PLL’s R input.
4:0 R RO -
72 November 30, 2007
Preliminary
System Control
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields when the USERCC2 bit is set. This allows
RCC2 to be used to extend the capabilities, while also providing a means to be backward-compatible
to previous parts. The fields within the RCC2 register occupy the same bit positions as they do
within the RCC register as LSB-justified.
The SYSDIV2 field is wider so that additional larger divisors are possible. This allows a lower system
clock frequency for improved Deep Sleep power consumption.
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x0780.2800
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USERCC2 reserved SYSDIV2 reserved
Type R/W RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWRDN2 reserved BYPASS2 reserved OSCSRC2 reserved
Type RO RO R/W RO R/W RO RO RO RO R/W R/W R/W RO RO RO RO
Reset 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Use RCC2
When set, overrides the RCC register fields.
31 USERCC2 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30:29 reserved RO 0x0
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
This field is wider than the RCC register SYSDIV field in order to provide
additional divisor values. This permits the system clock to be run at
much lower frequencies during Deep Sleep mode. For example, where
the RCC register SYSDIV encoding of 1111 provides /16, the RCC2
register SYSDIV2 encoding of 111111 provides /64.
28:23 SYSDIV2 R/W 0x0F
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:14 reserved RO 0x0
Power-Down PLL
When set, powers down the PLL.
13 PWRDN2 R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12 reserved RO 0
Bypass PLL
When set, bypasses the PLL for the clock source.
11 BYPASS2 R/W 1
November 30, 2007 73
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LM3S6110 Microcontroller
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10:7 reserved RO 0x0
System Clock Source
Value Description
0x0 Main oscillator (MOSC)
0x1 Internal oscillator (IOSC)
0x2 Internal oscillator / 4
0x3 30 kHz internal oscillator
0x7 32 kHz external oscillator
6:4 OSCSRC2 R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0
74 November 30, 2007
Preliminary
System Control
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved DSDIVORIDE reserved
Type RO RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DSOSCSRC reserved
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:29 reserved RO 0x0
Divider Field Override
6-bit system divider field to override when Deep-Sleep occurs with PLL
running.
28:23 DSDIVORIDE R/W 0x0F
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22:7 reserved RO 0x0
Clock Source
When set, forces IOSC to be clock source during Deep Sleep mode.
Value Name Description
0x0 NOORIDE No override to the oscillator clock source is done
0x1 IOSC Use internal 12 MHz oscillator as source
0x3 30kHz Use 30 kHz internal oscillator
0x7 32kHz Use 32 kHz external oscillator
6:4 DSOSCSRC R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0x0
November 30, 2007 75
Preliminary
LM3S6110 Microcontroller
Register 12: Device Identification 1 (DID1), offset 0x004
This register identifies the device family, part number, temperature range, pin count, and package
type.
Device Identification 1 (DID1)
Base 0x400F.E000
Offset 0x004
Type RO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VER FAM PARTNO
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 1 0 0 0 0 0 1 1 1 0 1 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOUNT reserved TEMP PKG ROHS QUAL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 0 0 0 0 0 0 0 1 0 1 1 - -
Bit/Field Name Type Reset Description
DID1 Version
This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Value Description
First revision of the DID1 register format, indicating a Stellaris
Fury-class device.
0x1
31:28 VER RO 0x1
Family
This field provides the family identification of the device within the
Luminary Micro product portfolio. The value is encoded as follows (all
other encodings are reserved):
Value Description
Stellaris family of microcontollers, that is, all devices with
external part numbers starting with LM3S.
0x0
27:24 FAM RO 0x0
Part Number
This field provides the part number of the device within the family. The
value is encoded as follows (all other encodings are reserved):
Value Description
0x74 LM3S6110
23:16 PARTNO RO 0x74
Package Pin Count
This field specifies the number of pins on the device package. The value
is encoded as follows (all other encodings are reserved):
Value Description
0x2 100-pin package
15:13 PINCOUNT RO 0x2
76 November 30, 2007
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System Control
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12:8 reserved RO 0
Temperature Range
This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x1 Industrial temperature range (-40°C to 85°C)
7:5 TEMP RO 0x1
Package Type
This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):
Value Description
0x1 LQFP package
4:3 PKG RO 0x1
RoHS-Compliance
This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.
2 ROHS RO 1
Qualification Status
This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x0 Engineering Sample (unqualified)
0x1 Pilot Production (unqualified)
0x2 Fully Qualified
1:0 QUAL RO -
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Register 13: Device Capabilities 0 (DC0), offset 0x008
This register is predefined by the part and can be used to verify features.
Device Capabilities 0 (DC0)
Base 0x400F.E000
Offset 0x008
Type RO, reset 0x003F.001F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRAMSZ
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASHSZ
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
Bit/Field Name Type Reset Description
SRAM Size
Indicates the size of the on-chip SRAM memory.
Value Description
0x003F 16 KB of SRAM
31:16 SRAMSZ RO 0x003F
Flash Size
Indicates the size of the on-chip flash memory.
Value Description
0x001F 64 KB of Flash
15:0 FLASHSZ RO 0x001F
78 November 30, 2007
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System Control
Register 14: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: CANs, PWM,
ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the
maximum clock frequency and maximum ADC sample rate. The format of this register is consistent
with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control
register.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0010.709F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved PWM reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MINSYSDIV reserved MPU reserved PLL WDT SWO SWD JTAG
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 1 1 0 0 0 0 1 0 0 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:21 reserved RO 0
PWM Module Present
When set, indicates that the PWM module is present.
20 PWM RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:16 reserved RO 0
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
0x7 Specifies a 25-MHz clock with a PLL divider of 8.
15:12 MINSYSDIV RO 0x7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:8 reserved RO 0
MPU Present
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the ARM Cortex-M3 Technical Reference Manual
for details on the MPU.
7 MPU RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:5 reserved RO 0
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Bit/Field Name Type Reset Description
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
4 PLL RO 1
Watchdog Timer Present
When set, indicates that a watchdog timer is present.
3 WDT RO 1
SWO Trace Port Present
When set, indicates that the Serial Wire Output (SWO) trace port is
present.
2 SWO RO 1
SWD Present
When set, indicates that the Serial Wire Debugger (SWD) is present.
1 SWD RO 1
JTAG Present
When set, indicates that the JTAG debugger interface is present.
0 JTAG RO 1
80 November 30, 2007
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System Control
Register 15: Device Capabilities 2 (DC2), offset 0x014
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register
is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software
reset control register.
Device Capabilities 2 (DC2)
Base 0x400F.E000
Offset 0x014
Type RO, reset 0x0707.0011
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SSI0 reserved UART0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Present
When set, indicates that analog comparator 2 is present.
26 COMP2 RO 1
Analog Comparator 1 Present
When set, indicates that analog comparator 1 is present.
25 COMP1 RO 1
Analog Comparator 0 Present
When set, indicates that analog comparator 0 is present.
24 COMP0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
Timer 2 Present
When set, indicates that General-Purpose Timer module 2 is present.
18 TIMER2 RO 1
Timer 1 Present
When set, indicates that General-Purpose Timer module 1 is present.
17 TIMER1 RO 1
Timer 0 Present
When set, indicates that General-Purpose Timer module 0 is present.
16 TIMER0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:5 reserved RO 0
SSI0 Present
When set, indicates that SSI module 0 is present.
4 SSI0 RO 1
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:1 reserved RO 0
UART0 Present
When set, indicates that UART module 0 is present.
0 UART0 RO 1
82 November 30, 2007
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System Control
Register 16: Device Capabilities 3 (DC3), offset 0x018
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os.
Device Capabilities 3 (DC3)
Base 0x400F.E000
Offset 0x018
Type RO, reset 0x0F00.B7C3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved CCP3 CCP2 CCP1 CCP0 reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWMFAULT reserved C2PLUS C2MINUS reserved C1PLUS C1MINUS C0O C0PLUS C0MINUS reserved PWM1 PWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 0 1 1 0 1 1 1 1 1 0 0 0 0 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:28 reserved RO 0
CCP3 Pin Present
When set, indicates that Capture/Compare/PWM pin 3 is present.
27 CCP3 RO 1
CCP2 Pin Present
When set, indicates that Capture/Compare/PWM pin 2 is present.
26 CCP2 RO 1
CCP1 Pin Present
When set, indicates that Capture/Compare/PWM pin 1 is present.
25 CCP1 RO 1
CCP0 Pin Present
When set, indicates that Capture/Compare/PWM pin 0 is present.
24 CCP0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:16 reserved RO 0
PWM Fault Pin Present
When set, indicates that the PWM Fault pin is present.
15 PWMFAULT RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14 reserved RO 0
C2+ Pin Present
When set, indicates that the analog comparator 2 (+) input pin is present.
13 C2PLUS RO 1
C2- Pin Present
When set, indicates that the analog comparator 2 (-) input pin is present.
12 C2MINUS RO 1
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Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11 reserved RO 0
C1+ Pin Present
When set, indicates that the analog comparator 1 (+) input pin is present.
10 C1PLUS RO 1
C1- Pin Present
When set, indicates that the analog comparator 1 (-) input pin is present.
9 C1MINUS RO 1
C0o Pin Present
When set, indicates that the analog comparator 0 output pin is present.
8 C0O RO 1
C0+ Pin Present
When set, indicates that the analog comparator 0 (+) input pin is present.
7 C0PLUS RO 1
C0- Pin Present
When set, indicates that the analog comparator 0 (-) input pin is present.
6 C0MINUS RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:2 reserved RO 0
PWM1 Pin Present
When set, indicates that the PWM pin 1 is present.
1 PWM1 RO 1
PWM0 Pin Present
When set, indicates that the PWM pin 0 is present.
0 PWM0 RO 1
84 November 30, 2007
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System Control
Register 17: Device Capabilities 4 (DC4), offset 0x01C
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Ethernet MAC
and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2,
and DCGC2 clock control registers and the SRCR2 software reset control register.
Device Capabilities 4 (DC4)
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x5000.007F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
Ethernet PHY0 Present
When set, indicates that Ethernet PHY module 0 is present.
30 EPHY0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
Ethernet MAC0 Present
When set, indicates that Ethernet MAC module 0 is present.
28 EMAC0 RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
GPIO Port G Present
When set, indicates that GPIO Port G is present.
6 GPIOG RO 1
GPIO Port F Present
When set, indicates that GPIO Port F is present.
5 GPIOF RO 1
GPIO Port E Present
When set, indicates that GPIO Port E is present.
4 GPIOE RO 1
GPIO Port D Present
When set, indicates that GPIO Port D is present.
3 GPIOD RO 1
GPIO Port C Present
When set, indicates that GPIO Port C is present.
2 GPIOC RO 1
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Bit/Field Name Type Reset Description
GPIO Port B Present
When set, indicates that GPIO Port B is present.
1 GPIOB RO 1
GPIO Port A Present
When set, indicates that GPIO Port A is present.
0 GPIOA RO 1
86 November 30, 2007
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System Control
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 0 (RCGC0)
Base 0x400F.E000
Offset 0x100
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved PWM reserved
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WDT reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:21 reserved RO 0
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:4 reserved RO 0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved PWM reserved
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WDT reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:21 reserved RO 0
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:4 reserved RO 0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
88 November 30, 2007
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System Control
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
Type R/W, reset 0x00000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved PWM reserved
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WDT reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:21 reserved RO 0
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:4 reserved RO 0
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 1 (RCGC1)
Base 0x400F.E000
Offset 0x104
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SSI0 reserved UART0
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
26 COMP2 R/W 0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
25 COMP1 R/W 0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
90 November 30, 2007
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Bit/Field Name Type Reset Description
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18 TIMER2 R/W 0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17 TIMER1 R/W 0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:5 reserved RO 0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:1 reserved RO 0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0 UART0 R/W 0
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Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 1 (SCGC1)
Base 0x400F.E000
Offset 0x114
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SSI0 reserved UART0
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
26 COMP2 R/W 0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
25 COMP1 R/W 0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
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System Control
Bit/Field Name Type Reset Description
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18 TIMER2 R/W 0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17 TIMER1 R/W 0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:5 reserved RO 0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:1 reserved RO 0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0 UART0 R/W 0
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Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SSI0 reserved UART0
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
26 COMP2 R/W 0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
25 COMP1 R/W 0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
94 November 30, 2007
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System Control
Bit/Field Name Type Reset Description
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18 TIMER2 R/W 0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17 TIMER1 R/W 0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:5 reserved RO 0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:1 reserved RO 0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0 UART0 R/W 0
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Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 2 (RCGC2)
Base 0x400F.E000
Offset 0x108
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
6 GPIOG R/W 0
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System Control
Bit/Field Name Type Reset Description
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 GPIOF R/W 0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 GPIOE R/W 0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3 GPIOD R/W 0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 GPIOC R/W 0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 GPIOB R/W 0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0 GPIOA R/W 0
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Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset
0x118
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 2 (SCGC2)
Base 0x400F.E000
Offset 0x118
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
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System Control
Bit/Field Name Type Reset Description
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
6 GPIOG R/W 0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 GPIOF R/W 0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 GPIOE R/W 0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3 GPIOD R/W 0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 GPIOC R/W 0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 GPIOB R/W 0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0 GPIOA R/W 0
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Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
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System Control
Bit/Field Name Type Reset Description
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
6 GPIOG R/W 0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5 GPIOF R/W 0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4 GPIOE R/W 0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3 GPIOD R/W 0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 GPIOC R/W 0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 GPIOB R/W 0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0 GPIOA R/W 0
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Register 27: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved PWM reserved
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WDT reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:21 reserved RO 0
PWM Reset Control
Reset control for PWM module.
20 PWM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:4 reserved RO 0
WDT Reset Control
Reset control for Watchdog unit.
3 WDT R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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System Control
Register 28: Software Reset Control 1 (SRCR1), offset 0x044
Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved COMP2 COMP1 COMP0 reserved TIMER2 TIMER1 TIMER0
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SSI0 reserved UART0
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:27 reserved RO 0
Analog Comp 2 Reset Control
Reset control for analog comparator 2.
26 COMP2 R/W 0
Analog Comp 1 Reset Control
Reset control for analog comparator 1.
25 COMP1 R/W 0
Analog Comp 0 Reset Control
Reset control for analog comparator 0.
24 COMP0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:19 reserved RO 0
Timer 2 Reset Control
Reset control for General-Purpose Timer module 2.
18 TIMER2 R/W 0
Timer 1 Reset Control
Reset control for General-Purpose Timer module 1.
17 TIMER1 R/W 0
Timer 0 Reset Control
Reset control for General-Purpose Timer module 0.
16 TIMER0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:5 reserved RO 0
SSI0 Reset Control
Reset control for SSI unit 0.
4 SSI0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:1 reserved RO 0
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Bit/Field Name Type Reset Description
UART0 Reset Control
Reset control for UART unit 0.
0 UART0 R/W 0
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Register 29: Software Reset Control 2 (SRCR2), offset 0x048
Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register.
Software Reset Control 2 (SRCR2)
Base 0x400F.E000
Offset 0x048
Type R/W, reset 0x00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved EPHY0 reserved EMAC0 reserved
Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31 reserved RO 0
PHY0 Reset Control
Reset control for Ethernet PHY unit 0.
30 EPHY0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29 reserved RO 0
MAC0 Reset Control
Reset control for Ethernet MAC unit 0.
28 EMAC0 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27:7 reserved RO 0
Port G Reset Control
Reset control for GPIO Port G.
6 GPIOG R/W 0
Port F Reset Control
Reset control for GPIO Port F.
5 GPIOF R/W 0
Port E Reset Control
Reset control for GPIO Port E.
4 GPIOE R/W 0
Port D Reset Control
Reset control for GPIO Port D.
3 GPIOD R/W 0
Port C Reset Control
Reset control for GPIO Port C.
2 GPIOC R/W 0
Port B Reset Control
Reset control for GPIO Port B.
1 GPIOB R/W 0
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Bit/Field Name Type Reset Description
Port A Reset Control
Reset control for GPIO Port A.
0 GPIOA R/W 0
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System Control
7 Internal Memory
The LM3S6110 microcontroller comes with 16 KB of bit-banded SRAM and 64 KB of flash memory.
The flash controller provides a user-friendly interface, making flash programming a simple task.
Flash protection can be applied to the flash memory on a 2-KB block basis.
7.1 Block Diagram
Figure 7-1. Flash Block Diagram
Flash Control
FMA
FCMISC
FCIM
FCRIS
FMC
FMD
Flash Timing
USECRL
Flash Protection
FMPREn
FMPPEn
Flash Array
SRAM Array
Bridge
Cortex-M3
ICode
DCode
System Bus
APB
User Registers
USER_REG0
USER_REG1
USER_DBG
7.2 Functional Description
This section describes the functionality of both the flash and SRAM memories.
7.2.1 SRAM Memory
The internal SRAM of the Stellaris® devices is located at address 0x2000.0000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has
introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor,
certain regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
The bit-band alias is calculated by using the formula:
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bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3
Technical Reference Manual.
7.2.2 Flash Memory
The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be
programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB
blocks that can be individually protected. The protection allows blocks to be marked as read-only
or execute-only, providing different levels of code protection. Read-only blocks cannot be erased
or programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
See also “Serial Flash Loader” on page 430 for a preprogrammed flash-resident utility used to
download code to the flash memory of a device without the use of a debug interface.
7.2.2.1 Flash Memory Timing
The timing for the flash is automatically handled by the flash controller. However, in order to do so,
it must know the clock rate of the system in order to time its internal signals properly. The number
of clock cycles per microsecond must be provided to the flash controller for it to accomplish this
timing. It is software's responsibility to keep the flash controller updated with this information via the
USec Reload (USECRL) register.
On reset, the USECRL register is loaded with a value that configures the flash timing so that it works
with the maximum clock rate of the part. If software changes the system operating frequency, the
new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash
modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value
of 0x13 (20-1) must be written to the USECRL register.
7.2.2.2 Flash Memory Protection
The user is provided two forms of flash protection per 2-KB flash blocks in one pair of 32-bit wide
registers. The protection policy for each form is controlled by individual bits (per policy per block)
in the FMPPEn and FMPREn registers.
■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed
(written) or erased. If cleared, the block may not be changed.
■ Flash Memory Protection Read Enable (FMPREn): If set, the block may be executed or read
by software or debuggers. If cleared, the block may only be executed. The contents of the memory
block are prohibited from being accessed as data and traversing the DCode bus.
The policies may be combined as shown in Table 7-1 on page 109.
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Table 7-1. Flash Protection Policy Combinations
FMPPEn FMPREn Protection
Execute-only protection. The block may only be executed and may not be written or erased. This mode
is used to protect code.
0 0
1 0 The block may be written, erased or executed, but not read. This combination is unlikely to be used.
Read-only protection. The block may be read or executed but may not be written or erased. This mode
is used to lock the block from further modification while allowing any read or execute access.
0 1
1 1 No protection. The block may be written, erased, executed or read.
An access that attempts to program or erase a PE-protected block is prohibited. A controller interrupt
may be optionally generated (by setting the AMASK bit in the FIM register) to alert software developers
of poorly behaving software during the development and debug phases.
An access that attempts to read an RE-protected block is prohibited. Such accesses return data
filled with all 0s. A controller interrupt may be optionally generated to alert software developers of
poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. This implements a policy of open access and programmability. The register bits may be
changed by writing the specific register bit. The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. Details on
programming these bits are discussed in “Nonvolatile Register Programming” on page 110.
7.3 Flash Memory Initialization and Configuration
7.3.1 Flash Programming
The Stellaris® devices provide a user-friendly interface for flash programming. All erase/program
operations are handled via three registers: FMA, FMD, and FMC.
7.3.1.1 To program a 32-bit word
1. Write source data to the FMD register.
2. Write the target address to the FMA register.
3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register.
4. Poll the FMC register until the WRITE bit is cleared.
7.3.1.2 To perform an erase of a 1-KB page
1. Write the page address to the FMA register.
2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register.
3. Poll the FMC register until the ERASE bit is cleared.
7.3.1.3 To perform a mass erase of the flash
1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register.
2. Poll the FMC register until the MERASE bit is cleared.
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7.3.2 Nonvolatile Register Programming
This section discusses how to update registers that are resident within the flash memory itself.
These registers exist in a separate space from the main flash array and are not affected by an
ERASE or MASS ERASE operation. These nonvolatile registers are updated by using the COMT bit
in the FMC register to activate a write operation. For the USER_DBG register, the data to be written
must be loaded into the FMD register before it is "committed". All other registers are R/W and can
have their operation tried before committing them to nonvolatile memory.
Important: These registers can only have bits changed from 1 to 0 by the user and there is no
mechanism for the user to erase them back to a 1 value.
In addition, the USER_REG0, USER_REG1, and USER_DBG use bit 31 (NW) of their respective
registers to indicate that they are available for user write. These three registers can only be written
once whereas the flash protection registers may be written multiple times. Table 7-2 on page 110
provides the FMA address required for commitment of each of the registers and the source of the
data to be written when the COMT bit of the FMC register is written with a value of 0xA442.0008.
After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to
complete.
Table 7-2. Flash Resident Registersa
Register to be Committed FMA Value Data Source
FMPRE0 0x0000.0000 FMPRE0
FMPRE1 0x0000.0002 FMPRE1
FMPRE2 0x0000.0004 FMPRE2
FMPRE3 0x0000.0008 FMPRE3
FMPPE0 0x0000.0001 FMPPE0
FMPPE1 0x0000.0003 FMPPE1
FMPPE2 0x0000.0005 FMPPE2
FMPPE3 0x0000.0007 FMPPE3
USER_REG0 0x8000.0000 USER_REG0
USER_REG1 0x8000.0001 USER_REG1
USER_DBG 0x7510.0000 FMD
a. Which FMPREn and FMPPEn registers are available depend on the flash size of your particular Stellaris® device.
7.4 Register Map
Table 7-3 on page 110 lists the Flash memory and control registers. The offset listed is a hexadecimal
increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers
are relative to the Flash control base address of 0x400F.D000. The FMPREn, FMPPEn, USECRL,
USER_DBG, and USER_REGn registers are relative to the System Control base address of
0x400F.E000.
Table 7-3. Flash Register Map
See
Offset Name Type Reset Description page
Flash Control Offset
0x000 FMA R/W 0x0000.0000 Flash Memory Address 112
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See
Offset Name Type Reset Description page
0x004 FMD R/W 0x0000.0000 Flash Memory Data 113
0x008 FMC R/W 0x0000.0000 Flash Memory Control 114
0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 116
0x010 FCIM R/W 0x0000.0000 Flash Controller Interrupt Mask 117
0x014 FCMISC R/W1C 0x0000.0000 Flash Controller Masked Interrupt Status and Clear 118
System Control Offset
0x130 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 120
0x200 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 120
0x134 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 121
0x400 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 121
0x140 USECRL R/W 0x16 USec Reload 119
0x1D0 USER_DBG R/W 0xFFFF.FFFE User Debug 122
0x1E0 USER_REG0 R/W 0xFFFF.FFFF User Register 0 123
0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 124
0x204 FMPRE1 R/W 0x0000.0000 Flash Memory Protection Read Enable 1 125
0x208 FMPRE2 R/W 0x0000.0000 Flash Memory Protection Read Enable 2 126
0x20C FMPRE3 R/W 0x0000.0000 Flash Memory Protection Read Enable 3 127
0x404 FMPPE1 R/W 0x0000.0000 Flash Memory Protection Program Enable 1 128
0x408 FMPPE2 R/W 0x0000.0000 Flash Memory Protection Program Enable 2 129
0x40C FMPPE3 R/W 0x0000.0000 Flash Memory Protection Program Enable 3 130
7.5 Flash Register Descriptions (Flash Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000.
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Register 1: Flash Memory Address (FMA), offset 0x000
During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations, this register contains a 1 KB-aligned address and specifies
which page is erased. Note that the alignment requirements must be met by software or the results
of the operation are unpredictable.
Flash Memory Address (FMA)
Base 0x400F.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0
Address Offset
Address offset in flash where operation is performed, except for
nonvolatile registers (see “Nonvolatile Register Programming” on page
110 for details on values for this field).
15:0 OFFSET R/W 0x0
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Register 2: Flash Memory Data (FMD), offset 0x004
This register contains the data to be written during the programming cycle or read during the read
cycle. Note that the contents of this register are undefined for a read access of an execute-only
block. This register is not used during the erase cycles.
Flash Memory Data (FMD)
Base 0x400F.D000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Data Value
Data value for write operation.
31:0 DATA R/W 0x0
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Register 3: Flash Memory Control (FMC), offset 0x008
When this register is written, the flash controller initiates the appropriate access cycle for the location
specified by the Flash Memory Address (FMA) register (see page 112). If the access is a write
access, the data contained in the Flash Memory Data (FMD) register (see page 113) is written.
This is the final register written and initiates the memory operation. There are four control bits in the
lower byte of this register that, when set, initiate the memory operation. The most used of these
register bits are the ERASE and WRITE bits.
It is a programming error to write multiple control bits and the results of such an operation are
unpredictable.
Flash Memory Control (FMC)
Base 0x400F.D000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRKEY
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved COMT MERASE ERASE WRITE
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Flash Write Key
This field contains a write key, which is used to minimize the incidence
of accidental flash writes. The value 0xA442 must be written into this
field for a write to occur. Writes to the FMC register without this WRKEY
value are ignored. A read of this field returns the value 0.
31:16 WRKEY WO 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:4 reserved RO 0x0
Commit Register Value
Commit (write) of register value to nonvolatile storage. A write of 0 has
no effect on the state of this bit.
If read, the state of the previous commit access is provided. If the
previous commit access is complete, a 0 is returned; otherwise, if the
commit access is not complete, a 1 is returned.
This can take up to 50 μs.
3 COMT R/W 0
Mass Erase Flash Memory
If this bit is set, the flash main memory of the device is all erased. A
write of 0 has no effect on the state of this bit.
If read, the state of the previous mass erase access is provided. If the
previous mass erase access is complete, a 0 is returned; otherwise, if
the previous mass erase access is not complete, a 1 is returned.
This can take up to 250 ms.
2 MERASE R/W 0
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Bit/Field Name Type Reset Description
Erase a Page of Flash Memory
If this bit is set, the page of flash main memory as specified by the
contents of FMA is erased. A write of 0 has no effect on the state of this
bit.
If read, the state of the previous erase access is provided. If the previous
erase access is complete, a 0 is returned; otherwise, if the previous
erase access is not complete, a 1 is returned.
This can take up to 25 ms.
1 ERASE R/W 0
Write a Word into Flash Memory
If this bit is set, the data stored in FMD is written into the location as
specified by the contents of FMA. A write of 0 has no effect on the state
of this bit.
If read, the state of the previous write update is provided. If the previous
write access is complete, a 0 is returned; otherwise, if the write access
is not complete, a 1 is returned.
This can take up to 50 μs.
0 WRITE R/W 0
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Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled
if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Base 0x400F.D000
Offset 0x00C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PRIS ARIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Programming Raw Interrupt Status
This bit indicates the current state of the programming cycle. If set, the
programming cycle completed; if cleared, the programming cycle has
not completed. Programming cycles are either write or erase actions
generated through the Flash Memory Control (FMC) register bits (see
page 114).
1 PRIS RO 0
Access Raw Interrupt Status
This bit indicates if the flash was improperly accessed. If set, the program
tried to access the flash counter to the policy as set in the Flash Memory
Protection Read Enable (FMPREn) and Flash Memory Protection
Program Enable (FMPPEn) registers. Otherwise, no access has tried
to improperly access the flash.
0 ARIS RO 0
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Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the flash controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PMASK AMASK
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the controller. If set, a programming-generated interrupt is promoted
to the controller. Otherwise, interrupts are recorded but suppressed from
the controller.
1 PMASK R/W 0
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
controller. If set, an access-generated interrupt is promoted to the
controller. Otherwise, interrupts are recorded but suppressed from the
controller.
0 AMASK R/W 0
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Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PMISC AMISC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Programming Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because a
programming cycle completed and was not masked. This bit is cleared
by writing a 1. The PRIS bit in the FCRIS register (see page 116) is also
cleared when the PMISC bit is cleared.
1 PMISC R/W1C 0
Access Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because an improper
access was attempted and was not masked. This bit is cleared by writing
a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC
bit is cleared.
0 AMISC R/W1C 0
7.6 Flash Register Descriptions (System Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the System Control base address of
0x400F.E000.
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Register 7: USec Reload (USECRL), offset 0x140
Note: Offset is relative to System Control base address of 0x400F.E000
This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller.
The internal flash has specific minimum and maximum requirements on the length of time the high
voltage write pulse can be applied. It is required that this register contain the operating frequency
(in MHz -1) whenever the flash is being erased or programmed. The user is required to change this
value if the clocking conditions are changed for a flash erase/program operation.
USec Reload (USECRL)
Base 0x400F.E000
Offset 0x140
Type R/W, reset 0x16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved USEC
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Microsecond Reload Value
MHz -1 of the controller clock when the flash is being erased or
programmed.
USEC should be set to 0x18 (24 MHz) whenever the flash is being erased
or programmed.
7:0 USEC R/W 0x18
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Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130
and 0x200
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 0 (FMPRE0)
Base 0x400F.D000
Offset 0x130 and 0x200
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 64 KB of flash.
31:0 READ_ENABLE R/W 0xFFFFFFFF
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Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset
0x134 and 0x400
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 0 (FMPPE0)
Base 0x400F.D000
Offset 0x134 and 0x400
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0xFFFFFFFF Enables 64 KB of flash.
31:0 PROG_ENABLE R/W 0xFFFFFFFF
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Register 10: User Debug (USER_DBG), offset 0x1D0
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides a write-once mechanism to disable external debugger access to the device
in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory
and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0
disables any external debugger access to the device permanently, starting with the next power-up
cycle of the device. The NOTWRITTEN bit (bit 31) indicates that the register is available to be written
and is controlled through hardware to ensure that the register is only written once.
User Debug (USER_DBG)
Base 0x400F.E000
Offset 0x1D0
Type R/W, reset 0xFFFF.FFFE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NW DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA DBG1 DBG0
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Bit/Field Name Type Reset Description
User Debug Not Written
Specifies that this 32-bit dword has not been written.
31 NW R/W 1
User Data
Contains the user data value. This field is initialized to all 1s and can
only be written once.
30:2 DATA R/W 0x1FFFFFFF
Debug Control 1
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
1 DBG1 R/W 1
Debug Control 0
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
0 DBG0 R/W 0
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Register 11: User Register 0 (USER_REG0), offset 0x1E0
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 0 (USER_REG0)
Base 0x400F.E000
Offset 0x1E0
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NW DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Not Written
Specifies that this 32-bit dword has not been written.
31 NW R/W 1
User Data
Contains the user data value. This field is initialized to all 1s and can
only be written once.
30:0 DATA R/W 0x7FFFFFFF
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Register 12: User Register 1 (USER_REG1), offset 0x1E4
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 1 (USER_REG1)
Base 0x400F.E000
Offset 0x1E4
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NW DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Not Written
Specifies that this 32-bit dword has not been written.
31 NW R/W 1
User Data
Contains the user data value. This field is initialized to all 1s and can
only be written once.
30:0 DATA R/W 0x7FFFFFFF
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Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 1 (FMPRE1)
Base 0x400F.E000
Offset 0x204
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0x00000000 Enables 64 KB of flash.
31:0 READ_ENABLE R/W 0x00000000
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Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 2 (FMPRE2)
Base 0x400F.E000
Offset 0x208
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0x00000000 Enables 64 KB of flash.
31:0 READ_ENABLE R/W 0x00000000
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Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 3 (FMPRE3)
Base 0x400F.E000
Offset 0x20C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READ_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0x00000000 Enables 64 KB of flash.
31:0 READ_ENABLE R/W 0x00000000
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Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset
0x404
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 1 (FMPPE1)
Base 0x400F.E000
Offset 0x404
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0x00000000 Enables 64 KB of flash.
31:0 PROG_ENABLE R/W 0x00000000
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Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset
0x408
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 2 (FMPPE2)
Base 0x400F.E000
Offset 0x408
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0x00000000 Enables 64 KB of flash.
31:0 PROG_ENABLE R/W 0x00000000
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Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset
0x40C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 3 (FMPPE3)
Base 0x400F.E000
Offset 0x40C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROG_ENABLE
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value Description
0x00000000 Enables 64 KB of flash.
31:0 PROG_ENABLE R/W 0x00000000
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8 General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, and Port G, ). The GPIO module is
FiRM-compliant and supports 8-35 programmable input/output pins, depending on the peripherals
being used.
The GPIO module has the following features:
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ 5-V-tolerant input/outputs
■ Bit masking in both read and write operations through address lines
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
8.1 Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
8-1 on page 132). The LM3S6110 microcontroller contains seven ports and thus seven of these
physical GPIO blocks.
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Figure 8-1. GPIO Port Block Diagram
Alternate Input
Alternate Output
Alternate Output Enable
Interrupt
GPIO Input
GPIO Output
GPIO Output Enable
Pad Output
Pad Output Enable
Package I/O Pin
GPIODATA
GPIODIR
Data
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
Interrupt
Control
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
Pad
Control
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
Identification Registers
GPIOAFSEL
Mode
Control
DEMUX MUX MUX
Digital
I/O Pad
Pad Input
GPIOLOCK
Commit
Control
GPIOCR
8.1.1 Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
8.1.1.1 Data Direction Operation
The GPIO Direction (GPIODIR) register (see page 139) is used to configure each individual pin as
an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and
the corresponding data register bit will capture and store the value on the GPIO port. When the data
direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit
will be driven out on the GPIO port.
8.1.1.2 Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 138) by using bits [9:2] of the address bus as a mask.
This allows software drivers to modify individual GPIO pins in a single instruction, without affecting
the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write
operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA
register covers 256 locations in the memory map.
During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA
register is altered. If it is cleared to 0, it is left unchanged.
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For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 8-2 on page 133, where u is data unchanged by the write.
Figure 8-2. GPIODATA Write Example
0 0 1 0 0 1 1 0 1 0
u u 1 u u 0 1 u
9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 1 1
7 6 5 4 3 2 1 0
GPIODATA
0xEB
0x098
ADDR[9:2]
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value.
For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-3 on page 133.
Figure 8-3. GPIODATA Read Example
0 0 1 1 0 0 0 1 0 0
0 0 1 1 0 0 0 0
9 8 7 6 5 4 3 2 1 0
1 0 1 1 1 1 1 0
7 6 5 4 3 2 1 0
Returned Value
GPIODATA
0x0C4
ADDR[9:2]
8.1.2 Interrupt Control
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source
holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:
■ GPIO Interrupt Sense (GPIOIS) register (see page 140)
■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 141)
■ GPIO Interrupt Event (GPIOIEV) register (see page 142)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 143).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 144 and page 145). As the name implies, the GPIOMIS register only shows interrupt
conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a
GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller.
Interrupts are cleared by writing a 1 to the GPIO Interrupt Clear (GPIOICR) register (see page 146).
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When programming the following interrupt control registers, the interrupts should be masked (GPIOIM
set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can
generate a spurious interrupt if the corresponding bits are enabled.
8.1.3 Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is enabled
via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 147), the pin state is
controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO
mode, where the GPIODATA register is used to read/write the corresponding pins.
8.1.4 Commit Control
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 147) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 157) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 158) have been set to 1.
8.1.5 Pad Control
The pad control registers allow for GPIO pad configuration by software based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers.
8.1.6 Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
8.2 Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 8-1 on page 134
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 8-2 on page 135 shows how a rising edge interrupt would be configured for pin
2 of a GPIO port.
Table 8-1. GPIO Pad Configuration Examples
Configuration GPIO Register Bit Valuea
AFSEL DIR ODR DEN PUR PDR DR2R DR4R DR8R SLR
Digital Input (GPIO) 0 0 0 1 ? ? X X X X
Digital Output (GPIO) 0 1 0 1 ? ? ? ? ? ?
Open Drain Input 0 0 1 1 X X X X X X
(GPIO)
Open Drain Output 0 1 1 1 X X ? ? ? ?
(GPIO)
Digital Input (Timer 1 X 0 1 ? ? X X X X
CCP)
Digital Output (PWM) 1 X 0 1 ? ? ? ? ? ?
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Configuration GPIO Register Bit Valuea
AFSEL DIR ODR DEN PUR PDR DR2R DR4R DR8R SLR
Digital Output (Timer 1 X 0 1 ? ? ? ? ? ?
PWM)
Digital Input/Output 1 X 0 1 ? ? ? ? ? ?
(SSI)
Digital Input/Output 1 X 0 1 ? ? ? ? ? ?
(UART)
Analog Input 0 0 0 0 0 0 X X X X
(Comparator)
Digital Output 1 X 0 1 ? ? ? ? ? ?
(Comparator)
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
Table 8-2. GPIO Interrupt Configuration Example
Desired Pin 2 Bit Valuea
Interrupt
Event
Trigger
Register
7 6 5 4 3 2 1 0
0=edge X X X X X 0 X X
1=level
GPIOIS
0=single X X X X X 0 X X
edge
1=both
edges
GPIOIBE
0=Low level, X X X X X 1 X X
or negative
edge
1=High level,
or positive
edge
GPIOIEV
0=masked 0 0 0 0 0 1 0 0
1=not
masked
GPIOIM
a. X=Ignored (don’t care bit)
8.3 Register Map
Table 8-3 on page 136 lists the GPIO registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that GPIO port’s base address:
■ GPIO Port A: 0x4000.4000
■ GPIO Port B: 0x4000.5000
■ GPIO Port C: 0x4000.6000
■ GPIO Port D: 0x4000.7000
■ GPIO Port E: 0x4002.4000
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■ GPIO Port F: 0x4002.5000
■ GPIO Port G: 0x4002.6000
Important: The GPIO registers in this chapter are duplicated in each GPIO block, however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to those unconnected bits has no effect and reading those unconnected
bits returns no meaningful data.
Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are
0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and
PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default
reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
The default register type for the GPIOCR register is RO for all GPIO pins, with the exception
of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because of this, the register type for
GPIO Port B7 and GPIO Port C[3:0] is R/W.
The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the
exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port
is not accidentally programmed as a GPIO, these five pins default to non-commitable.
Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while
the default reset value of GPIOCR for Port C is 0x0000.00F0.
Table 8-3. GPIO Register Map
See
Offset Name Type Reset Description page
0x000 GPIODATA R/W 0x0000.0000 GPIO Data 138
0x400 GPIODIR R/W 0x0000.0000 GPIO Direction 139
0x404 GPIOIS R/W 0x0000.0000 GPIO Interrupt Sense 140
0x408 GPIOIBE R/W 0x0000.0000 GPIO Interrupt Both Edges 141
0x40C GPIOIEV R/W 0x0000.0000 GPIO Interrupt Event 142
0x410 GPIOIM R/W 0x0000.0000 GPIO Interrupt Mask 143
0x414 GPIORIS RO 0x0000.0000 GPIO Raw Interrupt Status 144
0x418 GPIOMIS RO 0x0000.0000 GPIO Masked Interrupt Status 145
0x41C GPIOICR W1C 0x0000.0000 GPIO Interrupt Clear 146
0x420 GPIOAFSEL R/W - GPIO Alternate Function Select 147
0x500 GPIODR2R R/W 0x0000.00FF GPIO 2-mA Drive Select 149
0x504 GPIODR4R R/W 0x0000.0000 GPIO 4-mA Drive Select 150
0x508 GPIODR8R R/W 0x0000.0000 GPIO 8-mA Drive Select 151
0x50C GPIOODR R/W 0x0000.0000 GPIO Open Drain Select 152
0x510 GPIOPUR R/W - GPIO Pull-Up Select 153
0x514 GPIOPDR R/W 0x0000.0000 GPIO Pull-Down Select 154
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General-Purpose Input/Outputs (GPIOs)
See
Offset Name Type Reset Description page
0x518 GPIOSLR R/W 0x0000.0000 GPIO Slew Rate Control Select 155
0x51C GPIODEN R/W - GPIO Digital Enable 156
0x520 GPIOLOCK R/W 0x0000.0001 GPIO Lock 157
0x524 GPIOCR - - GPIO Commit 158
0xFD0 GPIOPeriphID4 RO 0x0000.0000 GPIO Peripheral Identification 4 160
0xFD4 GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 161
0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 162
0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 163
0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 164
0xFE4 GPIOPeriphID1 RO 0x0000.0000 GPIO Peripheral Identification 1 165
0xFE8 GPIOPeriphID2 RO 0x0000.0018 GPIO Peripheral Identification 2 166
0xFEC GPIOPeriphID3 RO 0x0000.0001 GPIO Peripheral Identification 3 167
0xFF0 GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 168
0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 169
0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 170
0xFFC GPIOPCellID3 RO 0x0000.00B1 GPIO PrimeCell Identification 3 171
8.4 Register Descriptions
The remainder of this section lists and describes the GPIO registers, in numerical order by address
offset.
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Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 139).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from
the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause
the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the
corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
GPIO Data (GPIODATA)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Data
This register is virtually mapped to 256 locations in the address space.
To facilitate the reading and writing of data to these registers by
independent drivers, the data read from and the data written to the
registers are masked by the eight address lines ipaddr[9:2]. Reads
from this register return its current state. Writes to this register only affect
bits that are not masked by ipaddr[9:2] and are configured as
outputs. See “Data Register Operation” on page 132 for examples of
reads and writes.
7:0 DATA R/W 0x00
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General-Purpose Input/Outputs (GPIOs)
Register 2: GPIO Direction (GPIODIR), offset 0x400
The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure
the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are
cleared by a reset, meaning all GPIO pins are inputs by default.
GPIO Direction (GPIODIR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x400
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DIR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Data Direction
The DIR values are defined as follows:
Value Description
0 Pins are inputs.
1 Pins are outputs.
7:0 DIR R/W 0x00
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Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the
corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits
are cleared by a reset.
GPIO Interrupt Sense (GPIOIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x404
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IS
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Sense
The IS values are defined as follows:
Value Description
0 Edge on corresponding pin is detected (edge-sensitive).
1 Level on corresponding pin is detected (level-sensitive).
7:0 IS R/W 0x00
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Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register (see page 140) is set to detect edges, bits set to High in GPIOIBE
configure the corresponding pin to detect both rising and falling edges, regardless of the
corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 142). Clearing a bit
configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.
GPIO Interrupt Both Edges (GPIOIBE)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x408
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IBE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Both Edges
The IBE values are defined as follows:
Value Description
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 142).
0
1 Both edges on the corresponding pin trigger an interrupt.
Note: Single edge is determined by the corresponding bit
in GPIOIEV.
7:0 IBE R/W 0x00
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Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C
The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the
corresponding pin to detect rising edges or high levels, depending on the corresponding bit value
in the GPIO Interrupt Sense (GPIOIS) register (see page 140). Clearing a bit configures the pin to
detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are
cleared by a reset.
GPIO Interrupt Event (GPIOIEV)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x40C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IEV
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Event
The IEV values are defined as follows:
Value Description
Falling edge or Low levels on corresponding pins trigger
interrupts.
0
Rising edge or High levels on corresponding pins trigger
interrupts.
1
7:0 IEV R/W 0x00
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Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding
pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables
interrupt triggering on that pin. All bits are cleared by a reset.
GPIO Interrupt Mask (GPIOIM)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x410
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IME
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Mask Enable
The IME values are defined as follows:
Value Description
0 Corresponding pin interrupt is masked.
1 Corresponding pin interrupt is not masked.
7:0 IME R/W 0x00
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Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the
status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the
requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask
(GPIOIM) register (see page 143). Bits read as zero indicate that corresponding input pins have not
initiated an interrupt. All bits are cleared by a reset.
GPIO Raw Interrupt Status (GPIORIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x414
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Raw Status
Reflects the status of interrupt trigger condition detection on pins (raw,
prior to masking).
The RIS values are defined as follows:
Value Description
0 Corresponding pin interrupt requirements not met.
1 Corresponding pin interrupt has met requirements.
7:0 RIS RO 0x00
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General-Purpose Input/Outputs (GPIOs)
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect
the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has
been generated, or the interrupt is masked.
GPIOMIS is the state of the interrupt after masking.
GPIO Masked Interrupt Status (GPIOMIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x418
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Masked Interrupt Status
Masked value of interrupt due to corresponding pin.
The MIS values are defined as follows:
Value Description
0 Corresponding GPIO line interrupt not active.
1 Corresponding GPIO line asserting interrupt.
7:0 MIS RO 0x00
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Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt edge detection logic register. Writing a 0 has no effect.
GPIO Interrupt Clear (GPIOICR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x41C
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IC
Type RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Interrupt Clear
The IC values are defined as follows:
Value Description
0 Corresponding interrupt is unaffected.
1 Corresponding interrupt is cleared.
7:0 IC W1C 0x00
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General-Purpose Input/Outputs (GPIOs)
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register
selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore
no GPIO line is set to hardware control by default.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 147) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 157) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 158) have been set to 1.
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors,
and apply RST or power-cycle the part.
In addition, it is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
GPIO Alternate Function Select (GPIOAFSEL)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x420
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved AFSEL
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
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Bit/Field Name Type Reset Description
GPIO Alternate Function Select
The AFSEL values are defined as follows:
Value Description
0 Software control of corresponding GPIO line (GPIO mode).
Hardware control of corresponding GPIO line (alternate
hardware function).
1
Note: The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
7:0 AFSEL R/W -
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Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO
signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 2-mA Drive Select (GPIODR2R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x500
Type R/W, reset 0x0000.00FF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DRV2
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad 2-mA Drive Enable
A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the
corresponding 2-mA enable bit. The change is effective on the second
clock cycle after the write.
7:0 DRV2 R/W 0xFF
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Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504
The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 4-mA Drive Select (GPIODR4R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x504
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DRV4
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad 4-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the
corresponding 4-mA enable bit. The change is effective on the second
clock cycle after the write.
7:0 DRV4 R/W 0x00
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Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R
register are automatically cleared by hardware.
GPIO 8-mA Drive Select (GPIODR8R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x508
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DRV8
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad 8-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the
corresponding 8-mA enable bit. The change is effective on the second
clock cycle after the write.
7:0 DRV8 R/W 0x00
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Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see
page 156). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R,
and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open
drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open drain output
when set to 1.
GPIO Open Drain Select (GPIOODR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x50C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ODE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Output Pad Open Drain Enable
The ODE values are defined as follows:
Value Description
0 Open drain configuration is disabled.
1 Open drain configuration is enabled.
7:0 ODE R/W 0x00
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General-Purpose Input/Outputs (GPIOs)
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up
resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 154).
GPIO Pull-Up Select (GPIOPUR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x510
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PUE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Pad Weak Pull-Up Enable
A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n]
enables. The change is effective on the second clock cycle after the
write.
Note: The default reset value for the GPIOAFSEL, GPIOPUR, and
GPIODEN registers are 0x0000.0000 for all GPIO pins, with
the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
These five pins default to JTAG/SWD functionality. Because
of this, the default reset value of these registers for GPIO Port
B is 0x0000.0080 while the default reset value for Port C is
0x0000.000F.
7:0 PUE R/W -
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Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak
pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 153).
GPIO Pull-Down Select (GPIOPDR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x514
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PDE
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Pad Weak Pull-Down Enable
A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n]
enables. The change is effective on the second clock cycle after the
write.
7:0 PDE R/W 0x00
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General-Purpose Input/Outputs (GPIOs)
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
The GPIOSLR register is the slew rate control register. Slew rate control is only available when
using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see
page 151).
GPIO Slew Rate Control Select (GPIOSLR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x518
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SRL
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Slew Rate Limit Enable (8-mA drive only)
The SRL values are defined as follows:
Value Description
0 Slew rate control disabled.
1 Slew rate control enabled.
7:0 SRL R/W 0x00
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Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
The GPIODEN register is the digital enable register. By default, with the exception of the GPIO
signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven
(tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not
allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or
alternate function), the corresponding GPIODEN bit must be set.
GPIO Digital Enable (GPIODEN)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x51C
Type R/W, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DEN
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
Digital Enable
The DEN values are defined as follows:
Value Description
0 Digital functions disabled.
1 Digital functions enabled.
Note: The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
7:0 DEN R/W -
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General-Purpose Input/Outputs (GPIOs)
Register 19: GPIO Lock (GPIOLOCK), offset 0x520
The GPIOLOCK register enables write access to the GPIOCR register (see page 158). Writing
0x1ACCE551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value
to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns
the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses
are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses
are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000.
GPIO Lock (GPIOLOCK)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x520
Type R/W, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
GPIO Lock
A write of the value 0x1ACCE551 unlocks the GPIO Commit (GPIOCR)
register for write access. A write of any other value reapplies the lock,
preventing any register updates. A read of this register returns the
following values:
Value Description
0x0000.0001 locked
0x0000.0000 unlocked
31:0 LOCK R/W 0x0000.0001
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Register 20: GPIO Commit (GPIOCR), offset 0x524
The GPIOCR register is the commit register. The value of the GPIOCR register determines which
bits of the GPIOAFSEL register will be committed when a write to the GPIOAFSEL register is
performed. If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit
in the GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the
GPIOCR register is a one, the data being written to the corresponding bit of the GPIOAFSEL register
will be committed to the register and will reflect the new value.
The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked.
Writes to the GPIOCR register will be ignored if the GPIOLOCK register is locked.
Important: This register is designed to prevent accidental programming of the GPIOAFSEL registers
that control connectivity to the JTAG/SWD debug hardware. By initializing the bits of
the GPIOCR register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only
be converted to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR,
and GPIOAFSEL registers.
Because this protection is currently only implemented on the JTAG/SWD pins on PB7
and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0.
These bits are hardwired to 0x1, ensuring that it is always possible to commit new
values to the GPIOAFSEL register bits of these other pins.
GPIO Commit (GPIOCR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x524
Type -, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CR
Type RO RO RO RO RO RO RO RO - - - - - - - -
Reset 0 0 0 0 0 0 0 0 - - - - - - - -
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
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General-Purpose Input/Outputs (GPIOs)
Bit/Field Name Type Reset Description
GPIO Commit
On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL
bit to be set to its alternate function.
Note: The default register type for the GPIOCR register is RO for
all GPIO pins, with the exception of the five JTAG/SWD pins
(PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because
of this, the register type for GPIO Port B7 and GPIO Port
C[3:0] is R/W.
The default reset value for the GPIOCR register is
0x0000.00FF for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the
JTAG port is not accidentally programmed as a GPIO, these
five pins default to non-commitable. Because of this, the
default reset value of GPIOCR for GPIO Port B is
0x0000.007F while the default reset value of GPIOCR for Port
C is 0x0000.00F0.
7:0 CR - -
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Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 4 (GPIOPeriphID4)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID4 RO 0x00 GPIO Peripheral ID Register[7:0]
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General-Purpose Input/Outputs (GPIOs)
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 5 (GPIOPeriphID5)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID5 RO 0x00 GPIO Peripheral ID Register[15:8]
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Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 6 (GPIOPeriphID6)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID6 RO 0x00 GPIO Peripheral ID Register[23:16]
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General-Purpose Input/Outputs (GPIOs)
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 7 (GPIOPeriphID7)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID7 RO 0x00 GPIO Peripheral ID Register[31:24]
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Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 0 (GPIOPeriphID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE0
Type RO, reset 0x0000.0061
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID0 RO 0x61
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General-Purpose Input/Outputs (GPIOs)
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 1 (GPIOPeriphID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID1 RO 0x00
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Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 2 (GPIOPeriphID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID2 RO 0x18
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General-Purpose Input/Outputs (GPIOs)
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 3 (GPIOPeriphID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID3 RO 0x01
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Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 0 (GPIOPCellID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
7:0 CID0 RO 0x0D
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Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 1 (GPIOPCellID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
7:0 CID1 RO 0xF0
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Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 2 (GPIOPCellID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
7:0 CID2 RO 0x05
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Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 3 (GPIOPCellID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPIO PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
7:0 CID3 RO 0xB1
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9 General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris® General-Purpose Timer Module (GPTM) contains three GPTM blocks (Timer0, Timer1,
and Timer 2). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA and
TimerB) that can be configured to operate independently as timers or event counters, or configured
to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
Note: Timer2 is an internal timer and can only be used to generate internal interrupts.
The General-Purpose Timer Module is one timing resource available on the Stellaris® microcontrollers.
Other timer resources include the System Timer (SysTick) (see “System Timer (SysTick)” on page 34)
and the PWM timer in the PWM module (see “PWM Timer” on page 366).
The following modes are supported:
■ 32-bit Timer modes
– Programmable one-shot timer
– Programmable periodic timer
– Real-Time Clock using 32.768-KHz input clock
– Software-controlled event stalling (excluding RTC mode)
■ 16-bit Timer modes
– General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only)
– Programmable one-shot timer
– Programmable periodic timer
– Software-controlled event stalling
■ 16-bit Input Capture modes
– Input edge count capture
– Input edge time capture
■ 16-bit PWM mode
– Simple PWM mode with software-programmable output inversion of the PWM signal
9.1 Block Diagram
Note: In Figure 9-1 on page 173, the specific CCP pins available depend on the Stellaris® device.
See Table 9-1 on page 173 for the available CCPs.
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Figure 9-1. GPTM Module Block Diagram
TA Comparator
TB Comparator
GPTMTBR
GPTMAR
Clock / Edge
Detect
RTC Divider
Clock / Edge
Detect
TimerA
Interrupt
TimerB
Interrupt
System
Clock
0x0000 (Down Counter Modes)
0x0000 (Down Counter Modes)
32 KHz or
Even CCP Pin
Odd CCP Pin
En
En
TimerA Control
GPTMTAPMR
GPTMTAILR
GPTMTAMATCHR
GPTMTAPR
GPTMTAMR
TimerB Control
GPTMTBPMR
GPTMTBILR
GPTMTBMATCHR
GPTMTBPR
GPTMTBMR
Interrupt / Config
GPTMCFG
GPTMRIS
GPTMICR
GPTMMIS
GPTMIMR
GPTMCTL
Table 9-1. Available CCP Pins
Timer 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin
Timer 0 TimerA CCP0 -
TimerB - CCP1
Timer 1 TimerA CCP2 -
TimerB - CCP3
Timer 2 TimerA - -
TimerB - -
9.2 Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit
load/initialization registers and their associated control functions. The exact functionality of each
GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 184),
the GPTM TimerA Mode (GPTMTAMR) register (see page 185), and the GPTM TimerB Mode
(GPTMTBMR) register (see page 187). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
9.2.1 GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters TimerA and TimerB are initialized to
0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
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(GPTMTAILR) register (see page 198) and the GPTM TimerB Interval Load (GPTMTBILR) register
(see page 199). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale
(GPTMTAPR) register (see page 202) and the GPTM TimerB Prescale (GPTMTBPR) register (see
page 203).
9.2.2 32-Bit Timer Operating Modes
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configuration.
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 198
■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 199
■ GPTM TimerA (GPTMTAR) register [15:0], see page 206
■ GPTM TimerB (GPTMTBR) register [15:0], see page 207
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
9.2.2.1 32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB
registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is
determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register
(see page 185), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register.
When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 189), the
timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the
timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to
be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If
configured as a periodic timer, it continues counting.
In addition to reloading the count value, the GPTM generates interrupts and output triggers when
it reaches the 0x0000000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status
(GPTMRIS) register (see page 194), and holds it until it is cleared by writing the GPTM Interrupt
Clear (GPTMICR) register (see page 196). If the time-out interrupt is enabled in the GPTM Interrupt
Mask (GPTIMR) register (see page 192), the GPTM also sets the TATOMIS bit in the GPTM Masked
Interrupt Status (GPTMMIS) register (see page 195).
The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000.0000
state, and deasserted on the following clock cycle. It is enabled by setting the TAOTE bit in GPTMCTL.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
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If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal
is deasserted.
9.2.2.2 32-Bit Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is
loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA
Match (GPTMTAMATCHR) register (see page 200) by the controller.
The input clock on the CCP0, CCP2, or CCP4 pins is required to be 32.768 KHz in RTC mode. The
clock signal is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter.
When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its
preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until
either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs,
the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the
GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags
are cleared by writing the RTCCINT bit in GPTMICR.
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if
the RTCEN bit is set in GPTMCTL.
9.2.3 16-Bit Timer Operating Modes
The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration
(GPTMCFG) register (see page 184). This section describes each of the GPTM 16-bit modes of
operation. TimerA and TimerB have identical modes, so a single description is given using an n to
reference both.
9.2.3.1 16-Bit One-Shot/Periodic Timer Mode
In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with
an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The
selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR)
register.
When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from
its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from
GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops
counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it
continues counting.
In addition to reloading the count value, the timer generates interrupts and output triggers when it
reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it
until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR,
the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt.
The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000 state,
and deasserted on the following clock cycle. It is enabled by setting the TnOTE bit in the GPTMCTL
register, and can trigger SoC-level events.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
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If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal
is deasserted.
The following example shows a variety of configurations for a 16-bit free running timer while using
the prescaler. All values assume a 25-MHz clock with Tc=20 ns (clock period).
Table 9-2. 16-Bit Timer With Prescaler Configurations
Prescale #Clock (T c)a Max Time Units
00000000 1 2.6214 mS
00000001 2 5.2428 mS
00000010 3 7.8642 mS
------------ -- -- --
11111100 254 665.8458 mS
11111110 255 668.4672 mS
11111111 256 671.0886 mS
a. Tc is the clock period.
9.2.3.2 16-Bit Input Edge Count Mode
In Edge Count mode, the timer is configured as a down-counter capable of capturing three types
of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit
of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined
by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match
(GPTMTnMATCHR) register is configured so that the difference between the value in the
GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that
must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count
matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the
GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded
using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in
the GPTMCTL register. Once the event count has been reached, all further events are ignored until
TnEN is re-enabled by software.
Figure 9-2 on page 177 shows how input edge count mode works. In this case, the timer start value
is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so that four
edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit after
the current count matches the value in the GPTMnMR register.
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Figure 9-2. 16-Bit Input Edge Count Mode Example
0x000A
0x0006
0x0007
0x0008
0x0009
Input Signal
Timer stops,
flags
asserted
Timer reload
Count on next cycle Ignored Ignored
9.2.3.3 16-Bit Input Edge Time Mode
Note: The prescaler is not available in 16-Bit Input Edge Time mode.
In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value
loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of both
rising and falling edges. The timer is placed into Edge Time mode by setting the TnCMR bit in the
GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT
fields of the GPTMCnTL register.
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture.
When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR
register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and
the CnEMIS bit, if the interrupt is not masked).
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the
GPTMnILR register.
Figure 9-3 on page 178 shows how input edge timing mode works. In the diagram, it is assumed that
the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture
rising edge events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR
register, and is held there until another rising edge is detected (at which point the new count value
is loaded into GPTMTnR).
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Figure 9-3. 16-Bit Input Edge Time Mode Example
GPTMTnR=Y
Input Signal
Time
Count
GPTMTnR=X GPTMTnR=Z
Z
X
Y
0xFFFF
9.2.3.4 16-Bit PWM Mode
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled
with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR
field to 0x2.
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from
GPTMTnILR (and GPTMTnPR if using a prescaler) and continues counting until disabled by software
clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM
mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTM Timern Match
Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by
setting the TnPWML bit in the GPTMCTL register.
Figure 9-4 on page 179 shows how to generate an output PWM with a 1-ms period and a 66% duty
cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML
=1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is
GPTMnMR=0x411A.
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Figure 9-4. 16-Bit PWM Mode Example
Output
Signal
Time
Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR
0xC350
0x411A
TnPWML = 0
TnPWML = 1
TnEN set
9.3 Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0,
TIMER1, and TIMER2 bits in the RCGC1 register.
This section shows module initialization and configuration examples for each of the supported timer
modes.
9.3.1 32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0.
3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR).
5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
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7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
In One-Shot mode, the timer stops counting after step 7 on page 180. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
9.3.2 32-Bit Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on its CCP0, CCP2, or CCP4
pins. To enable the RTC feature, follow these steps:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1.
3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR).
4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired.
5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded
with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared.
9.3.3 16-Bit One-Shot/Periodic Timer Mode
A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4.
3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register:
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register
(GPTMTnPR).
5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR).
6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start
counting.
8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
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In One-Shot mode, the timer stops counting after step 8 on page 180. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
9.3.4 16-Bit Input Edge Count Mode
A timer is configured to Input Edge Count mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.
4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register.
7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.
9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM
Interrupt Clear (GPTMICR) register.
In Input Edge Count Mode, the timer stops after the desired number of edge events has been
detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 181
through step 9 on page 181.
9.3.5 16-Bit Input Edge Timing Mode
A timer is configured to Input Edge Timing mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3.
4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting.
8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM
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Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timern (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
9.3.6 16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field
of the GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.
7. If a prescaler is going to be used, configure the GPTM Timern Prescale (GPTMTnPR) register
and the GPTM Timern Prescale Match (GPTMTnPMR) register.
8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
9.4 Register Map
Table 9-3 on page 182 lists the GPTM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that timer’s base address:
■ Timer0: 0x4003.0000
■ Timer1: 0x4003.1000
■ Timer2: 0x4003.2000
Table 9-3. Timers Register Map
See
Offset Name Type Reset Description page
0x000 GPTMCFG R/W 0x0000.0000 GPTM Configuration 184
0x004 GPTMTAMR R/W 0x0000.0000 GPTM TimerA Mode 185
0x008 GPTMTBMR R/W 0x0000.0000 GPTM TimerB Mode 187
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See
Offset Name Type Reset Description page
0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 189
0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 192
0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 194
0x020 GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 195
0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 196
GPTM TimerA Interval Load 198
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
0x028 GPTMTAILR R/W
0x02C GPTMTBILR R/W 0x0000.FFFF GPTM TimerB Interval Load 199
GPTM TimerA Match 200
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
0x030 GPTMTAMATCHR R/W
0x034 GPTMTBMATCHR R/W 0x0000.FFFF GPTM TimerB Match 201
0x038 GPTMTAPR R/W 0x0000.0000 GPTM TimerA Prescale 202
0x03C GPTMTBPR R/W 0x0000.0000 GPTM TimerB Prescale 203
0x040 GPTMTAPMR R/W 0x0000.0000 GPTM TimerA Prescale Match 204
0x044 GPTMTBPMR R/W 0x0000.0000 GPTM TimerB Prescale Match 205
GPTM TimerA 206
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
0x048 GPTMTAR RO
0x04C GPTMTBR RO 0x0000.FFFF GPTM TimerB 207
9.5 Register Descriptions
The remainder of this section lists and describes the GPTM registers, in numerical order by address
offset.
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Register 1: GPTM Configuration (GPTMCFG), offset 0x000
This register configures the global operation of the GPTM module. The value written to this register
determines whether the GPTM is in 32- or 16-bit mode.
GPTM Configuration (GPTMCFG)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GPTMCFG
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
GPTM Configuration
The GPTMCFG values are defined as follows:
Value Description
0x0 32-bit timer configuration.
0x1 32-bit real-time clock (RTC) counter configuration.
0x2 Reserved.
0x3 Reserved.
16-bit timer configuration, function is controlled by bits 1:0 of
GPTMTAMR and GPTMTBMR.
0x4-0x7
2:0 GPTMCFG R/W 0x0
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Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.
GPTM TimerA Mode (GPTMTAMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TAAMS TACMR TAMR
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
GPTM TimerA Alternate Mode Select
The TAAMS values are defined as follows:
Value Description
0 Capture mode is enabled.
1 PWM mode is enabled.
Note: To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.
3 TAAMS R/W 0
GPTM TimerA Capture Mode
The TACMR values are defined as follows:
Value Description
0 Edge-Count mode.
1 Edge-Time mode.
2 TACMR R/W 0
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Bit/Field Name Type Reset Description
GPTM TimerA Mode
The TAMR values are defined as follows:
Value Description
0x0 Reserved.
0x1 One-Shot Timer mode.
0x2 Periodic Timer mode.
0x3 Capture mode.
The Timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register (16-or 32-bit).
In 16-bit timer configuration, TAMR controls the 16-bit timer modes for
TimerA.
In 32-bit timer configuration, this register controls the mode and the
contents of GPTMTBMR are ignored.
1:0 TAMR R/W 0x0
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Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to
0x2.
GPTM TimerB Mode (GPTMTBMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBAMS TBCMR TBMR
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
GPTM TimerB Alternate Mode Select
The TBAMS values are defined as follows:
Value Description
0 Capture mode is enabled.
1 PWM mode is enabled.
Note: To enable PWM mode, you must also clear the TBCMR
bit and set the TBMR field to 0x2.
3 TBAMS R/W 0
GPTM TimerB Capture Mode
The TBCMR values are defined as follows:
Value Description
0 Edge-Count mode.
1 Edge-Time mode.
2 TBCMR R/W 0
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Bit/Field Name Type Reset Description
GPTM TimerB Mode
The TBMR values are defined as follows:
Value Description
0x0 Reserved.
0x1 One-Shot Timer mode.
0x2 Periodic Timer mode.
0x3 Capture mode.
The timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
In 16-bit timer configuration, these bits control the 16-bit timer modes
for TimerB.
In 32-bit timer configuration, this register’s contents are ignored and
GPTMTAMR is used.
1:0 TBMR R/W 0x0
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Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBPWML TBOTE reserved TBEVENT TBSTALL TBEN reserved TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN
Type RO R/W R/W RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:15 reserved RO 0x00
GPTM TimerB PWM Output Level
The TBPWML values are defined as follows:
Value Description
0 Output is unaffected.
1 Output is inverted.
14 TBPWML R/W 0
GPTM TimerB Output Trigger Enable
The TBOTE values are defined as follows:
Value Description
0 The output TimerB trigger is disabled.
1 The output TimerB trigger is enabled.
13 TBOTE R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12 reserved RO 0
GPTM TimerB Event Mode
The TBEVENT values are defined as follows:
Value Description
0x0 Positive edge.
0x1 Negative edge.
0x2 Reserved
0x3 Both edges.
11:10 TBEVENT R/W 0x0
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Bit/Field Name Type Reset Description
GPTM TimerB Stall Enable
The TBSTALL values are defined as follows:
Value Description
0 TimerB stalling is disabled.
1 TimerB stalling is enabled.
9 TBSTALL R/W 0
GPTM TimerB Enable
The TBEN values are defined as follows:
Value Description
0 TimerB is disabled.
TimerB is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
8 TBEN R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7 reserved RO 0
GPTM TimerA PWM Output Level
The TAPWML values are defined as follows:
Value Description
0 Output is unaffected.
1 Output is inverted.
6 TAPWML R/W 0
GPTM TimerA Output Trigger Enable
The TAOTE values are defined as follows:
Value Description
0 The output TimerA trigger is disabled.
1 The output TimerA trigger is enabled.
5 TAOTE R/W 0
GPTM RTC Enable
The RTCEN values are defined as follows:
Value Description
0 RTC counting is disabled.
1 RTC counting is enabled.
4 RTCEN R/W 0
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Bit/Field Name Type Reset Description
GPTM TimerA Event Mode
The TAEVENT values are defined as follows:
Value Description
0x0 Positive edge.
0x1 Negative edge.
0x2 Reserved
0x3 Both edges.
3:2 TAEVENT R/W 0x0
GPTM TimerA Stall Enable
The TASTALL values are defined as follows:
Value Description
0 TimerA stalling is disabled.
1 TimerA stalling is enabled.
1 TASTALL R/W 0
GPTM TimerA Enable
The TAEN values are defined as follows:
Value Description
0 TimerA is disabled.
TimerA is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
0 TAEN R/W 0
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Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables
the interrupt, while writing a 0 disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x018
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBEIM CBMIM TBTOIM reserved RTCIM CAEIM CAMIM TATOIM
Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Interrupt Mask
The CBEIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
10 CBEIM R/W 0
GPTM CaptureB Match Interrupt Mask
The CBMIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
9 CBMIM R/W 0
GPTM TimerB Time-Out Interrupt Mask
The TBTOIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
8 TBTOIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0
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Bit/Field Name Type Reset Description
GPTM RTC Interrupt Mask
The RTCIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
3 RTCIM R/W 0
GPTM CaptureA Event Interrupt Mask
The CAEIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
2 CAEIM R/W 0
GPTM CaptureA Match Interrupt Mask
The CAMIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
1 CAMIM R/W 0
GPTM TimerA Time-Out Interrupt Mask
The TATOIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
0 TATOIM R/W 0
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Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBERIS CBMRIS TBTORIS reserved RTCRIS CAERIS CAMRIS TATORIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
10 CBERIS RO 0
GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
9 CBMRIS RO 0
GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
8 TBTORIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x0
GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
3 RTCRIS RO 0
GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
2 CAERIS RO 0
GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
1 CAMRIS RO 0
GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
0 TATORIS RO 0
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Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x020
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBEMIS CBMMIS TBTOMIS reserved RTCMIS CAEMIS CAMMIS TATOMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Masked Interrupt
This is the CaptureB event interrupt status after masking.
10 CBEMIS RO 0
GPTM CaptureB Match Masked Interrupt
This is the CaptureB match interrupt status after masking.
9 CBMMIS RO 0
GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
8 TBTOMIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x0
GPTM RTC Masked Interrupt
This is the RTC event interrupt status after masking.
3 RTCMIS RO 0
GPTM CaptureA Event Masked Interrupt
This is the CaptureA event interrupt status after masking.
2 CAEMIS RO 0
GPTM CaptureA Match Masked Interrupt
This is the CaptureA match interrupt status after masking.
1 CAMMIS RO 0
GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
0 TATOMIS RO 0
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Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x024
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CBECINT CBMCINT TBTOCINT reserved RTCCINT CAECINT CAMCINT TATOCINT
Type RO RO RO RO RO W1C W1C W1C RO RO RO RO W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
GPTM CaptureB Event Interrupt Clear
The CBECINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
10 CBECINT W1C 0
GPTM CaptureB Match Interrupt Clear
The CBMCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
9 CBMCINT W1C 0
GPTM TimerB Time-Out Interrupt Clear
The TBTOCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
8 TBTOCINT W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x0
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Bit/Field Name Type Reset Description
GPTM RTC Interrupt Clear
The RTCCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
3 RTCCINT W1C 0
GPTM CaptureA Event Interrupt Clear
The CAECINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
2 CAECINT W1C 0
GPTM CaptureA Match Raw Interrupt
This is the CaptureA match interrupt status after masking.
1 CAMCINT W1C 0
GPTM TimerA Time-Out Raw Interrupt
The TATOCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
0 TATOCINT W1C 0
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Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028
This register is used to load the starting count value into the timer. When GPTM is configured to
one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond
to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
GPTM TimerA Interval Load (GPTMTAILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x028
Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAILRH
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAILRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
GPTM TimerA Interval Load Register High
When configured for 32-bit mode via the GPTMCFG register, the GPTM
TimerB Interval Load (GPTMTBILR) register loads this value on a
write. A read returns the current value of GPTMTBILR.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBILR.
0xFFFF
(32-bit mode)
0x0000 (16-bit
mode)
31:16 TAILRH R/W
GPTM TimerA Interval Load Register Low
For both 16- and 32-bit modes, writing this field loads the counter for
TimerA. A read returns the current value of GPTMTAILR.
15:0 TAILRL R/W 0xFFFF
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General-Purpose Timers
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C
This register is used to load the starting count value into TimerB. When the GPTM is configured to
a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes.
GPTM TimerB Interval Load (GPTMTBILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBILRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
GPTM TimerB Interval Load Register
When the GPTM is not configured as a 32-bit timer, a write to this field
updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads
return the current value of GPTMTBILR.
15:0 TBILRL R/W 0xFFFF
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Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerA Match (GPTMTAMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x030
Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMRH
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
GPTM TimerA Match Register High
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the upper half of
GPTMTAR, to determine match events.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBMATCHR.
0xFFFF
(32-bit mode)
0x0000 (16-bit
mode)
31:16 TAMRH R/W
GPTM TimerA Match Register Low
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the lower half of
GPTMTAR, to determine match events.
When configured for PWM mode, this value along with GPTMTAILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTAILR
minus this value.
15:0 TAMRL R/W 0xFFFF
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General-Purpose Timers
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerB Match (GPTMTBMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x034
Type R/W, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBMRL
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
GPTM TimerB Match Register Low
When configured for PWM mode, this value along with GPTMTBILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTBILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTBILR
minus this value.
15:0 TBMRL R/W 0xFFFF
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Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerA Prescale (GPTMTAPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TAPSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerA Prescale
The register loads this value on a write. A read returns the current value
of the register.
Refer to Table 9-2 on page 176 for more details and an example.
7:0 TAPSR R/W 0x00
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General-Purpose Timers
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerB Prescale (GPTMTBPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x03C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBPSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerB Prescale
The register loads this value on a write. A read returns the current value
of this register.
Refer to Table 9-2 on page 176 for more details and an example.
7:0 TBPSR R/W 0x00
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Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040
This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerA Prescale Match (GPTMTAPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x040
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TAPSMR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerA Prescale Match
This value is used alongside GPTMTAMATCHR to detect timer match
events while using a prescaler.
7:0 TAPSMR R/W 0x00
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General-Purpose Timers
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044
This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerB Prescale Match (GPTMTBPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x044
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TBPSMR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
GPTM TimerB Prescale Match
This value is used alongside GPTMTBMATCHR to detect timer match
events while using a prescaler.
7:0 TBPSMR R/W 0x00
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LM3S6110 Microcontroller
Register 17: GPTM TimerA (GPTMTAR), offset 0x048
This register shows the current value of the TimerA counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerA (GPTMTAR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x048
Type RO, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TARH
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TARL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
GPTM TimerA Register High
If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the
GPTMCFG is in a 16-bit mode, this is read as zero.
0xFFFF
(32-bit mode)
0x0000 (16-bit
mode)
31:16 TARH RO
GPTM TimerA Register Low
A read returns the current value of the GPTM TimerA Count Register,
except in Input Edge Count mode, when it returns the timestamp from
the last edge event.
15:0 TARL RO 0xFFFF
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General-Purpose Timers
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C
This register shows the current value of the TimerB counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerB (GPTMTBR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x04C
Type RO, reset 0x0000.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBRL
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
GPTM TimerB
A read returns the current value of the GPTM TimerB Count Register,
except in Input Edge Count mode, when it returns the timestamp from
the last edge event.
15:0 TBRL RO 0xFFFF
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LM3S6110 Microcontroller
10 Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
The Stellaris® Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, a locking register, and user-enabled stalling.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
10.1 Block Diagram
Figure 10-1. WDT Module Block Diagram
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
WDTRIS
WDTMIS
WDTLOCK
WDTTEST
WDTLOAD
WDTVALUE
Comparator
32-Bit Down
Counter
0x00000000
Interrupt
System Clock
Identification Registers
WDTPCellID0 WDTPeriphID0 WDTPeriphID4
WDTPCellID1 WDTPeriphID1 WDTPeriphID5
WDTPCellID2 WDTPeriphID2 WDTPeriphID6
WDTPCellID3 WDTPeriphID3 WDTPeriphID7
10.2 Functional Description
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the
208 November 30, 2007
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Watchdog Timer
Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written,
which prevents the timer configuration from being inadvertently altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) register.
The Watchdog module interrupt and reset generation can be enabled or disabled as required. When
the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its
last state.
10.3 Initialization and Configuration
To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register.
The Watchdog Timer is configured using the following sequence:
1. Load the WDTLOAD register with the desired timer load value.
2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.
3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register.
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write
a value of 0x1ACC.E551.
10.4 Register Map
Table 10-1 on page 209 lists the Watchdog registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000.
Table 10-1. Watchdog Timer Register Map
See
Offset Name Type Reset Description page
0x000 WDTLOAD R/W 0xFFFF.FFFF Watchdog Load 211
0x004 WDTVALUE RO 0xFFFF.FFFF Watchdog Value 212
0x008 WDTCTL R/W 0x0000.0000 Watchdog Control 213
0x00C WDTICR WO - Watchdog Interrupt Clear 214
0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 215
0x014 WDTMIS RO 0x0000.0000 Watchdog Masked Interrupt Status 216
0x418 WDTTEST R/W 0x0000.0000 Watchdog Test 217
0xC00 WDTLOCK R/W 0x0000.0000 Watchdog Lock 218
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LM3S6110 Microcontroller
See
Offset Name Type Reset Description page
0xFD0 WDTPeriphID4 RO 0x0000.0000 Watchdog Peripheral Identification 4 219
0xFD4 WDTPeriphID5 RO 0x0000.0000 Watchdog Peripheral Identification 5 220
0xFD8 WDTPeriphID6 RO 0x0000.0000 Watchdog Peripheral Identification 6 221
0xFDC WDTPeriphID7 RO 0x0000.0000 Watchdog Peripheral Identification 7 222
0xFE0 WDTPeriphID0 RO 0x0000.0005 Watchdog Peripheral Identification 0 223
0xFE4 WDTPeriphID1 RO 0x0000.0018 Watchdog Peripheral Identification 1 224
0xFE8 WDTPeriphID2 RO 0x0000.0018 Watchdog Peripheral Identification 2 225
0xFEC WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 226
0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 227
0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 228
0xFF8 WDTPCellID2 RO 0x0000.0005 Watchdog PrimeCell Identification 2 229
0xFFC WDTPCellID3 RO 0x0000.00B1 Watchdog PrimeCell Identification 3 230
10.5 Register Descriptions
The remainder of this section lists and describes the WDT registers, in numerical order by address
offset.
210 November 30, 2007
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Watchdog Timer
Register 1: Watchdog Load (WDTLOAD), offset 0x000
This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the
value is immediately loaded and the counter restarts counting down from the new value. If the
WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated.
Watchdog Load (WDTLOAD)
Base 0x4000.0000
Offset 0x000
Type R/W, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTLoad
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTLoad
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
31:0 WDTLoad R/W 0xFFFF.FFFF Watchdog Load Value
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LM3S6110 Microcontroller
Register 2: Watchdog Value (WDTVALUE), offset 0x004
This register contains the current count value of the timer.
Watchdog Value (WDTVALUE)
Base 0x4000.0000
Offset 0x004
Type RO, reset 0xFFFF.FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTValue
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTValue
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Watchdog Value
Current value of the 32-bit down counter.
31:0 WDTValue RO 0xFFFF.FFFF
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Watchdog Timer
Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.
Watchdog Control (WDTCTL)
Base 0x4000.0000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RESEN INTEN
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Watchdog Reset Enable
The RESEN values are defined as follows:
Value Description
0 Disabled.
1 Enable the Watchdog module reset output.
1 RESEN R/W 0
Watchdog Interrupt Enable
The INTEN values are defined as follows:
Value Description
Interrupt event disabled (once this bit is set, it can only be
cleared by a hardware reset).
0
1 Interrupt event enabled. Once enabled, all writes are ignored.
0 INTEN R/W 0
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Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C
This register is the interrupt clear register. A write of any value to this register clears the Watchdog
interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is
indeterminate.
Watchdog Interrupt Clear (WDTICR)
Base 0x4000.0000
Offset 0x00C
Type WO, reset -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTIntClr
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTIntClr
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset - - - - - - - - - - - - - - - -
Bit/Field Name Type Reset Description
31:0 WDTIntClr WO - Watchdog Interrupt Clear
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Watchdog Timer
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010
This register is the raw interrupt status register. Watchdog interrupt events can be monitored via
this register if the controller interrupt is masked.
Watchdog Raw Interrupt Status (WDTRIS)
Base 0x4000.0000
Offset 0x010
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WDTRIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Watchdog Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of WDTINTR.
0 WDTRIS RO 0
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LM3S6110 Microcontroller
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.
Watchdog Masked Interrupt Status (WDTMIS)
Base 0x4000.0000
Offset 0x014
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WDTMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Watchdog Masked Interrupt Status
Gives the masked interrupt state (after masking) of the WDTINTR
interrupt.
0 WDTMIS RO 0
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Watchdog Timer
Register 7: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
Watchdog Test (WDTTEST)
Base 0x4000.0000
Offset 0x418
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved STALL reserved
Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:9 reserved RO 0x00
Watchdog Stall Enable
When set to 1, if the Stellaris® microcontroller is stopped with a
debugger, the watchdog timer stops counting. Once the microcontroller
is restarted, the watchdog timer resumes counting.
8 STALL R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0 reserved RO 0x00
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Register 8: Watchdog Lock (WDTLOCK), offset 0xC00
Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing
any other value to the WDTLOCK register re-enables the locked state for register writes to all the
other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value
written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns
0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)).
Watchdog Lock (WDTLOCK)
Base 0x4000.0000
Offset 0xC00
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTLock
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTLock
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Watchdog Lock
A write of the value 0x1ACC.E551 unlocks the watchdog registers for
write access. A write of any other value reapplies the lock, preventing
any register updates.
A read of this register returns the following values:
Value Description
0x0000.0001 Locked
0x0000.0000 Unlocked
31:0 WDTLock R/W 0x0000
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Watchdog Timer
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 4 (WDTPeriphID4)
Base 0x4000.0000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID4 RO 0x00 WDT Peripheral ID Register[7:0]
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Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset
0xFD4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 5 (WDTPeriphID5)
Base 0x4000.0000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID5 RO 0x00 WDT Peripheral ID Register[15:8]
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Watchdog Timer
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset
0xFD8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 6 (WDTPeriphID6)
Base 0x4000.0000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID6 RO 0x00 WDT Peripheral ID Register[23:16]
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Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset
0xFDC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 7 (WDTPeriphID7)
Base 0x4000.0000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID7 RO 0x00 WDT Peripheral ID Register[31:24]
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Watchdog Timer
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset
0xFE0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 0 (WDTPeriphID0)
Base 0x4000.0000
Offset 0xFE0
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID0 RO 0x05 Watchdog Peripheral ID Register[7:0]
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Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset
0xFE4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 1 (WDTPeriphID1)
Base 0x4000.0000
Offset 0xFE4
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID1 RO 0x18 Watchdog Peripheral ID Register[15:8]
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Watchdog Timer
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset
0xFE8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 2 (WDTPeriphID2)
Base 0x4000.0000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID2 RO 0x18 Watchdog Peripheral ID Register[23:16]
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Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset
0xFEC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 3 (WDTPeriphID3)
Base 0x4000.0000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 PID3 RO 0x01 Watchdog Peripheral ID Register[31:24]
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Watchdog Timer
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 0 (WDTPCellID0)
Base 0x4000.0000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID0 RO 0x0D Watchdog PrimeCell ID Register[7:0]
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Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 1 (WDTPCellID1)
Base 0x4000.0000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID1 RO 0xF0 Watchdog PrimeCell ID Register[15:8]
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Watchdog Timer
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 2 (WDTPCellID2)
Base 0x4000.0000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID2 RO 0x05 Watchdog PrimeCell ID Register[23:16]
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Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 3 (WDTPCellID3)
Base 0x4000.0000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
7:0 CID3 RO 0xB1 Watchdog PrimeCell ID Register[31:24]
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Watchdog Timer
11 Universal Asynchronous Receivers/Transmitters
(UARTs)
The Stellaris® Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable,
16C550-type serial interface characteristics. The LM3S6110 controller is equipped with one UART
module.
The UART has the following features:
■ Separate transmit and receive FIFOs
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Programmable baud-rate generator allowing rates up to 1.5625 Mbps
■ Standard asynchronous communication bits for start, stop, and parity
■ False start bit detection
■ Line-break generation and detection
■ Fully programmable serial interface characteristics:
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing:
– Programmable use of IrDA Serial InfraRed (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
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11.1 Block Diagram
Figure 11-1. UART Module Block Diagram
Receiver
Transmitter
System Clock
Control / Status
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
UARTILPR
Interrupt Control
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
Baud Rate
Generator
UARTIBRD
UARTFBRD
Identification
Registers
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UART PeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
UARTDR
TXFIFO
16x8
...
RXFIFO
16x8
...
Interrupt
UnTx
UnRx
11.2 Functional Description
Each Stellaris® UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 250). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected
to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
11.2.1 Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
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Universal Asynchronous Receivers/Transmitters (UARTs)
bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 11-2 on page 233 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 11-2. UART Character Frame
1
0 5-8 data bits
LSB MSB
Parity bit
if enabled
1-2
stop bits
UnTX
n
Start
11.2.2 Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 246) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 247). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.):
BRD = BRDI + BRDF = SysClk / (16 * Baud Rate)
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register)
can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and
adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as
Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error
detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 248), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
■ UARTIBRD write, UARTFBRD write, and UARTLCRH write
■ UARTFBRD write, UARTIBRD write, and UARTLCRH write
■ UARTIBRD write and UARTLCRH write
■ UARTFBRD write and UARTLCRH write
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11.2.3 Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 243) is asserted as soon as
data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has
been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 (described in “Transmit/Receive Logic” on page 232).
The start bit is valid if UnRx is still low on the eighth cycle of Baud16, otherwise a false start bit is
detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR)
register (see page 241). If the start bit was valid, successive data bits are sampled on every 16th
cycle of Baud16 (that is, one bit period later) according to the programmed length of the data
characters. The parity bit is then checked if parity mode was enabled. Data length and parity are
defined in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When
a full word is received, the data is stored in the receive FIFO, with any error bits associated with
that word.
11.2.4 Serial IR (SIR)
The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream, and half-duplex
serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to
provide a digital encoded output, and decoded input to the UART. The UART signal pins can be
connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block
has two modes of operation:
■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the
selected baud rate bit period on the output pin, while logic one levels are transmitted as a static
LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light
for each zero. On the reception side, the incoming light pulses energize the photo transistor base
of the receiver, pulling its output LOW. This drives the UART input pin LOW.
■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the
period of the internally generated IrLPBaud16 signal (1.63 μs, assuming a nominal 1.8432 MHz
frequency) by changing the appropriate bit in the UARTCR register.
Figure 11-3 on page 235 shows the UART transmit and receive signals, with and without IrDA
modulation.
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Figure 11-3. IrDA Data Modulation
0 1 0 1 0 0 1 1 0 1
Data bits
0 1 0 1 0 0 1 1 0 1
Start Data bits
bit
Start Stop
Bit period Bit period
3
16
UnTx
UnTx with IrDA
UnRx with IrDA
UnRx
Stop
bit
In both normal and low-power IrDA modes:
■ During transmission, the UART data bit is used as the base for encoding
■ During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay
between transmission and reception. This delay must be generated by software because it is not
automatically supported by the UART. The delay is required because the infrared receiver electronics
might become biased, or even saturated from the optical power coupled from the adjacent transmitter
LED. This delay is known as latency, or receiver setup time.
11.2.5 FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 239). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data
in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 248).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 243) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the
UARTRSR register shows overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 252). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For
example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt
after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the
½ mark.
11.2.6 Interrupts
The UART can generate interrupts when the following conditions are observed:
■ Overrun Error
■ Break Error
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■ Parity Error
■ Framing Error
■ Receive Timeout
■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)
■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 257).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM ) register (see page 254) by setting the corresponding IM bit to 1. If interrupts are
not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 256).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 258).
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data
is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO
becomes empty through reading all the data (or by reading the holding register), or when a 1 is
written to the corresponding bit in the UARTICR register.
11.2.7 Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 250). In loopback mode,
data transmitted on UnTx is received on the UnRx input.
11.2.8 IrDA SIR block
The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the
SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR
transceiver.
The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same
time. Transmission must be stopped before data can be received. The IrDA SIR physical layer
specifies a minimum 10-ms delay between transmission and reception.
11.3 Initialization and Configuration
To use the UART, the peripheral clock must be enabled by setting the UART0 bit in the RCGC1
register.
This section discusses the steps that are required for using a UART module. For this example, the
system clock is assumed to be 20 MHz and the desired UART configuration is:
■ 115200 baud rate
■ Data length of 8 bits
■ One stop bit
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■ No parity
■ FIFOs disabled
■ No interrupts
The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the
UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the
equation described in “Baud-Rate Generation” on page 233, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 246) should be set to 10.
The value to be loaded into the UARTFBRD register (see page 247) is calculated by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Enable the UART by setting the UARTEN bit in the UARTCTL register.
11.4 Register Map
Table 11-1 on page 237 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■ UART0: 0x4000.C000
Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 250)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 11-1. UART Register Map
See
Offset Name Type Reset Description page
0x000 UARTDR R/W 0x0000.0000 UART Data 239
0x004 UARTRSR/UARTECR R/W 0x0000.0000 UART Receive Status/Error Clear 241
0x018 UARTFR RO 0x0000.0090 UART Flag 243
0x020 UARTILPR R/W 0x0000.0000 UART IrDA Low-Power Register 245
0x024 UARTIBRD R/W 0x0000.0000 UART Integer Baud-Rate Divisor 246
0x028 UARTFBRD R/W 0x0000.0000 UART Fractional Baud-Rate Divisor 247
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See
Offset Name Type Reset Description page
0x02C UARTLCRH R/W 0x0000.0000 UART Line Control 248
0x030 UARTCTL R/W 0x0000.0300 UART Control 250
0x034 UARTIFLS R/W 0x0000.0012 UART Interrupt FIFO Level Select 252
0x038 UARTIM R/W 0x0000.0000 UART Interrupt Mask 254
0x03C UARTRIS RO 0x0000.000F UART Raw Interrupt Status 256
0x040 UARTMIS RO 0x0000.0000 UART Masked Interrupt Status 257
0x044 UARTICR W1C 0x0000.0000 UART Interrupt Clear 258
0xFD0 UARTPeriphID4 RO 0x0000.0000 UART Peripheral Identification 4 260
0xFD4 UARTPeriphID5 RO 0x0000.0000 UART Peripheral Identification 5 261
0xFD8 UARTPeriphID6 RO 0x0000.0000 UART Peripheral Identification 6 262
0xFDC UARTPeriphID7 RO 0x0000.0000 UART Peripheral Identification 7 263
0xFE0 UARTPeriphID0 RO 0x0000.0011 UART Peripheral Identification 0 264
0xFE4 UARTPeriphID1 RO 0x0000.0000 UART Peripheral Identification 1 265
0xFE8 UARTPeriphID2 RO 0x0000.0018 UART Peripheral Identification 2 266
0xFEC UARTPeriphID3 RO 0x0000.0001 UART Peripheral Identification 3 267
0xFF0 UARTPCellID0 RO 0x0000.000D UART PrimeCell Identification 0 268
0xFF4 UARTPCellID1 RO 0x0000.00F0 UART PrimeCell Identification 1 269
0xFF8 UARTPCellID2 RO 0x0000.0005 UART PrimeCell Identification 2 270
0xFFC UARTPCellID3 RO 0x0000.00B1 UART PrimeCell Identification 3 271
11.5 Register Descriptions
The remainder of this section lists and describes the UART registers, in numerical order by address
offset.
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Register 1: UART Data (UARTDR), offset 0x000
This register is the data register (the interface to the FIFOs).
When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs
are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.
UART Data (UARTDR)
UART0 base: 0x4000.C000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OE BE PE FE DATA
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0
UART Overrun Error
The OE values are defined as follows:
Value Description
0 There has been no data loss due to a FIFO overrun.
New data was received when the FIFO was full, resulting in
data loss.
1
11 OE RO 0
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the receive data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state) and the next valid start bit is received.
10 BE RO 0
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
9 PE RO 0
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Bit/Field Name Type Reset Description
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
8 FE RO 0
Data Transmitted or Received
When written, the data that is to be transmitted via the UART. When
read, the data that was received by the UART.
7:0 DATA R/W 0
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Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset
0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared to 0 on reset.
Read-Only Receive Status (UARTRSR) Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
Offset 0x004
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OE BE PE FE
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0
UART Overrun Error
When this bit is set to 1, data is received and the FIFO is already full.
This bit is cleared to 0 by a write to UARTECR.
The FIFO contents remain valid since no further data is written when
the FIFO is full, only the contents of the shift register are overwritten.
The CPU must now read the data in order to empty the FIFO.
3 OE RO 0
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the received data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
2 BE RO 0
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Bit/Field Name Type Reset Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
1 PE RO 0
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
0 FE RO 0
Write-Only Error Clear (UARTECR) Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
Offset 0x004
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved WO 0
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
7:0 DATA WO 0
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Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.
UART Flag (UARTFR)
UART0 base: 0x4000.C000
Offset 0x018
Type RO, reset 0x0000.0090
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXFE RXFF TXFF RXFE BUSY reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding
register is empty.
If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO
is empty.
7 TXFE RO 1
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is full.
If the FIFO is enabled, this bit is set when the receive FIFO is full.
6 RXFF RO 0
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding register
is full.
If the FIFO is enabled, this bit is set when the transmit FIFO is full.
5 TXFF RO 0
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is empty.
If the FIFO is enabled, this bit is set when the receive FIFO is empty.
4 RXFE RO 1
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Bit/Field Name Type Reset Description
UART Busy
When this bit is 1, the UART is busy transmitting data. This bit remains
set until the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
3 BUSY RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0 reserved RO 0
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Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor
value used to generate the IrLPBaud16 signal by dividing down the system clock (SysClk). All the
bits are cleared to 0 when reset.
The IrLPBaud16 internal signal is generated by dividing down the UARTCLK signal according to
the low-power divisor value written to UARTILPR. The low-power divisor value is calculated as
follows:
ILPDVSR = SysClk / FIrLPBaud16
where FIrLPBaud16 is nominally 1.8432 MHz.
IrLPBaud16 is an internal signal used for SIR pulse generation when low-power mode is used.
You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power
pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency
of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that
pulses greater than 1.4 μs are accepted as valid pulses.
Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
UART IrDA Low-Power Register (UARTILPR)
UART0 base: 0x4000.C000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ILPDVSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
IrDA Low-Power Divisor
This is an 8-bit low-power divisor value.
7:0 ILPDVSR R/W 0x00
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Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 233
for configuration details.
UART Integer Baud-Rate Divisor (UARTIBRD)
UART0 base: 0x4000.C000
Offset 0x024
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVINT
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0
15:0 DIVINT R/W 0x0000 Integer Baud-Rate Divisor
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Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 233
for configuration details.
UART Fractional Baud-Rate Divisor (UARTFBRD)
UART0 base: 0x4000.C000
Offset 0x028
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DIVFRAC
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
5:0 DIVFRAC R/W 0x000 Fractional Baud-Rate Divisor
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Register 7: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
UART Line Control (UARTLCRH)
UART0 base: 0x4000.C000
Offset 0x02C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SPS WLEN FEN STP2 EPS PEN BRK
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
7 SPS R/W 0
UART Word Length
The bits indicate the number of data bits transmitted or received in a
frame as follows:
Value Description
0x3 8 bits
0x2 7 bits
0x1 6 bits
0x0 5 bits (default)
6:5 WLEN R/W 0
UART Enable FIFOs
If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO
mode).
When cleared to 0, FIFOs are disabled (Character mode). The FIFOs
become 1-byte-deep holding registers.
4 FEN R/W 0
UART Two Stop Bits Select
If this bit is set to 1, two stop bits are transmitted at the end of a frame.
The receive logic does not check for two stop bits being received.
3 STP2 R/W 0
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Bit/Field Name Type Reset Description
UART Even Parity Select
If this bit is set to 1, even parity generation and checking is performed
during transmission and reception, which checks for an even number
of 1s in data and parity bits.
When cleared to 0, then odd parity is performed, which checks for an
odd number of 1s.
This bit has no effect when parity is disabled by the PEN bit.
2 EPS R/W 0
UART Parity Enable
If this bit is set to 1, parity checking and generation is enabled; otherwise,
parity is disabled and no parity bit is added to the data frame.
1 PEN R/W 0
UART Send Break
If this bit is set to 1, a Low level is continually output on the UnTX output,
after completing transmission of the current character. For the proper
execution of the break command, the software must set this bit for at
least two frames (character periods). For normal use, this bit must be
cleared to 0.
0 BRK R/W 0
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Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are written.
If the UART is disabled during a transmit or receive operation, the current transaction is completed
prior to the UART stopping.
UART Control (UARTCTL)
UART0 base: 0x4000.C000
Offset 0x030
Type R/W, reset 0x0000.0300
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RXE TXE LBE reserved SIRLP SIREN UARTEN
Type RO RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0
UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled. When
the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note: To enable reception, the UARTEN bit must also be set.
9 RXE R/W 1
UART Transmit Enable
If this bit is set to 1, the transmit section of the UART is enabled. When
the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note: To enable transmission, the UARTEN bit must also be set.
8 TXE R/W 1
UART Loop Back Enable
If this bit is set to 1, the UnTX path is fed through the UnRX path.
7 LBE R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:3 reserved RO 0
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Bit/Field Name Type Reset Description
UART SIR Low Power Mode
This bit selects the IrDA encoding mode. If this bit is cleared to 0,
low-level bits are transmitted as an active High pulse with a width of
3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted
with a pulse width which is 3 times the period of the IrLPBaud16 input
signal, regardless of the selected bit rate. Setting this bit uses less power,
but might reduce transmission distances. See page 245 for more
information.
2 SIRLP R/W 0
UART SIR Enable
If this bit is set to 1, the IrDA SIR block is enabled, and the UART will
transmit and receive data using SIR protocol.
1 SIREN R/W 0
UART Enable
If this bit is set to 1, the UART is enabled. When the UART is disabled
in the middle of transmission or reception, it completes the current
character before stopping.
0 UARTEN R/W 0
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Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.
UART Interrupt FIFO Level Select (UARTIFLS)
UART0 base: 0x4000.C000
Offset 0x034
Type R/W, reset 0x0000.0012
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RXIFLSEL TXIFLSEL
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
Value Description
0x0 RX FIFO ≥ 1/8 full
0x1 RX FIFO ≥ ¼ full
0x2 RX FIFO ≥ ½ full (default)
0x3 RX FIFO ≥ ¾ full
0x4 RX FIFO ≥ 7/8 full
0x5-0x7 Reserved
5:3 RXIFLSEL R/W 0x2
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Bit/Field Name Type Reset Description
UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
Value Description
0x0 TX FIFO ≤ 1/8 full
0x1 TX FIFO ≤ ¼ full
0x2 TX FIFO ≤ ½ full (default)
0x3 TX FIFO ≤ ¾ full
0x4 TX FIFO ≤ 7/8 full
0x5-0x7 Reserved
2:0 TXIFLSEL R/W 0x2
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Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to
a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a
0 prevents the raw interrupt signal from being sent to the interrupt controller.
UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OEIM BEIM PEIM FEIM RTIM TXIM RXIM reserved
Type RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
UART Overrun Error Interrupt Mask
On a read, the current mask for the OEIM interrupt is returned.
Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller.
10 OEIM R/W 0
UART Break Error Interrupt Mask
On a read, the current mask for the BEIM interrupt is returned.
Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller.
9 BEIM R/W 0
UART Parity Error Interrupt Mask
On a read, the current mask for the PEIM interrupt is returned.
Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller.
8 PEIM R/W 0
UART Framing Error Interrupt Mask
On a read, the current mask for the FEIM interrupt is returned.
Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller.
7 FEIM R/W 0
UART Receive Time-Out Interrupt Mask
On a read, the current mask for the RTIM interrupt is returned.
Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller.
6 RTIM R/W 0
UART Transmit Interrupt Mask
On a read, the current mask for the TXIM interrupt is returned.
Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller.
5 TXIM R/W 0
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Bit/Field Name Type Reset Description
UART Receive Interrupt Mask
On a read, the current mask for the RXIM interrupt is returned.
Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller.
4 RXIM R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0x00
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Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
Offset 0x03C
Type RO, reset 0x0000.000F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
UART Overrun Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
10 OERIS RO 0
UART Break Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
9 BERIS RO 0
UART Parity Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
8 PERIS RO 0
UART Framing Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
7 FERIS RO 0
UART Receive Time-Out Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
6 RTRIS RO 0
UART Transmit Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
5 TXRIS RO 0
UART Receive Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
4 RXRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0xF
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Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
Offset 0x040
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
UART Overrun Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
10 OEMIS RO 0
UART Break Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
9 BEMIS RO 0
UART Parity Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
8 PEMIS RO 0
UART Framing Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
7 FEMIS RO 0
UART Receive Time-Out Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
6 RTMIS RO 0
UART Transmit Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
5 TXMIS RO 0
UART Receive Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
4 RXMIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0
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Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
Offset 0x044
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OEIC BEIC PEIC FEIC RTIC TXIC RXIC reserved
Type RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
Overrun Error Interrupt Clear
The OEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
10 OEIC W1C 0
Break Error Interrupt Clear
The BEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
9 BEIC W1C 0
Parity Error Interrupt Clear
The PEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
8 PEIC W1C 0
Framing Error Interrupt Clear
The FEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
7 FEIC W1C 0
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Bit/Field Name Type Reset Description
Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
6 RTIC W1C 0
Transmit Interrupt Clear
The TXIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
5 TXIC W1C 0
Receive Interrupt Clear
The RXIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
4 RXIC W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0 reserved RO 0x00
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Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 4 (UARTPeriphID4)
UART0 base: 0x4000.C000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID4 RO 0x0000
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Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 5 (UARTPeriphID5)
UART0 base: 0x4000.C000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID5 RO 0x0000
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Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 6 (UARTPeriphID6)
UART0 base: 0x4000.C000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID6 RO 0x0000
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Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 7 (UARTPeriphID7)
UART0 base: 0x4000.C000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID7 RO 0x0000
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Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 0 (UARTPeriphID0)
UART0 base: 0x4000.C000
Offset 0xFE0
Type RO, reset 0x0000.0011
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID0 RO 0x11
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Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 1 (UARTPeriphID1)
UART0 base: 0x4000.C000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID1 RO 0x00
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Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 2 (UARTPeriphID2)
UART0 base: 0x4000.C000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID2 RO 0x18
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Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 3 (UARTPeriphID3)
UART0 base: 0x4000.C000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID3 RO 0x01
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Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 0 (UARTPCellID0)
UART0 base: 0x4000.C000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
7:0 CID0 RO 0x0D
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Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 1 (UARTPCellID1)
UART0 base: 0x4000.C000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
7:0 CID1 RO 0xF0
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Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 2 (UARTPCellID2)
UART0 base: 0x4000.C000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
7:0 CID2 RO 0x05
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Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 3 (UARTPCellID3)
UART0 base: 0x4000.C000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
UART PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
7:0 CID3 RO 0xB1
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12 Synchronous Serial Interface (SSI)
The Stellaris® Synchronous Serial Interface (SSI) is a master or slave interface for synchronous
serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas
Instruments synchronous serial interfaces.
The Stellaris® SSI module has the following features:
■ Master or slave operation
■ Programmable clock bit rate and prescale
■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
12.1 Block Diagram
Figure 12-1. SSI Module Block Diagram
Transmit/
Receive
Logic
Clock
Prescaler
SSICPSR
Control / Status
SSICR0
SSICR1
SSISR
Interrupt Control
SSIIM
SSIMIS
SSIRIS
SSIICR
SSIDR
TxFIFO
8 x 16
...
RxFIFO
8 x 16
...
System Clock
SSITx
SSIRx
SSIClk
SSIFss
Interrupt
Identification Registers
SSIPCellID0 SSIPeriphID0 SSIPeriphID4
SSIPCellID1 SSIPeriphID1 SSIPeriphID5
SSIPCellID2 SSIPeriphID2 SSIPeriphID6
SSIPCellID3 SSIPeriphID3 SSIPeriphID7
12.2 Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
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internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes.
12.2.1 Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the 25-MHz input clock. The clock is first divided by
an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 291). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 284).
The frequency of the output clock SSIClk is defined by:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
Note that although the SSIClk transmit clock can theoretically be 12.5 MHz, the module may not
be able to operate at that speed. For master mode, the system clock must be at least two times
faster than the SSIClk. For slave mode, the system clock must be at least 12 times faster than the
SSIClk.
See “Synchronous Serial Interface (SSI)” on page 422 to view SSI timing parameters.
12.2.2 FIFO Operation
12.2.2.1 Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 288), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
12.2.2.2 Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
12.2.3 Interrupts
The SSI can generate interrupts when the following conditions are observed:
■ Transmit FIFO service
■ Receive FIFO service
■ Receive FIFO time-out
■ Receive FIFO overrun
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All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
can only generate a single interrupt request to the controller at any given time. You can mask each
of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask
(SSIIM) register (see page 292). Setting the appropriate mask bit to 1 enables the interrupt.
Provision of the individual outputs, as well as a combined interrupt output, allows use of either a
global interrupt service routine, or modular device drivers to handle interrupts. The transmit and
receive dynamic dataflow interrupts have been separated from the status interrupts so that data
can be read or written in response to the FIFO trigger levels. The status of the individual interrupt
sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status
(SSIMIS) registers (see page 294 and page 295, respectively).
12.2.4 Frame Formats
Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. There are three basic frame types that can be selected:
■ Texas Instruments synchronous serial
■ Freescale SPI
■ MICROWIRE
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and
latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique, which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
12.2.4.1 Texas Instruments Synchronous Serial Frame Format
Figure 12-2 on page 275 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
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Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer)
SSIClk
4 to 16 bits
SSIFss
SSITx/SSIRx MSB LSB
In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is
pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data
is shifted onto the SSIRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSIClk after the LSB has been latched.
Figure 12-3 on page 275 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer)
MSB LSB
4 to 16 bits
SSIClk
SSIFss
SSITx/SSIRx
12.2.4.2 Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk
pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not
being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition
before the first data capture edge. When the SPH phase control bit is Low, data is captured on the
first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition.
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12.2.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 12-4 on page 276 and Figure 12-5 on page 276.
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
4 to 16 bits
SSIClk
SSIFss
SSIRx Q
SSITx
MSB
MSB
LSB
LSB
Note: Q is undefined.
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx LSB
SSITx MSB LSB
4 to 16 bits
LSB MSB
MSB
MSB
LSB
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto
the SSIRx input line of the master. The master SSITx output pad is enabled.
One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the
master and slave data have been set, the SSIClk master clock pin goes High after one further half
SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
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serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
12.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
12-6 on page 277, which covers both single and continuous transfers.
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1
4 to 16 bits
SSIClk
SSIFss
SSIRx
SSITx
Q
MSB
Q MSB
LSB
LSB
Note: Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After
a further one half SSIClk period, both master and slave valid data is enabled onto their respective
transmission lines. At the same time, the SSIClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned
to its idle High state one SSIClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
12.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 12-7 on page 278 and Figure 12-8 on page 278.
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Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
4 to 16 bits
SSIClk
SSIFss
SSIRx
SSITx
MSB Q
MSB LSB
LSB
Note: Q is undefined.
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSITx/SSIRx MSB LSB
4 to 16 bits
LSB MSB
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low, which causes slave data to be immediately
transferred onto the SSIRx line of the master. The master SSITx output pad is enabled.
One half period later, valid master data is transferred to the SSITx line. Now that both the master
and slave data have been set, the SSIClk master clock pin becomes Low after one further half
SSIClk period. This means that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss
line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
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12.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
12-9 on page 279, which covers both single and continuous transfers.
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1
4 to 16 bits
SSIClk
SSIFss
SSIRx
SSITx
Q Q
MSB
MSB
LSB
LSB
Note: Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled.
After a further one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until
the final bit of the last word has been captured, and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
12.2.4.7 MICROWIRE Frame Format
Figure 12-10 on page 280 shows the MICROWIRE frame format, again for a single frame. Figure
12-11 on page 281 shows the same format when back-to-back frames are transmitted.
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Figure 12-10. MICROWIRE Frame Format (Single Frame)
SSIClk
SSIFss
SSIRx MSB LSB
4 to 16 bits
output data
0
SSITx MSB LSB
8-bit control
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
full-duplex, using a master-slave message passing technique. Each serial transmission begins with
an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss
causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the
SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains
tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of
each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a
one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven
onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising
edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one
clock period after the last bit has been latched in the receive serial shifter, which causes the data
to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk
after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer.
However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs
back-to-back. The control byte of the next frame follows directly after the LSB of the received data
from the current frame. Each of the received values is transferred from the receive shifter on the
falling edge of SSIClk, after the LSB of the frame has been latched into the SSI.
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Figure 12-11. MICROWIRE Frame Format (Continuous Transfer)
8-bit control
SSIClk
SSIFss
SSIRx MSB LSB
4 to 16 bits
output data
0
SSITx LSB MSB LSB
MSB
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
Figure 12-12 on page 281 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
SSIClk
SSIFss
SSIRx
First RX data to be
sampled by SSI slave
tSetup=(2*tSSIClk)
tHold=tSSIClk
12.3 Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the clock prescale divisor by writing the SSICPSR register.
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4. Write the SSICR0 register with the following configuration:
■ Serial clock rate (SCR)
■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
■ The data size (DSS)
5. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
■ Master operation
■ Freescale SPI mode (SPO=1, SPH=1)
■ 1 Mbps bit rate
■ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is disabled.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
12.4 Register Map
Table 12-1 on page 282 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■ SSI0: 0x4000.8000
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 12-1. SSI Register Map
See
Offset Name Type Reset Description page
0x000 SSICR0 R/W 0x0000.0000 SSI Control 0 284
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See
Offset Name Type Reset Description page
0x004 SSICR1 R/W 0x0000.0000 SSI Control 1 286
0x008 SSIDR R/W 0x0000.0000 SSI Data 288
0x00C SSISR RO 0x0000.0003 SSI Status 289
0x010 SSICPSR R/W 0x0000.0000 SSI Clock Prescale 291
0x014 SSIIM R/W 0x0000.0000 SSI Interrupt Mask 292
0x018 SSIRIS RO 0x0000.0008 SSI Raw Interrupt Status 294
0x01C SSIMIS RO 0x0000.0000 SSI Masked Interrupt Status 295
0x020 SSIICR W1C 0x0000.0000 SSI Interrupt Clear 296
0xFD0 SSIPeriphID4 RO 0x0000.0000 SSI Peripheral Identification 4 297
0xFD4 SSIPeriphID5 RO 0x0000.0000 SSI Peripheral Identification 5 298
0xFD8 SSIPeriphID6 RO 0x0000.0000 SSI Peripheral Identification 6 299
0xFDC SSIPeriphID7 RO 0x0000.0000 SSI Peripheral Identification 7 300
0xFE0 SSIPeriphID0 RO 0x0000.0022 SSI Peripheral Identification 0 301
0xFE4 SSIPeriphID1 RO 0x0000.0000 SSI Peripheral Identification 1 302
0xFE8 SSIPeriphID2 RO 0x0000.0018 SSI Peripheral Identification 2 303
0xFEC SSIPeriphID3 RO 0x0000.0001 SSI Peripheral Identification 3 304
0xFF0 SSIPCellID0 RO 0x0000.000D SSI PrimeCell Identification 0 305
0xFF4 SSIPCellID1 RO 0x0000.00F0 SSI PrimeCell Identification 1 306
0xFF8 SSIPCellID2 RO 0x0000.0005 SSI PrimeCell Identification 2 307
0xFFC SSIPCellID3 RO 0x0000.00B1 SSI PrimeCell Identification 3 308
12.5 Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
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Register 1: SSI Control 0 (SSICR0), offset 0x000
SSICR0 is control register 0 and contains bit fields that control various functions within the SSI
module. Functionality such as protocol mode, clock rate, and data size are configured in this register.
SSI Control 0 (SSICR0)
SSI0 base: 0x4000.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCR SPH SPO FRF DSS
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
SSI Serial Clock Rate
The value SCR is used to generate the transmit and receive bit rate of
the SSI. The bit rate is:
BR=FSSIClk/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
15:8 SCR R/W 0x0000
SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. It has the most impact on the first bit transmitted by
either allowing or not allowing a clock transition before the first data
capture edge.
When the SPH bit is 0, data is captured on the first clock edge transition.
If SPH is 1, data is captured on the second clock edge transition.
7 SPH R/W 0
SSI Serial Clock Polarity
This bit is only applicable to the Freescale SPI Format.
When the SPO bit is 0, it produces a steady state Low value on the
SSIClk pin. If SPO is 1, a steady state High value is placed on the
SSIClk pin when data is not being transferred.
6 SPO R/W 0
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Bit/Field Name Type Reset Description
SSI Frame Format Select
The FRF values are defined as follows:
Value Frame Format
0x0 Freescale SPI Frame Format
0x1 Texas Intruments Synchronous Serial Frame Format
0x2 MICROWIRE Frame Format
0x3 Reserved
5:4 FRF R/W 0x0
SSI Data Size Select
The DSS values are defined as follows:
Value Data Size
0x0-0x2 Reserved
0x3 4-bit data
0x4 5-bit data
0x5 6-bit data
0x6 7-bit data
0x7 8-bit data
0x8 9-bit data
0x9 10-bit data
0xA 11-bit data
0xB 12-bit data
0xC 13-bit data
0xD 14-bit data
0xE 15-bit data
0xF 16-bit data
3:0 DSS R/W 0x00
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Register 2: SSI Control 1 (SSICR1), offset 0x004
SSICR1 is control register 1 and contains bit fields that control various functions within the SSI
module. Master and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SOD MS SSE LBM
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In multiple-slave
systems, it is possible for the SSI master to broadcast a message to all
slaves in the system while ensuring that only one slave drives data onto
the serial output line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD bit can be
configured so that the SSI slave does not drive the SSITx pin.
The SOD values are defined as follows:
Value Description
0 SSI can drive SSITx output in Slave Output mode.
1 SSI must not drive the SSITx output in Slave mode.
3 SOD R/W 0
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
SSI is disabled (SSE=0).
The MS values are defined as follows:
Value Description
0 Device configured as a master.
1 Device configured as a slave.
2 MS R/W 0
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Bit/Field Name Type Reset Description
SSI Synchronous Serial Port Enable
Setting this bit enables SSI operation.
The SSE values are defined as follows:
Value Description
0 SSI operation disabled.
1 SSI operation enabled.
Note: This bit must be set to 0 before any control registers
are reprogrammed.
1 SSE R/W 0
SSI Loopback Mode
Setting this bit enables Loopback Test mode.
The LBM values are defined as follows:
Value Description
0 Normal serial port operation enabled.
Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.
1
0 LBM R/W 0
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Register 3: SSI Data (SSIDR), offset 0x008
SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO
(pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI
receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed
to by the current FIFO write pointer).
When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written
to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is
loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed
bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
SSI0 base: 0x4000.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0000
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.
15:0 DATA R/W 0x0000
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Register 4: SSI Status (SSISR), offset 0x00C
SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
Offset 0x00C
Type RO, reset 0x0000.0003
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BSY RFF RNE TNF TFE
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 reserved RO 0x00
SSI Busy Bit
The BSY values are defined as follows:
Value Description
0 SSI is idle.
SSI is currently transmitting and/or receiving a frame, or the
transmit FIFO is not empty.
1
4 BSY RO 0
SSI Receive FIFO Full
The RFF values are defined as follows:
Value Description
0 Receive FIFO is not full.
1 Receive FIFO is full.
3 RFF RO 0
SSI Receive FIFO Not Empty
The RNE values are defined as follows:
Value Description
0 Receive FIFO is empty.
1 Receive FIFO is not empty.
2 RNE RO 0
SSI Transmit FIFO Not Full
The TNF values are defined as follows:
Value Description
0 Transmit FIFO is full.
1 Transmit FIFO is not full.
1 TNF RO 1
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Bit/Field Name Type Reset Description
SSI Transmit FIFO Empty
The TFE values are defined as follows:
Value Description
0 Transmit FIFO is not empty.
1 Transmit FIFO is empty.
0 TFE R0 1
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Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
SSICPSR is the clock prescale register and specifies the division factor by which the system clock
must be internally divided before further use.
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CPSDVSR
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254, depending on the
frequency of SSIClk. The LSB always returns 0 on reads.
7:0 CPSDVSR R/W 0x00
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Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding
mask.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXIM RXIM RTIM RORIM
Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SSI Transmit FIFO Interrupt Mask
The TXIM values are defined as follows:
Value Description
0 TX FIFO half-full or less condition interrupt is masked.
1 TX FIFO half-full or less condition interrupt is not masked.
3 TXIM R/W 0
SSI Receive FIFO Interrupt Mask
The RXIM values are defined as follows:
Value Description
0 RX FIFO half-full or more condition interrupt is masked.
1 RX FIFO half-full or more condition interrupt is not masked.
2 RXIM R/W 0
SSI Receive Time-Out Interrupt Mask
The RTIM values are defined as follows:
Value Description
0 RX FIFO time-out interrupt is masked.
1 RX FIFO time-out interrupt is not masked.
1 RTIM R/W 0
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Bit/Field Name Type Reset Description
SSI Receive Overrun Interrupt Mask
The RORIM values are defined as follows:
Value Description
0 RX FIFO overrun interrupt is masked.
1 RX FIFO overrun interrupt is not masked.
0 RORIM R/W 0
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Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
Offset 0x018
Type RO, reset 0x0000.0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXRIS RXRIS RTRIS RORRIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0x00
SSI Transmit FIFO Raw Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
3 TXRIS RO 1
SSI Receive FIFO Raw Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
2 RXRIS RO 0
SSI Receive Time-Out Raw Interrupt Status
Indicates that the receive time-out has occurred, when set.
1 RTRIS RO 0
SSI Receive Overrun Raw Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
0 RORRIS RO 0
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Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
Offset 0x01C
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TXMIS RXMIS RTMIS RORMIS
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:4 reserved RO 0
SSI Transmit FIFO Masked Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
3 TXMIS RO 0
SSI Receive FIFO Masked Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
2 RXMIS RO 0
SSI Receive Time-Out Masked Interrupt Status
Indicates that the receive time-out has occurred, when set.
1 RTMIS RO 0
SSI Receive Overrun Masked Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
0 RORMIS RO 0
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Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
Offset 0x020
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RTIC RORIC
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
SSI Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
0 No effect on interrupt.
1 Clears interrupt.
1 RTIC W1C 0
SSI Receive Overrun Interrupt Clear
The RORIC values are defined as follows:
Value Description
0 No effect on interrupt.
1 Clears interrupt.
0 RORIC W1C 0
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Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 4 (SSIPeriphID4)
SSI0 base: 0x4000.8000
Offset 0xFD0
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID4
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID4 RO 0x00
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Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 5 (SSIPeriphID5)
SSI0 base: 0x4000.8000
Offset 0xFD4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID5
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID5 RO 0x00
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Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 6 (SSIPeriphID6)
SSI0 base: 0x4000.8000
Offset 0xFD8
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID6
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID6 RO 0x00
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Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 7 (SSIPeriphID7)
SSI0 base: 0x4000.8000
Offset 0xFDC
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID7
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID7 RO 0x00
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Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 0 (SSIPeriphID0)
SSI0 base: 0x4000.8000
Offset 0xFE0
Type RO, reset 0x0000.0022
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
7:0 PID0 RO 0x22
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Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 1 (SSIPeriphID1)
SSI0 base: 0x4000.8000
Offset 0xFE4
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
7:0 PID1 RO 0x00
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Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 2 (SSIPeriphID2)
SSI0 base: 0x4000.8000
Offset 0xFE8
Type RO, reset 0x0000.0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
7:0 PID2 RO 0x18
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Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 3 (SSIPeriphID3)
SSI0 base: 0x4000.8000
Offset 0xFEC
Type RO, reset 0x0000.0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
7:0 PID3 RO 0x01
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Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 0 (SSIPCellID0)
SSI0 base: 0x4000.8000
Offset 0xFF0
Type RO, reset 0x0000.000D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
7:0 CID0 RO 0x0D
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Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 1 (SSIPCellID1)
SSI0 base: 0x4000.8000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID1
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
7:0 CID1 RO 0xF0
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Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 2 (SSIPCellID2)
SSI0 base: 0x4000.8000
Offset 0xFF8
Type RO, reset 0x0000.0005
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID2
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
7:0 CID2 RO 0x05
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Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 3 (SSIPCellID3)
SSI0 base: 0x4000.8000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CID3
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x00
SSI PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
7:0 CID3 RO 0xB1
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13 Ethernet Controller
The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and
network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3
specifications and fully supports 10BASE-T and 100BASE-TX standards.
The Ethernet Controller module has the following features:
■ Conforms to the IEEE 802.3-2002 specification
– 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer
interface to the line
– 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler
– Full-featured auto-negotiation
■ Multiple operational modes
– Full- and half-duplex 100 Mbps
– Full- and half-duplex 10 Mbps
– Power-saving and power-down modes
■ Highly configurable
– Programmable MAC address
– LED activity selection
– Promiscuous mode support
– CRC error-rejection control
– User-configurable interrupts
■ Physical media manipulation
– Automatic MDI/MDI-X cross-over correction
– Register-programmable transmit amplitude
– Automatic polarity correction and 10BASE-T signal reception
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13.1 Block Diagram
Figure 13-1. Ethernet Controller Block Diagram
MACISR
MACIACK
MACIMR
Interrupt
Control
MACRCR
MACNPR
Receive
Control
MACTCR
MACITHR
MACTRR
Transmit
Control
Transmit
FIFO
Receive
FIFO
MACIAR0
MACIAR1
Individual
Address
MACMDTX
MACMCR
MACMDVR
MACMAR
MACMDRX
MII
Control
MACDR
Data
Access
TXOP
TXON
RXIP
RXIN
XTLP
XTLN
MDIX
Clock
Reference
Transmit
Encoding
Pulse
Shaping
Receive
Decoding
Clock
Recovery
Auto
Negotiation
Carrier
Sense
MR3
MR0
MR1
MR2
MR4
Media Independent Interface
Management Register Set
MR5
MR18
MR6
MR16
MR17
MR19
MR23
MR24
Collision
Detect System Clock
Interrupt
13.2 Functional Description
As shown in Figure 13-2 on page 310, the Ethernet Controller is functionally divided into two layers
or modules: the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These
correspond to the OSI model layers 2 and 1. The primary interface to the Ethernet Controller is a
simple bus interface to the MAC layer. The MAC layer provides transmit and receive processing for
Ethernet frames. The MAC layer also provides the interface to the PHY module via an internal Media
Independent Interface (MII).
Figure 13-2. Ethernet Controller
Cortex M3
Media Access
Controller
MAC
(Layer 2)
Physical
Layer Entity
PHY
(Layer 1)
Magnetics RJ45
Ethernet Controller
13.2.1 Internal MII Operation
For the MII management interface to function properly, the MDIO signal must be connected through
a 10k Ω pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor will prevent
management transactions on this internal MII to function. Note that it is possible for data transmission
across the MII to still function since the PHY layer will auto-negotiate the link parameters by default.
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For the MII management interface to function properly, the internal clock must be divided down from
the system clock to a frequency no greater than 2.5 MHz. The MACMDV register contains the divider
used for scaling down the system clock. See page 330 for more details about the use of this register.
13.2.2 PHY Configuration/Operation
The Physical Layer (PHY) in the Ethernet Controller includes integrated ENDECs,
scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions.
The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an
adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery.
The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX
applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The
Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external
filter is required.
13.2.2.1 Clock Selection
The PHY has an on-chip crystal oscillator which can also be driven by an external oscillator. In this
mode of operation, a 25-MHz crystal should be connected between the XTALPPHY and XTALNPHY
pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY pin. In this
mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground.
13.2.2.2 Auto-Negotiation
The PHY supports the auto-negotiation functions of Clause 28 of the IEEE 802.3 standard for 10/100
Mbps operation over copper wiring. This function can be enabled via register settings. The
auto-negotiation function defaults to On and the ANEGEN bit in the MR0 register is High after reset.
Software can disable the auto-negotiation function by writing to the ANEGEN bit. The contents of the
MR4 register are sent to the PHY’s link partner during auto-negotiation via fast-link pulse coding.
Once auto-negotiation is complete, the DPLX and RATE bits in the MR18 register reflect the actual
speed and duplex that was chosen. If auto-negotiation fails to establish a link for any reason, the
ANEGF bit in the MR18 register reflects this and auto-negotiation restarts from the beginning. Writing
a 1 to the RANEG bit in the MR0 register also causes auto-negotiation to restart.
13.2.2.3 Polarity Correction
The PHY is capable of either automatic or manual polarity reversal for 10BASE-T and auto-negotiation
functions. Bits 4 and 5 (RVSPOL and APOL) in the MR16 register control this feature. The default is
automatic mode, where APOL is Low and RVSPOL indicates if the detection circuitry has inverted
the input signal. To enter manual mode, APOL should be set High and RVSPOL then controls the
signal polarity.
13.2.2.4 MDI/MDI-X Configuration
The PHY supports the automatic MDI/MDI-X configuration as defined in IEEE 802.3-2002
specification. This eliminates the need for cross-over cables when connecting to another device,
such as a hub. The algorithm is controlled via settings in the MR24 register. Refer to page 352 for
additional details about these settings.
13.2.2.5 LED Indicators
The PHY supports two LED signals that can be used to indicate various states of operation of the
Ethernet Controller. These signals are mapped to the LED0 and LED1 pins. By default, these pins
are configured as GPIO signals (PF3 and PF2). For the PHY layer to drive these signals, they must
be reconfigured to their hardware function. See “General-Purpose Input/Outputs (GPIOs)” on page
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131 for additional details. The function of these pins is programmable via the PHY layer MR23 register.
Refer to page 351 for additonal details on how to program these LED functions.
13.2.3 MAC Configuration/Operation
13.2.3.1 Ethernet Frame Format
Ethernet data is carried by Ethernet frames. The basic frame format is shown in Figure
13-3 on page 312.
Figure 13-3. Ethernet Frame
Preamble SFD Destination Address Source Address Length/
Type Data FCS
7
Bytes
6
Bytes
6
Bytes
2
Bytes
1
Byte
4
Bytes
46 - 1500
Bytes
The seven fields of the frame are transmitted from left to right. The bits within the frame are
transmitted from least to most significant bit.
■ Preamble
The Preamble field is used by the physical layer signaling circuitry to synchronize with the received
frame’s timing. The preamble is 7 octets long.
■ Start Frame Delimiter (SFD)
The SFD field follows the preamble pattern and indicates the start of the frame. Its value is
1010.1011.
■ Destination Address (DA)
This field specifies destination addresses for which the frame is intended. The LSB of the DA
determines whether the address is an individual (0), or group/multicast (1) address.
■ Source Address (SA)
The source address field identifies the station from which the frame was initiated.
■ Length/Type Field
The meaning of this field depends on its numeric value. The first of two octets is most significant.
This field can be interpreted as length or type code. The maximum length of the data field is
1500 octets. If the value of the Length/Type field is less than or equal to 1500 decimal, it indicates
the number of MAC client data octets. If the value of this field is greater than or equal to 1536
decimal, then it is type interpretation. The meaning of the Length/Type field when the value is
between 1500 and 1536 decimal is unspecified by the standard. The MAC module assumes
type interpretation if the value of the Length/Type field is greater than 1500 decimal.
■ Data
The data field is a sequence of 0 to 1500 octets. Full data transparency is provided so any values
can appear in this field. A minimum frame size is required to properly meet the IEEE standard.
If necessary, the data field is extended by appending extra bits (a pad). The pad field can have
a size of 0 to 46 octets. The sum of the data and pad lengths must be a minimum of 46 octets.
The MAC module automatically inserts pads if required, though it can be disabled by a register
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write. For the MAC module core, data sent/received can be larger than 1500 bytes, and no Frame
Too Long error is reported. Instead, a FIFO Overrun error is reported when the frame received
is too large to fit into the Ethernet Controller’s RAM.
■ Frame Check Sequence (FCS)
The frame check sequence carries the cyclic redundancy check (CRC) value. The value of this
field is computed over destination address, source address, length/type, data, and pad fields
using the CRC-32 algorithm. The MAC module computes the FCS value one nibble at a time.
For transmitted frames, this field is automatically inserted by the MAC layer, unless disabled by
the CRC bit in the MACTCTL register. For received frames, this field is automatically checked.
If the FCS does not pass, the frame will not be placed in the RX FIFO, unless the FCS check is
disabled by the BADCRC bit in the MACRCTL register.
13.2.3.2 MAC Layer FIFOs
For Ethernet frame transmission, a 2 KB TX FIFO is provided that can be used to store a single
frame. While the IEEE 802.3 specification limits the size of an Ethernet frame's payload section to
1500 Bytes, the Ethernet Controller places no such limit. The full buffer can be used, for a payload
of up to 2032 bytes.
For Ethernet frame reception, a 2-KB RX FIFO is provided that can be used to store multiple frames,
up to a maximum of 31 frames. If a frame is received and there is insufficient space in the RX FIFO,
an overflow error will be indicated.
For details regarding the TX and RX FIFO layout, refer to Table 13-1 on page 313. Please note the
following difference between TX and RX FIFO layout. For the TX FIFO, the Data Length field in the
first FIFO word refers to the Ethernet frame data payload, as shown in the 5th to nth FIFO positions.
For the RX FIFO, the Frame Length field is the total length of the received Ethernet frame, including
the FCS and Frame Length bytes. Also note that if FCS generation is disabled with the CRC bit in
the MACTCTL register, the last word in the FIFO must be the FCS bytes for the frame that has been
written to the FIFO.
Also note that if the length of the data payload section is not a multiple of 4, the FCS field will overlap
words in the FIFO. However, for the RX FIFO, the beginning of the next frame will always be on a
word boundary.
Table 13-1. TX & RX FIFO Organization
FIFO Word Read/Write Word Bit Fields TX FIFO (Write) RX FIFO (Read)
Sequence
1st 7:0 Data Length LSB Frame Length LSB
15:8 Data Length MSB Frame Length MSB
23:16 DA oct 1
31:24 DA oct 2
2nd 7:0 DA oct 3
15:8 DA oct 4
23:16 DA oct 5
31:24 DA oct 6
3rd 7:0 SA oct 1
15:8 SA oct 2
23:16 SA oct 3
31:24 SA oct 4
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FIFO Word Read/Write Word Bit Fields TX FIFO (Write) RX FIFO (Read)
Sequence
4th 7:0 SA oct 5
15:8 SA oct 6
23:16 Len/Type MSB
31:24 Len/Type LSB
5th to nth 7:0 data oct n
15:8 data oct n+1
23:16 data oct n+2
31:24 data oct n+3
FCS 1 (if the CRC bit in FCS 1
MACCTL is 0)
last 7:0
FCS 2 (if the CRC bit in FCS 2
MACCTL is 0)
15:8
FCS 3 (if the CRC bit in FCS 3
MACCTL is 0)
23:16
FCS 4 (if the CRC bit in FCS 4
MACCTL is 0)
31:24
13.2.3.3 Ethernet Transmission Options
The Ethernet Controller can automatically generate and insert the Frame Check Sequence (FCS)
at the end of the transmit frame. This is controlled by the CRC bit in the MACTCTL register. For test
purposes, in order to generate a frame with an invalid CRC, this feature can be disabled.
The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46
bytes. The Ethernet Controller can be configured to automatically pad the data section if the payload
data section loaded into the FIFO is less than the minimum 46 bytes. This feature is controlled by
the PADEN bit in the MACTCTL register.
At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation
by using the DUPLEX bit in the MACTCTL register.
13.2.3.4 Ethernet Reception Options
Using the BADCRC bit in the MACRCTL register, the Ethernet Controller can be configured to reject
incoming Ethernet frames with an invalid FCS field.
The Ethernet receiver can also be configured for Promiscuous and Multicast modes using the PRMS
and AMUL fields in the MACRCTL register. If these modes are not enabled, only Ethernet frames
with a broadcast address, or frames matching the MAC address programmed into the MACIA0 and
MACIA1 register will be placed into the RX FIFO.
13.2.4 Interrupts
The Ethernet Controller can generate an interrupt for one or more of the following conditions:
■ A frame has been received into an empty RX FIFO
■ A frame transmission error has occurred
■ A frame has been transmitted successfully
■ A frame has been received with no room in the RX FIFO (overrun)
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■ A frame has been received with one or more error conditions (for example, FCS failed)
■ An MII management transaction between the MAC and PHY layers has completed
■ One or more of the following PHY layer conditions occurs:
– Auto-Negotiate Complete
– Remote Fault
– Link Status Change
– Link Partner Acknowledge
– Parallel Detect Fault
– Page Received
– Receive Error
– Jabber Event Detected
13.3 Initialization and Configuration
To use the Ethernet Controller, the peripheral must be enabled by setting the EPHY0 and EMAC0
bits in the RCGC2 register. The following steps can then be used to configure the Ethernet Controller
for basic operation.
1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming
a 20-MHz system clock, the MACDIV value would be 4.
2. Program the MACIA0 and MACIA1 register for address filtering.
3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation
using a value of 0x16.
4. Program the MACRCTL register to reject frames with bad FCS using a value of 0x08.
5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and
MACRCTL registers.
6. To transmit a frame, write the frame into the TX FIFO using the MACDATA register. Then set
the NEWTX bit in the MACTR register to initiate the transmit process. When the NEWTX bit has
been cleared, the TX FIFO will be available for the next transmit frame.
7. To receive a frame, wait for the NPR field in the MACNP register to be non-zero. Then begin
reading the frame from the RX FIFO by using the MACDATA register. When the frame (including
the FCS field) has been read, the NPR field should decrement by one. When there are no more
frames in the RX FIFO, the NPR field will read 0.
13.4 Ethernet Register Map
Table 13-2 on page 316 lists the Ethernet MAC registers. All addresses given are relative to the
Ethernet MAC base address of 0x4004.8000.
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The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY.
The registers are collectively known as the MII Management registers and are detailed in Section
22.2.4 of the IEEE 802.3 specification. Table 13-2 on page 316 also lists these MII Management
registers. All addresses given are absolute and are written directly to the REGADR field of the
MACMCTL register. The format of registers 0 to 15 are defined by the IEEE specification and are
common to all PHY implementations. The only variance allowed is for features that may or may not
be supported by a specific PHY. Registers 16 to 31 are vendor-specific registers, used to support
features that are specific to a vendors PHY implementation. Vendor-specific registers not listed are
reserved.
Table 13-2. Ethernet Register Map
See
Offset Name Type Reset Description page
Ethernet MAC
0x000 MACRIS RO 0x0000.0000 Ethernet MAC Raw Interrupt Status 318
0x000 MACIACK W1C 0x0000.0000 Ethernet MAC Interrupt Acknowledge 320
0x004 MACIM R/W 0x0000.007F Ethernet MAC Interrupt Mask 321
0x008 MACRCTL R/W 0x0000.0008 Ethernet MAC Receive Control 322
0x00C MACTCTL R/W 0x0000.0000 Ethernet MAC Transmit Control 323
0x010 MACDATA R/W 0x0000.0000 Ethernet MAC Data 324
0x014 MACIA0 R/W 0x0000.0000 Ethernet MAC Individual Address 0 326
0x018 MACIA1 R/W 0x0000.0000 Ethernet MAC Individual Address 1 327
0x01C MACTHR R/W 0x0000.003F Ethernet MAC Threshold 328
0x020 MACMCTL R/W 0x0000.0000 Ethernet MAC Management Control 329
0x024 MACMDV R/W 0x0000.0080 Ethernet MAC Management Divider 330
0x02C MACMTXD R/W 0x0000.0000 Ethernet MAC Management Transmit Data 331
0x030 MACMRXD R/W 0x0000.0000 Ethernet MAC Management Receive Data 332
0x034 MACNP RO 0x0000.0000 Ethernet MAC Number of Packets 333
0x038 MACTR R/W 0x0000.0000 Ethernet MAC Transmission Request 334
MII Management
- MR0 R/W 0x3100 Ethernet PHY Management Register 0 – Control 335
- MR1 RO 0x7849 Ethernet PHY Management Register 1 – Status 337
Ethernet PHY Management Register 2 – PHY Identifier 339
- MR2 RO 0x000E 1
Ethernet PHY Management Register 3 – PHY Identifier 340
- MR3 RO 0x7237 2
Ethernet PHYManagement Register 4 – Auto-Negotiation 341
- MR4 R/W 0x01E1 Advertisement
Ethernet PHYManagement Register 5 – Auto-Negotiation 343
- MR5 RO 0x0000 Link Partner Base Page Ability
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See
Offset Name Type Reset Description page
Ethernet PHYManagement Register 6 – Auto-Negotiation 344
- MR6 RO 0x0000 Expansion
Ethernet PHY Management Register 16 – 345
- MR16 R/W 0x0140 Vendor-Specific
Ethernet PHY Management Register 17 – Interrupt 347
- MR17 R/W 0x0000 Control/Status
- MR18 RO 0x0000 Ethernet PHY Management Register 18 – Diagnostic 349
Ethernet PHY Management Register 19 – Transceiver 350
- MR19 R/W 0x4000 Control
Ethernet PHY Management Register 23 – LED 351
- MR23 R/W 0x0010 Configuration
Ethernet PHY Management Register 24 –MDI/MDIX 352
- MR24 R/W 0x00C0 Control
13.5 Ethernet MAC Register Descriptions
The remainder of this section lists and describes the Ethernet MAC registers, in numerical order by
address offset. Also see “MII Management Register Descriptions” on page 334.
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Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000
The MACRIS register is the interrupt status register. On a read, this register gives the current status
value of the corresponding interrupt prior to masking.
Ethernet MAC Raw Interrupt Status (MACRIS)
Base 0x4004.8000
Offset 0x000
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PHYINT MDINT RXER FOV TXEMP TXER RXINT
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x0
PHY Interrupt
When set, indicates that an enabled interrupt in the PHY layer has
occured. MR17 in the PHY must be read to determine the specific PHY
event that triggered this interrupt.
6 PHYINT RO 0x0
MII Transaction Complete
When set, indicates that a transaction (read or write) on the MII interface
has completed successfully.
5 MDINT RO 0x0
Receive Error
This bit indicates that an error was encountered on the receiver. The
possible errors that can cause this interrupt bit to be set are:
■ A receive error occurs during the reception of a frame (100 Mb/s
only).
■ The frame is not an integer number of bytes (dribble bits) due to an
alignment error.
■ The CRC of the frame does not pass the FCS check.
■ The length/type field is inconsistent with the frame data size when
interpreted as a length field.
4 RXER RO 0x0
FIFO Overrrun
When set, indicates that an overrun was encountered on the receive
FIFO.
3 FOV RO 0x0
Transmit FIFO Empty
When set, indicates that the packet was transmitted and that the TX
FIFO is empty.
2 TXEMP RO 0x0
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Bit/Field Name Type Reset Description
Transmit Error
When set, indicates that an error was encountered on the transmitter.
The possible errors that can cause this interrupt bit to be set are:
■ The data length field stored in the TX FIFO exceeds 2032. The
frame is not sent when this error occurs.
■ The retransmission attempts during the backoff process have
exceeded the maximum limit of 16.
1 TXER RO 0x0
Packet Received
When set, indicates that at least one packet has been received and is
stored in the receiver FIFO.
0 RXINT RO 0x0
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Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000
A write of a 1 to any bit position of this register clears the corresponding interrupt bit in the Ethernet
MAC Raw Interrupt Status (MACRIS) register.
Ethernet MAC Interrupt Acknowledge (MACIACK)
Base 0x4004.8000
Offset 0x000
Type W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PHYINT MDINT RXER FOV TXEMP TXER RXINT
Type RO RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x0
Clear PHY Interrupt
A write of a 1 clears the PHYINT interrupt read from the MACRIS
register.
6 PHYINT W1C 0x0
Clear MII Transaction Complete
A write of a 1 clears the MDINT interrupt read from the MACRIS register.
5 MDINT W1C 0x0
Clear Receive Error
A write of a 1 clears the RXER interrupt read from the MACRIS register.
4 RXER W1C 0x0
Clear FIFO Overrun
A write of a 1 clears the FOV interrupt read from the MACRIS register.
3 FOV W1C 0x0
Clear Transmit FIFO Empty
A write of a 1 clears the TXEMP interrupt read from the MACRIS register.
2 TXEMP W1C 0x0
Clear Transmit Error
A write of a 1 clears the TXER interrupt read from the MACRIS register
and resets the TX FIFO write pointer.
1 TXER W1C 0x0
Clear Packet Received
A write of a 1 clears the RXINT interrupt read from the MACRIS register.
0 RXINT W1C 0x0
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Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004
This register allows software to enable/disable Ethernet MAC interrupts. Writing a 0 disables the
interrupt, while writing a 1 enables it.
Ethernet MAC Interrupt Mask (MACIM)
Base 0x4004.8000
Offset 0x004
Type R/W, reset 0x0000.007F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PHYINTM MDINTM RXERM FOVM TXEMPM TXERM RXINTM
Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:7 reserved RO 0x0
Mask PHY Interrupt
This bit masks the PHYINT bit in the MACRIS register from being
asserted.
6 PHYINTM R/W 1
Mask MII Transaction Complete
This bit masks the MDINT bit in the MACRIS register from being
asserted.
5 MDINTM R/W 1
Mask Receive Error
This bit masks the RXER bit in the MACRIS register from being asserted.
4 RXERM R/W 1
Mask FIFO Overrrun
This bit masks the FOV bit in the MACRIS register from being asserted.
3 FOVM R/W 1
Mask Transmit FIFO Empty
This bit masks the TXEMP bit in the MACRIS register from being
asserted.
2 TXEMPM R/W 1
Mask Transmit Error
This bit masks the TXER bit in the MACRIS register from being asserted.
1 TXERM R/W 1
Mask Packet Received
This bit masks the RXINT bit in the MACRIS register from being
asserted.
0 RXINTM R/W 1
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Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008
This register enables software to configure the receive module and control the types of frames that
are received from the physical medium. It is important to note that when the receive module is
enabled, all valid frames with a broadcast address of FF-FF-FF-FF-FF-FF in the Destination Address
field will be received and stored in the RX FIFO, even if the AMUL bit is not set.
Ethernet MAC Receive Control (MACRCTL)
Base 0x4004.8000
Offset 0x008
Type R/W, reset 0x0000.0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RSTFIFO BADCRC PRMS AMUL RXEN
Type RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 reserved RO 0x0
Clear Receive FIFO
When set, clears the receive FIFO. This should be done when software
initialization is performed.
It is recommended that the receiver be disabled (RXEN = 0), and then
the reset initiated (RSTFIFO = 1). This sequence will flush and reset the
RX FIFO.
4 RSTFIFO R/W 0x0
Enable Reject Bad CRC
The BADCRC bit enables the rejection of frames with an incorrectly
calculated CRC.
3 BADCRC R/W 0x1
Enable Promiscuous Mode
The PRMS bit enables Promiscuous mode, which accepts all valid frames,
regardless of the Destination Address.
2 PRMS R/W 0x0
Enable Multicast Frames
The AMUL bit enables the reception of multicast frames from the physical
medium.
1 AMUL R/W 0x0
Enable Receiver
The RXEN bit enables the Ethernet receiver. When this bit is Low, the
receiver is disabled and all frames on the physical medium are ignored.
0 RXEN R/W 0x0
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Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C
This register enables software to configure the transmit module, and control frames are placed onto
the physical medium.
Ethernet MAC Transmit Control (MACTCTL)
Base 0x4004.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DUPLEX reserved CRC PADEN TXEN
Type RO RO RO RO RO RO RO RO RO RO RO R/W RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:5 reserved RO 0x0
Enable Duplex Mode
When set, enables Duplex mode, allowing simultaneous transmission
and reception.
4 DUPLEX R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3 reserved RO 0x0
Enable CRC Generation
When set, enables the automatic generation of the CRC and the
placement at the end of the packet. If this bit is not set, the frames placed
in the TX FIFO will be sent exactly as they are written into the FIFO.
2 CRC R/W 0x0
Enable Packet Padding
When set, enables the automatic padding of packets that do not meet
the minimum frame size.
1 PADEN R/W 0x0
Enable Transmitter
When set, enables the transmitter. When this bit is 0, the transmitter is
disabled.
0 TXEN R/W 0x0
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Register 6: Ethernet MAC Data (MACDATA), offset 0x010
This register enables software to access the TX and RX FIFOs.
Reads from this register return the data stored in the RX FIFO from the location indicated by the
read pointer.
Writes to this register store the data in the TX FIFO at the location indicated by the write pointer.
The write pointer is then auto-incremented to the next TX FIFO location.
There is no mechanism for randomly accessing bytes in either the RX or TX FIFOs. Data must be
read from the RX FIFO sequentially and stored in a buffer for further processing. Once a read has
been performed, the data in the FIFO cannot be re-read. Data must be written to the TX FIFO
sequentially. If an error is made in placing the frame into the TX FIFO, the write pointer can be reset
to the start of the TX FIFO by writing the TXER bit of the MACIACK register and then the data
re-written.
Read-Only Register
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDATA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Receive FIFO Data
The RXDATA bits represent the next four bytes of data stored in the RX
FIFO.
31:0 RXDATA RO 0x0
Write-Only Register
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type WO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDATA
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit/Field Name Type Reset Description
Transmit FIFO Data
The TXDATA bits represent the next four bytes of data to place in the
TX FIFO for transmission.
31:0 TXDATA WO 0x0
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Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014
This register enables software to program the first four bytes of the hardware MAC address of the
Network Interface Card (NIC). (The last two bytes are in MACIA1). The 6-byte IAR is compared
against the incoming Destination Address fields to determine whether the frame should be received.
Ethernet MAC Individual Address 0 (MACIA0)
Base 0x4004.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MACOCT4 MACOCT3
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACOCT2 MACOCT1
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
MAC Address Octet 4
The MACOCT4 bits represent the fourth octet of the MAC address used
to uniquely identify each Ethernet Controller.
31:24 MACOCT4 R/W 0x0
MAC Address Octet 3
The MACOCT3 bits represent the third octet of the MAC address used
to uniquely identify each Ethernet Controller.
23:16 MACOCT3 R/W 0x0
MAC Address Octet 2
The MACOCT2 bits represent the second octet of the MAC address used
to uniquely identify each Ethernet Controller.
15:8 MACOCT2 R/W 0x0
MAC Address Octet 1
The MACOCT1 bits represent the first octet of the MAC address used to
uniquely identify each Ethernet Controller.
7:0 MACOCT1 R/W 0x0
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Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018
This register enables software to program the last two bytes of the hardware MAC address of the
Network Interface Card (NIC). (The first four bytes are in MACIA0). The 6-byte IAR is compared
against the incoming Destination Address fields to determine whether the frame should be received.
Ethernet MAC Individual Address 1 (MACIA1)
Base 0x4004.8000
Offset 0x018
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACOCT6 MACOCT5
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0
MAC Address Octet 6
The MACOCT6 bits represent the sixth octet of the MAC address used
to uniquely identify each Ethernet Controller.
15:8 MACOCT6 R/W 0x0
MAC Address Octet 5
The MACOCT5 bits represent the fifth octet of the MAC address used to
uniquely identify each Ethernet Controller.
7:0 MACOCT5 R/W 0x0
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Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C
This register enables software to set the threshold level at which the transmission of the frame
begins. If the THRESH bits are set to 0x3F, which is the reset value, transmission does not start until
the NEWTX bit is set in the MACTR register. This effectively disables the early transmission feature.
Writing the THRESH bits to any value besides all 1s enables the early transmission feature. Once
the byte count of data in the TX FIFO reaches this level, transmission of the frame begins. When
THRESH is set to all 0s, transmission of the frame begins after 4 bytes (a single write) are stored in
the TX FIFO. Each increment of the THRESH bit field waits for an additional 32 bytes of data (eight
writes) to be stored in the TX FIFO. Therefore, a value of 0x01 would wait for 36 bytes of data to
be written while a value of 0x02 would wait for 68 bytes to be written. In general, early transmission
starts when:
Number of Bytes >= 4 (THRESH x 8 + 1)
Reaching the threshold level has the same effect as setting the NEWTX bit in the MACTR register.
Transmission of the frame begins and then the number of bytes indicated by the Data Length field
is sent out on the physical medium. Because under-run checking is not performed, it is possible
that the tail pointer may reach and pass the write pointer in the TX FIFO. This causes indeterminate
values to be written to the physical medium rather than the end of the frame. Therefore, sufficient
bus bandwidth for writing to the TX FIFO must be guaranteed by the software.
If a frame smaller than the threshold level needs to be sent, the NEWTX bit in the MACTR register
must be set with an explicit write. This initiates the transmission of the frame even though the
threshold limit has not been reached.
If the threshold level is set too small, it is possible for the transmitter to underrun. If this occurs, the
transmit frame is aborted, and a transmit error occurs.
Ethernet MAC Threshold (MACTHR)
Base 0x4004.8000
Offset 0x01C
Type R/W, reset 0x0000.003F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved THRESH
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x0
Threshold Value
The THRESH bits represent the early transmit threshold. Once the amount
of data in the TX FIFO exceeds this value, transmission of the packet
begins.
5:0 THRESH R/W 0x3F
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Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020
This register enables software to control the transfer of data to and from the MII Management
registers in the Ethernet PHY. The address, name, type, reset configuration, and functional description
of each of these registers can be found in Table 13-2 on page 316 and in “MII Management Register
Descriptions” on page 334.
In order to initiate a read transaction from the MII Management registers, the WRITE bit must be
written with a 0 during the same cycle that the START bit is written with a 1.
In order to initiate a write transaction to the MII Management registers, the WRITE bit must be written
with a 1 during the same cycle that the START bit is written with a 1.
Ethernet MAC Management Control (MACMCTL)
Base 0x4004.8000
Offset 0x020
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved REGADR reserved WRITE START
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0
MII Register Address
The REGADR bit field represents the MII Management register address
for the next MII management interface transaction.
7:3 REGADR R/W 0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2 reserved RO 0x0
MII Register Transaction Type
The WRITE bit represents the operation of the next MII management
interface transaction. If WRITE is set, the next operation will be a write;
otherwise, it will be a read.
1 WRITE R/W 0x0
MII Register Transaction Enable
The START bit represents the initiation of the next MII management
interface transaction. When a 1 is written to this bit, the MII register
located at REGADR will be read (WRITE=0) or written (WRITE=1).
0 START R/W 0x0
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Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024
This register enables software to set the clock divider for the Management Data Clock (MDC). This
clock is used to synchronize read and write transactions between the system and the MII Management
registers. The frequency of the MDC clock can be calculated from the following formula:
Fmdc = Fipclk / (2 * (MACMDVR + 1 ))
The clock divider must be written with a value that ensures that the MDC clock will not exceed a
frequency of 2.5 MHz.
Ethernet MAC Management Divider (MACMDV)
Base 0x4004.8000
Offset 0x024
Type R/W, reset 0x0000.0080
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DIV
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:8 reserved RO 0x0
Clock Divider
The DIV bits are used to set the clock divider for the MDC clock used
to transmit data between the MAC and PHY over the serial MII interface.
7:0 DIV R/W 0x80
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Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset
0x02C
This register holds the next value to be written to the MII Management registers.
Ethernet MAC Management Transmit Data (MACMTXD)
Base 0x4004.8000
Offset 0x02C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDTX
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0
MII Register Transmit Data
The MDTX bits represent the data that will be written in the next MII
management transaction.
15:0 MDTX R/W 0x0
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Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset
0x030
This register holds the last value read from the MII Management registers.
Ethernet MAC Management Receive Data (MACMRXD)
Base 0x4004.8000
Offset 0x030
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDRX
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x0
MII Register Receive Data
The MDRX bits represent the data that was read in the previous MII
management transaction.
15:0 MDRX R/W 0x0
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Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034
This register holds the number of frames that are currently in the RX FIFO. When NPR is 0, there
are no frames in the RX FIFO and the RXINT bit is not set. When NPR is any other value, there is
at least one frame in the RX FIFO and the RXINT bit in the MACRIS register is set.
Ethernet MAC Number of Packets (MACNP)
Base 0x4004.8000
Offset 0x034
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved NPR
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x0
Number of Packets in Receive FIFO
The NPR bits represent the number of packets stored in the RX FIFO.
While the NPR field is greater than 0, the RXINT interrupt in the MACRIS
register will be asserted.
5:0 NPR RO 0x0
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Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038
This register enables software to initiate the transmission of the frame currently located in the TX
FIFO to the physical medium. Once the frame has been transmitted to the medium from the TX
FIFO or a transmission error has been encountered, the NEWTX bit is auto-cleared by the hardware.
Ethernet MAC Transmission Request (MACTR)
Base 0x4004.8000
Offset 0x038
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved NEWTX
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x0
New Transmission
When set, the NEWTX bit initiates an Ethernet transmission once the
packet has been placed in the TX FIFO. This bit is cleared once the
transmission has been completed. If early transmission is being used
(see the MACTHR register), this bit does not need to be set.
0 NEWTX R/W 0x0
13.6 MII Management Register Descriptions
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY.
The registers are collectively known as the MII Management registers. All addresses given are
absolute. Addresses not listed are reserved. Also see “Ethernet MAC Register
Descriptions” on page 317.
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Register 16: Ethernet PHY Management Register 0 – Control (MR0), address
0x00
This register enables software to configure the operation of the PHY. The default settings of these
registers are designed to initialize the PHY to a normal operational mode without configuration.
Ethernet PHY Management Register 0 – Control (MR0)
Base 0x4004.8000
Address 0x00
Type R/W, reset 0x3100
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT reserved
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Reset Registers
When set, resets the registers to their default state and reinitializes
internal state machines. Once the reset operation has completed, this
bit is cleared by hardware.
15 RESET R/W 0
Loopback Mode
When set, enables the Loopback mode of operation. The receive circuitry
is isolated from the physical medium and transmissions are sent back
through the receive circuitry instead of the medium.
14 LOOPBK R/W 0
Speed Select
1: Enables the 100 Mb/s mode of operation (100BASE-TX).
0: Enables the 10 Mb/s mode of operation (10BASE-T).
13 SPEEDSL R/W 1
Auto-Negotiation Enable
When set, enables the Auto-Negotiation process.
12 ANEGEN R/W 1
Power Down
When set, places the PHY into a low-power consuming state.
11 PWRDN R/W 0
Isolate
When set, isolates transmit and receive data paths and ignores all
signaling on these buses.
10 ISO R/W 0
Restart Auto-Negotiation
When set, restarts the Auto-Negotiation process. Once the restart has
initiated, this bit is cleared by hardware.
9 RANEG R/W 0
Set Duplex Mode
1: Enables the Full-Duplex mode of operation. This bit can be set by
software in a manual configuration process or by the Auto-Negotiation
process.
0: Enables the Half-Duplex mode of operation.
8 DUPLEX R/W 1
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Bit/Field Name Type Reset Description
Collision Test
When set, enables the Collision Test mode of operation. The COLT bit
asserts after the initiation of a transmission and de-asserts once the
transmission is halted.
7 COLT R/W 0
6:0 reserved R/W 0x00 Write as 0, ignore on read.
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Register 17: Ethernet PHY Management Register 1 – Status (MR1), address
0x01
This register enables software to determine the capabilities of the PHY and perform its initialization
and operation appropriately.
Ethernet PHY Management Register 1 – Status (MR1)
Base 0x4004.8000
Address 0x01
Type RO, reset 0x7849
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved 100X_F 100X_H 10T_F 10T_H reserved MFPS ANEGC RFAULT ANEGA LINK JAB EXTD
Type RO RO RO RO RO RO RO RO RO RO RO RC RO RO RC RO
Reset 0 1 1 1 1 0 0 0 0 1 0 0 1 0 0 1
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15 reserved RO 0
100BASE-TX Full-Duplex Mode
When set, indicates that the PHY is capable of supporting 100BASE-TX
Full-Duplex mode.
14 100X_F RO 1
100BASE-TX Half-Duplex Mode
When set, indicates that the PHY is capable of supporting 100BASE-TX
Half-Duplex mode.
13 100X_H RO 1
10BASE-T Full-Duplex Mode
When set, indicates that the PHY is capable of 10BASE-T Full-Duplex
mode.
12 10T_F RO 1
10BASE-T Half-Duplex Mode
When set, indicates that the PHY is capable of supporting 10BASE-T
Half-Duplex mode.
11 10T_H RO 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10:7 reserved RO 0
Management Frames with Preamble Suppressed
When set, indicates that the Management Interface is capable of
receiving management frames with the preamble suppressed.
6 MFPS RO 1
Auto-Negotiation Complete
When set, indicates that the Auto-Negotiation process has been
completed and that the extended registers defined by the
Auto-Negotiation protocol are valid.
5 ANEGC RO 0
Remote Fault
When set, indicates that a remote fault condition has been detected.
This bit remains set until it is read, even if the condition no longer exists.
4 RFAULT RC 0
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Bit/Field Name Type Reset Description
Auto-Negotiation
When set, indicates that the PHY has the ability to perform
Auto-Negotiation.
3 ANEGA RO 1
Link Made
When set, indicates that a valid link has been established by the PHY.
2 LINK RO 0
Jabber Condition
When set, indicates that a jabber condition has been detected by the
PHY. This bit remains set until it is read, even if the jabber condition no
longer exists.
1 JAB RC 0
Extended Capabilities
When set, indicates that the PHY provides an extended set of capabilities
that can be accessed through the extended register set.
0 EXTD RO 1
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Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2),
address 0x02
This register, along with MR3, provides a 32-bit value indicating the manufacturer, model, and
revision information.
Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2)
Base 0x4004.8000
Address 0x02
Type RO, reset 0x000E
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUI[21:6]
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
Bit/Field Name Type Reset Description
Organizationally Unique Identifier[21:6]
This field, along with the OUI[5:0] field in MR3, makes up the
Organizationally Unique Identifier indicating the PHY manufacturer.
15:0 OUI[21:6] RO 0x000E
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Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3),
address 0x03
This register, along with MR2, provides a 32-bit value indicating the manufacturer, model, and
revision information.
Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3)
Base 0x4004.8000
Address 0x03
Type RO, reset 0x7237
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUI[5:0] MN RN
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1
Bit/Field Name Type Reset Description
Organizationally Unique Identifier[5:0]
This field, along with the OUI[21:6] field in MR2, makes up the
Organizationally Unique Identifier indicating the PHY manufacturer.
15:10 OUI[5:0] RO 0x1C
Model Number
The MN field represents the Model Number of the PHY.
9:4 MN RO 0x23
Revision Number
The RN field represents the Revision Number of the PHY.
3:0 RN RO 0x7
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Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation
Advertisement (MR4), address 0x04
This register provides the advertised abilities of the PHY used during Auto-Negotiation. Bits 8:5
represent the Technology Ability Field bits. This field can be overwritten by software to Auto-Negotiate
to an alternate common technology. Writing to this register has no effect until Auto-Negotiation is
re-initiated.
Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4)
Base 0x4004.8000
Address 0x04
Type R/W, reset 0x01E1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NP reserved RF reserved A3 A2 A1 A0 S[4:0]
Type RO RO R/W RO RO RO RO R/W R/W R/W R/W RO RO RO RO RO
Reset 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1
Bit/Field Name Type Reset Description
Next Page
When set, indicates the PHY is capable of Next Page exchanges to
provide more detailed information on the PHY’s capabilities.
15 NP RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14 reserved RO 0
Remote Fault
When set, indicates to the link partner that a Remote Fault condition
has been encountered.
13 RF R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12:9 reserved RO 0
Technology Ability Field[3]
When set, indicates that the PHY supports the 100Base-TX full-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated with the
RANEG bit in the MR0 register.
8 A3 R/W 1
Technology Ability Field[2]
When set, indicates that the PHY supports the 100Base-T half-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated.
7 A2 R/W 1
Technology Ability Field[1]
When set, indicates that the PHY supports the 10Base-T full-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated.
6 A1 R/W 1
Technology Ability Field[0]
When set, indicates that the PHY supports the 10Base-T half-duplex
signaling protocol. If software wants to ensure that this mode is not used,
this bit can be written to 0 and Auto-Negotiation re-initiated.
5 A0 R/W 1
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Bit/Field Name Type Reset Description
Selector Field
The S[4:0] field encodes 32 possible messages for communicating
between PHYs. This field is hard-coded to 0x01, indicating that the
Stellaris® PHY is IEEE 802.3 compliant.
4:0 S[4:0] RO 0x01
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Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link
Partner Base Page Ability (MR5), address 0x05
This register provides the advertised abilities of the link partner’s PHY that are received and stored
during Auto-Negotiation.
Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5)
Base 0x4004.8000
Address 0x05
Type RO, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NP ACK RF A[7:0] S[4:0]
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Next Page
When set, indicates that the link partner’s PHY is capable of Next page
exchanges to provide more detailed information on the PHY’s
capabilities.
15 NP RO 0
Acknowledge
When set, indicates that the device has successfully received the link
partner’s advertised abilities during Auto-Negotiation.
14 ACK RO 0
Remote Fault
Used as a standard transport mechanism for transmitting simple fault
information.
13 RF RO 0
Technology Ability Field
The A[7:0] field encodes individual technologies that are supported
by the PHY. See the MR4 register.
12:5 A[7:0] RO 0x00
Selector Field
The S[4:0] field encodes possible messages for communicating
between PHYs.
Value Description
0x00 Reserved
0x01 IEEE Std 802.3
0x02 IEEE Std 802.9 ISLAN-16T
0x03 IEEE Std 802.5
0x04 IEEE Std 1394
0x05–0x1F Reserved
4:0 S[4:0] RO 0x00
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Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation
Expansion (MR6), address 0x06
This register enables software to determine the Auto-Negotiation and Next Page capabilities of the
PHY and the link partner after Auto-Negotiation.
Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6)
Base 0x4004.8000
Address 0x06
Type RO, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PDF LPNPA reserved PRX LPANEGA
Type RO RO RO RO RO RO RO RO RO RO RO RC RO RO RC RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:5 reserved RO 0x000
Parallel Detection Fault
When set, indicates that more than one technology has been detected
at link up. This bit is cleared when read.
4 PDF RC 0
Link Partner is Next Page Able
When set, indicates that the link partner is Next Page Able.
3 LPNPA RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2 reserved RO 0x000
New Page Received
When set, indicates that a New Page has been received from the link
partner and stored in the appropriate location. This bit remains set until
the register is read.
1 PRX RC 0
Link Partner is Auto-Negotiation Able
When set, indicates that the Link partner is Auto-Negotiation Able.
0 LPANEGA RO 0
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Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16),
address 0x10
This register enables software to configure the operation of vendor-specific modes of the PHY.
Ethernet PHY Management Register 16 – Vendor-Specific (MR16)
Base 0x4004.8000
Address 0x10
Type R/W, reset 0x0140
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPTR INPOL reserved TXHIM SQEI NL10 reserved APOL RVSPOL reserved PCSBP RXCC
Type R/W R/W RO R/W R/W R/W RO RO RO RO R/W R/W RO RO R/W R/W
Reset 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Repeater Mode
When set, enables the repeater mode of operation. In this mode,
full-duplex is not allowed and the Carrier Sense signal only responds
to receive activity. If the PHY is configured to 10Base-T mode, the SQE
test function is disabled.
15 RPTR R/W 0
Interrupt Polarity
1: Sets the polarity of the PHY interrupt to be active High.
0: Sets the polarity of the PHY interrupt to active Low.
Important: Because the Media Access Controller expects active
Low interrupts from the PHY, this bit must always be
written with a 0 to ensure proper operation.
14 INPOL R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13 reserved RO 0
Transmit High Impedance Mode
When set, enables the transmitter High Impedance mode. In this mode,
the TXOP and TXON transmitter pins are put into a high impedance state.
The RXIP and RXIN pins remain fully functional.
12 TXHIM R/W 0
SQE Inhibit Testing
When set, prohibits 10Base-T SQE testing.
When 0, the SQE testing is performed by generating a Collision pulse
following the completion of the transmission of a frame.
11 SQEI R/W 0
Natural Loopback Mode
When set, enables the 10Base-T Natural Loopback mode. This causes
the transmission data received by the PHY to be looped back onto the
receive data path when 10Base-T mode is enabled.
10 NL10 R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9:6 reserved RO 0x05
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Bit/Field Name Type Reset Description
Auto-Polarity Disable
When set, disables the PHY’s auto-polarity function.
If this bit is 0, the PHY automatically inverts the received signal due to
a wrong polarity connection during Auto-Negotiation if the PHY is in
10Base-T mode.
5 APOL R/W 0
Receive Data Polarity
This bit indicates whether the receive data pulses are being inverted.
If the APOL bit is 0, then the RVSPOL bit is read-only and indicates
whether the auto-polarity circuitry is reversing the polarity. In this case,
a 1 in the RVSPOL bit indicates that the receive data is inverted while a
0 indicates that the receive data is not inverted.
If the APOL bit is 1, then the RVSPOL bit is writable and software can
force the receive data to be inverted. Setting RVSPOL to 1 forces the
receive data to be inverted while a 0 does not invert the receive data.
4 RVSPOL R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:2 reserved RO 0
PCS Bypass
When set, enables the bypass of the PCS and scrambling/descrambling
functions in 100Base-TX mode. This mode is only valid when
Auto-Negotiation is disabled and 100Base-T mode is enabled.
1 PCSBP R/W 0
Receive Clock Control
When set, enables the Receive Clock Control power saving mode if the
PHY is configured in 100Base-TX mode. This mode shuts down the
receive clock when no data is being received from the physical medium
to save power. This mode should not be used when PCSBP is enabled
and is automatically disabled when the LOOPBK bit in the MR0 register
is set.
0 RXCC R/W 0
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Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status
(MR17), address 0x11
This register provides the means for controlling and observing the events, which trigger a PHY
interrupt in the MACRIS register. This register can also be used in a polling mode via the MII Serial
Interface as a means to observe key events within the PHY via one register address. Bits 0 through
7 are status bits, which are each set to logic 1 based on an event. These bits are cleared after the
register is read. Bits 8 through 15 of this register, when set to logic 1, enable their corresponding
bit in the lower byte to signal a PHY interrupt in the MACRIS register.
Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17)
Base 0x4004.8000
Address 0x11
Type R/W, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JABBER_IE RXER_IE PRX_IE PDF_IE LPACK_IELSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INTRXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT ANEGCOMP_INT
Type R/W R/W R/W R/W R/W R/W R/W R/W RC RC RC RC RC RC RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Jabber Interrupt Enable
When set, enables system interrupts when a Jabber condition is detected
by the PHY.
15 JABBER_IE R/W 0
Receive Error Interrupt Enable
When set, enables system interrupts when a receive error is detected
by the PHY.
14 RXER_IE R/W 0
Page Received Interrupt Enable
When set, enables system interrupts when a new page is received by
the PHY.
13 PRX_IE R/W 0
Parallel Detection Fault Interrupt Enable
When set, enables system interrupts when a Parallel Detection Fault is
detected by the PHY.
12 PDF_IE R/W 0
LP Acknowledge Interrupt Enable
When set, enables system interrupts when FLP bursts are received with
the Acknowledge bit during Auto-Negotiation.
11 LPACK_IE R/W 0
Link Status Change Interrupt Enable
When set, enables system interrupts when the Link Status changes
from OK to FAIL.
10 LSCHG_IE R/W 0
Remote Fault Interrupt Enable
When set, enables system interrupts when a Remote Fault condition is
signaled by the link partner.
9 RFAULT_IE R/W 0
Auto-Negotiation Complete Interrupt Enable
When set, enables system interrupts when the Auto-Negotiation
sequence has completed successfully.
8 ANEGCOMP_IE R/W 0
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Bit/Field Name Type Reset Description
Jabber Event Interrupt
When set, indicates that a Jabber event has been detected by the
10Base-T circuitry.
7 JABBER_INT RC 0
Receive Error Interrupt
When set, indicates that a receive error has been detected by the PHY.
6 RXER_INT RC 0
Page Receive Interrupt
When set, indicates that a new page has been received from the link
partner during Auto-Negotiation.
5 PRX_INT RC 0
Parallel Detection Fault Interrupt
When set, indicates that a Parallel Detection Fault has been detected
by the PHY during the Auto-Negotiation process.
4 PDF_INT RC 0
LP Acknowledge Interrupt
When set, indicates that an FLP burst has been received with the
Acknowledge bit set during Auto-Negotiation.
3 LPACK_INT RC 0
Link Status Change Interrupt
When set, indicates that the link status has changed from OK to FAIL.
2 LSCHG_INT RC 0
Remote Fault Interrupt
When set, indicates that a Remote Fault condition has been signaled
by the link partner.
1 RFAULT_INT RC 0
Auto-Negotiation Complete Interrupt
When set, indicates that the Auto-Negotiation sequence has completed
successfully.
0 ANEGCOMP_INT RC 0
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Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18),
address 0x12
This register enables software to diagnose the results of the previous Auto-Negotiation.
Ethernet PHY Management Register 18 – Diagnostic (MR18)
Base 0x4004.8000
Address 0x12
Type RO, reset 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ANEGF DPLX RATE RXSD RX_LOCK reserved
Type RO RO RO RC RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13 reserved RO 0
Auto-Negotiation Failure
When set, indicates that no common technology was found during
Auto-Negotiation and has failed. This bit remains set until read.
12 ANEGF RC 0
Duplex Mode
When set, indicates that Full-Duplex was the highest common
denominator found during the Auto-Negotiation process. Otherwise,
Half-Duplex was the highest common denominator found.
11 DPLX RO 0
Rate
When set, indicates that 100Base-TX was the highest common
denominator found during the Auto-Negotiation process. Otherwise,
10Base-TX was the highest common denominator found.
10 RATE RO 0
Receive Detection
When set, indicates that receive signal detection has occurred (in
100Base-TX mode) or that Manchester-encoded data has been detected
(in 10Base-T mode).
9 RXSD RO 0
Receive PLL Lock
When set, indicates that the Receive PLL has locked onto the receive
signal for the selected speed of operation (10Base-T or 100Base-TX).
8 RX_LOCK RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0 reserved RO 00
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Register 26: Ethernet PHY Management Register 19 – Transceiver Control
(MR19), address 0x13
This register enables software to set the gain of the transmit output to compensate for transformer
loss.
Ethernet PHY Management Register 19 – Transceiver Control (MR19)
Base 0x4004.8000
Address 0x13
Type R/W, reset 0x4000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXO[1:0] reserved
Type R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Transmit Amplitude Selection
The TXO[1:0] field sets the transmit output amplitude to account for
transmit transformer insertion loss.
Value Description
0x0 Gain set for 0.0dB of insertion loss
0x1 Gain set for 0.4dB of insertion loss
0x2 Gain set for 0.8dB of insertion loss
0x3 Gain set for 1.2dB of insertion loss
15:14 TXO[1:0] R/W 1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13:0 reserved RO 0x0
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Register 27: Ethernet PHY Management Register 23 – LED Configuration
(MR23), address 0x17
This register enables software to select the source that will cause the LEDs to toggle.
Ethernet PHY Management Register 23 – LED Configuration (MR23)
Base 0x4004.8000
Address 0x17
Type R/W, reset 0x0010
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved LED1[3:0] LED0[3:0]
Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8 reserved RO 0x0
LED1 Source
The LED1 field selects the source that will toggle the LED1 signal.
Value Description
0x0 Link OK
0x1 RX or TX Activity (Default LED1)
0x2 TX Activity
0x3 RX Activity
0x4 Collision
0x5 100BASE-TX mode
0x6 10BASE-T mode
0x7 Full-Duplex
0x8 Link OK & Blink=RX or TX Activity
7:4 LED1[3:0] R/W 1
LED0 Source
The LED0 field selects the source that will toggle the LED0 signal.
Value Description
0x0 Link OK (Default LED0)
0x1 RX or TX Activity
0x2 TX Activity
0x3 RX Activity
0x4 Collision
0x5 100BASE-TX mode
0x6 10BASE-T mode
0x7 Full-Duplex
0x8 Link OK & Blink=RX or TX Activity
3:0 LED0[3:0] R/W 0
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Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24),
address 0x18
This register enables software to control the behavior of the MDI/MDIX mux and its switching
capabilities.
Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24)
Base 0x4004.8000
Address 0x18
Type R/W, reset 0x00C0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PD_MODEAUTO_SW MDIX MDIX_CM MDIX_SD
Type RO RO RO RO RO RO RO RO R/W R/W R/W RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8 reserved RO 0x0
Parallel Detection Mode
When set, enables the Parallel Detection mode and allows auto-switching
to work when Auto-Negotiation is not enabled.
7 PD_MODE R/W 0
Auto-Switching Enable
When set, enables Auto-Switching of the MDI/MDIX mux.
6 AUTO_SW R/W 0
Auto-Switching Configuration
When set, indicates that the MDI/MDIX mux is in the crossover (MDIX)
configuration.
When 0, it indicates that the mux is in the pass-through (MDI)
configuration.
When the AUTO_SW bit is 1, the MDIX bit is read-only. When the
AUTO_SW bit is 0, the MDIX bit is read/write and can be configured
manually.
5 MDIX R/W 0
Auto-Switching Complete
When set, indicates that the auto-switching sequence has completed.
If 0, it indicates that the sequence has not completed or that
auto-switching is disabled.
4 MDIX_CM RO 0
Auto-Switching Seed
This field provides the initial seed for the switching algorithm. This seed
directly affects the number of attempts [5,4] respectively to write bits
[3:0].
A 0 sets the seed to 0x5.
3:0 MDIX_SD R/W 0
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14 Analog Comparators
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S6110 controller provides three independent integrated analog comparators that can be
configured to drive an output or generate an interrupt.
Note: Not all comparators have the option to drive an output pin. See the Comparator Operating
Mode tables for more information.
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts to cause it to start
capturing a sample sequence.
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14.1 Block Diagram
Figure 14-1. Analog Comparator Module Block Diagram
interrupt
C2+
C2-
output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 2
ACSTAT2
ACCTL2
interrupt
C1-
C1+ output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 1
ACSTAT1
ACCTL1
Voltage
Ref
ACREFCTL
output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 0
ACSTAT0
ACCTL0
C0+
internal
bus
interrupt
C0-
C0o
14.2 Functional Description
Important: It is recommended that the Digital-Input enable (the GPIODEN bit in the GPIO module)
for the analog input pin be disabled to prevent excessive current draw from the I/O
pads.
The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT.
VIN- < VIN+, VOUT = 1
VIN- > VIN+, VOUT = 0
As shown in Figure 14-2 on page 355, the input source for VIN- is an external input. In addition to
an external input, input sources for VIN+ can be the +ve input of comparator 0 or an internal reference.
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Analog Comparators
Figure 14-2. Structure of Comparator Unit
output
-ve input
+ve input
interrupt
internal
bus
+ve input (alternate)
reference input
ACCTL ACSTAT
IntGen
2
1
0
CINV
A comparator is configured through two status/control registers (ACCTL and ACSTAT ). The internal
reference is configured through one control register (ACREFCTL). Interrupt status and control is
configured through three registers (ACMIS, ACRIS, and ACINTEN). The operating modes of the
comparators are shown in the Comparator Operating Mode tables.
Typically, the comparator output is used internally to generate controller interrupts. It may also be
used to drive an external pin.
Important: Certain register bit values must be set before using the analog comparators. The proper
pad configuration for the comparator input and output pins are described in the
Comparator Operating Mode tables.
Table 14-1. Comparator 0 Operating Modes
ACCNTL0 Comparator 0
ASRCP VIN- VIN+ Output Interrupt
00 C0- C0+ C0o/C1+ yes
01 C0- C0+ C0o/C1+ yes
10 C0- Vref C0o/C1+ yes
11 C0- reserved C0o/C1+ yes
Table 14-2. Comparator 1 Operating Modes
ACCNTL1 Comparator 1
ASRCP VIN- VIN+ Output Interrupt
00 C1- C0o/C1+a n/a yes
01 C1- C0+ n/a yes
10 C1- Vref n/a yes
11 C1- reserved n/a yes
a. C0o and C1+ signals share a single pin and may only be used as one or the other.
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Table 14-3. Comparator 2 Operating Modes
ACCNTL2 Comparator 2
ASRCP VIN- VIN+ Output Interrupt
00 C2- C2+ n/a yes
01 C2- C0+ n/a yes
10 C2- Vref n/a yes
11 C2- reserved n/a yes
14.2.1 Internal Reference Programming
The structure of the internal reference is shown in Figure 14-3 on page 356. This is controlled by a
single configuration register (ACREFCTL). Table 14-4 on page 356 shows the programming options
to develop specific internal reference values, to compare an external voltage against a particular
voltage generated internally.
Figure 14-3. Comparator Internal Reference Structure
8R R R
8R
R R
•••
•••
0
Decoder
15 14 1
AVDD
EN
internal
reference
VREF
RNG
Table 14-4. Internal Reference Voltage and ACREFCTL Field Values
ACREFCTL Register Output Reference Voltage Based on VREF Field Value
EN Bit Value RNG Bit Value
0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and VREF=0
for the least noisy ground reference.
EN=0 RNG=X
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ACREFCTL Register Output Reference Voltage Based on VREF Field Value
EN Bit Value RNG Bit Value
Total resistance in ladder is 32 R.
VREF AVDD
R V REF
RT
= × ----------------
VREF AVDD
(VREF + 8)
32
= × ------------------------------
VR EF = 0.825 + 0.103 VREF
The range of internal reference in this mode is 0.825-2.37 V.
EN=1 RNG=0
Total resistance in ladder is 24 R.
VREF AVDD
R V REF
RT
= × ----------------
VREF AVDD
(VREF)
24
= × --------------------
VREF = 0.1375 x VREF
The range of internal reference for this mode is 0.0-2.0625 V.
RNG=1
14.3 Initialization and Configuration
The following example shows how to configure an analog comparator to read back its output value
from an internal register.
1. Enable the analog comparator 0 clock by writing a value of 0x0010.0000 to the RCGC1 register
in the System Control module.
2. In the GPIO module, enable the GPIO port/pin associated with C0- as a GPIO input.
3. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the
value 0x0000.030C.
4. Configure comparator 0 to use the internal voltage reference and to not invert the output on the
C0o pin by writing the ACCTL0 register with the value of 0x0000.040C.
5. Delay for some time.
6. Read the comparator output value by reading the ACSTAT0 register’s OVAL value.
Change the level of the signal input on C0- to see the OVAL value change.
14.4 Register Map
Table 14-5 on page 358 lists the comparator registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Analog Comparator base address of 0x4003.C000.
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Table 14-5. Analog Comparators Register Map
See
Offset Name Type Reset Description page
0x00 ACMIS R/W1C 0x0000.0000 Analog Comparator Masked Interrupt Status 359
0x04 ACRIS RO 0x0000.0000 Analog Comparator Raw Interrupt Status 360
0x08 ACINTEN R/W 0x0000.0000 Analog Comparator Interrupt Enable 361
0x10 ACREFCTL R/W 0x0000.0000 Analog Comparator Reference Voltage Control 362
0x20 ACSTAT0 RO 0x0000.0000 Analog Comparator Status 0 363
0x24 ACCTL0 R/W 0x0000.0000 Analog Comparator Control 0 364
0x40 ACSTAT1 RO 0x0000.0000 Analog Comparator Status 1 363
0x44 ACCTL1 R/W 0x0000.0000 Analog Comparator Control 1 364
0x60 ACSTAT2 RO 0x0000.0000 Analog Comparator Status 2 363
0x64 ACCTL2 R/W 0x0000.0000 Analog Comparator Control 2 364
14.5 Register Descriptions
The remainder of this section lists and describes the Analog Comparator registers, in numerical
order by address offset.
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Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00
This register provides a summary of the interrupt status (masked) of the comparator.
Analog Comparator Masked Interrupt Status (ACMIS)
Base 0x4003.C000
Offset 0x00
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Comparator 2 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
2 IN2 R/W1C 0
Comparator 1 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
1 IN1 R/W1C 0
Comparator 0 Masked Interrupt Status
Gives the masked interrupt state of this interrupt. Write 1 to this bit to
clear the pending interrupt.
0 IN0 R/W1C 0
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Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04
This register provides a summary of the interrupt status (raw) of the comparator.
Analog Comparator Raw Interrupt Status (ACRIS)
Base 0x4003.C000
Offset 0x04
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Comparator 2 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
2.
2 IN2 RO 0
Comparator 1 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
1.
1 IN1 RO 0
Comparator 0 Interrupt Status
When set, indicates that an interrupt has been generated by comparator
0.
0 IN0 RO 0
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Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08
This register provides the interrupt enable for the comparator.
Analog Comparator Interrupt Enable (ACINTEN)
Base 0x4003.C000
Offset 0x08
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IN2 IN1 IN0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:3 reserved RO 0x00
Comparator 2 Interrupt Enable
When set, enables the controller interrupt from the comparator 2 output
2 IN2 R/W 0
Comparator 1 Interrupt Enable
When set, enables the controller interrupt from the comparator 1 output.
1 IN1 R/W 0
Comparator 0 Interrupt Enable
When set, enables the controller interrupt from the comparator 0 output.
0 IN0 R/W 0
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Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset
0x10
This register specifies whether the resistor ladder is powered on as well as the range and tap.
Analog Comparator Reference Voltage Control (ACREFCTL)
Base 0x4003.C000
Offset 0x10
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved EN RNG reserved VREF
Type RO RO RO RO RO RO R/W R/W RO RO RO RO R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:10 reserved RO 0x00
Resistor Ladder Enable
The EN bit specifies whether the resistor ladder is powered on. If 0, the
resistor ladder is unpowered. If 1, the resistor ladder is connected to
the analog VDD.
This bit is reset to 0 so that the internal reference consumes the least
amount of power if not used and programmed.
9 EN R/W 0
Resistor Ladder Range
The RNG bit specifies the range of the resistor ladder. If 0, the resistor
ladder has a total resistance of 32 R. If 1, the resistor ladder has a total
resistance of 24 R.
8 RNG R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4 reserved RO 0x00
Resistor Ladder Voltage Ref
The VREF bit field specifies the resistor ladder tap that is passed through
an analog multiplexer. The voltage corresponding to the tap position is
the internal reference voltage available for comparison. See Table
14-4 on page 356 for some output reference voltage examples.
3:0 VREF R/W 0x00
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Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60
These registers specify the current output value of the comparator.
Analog Comparator Status 0 (ACSTAT0)
Base 0x4003.C000
Offset 0x20
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved OVAL reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Comparator Output Value
The OVAL bit specifies the current output value of the comparator.
1 OVAL RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64
These registers configure the comparator’s input and output.
Analog Comparator Control 0 (ACCTL0)
Base 0x4003.C000
Offset 0x24
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ASRCP reserved ISLVAL ISEN CINV reserved
Type RO RO RO RO RO R/W R/W RO RO RO RO R/W R/W R/W R/W RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:11 reserved RO 0x00
Analog Source Positive
The ASRCP field specifies the source of input voltage to the VIN+ terminal
of the comparator. The encodings for this field are as follows:
Value Function
0x0 Pin value
0x1 Pin value of C0+
0x2 Internal voltage reference
0x3 Reserved
10:9 ASRCP R/W 0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8:5 reserved RO 0
Interrupt Sense Level Value
The ISLVAL bit specifies the sense value of the input that generates
an interrupt if in Level Sense mode. If 0, an interrupt is generated if the
comparator output is Low. Otherwise, an interrupt is generated if the
comparator output is High.
4 ISLVAL R/W 0
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Bit/Field Name Type Reset Description
Interrupt Sense
The ISEN field specifies the sense of the comparator output that
generates an interrupt. The sense conditioning is as follows:
Value Function
0x0 Level sense, see ISLVAL
0x1 Falling edge
0x2 Rising edge
0x3 Either edge
3:2 ISEN R/W 0x0
Comparator Output Invert
The CINV bit conditionally inverts the output of the comparator. If 0, the
output of the comparator is unchanged. If 1, the output of the comparator
is inverted prior to being processed by hardware.
1 CINV R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 reserved RO 0
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15 Pulse Width Modulator (PWM)
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
The Stellaris® PWM module consists of one PWM generator block and a control block. The PWM
generator block contains one timer (16-bit down or up/down counter), two PWM comparators, a
PWM signal generator, a dead-band generator, and an interrupt selector. The control block determines
the polarity of the PWM signals, and which signals are passed through to the pins.
The PWM generator block produces two PWM signals that can either be independent signals (other
than being based on the same timer and therefore having the same frequency) or a single pair of
complementary signals with dead-band delays inserted. The output of the PWM generation block
is managed by the output control block before being passed to the device pins.
The Stellaris® PWM module provides a great deal of flexibility. It can generate simple PWM signals,
such as those required by a simple charge pump. It can also generate paired PWM signals with
dead-band delays, such as those required by a half-H bridge driver.
15.1 Block Diagram
Figure 15-1 on page 366 provides a block diagram of a Stellaris® PWM module. The LM3S6110
controller contains one generator block (PWM0) and generates two independent PWM signals or
one paired PWM signal with dead-band delays inserted.
Figure 15-1. PWM Module Block Diagram
Interrupt and
Trigger Generate
PWMnINTEN
PWMnRIS
PWMnISC
PWM Clock
Interrupt
Dead-Band
Generator
PWMnDBCTL
PWMnDBRISE
PWMnDBFALL
PWM Output
Control
PWMENABLE
PWMINVERT
PWMFAULT
PWM
Generator
PWMnGENA
PWMnGENB
pwma
pwmb
Timer
PWMnLOAD
PWMnCOUNT
Comparator A
PWMnCMPA
Comparator B
PWMnCMPB
zero
load
dir
16
cmpA
cmpB
Fault
PWM Generator Block
15.2 Functional Description
15.2.1 PWM Timer
The timer runs in one of two modes: Count-Down mode or Count-Up/Down mode. In Count-Down
mode, the timer counts from the load value to zero, goes back to the load value, and continues
counting down. In Count-Up/Down mode, the timer counts from zero up to the load value, back
down to zero, back up to the load value, and so on. Generally, Count-Down mode is used for
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generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used for generating
center-aligned PWM signals.
The timers output three signals that are used in the PWM generation process: the direction signal
(this is always Low in Count-Down mode, but alternates between Low and High in Count-Up/Down
mode), a single-clock-cycle-width High pulse when the counter is zero, and a single-clock-cycle-width
High pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero
pulse is immediately followed by the load pulse.
15.2.2 PWM Comparators
There are two comparators in the PWM generator that monitor the value of the counter; when either
match the counter, they output a single-clock-cycle-width High pulse. When in Count-Up/Down
mode, these comparators match both when counting up and when counting down; they are therefore
qualified by the counter direction signal. These qualified pulses are used in the PWM generation
process. If either comparator match value is greater than the counter load value, then that comparator
never outputs a High pulse.
Figure 15-2 on page 367 shows the behavior of the counter and the relationship of these pulses
when the counter is in Count-Down mode. Figure 15-3 on page 368 shows the behavior of the counter
and the relationship of these pulses when the counter is in Count-Up/Down mode.
Figure 15-2. PWM Count-Down Mode
Load
Zero
CompB
CompA
Load
Zero
B
A
Dir
ADown
BDown
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Figure 15-3. PWM Count-Up/Down Mode
Load
Zero
CompB
CompA
Load
Zero
B
A
Dir
BUp
AUp ADown
BDown
15.2.3 PWM Signal Generator
The PWM generator takes these pulses (qualified by the direction signal), and generates two PWM
signals. In Count-Down mode, there are four events that can affect the PWM signal: zero, load,
match A down, and match B down. In Count-Up/Down mode, there are six events that can affect
the PWM signal: zero, load, match A down, match A up, match B down, and match B up. The match
A or match B events are ignored when they coincide with the zero or load events. If the match A
and match B events coincide, the first signal, PWMA, is generated based only on the match A event,
and the second signal, PWMB, is generated based only on the match B event.
For each event, the effect on each output PWM signal is programmable: it can be left alone (ignoring
the event), it can be toggled, it can be driven Low, or it can be driven High. These actions can be
used to generate a pair of PWM signals of various positions and duty cycles, which do or do not
overlap. Figure 15-4 on page 368 shows the use of Count-Up/Down mode to generate a pair of
center-aligned, overlapped PWM signals that have different duty cycles.
Figure 15-4. PWM Generation Example In Count-Up/Down Mode
Load
Zero
CompB
CompA
PWMB
PWMA
In this example, the first generator is set to drive High on match A up, drive Low on match A down,
and ignore the other four events. The second generator is set to drive High on match B up, drive
Low on match B down, and ignore the other four events. Changing the value of comparator A
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changes the duty cycle of the PWMA signal, and changing the value of comparator B changes the
duty cycle of the PWMB signal.
15.2.4 Dead-Band Generator
The two PWM signals produced by the PWM generator are passed to the dead-band generator. If
disabled, the PWM signals simply pass through unmodified. If enabled, the second PWM signal is
lost and two PWM signals are generated based on the first PWM signal. The first output PWM signal
is the input signal with the rising edge delayed by a programmable amount. The second output
PWM signal is the inversion of the input signal with a programmable delay added between the falling
edge of the input signal and the rising edge of this new signal.
This is therefore a pair of active High signals where one is always High, except for a programmable
amount of time at transitions where both are Low. These signals are therefore suitable for driving
a half-H bridge, with the dead-band delays preventing shoot-through current from damaging the
power electronics. Figure 15-5 on page 369 shows the effect of the dead-band generator on an input
PWM signal.
Figure 15-5. PWM Dead-Band Generator
Input
PWMA
PWMB
Rising Edge
Delay
Falling Edge
Delay
15.2.5 Interrupt Selector
The PWM generator also takes the same four (or six) counter events and uses them to generate
an interrupt. Any of these events or a set of these events can be selected as a source for an interrupt;
when any of the selected events occur, an interrupt is generated. The selection of events allows
the interrupt to occur at a specific position within the PWM signal. Note that interrupts are based on
the raw events; delays in the PWM signal edges caused by the dead-band generator are not taken
into account.
15.2.6 Synchronization Methods
There is a global reset capability that can reset the counter of the PWM generator.
The counter load values and comparator match values of the PWM generator can be updated in
two ways. The first is immediate update mode, where a new value is used as soon as the counter
reaches zero. By waiting for the counter to reach zero, a guaranteed behavior is defined, and overly
short or overly long output PWM pulses are prevented.
The other update method is synchronous, where the new value is not used until a global synchronized
update signal is asserted, at which point the new value is used as soon as the counter reaches
zero. This second mode allows multiple items to be updated simultaneously without odd effects
during the update; everything runs from the old values until a point at which they all run from the
new values.
15.2.7 Fault Conditions
There are two external conditions that affect the PWM block; the signal input on the Fault pin and
the stalling of the controller by a debugger. There are two mechanisms available to handle such
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conditions: the output signals can be forced into an inactive state and/or the PWM timers can be
stopped.
Each output signal has a fault bit. If set, a fault input signal causes the corresponding output signal
to go into the inactive state. If the inactive state is a safe condition for the signal to be in for an
extended period of time, this keeps the output signal from driving the outside world in a dangerous
manner during the fault condition. A fault condition can also generate a controller interrupt.
Each PWM generator can also be configured to stop counting during a stall condition. The user can
select for the counters to run until they reach zero then stop, or to continue counting and reloading.
A stall condition does not generate a controller interrupt.
15.2.8 Output Control Block
With the PWM generator block producing two raw PWM signals, the output control block takes care
of the final conditioning of the PWM signals before they go to the pins. Via a single register, the set
of PWM signals that are actually enabled to the pins can be modified; this can be used, for example,
to perform commutation of a brushless DC motor with a single register write (and without modifying
the individual PWM generators, which are modified by the feedback control loop). Similarly, fault
control can disable any of the PWM signals as well. A final inversion can be applied to any of the
PWM signals, making them active Low instead of the default active High.
15.3 Initialization and Configuration
The following example shows how to initialize the PWM Generator 0 with a 25-KHz frequency, and
with a 25% duty cycle on the PWM0 pin and a 75% duty cycle on the PWM1 pin. This example assumes
the system clock is 20 MHz.
1. Enable the PWM clock by writing a value of 0x0010.0000 to the RCGC0 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register.
4. Configure the Run-Mode Clock Configuration (RCC) register in the System Control module
to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000).
5. Configure the PWM generator for countdown mode with immediate updates to the parameters.
■ Write the PWM0CTL register with a value of 0x0000.0000.
■ Write the PWM0GENA register with a value of 0x0000.008C.
■ Write the PWM0GENB register with a value of 0x0000.080C.
6. Set the period. For a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM
clock source is 10 MHz; the system clock divided by 2. This translates to 400 clock ticks per
period. Use this value to set the PWM0LOAD register. In Count-Down mode, set the Load field
in the PWM0LOAD register to the requested period minus one.
■ Write the PWM0LOAD register with a value of 0x0000.018F.
7. Set the pulse width of the PWM0 pin for a 25% duty cycle.
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■ Write the PWM0CMPA register with a value of 0x0000.012B.
8. Set the pulse width of the PWM1 pin for a 75% duty cycle.
■ Write the PWM0CMPB register with a value of 0x0000.0063.
9. Start the timers in PWM generator 0.
■ Write the PWM0CTL register with a value of 0x0000.0001.
10. Enable PWM outputs.
■ Write the PWMENABLE register with a value of 0x0000.0003.
15.4 Register Map
Table 15-1 on page 371 lists the PWM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the PWM base address of 0x4002.8000.
Table 15-1. PWM Register Map
See
Offset Name Type Reset Description page
0x000 PWMCTL R/W 0x0000.0000 PWM Master Control 373
0x004 PWMSYNC R/W 0x0000.0000 PWM Time Base Sync 374
0x008 PWMENABLE R/W 0x0000.0000 PWM Output Enable 375
0x00C PWMINVERT R/W 0x0000.0000 PWM Output Inversion 376
0x010 PWMFAULT R/W 0x0000.0000 PWM Output Fault 377
0x014 PWMINTEN R/W 0x0000.0000 PWM Interrupt Enable 378
0x018 PWMRIS RO 0x0000.0000 PWM Raw Interrupt Status 379
0x01C PWMISC R/W1C 0x0000.0000 PWM Interrupt Status and Clear 380
0x020 PWMSTATUS RO 0x0000.0000 PWM Status 381
0x040 PWM0CTL R/W 0x0000.0000 PWM0 Control 382
0x044 PWM0INTEN R/W 0x0000.0000 PWM0 Interrupt Enable 384
0x048 PWM0RIS RO 0x0000.0000 PWM0 Raw Interrupt Status 386
0x04C PWM0ISC R/W1C 0x0000.0000 PWM0 Interrupt Status and Clear 387
0x050 PWM0LOAD R/W 0x0000.0000 PWM0 Load 388
0x054 PWM0COUNT RO 0x0000.0000 PWM0 Counter 389
0x058 PWM0CMPA R/W 0x0000.0000 PWM0 Compare A 390
0x05C PWM0CMPB R/W 0x0000.0000 PWM0 Compare B 391
0x060 PWM0GENA R/W 0x0000.0000 PWM0 Generator A Control 392
0x064 PWM0GENB R/W 0x0000.0000 PWM0 Generator B Control 395
0x068 PWM0DBCTL R/W 0x0000.0000 PWM0 Dead-Band Control 398
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See
Offset Name Type Reset Description page
0x06C PWM0DBRISE R/W 0x0000.0000 PWM0 Dead-Band Rising-Edge Delay 399
0x070 PWM0DBFALL R/W 0x0000.0000 PWM0 Dead-Band Falling-Edge-Delay 400
15.5 Register Descriptions
The remainder of this section lists and describes the PWM registers, in numerical order by address
offset.
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Register 1: PWM Master Control (PWMCTL), offset 0x000
This register provides master control over the PWM generation block.
PWM Master Control (PWMCTL)
Base 0x4002.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved GlobalSync0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Update PWM Generator 0
Setting this bit causes any queued update to a load or comparator
register in PWM generator 0 to be applied the next time the
corresponding counter becomes zero. This bit automatically clears when
the updates have completed; it cannot be cleared by software.
0 GlobalSync0 R/W 0
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Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004
This register provides a method to perform synchronization of the counters in the PWM generation
blocks. Writing a bit in this register to 1 causes the specified counter to reset back to 0; writing
multiple bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred;
reading them back as zero indicates that the synchronization has completed.
PWM Time Base Sync (PWMSYNC)
Base 0x4002.8000
Offset 0x004
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Sync0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Reset Generator 0 Counter
Performs a reset of the PWM generator 0 counter.
0 Sync0 R/W 0
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Register 3: PWM Output Enable (PWMENABLE), offset 0x008
This register provides a master control of which generated PWM signals are output to device pins.
By disabling a PWM output, the generation process can continue (for example, when the time bases
are synchronized) without driving PWM signals to the pins. When bits in this register are set, the
corresponding PWM signal is passed through to the output stage, which is controlled by the
PWMINVERT register. When bits are not set, the PWM signal is replaced by a zero value which is
also passed to the output stage.
PWM Output Enable (PWMENABLE)
Base 0x4002.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWM1En PWM0En
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
PWM1 Output Enable
When set, allows the generated PWM1 signal to be passed to the device
pin.
1 PWM1En R/W 0
PWM0 Output Enable
When set, allows the generated PWM0 signal to be passed to the device
pin.
0 PWM0En R/W 0
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Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C
This register provides a master control of the polarity of the PWM signals on the device pins. The
PWM signals generated by the PWM generator are active High; they can optionally be made active
Low via this register. Disabled PWM channels are also passed through the output inverter (if so
configured) so that inactive channels maintain the correct polarity.
PWM Output Inversion (PWMINVERT)
Base 0x4002.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PWM1Inv PWM0Inv
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
Invert PWM1 Signal
When set, the generated PWM1 signal is inverted.
1 PWM1Inv R/W 0
Invert PWM0 Signal
When set, the generated PWM0 signal is inverted.
0 PWM0Inv R/W 0
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Register 5: PWM Output Fault (PWMFAULT), offset 0x010
This register controls the behavior of the PWM outputs in the presence of fault conditions. Both the
fault input and debug events are considered fault conditions. On a fault condition, each PWM signal
can either be passed through unmodified or driven Low. For outputs that are configured for
pass-through, the debug event handling on the corresponding PWM generator also determines if
the PWM signal continues to be generated.
Fault condition control happens before the output inverter, so PWM signals driven Low on fault are
inverted if the channel is configured for inversion (therefore, the pin is driven High on a fault condition).
PWM Output Fault (PWMFAULT)
Base 0x4002.8000
Offset 0x010
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Fault1 Fault0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:2 reserved RO 0x00
PWM1 Driven Low on Fault
When set, the PWM1 output signal is driven Low on a fault condition.
1 Fault1 R/W 0
PWM0 Driven Low on Fault
When set, the PWM0 output signal is driven Low on a fault condition.
0 Fault0 R/W 0
November 30, 2007 377
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LM3S6110 Microcontroller
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014
This register controls the global interrupt generation capabilities of the PWM module. The events
that can cause an interrupt are the fault input and the individual interrupts from the PWM generator.
PWM Interrupt Enable (PWMINTEN)
Base 0x4002.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved IntFault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntPWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:17 reserved RO 0x00
Fault Interrupt Enable
When 1, an interrupt occurs when the fault input is asserted.
16 IntFault R/W 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:1 reserved RO 0x00
PWM0 Interrupt Enable
When 1, an interrupt occurs when the PWM generator 0 block asserts
an interrupt.
0 IntPWM0 R/W 0
378 November 30, 2007
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Pulse Width Modulator (PWM)
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller. The fault interrupt is latched on detection;
it must be cleared through the PWM Interrupt Status and Clear (PWMISC) register (see page 380).
The PWM generator interrupts simply reflect the status of the PWM generator; they are cleared via
the interrupt status register in the PWM generator block. Bits set to 1 indicate the events that are
active; a zero bit indicates that the event in question is not active.
PWM Raw Interrupt Status (PWMRIS)
Base 0x4002.8000
Offset 0x018
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved IntFault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntPWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:17 reserved RO 0x00
Fault Interrupt Asserted
Indicates that the fault input has been asserted.
16 IntFault RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:1 reserved RO 0x00
PWM0 Interrupt Asserted
Indicates that the PWM generator 0 block is asserting its interrupt.
0 IntPWM0 RO 0
November 30, 2007 379
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LM3S6110 Microcontroller
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C
This register provides a summary of the interrupt status of the PWM generator block. A bit set to 1
indicates that the generator block is asserting an interrupt. The individual interrupt status registers
must be consulted to determine the reason for the interrupt, and used to clear the interrupt. For the
fault interrupt, a write of 1 to that bit position clears the latched interrupt status.
PWM Interrupt Status and Clear (PWMISC)
Base 0x4002.8000
Offset 0x01C
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved IntFault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntPWM0
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:17 reserved RO 0x00
Fault Interrupt Asserted
Indicates if the fault input is asserting an interrupt.
16 IntFault R/W1C 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:1 reserved RO 0x00
PWM0 Interrupt Status
Indicates if the PWM generator 0 block is asserting an interrupt.
0 IntPWM0 RO 0
380 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Register 9: PWM Status (PWMSTATUS), offset 0x020
This register provides the status of the Fault input signal.
PWM Status (PWMSTATUS)
Base 0x4002.8000
Offset 0x020
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Fault
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Fault Interrupt Status
When set to 1, indicates the fault input is asserted.
0 Fault RO 0
November 30, 2007 381
Preliminary
LM3S6110 Microcontroller
Register 10: PWM0 Control (PWM0CTL), offset 0x040
This register configures the PWM signal generation block. The Register Update mode, Debug mode,
Counting mode, and Block Enable mode are all controlled via this register. The block produces the
PWM signals, which can be either two independent PWM signals (from the same counter), or a
paired set of PWM signals with dead-band delays added.
These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator
0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable
mode are all controlled via these registers. The blocks produce the PWM signals, which can be
either two independent PWM signals (from the same counter), or a paired set of PWM signals with
dead-band delays added.
The PWM0 block produces the PWM0 and PWM1 outputs.
PWM0 Control (PWM0CTL)
Base 0x4002.8000
Offset 0x040
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved CmpBUpdCmpAUpd LoadUpd Debug Mode Enable
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
Comparator B Update Mode
Same as CmpAUpd but for the comparator B register.
5 CmpBUpd R/W 0
Comparator A Update Mode
The Update mode for the comparator A register. If 0, updates to the
register are reflected to the comparator the next time the counter is 0.
If 1, updates to the register are delayed until the next time the counter
is 0 after a synchronous update has been requested through the PWM
Master Control (PWMCTL) register (see page 373).
4 CmpAUpd R/W 0
Load Register Update Mode
The Update mode for the load register. If 0, updates to the register are
reflected to the counter the next time the counter is 0. If 1, updates to
the register are delayed until the next time the counter is 0 after a
synchronous update has been requested through the PWM Master
Control (PWMCTL) register.
3 LoadUpd R/W 0
Debug Mode
The behavior of the counter in Debug mode. If 0, the counter stops
running when it next reaches 0, and continues running again when no
longer in Debug mode. If 1, the counter always runs.
2 Debug R/W 0
382 November 30, 2007
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Pulse Width Modulator (PWM)
Bit/Field Name Type Reset Description
Counter Mode
The mode for the counter. If 0, the counter counts down from the load
value to 0 and then wraps back to the load value (Count-Down mode).
If 1, the counter counts up from 0 to the load value, back down to 0, and
then repeats (Count-Up/Down mode).
1 Mode R/W 0
PWM Block Enable
Master enable for the PWM generation block. If 0, the entire block is
disabled and not clocked. If 1, the block is enabled and produces PWM
signals.
0 Enable R/W 0
November 30, 2007 383
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LM3S6110 Microcontroller
Register 11: PWM0 Interrupt Enable (PWM0INTEN), offset 0x044
This register controls the interrupt generation capabilities of the PWM generator. The events that
can cause an interrupt are:
■ The counter being equal to the load register
■ The counter being equal to zero
■ The counter being equal to the comparator A register while counting up
■ The counter being equal to the comparator A register while counting down
■ The counter being equal to the comparator B register while counting up
■ The counter being equal to the comparator B register while counting down
Any combination of these events can generate either an interrupt.
PWM0 Interrupt Enable (PWM0INTEN)
Base 0x4002.8000
Offset 0x044
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntCmpBDIntCmpBUIntCmpADIntCmpAU IntCntLoad IntCntZero
Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
Interrupt for Counter=Comparator B Down
When 1, an interrupt occurs when the counter matches the comparator B
value and the counter is counting down.
5 IntCmpBD R/W 0
Interrupt for Counter=Comparator B Up
When 1, an interrupt occurs when the counter matches the comparator B
value and the counter is counting up.
4 IntCmpBU R/W 0
Interrupt for Counter=Comparator A Down
When 1, an interrupt occurs when the counter matches the comparator A
value and the counter is counting down.
3 IntCmpAD R/W 0
Interrupt for Counter=Comparator A Up
When 1, an interrupt occurs when the counter matches the comparator A
value and the counter is counting up.
2 IntCmpAU R/W 0
384 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Bit/Field Name Type Reset Description
Interrupt for Counter=Load
When 1, an interrupt occurs when the counter matches the PWMnLOAD
register.
1 IntCntLoad R/W 0
Interrupt for Counter=0
When 1, an interrupt occurs when the counter is 0.
0 IntCntZero R/W 0
November 30, 2007 385
Preliminary
LM3S6110 Microcontroller
Register 12: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller. Bits set to 1 indicate the latched events that
have occurred; a 0 bit indicates that the event in question has not occurred.
PWM0 Raw Interrupt Status (PWM0RIS)
Base 0x4002.8000
Offset 0x048
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntCmpBDIntCmpBUIntCmpADIntCmpAU IntCntLoad IntCntZero
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
Comparator B Down Interrupt Status
Indicates that the counter has matched the comparator B value while
counting down.
5 IntCmpBD RO 0
Comparator B Up Interrupt Status
Indicates that the counter has matched the comparator B value while
counting up.
4 IntCmpBU RO 0
Comparator A Down Interrupt Status
Indicates that the counter has matched the comparator A value while
counting down.
3 IntCmpAD RO 0
Comparator A Up Interrupt Status
Indicates that the counter has matched the comparator A value while
counting up.
2 IntCmpAU RO 0
Counter=Load Interrupt Status
Indicates that the counter has matched the PWMnLOAD register.
1 IntCntLoad RO 0
Counter=0 Interrupt Status
Indicates that the counter has matched 0.
0 IntCntZero RO 0
386 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Register 13: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
This register provides the current set of interrupt sources that are asserted to the controller. Bits set
to 1 indicate the latched events that have occurred; a 0 bit indicates that the event in question has
not occurred. These are R/W1C registers; writing a 1 to a bit position clears the corresponding
interrupt reason.
PWM0 Interrupt Status and Clear (PWM0ISC)
Base 0x4002.8000
Offset 0x04C
Type R/W1C, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IntCmpBDIntCmpBUIntCmpADIntCmpAU IntCntLoad IntCntZero
Type RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:6 reserved RO 0x00
Comparator B Down Interrupt
Indicates that the counter has matched the comparator B value while
counting down.
5 IntCmpBD R/W1C 0
Comparator B Up Interrupt
Indicates that the counter has matched the comparator B value while
counting up.
4 IntCmpBU R/W1C 0
Comparator A Down Interrupt
Indicates that the counter has matched the comparator A value while
counting down.
3 IntCmpAD R/W1C 0
Comparator A Up Interrupt
Indicates that the counter has matched the comparator A value while
counting up.
2 IntCmpAU R/W1C 0
Counter=Load Interrupt
Indicates that the counter has matched the PWMnLOAD register.
1 IntCntLoad R/W1C 0
Counter=0 Interrupt
Indicates that the counter has matched 0.
0 IntCntZero R/W1C 0
November 30, 2007 387
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LM3S6110 Microcontroller
Register 14: PWM0 Load (PWM0LOAD), offset 0x050
This register contains the load value for the PWM counter. Based on the counter mode, either this
value is loaded into the counter after it reaches zero, or it is the limit of up-counting after which the
counter decrements back to zero. If the Load Value Update mode is immediate, this value is used
the next time the counter reaches zero; if the mode is synchronous, it is used the next time the
counter reaches zero after a synchronous update has been requested through the PWM Master
Control (PWMCTL) register (see page 373). If this register is re-written before the actual update
occurs, the previous value is never used and is lost.
PWM0 Load (PWM0LOAD)
Base 0x4002.8000
Offset 0x050
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Load
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Counter Load Value
The counter load value.
15:0 Load R/W 0
388 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Register 15: PWM0 Counter (PWM0COUNT), offset 0x054
This register contains the current value of the PWM counter. When this value matches the load
register, a pulse is output; this can drive the generation of a PWM signal (via the
PWMnGENA/PWMnGENB registers, see page 392 and page 395) or drive an interrupt (via the
PWMnINTEN register, see page 384). A pulse with the same capabilities is generated when this
value is zero.
PWM0 Counter (PWM0COUNT)
Base 0x4002.8000
Offset 0x054
Type RO, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Count
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Counter Value
The current value of the counter.
15:0 Count RO 0x00
November 30, 2007 389
Preliminary
LM3S6110 Microcontroller
Register 16: PWM0 Compare A (PWM0CMPA), offset 0x058
This register contains a value to be compared against the counter . When this value matches the
counter, a pulse is output; this can drive the generation of a PWM signal (via the
PWMnGENA/PWMnGENB registers) or drive an interrupt (via the PWMnINTEN register). If the
value of this register is greater than the PWMnLOAD register (see page 388), then no pulse is ever
output.
If the comparator A update mode is immediate (based on the CmpAUpd bit in the PWMnCTL register),
then this 16-bit CompA value is used the next time the counter reaches zero. If the update mode is
synchronous, it is used the next time the counter reaches zero after a synchronous update has been
requested through the PWM Master Control (PWMCTL) register (see page 373). If this register is
rewritten before the actual update occurs, the previous value is never used and is lost.
PWM0 Compare A (PWM0CMPA)
Base 0x4002.8000
Offset 0x058
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CompA
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Comparator A Value
The value to be compared against the counter.
15:0 CompA R/W 0x00
390 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Register 17: PWM0 Compare B (PWM0CMPB), offset 0x05C
This register contains a value to be compared against the counter. When this value matches the
counter, a pulse is output; this can drive the generation of a PWM signal (via the
PWMnGENA/PWMnGENB registers) or drive an interrupt (via the PWMnINTEN register). If the
value of this register is greater than the PWMnLOAD register, then no pulse is ever output.
IF the comparator B update mode is immediate (based on the CmpBUpd bit in the PWMnCTL
register), then this 16-bit CompB value is used the next time the counter reaches zero. If the update
mode is synchronous, it is used the next time the counter reaches zero after a synchronous update
has been requested through the PWM Master Control (PWMCTL) register (see page 373). If this
register is rewritten before the actual update occurs, the previous value is never used and is lost.
PWM0 Compare B (PWM0CMPB)
Base 0x4002.8000
Offset 0x05C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CompB
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:16 reserved RO 0x00
Comparator B Value
The value to be compared against the counter.
15:0 CompB R/W 0x00
November 30, 2007 391
Preliminary
LM3S6110 Microcontroller
Register 18: PWM0 Generator A Control (PWM0GENA), offset 0x060
This register controls the generation of the PWMnA signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators. When the
counter is running in Count-Down mode, only four of these events occur; when running in
Count-Up/Down mode, all six occur. These events provide great flexibility in the positioning and
duty cycle of the PWM signal that is produced.
The PWM0GENA register controls generation of the PWM0A signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare A action is taken and the compare B action is ignored.
PWM0 Generator A Control (PWM0GENA)
Base 0x4002.8000
Offset 0x060
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Action for Comparator B Down
The action to be taken when the counter matches comparator B while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
11:10 ActCmpBD R/W 0x0
392 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Bit/Field Name Type Reset Description
Action for Comparator B Up
The action to be taken when the counter matches comparator B while
counting up. Occurs only when the Mode bit in the PWMnCTL register
(see page 382) is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
9:8 ActCmpBU R/W 0x0
Action for Comparator A Down
The action to be taken when the counter matches comparator A while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
7:6 ActCmpAD R/W 0x0
Action for Comparator A Up
The action to be taken when the counter matches comparator A while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
5:4 ActCmpAU R/W 0x0
Action for Counter=Load
The action to be taken when the counter matches the load value.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
3:2 ActLoad R/W 0x0
November 30, 2007 393
Preliminary
LM3S6110 Microcontroller
Bit/Field Name Type Reset Description
Action for Counter=0
The action to be taken when the counter is zero.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
1:0 ActZero R/W 0x0
394 November 30, 2007
Preliminary
Pulse Width Modulator (PWM)
Register 19: PWM0 Generator B Control (PWM0GENB), offset 0x064
This register controls the generation of the PWMnB signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators. When the
counter is running in Down mode, only four of these events occur; when running in Up/Down mode,
all six occur. These events provide great flexibility in the positioning and duty cycle of the PWM
signal that is produced.
The PWM0GENB register controls generation of the PWM0B signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare B action is taken and the compare A action is ignored.
PWM0 Generator B Control (PWM0GENB)
Base 0x4002.8000
Offset 0x064
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Action for Comparator B Down
The action to be taken when the counter matches comparator B while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
11:10 ActCmpBD R/W 0x0
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Bit/Field Name Type Reset Description
Action for Comparator B Up
The action to be taken when the counter matches comparator B while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
9:8 ActCmpBU R/W 0x0
Action for Comparator A Down
The action to be taken when the counter matches comparator A while
counting down.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
7:6 ActCmpAD R/W 0x0
Action for Comparator A Up
The action to be taken when the counter matches comparator A while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
5:4 ActCmpAU R/W 0x0
Action for Counter=Load
The action to be taken when the counter matches the load value.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
3:2 ActLoad R/W 0x0
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Bit/Field Name Type Reset Description
Action for Counter=0
The action to be taken when the counter is 0.
The table below defines the effect of the event on the output signal.
Value Description
0x0 Do nothing.
0x1 Invert the output signal.
0x2 Set the output signal to 0.
0x3 Set the output signal to 1.
1:0 ActZero R/W 0x0
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Register 20: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068
The PWM0DBCTL register controls the dead-band generator, which produces the PWM0 and PWM1
signals based on the PWM0A and PWM0B signals. When disabled, the PWM0A signal passes through
to the PWM0 signal and the PWM0B signal passes through to the PWM1 signal. When enabled and
inverting the resulting waveform, the PWM0B signal is ignored; the PWM0 signal is generated by
delaying the rising edge(s) of the PWM0A signal by the value in the PWM0DBRISE register (see
page 399), and the PWM1 signal is generated by delaying the falling edge(s) of the PWM0A signal by
the value in the PWM0DBFALL register (see page 400).
PWM0 Dead-Band Control (PWM0DBCTL)
Base 0x4002.8000
Offset 0x068
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Enable
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:1 reserved RO 0x00
Dead-Band Generator Enable
When set, the dead-band generator inserts dead bands into the output
signals; when clear, it simply passes the PWM signals through.
0 Enable R/W 0
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Register 21: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset
0x06C
The PWM0DBRISE register contains the number of clock ticks to delay the rising edge of the PWM0A
signal when generating the PWM0 signal. If the dead-band generator is disabled through the
PWMnDBCTL register, the PWM0DBRISE register is ignored. If the value of this register is larger
than the width of a High pulse on the input PWM signal, the rising-edge delay consumes the entire
High time of the signal, resulting in no High time on the output. Care must be taken to ensure that
the input High time always exceeds the rising-edge delay.
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE)
Base 0x4002.8000
Offset 0x06C
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RiseDelay
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Dead-Band Rise Delay
The number of clock ticks to delay the rising edge.
11:0 RiseDelay R/W 0
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Register 22: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset
0x070
The PWM0DBFALL register contains the number of clock ticks to delay the falling edge of the
PWM0A signal when generating the PWM1 signal. If the dead-band generator is disabled, this register
is ignored. If the value of this register is larger than the width of a Low pulse on the input PWM
signal, the falling-edge delay consumes the entire Low time of the signal, resulting in no Low time
on the output. Care must be taken to ensure that the input Low time always exceeds the falling-edge
delay.
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL)
Base 0x4002.8000
Offset 0x070
Type R/W, reset 0x0000.0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved FallDelay
Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit/Field Name Type Reset Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
31:12 reserved RO 0x00
Dead-Band Fall Delay
The number of clock ticks to delay the falling edge.
11:0 FallDelay R/W 0x00
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Pulse Width Modulator (PWM)
16 Pin Diagram
Figure 16-1 on page 401 shows the pin diagram and pin-to-signal-name mapping.
Figure 16-1. Pin Connection Diagram
LM3S6110
38
39
40
41
42
43
44
45
46
47
48
49
50
1 75
26 100
2
27
5
6
3
4
7
8
11
9
10
99
28 98
29 97
30 96
31 95
32 94
33 93
34 92
35 91
36 90
73
72
74
71
69
68
70
67
65
66
12
13
14
17
18
15
16
19
20
23
21
22
24
25
64
37 89
88
87
86
85
84
83
82
81
80
79
78
77
76
63
61
60
62
59
57
56
58
55
53
54
52
51
NC
NC
VDDA
GNDA
NC
NC
LDO
VDD
GND
PD0/PWM0
PD1/PWM1
PD2
PD3
VDD25
GND
XTALPPHY
XTALNPHY
NC
NC
VDD
GND
PC7/C2-
PC6/C2+
PC5/C1+
PC4
PA0/U0Rx
PA1/U0Tx
PA2/SSI0Clk
PA3/SSI0Fss
PA4/SSI0Rx
PA5/SSI0Tx
VDD
GND
PA6/CCP1
NC
VCCPHY
RXIN
VDD25
GND
RXIP
GNDPHY
GNDPHY
TXOP
VDD
GND
TXON
PF0
OSC0
OSC1
NC
NC
NC
NC
GND
VDD
VDD
GND
MDIO
PF3/LED0
PF2/LED1
PF1
VDD25
GND
RST
CMOD0
PB0/CCP0
PB1/CCP2
VDD
GND
PB2
PB3/Fault
NC
NC
NC
NC
CMOD1
PC3/TDO/SWO
PC2/TDI
PC1/TMS/SWDIO
PC0/TCK/SWCLK
VDD
GND
VCCPHY
VCCPHY
GNDPHY
GNDPHY
GND
VDD25
PB7/TRST
PB6/C0+
PB5/C1-
PB4/C0-
VDD
GND
PD4/CCP3
PD5
GNDA
VDDA
PD6
PD7/C0o
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17 Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register.
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
Table 17-1 on page 402 shows the pin-to-signal-name mapping, including functional characteristics
of the signals. Table 17-2 on page 406 lists the signals in alphabetical order by signal name.
Table 17-3 on page 409 groups the signals by functionality, except for GPIOs. Table 17-4 on page
412 lists the GPIO pins and their alternate functionality.
Table 17-1. Signals by Pin Number
Pin Number Pin Name Pin Type Buffer Type Description
1 NC - - No connect
2 NC - - No connect
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
3 VDDA - Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
4 GNDA - Power
5 NC - - No connect
6 NC - - No connect
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 μF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
7 LDO - Power
8 VDD - Power Positive supply for I/O and some logic.
9 GND - Power Ground reference for logic and I/O pins.
10 PD0 I/O TTL GPIO port D bit 0
PWM0 O TTL PWM 0
11 PD1 I/O TTL GPIO port D bit 1
PWM1 O TTL PWM 1
12 PD2 I/O TTL GPIO port D bit 2
13 PD3 I/O TTL GPIO port D bit 3
Positive supply for most of the logic function,
including the processor core and most
peripherals.
14 VDD25 - Power
15 GND - Power Ground reference for logic and I/O pins.
16 XTALPPHY O TTL XTALP of the Ethernet PHY
17 XTALNPHY I TTL XTALN of the Ethernet PHY
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Pin Number Pin Name Pin Type Buffer Type Description
18 NC - - No connect
19 NC - - No connect
20 VDD - Power Positive supply for I/O and some logic.
21 GND - Power Ground reference for logic and I/O pins.
22 PC7 I/O TTL GPIO port C bit 7
C2- I Analog Analog comparator 2 negative input
23 PC6 I/O TTL GPIO port C bit 6
C2+ I Analog Analog comparator positive input
24 PC5 I/O TTL GPIO port C bit 5
C1+ I Analog Analog comparator positive input
25 PC4 I/O TTL GPIO port C bit 4
26 PA0 I/O TTL GPIO port A bit 0
UART module 0 receive. When in IrDA mode,
this signal has IrDA modulation.
U0Rx I TTL
27 PA1 I/O TTL GPIO port A bit 1
UART module 0 transmit. When in IrDA mode,
this signal has IrDA modulation.
U0Tx O TTL
28 PA2 I/O TTL GPIO port A bit 2
SSI0Clk I/O TTL SSI module 0 clock
29 PA3 I/O TTL GPIO port A bit 3
SSI0Fss I/O TTL SSI module 0 frame
30 PA4 I/O TTL GPIO port A bit 4
SSI0Rx I TTL SSI module 0 receive
31 PA5 I/O TTL GPIO port A bit 5
SSI0Tx O TTL SSI module 0 transmit
32 VDD - Power Positive supply for I/O and some logic.
33 GND - Power Ground reference for logic and I/O pins.
34 PA6 I/O TTL GPIO port A bit 6
CCP1 I/O TTL Capture/Compare/PWM 1
35 NC - - No connect
36 VCCPHY I TTL VCC of the Ethernet PHY
37 RXIN I Analog RXIN of the Ethernet PHY
Positive supply for most of the logic function,
including the processor core and most
peripherals.
38 VDD25 - Power
39 GND - Power Ground reference for logic and I/O pins.
40 RXIP I Analog RXIP of the Ethernet PHY
41 GNDPHY I TTL GND of the Ethernet PHY
42 GNDPHY I TTL GND of the Ethernet PHY
43 TXOP O Analog TXOP of the Ethernet PHY
44 VDD - Power Positive supply for I/O and some logic.
45 GND - Power Ground reference for logic and I/O pins.
46 TXON O Analog TXON of the Ethernet PHY
47 PF0 I/O TTL GPIO port F bit 0
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Pin Number Pin Name Pin Type Buffer Type Description
Main oscillator crystal input or an external
clock reference input.
48 OSC0 I Analog
49 OSC1 I Analog Main oscillator crystal output.
50 NC - - No connect
51 NC - - No connect
52 NC - - No connect
53 NC - - No connect
54 GND - Power Ground reference for logic and I/O pins.
55 VDD - Power Positive supply for I/O and some logic.
56 VDD - Power Positive supply for I/O and some logic.
57 GND - Power Ground reference for logic and I/O pins.
58 MDIO I/O TTL MDIO of the Ethernet PHY
59 PF3 I/O TTL GPIO port F bit 3
LED0 O TTL MII LED 0
60 PF2 I/O TTL GPIO port F bit 2
LED1 O TTL MII LED 1
61 PF1 I/O TTL GPIO port F bit 1
Positive supply for most of the logic function,
including the processor core and most
peripherals.
62 VDD25 - Power
63 GND - Power Ground reference for logic and I/O pins.
64 RST I TTL System reset input.
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
65 CMOD0 I/O TTL
66 PB0 I/O TTL GPIO port B bit 0
CCP0 I/O TTL Capture/Compare/PWM 0
67 PB1 I/O TTL GPIO port B bit 1
CCP2 I/O TTL Capture/Compare/PWM 2
68 VDD - Power Positive supply for I/O and some logic.
69 GND - Power Ground reference for logic and I/O pins.
70 PB2 I/O TTL GPIO port B bit 2
71 PB3 I/O TTL GPIO port B bit 3
Fault I TTL PWM Fault
72 NC - - No connect
73 NC - - No connect
74 NC - - No connect
75 NC - - No connect
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
76 CMOD1 I/O TTL
77 PC3 I/O TTL GPIO port C bit 3
TDO O TTL JTAG TDO and SWO
SWO O TTL JTAG TDO and SWO
78 PC2 I/O TTL GPIO port C bit 2
TDI I TTL JTAG TDI
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Signal Tables
Pin Number Pin Name Pin Type Buffer Type Description
79 PC1 I/O TTL GPIO port C bit 1
TMS I/O TTL JTAG TMS and SWDIO
SWDIO I/O TTL JTAG TMS and SWDIO
80 PC0 I/O TTL GPIO port C bit 0
TCK I TTL JTAG/SWD CLK
SWCLK I TTL JTAG/SWD CLK
81 VDD - Power Positive supply for I/O and some logic.
82 GND - Power Ground reference for logic and I/O pins.
83 VCCPHY I TTL VCC of the Ethernet PHY
84 VCCPHY I TTL VCC of the Ethernet PHY
85 GNDPHY I TTL GND of the Ethernet PHY
86 GNDPHY I TTL GND of the Ethernet PHY
87 GND - Power Ground reference for logic and I/O pins.
Positive supply for most of the logic function,
including the processor core and most
peripherals.
88 VDD25 - Power
89 PB7 I/O TTL GPIO port B bit 7
TRST I TTL JTAG TRSTn
90 PB6 I/O TTL GPIO port B bit 6
C0+ I Analog Analog comparator 0 positive input
91 PB5 I/O TTL GPIO port B bit 5
C1- I Analog Analog comparator 1 negative input
92 PB4 I/O TTL GPIO port B bit 4
C0- I Analog Analog comparator 0 negative input
93 VDD - Power Positive supply for I/O and some logic.
94 GND - Power Ground reference for logic and I/O pins.
95 PD4 I/O TTL GPIO port D bit 4
CCP3 I/O TTL Capture/Compare/PWM 3
96 PD5 I/O TTL GPIO port D bit 5
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
97 GNDA - Power
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
98 VDDA - Power
99 PD6 I/O TTL GPIO port D bit 6
100 PD7 I/O TTL GPIO port D bit 7
C0o O TTL Analog comparator 0 output
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Table 17-2. Signals by Signal Name
Pin Name Pin Number Pin Type Buffer Type Description
C0+ 90 I Analog Analog comparator 0 positive input
C0- 92 I Analog Analog comparator 0 negative input
C0o 100 O TTL Analog comparator 0 output
C1+ 24 I Analog Analog comparator positive input
C1- 91 I Analog Analog comparator 1 negative input
C2+ 23 I Analog Analog comparator positive input
C2- 22 I Analog Analog comparator 2 negative input
CCP0 66 I/O TTL Capture/Compare/PWM 0
CCP1 34 I/O TTL Capture/Compare/PWM 1
CCP2 67 I/O TTL Capture/Compare/PWM 2
CCP3 95 I/O TTL Capture/Compare/PWM 3
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD0 65 I/O TTL
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1 76 I/O TTL
Fault 71 I TTL PWM Fault
GND 9 - Power Ground reference for logic and I/O pins.
GND 15 - Power Ground reference for logic and I/O pins.
GND 21 - Power Ground reference for logic and I/O pins.
GND 33 - Power Ground reference for logic and I/O pins.
GND 39 - Power Ground reference for logic and I/O pins.
GND 45 - Power Ground reference for logic and I/O pins.
GND 54 - Power Ground reference for logic and I/O pins.
GND 57 - Power Ground reference for logic and I/O pins.
GND 63 - Power Ground reference for logic and I/O pins.
GND 69 - Power Ground reference for logic and I/O pins.
GND 82 - Power Ground reference for logic and I/O pins.
GND 87 - Power Ground reference for logic and I/O pins.
GND 94 - Power Ground reference for logic and I/O pins.
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
GNDA 4 - Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
GNDA 97 - Power
GNDPHY 41 I TTL GND of the Ethernet PHY
GNDPHY 42 I TTL GND of the Ethernet PHY
GNDPHY 85 I TTL GND of the Ethernet PHY
GNDPHY 86 I TTL GND of the Ethernet PHY
406 November 30, 2007
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Signal Tables
Pin Name Pin Number Pin Type Buffer Type Description
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 μF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
LDO 7 - Power
LED0 59 O TTL MII LED 0
LED1 60 O TTL MII LED 1
MDIO 58 I/O TTL MDIO of the Ethernet PHY
NC 1 - - No connect
NC 2 - - No connect
NC 5 - - No connect
NC 6 - - No connect
NC 18 - - No connect
NC 19 - - No connect
NC 35 - - No connect
NC 50 - - No connect
NC 51 - - No connect
NC 52 - - No connect
NC 53 - - No connect
NC 72 - - No connect
NC 73 - - No connect
NC 74 - - No connect
NC 75 - - No connect
Main oscillator crystal input or an external
clock reference input.
OSC0 48 I Analog
OSC1 49 I Analog Main oscillator crystal output.
PA0 26 I/O TTL GPIO port A bit 0
PA1 27 I/O TTL GPIO port A bit 1
PA2 28 I/O TTL GPIO port A bit 2
PA3 29 I/O TTL GPIO port A bit 3
PA4 30 I/O TTL GPIO port A bit 4
PA5 31 I/O TTL GPIO port A bit 5
PA6 34 I/O TTL GPIO port A bit 6
PB0 66 I/O TTL GPIO port B bit 0
PB1 67 I/O TTL GPIO port B bit 1
PB2 70 I/O TTL GPIO port B bit 2
PB3 71 I/O TTL GPIO port B bit 3
PB4 92 I/O TTL GPIO port B bit 4
PB5 91 I/O TTL GPIO port B bit 5
PB6 90 I/O TTL GPIO port B bit 6
PB7 89 I/O TTL GPIO port B bit 7
PC0 80 I/O TTL GPIO port C bit 0
PC1 79 I/O TTL GPIO port C bit 1
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Pin Name Pin Number Pin Type Buffer Type Description
PC2 78 I/O TTL GPIO port C bit 2
PC3 77 I/O TTL GPIO port C bit 3
PC4 25 I/O TTL GPIO port C bit 4
PC5 24 I/O TTL GPIO port C bit 5
PC6 23 I/O TTL GPIO port C bit 6
PC7 22 I/O TTL GPIO port C bit 7
PD0 10 I/O TTL GPIO port D bit 0
PD1 11 I/O TTL GPIO port D bit 1
PD2 12 I/O TTL GPIO port D bit 2
PD3 13 I/O TTL GPIO port D bit 3
PD4 95 I/O TTL GPIO port D bit 4
PD5 96 I/O TTL GPIO port D bit 5
PD6 99 I/O TTL GPIO port D bit 6
PD7 100 I/O TTL GPIO port D bit 7
PF0 47 I/O TTL GPIO port F bit 0
PF1 61 I/O TTL GPIO port F bit 1
PF2 60 I/O TTL GPIO port F bit 2
PF3 59 I/O TTL GPIO port F bit 3
PWM0 10 O TTL PWM 0
PWM1 11 O TTL PWM 1
RST 64 I TTL System reset input.
RXIN 37 I Analog RXIN of the Ethernet PHY
RXIP 40 I Analog RXIP of the Ethernet PHY
SSI0Clk 28 I/O TTL SSI module 0 clock
SSI0Fss 29 I/O TTL SSI module 0 frame
SSI0Rx 30 I TTL SSI module 0 receive
SSI0Tx 31 O TTL SSI module 0 transmit
SWCLK 80 I TTL JTAG/SWD CLK
SWDIO 79 I/O TTL JTAG TMS and SWDIO
SWO 77 O TTL JTAG TDO and SWO
TCK 80 I TTL JTAG/SWD CLK
TDI 78 I TTL JTAG TDI
TDO 77 O TTL JTAG TDO and SWO
TMS 79 I/O TTL JTAG TMS and SWDIO
TRST 89 I TTL JTAG TRSTn
TXON 46 O Analog TXON of the Ethernet PHY
TXOP 43 O Analog TXOP of the Ethernet PHY
UART module 0 receive. When in IrDA mode,
this signal has IrDA modulation.
U0Rx 26 I TTL
UART module 0 transmit. When in IrDA mode,
this signal has IrDA modulation.
U0Tx 27 O TTL
VCCPHY 36 I TTL VCC of the Ethernet PHY
VCCPHY 83 I TTL VCC of the Ethernet PHY
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Signal Tables
Pin Name Pin Number Pin Type Buffer Type Description
VCCPHY 84 I TTL VCC of the Ethernet PHY
VDD 8 - Power Positive supply for I/O and some logic.
VDD 20 - Power Positive supply for I/O and some logic.
VDD 32 - Power Positive supply for I/O and some logic.
VDD 44 - Power Positive supply for I/O and some logic.
VDD 55 - Power Positive supply for I/O and some logic.
VDD 56 - Power Positive supply for I/O and some logic.
VDD 68 - Power Positive supply for I/O and some logic.
VDD 81 - Power Positive supply for I/O and some logic.
VDD 93 - Power Positive supply for I/O and some logic.
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 14 - Power
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 38 - Power
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 62 - Power
Positive supply for most of the logic function,
including the processor core and most
peripherals.
VDD25 88 - Power
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
VDDA 3 - Power
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
VDDA 98 - Power
XTALNPHY 17 I TTL XTALN of the Ethernet PHY
XTALPPHY 16 O TTL XTALP of the Ethernet PHY
Table 17-3. Signals by Function, Except for GPIO
Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
Analog C0+ 90 I Analog Analog comparator 0 positive input
Comparators C0- 92 I Analog Analog comparator 0 negative input
C0o 100 O TTL Analog comparator 0 output
C1+ 24 I Analog Analog comparator positive input
C1- 91 I Analog Analog comparator 1 negative input
C2+ 23 I Analog Analog comparator positive input
C2- 22 I Analog Analog comparator 2 negative input
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Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
Ethernet PHY GNDPHY 41 I TTL GND of the Ethernet PHY
GNDPHY 42 I TTL GND of the Ethernet PHY
GNDPHY 85 I TTL GND of the Ethernet PHY
GNDPHY 86 I TTL GND of the Ethernet PHY
LED0 59 O TTL MII LED 0
LED1 60 O TTL MII LED 1
MDIO 58 I/O TTL MDIO of the Ethernet PHY
RXIN 37 I Analog RXIN of the Ethernet PHY
RXIP 40 I Analog RXIP of the Ethernet PHY
TXON 46 O Analog TXON of the Ethernet PHY
TXOP 43 O Analog TXOP of the Ethernet PHY
VCCPHY 36 I TTL VCC of the Ethernet PHY
VCCPHY 83 I TTL VCC of the Ethernet PHY
VCCPHY 84 I TTL VCC of the Ethernet PHY
XTALNPHY 17 I TTL XTALN of the Ethernet PHY
XTALPPHY 16 O TTL XTALP of the Ethernet PHY
General-Purpose CCP0 66 I/O TTL Capture/Compare/PWM 0
Timers CCP1 34 I/O TTL Capture/Compare/PWM 1
CCP2 67 I/O TTL Capture/Compare/PWM 2
CCP3 95 I/O TTL Capture/Compare/PWM 3
JTAG/SWD/SWO SWCLK 80 I TTL JTAG/SWD CLK
SWDIO 79 I/O TTL JTAG TMS and SWDIO
SWO 77 O TTL JTAG TDO and SWO
TCK 80 I TTL JTAG/SWD CLK
TDI 78 I TTL JTAG TDI
TDO 77 O TTL JTAG TDO and SWO
TMS 79 I/O TTL JTAG TMS and SWDIO
PWM Fault 71 I TTL PWM Fault
PWM0 10 O TTL PWM 0
PWM1 11 O TTL PWM 1
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Signal Tables
Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
Power GND 9 - Power Ground reference for logic and I/O pins.
GND 15 - Power Ground reference for logic and I/O pins.
GND 21 - Power Ground reference for logic and I/O pins.
GND 33 - Power Ground reference for logic and I/O pins.
GND 39 - Power Ground reference for logic and I/O pins.
GND 45 - Power Ground reference for logic and I/O pins.
GND 54 - Power Ground reference for logic and I/O pins.
GND 57 - Power Ground reference for logic and I/O pins.
GND 63 - Power Ground reference for logic and I/O pins.
GND 69 - Power Ground reference for logic and I/O pins.
GND 82 - Power Ground reference for logic and I/O pins.
GND 87 - Power Ground reference for logic and I/O pins.
GND 94 - Power Ground reference for logic and I/O pins.
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
GNDA 4 - Power
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
GNDA 97 - Power
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 μF or greater. When the on-chip LDO is
used to provide power to the logic, the LDO pin
must also be connected to the VDD25 pins at the
board level in addition to the decoupling
capacitor(s).
LDO 7 - Power
VDD 8 - Power Positive supply for I/O and some logic.
VDD 20 - Power Positive supply for I/O and some logic.
VDD 32 - Power Positive supply for I/O and some logic.
VDD 44 - Power Positive supply for I/O and some logic.
VDD 55 - Power Positive supply for I/O and some logic.
VDD 56 - Power Positive supply for I/O and some logic.
VDD 68 - Power Positive supply for I/O and some logic.
VDD 81 - Power Positive supply for I/O and some logic.
VDD 93 - Power Positive supply for I/O and some logic.
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 14 - Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 38 - Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 62 - Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD25 88 - Power
VDDA 3 - Power
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Buffer Description
Type
Pin Pin Type
Number
Function Pin Name
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
VDDA 98 - Power
SSI SSI0Clk 28 I/O TTL SSI module 0 clock
SSI0Fss 29 I/O TTL SSI module 0 frame
SSI0Rx 30 I TTL SSI module 0 receive
SSI0Tx 31 O TTL SSI module 0 transmit
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
System Control & CMOD0 65 I/O TTL
Clocks
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1 76 I/O TTL
Main oscillator crystal input or an external clock
reference input.
OSC0 48 I Analog
OSC1 49 I Analog Main oscillator crystal output.
RST 64 I TTL System reset input.
TRST 89 I TTL JTAG TRSTn
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
UART U0Rx 26 I TTL
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U0Tx 27 O TTL
Table 17-4. GPIO Pins and Alternate Functions
GPIO Pin Pin Number Multiplexed Function Multiplexed Function
PA0 26 U0Rx
PA1 27 U0Tx
PA2 28 SSI0Clk
PA3 29 SSI0Fss
PA4 30 SSI0Rx
PA5 31 SSI0Tx
PA6 34 CCP1
PB0 66 CCP0
PB1 67 CCP2
PB2 70
PB3 71 Fault
PB4 92 C0-
PB5 91 C1-
PB6 90 C0+
PB7 89 TRST
PC0 80 TCK SWCLK
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Signal Tables
GPIO Pin Pin Number Multiplexed Function Multiplexed Function
PC1 79 TMS SWDIO
PC2 78 TDI
PC3 77 TDO SWO
PC4 25
PC5 24 C1+
PC6 23 C2+
PC7 22 C2-
PD0 10 PWM0
PD1 11 PWM1
PD2 12
PD3 13
PD4 95 CCP3
PD5 96
PD6 99
PD7 100 C0o
PF0 47
PF1 61
PF2 60 LED1
PF3 59 LED0
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18 Operating Characteristics
Table 18-1. Temperature Characteristics
Characteristic Symbol Value Unit
Operating temperature rangea TA -40 to +85 °C
a. Maximum storage temperature is 150°C.
Table 18-2. Thermal Characteristics
Characteristic Symbol Value Unit
Thermal resistance (junction to ambient)a ΘJA 55.3 °C/W
Average junction temperatureb TJ TA + (PAVG • ΘJA) °C
a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator.
b. Power dissipation is a function of temperature.
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Operating Characteristics
19 Electrical Characteristics
19.1 DC Characteristics
19.1.1 Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device.
Note: The device is not guaranteed to operate properly at the maximum ratings.
Table 19-1. Maximum Ratings
Characteristic Symbol Value Unit
a
Min Max
I/O supply voltage (VDD) VDD 0 4 V
Core supply voltage (VDD25) VDD25 0 4 V
Analog supply voltage (VDDA) VDDA 0 4 V
Ethernet PHY supply voltage (VCCPHY) VCCPHY 0 4 V
Input voltage VIN -0.3 5.5 V
Maximum current per output pins I - 25 mA
a. Voltages are measured with respect to GND.
Important: This device contains circuitry to protect the inputs against damage due to high-static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are
connected to an appropriate logic voltage level (for example, either GND or VDD).
19.1.2 Recommended DC Operating Conditions
Table 19-2. Recommended DC Operating Conditions
Parameter Parameter Name Min Nom Max Unit
VDD I/O supply voltage 3.0 3.3 3.6 V
VDD25 Core supply voltage 2.25 2.5 2.75 V
VDDA Analog supply voltage 3.0 3.3 3.6 V
VCCPHY Ethernet PHY supply voltage 3.0 3.3 3.6 V
VIH High-level input voltage 2.0 - 5.0 V
VIL Low-level input voltage -0.3 - 1.3 V
VSIH High-level input voltage for Schmitt trigger inputs 0.8 * VDD - VDD V
VSIL Low-level input voltage for Schmitt trigger inputs 0 - 0.2 * VDD V
VOH High-level output voltage 2.4 - - V
VOL Low-level output voltage - - 0.4 V
IOH High-level source current, VOH=2.4 V
2-mA Drive 2.0 - - mA
4-mA Drive 4.0 - - mA
8-mA Drive 8.0 - - mA
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Parameter Parameter Name Min Nom Max Unit
IOL Low-level sink current, VOL=0.4 V
2-mA Drive 2.0 - - mA
4-mA Drive 4.0 - - mA
8-mA Drive 8.0 - - mA
19.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics
Table 19-3. LDO Regulator Characteristics
Parameter Parameter Name Min Nom Max Unit
VLDOOUT Programmable internal (logic) power supply output value 2.25 2.5 2.75 V
Output voltage accuracy - 2% - %
tPON Power-on time - - 100 μs
tON Time on - - 200 μs
tOFF Time off - - 100 μs
VSTEP Step programming incremental voltage - 50 - mV
CLDO External filter capacitor size for internal power supply 1.0 - 3.0 μF
19.1.4 Power Specifications
The power measurements specified in the tables that follow are run on the core processor using
SRAM with the following specifications (except as noted):
■ VDD = 3.3 V
■ VDD25 = 2.50 V
■ VDDA = 3.3 V
■ VDDPHY = 3.3 V
■ Temperature = 25°C
■ Clock Source (MOSC) =3.579545 MHz Crystal Oscillator
■ Main oscillator (MOSC) = enabled
■ Internal oscillator (IOSC) = disabled
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Table 19-4. Detailed Power Specifications
3.3 V VDD, VDDA, 2.5 V VDD25 Unit
VDDPHY
Parameter Parameter Name Conditions
Nom Max Nom Max
VDD25 = 2.50 V 48 pendinga 64 pendinga mA
Code= while(1){} executed in Flash
Peripherals = All ON
System Clock = 25 MHz (with PLL)
Run mode 1 (Flash
loop)
IDD_RUN
VDD25 = 2.50 V 5 pendinga 33 pendinga mA
Code= while(1){} executed in Flash
Peripherals = All OFF
System Clock = 25 MHz (with PLL)
Run mode 2 (Flash
loop)
VDD25 = 2.50 V 48 pendinga 56 pendinga mA
Code= while(1){} executed in SRAM
Peripherals = All ON
System Clock = 25 MHz (with PLL)
Run mode 1 (SRAM
loop)
VDD25 = 2.50 V 5 pendinga 26 pendinga mA
Code= while(1){} executed in SRAM
Peripherals = All OFF
System Clock = 25 MHz (with PLL)
Run mode 2 (SRAM
loop)
VDD25 = 2.50 V 5 pendinga 12 pendinga mA
Peripherals = All OFF
System Clock = 25 MHz (with PLL)
IDD_SLEEP Sleep mode
LDO = 2.25 V 4.6 pendinga 0.21 pendinga mA
Peripherals = All OFF
System Clock = IOSC30KHZ/64
IDD_DEEPSLEEP Deep-Sleep mode
a. Pending characterization completion.
19.1.5 Flash Memory Characteristics
Table 19-5. Flash Memory Characteristics
Parameter Parameter Name Min Nom Max Unit
PECYC Number of guaranteed program/erase cycles before failurea 10,000 100,000 - cycles
TRET Data retention at average operating temperature of 85˚C 10 - - years
TPROG Word program time 20 - - μs
TERASE Page erase time 20 - - ms
TME Mass erase time 200 - - ms
a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1.
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19.2 AC Characteristics
19.2.1 Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements. Timing
measurements are for 4-mA drive strength.
Figure 19-1. Load Conditions
CL = 50 pF
GND
pin
19.2.2 Clocks
Table 19-6. Phase Locked Loop (PLL) Characteristics
Parameter Parameter Name Min Nom Max Unit
fref_crystal Crystal referencea 3.579545 - 8.192 MHz
fref_ext External clock referencea 3.579545 - 8.192 MHz
fpll PLL frequencyb - 400 - MHz
TREADY PLL lock time - - 0.5 ms
a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration
(RCC) register.
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register.
Table 19-7. Clock Characteristics
Parameter Parameter Name Min Nom Max Unit
fIOSC Internal 12 MHz oscillator frequency 8.4 12 15.6 MHz
fIOSC30KHZ Internal 30 KHz oscillator frequency 21 30 39 KHz
fMOSC Main oscillator frequency 1 - 8 MHz
tMOSC_per Main oscillator period 125 - 1000 ns
fref_crystal_bypass Crystal reference using the main oscillator (PLL in BYPASS mode) 1 - 8 MHz
fref_ext_bypass External clock reference (PLL in BYPASS mode) 0 - 25 MHz
fsystem_clock System clock 0 - 25 MHz
Table 19-8. Crystal Characteristics
Parameter Name Value Units
Frequency 8 6 4 3.5 MHz
Frequency tolerance ±50 ±50 ±50 ±50 ppm
Aging ±5 ±5 ±5 ±5 ppm/yr
Oscillation mode Parallel Parallel Parallel Parallel
Temperature stability (0 - 85 °C) ±25 ±25 ±25 ±25 ppm
Motional capacitance (typ) 27.8 37.0 55.6 63.5 pF
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Parameter Name Value Units
Motional inductance (typ) 14.3 19.1 28.6 32.7 mH
Equivalent series resistance (max) 120 160 200 220 Ω
Shunt capacitance (max) 10 10 10 10 pF
Load capacitance (typ) 16 16 16 16 pF
Drive level (typ) 100 100 100 100 μW
19.2.3 Analog Comparator
Table 19-9. Analog Comparator Characteristics
Parameter Parameter Name Min Nom Max Unit
VOS Input offset voltage - ±10 ±25 mV
VCM Input common mode voltage range 0 - VDD-1.5 V
CMRR Common mode rejection ratio 50 - - dB
TRT Response time - - 1 μs
TMC Comparator mode change to Output Valid - - 10 μs
Table 19-10. Analog Comparator Voltage Reference Characteristics
Parameter Parameter Name Min Nom Max Unit
RHR Resolution high range - VDD/32 - LSB
RLR Resolution low range - VDD/24 - LSB
AHR Absolute accuracy high range - - ±1/2 LSB
ALR Absolute accuracy low range - - ±1/4 LSB
19.2.4 Ethernet Controller
Table 19-11. 100BASE-TX Transmitter Characteristicsa
Parameter Name Min Nom Max Unit
Peak output amplitude 950 - 1050 mVpk
Output amplitude symmetry 0.98 - 1.02 mVpk
Output overshoot - - 5 %
Rise/Fall time 3 - 5 ns
Rise/Fall time imbalance - - 500 ps
Duty cycle distortion - - - ps
Jitter - - 1.4 ns
a. Measured at the line side of the transformer.
Table 19-12. 100BASE-TX Transmitter Characteristics (informative)a
Parameter Name Min Nom Max Unit
Return loss 16 - - dB
Open-circuit inductance 350 - - μs
a. The specifications in this table are included for information only. They are mainly a function of the external transformer
and termination resistors used for measurements.
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Table 19-13. 100BASE-TX Receiver Characteristics
Parameter Name Min Nom Max Unit
Signal detect assertion threshold 600 700 mVppd
Signal detect de-assertion threshold 350 425 - mVppd
Differential input resistance 20 - - kΩ
Jitter tolerance (pk-pk) 4 - - ns
Baseline wander tracking -75 - +75 %
Signal detect assertion time - - 1000 μs
Signal detect de-assertion time - - 4 μs
Table 19-14. 10BASE-T Transmitter Characteristicsa
Parameter Name Min Nom Max Unit
Peak differential output signal 2.2 - 2.8 V
Harmonic content 27 - - dB
Link pulse width - 100 - ns
300 - ns
350
Start-of-idle pulse width -
a. The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using
the procedures found in Clause 14 of IEEE 802.3.
Table 19-15. 10BASE-T Transmitter Characteristics (informative)a
Parameter Name Min Nom Max Unit
Output return loss 15 - - dB
Output impedance balance 29-17log(f/10) - - dB
Peak common-mode output voltage - - 50 mV
Common-mode rejection - - 100 mV
Common-mode rejection jitter - - 1 ns
a. The specifications in this table are included for information only. They are mainly a function of the external transformer
and termination resistors used for measurements.
Table 19-16. 10BASE-T Receiver Characteristics
Parameter Name Min Nom Max Unit
DLL phase acquisition time - 10 - BT
Jitter tolerance (pk-pk) 30 - - ns
Input squelched threshold 500 600 700 mVppd
Input unsquelched threshold 275 350 425 mVppd
Differential input resistance - 20 - kΩ
Bit error ratio - 10-10 - -
Common-mode rejection 25 - - V
Table 19-17. Isolation Transformersa
Name Value Condition
Turns ratio 1 CT : 1 CT +/- 5%
Open-circuit inductance 350 uH (min) @ 10 mV, 10 kHz
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Name Value Condition
Leakage inductance 0.40 uH (max) @ 1 MHz (min)
Inter-winding capacitance 25 pF (max)
DC resistance 0.9 Ohm (max)
Insertion loss 0.4 dB (typ) 0-65 MHz
HIPOT 1500 Vrms
a. Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common-mode
chokes are recommended for exceeding FCC requirements. This table gives the recommended line transformer
characteristics.
Note: The 100Base-TX amplitude specifications assume a transformer loss of 0.4 dB. For the
transmit line transformer with higher insertion losses, up to 1.2 dB of insertion loss can be
compensated by selecting the appropriate setting in the Transmit Amplitude Selection (TXO)
bits in the MR19 register.
Table 19-18. Ethernet Reference Crystala
Name Value Condition
Frequency 25.00000 MHz
Load capacitanceb 4c pF
Frequency tolerance ±50 PPM
Aging ±2 PPM/yr
Temperature stability (0° to 70°) ±5 PPM
Oscillation mode Parallel resonance, fundamental mode
Parameters at 25° C ±2° C; Drive level = 0.5 mW
Drive level (typ) 50-100 μW
Shunt capacitance (max) 10 pF
Motional capacitance (min) 10 fF
Serious resistance (max) 60 Ω
Spurious response (max) > 5 dB below main within 500 kHz
a. If the internal crystal oscillator is used, select a crystal with the following characteristics.
b. Equivalent differential capacitance across XTLP/XTLN.
c. If crystal with a larger load is used, external shunt capacitors to ground should be added to make up the equivalent
capacitance difference.
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Figure 19-2. External XTLP Oscillator Characteristics
Tclkper
Tr
Tclkhi Tclklo
Tf
Table 19-19. External XTLP Oscillator Characteristics
Parameter Name Symbol Min Nom Max Unit
XTLN Input Low Voltage XTLNILV - - 0.8 -
XTLP Frequencya XTLPf - 25.0 - -
XTLP Periodb Tclkper - 40 - -
60 %
60
40 -
40
XTLPDC XTLP Duty Cycle
Rise/Fall Time Tr , Tf - - 4.0 ns
Absolute Jitter - - 0.1 ns
a. IEEE 802.3 frequency tolerance ±50 ppm.
b. IEEE 802.3 frequency tolerance ±50 ppm.
19.2.5 Synchronous Serial Interface (SSI)
Table 19-20. SSI Characteristics
Parameter No. Parameter Parameter Name Min Nom Max Unit
S1 tclk_per SSIClk cycle time 2 - 65024 system clocks
S2 tclk_high SSIClk high time - 1/2 - t clk_per
S3 tclk_low SSIClk low time - 1/2 - t clk_per
S4 tclkrf SSIClk rise/fall time - 7.4 26 ns
S5 tDMd Data from master valid delay time 0 - 20 ns
S6 tDMs Data from master setup time 20 - - ns
S7 tDMh Data from master hold time 40 - - ns
S8 tDSs Data from slave setup time 20 - - ns
S9 tDSh Data from slave hold time 40 - - ns
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Figure 19-3. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement
SSIClk
SSIFss
SSITx
SSIRx MSB LSB
S2
S3
S1
S4
4 to 16 bits
Figure 19-4. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer
0
SSIClk
SSIFss
SSITx
SSIRx
MSB LSB
MSB LSB
S2
S3
S1
8-bit control
4 to 16 bits output data
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Figure 19-5. SSI Timing for SPI Frame Format (FRF=00), with SPH=1
SSIClk
(SPO=1)
SSITx
(master)
SSIRx
(slave) LSB
SSIClk
(SPO=0)
S2
S1
S4
SSIFss
LSB
S3
MSB
S5
S6 S7
S8 S9
MSB
19.2.6 JTAG and Boundary Scan
Table 19-21. JTAG Characteristics
Parameter No. Parameter Parameter Name Min Nom Max Unit
J1 fTCK TCK operational clock frequency 0 - 10 MHz
J2 tTCK TCK operational clock period 100 - - ns
J3 tTCK_LOW TCK clock Low time - tTCK - ns
J4 tTCK_HIGH TCK clock High time - tTCK - ns
J5 tTCK_R TCK rise time 0 - 10 ns
J6 tTCK_F TCK fall time 0 - 10 ns
J7 tTMS_SU TMS setup time to TCK rise 20 - - ns
J8 tTMS_HLD TMS hold time from TCK rise 20 - - ns
J9 tTDI_SU TDI setup time to TCK rise 25 - - ns
J10 tTDI_HLD TDI hold time from TCK rise 25 - - ns
J11 TCK fall to Data Valid from High-Z 2-mA drive - 23 35 ns
t TDO_ZDV 4-mA drive 15 26 ns
8-mA drive 14 25 ns
8-mA drive with slew rate control 18 29 ns
J12 TCK fall to Data Valid from Data Valid 2-mA drive - 21 35 ns
t TDO_DV 4-mA drive 14 25 ns
8-mA drive 13 24 ns
8-mA drive with slew rate control 18 28 ns
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Parameter No. Parameter Parameter Name Min Nom Max Unit
J13 TCK fall to High-Z from Data Valid 2-mA drive - 9 11 ns
t TDO_DVZ 4-mA drive 7 9 ns
8-mA drive 6 8 ns
8-mA drive with slew rate control 7 9 ns
J14 tTRST TRST assertion time 100 - - ns
J15 tTRST_SU TRST setup time to TCK rise 10 - - ns
Figure 19-6. JTAG Test Clock Input Timing
TCK
J6 J5
J3 J4
J2
Figure 19-7. JTAG Test Access Port (TAP) Timing
TDO Output Valid
TCK
TDO Output Valid
J12
TDO
TDI
TMS
TDI Input Valid TDI Input Valid
J13
J9 J10
TMS Input Valid
J9 J10
TMS Input Valid
J11
J7 J8 J7 J8
Figure 19-8. JTAG TRST Timing
TCK
J14 J15
TRST
19.2.7 General-Purpose I/O
Note: All GPIOs are 5 V-tolerant.
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Table 19-22. GPIO Characteristics
Parameter Parameter Name Condition Min Nom Max Unit
tGPIOR GPIO Rise Time (from 20% to 80% of VDD) 2-mA drive - 17 26 ns
4-mA drive 9 13 ns
8-mA drive 6 9 ns
8-mA drive with slew rate control 10 12 ns
tGPIOF GPIO Fall Time (from 80% to 20% of VDD) 2-mA drive - 17 25 ns
4-mA drive 8 12 ns
8-mA drive 6 10 ns
8-mA drive with slew rate control 11 13 ns
19.2.8 Reset
Table 19-23. Reset Characteristics
Parameter No. Parameter Parameter Name Min Nom Max Unit
R1 VTH Reset threshold - 2.0 - V
R2 VBTH Brown-Out threshold 2.85 2.9 2.95 V
R3 TPOR Power-On Reset timeout - 10 - ms
R4 TBOR Brown-Out timeout - 500 - μs
R5 TIRPOR Internal reset timeout after POR 6 - 11 ms
R6 TIRBOR Internal reset timeout after BORa 0 - 1 μs
R7 TIRHWR Internal reset timeout after hardware reset (RST pin) 0 - 1 ms
R8 TIRSWR Internal reset timeout after software-initiated system reset a 2.5 - 20 μs
R9 TIRWDR Internal reset timeout after watchdog reseta 2.5 - 20 μs
R10 TVDDRISE Supply voltage (VDD) rise time (0V-3.3V) - - 100 ms
R11 TMIN Minimum RST pulse width 2 - - μs
a. 20 * t MOSC_per
Figure 19-9. External Reset Timing (RST)
RST
/Reset
(Internal)
R11 R7
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Figure 19-10. Power-On Reset Timing
VDD
/POR
(Internal)
/Reset
(Internal)
R3
R1
R5
Figure 19-11. Brown-Out Reset Timing
VDD
/BOR
(Internal)
/Reset
(Internal)
R2
R4
R6
Figure 19-12. Software Reset Timing
R8
SW Reset
/Reset
(Internal)
Figure 19-13. Watchdog Reset Timing
WDOG
Reset
(Internal)
/Reset
(Internal)
R9
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20 Package Information
Figure 20-1. 100-Pin LQFP Package
Note: The following notes apply to the package drawing.
1. All dimensions shown in mm.
2. Dimensions shown are nominal with tolerances indicated.
3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane.
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Package Information
Body +2.00 mm Footprint, 1.4 mm package thickness
Symbols Leads 100L
A Max. 1.60
A1 0.05 Min./0.15 Max.
A2 ±0.05 1.40
D ±0.20 16.00
D1 ±0.05 14.00
E ±0.20 16.00
E1 ±0.05 14.00
L ±0.15/-0.10 0.60
e BASIC 0.50
b ±0.05 0.22
θ === 0˚~7˚
ddd Max. 0.08
ccc Max. 0.08
JEDEC Reference Drawing MS-026
Variation Designator BED
November 30, 2007 429
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LM3S6110 Microcontroller
A Serial Flash Loader
A.1 Serial Flash Loader
The Stellaris® serial flash loader is a preprogrammed flash-resident utility used to download code
to the flash memory of a device without the use of a debug interface. The serial flash loader uses
a simple packet interface to provide synchronous communication with the device. The flash loader
runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used.
The two serial interfaces that can be used are the UART0 and SSI0 interfaces. For simplicity, both
the data format and communication protocol are identical for both serial interfaces.
A.2 Interfaces
Once communication with the flash loader is established via one of the serial interfaces, that interface
is used until the flash loader is reset or new code takes over. For example, once you start
communicating using the SSI port, communications with the flash loader via the UART are disabled
until the device is reset.
A.2.1 UART
The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial
format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is
automatically detected by the flash loader and can be any valid baud rate supported by the host
and the device. The auto detection sequence requires that the baud rate should be no more than
1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the
same as the hardware limitation for the maximum baud rate for any UART on a Stellaris® device
which is calculated as follows:
Max Baud Rate = System Clock Frequency / 16
In order to determine the baud rate, the serial flash loader needs to determine the relationship
between its own crystal frequency and the baud rate. This is enough information for the flash loader
to configure its UART to the same baud rate as the host. This automatic baud-rate detection allows
the host to use any valid baud rate that it wants to communicate with the device.
The method used to perform this automatic synchronization relies on the host sending the flash
loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can
use to calculate the ratios needed to program the UART to match the host’s baud rate. After the
host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader
returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received
after at least twice the time required to transfer the two bytes, the host can resend another pattern
of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader acknowledges that it has
received a synchronization pattern correctly. For example, the time to wait for data back from the
flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate
of 115200, this time is 2*(20/115200) or 0.35 ms.
A.2.2 SSI
The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications,
with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See “Frame
Formats” on page 274 in the SSI chapter for more information on formats for this transfer protocol.
Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI
clock can run. This allows the SSI clock to be at most 1/12 the crystal frequency of the board running
430 November 30, 2007
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Serial Flash Loader
the flash loader. Since the host device is the master, the SSI on the flash loader device does not
need to determine the clock as it is provided directly by the host.
A.3 Packet Handling
All communications, with the exception of the UART auto-baud, are done via defined packets that
are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same
format for receiving and sending packets, including the method used to acknowledge successful or
unsuccessful reception of a packet.
A.3.1 Packet Format
All packets sent and received from the device use the following byte-packed format.
struct
{
unsigned char ucSize;
unsigned char ucCheckSum;
unsigned char Data[];
};
ucSize The first byte received holds the total size of the transfer including
the size and checksum bytes.
ucChecksum This holds a simple checksum of the bytes in the data buffer only.
The algorithm is Data[0]+Data[1]+…+ Data[ucSize-3].
Data This is the raw data intended for the device, which is formatted in
some form of command interface. There should be ucSize–2
bytes of data provided in this buffer to or from the device.
A.3.2 Sending Packets
The actual bytes of the packet can be sent individually or all at once; the only limitation is that
commands that cause flash memory access should limit the download sizes to prevent losing bytes
during flash programming. This limitation is discussed further in the section that describes the serial
flash loader command, COMMAND_SEND_DATA (see “COMMAND_SEND_DATA
(0x24)” on page 433).
Once the packet has been formatted correctly by the host, it should be sent out over the UART or
SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned
from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from
the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This
does not indicate that the actual contents of the command issued in the data portion of the packet
were valid, just that the packet was received correctly.
A.3.3 Receiving Packets
The flash loader sends a packet of data in the same format that it receives a packet. The flash loader
may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte
is the size of the packet followed by a checksum byte, and finally followed by the data itself. There
is no break in the data after the first non-zero byte is sent from the flash loader. Once the device
communicating with the flash loader receives all the bytes, it must either ACK or NAK the packet to
indicate that the transmission was successful. The appropriate response after sending a NAK to
the flash loader is to resend the command that failed and request the data again. If needed, the
host may send leading zeros before sending down the ACK/NAK signal to the flash loader, as the
November 30, 2007 431
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LM3S6110 Microcontroller
flash loader only accepts the first non-zero data as a valid response. This zero padding is needed
by the SSI interface in order to receive data to or from the flash loader.
A.4 Commands
The next section defines the list of commands that can be sent to the flash loader. The first byte of
the data should always be one of the defined commands, followed by data or parameters as
determined by the command that is sent.
A.4.1 COMMAND_PING (0X20)
This command simply accepts the command and sets the global status to success. The format of
the packet is as follows:
Byte[0] = 0x03;
Byte[1] = checksum(Byte[2]);
Byte[2] = COMMAND_PING;
The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one
byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status,
the receipt of an ACK can be interpreted as a successful ping to the flash loader.
A.4.2 COMMAND_GET_STATUS (0x23)
This command returns the status of the last command that was issued. Typically, this command
should be sent after every command to ensure that the previous command was successful or to
properly respond to a failure. The command requires one byte in the data of the packet and should
be followed by reading a packet with one byte of data that contains a status code. The last step is
to ACK or NAK the received data so the flash loader knows that the data has been read.
Byte[0] = 0x03
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_GET_STATUS
A.4.3 COMMAND_DOWNLOAD (0x21)
This command is sent to the flash loader to indicate where to store data and how many bytes will
be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit
values that are both transferred MSB first. The first 32-bit value is the address to start programming
data into, while the second is the 32-bit size of the data that will be sent. This command also triggers
an erase of the full area to be programmed so this command takes longer than other commands.
This results in a longer time to receive the ACK/NAK back from the board. This command should
be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size
are valid for the device running the flash loader.
The format of the packet to send this command is a follows:
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_DOWNLOAD
Byte[3] = Program Address [31:24]
Byte[4] = Program Address [23:16]
Byte[5] = Program Address [15:8]
Byte[6] = Program Address [7:0]
Byte[7] = Program Size [31:24]
432 November 30, 2007
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Serial Flash Loader
Byte[8] = Program Size [23:16]
Byte[9] = Program Size [15:8]
Byte[10] = Program Size [7:0]
A.4.4 COMMAND_SEND_DATA (0x24)
This command should only follow a COMMAND_DOWNLOAD command or another
COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands
automatically increment address and continue programming from the previous location. The caller
should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program
successfully and not overflow input buffers of the serial interfaces. The command terminates
programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been
received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to
ensure that the data was successfully programmed into the flash. If the flash loader sends a NAK
to this command, the flash loader does not increment the current address to allow retransmission
of the previous data.
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_SEND_DATA
Byte[3] = Data[0]
Byte[4] = Data[1]
Byte[5] = Data[2]
Byte[6] = Data[3]
Byte[7] = Data[4]
Byte[8] = Data[5]
Byte[9] = Data[6]
Byte[10] = Data[7]
A.4.5 COMMAND_RUN (0x22)
This command is used to tell the flash loader to execute from the address passed as the parameter
in this command. This command consists of a single 32-bit value that is interpreted as the address
to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK
signal back to the host device before actually executing the code at the given address. This allows
the host to know that the command was received successfully and the code is now running.
Byte[0] = 7
Byte[1] = checksum(Bytes[2:6])
Byte[2] = COMMAND_RUN
Byte[3] = Execute Address[31:24]
Byte[4] = Execute Address[23:16]
Byte[5] = Execute Address[15:8]
Byte[6] = Execute Address[7:0]
A.4.6 COMMAND_RESET (0x25)
This command is used to tell the flash loader device to reset. This is useful when downloading a
new image that overwrote the flash loader and wants to start from a full reset. Unlike the
COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set
up for the new code. It can also be used to reset the flash loader if a critical error occurs and the
host device wants to restart communication with the flash loader.
November 30, 2007 433
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LM3S6110 Microcontroller
Byte[0] = 3
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_RESET
The flash loader responds with an ACK signal back to the host device before actually executing the
software reset to the device running the flash loader. This allows the host to know that the command
was received successfully and the part will be reset.
434 November 30, 2007
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Serial Flash Loader
B Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
System Control
Base 0x400F.E000
DID0, type RO, offset 0x000, reset -
VER CLASS
MAJOR MINOR
PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD
BORIOR
LDOPCTL, type R/W, offset 0x034, reset 0x0000.0000
VADJ
RIS, type RO, offset 0x050, reset 0x0000.0000
PLLLRIS BORRIS
IMC, type R/W, offset 0x054, reset 0x0000.0000
PLLLIM BORIM
MISC, type R/W1C, offset 0x058, reset 0x0000.0000
PLLLMIS BORMIS
RESC, type R/W, offset 0x05C, reset -
LDO SW WDT BOR POR EXT
RCC, type R/W, offset 0x060, reset 0x07AE.3AD1
ACG SYSDIV USESYSDIV USEPWMDIV PWMDIV
PWRDN BYPASS XTAL OSCSRC IOSCDIS MOSCDIS
PLLCFG, type RO, offset 0x064, reset -
F R
RCC2, type R/W, offset 0x070, reset 0x0780.2800
USERCC2 SYSDIV2
PWRDN2 BYPASS2 OSCSRC2
DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000
DSDIVORIDE
DSOSCSRC
DID1, type RO, offset 0x004, reset -
VER FAM PARTNO
PINCOUNT TEMP PKG ROHS QUAL
DC0, type RO, offset 0x008, reset 0x003F.001F
SRAMSZ
FLASHSZ
DC1, type RO, offset 0x010, reset 0x0010.709F
PWM
MINSYSDIV MPU PLL WDT SWO SWD JTAG
DC2, type RO, offset 0x014, reset 0x0707.0011
COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0
SSI0 UART0
DC3, type RO, offset 0x018, reset 0x0F00.B7C3
CCP3 CCP2 CCP1 CCP0
PWMFAULT C2PLUS C2MINUS C1PLUS C1MINUS C0O C0PLUS C0MINUS PWM1 PWM0
November 30, 2007 435
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LM3S6110 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DC4, type RO, offset 0x01C, reset 0x5000.007F
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
RCGC0, type R/W, offset 0x100, reset 0x00000040
PWM
WDT
SCGC0, type R/W, offset 0x110, reset 0x00000040
PWM
WDT
DCGC0, type R/W, offset 0x120, reset 0x00000040
PWM
WDT
RCGC1, type R/W, offset 0x104, reset 0x00000000
COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0
SSI0 UART0
SCGC1, type R/W, offset 0x114, reset 0x00000000
COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0
SSI0 UART0
DCGC1, type R/W, offset 0x124, reset 0x00000000
COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0
SSI0 UART0
RCGC2, type R/W, offset 0x108, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
SCGC2, type R/W, offset 0x118, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
DCGC2, type R/W, offset 0x128, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
SRCR0, type R/W, offset 0x040, reset 0x00000000
PWM
WDT
SRCR1, type R/W, offset 0x044, reset 0x00000000
COMP2 COMP1 COMP0 TIMER2 TIMER1 TIMER0
SSI0 UART0
SRCR2, type R/W, offset 0x048, reset 0x00000000
EPHY0 EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Internal Memory
Flash Control Offset
Base 0x400F.D000
FMA, type R/W, offset 0x000, reset 0x0000.0000
OFFSET
FMD, type R/W, offset 0x004, reset 0x0000.0000
DATA
DATA
FMC, type R/W, offset 0x008, reset 0x0000.0000
WRKEY
COMT MERASE ERASE WRITE
436 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FCRIS, type RO, offset 0x00C, reset 0x0000.0000
PRIS ARIS
FCIM, type R/W, offset 0x010, reset 0x0000.0000
PMASK AMASK
FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000
PMISC AMISC
Internal Memory
System Control Offset
Base 0x400F.E000
USECRL, type R/W, offset 0x140, reset 0x16
USEC
FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
USER_DBG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE
NW DATA
DATA DBG1 DBG0
USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF
NW DATA
DATA
USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF
NW DATA
DATA
FMPRE1, type R/W, offset 0x204, reset 0x0000.0000
READ_ENABLE
READ_ENABLE
FMPRE2, type R/W, offset 0x208, reset 0x0000.0000
READ_ENABLE
READ_ENABLE
FMPRE3, type R/W, offset 0x20C, reset 0x0000.0000
READ_ENABLE
READ_ENABLE
FMPPE1, type R/W, offset 0x404, reset 0x0000.0000
PROG_ENABLE
PROG_ENABLE
FMPPE2, type R/W, offset 0x408, reset 0x0000.0000
PROG_ENABLE
PROG_ENABLE
FMPPE3, type R/W, offset 0x40C, reset 0x0000.0000
PROG_ENABLE
PROG_ENABLE
General-Purpose Input/Outputs (GPIOs)
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Preliminary
LM3S6110 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIODATA, type R/W, offset 0x000, reset 0x0000.0000
DATA
GPIODIR, type R/W, offset 0x400, reset 0x0000.0000
DIR
GPIOIS, type R/W, offset 0x404, reset 0x0000.0000
IS
GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000
IBE
GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000
IEV
GPIOIM, type R/W, offset 0x410, reset 0x0000.0000
IME
GPIORIS, type RO, offset 0x414, reset 0x0000.0000
RIS
GPIOMIS, type RO, offset 0x418, reset 0x0000.0000
MIS
GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000
IC
GPIOAFSEL, type R/W, offset 0x420, reset -
AFSEL
GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF
DRV2
GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000
DRV4
GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000
DRV8
GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000
ODE
GPIOPUR, type R/W, offset 0x510, reset -
PUE
GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000
PDE
438 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000
SRL
GPIODEN, type R/W, offset 0x51C, reset -
DEN
GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001
LOCK
LOCK
GPIOCR, type -, offset 0x524, reset -
CR
GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061
PID0
GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
General-Purpose Timers
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Preliminary
LM3S6110 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000
GPTMCFG
GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000
TAAMS TACMR TAMR
GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000
TBAMS TBCMR TBMR
GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000
TBPWML TBOTE TBEVENT TBSTALL TBEN TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN
GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000
CBEIM CBMIM TBTOIM RTCIM CAEIM CAMIM TATOIM
GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000
CBERIS CBMRIS TBTORIS RTCRIS CAERIS CAMRIS TATORIS
GPTMMIS, type RO, offset 0x020, reset 0x0000.0000
CBEMIS CBMMIS TBTOMIS RTCMIS CAEMIS CAMMIS TATOMIS
GPTMICR, type W1C, offset 0x024, reset 0x0000.0000
CBECINT CBMCINT TBTOCINT RTCCINT CAECINT CAMCINT TATOCINT
GPTMTAILR, type R/W, offset 0x028, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
TAILRH
TAILRL
GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF
TBILRL
GPTMTAMATCHR, type R/W, offset 0x030, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
TAMRH
TAMRL
GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF
TBMRL
GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000
TAPSR
GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000
TBPSR
GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000
TAPSMR
GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000
TBPSMR
440 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPTMTAR, type RO, offset 0x048, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
TARH
TARL
GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF
TBRL
Watchdog Timer
Base 0x4000.0000
WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF
WDTLoad
WDTLoad
WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF
WDTValue
WDTValue
WDTCTL, type R/W, offset 0x008, reset 0x0000.0000
RESEN INTEN
WDTICR, type WO, offset 0x00C, reset -
WDTIntClr
WDTIntClr
WDTRIS, type RO, offset 0x010, reset 0x0000.0000
WDTRIS
WDTMIS, type RO, offset 0x014, reset 0x0000.0000
WDTMIS
WDTTEST, type R/W, offset 0x418, reset 0x0000.0000
STALL
WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000
WDTLock
WDTLock
WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005
PID0
WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018
PID1
WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
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LM3S6110 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Universal Asynchronous Receivers/Transmitters (UARTs)
UART0 base: 0x4000.C000
UARTDR, type R/W, offset 0x000, reset 0x0000.0000
OE BE PE FE DATA
UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000
OE BE PE FE
UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000
DATA
UARTFR, type RO, offset 0x018, reset 0x0000.0090
TXFE RXFF TXFF RXFE BUSY
UARTILPR, type R/W, offset 0x020, reset 0x0000.0000
ILPDVSR
UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000
DIVINT
UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000
DIVFRAC
UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000
SPS WLEN FEN STP2 EPS PEN BRK
UARTCTL, type R/W, offset 0x030, reset 0x0000.0300
RXE TXE LBE SIRLP SIREN UARTEN
UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012
RXIFLSEL TXIFLSEL
UARTIM, type R/W, offset 0x038, reset 0x0000.0000
OEIM BEIM PEIM FEIM RTIM TXIM RXIM
UARTRIS, type RO, offset 0x03C, reset 0x0000.000F
OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS
442 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UARTMIS, type RO, offset 0x040, reset 0x0000.0000
OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS
UARTICR, type W1C, offset 0x044, reset 0x0000.0000
OEIC BEIC PEIC FEIC RTIC TXIC RXIC
UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011
PID0
UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Synchronous Serial Interface (SSI)
SSI0 base: 0x4000.8000
SSICR0, type R/W, offset 0x000, reset 0x0000.0000
SCR SPH SPO FRF DSS
SSICR1, type R/W, offset 0x004, reset 0x0000.0000
SOD MS SSE LBM
SSIDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
November 30, 2007 443
Preliminary
LM3S6110 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSISR, type RO, offset 0x00C, reset 0x0000.0003
BSY RFF RNE TNF TFE
SSICPSR, type R/W, offset 0x010, reset 0x0000.0000
CPSDVSR
SSIIM, type R/W, offset 0x014, reset 0x0000.0000
TXIM RXIM RTIM RORIM
SSIRIS, type RO, offset 0x018, reset 0x0000.0008
TXRIS RXRIS RTRIS RORRIS
SSIMIS, type RO, offset 0x01C, reset 0x0000.0000
TXMIS RXMIS RTMIS RORMIS
SSIICR, type W1C, offset 0x020, reset 0x0000.0000
RTIC RORIC
SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022
PID0
SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
444 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Ethernet Controller
Ethernet MAC
Base 0x4004.8000
MACRIS, type RO, offset 0x000, reset 0x0000.0000
PHYINT MDINT RXER FOV TXEMP TXER RXINT
MACIACK, type W1C, offset 0x000, reset 0x0000.0000
PHYINT MDINT RXER FOV TXEMP TXER RXINT
MACIM, type R/W, offset 0x004, reset 0x0000.007F
PHYINTM MDINTM RXERM FOVM TXEMPM TXERM RXINTM
MACRCTL, type R/W, offset 0x008, reset 0x0000.0008
RSTFIFO BADCRC PRMS AMUL RXEN
MACTCTL, type R/W, offset 0x00C, reset 0x0000.0000
DUPLEX CRC PADEN TXEN
MACDATA, type RO, offset 0x010, reset 0x0000.0000
RXDATA
RXDATA
MACDATA, type WO, offset 0x010, reset 0x0000.0000
TXDATA
TXDATA
MACIA0, type R/W, offset 0x014, reset 0x0000.0000
MACOCT4 MACOCT3
MACOCT2 MACOCT1
MACIA1, type R/W, offset 0x018, reset 0x0000.0000
MACOCT6 MACOCT5
MACTHR, type R/W, offset 0x01C, reset 0x0000.003F
THRESH
MACMCTL, type R/W, offset 0x020, reset 0x0000.0000
REGADR WRITE START
MACMDV, type R/W, offset 0x024, reset 0x0000.0080
DIV
MACMTXD, type R/W, offset 0x02C, reset 0x0000.0000
MDTX
MACMRXD, type R/W, offset 0x030, reset 0x0000.0000
MDRX
MACNP, type RO, offset 0x034, reset 0x0000.0000
NPR
November 30, 2007 445
Preliminary
LM3S6110 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACTR, type R/W, offset 0x038, reset 0x0000.0000
NEWTX
Ethernet Controller
MII Management
Base 0x4004.8000
MR0, type R/W, address 0x00, reset 0x3100
RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT
MR1, type RO, address 0x01, reset 0x7849
100X_F 100X_H 10T_F 10T_H MFPS ANEGC RFAULT ANEGA LINK JAB EXTD
MR2, type RO, address 0x02, reset 0x000E
OUI[21:6]
MR3, type RO, address 0x03, reset 0x7237
OUI[5:0] MN RN
MR4, type R/W, address 0x04, reset 0x01E1
NP RF A3 A2 A1 A0 S[4:0]
MR5, type RO, address 0x05, reset 0x0000
NP ACK RF A[7:0] S[4:0]
MR6, type RO, address 0x06, reset 0x0000
PDF LPNPA PRX LPANEGA
MR16, type R/W, address 0x10, reset 0x0140
RPTR INPOL TXHIM SQEI NL10 APOL RVSPOL PCSBP RXCC
MR17, type R/W, address 0x11, reset 0x0000
JABBER_IE RXER_IE PRX_IE PDF_IE LPACK_IE LSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INT RXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT ANEGCOMP_INT
MR18, type RO, address 0x12, reset 0x0000
ANEGF DPLX RATE RXSD RX_LOCK
MR19, type R/W, address 0x13, reset 0x4000
TXO[1:0]
MR23, type R/W, address 0x17, reset 0x0010
LED1[3:0] LED0[3:0]
MR24, type R/W, address 0x18, reset 0x00C0
PD_MODE AUTO_SW MDIX MDIX_CM MDIX_SD
Analog Comparators
Base 0x4003.C000
ACMIS, type R/W1C, offset 0x00, reset 0x0000.0000
IN2 IN1 IN0
ACRIS, type RO, offset 0x04, reset 0x0000.0000
IN2 IN1 IN0
ACINTEN, type R/W, offset 0x08, reset 0x0000.0000
IN2 IN1 IN0
ACREFCTL, type R/W, offset 0x10, reset 0x0000.0000
EN RNG VREF
ACSTAT0, type RO, offset 0x20, reset 0x0000.0000
OVAL
ACSTAT1, type RO, offset 0x40, reset 0x0000.0000
OVAL
446 November 30, 2007
Preliminary
Register Quick Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACSTAT2, type RO, offset 0x60, reset 0x0000.0000
OVAL
ACCTL0, type R/W, offset 0x24, reset 0x0000.0000
ASRCP ISLVAL ISEN CINV
ACCTL1, type R/W, offset 0x44, reset 0x0000.0000
ASRCP ISLVAL ISEN CINV
ACCTL2, type R/W, offset 0x64, reset 0x0000.0000
ASRCP ISLVAL ISEN CINV
Pulse Width Modulator (PWM)
Base 0x4002.8000
PWMCTL, type R/W, offset 0x000, reset 0x0000.0000
GlobalSync0
PWMSYNC, type R/W, offset 0x004, reset 0x0000.0000
Sync0
PWMENABLE, type R/W, offset 0x008, reset 0x0000.0000
PWM1En PWM0En
PWMINVERT, type R/W, offset 0x00C, reset 0x0000.0000
PWM1Inv PWM0Inv
PWMFAULT, type R/W, offset 0x010, reset 0x0000.0000
Fault1 Fault0
PWMINTEN, type R/W, offset 0x014, reset 0x0000.0000
IntFault
IntPWM0
PWMRIS, type RO, offset 0x018, reset 0x0000.0000
IntFault
IntPWM0
PWMISC, type R/W1C, offset 0x01C, reset 0x0000.0000
IntFault
IntPWM0
PWMSTATUS, type RO, offset 0x020, reset 0x0000.0000
Fault
PWM0CTL, type R/W, offset 0x040, reset 0x0000.0000
CmpBUpd CmpAUpd LoadUpd Debug Mode Enable
PWM0INTEN, type R/W, offset 0x044, reset 0x0000.0000
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM0RIS, type RO, offset 0x048, reset 0x0000.0000
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
PWM0ISC, type R/W1C, offset 0x04C, reset 0x0000.0000
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
November 30, 2007 447
Preliminary
LM3S6110 Microcontroller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM0LOAD, type R/W, offset 0x050, reset 0x0000.0000
Load
PWM0COUNT, type RO, offset 0x054, reset 0x0000.0000
Count
PWM0CMPA, type R/W, offset 0x058, reset 0x0000.0000
CompA
PWM0CMPB, type R/W, offset 0x05C, reset 0x0000.0000
CompB
PWM0GENA, type R/W, offset 0x060, reset 0x0000.0000
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
PWM0GENB, type R/W, offset 0x064, reset 0x0000.0000
ActCmpBD ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero
PWM0DBCTL, type R/W, offset 0x068, reset 0x0000.0000
Enable
PWM0DBRISE, type R/W, offset 0x06C, reset 0x0000.0000
RiseDelay
PWM0DBFALL, type R/W, offset 0x070, reset 0x0000.0000
FallDelay
448 November 30, 2007
Preliminary
Register Quick Reference
C Ordering and Contact Information
C.1 Ordering Information
L M 3 S n n n n – g p p s s – r r m
Part Numbe