AT89C5131 Hardware User Guide - Atmel Corporation - Farnell Element 14 - Revenir à l'accueil

 

 

Branding Farnell element14 (France)

 

Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Recherche intégrée

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

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Voltage Level Translation

Puce électronique / Microchip :

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Raspberry Pi board B product overview

Logiciels :

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Introduction to Cadsoft EAGLE PCB Design Software in Chinese

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Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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Ben's Autodesk 123D Tutorial Trailer

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Ben's CadSoft EAGLE Tutorial Trailer

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Ben Heck's Soldering Tutorial Trailer

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Ben Heck's AVR Dev Board tutorial

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Ben Heck's Pinball Tutorial Trailer

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Ben Heck's Interface Tutorial Trailer

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First Stage with Python and PiFace Digital

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Cypress - Getting Started with PSoC® 3 - Part 2

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

Autres documentations :

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STK525 ............................................................................................. Hardware User Guide STK525 Hardware User Guide User Guide 1 7608A–AVR–04/06 Section 1 Introduction ........................................................................................... 1-3 1.1 Overview ...................................................................................................1-3 1.2 STK525 Starter Kit Features .....................................................................1-4 Section 2 Using the STK525................................................................................. 2-6 2.1 Overview ...................................................................................................2-6 2.2 Power Supply ............................................................................................2-7 2.3 RESET ....................................................................................................2-10 2.4 AT90USBxxx AVR Microcontroller..........................................................2-11 2.5 Serial Links .............................................................................................2-11 2.6 On-board Resources...............................................................................2-14 2.7 STK500 Resources .................................................................................2-19 2.8 In-System Programming .........................................................................2-20 2.10 Test Points ..............................................................................................2-23 2.11 Configuration Pads .................................................................................2-24 2.12 Solder Pads ............................................................................................2-25 Section 3 Troubleshooting Guide ....................................................................... 3-26 Section 4 Technical Specifications ..................................................................... 4-27 Section 5 Technical Support............................................................................... 5-28 Section 6 Complete Schematics......................................................................... 6-29 STK525 Hardware User Guide 1-3 7608A–AVR–04/06 Section 1 Introduction Congratulation for acquiring the AVR® STK525 Starter Kit. This kit is designed to give designers a quick start to develop code on the AT90USBxxx and for prototyping and testing of new designs. 1.1 Overview This document describes the STK525 dedicated to the AT90USBxxx AVR microcontroller. This board is designed to allow an easy evaluation of the product using demonstration software. To complement the evaluation and enable additional development capability, the STK525 can be plugged into the Atmel STK500 Starter Kit Board in order to use the AT90USBxxx with advanced features such as variable VCC, variable VRef, variable XTAL, etc. and supports all AVR development tools. To increase its demonstrative capabilities, this stand alone board has numerous onboard resources (USB, RS232, joystick, data-flash, microphone and temperature sensor). This user guide acts as a general getting started guide as well as a complete technical reference for advanced users. Introduction 1-4 STK525 Hardware User Guide 7608A–AVR–04/06 Figure 1-1 . STK525 Board 1.2 STK525 Starter Kit Features The STK525 provides the following features: 􀀀 AT90USBxxx TQFP device (2.7V 1.0 STK500 Expand connectors A4 Tuesday , January 17, 2006 2 4 STKNC Important: Def ault conf iguration: open reserv ed f or f uture mass storage extension 3.3V SP3 STK525 MEZZANINE FOR STK500 NRST STKNC VTG XTAL1 PA0 R8 2k PB7 PB3 PB5 PD5 PD7 PB1 PB6 PD1 PD3 PB2 PB4 PD6 PB0 PD2 PD4 C12 1nF PD0 1 2 AREF JP3 STK AREF VTG REF XT1 XT2 PE[2..0] VTG VTG PE[2..0] VTG PC[7..0] PC[7..0] PB[7..0] PD[7..0] PA[7..0] PA[7..0] PA5 PA7 PA6 PA1 PA3 PA4 1 2 JP1 STK X1 PA2 1 2 JP2 STK X2 PB[7..0] Complete Schematics STK525 Hardware User Guide 6-33 7608A–AVR–04/06 Figure 6-3 . Schematics, 3 of 5 Data Flash 3.3V LEDs 3.3V PF[7..0] DECOUPLING CAPACITOR CLOSE TO THE CONNECTOR R19 POT 100k Select 5 Lef t 7 Up 3 Right 6 Down 4 Com1 1 Com2 2 SW3 TPA511G PF[7..0] Temp Sensor PB[7..0] R18 NCP18WF104J03RB 5 9 4 8 3 7 2 6 1 10 11 P1 SUB-D9 FEMALE RS232 1234 J7 PF Spare (Not mounted) RS232 Interface JTAG Interface RS-CTS 3.3V Serial ISP Interface PE[7..0] CP1 VCC R16 100k STK525 MEZZANINE FOR STK500 3.3V VCC BUSY 1 RESET 2 WP 3 VCC 6 GND 7 CS 11 SCK 12 SI 13 SO 14 U2 AT45DB321C TSOP28 Microphone Preamplifier Interface PF0 VCC PB[7..0] CTS Title Size Document Number Rev Date: Sheet of 1.0 Interf aces A4 Tuesday , January 17, 2006 3 4 C20 100nF RTS CP2 R23 100k . 11 . 12 . 10 . 9 . 8 . 7 . 13 . 14 . 15 . 16 C1+ 1 V+ 2 C1- 3 C2+ 4 C2- 5 V- 6 TTL RS 232 GND VCC U3 MAX3232 RS232 BUFFER C17 100nF C16 100nF C18 100nF PF1 C19 100nF PD2 RxD DECOUPLING CAPACITOR CLOSE TO THE DEVICE RS-TxD RS-RxD PD[7..0] VCC PF0 1 TP4 Mic VCC DECOUPLING CAPACITOR CLOSE TO THE DEVICE C15 100nF PF1 SP4 PF2 SP5 VCC Caution DataFlash Fix 3V Power supply Only PF3 PB[7..0] C26 100nF RESET R11 100k CP3 DECOUPLING CAPACITOR CLOSE TO THE CONNECTOR PB5 PDO 1 VCC 2 SCK 3 PDI 4 RESET 5 GND 6 CON 2x3 J5 ISP CON TCK 1 GND 2 TDO 3 VCC 4 TMS 5 RESET 6 VCC 7 n.c. 8 TDI 9 GND 10 CON 2x5 J4 JTAG CON C21 100nF C23 100nF PD1 PF4 PF6 PF7 PF5 RESET PB1 R17 0 PB2 PB3 3.3V PB6 PD0 VCC PD3 TXD SP7 PB7 5 6 7 8 4 + - U4B LMV358 3 2 1 8 4 + - U4A LMV358 R27 0 R26 22k R25 10k R24 100k PB4 + C25 1uF R21 100k R28 100k C22 220pF + C24 4.7uF 3.3V R20 2.2k MIC1 MICROPHONE R22 100k DECOUPLING CAPACITOR CLOSE TO THE DEVICE PE4 PB1 R10 100k PF2 In-line Grouped LEDs RESET TOPLED LP M676 D2 LED 0 (green) TOPLED LP M676 D3 LED 1 (green) TOPLED LP M676 D4 LED 2 (green) TOPLED LP M676 D5 LED 3 (green) PB2 1k R12 1k R13 PE5 1k R14 1k R15 PD4 PB3 PD5 PD7 PD[7..0] PD6 SP8 RS-RTS Joystick Interface Complete Schematics 6-34 STK525 Hardware User Guide 7608A–AVR–04/06 Figure 6-4 . Schematics, 4 of 5 - C30 4.7uF VTG IN GND OUT U8 LM340 VBUS generator f or OTG/HOST mode 1F 1.0 POWER A4 Tuesday , January 17, 2006 4 4 5V C32 220nF 1 2 3 4 5 6 7 8 JP6 VCC Source VCC - C34 4.7uF 2 1 3 JP7 VBUS gen D6 LL4148 R32 10k R35 100k 1% 3 1 4 2 - + U7 DF005S 321 J6 CONNECTOR JACK PWR Ext Power Supply C33 100nF C29 33nF UVCON VBUS OUT 1 IN 2 GND 3 OUT 4 FAULT SHDN 8 7 CC 6 SET 5 U6 LP3982 Complete Schematics STK525 Hardware User Guide 6-35 7608A–AVR–04/06 Figure 6-5 . Assembly Drawing, 1 of 2 (component side) Figure 6-6 . Assembly Drawing, 2 of 2 (solder side) Complete Schematics 6-36 STK525 Hardware User Guide 7608A–AVR–04/06 Table 6-1 . Bill of material Item Q.ty Reference Part Tech. Characteristics Package 1 2 CR1,CR2 PGB0010603 ESD protection CASE 0805 2 19 C1,C2,C3,C4,C5,C6,C13,C14,C15,C16,C 17,C18,C19,C20,C21,C23,C26,C27,C33 100nF 50V-10% Ceramic CASE 0805 3 2 C7,C25 1uF 10Vmin ±10% EIA/IECQ 3216 4 3 C8,C9,C32 220nF 50V-10% Ceramic CASE 0805 5 2 C10,C11 15pF 50V-5% Ceramic CASE 0805 6 1 C12 1nF 50V-5% Ceramic CASE 0805 7 1 C22 220pF 50V-5% Ceramic CASE 0805 8 5 C24,C28,C30,C31,C34 4.7uF 10Vmin ±10% EIA/IECQ 3216 9 1 C29 33nF 50V-5% Ceramic CASE 0805 10 3 CP1, CP2, CP3 Configuration Pad 11 1 D1 BAT54/SOT Vf=0.3V SOT23 12 5 D2,D3,D4,D5,D8 TOPLED LP M676 Green I=10 mA_ PLCC-2 13 2 D6,D7 LL4148 i=200mA max LL-34 14 5 JP1,JP2,JP3,JP4,JP5 JUMPER 1x2 Need 1 shunt 0,1" pitch 15 1 J1 USB_MiniABF USB mini AB receptacle Surface mount 16 2 J2,J3 CON 2x20 17 1 J4 CON 2x5 18 1 J5 CON 2x3 19 1 J7 CON 2x2 Not Mounted 20 1 JP6 JUMPER 2x4 Need 1 shunt 0,1" pitch 21 1 J6 CONNECTOR JACK PWR Int.Diam=2.1mm PCB Embase 22 1 JP7 JUMPER 3x1 23 1 L1 BLM-21A102S FERRITE BEAD 1 KOhms at 100 MHz CASE 0805 24 1 MIC1 MICROPHONE Electret Cap Mic 25 1 M1 FDV304P/FAI MOSFET P SOT23 26 1 P1 SUB-D9 FEMALE 90° with harpoons 27 2 Q1,Q2 BC847B NPN IC peak=200mA SOT23 28 2 R1,R2 22 1/16W-5% SMD CASE 0602 29 2 R3,R5 47k 1/16W-5% SMD CASE 0603 30 5 R4,R6,R7,R17,R27 0 CASE 0603 31 1 R8 2k CASE 0604 32 4 R9,R25,R29,R32 10k 1/16W-5% SMD CASE 0603 Complete Schematics STK525 Hardware User Guide 6-37 7608A–AVR–04/06 6.0.1 Default Configuration - Summary Table 6-2 . Default Configuration summary 33 9 R10,R11,R16,R21,R22,R23,R24,R28,R33 100k 1/16W-5% SMD CASE 0603 34 5 R12,R13,R14,R15,R34 1k 1/16W-5% SMD CASE 0603 35 1 R18 NCP18WF104J03RB 100K - ß=4250 CASE 0603 36 1 R19 POT 100k PT10MH104ME 37 1 R19 Button Pot Button 38 1 R20 2.2k 1/16W-5% SMD CASE 0603 39 1 R26 22k 1/16W-5% SMD CASE 0603 40 1 R30, R35 100k 1% 1/16W-1% SMD CASE 0603 41 1 R31 120k 1% 1/16W-1% SMD CASE 0603 42 6 SP1,SP2,SP3,SP4,SP5,SP6 SolderPad (NA) (NA) 43 2 SW1,SW2 PUSH-BUTTON 6x3.5mm - 1.6N 44 1 SW3 TPA511G 4+1 ways joystick CMS 45 8 TP1,TP2,TP3,TP4,TP5,TP6, TP7, TP8 TEST POINT Diam.=1.32mm 46 1 U1 AT90USBxxx TQFP64 47 1 U1 Socket TQFP64 ZIF 48 1 U2 AT45DB321C TSOP28 49 1 U3 MAX3232ECAE+ SSOP16 50 1 U4 LMV358 SO8 51 1 U5 TPS2041A SOIC8 52 1 U6 LP3982 Low Drop Out Vin Max 6V, 300mA MSOP8 53 1 U7 DF005S Bridge rectifier See DS 54 1 U8 LM340 Reg 5V CMS SOT223 55 1 Y1 8MHz CRYSTAL H=4mm HC49/4H Item Q.ty Reference Part Tech. Characteristics Package Name Ref. Function State Jumpers STKX1 JP1 XTAL Configuration OFF STKX2 JP2 XTAL Configuration OFF Aref JP3 STK500 Analog Ref OFF VTG33 JP4 Short 3.3V to VTG (Mass storage extension board) OFF UCAP JP5 Short UCAP with Uvcc OFF Vcc Src JP6 Vcc Selection 3.4 shorted Vbus Gen JP7 VBUS generation selection (host mode) 2.3 shorted Solder PADS Complete Schematics 6-38 STK525 Hardware User Guide 7608A–AVR–04/06 SP1 Bypass L1 OPEN SP2 OPEN SP3 3.3V on Expand 0 NC pin OPEN SP4 CTS OPEN SP5 RTS OPEN SP6 Bypass limiter OPEN SP7 RS232 hardware control enable OPEN SP8 RS232 hardware control enable OPEN Configuration PADS CP1 Bypass CTN in on PF0 CLOSE CP2 Bypass Potentiometer ADC in on PF1 CLOSE CP3 Bypass Mic In on PF2 CLOSE Name Ref. Function State Printed on recycled paper. 7608A–AVR–04/06 /xM © Atmel Corporation 2006. All rights reserved. Atmel®, logo and combinations thereof, are registered trademarks, and Everywhere You Are® are the trademarks of Atmel Corporation or its subsidiaries. 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IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUTOF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes norepresentationsor warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specificationsand product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for useas components in applications intended to support or sustainlife. Atmel Corporation Atmel Operations 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Literature Requests www.atmel.com/literature MSP430 Hardware Tools User's Guide Literature Number: SLAU278R May 2009–Revised May 2014 Contents Preface ........................................................................................................................................ 8 1 Get Started Now!................................................................................................................ 11 1.1 Flash Emulation Tool (FET) Overview................................................................................... 12 1.2 Kit Contents, MSP-FET430PIF........................................................................................... 13 1.3 Kit Contents, eZ430-F2013 ............................................................................................... 13 1.4 Kit Contents, eZ430-T2012 ............................................................................................... 13 1.5 Kit Contents, eZ430-RF2500 ............................................................................................. 13 1.6 Kit Contents, eZ430-RF2500T............................................................................................ 13 1.7 Kit Contents, eZ430-RF2500-SEH....................................................................................... 13 1.8 Kit Contents, eZ430-Chronos-xxx........................................................................................ 14 1.9 Kit Contents, MSP-FET430UIF........................................................................................... 14 1.10 Kit Contents, MSP-FET.................................................................................................... 14 1.11 Kit Contents, MSP-FET430xx ............................................................................................ 14 1.12 Kit Contents, FET430F6137RF900 ...................................................................................... 15 1.13 Kit Contents, MSP-TS430xx .............................................................................................. 15 1.14 Kit Contents, EM430Fx1x7RF900 ....................................................................................... 17 1.15 Hardware Installation, MSP-FET430PIF ................................................................................ 17 1.16 Hardware Installation, MSP-FET430UIF ................................................................................ 18 1.17 Hardware Installation, MSP-FET ......................................................................................... 18 1.18 Hardware Installation, eZ430-XXXX, MSP-EXP430G2, MSP-EXP430FR5739, MSP-EXP430F5529.......... 18 1.19 Hardware Installation, MSP-FET430Uxx, MSP-TS430xxx, FET430F6137RF900, EM430Fx137RF900 ....... 19 1.20 Important MSP430 Documents on the Web ............................................................................ 20 2 Design Considerations for In-Circuit Programming ................................................................ 21 2.1 Signal Connections for In-System Programming and Debugging ................................................... 22 2.2 External Power ............................................................................................................. 26 2.3 Bootstrap Loader (BSL) ................................................................................................... 26 A Frequently Asked Questions and Known Issues .................................................................... 27 A.1 Hardware FAQs ............................................................................................................ 28 A.2 Known Issues ............................................................................................................... 30 B Hardware........................................................................................................................... 31 B.1 MSP-TS430D8.............................................................................................................. 33 B.2 MSP-TS430PW14.......................................................................................................... 36 B.3 MSP-TS430L092 ........................................................................................................... 39 B.4 MSP-TS430L092 Active Cable ........................................................................................... 42 B.5 MSP-TS430PW24.......................................................................................................... 45 B.6 MSP-TS430DW28.......................................................................................................... 48 B.7 MSP-TS430PW28.......................................................................................................... 51 B.8 MSP-TS430PW28A........................................................................................................ 54 B.9 MSP-TS430RHB32A....................................................................................................... 57 B.10 MSP-TS430DA38 .......................................................................................................... 60 B.11 MSP-TS430QFN23x0...................................................................................................... 63 B.12 MSP-TS430RSB40......................................................................................................... 66 B.13 MSP-TS430RHA40A....................................................................................................... 69 B.14 MSP-TS430DL48........................................................................................................... 72 2 Contents SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com B.15 MSP-TS430RGZ48B....................................................................................................... 75 B.16 MSP-TS430RGZ48C ...................................................................................................... 78 B.17 MSP-TS430PM64 .......................................................................................................... 81 B.18 MSP-TS430PM64A ........................................................................................................ 84 B.19 MSP-TS430RGC64B ...................................................................................................... 87 B.20 MSP-TS430RGC64C ...................................................................................................... 90 B.21 MSP-TS430RGC64USB................................................................................................... 94 B.22 MSP-TS430PN80 .......................................................................................................... 98 B.23 MSP-TS430PN80A ....................................................................................................... 101 B.24 MSP-TS430PN80USB ................................................................................................... 104 B.25 MSP-TS430PZ100........................................................................................................ 108 B.26 MSP-TS430PZ100A...................................................................................................... 111 B.27 MSP-TS430PZ100B...................................................................................................... 114 B.28 MSP-TS430PZ100C...................................................................................................... 117 B.29 MSP-TS430PZ100D...................................................................................................... 121 B.30 MSP-TS430PZ5x100..................................................................................................... 124 B.31 MSP-TS430PZ100USB .................................................................................................. 127 B.32 MSP-TS430PEU128...................................................................................................... 131 B.33 EM430F5137RF900 ...................................................................................................... 134 B.34 EM430F6137RF900 ...................................................................................................... 138 B.35 EM430F6147RF900 ...................................................................................................... 142 B.36 MSP-FET .................................................................................................................. 146 B.36.1 Features ......................................................................................................... 146 B.36.2 Release Notes .................................................................................................. 146 B.36.3 Schematics ...................................................................................................... 148 B.36.4 Layout............................................................................................................ 153 B.36.5 LED Signals ..................................................................................................... 153 B.36.6 JTAG Target Connector ....................................................................................... 154 B.36.7 Specifications ................................................................................................... 156 B.36.8 MSP-FET Revision History.................................................................................... 156 B.37 MSP-FET430PIF.......................................................................................................... 157 B.38 MSP-FET430UIF.......................................................................................................... 159 B.38.1 MSP-FET430UIF Revision History ........................................................................... 164 C Hardware Installation Guide ............................................................................................... 165 C.1 Hardware Installation ..................................................................................................... 166 Revision History ........................................................................................................................ 171 SLAU278R–May 2009–Revised May 2014 Contents 3 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com List of Figures 2-1. Signal Connections for 4-Wire JTAG Communication................................................................. 23 2-2. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire) Used by MSP430F2xx, MSP430G2xx, and MSP430F4xx Devices.............................................................................. 24 2-3. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire) Used by MSP430F5xx and MSP430F6xx Devices ..................................................................................................... 25 B-1. MSP-TS430D8 Target Socket Module, Schematic .................................................................... 33 B-2. MSP-TS430D8 Target Socket Module, PCB ........................................................................... 34 B-3. MSP-TS430PW14 Target Socket Module, Schematic ................................................................ 36 B-4. MSP-TS430PW14 Target Socket Module, PCB ....................................................................... 37 B-5. MSP-TS430L092 Target Socket Module, Schematic.................................................................. 39 B-6. MSP-TS430L092 Target Socket Module, PCB......................................................................... 40 B-7. MSP-TS430L092 Active Cable Target Socket Module, Schematic.................................................. 42 B-8. MSP-TS430L092 Active Cable Target Socket Module, PCB......................................................... 43 B-9. MSP-TS430PW24 Target Socket Module, Schematic ................................................................ 45 B-10. MSP-TS430PW24 Target Socket Module, PCB ....................................................................... 46 B-11. MSP-TS430DW28 Target Socket Module, Schematic ................................................................ 48 B-12. MSP-TS430DW28 Target Socket Module, PCB ....................................................................... 49 B-13. MSP-TS430PW28 Target Socket Module, Schematic ................................................................ 51 B-14. MSP-TS430PW28 Target Socket Module, PCB ....................................................................... 52 B-15. MSP-TS430PW28A Target Socket Module, Schematic .............................................................. 54 B-16. MSP-TS430PW28A Target Socket Module, PCB (Red) .............................................................. 55 B-17. MSP-TS430RHB32A Target Socket Module, Schematic ............................................................. 57 B-18. MSP-TS430RHB32A Target Socket Module, PCB .................................................................... 58 B-19. MSP-TS430DA38 Target Socket Module, Schematic................................................................. 60 B-20. MSP-TS430DA38 Target Socket Module, PCB........................................................................ 61 B-21. MSP-TS430QFN23x0 Target Socket Module, Schematic ............................................................ 63 B-22. MSP-TS430QFN23x0 Target Socket Module, PCB ................................................................... 64 B-23. MSP-TS430RSB40 Target Socket Module, Schematic ............................................................... 66 B-24. MSP-TS430RSB40 Target Socket Module, PCB ...................................................................... 67 B-25. MSP-TS430RHA40A Target Socket Module, Schematic ............................................................. 69 B-26. MSP-TS430RHA40A Target Socket Module, PCB .................................................................... 70 B-27. MSP-TS430DL48 Target Socket Module, Schematic ................................................................. 72 B-28. MSP-TS430DL48 Target Socket Module, PCB ........................................................................ 73 B-29. MSP-TS430RGZ48B Target Socket Module, Schematic ............................................................. 75 B-30. MSP-TS430RGZ48B Target Socket Module, PCB .................................................................... 76 B-31. MSP-TS430RGZ48C Target Socket Module, Schematic ............................................................. 78 B-32. MSP-TS430RGZ48C Target Socket Module, PCB .................................................................... 79 B-33. MSP-TS430PM64 Target Socket Module, Schematic................................................................. 81 B-34. MSP-TS430PM64 Target Socket Module, PCB........................................................................ 82 B-35. MSP-TS430PM64A Target Socket Module, Schematic............................................................... 84 B-36. MSP-TS430PM64A Target Socket Module, PCB...................................................................... 85 B-37. MSP-TS430RGC64B Target Socket Module, Schematic............................................................. 87 B-38. MSP-TS430RGC64B Target Socket Module, PCB.................................................................... 88 B-39. MSP-TS430RGC64C Target Socket Module, Schematic............................................................. 91 B-40. MSP-TS430RGC64C Target Socket Module, PCB.................................................................... 92 B-41. MSP-TS430RGC64USB Target Socket Module, Schematic ......................................................... 94 B-42. MSP-TS430RGC64USB Target Socket Module, PCB ................................................................ 95 B-43. MSP-TS430PN80 Target Socket Module, Schematic................................................................. 98 4 List of Figures SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com B-44. MSP-TS430PN80 Target Socket Module, PCB........................................................................ 99 B-45. MSP-TS430PN80A Target Socket Module, Schematic.............................................................. 101 B-46. MSP-TS430PN80A Target Socket Module, PCB..................................................................... 102 B-47. MSP-TS430PN80USB Target Socket Module, Schematic.......................................................... 104 B-48. MSP-TS430PN80USB Target Socket Module, PCB................................................................. 105 B-49. MSP-TS430PZ100 Target Socket Module, Schematic .............................................................. 108 B-50. MSP-TS430PZ100 Target Socket Module, PCB ..................................................................... 109 B-51. MSP-TS430PZ100A Target Socket Module, Schematic ............................................................ 111 B-52. MSP-TS430PZ100A Target Socket Module, PCB ................................................................... 112 B-53. MSP-TS430PZ100B Target Socket Module, Schematic ............................................................ 114 B-54. MSP-TS430PZ100B Target Socket Module, PCB ................................................................... 115 B-55. MSP-TS430PZ100C Target Socket Module, Schematic ............................................................ 117 B-56. MSP-TS430PZ100C Target Socket Module, PCB ................................................................... 118 B-57. MSP-TS430PZ100D Target Socket Module, Schematic ............................................................ 121 B-58. MSP-TS430PZ100D Target Socket Module, PCB ................................................................... 122 B-59. MSP-TS430PZ5x100 Target Socket Module, Schematic ........................................................... 124 B-60. MSP-TS430PZ5x100 Target Socket Module, PCB .................................................................. 125 B-61. MSP-TS430PZ100USB Target Socket Module, Schematic......................................................... 127 B-62. MSP-TS430PZ100USB Target Socket Module, PCB................................................................ 128 B-63. MSP-TS430PEU128 Target Socket Module, Schematic ............................................................ 131 B-64. MSP-TS430PEU128 Target Socket Module, PCB ................................................................... 132 B-65. EM430F5137RF900 Target board, Schematic........................................................................ 134 B-66. EM430F5137RF900 Target board, PCB............................................................................... 135 B-67. EM430F6137RF900 Target board, Schematic........................................................................ 138 B-68. EM430F6137RF900 Target Board, PCB .............................................................................. 139 B-69. EM430F6147RF900 Target Board, Schematic ....................................................................... 142 B-70. EM430F6147RF900 Target Board, PCB .............................................................................. 143 B-71. MSP-FET Top View ...................................................................................................... 147 B-72. MSP-FET Bottom View .................................................................................................. 147 B-73. MSP-FET USB Debugger, Schematic (1 of 5)........................................................................ 148 B-74. MSP-FET USB Debugger, Schematic (2 of 5)........................................................................ 149 B-75. MSP-FET USB Debugger, Schematic (3 of 5)........................................................................ 150 B-76. MSP-FET USB Debugger, Schematic (4 of 5)........................................................................ 151 B-77. MSP-FET USB Debugger, Schematic (5 of 5)........................................................................ 152 B-78. MSP-FET USB Debugger, PCB (Top) ................................................................................. 153 B-79. MSP-FET USB Debugger, PCB (Bottom) ............................................................................. 153 B-80. JTAG Connector Pinout.................................................................................................. 154 B-81. Pin States After Power-Up............................................................................................... 155 B-82. MSP-FET430PIF FET Interface Module, Schematic................................................................. 157 B-83. MSP-FET430PIF FET Interface Module, PCB........................................................................ 158 B-84. MSP-FET430UIF USB Interface, Schematic (1 of 4) ................................................................ 159 B-85. MSP-FET430UIF USB Interface, Schematic (2 of 4) ................................................................ 160 B-86. MSP-FET430UIF USB Interface, Schematic (3 of 4) ................................................................ 161 B-87. MSP-FET430UIF USB Interface, Schematic (4 of 4) ................................................................ 162 B-88. MSP-FET430UIF USB Interface, PCB................................................................................. 163 C-1. Windows XP Hardware Wizard ......................................................................................... 166 C-2. Windows XP Driver Location Selection Folder........................................................................ 167 C-3. Device Manager Using USB Debug Interface using VID/PID 0x2047/0x0010 ................................... 168 C-4. Device Manager Using USB Debug Interface with VID/PID 0x0451/0xF430 ..................................... 169 SLAU278R–May 2009–Revised May 2014 List of Figures 5 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com C-5. Device Manager Using USB Debug Interface With VID/PID 0x0451/0xF432 .................................... 170 6 List of Figures SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com List of Tables 1-1. Flash Emulation Tool (FET) Features and Device Compatibility..................................................... 12 1-2. Individual Kit Contents, MSP-TS430xx.................................................................................. 15 B-1. MSP-TS430D8 Bill of Materials .......................................................................................... 35 B-2. MSP-TS430PW14 Bill of Materials....................................................................................... 38 B-3. MSP-TS430L092 Bill of Materials ........................................................................................ 41 B-4. MSP-TS430L092 JP1 Settings ........................................................................................... 43 B-5. MSP-TS430L092 Active Cable Bill of Materials ........................................................................ 44 B-6. MSP-TS430PW24 Bill of Materials....................................................................................... 47 B-7. MSP-TS430DW28 Bill of Materials ...................................................................................... 50 B-8. MSP-TS430PW28 Bill of Materials ...................................................................................... 53 B-9. MSP-TS430PW28A Bill of Materials..................................................................................... 56 B-10. MSP-TS430RHB32A Bill of Materials ................................................................................... 59 B-11. MSP-TS430DA38 Bill of Materials ....................................................................................... 62 B-12. MSP-TS430QFN23x0 Bill of Materials .................................................................................. 65 B-13. MSP-TS430RSB40 Bill of Materials ..................................................................................... 68 B-14. MSP-TS430RHA40A Bill of Materials ................................................................................... 71 B-15. MSP-TS430DL48 Bill of Materials ....................................................................................... 74 B-16. MSP-TS430RGZ48B Bill of Materials ................................................................................... 77 B-17. MSP-TS430RGZ48C Revision History .................................................................................. 79 B-18. MSP-TS430RGZ48C Bill of Materials ................................................................................... 80 B-19. MSP-TS430PM64 Bill of Materials....................................................................................... 83 B-20. MSP-TS430PM64A Bill of Materials ..................................................................................... 86 B-21. MSP-TS430RGC64B Bill of Materials ................................................................................... 89 B-22. MSP-TS430RGC64C Bill of Materials ................................................................................... 93 B-23. MSP-TS430RGC64USB Bill of Materials ............................................................................... 96 B-24. MSP-TS430PN80 Bill of Materials...................................................................................... 100 B-25. MSP-TS430PN80A Bill of Materials.................................................................................... 103 B-26. MSP-TS430PN80USB Bill of Materials ................................................................................ 106 B-27. MSP-TS430PZ100 Bill of Materials .................................................................................... 110 B-28. MSP-TS430PZ100A Bill of Materials................................................................................... 113 B-29. MSP-TS430PZ100B Bill of Materials................................................................................... 116 B-30. MSP-TS430PZ100C Bill of Materials .................................................................................. 119 B-31. MSP-TS430PZ100D Bill of Materials .................................................................................. 123 B-32. MSP-TS430PZ5x100 Bill of Materials.................................................................................. 126 B-33. MSP-TS430PZ100USB Bill of Materials ............................................................................... 129 B-34. MSP-TS430PEU128 Bill of Materials .................................................................................. 133 B-35. EM430F5137RF900 Bill of Materials................................................................................... 136 B-36. EM430F6137RF900 Bill of Materials................................................................................... 140 B-37. EM430F6147RF900 Bill of Materials................................................................................... 144 B-38. UART Backchannel Implementation ................................................................................... 146 B-39. MSP-FET LED Signals................................................................................................... 153 B-40. JTAG Connector Pin State by Operating Mode ...................................................................... 154 B-41. Specifications.............................................................................................................. 156 B-42. MSP-FET Revision History .............................................................................................. 156 C-1. USB VIDs and PIDs Used in MSP430 Tools.......................................................................... 166 SLAU278R–May 2009–Revised May 2014 List of Tables 7 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Preface SLAU278R–May 2009–Revised May 2014 Read This First About This Manual This manual describes the hardware of the Texas Instruments MSP-FET430 Flash Emulation Tool (FET). The FET is the program development tool for the MSP430™ ultra-low-power microcontroller. Both available interface types, the parallel port interface and the USB interface, are described. How to Use This Manual Read and follow the instructions in Chapter 1. This chapter lists the contents of the FET, provides instructions on installing the hardware and according software drivers. After you see how quick and easy it is to use the development tools, TI recommends that you read all of this manual. This manual describes the setup and operation of the FET but does not fully describe the MSP430™ microcontrollers or the development software systems. For details of these items, see the appropriate TI documents listed in Section 1.20. This manual applies to the following tools (and devices): • MSP-FET430PIF (debug interface with parallel port connection, for all MSP430 flash-based devices) • MSP-FET430UIF (debug interface with USB connection, for all MSP430 flash-based devices) • MSP-FET (successor to MSP-FET430UIF, debug interface with USB connection, for all MSP430 devices) • eZ430-F2013 (USB stick form factor interface with attached MSP430F2013 target, for all MSP430F20xx, MSP430G2x01, MSP430G2x11, MSP430G2x21, and MSP430G2x31 devices) • eZ430-T2012 (three MSP430F2012 based target boards) • eZ430-RF2500 (USB stick form factor interface with attached MSP430F2274 and CC2500 target, for all MSP430F20xx, MSP430F21x2, MSP430F22xx, MSP430G2x01, MSP430G2x11, MSP430G2x21, and MSP430G2x31 devices) • eZ430-RF2500T (one MSP430F2274 and CC2500 target board including battery pack) • eZ430-RF2500-SEH (USB stick form factor interface with attached MSP430F2274 and CC2500 target and solar energy harvesting module) • eZ430-Chronos-xxx (USB stick form factor interface with CC430F6137 based development system contained in a watch. Includes <1 GHz RF USB access point) Stand-alone target-socket modules (without debug interface) named as MSP-TS430TSxx. Tools named as MSP-FET430Uxx contain the USB debug interface (MSP-FET430UIF) and the respective target socket module MSP-TS430TSxx, where 'xx' is the same for both names. The following tools contain also the USB debug interface (MSP-FET430UIF): • FET430F5137RF900 (for CC430F513x devices in 48-pin RGZ packages) (green PCB) • FET430F6137RF900 (for CC430F612x and CC430F613x devices in 64-pin RGC packages) (green PCB) These tools contain the most up-to-date materials available at the time of packaging. For the latest materials (data sheets, user's guides, software, application information, and so on), visit the TI MSP430 web site at www.ti.com/msp430 or contact your local TI sales office. 8 Read This First SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com Information About Cautions and Warnings Information About Cautions and Warnings This document may contain cautions and warnings. CAUTION This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. WARNING This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. The information in a caution or a warning is provided for your protection. Read each caution and warning carefully. Related Documentation From Texas Instruments MSP430 development tools documentation: Code Composer Studio for MSP430 User's Guide (literature number SLAU157) Code Composer Studio v5.x Core Edition (CCS Mediawiki) IAR Embedded Workbench for MSP430(tm) User's Guide (literature number SLAU138) IAR Embedded Workbench KickStart installer (literature number SLAC050) eZ430-F2013 Development Tool User's Guide (literature number SLAU176) eZ430-RF2480 Demonstration Kit User's Guide (literature number SWRU151) eZ430-RF2500 Development Tool User's Guide (literature number SLAU227) eZ430-RF2500-SEH Development Tool User's Guide (literature number SLAU273) eZ430-Chronos Development Tool User's Guide (literature number SLAU292) Spectrum Analyzer (MSP-SA430-SUB1GHZ) User's Guide (literature number SLAU371) MSP-EXP430F5529 Experimenter Board User's Guide (literature number SLAU330) MSP-EXP430F5438 Experimenter Board User's Guide (literature number SLAU263) MSP-EXP430G2 LaunchPad Experimenter Board User's Guide (literature number SLAU318) MSP Gang Programmer (MSP-GANG) User's Guide (literature number SLAU358) MSP430 Gang Programmer (MSP-GANG430) User's Guide (literature number SLAU101) MSP430 device user's guides: MSP430x1xx Family User's Guide (literature number SLAU049) MSP430x2xx Family User's Guide (literature number SLAU144) MSP430x3xx Family User's Guide (literature number SLAU012) MSP430x4xx Family User's Guide (literature number SLAU056) MSP430x5xx and MSP430x6xx Family User's Guide (literature number SLAU208) CC430 Family User's Guide (literature number SLAU259) SLAU278R–May 2009–Revised May 2014 Read This First 9 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated If You Need Assistance www.ti.com MSP430FR57xx Family User's Guide (literature number SLAU272) MSP430FR58xx and MSP430FR59xx Family User's Guide (literature number SLAU367) If You Need Assistance Support for the MSP430 devices and the FET development tools is provided by the Texas Instruments Product Information Center (PIC). Contact information for the PIC can be found on the TI web site at www.ti.com/support. The Texas Instruments E2E Community support forums for the MSP430 provide open interaction with peer engineers, TI engineers, and other experts. Additional device-specific information can be found on the MSP430 web site. 10 Read This First SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Chapter 1 SLAU278R–May 2009–Revised May 2014 Get Started Now! This chapter lists the contents of the FET and provides instruction on installing the hardware. Topic ........................................................................................................................... Page 1.1 Flash Emulation Tool (FET) Overview ................................................................... 12 1.2 Kit Contents, MSP-FET430PIF.............................................................................. 13 1.3 Kit Contents, eZ430-F2013................................................................................... 13 1.4 Kit Contents, eZ430-T2012................................................................................... 13 1.5 Kit Contents, eZ430-RF2500 ................................................................................ 13 1.6 Kit Contents, eZ430-RF2500T............................................................................... 13 1.7 Kit Contents, eZ430-RF2500-SEH ......................................................................... 13 1.8 Kit Contents, eZ430-Chronos-xxx......................................................................... 14 1.9 Kit Contents, MSP-FET430UIF.............................................................................. 14 1.10 Kit Contents, MSP-FET ....................................................................................... 14 1.11 Kit Contents, MSP-FET430xx .............................................................................. 14 1.12 Kit Contents, FET430F6137RF900 ........................................................................ 15 1.13 Kit Contents, MSP-TS430xx ................................................................................. 15 1.14 Kit Contents, EM430Fx1x7RF900.......................................................................... 17 1.15 Hardware Installation, MSP-FET430PIF ................................................................. 17 1.16 Hardware Installation, MSP-FET430UIF ................................................................. 18 1.17 Hardware Installation, MSP-FET........................................................................... 18 1.18 Hardware Installation, eZ430-XXXX, MSP-EXP430G2, MSP-EXP430FR5739, MSPEXP430F5529..................................................................................................... 18 1.19 Hardware Installation, MSP-FET430Uxx, MSP-TS430xxx, FET430F6137RF900, EM430Fx137RF900 ............................................................................................. 19 1.20 Important MSP430 Documents on the Web............................................................ 20 SLAU278R–May 2009–Revised May 2014 Get Started Now! 11 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Flash Emulation Tool (FET) Overview www.ti.com 1.1 Flash Emulation Tool (FET) Overview TI offers several flash emulation tools according to different requirements. Table 1-1. Flash Emulation Tool (FET) Features and Device Compatibility(1) eZ430-F2013 eZ430-RF2500 eZ430-RF2480 eZ430-RF2560 MSP-WDSxx Metawatch eZ430-Chronos MSP-FET430PIF MSP-FET430UIF LaunchPad (MSP-EXP430G2) MSP-EXP430FR5739 MSP-EXP430F5529 Supports all programmable MSP430 and CC430 devices (F1xx, F2xx, F4xx, F5xx, F6xx, G2xx, L092, FR57xx, FR59xx, x x MSP430TCH5E) Supports only F20xx, G2x01, G2x11, x G2x21, G2x31 Supports MSP430F20xx, F21x2, F22xx, x G2x01, G2x11, G2x21, G2x31, G2x53 Supports MSP430F20xx, F21x2, F22xx, x x G2x01, G2x11, G2x21, G2x31 Supports F5438, F5438A x Supports BT5190, F5438A x x Supports only F552x x Supports FR57xx, F5638, F6638 x Supports only CC430F613x x Allows fuse blow x Adjustable target supply voltage x Fixed 2.8-V target supply voltage x Fixed 3.6-V target supply voltage x x x x x x x x x 4-wire JTAG x x 2-wire JTAG(2) x x x x x x x x x x Application UART x x x x x x x x Supported by CCS for Windows x x x x x x x x x x x Supported by CCS for Linux x Supported by IAR x x x x x x x x x x x (1) The MSP-FET430PIF is for legacy device support only. This emulation tool will not support any new devices released after 2011. (2) The 2-wire JTAG debug interface is also referred to as Spy-Bi-Wire (SBW) interface. 12 Get Started Now! SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com Kit Contents, MSP-FET430PIF 1.2 Kit Contents, MSP-FET430PIF • One READ ME FIRST document • One MSP-FET430PIF interface module • One 25-conductor cable • One 14-conductor cable NOTE: This part is obsolete and is not recommended to use in new design. 1.3 Kit Contents, eZ430-F2013 • One QUICK START GUIDE document • One eZ430-F2013 development tool including one MSP430F2013 target board 1.4 Kit Contents, eZ430-T2012 • Three MSP430F2012-based target boards 1.5 Kit Contents, eZ430-RF2500 • One QUICK START GUIDE document • One eZ430-RF2500 CD-ROM • One eZ430-RF2500 development tool including one MSP430F2274 and CC2500 target board • One eZ430-RF2500T target board • One AAA battery pack with expansion board (batteries included) 1.6 Kit Contents, eZ430-RF2500T • One eZ430-RF2500T target board • One AAA battery pack with expansion board (batteries included) 1.7 Kit Contents, eZ430-RF2500-SEH • One MSP430 development tool CD containing documentation and development software • One eZ430-RF USB debugging interface • Two eZ430-RF2500T wireless target boards • One SEH-01 solar energy harvester board • One AAA battery pack with expansion board (batteries included) SLAU278R–May 2009–Revised May 2014 Get Started Now! 13 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Kit Contents, eZ430-Chronos-xxx www.ti.com 1.8 Kit Contents, eZ430-Chronos-xxx '433, '868, '915 • One QUICK START GUIDE document • One ez430-Chronos emulator • One screwdriver • Two spare screws eZ430-Chronos-433: – One 433-MHz eZ430-Chronos watch (battery included) – One 433-MHz eZ430-Chronos access point eZ430-Chronos-868: – One 868-MHz eZ430-Chronos watch (battery included) – One 868-MHz eZ430-Chronos access point eZ430-Chronos-915: – One 915-MHz eZ430-Chronos watch (battery included) – One 915-MHz eZ430-Chronos access point 1.9 Kit Contents, MSP-FET430UIF • One READ ME FIRST document • One MSP-FET430UIF interface module • One USB cable • One 14-conductor cable 1.10 Kit Contents, MSP-FET • One READ ME FIRST document • One MSP-FET interface module • One USB cable • One 14-conductor cable 1.11 Kit Contents, MSP-FET430xx • One READ ME FIRST document • One MSP-FET430UIF USB interface module. This is the unit that has a USB B-connector on one end of the case, and a 2×7-pin male connector on the other end of the case. • One USB cable • One 32.768-kHz crystal from Micro Crystal, if the board has an option to use the quartz. • A 2×7-pin male JTAG connector is also present on the PCB (see different setup for L092) • One 14-Pin JTAG conductor cable • One small box containing two MSP430 device samples (See table for Sample Type) • One target socket module. To determine the devices used for each board and a summary of the board, see Table 1-2. The name of MSP-TS430xx board can be derived from the name of the MSP-FET430xx kit; for example, the MSP-FET430U28A kit contains the MSP-TS430PW28A board. Refer to the device data sheets for device specifications. Device errata can be found in the respective device product folder on the web provided as a PDF document. Depending on the device, errata may also be found in the device bug database at www.ti.com/sc/cgi-bin/buglist.cgi. 14 Get Started Now! SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com Kit Contents, FET430F6137RF900 1.12 Kit Contents, FET430F6137RF900 • One READ ME FIRST document • One legal notice • One MSP-FET430UIF interface module • Two EM430F6137RF900 target socket modules. This is the PCB on which is soldered a CC430F6137 device in a 64-pin RGC package. A 2×7-pin male connector is also present on the PCB. • Two CC430EM battery packs • Four AAA batteries • Two 868-MHz or 915-MHz antennas • Two 32.768-kHz crystals • 18 PCB 2x4-pin headers • One USB cable • One 14-pin JTAG conductor cable 1.13 Kit Contents, MSP-TS430xx • One READ ME FIRST document • One 32.768-kHz crystal from Micro Crystal (except MSP-TS430PW24) • One target socket module • A 2×7-pin male JTAG connector is also present on the PCB (see different setup for L092) • MSP430 device samples (see Table 1-2 for sample type) Table 1-2. Individual Kit Contents, MSP-TS430xx Part Number Socket Type Supported Devices Included Devices Headers and Comment MSP-TS430D8 8-pin D MSP430G2210, 1 x MSP430G2210ID and Two PCB 1×4-pin headers (two male and (green PCB) (TSSOP ZIF) MSP430G2230 1 x MSP430G2230ID two female) MSP430F20xx, MSP-TS430PW14 14-pin PW MSP430G2x01, Four PCB 1×7-pin headers (two male and (green PCB) (TSSOP ZIF) MSP430G2x11, 2 x MSP430F2013IPW two female) MSP430G2x21, MSP430G2x31 Four PCB 1×7-pin headers (two male and two female). A "Micro-MaTch" 10-pin MSP-TS430L092 14-pin PW female connector is also present on the (green PCB) (TSSOP ZIF) MSP-TS430L092 2 x MSP430L092IPW PCB which connects the kit with an 'Active Cable' PCB; this 'Active Cable' PCB is connected by 14-pin JTAG cable with the FET430UIF MSP-TS430PW24 24-pin PW MSP430AFE2xx 2 x MSP430AFE253IPW Four PCB 1×12-pin headers (two male (green PCB) (TSSOP ZIF) and two female) MSP430F11x1, MSP430F11x2, MSP-TS430DW28 28-pin DW MSP430F12x, Four PCB 1×12-pin headers (two male (green PCB) (SSOP ZIF) MSP430F12x2, 2 x MSP430F123IDW and two female) MSP430F21xx Supports devices in 20- and 28-pin DA packages MSP430F11x1, MSP-TS430PW28 28-pin PW MSP430F11x2, Four PCB 1×12-pin headers (two male (green PCB) (TSSOP ZIF) MSP430F12x, 2 x MSP430F2132IPW and two female) MSP430F12x2, MSP430F21xx MSP430F20xx, MSP-TS430PW28A 28-pin PW MSP430G2xxx in 14-, 20-, Four PCB 1×12-pin headers (two male (red PCB) (TSSOP ZIF) and 28-pin PW packages, 2 x MSP430G2452IPW20 and two female) MSP430TCH5E in PW package MSP-TS430RHB32A 32-pin RHB MSP430i204x 2 x MSP430i2041TRHB Eight PCB 1×8-pin headers (four male (red PCB) (QFN ZIF) and four female) MSP-TS430DA38 38-pin DA MSP430F22xx, 2 x MSP430F2274IDA Four PCB 1×19-pin headers (two male (green PCB) (TSSOP ZIF) MSP430G2x44, 2 x MSP430G2744IDA and two female) MSP430G2x55 2 x MSP430G2955IDA SLAU278R–May 2009–Revised May 2014 Get Started Now! 15 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Kit Contents, MSP-TS430xx www.ti.com Table 1-2. Individual Kit Contents, MSP-TS430xx (continued) Part Number Socket Type Supported Devices Included Devices Headers and Comment MSP-TS430QFN23x0 40-pin RHA MSP430F23x0 2 x MSP430F2370IRHA Eight PCB 1×10-pin headers (four male (green PCB) (QFN ZIF) and four female) MSP-TS430RSB40 40-pin RSB MSP430F51x1, 2 x MSP430F5172IRSB Eight PCB 1×10-pin headers (four male (green PCB) (QFN ZIF) MSP430F51x2 and four female) MSP-TS430RHA40A 40-pin RHA MSP430FR572x, 2 x MSP430FR5739IRHA Eight PCB 1×10-pin headers (four male (red PCB) (QFN ZIF) MSP430FR573x and four female) MSP-TS430DL48 48-pin DL MSP430F42x0 2 x MSP430F4270IDL Four PCB 2×12-pin headers (two male (green PCB) (TSSOP ZIF) and two female) MSP-TS430RGZ48B 48-pin RGZ MSP430F534x 2 x MSP430F5342IRGZ Eight PCB 1×12-pin headers (four male (blue PCB) (QFN ZIF) and four female) MSP-TS430RGZ48C 48-pin RGZ MSP430FR58xx and 2 x MSP430FR5969IRGZ Eight PCB 1×12-pin headers (four male (black PCB) (QFN ZIF) MSP430FR59xx and four female) MSP430F13x, MSP430F14x, MSP430F14x1, MSP430F15x, MSP430F16x, MSP430F16x1, MSP430F23x, TS Kit: MSP-TS430PM64 64-pin PM MSP430F24x, 2 x MSP430F2618IPM; Eight PCB 1×16-pin headers (four male (green PCB) (QFP ZIF) MSP430F24xx, FET Kit: and four female) MSP430F261x, 2 x MSP430F417IPM and MSP430F41x, 2 x MSP430F169IPM MSP430F42x, MSP430F42xA, MSP430FE42x, MSP430FE42xA, MSP430FE42x2, MSP430FW42x MSP-TS430PM64A 64-pin PM MSP430F41x2 2 x MSP430F4152IPM Eight PCB 1×16-pin headers (four male (red PCB) (QFP ZIF) and four female) MSP-TS430RGC64B 64-pin RGC MSP430F530x 2 x MSP430F5310IRGC Eight PCB 1×16-pin headers (four male (blue PCB) (QFN ZIF) and four female) MSP430F522x, MSP-TS430RGC64C 64-pin RGC MSP430F521x , Eight PCB 1×16-pin headers (four male (black PCB) (QFN ZIF) MSP430F523x, 2 x MSP430F5229IRGC and four female) MSP430F524x, MSP430F525x MSP-TS430RGC64USB 64-pin RGC MSP430F550x, 2 x MSP430F5510IRGC or Eight PCB 1×16-pin headers (four male (green PCB) (QFN ZIF) MSP430F551x, 2 x MSP430F5528IRGC and four female) MSP430F552x MSP430F241x, MSP430F261x, MSP-TS430PN80 80-pin PN MSP430F43x, Eight PCB 1×20-pin headers (four male (green PCB) (QFP ZIF) MSP430F43x1, 2 x MSP430FG439IPN and four female) MSP430FG43x, MSP430F47x, MSP430FG47x MSP-TS430PN80A 80-pin PN MSP430F532x 2 x MSP430F5329IPN Eight PCB 1×20-pin headers (four male (red PCB) (QFP ZIF) and four female) MSP-TS430PN80USB 80-pin PN MSP430F552x, 2 x MSP430F5529IPN Eight PCB 1×20-pin headers (four male (green PCB) (QFP ZIF) MSP430F551x and four female) MSP430F43x, MSP-TS430PZ100 100-pin PZ MSP430F43x1, Eight PCB 1×25-pin headers (four male (green PCB) (QFP ZIF) MSP430F44x, 2 x MSP430FG4619IPZ and four female) MSP430FG461x, MSP430F47xx MSP-TS430PZ100A 100-pin PZ MSP430F471xx 2 x MSP430F47197IPZ Eight PCB 1×25-pin headers (four male (red PCB) (QFP ZIF) and four female) MSP-TS430PZ100B 100-pin PZ MSP430F67xx 2 x MSP430F6733IPZ Eight PCB 1×25-pin headers (four male (blue PCB) (QFP ZIF) and four female) MSP430F645x, MSP-TS430PZ100C 100-pin PZ MSP430F643x, 2 x MSP430F6438IPZ Eight PCB 1×25-pin headers (four male (black PCB) (QFP ZIF) MSP430F535x, and four female) MSP430F533x MSP-TS430PZ100D 100-pin PZ MSP430FR698x(1), 2 x MSP430FR6989IPZ Eight PCB 1×25-pin headers (four male (white PCB) (QFP ZIF) MSP430FR688x(1) and four female) 16 Get Started Now! SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com Kit Contents, EM430Fx1x7RF900 Table 1-2. Individual Kit Contents, MSP-TS430xx (continued) Part Number Socket Type Supported Devices Included Devices Headers and Comment MSP-TS430PZ5x100 100-pin PZ MSP430F543x, Eight PCB 1×25-pin headers (four male (green PCB) (QFP ZIF) MSP430BT5190, 2 x MSP430F5438IPZ and four female) MSP430SL5438A MSP-TS430PZ100USB 100-pin PZ MSP430F665x, Eight PCB 1×25-pin headers (four male (green PCB) (QFP ZIF) MSP430F663x, 2 x MSP430F6638IPZ and four female) MSP430F563x MSP430F677x, MSP430F676x, Four PCB 1x26-pin headers (two male MSP-TS430PEU128 128-pin PEU MSP430F674x, 2 x MSP430F67791IPEU and two female) and four PCB 1x38-pin (green PCB) (QFP ZIF) MSP430F677x1, headers (two male and two female) MSP430F676x1, MSP430F674x1 See the device data sheets for device specifications. Device errata can be found in the respective device product folder on the web provided as a PDF document. Depending on the device, errata may also be found in the device bug database at www.ti.com/sc/cgi-bin/buglist.cgi. 1.14 Kit Contents, EM430Fx1x7RF900 • One READ ME FIRST document • One legal notice • Two target socket module MSP-EM430F5137RF900: Two EM430F5137RF900 target socket modules. This is the PCB on which is soldered a CC430F5137 device in a 48-pin RGZ package. A 2×7-pin male connector is also present on the PCB MSP-EM430F6137RF900: Two EM430F6137RF900 target socket modules. This is the PCB on which is soldered a CC430F6137 device in a 64-pin RGC package. A 2×7-pin male connector is also present on the PCB MSP-EM430F6147RF900: Two EM430F6147RF900 target socket modules. This is the PCB on which is soldered a CC430F6147 device in a 64-pin RGC package. A 2×7-pin male connector is also present on the PCB • Two CC430EM battery packs • Four AAA batteries • Two 868- or 915-MHz antennas • Two 32.768-kHz crystals • 18 PCB 2×4-pin headers 1.15 Hardware Installation, MSP-FET430PIF Follow these steps to install the hardware for the MSP-FET430PIF tools: 1. Use the 25-conductor cable to connect the FET interface module to the parallel port of the PC. The necessary driver for accessing the PC parallel port is installed automatically during CCS or IAR Embedded Workbench installation. Note that a restart is required after the CCS or IAR Embedded Workbench installation for the driver to become active. 2. Use the 14-conductor cable to connect the parallel-port debug interface module to a target board, such as an MSP-TS430xxx target socket module. Module schematics and PCBs are shown in Appendix B. SLAU278R–May 2009–Revised May 2014 Get Started Now! 17 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Hardware Installation, MSP-FET430UIF www.ti.com 1.16 Hardware Installation, MSP-FET430UIF Follow these steps to install the hardware for the MSP-FET430UIF tool: 1. Install the IDE (CCS or IAR) you plan to use before connecting USB-FET interface to PC. The IDE installation installs drivers automatically. 2. Use the USB cable to connect the USB-FET interface module to a USB port on the PC. The USB FET should be recognized, as the USB device driver is installed automatically. If the driver has not been installed yet, the install wizard starts. Follow the prompts and point the wizard to the driver files. The default location for CCS is c:\ti\ccsv5\ccs_base\emulation\drivers\msp430\USB_CDC or c:\ti\ccsv5\ccs_base\emulation\drivers\msp430\USB_FET_XP_XX, depending of firmware version of the tool. The default location for IAR Embedded Workbench is \Embedded Workbench x.x\430\drivers\TIUSBFET\eZ430-UART or \Embedded Workbench x.x\430\drivers\, depending of firmware version of the tool. The USB driver is installed automatically. Detailed driver installation instructions can be found in Appendix C. 3. After connecting to a PC, the USB FET performs a self-test during which the red LED may flash for approximately two seconds. If the self-test passes successfully, the green LED stays on. 4. Use the 14-conductor cable to connect the USB-FET interface module to a target board, such as an MSP-TS430xxx target socket module. 5. Ensure that the MSP430 device is securely seated in the socket, and that its pin 1 (indicated with a circular indentation on the top surface) aligns with the "1" mark on the PCB. 6. Compared to the parallel-port debug interface, the USB FET has additional features including JTAG security fuse blow and adjustable target VCC (1.8 V to 3.6 V). Supply the module with up to 60 mA. 1.17 Hardware Installation, MSP-FET Follow these steps to install the hardware for the MSP-FET tool: 1. Install the IDE (CCS or IAR) that you plan to use before connecting MSP-FET to PC. During IDE installation, USB drivers are installed automatically. Make sure to use the latest IDE version, otherwise the USB drivers might not be able to recognize the MSP-FET. 2. Connect the MSP-FET to a USB port on the PC with the provided USB cable. 3. The following procedure applies to operation under Windows: (a) After connecting to the PC, the MSP-FET should be recognized automatically, as the USB device driver has been already installed together with the IDE. (b) If the driver has not been installed yet, the Found New Hardware wizard starts. Follow the instructions and point the wizard to the driver files. (c) The default location for CCS is c:\ti\ccsv6\ccs_base\emulation\drivers\msp430\USB_CDC. (d) The default location for IAR Embedded Workbench is \Embedded Workbench x.x\430\drivers\. 4. After connecting to a PC, the MSP-FET performs a self-test. If the self-test passes successfully, the green LED stays on. For a complete list of LED signals, please refer to the MSP-FET chapter in this document. 5. Connect the MSP-FET to a target board, such as an MSP-TS430xxx target socket module, with the 14-conductor cable. 6. Make sure that the MSP430 device is securely seated in the socket and that its pin 1 (indicated with a circular indentation on the top surface) aligns with the "1" mark on the PCB. 1.18 Hardware Installation, eZ430-XXXX, MSP-EXP430G2, MSP-EXP430FR5739, MSPEXP430F5529 To install the eZ430-XXXX, MSP-EXP430G2, MSP-EXP430FR5739, MSP-EXP430F5529 tools, follow steps 1 and 2 of Section 1.16 18 Get Started Now! SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com Hardware Installation, MSP-FET430Uxx, MSP-TS430xxx, FET430F6137RF900, EM430Fx137RF900 1.19 Hardware Installation, MSP-FET430Uxx, MSP-TS430xxx, FET430F6137RF900, EM430Fx137RF900 Follow these steps to install the hardware for the MSP-FET430Uxx and MSP-TS430xxx tools: 1. Follow steps 1 and 2 of Section 1.16 2. Connect the MSP-FET430PIF or MSP-FET430UIF debug interface to the appropriate port of the PC. Use the 14-conductor cable to connect the FET interface module to the supplied target socket module. 3. Ensure that the MSP430 device is securely seated in the socket and that its pin 1 (indicated with a circular indentation on the top surface) aligns with the "1" mark on the PCB. 4. Ensure that the two jumpers (LED and VCC) near the 2×7-pin male connector are in place. Illustrations of the target socket modules and their parts are found in Appendix B. SLAU278R–May 2009–Revised May 2014 Get Started Now! 19 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Important MSP430 Documents on the Web www.ti.com 1.20 Important MSP430 Documents on the Web The primary sources of MSP430 information are the device-specific data sheet and user's guide. The MSP430 web site (www.ti.com/msp430) contains the most recent version of these documents. PDF documents describing the CCS tools (CCS IDE, the assembler, the C compiler, the linker, and the librarian) are in the msp430\documentation folder. A Code Composer Studio specific Wiki page (FAQ) is available, and the Texas Instruments E2E Community support forums for the MSP430 and Code Composer Studio v5 provide additional help besides the product help and Welcome page. PDF documents describing the IAR tools (Workbench C-SPY, the assembler, the C compiler, the linker, and the librarian) are in the common\doc and 430\doc folders. Supplements to the documents (that is, the latest information) are available in HTML format in the same directories. A IAR specific Wiki Page is also available. 20 Get Started Now! SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Chapter 2 SLAU278R–May 2009–Revised May 2014 Design Considerations for In-Circuit Programming This chapter presents signal requirements for in-circuit programming of the MSP430. Topic ........................................................................................................................... Page 2.1 Signal Connections for In-System Programming and Debugging............................. 22 2.2 External Power................................................................................................... 26 2.3 Bootstrap Loader (BSL) ...................................................................................... 26 SLAU278R–May 2009–Revised May 2014 Design Considerations for In-Circuit Programming 21 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Signal Connections for In-System Programming and Debugging www.ti.com 2.1 Signal Connections for In-System Programming and Debugging MSP-FET430PIF, MSP-FET430UIF, MSP-GANG, MSP-GANG430, MSP-PRGS430 With the proper connections, the debugger and an FET hardware JTAG interface (such as the MSPFET430PIF and MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the connections also support the MSP-GANG430 or MSP-PRGS430 production programmers, thus providing an easy way to program prototype boards, if desired. Figure 2-1 shows the connections between the 14-pin FET interface module connector and the target device required to support in-system programming and debugging for 4-wire JTAG communication. Figure 2-2 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire). The 4-wire JTAG mode is supported on most MSP430 devices, except devices with low pin counts (for example, MSP430G2230). The 2-wire JTAG mode is available on selected devices only. See the Code Composer Studio for MSP430 User's Guide (SLAU157) or IAR Embedded Workbench Version 3+ for MSP430 User's Guide (SLAU138) for information on which interface method can be used on which device. The connections for the FET interface module and the MSP-GANG, MSP-GANG430, or MSP-PRGS430 are identical. Both the FET interface module and MSP-GANG430 can supply VCC to the target board (through pin 2). In addition, the FET interface module, MSP-GANG, and MSP-GANG430 have a VCCsense feature that, if used, requires an alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the target board (that is, a battery or other local power supply) and adjusts the output signals accordingly. If the target board is to be powered by a local VCC, then the connection to pin 4 on the JTAG should be made, and not the connection to pin 2. This uses the VCCsense feature and prevents any contention that might occur if the local on-board VCC were connected to the VCC supplied from the FET interface module, MSP-GANG or the MSP-GANG430. If the VCC-sense feature is not necessary (that is, if the target board is to be powered from the FET interface module, MSPGANG, or MSP-GANG430), the VCC connection is made to pin 2 on the JTAG header, and no connection is made to pin 4. Figure 2-1 and Figure 2-2 show a jumper block that supports both scenarios of supplying VCC to the target board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the jumper block. Pins 2 and 4 must not be connected at the same time. Note that in 4-wire JTAG communication mode (see Figure 2-1), the connection of the target RST signal to the JTAG connector is optional when using devices that support only 4-wire JTAG communication mode. However, when using devices that support 2-wire JTAG communication mode in 4-wire JTAG mode, the RST connection must be made. The MSP430 development tools and device programmers perform a target reset by issuing a JTAG command to gain control over the device. However, if this is unsuccessful, the RST signal of the JTAG connector may be used by the development tool or device programmer as an additional way to assert a device reset. 22 Design Considerations for In-Circuit Programming SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated 1 3 5 7 9 11 13 2 4 6 8 10 12 14 TDO/TDI TDI/VPP TMS TCK GND TEST/VPP JTAG VCC TOOL VCC TARGET J1 (see Note A) J2 (see Note A) VCC R1 47 k (see Note B) W C2 10 μF C3 0.1 μF VCC/AVCC/DVCC RST/NMI TDO/TDI TDI/VPP TMS TCK TEST/VPP (see Note C) V /AV /DV SS SS SS MSP430Fxxx C1 10 nF/2.2 nF (see Notes B and E) RST (see Note D) Important to connect www.ti.com Signal Connections for In-System Programming and Debugging A If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used, make connection J2. B The configuration of R1 and C1 for the RST/NMI pin depends on the device family. See the respective MSP430 family user's guide for the recommended configuration. C The TEST pin is available only on MSP430 family members with multiplexed JTAG pins. See the device-specific data sheet to determine if this pin is available. D The connection to the JTAG connector RST pin is optional when using a device that supports only 4-wire JTAG communication mode, and it is not required for device programming or debugging. However, this connection is required when using a device that supports 2-wire JTAG communication mode in 4-wire JTAG mode. E When using a device that supports 2-wire JTAG communication in 4-wire JTAG mode, the upper limit for C1 should not exceed 2.2 nF. This applies to both TI FET interface modules (LPT and USB FET). Figure 2-1. Signal Connections for 4-Wire JTAG Communication SLAU278R–May 2009–Revised May 2014 Design Considerations for In-Circuit Programming 23 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated 1 3 5 7 9 11 13 2 4 6 8 10 12 14 TEST/SBWTCK MSP430Fxxx RST/NMI/SBWTDIO TDO/TDI TCK GND TEST/VPP JTAG VCC TOOL VCC TARGET 330! R2 J1 (see Note A) J2 (see Note A) Important to connect VCC/AVCC/DVCC V /AV /DV SS SS SS R1 47 k! See Note B C1 2.2 nF See Note B VCC C2 10 μF C3 0.1 μF Signal Connections for In-System Programming and Debugging www.ti.com A If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used, make connection J2. B The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with the device. The upper limit for C1 is 2.2 nF when using current TI tools. C R2 protects the JTAG debug interface TCK signal from the JTAG security fuse blow voltage that is supplied by the TEST/VPP pin during the fuse blow process. If fuse blow functionality is not needed, R2 is not required (populate 0 Ω) and do not connect TEST/VPP to TEST/SBWTCK. Figure 2-2. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire) Used by MSP430F2xx, MSP430G2xx, and MSP430F4xx Devices 24 Design Considerations for In-Circuit Programming SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated 1 3 5 7 9 11 13 2 4 6 8 10 12 14 TEST/SBWTCK MSP430Fxxx RST/NMI/SBWTDIO TDO/TDI TCK GND JTAG R1 47 k! See Note B VCC TOOL VCC TARGET C1 2.2 nF See Note B J1 (see Note A) J2 (see Note A) Important to connect VCC/AVCC/DVCC V /AV /DV SS SS SS VCC C2 10 μF C3 0.1 μF www.ti.com Signal Connections for In-System Programming and Debugging A Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the debug or programming adapter. B The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with the device. The upper limit for C1 is 2.2 nF when using current TI tools. Figure 2-3. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire) Used by MSP430F5xx and MSP430F6xx Devices SLAU278R–May 2009–Revised May 2014 Design Considerations for In-Circuit Programming 25 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated External Power www.ti.com 2.2 External Power The MSP-FET430UIF can supply targets with up to 60 mA through pin 2 of the 14-pin connector. Note that the target should not consume more than 60 mA, even as a peak current, as it may violate the USB specification. For example, if the target board has a capacitor on VCC more than 10 μF, it may cause inrush current during capacitor charging that may exceed 60 mA. In this case, the current should be limited by the design of the target board, or an external power supply should be used. The VCC for the target can be selected between 1.8 V and 3.6 V in steps of 0.1 V. Alternatively, the target can be supplied externally. In this case, the external voltage should be connected to pin 4 of the 14-pin connector. The MSP-FET430UIF then adjusts the level of the JTAG signals to external VCC automatically. Only pin 2 (MSP-FET430UIF supplies target) or pin 4 (target is externally supplied) must be connected; not both at the same time. When a target socket module is powered from an external supply, the external supply powers the device on the target socket module and any user circuitry connected to the target socket module, and the FET interface module continues to be powered from the PC through the parallel port. If the externally supplied voltage differs from that of the FET interface module, the target socket module must be modified so that the externally supplied voltage is routed to the FET interface module (so that it may adjust its output voltage levels accordingly). See the target socket module schematics in Appendix B. The PC parallel port can source a limited amount of current. Because of the ultra-low-power requirement of the MSP430, a standalone FET does not exceed the available current. However, if additional circuitry is added to the tool, this current limit could be exceeded. In this case, external power can be supplied to the tool through connections provided on the target socket modules. See the schematics and pictorials of the target socket modules in Appendix B to locate the external power connectors. Note that the MSPFET430PIF is not recommended for new design. 2.3 Bootstrap Loader (BSL) The JTAG pins provide access to the memory of the MSP430 and CC430 devices. On some devices, these pins are shared with the device port pins, and this sharing of pins can complicate a design (or sharing may not be possible). As an alternative to using the JTAG pins, most MSP430Fxxx devices contain a program (a "bootstrap loader") that permits the flash memory to be erased and programmed using a reduced set of signals. The MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319) describes this interface. See the MSP430 web site for the application reports and a list of MSP430 BSL tool developers. TI suggests that MSP430Fxxx customers design their circuits with the BSL in mind (that is, TI suggests providing access to these signals by, for example, a header). See FAQ Hardware #10 for a second alternative to sharing the JTAG and port pins. 26 Design Considerations for In-Circuit Programming SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Appendix A SLAU278R–May 2009–Revised May 2014 Frequently Asked Questions and Known Issues This appendix presents solutions to frequently asked questions regarding the MSP-FET430 hardware. Topic ........................................................................................................................... Page A.1 Hardware FAQs.................................................................................................. 28 A.2 Known Issues .................................................................................................... 30 SLAU278R–May 2009–Revised May 2014 Frequently Asked Questions and Known Issues 27 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Hardware FAQs www.ti.com A.1 Hardware FAQs 1. MSP430F22xx Target Socket Module (MSP-TS430DA38) – Important Information Due to the large capacitive coupling introduced by the device socket between the adjacent signals XIN/P2.6 (socket pin 6) and RST/SBWTDIO (socket pin 7), in-system debugging can disturb the LFXT1 low-frequency crystal oscillator operation (ACLK). This behavior applies only to the Spy-Bi-Wire (2-wire) JTAG configuration and only to the period while a debug session is active. Workarounds: • Use the 4-wire JTAG mode debug configuration instead of the Spy-Bi-Wire (2-wire) JTAG configuration. This can be achieved by placing jumpers JP4 through JP9 accordingly. • Use the debugger option "Run Free" that can be selected from the Advanced Run drop-down menu (at top of Debug View). This prevents the debugger from accessing the MSP430 device while the application is running. Note that, in this mode, a manual halt is required to see if a breakpoint was hit. See the IDE documentation for more information on this feature. • Use an external clock source to drive XIN directly. 2. With current interface hardware and software, there is a weakness when adapting target boards that are powered externally. This leads to an accidental fuse check in the MSP430 device. This is valid for PIF and UIF but is seen most often on the UIF. A solution is being developed. Workarounds: • Connect the RST/NMI pin to the JTAG header (pin 11). LPT and USB tools are able to pull the RST line, which also resets the device internal fuse logic. • Use the debugger option "Release JTAG On Go" that can be selected from the IDE drop-down menu. This prevents the debugger from accessing the MCU while the application is running. Note that in this mode, a manual halt is required to see if a breakpoint was hit. See the IDE documentation for more information on this feature. • Use an external clock source to drive XIN directly. 3. The 14-conductor cable that connects the FET interface module and the target socket module must not exceed 8 inches (20 centimeters) in length. 4. The signal assignment on the 14-conductor cable is identical for the parallel port interface and the USB FET. 5. To use the on-chip ADC voltage references, the capacitor must be installed on the target socket module. See the schematic of the target socket module to populate the capacitor according to the data sheet of the device. 6. To use the charge pump on the devices with LCD+ Module, the capacitor must be installed on the target socket module. See the schematic of the target socket module to populate the capacitor according to the data sheet of the device. 7. Crystals or resonators Q1 and Q2 (if applicable) are not provided on the target socket module. For MSP430 devices that contain user-selectable loading capacitors, see the device and crystal data sheets for the value of capacitance. 8. Crystals or resonators have no effect upon the operation of the tool and the CCS debugger or C-SPY (as any required clocking and timing is derived from the internal DCO and FLL). 9. On devices with multiplexed port or JTAG pins, to use these pin in their port capability: For CCS: "Run Free" (in Run pulldown menu at top of Debug View) must be selected. For C-SPY: "Release JTAG On Go" must be selected. 10. As an alternative to sharing the JTAG and port pins (on low pin count devices), consider using an MSP430 device that is a "superset" of the smaller device. A very powerful feature of the MSP430 is that the family members are code and architecturally compatible, so code developed on one device (for example, one without shared JTAG and port pins) ports effortlessly to another (assuming an equivalent set of peripherals). 28 Frequently Asked Questions and Known Issues SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com Hardware FAQs 11. Information memory may not be blank (erased to 0xFF) when the device is delivered from TI. Customers should erase the information memory before its first use. Main memory of packaged devices is blank when the device is delivered from TI. 12. The device current is higher then expected. The device current measurement may not be accurate with the debugger connected to the device. For accurate measurement, disconnect the debugger. Additionally some unused pins of the device should be terminated. See the Connection of Unused Pins table in the device's family user's guide. 13. The following ZIF sockets are used in the FET tools and target socket modules: • 8-pin device (D package): Yamaichi IC369-0082 • 14-pin device (PW package): Enplas OTS-14-065-01 • 14-pin package for 'L092 (PW package): Yamaichi IC189-0142-146 • 24-pin package (PW package): Enplas OTS-24(28)-0.65-02 • 28-pin device (DW package): Wells-CTI 652 D028 • 28-pin device (PW package): Enplas OTS-28-0.65-01 • 38-pin device (DA package): Yamaichi IC189-0382-037 • 40-pin device (RHA package): Enplas QFN-40B-0.5-01 • 40-pin device (RSB package): Enplas QFN-40B-0.4 • 48-pin device (RGZ package): Yamaichi QFN11T048-008 A101121-001 • 48-pin device (DL package): Yamaichi IC51-0482-1163 • 64-pin device (PM package): Yamaichi IC51-0644-807 • 64-pin device (RGC package): Yamaichi QFN11T064-006 • 80-pin device (PN package): Yamaichi IC201-0804-014 • 100-pin device (PZ package): Yamaichi IC201-1004-008 • 128-pin device (PEU package): Yamaichi IC500-1284-009P Enplas: www.enplas.com Wells-CTI: www.wellscti.com Yamaichi: www.yamaichi.us SLAU278R–May 2009–Revised May 2014 Frequently Asked Questions and Known Issues 29 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Known Issues www.ti.com A.2 Known Issues MSP-FET430UIF Current detection algorithm of the UIF firmware Problem Description If high current is detected, the ICC monitor algorithm stays in a loop of frequently switching on and off the target power supply. This power switching puts some MSP430 devices such as the MSP430F5438 in a state that requires a power cycle to return the device to JTAG control. A side issue is that if the UIF firmware has entered this switch on and switch off loop, it is not possible to turn off the power supply to the target by calling MSP430_VCC(0). A power cycle is required to remove the device from this state. Solution IAR KickStart and Code Composer Essentials that have the MSP430.dll version 2.04.00.003 and higher do not show this problem. Update the software development tool to this version or higher to update the MSP-FET430UIF firmware. MSP-FET430PIF Some PCs do not supply 5 V through the parallel port Problem Description Device identification problems with modern PCs, because the parallel port often does not deliver 5 V as was common with earlier hardware. 1. When connected to a laptop, the test signal is clamped to 2.5 V. 2. When the external VCC becomes less than 3 V, up to 10 mA is flowing in the adapter through pin 4 (sense). Solution Measure the voltage level of the parallel port. If it is too low, provide external 5 V to the VCC pads of the interface. The jumper on a the target socket must be switched to external power. 30 Frequently Asked Questions and Known Issues SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Appendix B SLAU278R–May 2009–Revised May 2014 Hardware This appendix contains information relating to the FET hardware, including schematics, PCB pictorials, and bills of materials (BOMs). All other tools, such as the eZ430 series, are described in separate productspecific user's guides. SLAU278R–May 2009–Revised May 2014 Hardware 31 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Appendix B www.ti.com Topic ........................................................................................................................... Page B.1 MSP-TS430D8 .................................................................................................... 33 B.2 MSP-TS430PW14................................................................................................ 36 B.3 MSP-TS430L092 ................................................................................................. 39 B.4 MSP-TS430L092 Active Cable .............................................................................. 42 B.5 MSP-TS430PW24................................................................................................ 45 B.6 MSP-TS430DW28................................................................................................ 48 B.7 MSP-TS430PW28................................................................................................ 51 B.8 MSP-TS430PW28A.............................................................................................. 54 B.9 MSP-TS430RHB32A............................................................................................ 57 B.10 MSP-TS430DA38 ................................................................................................ 60 B.11 MSP-TS430QFN23x0........................................................................................... 63 B.12 MSP-TS430RSB40 .............................................................................................. 66 B.13 MSP-TS430RHA40A............................................................................................ 69 B.14 MSP-TS430DL48 ................................................................................................ 72 B.15 MSP-TS430RGZ48B ............................................................................................ 75 B.16 MSP-TS430RGZ48C ............................................................................................ 78 B.17 MSP-TS430PM64 ................................................................................................ 81 B.18 MSP-TS430PM64A.............................................................................................. 84 B.19 MSP-TS430RGC64B............................................................................................ 87 B.20 MSP-TS430RGC64C............................................................................................ 90 B.21 MSP-TS430RGC64USB ....................................................................................... 94 B.22 MSP-TS430PN80 ................................................................................................ 98 B.23 MSP-TS430PN80A ............................................................................................ 101 B.24 MSP-TS430PN80USB ........................................................................................ 104 B.25 MSP-TS430PZ100 ............................................................................................. 108 B.26 MSP-TS430PZ100A ........................................................................................... 111 B.27 MSP-TS430PZ100B ........................................................................................... 114 B.28 MSP-TS430PZ100C ........................................................................................... 117 B.29 MSP-TS430PZ100D ........................................................................................... 121 B.30 MSP-TS430PZ5x100 .......................................................................................... 124 B.31 MSP-TS430PZ100USB ....................................................................................... 127 B.32 MSP-TS430PEU128 ........................................................................................... 131 B.33 EM430F5137RF900 ........................................................................................... 134 B.34 EM430F6137RF900 ........................................................................................... 138 B.35 EM430F6147RF900 ........................................................................................... 142 B.36 MSP-FET ......................................................................................................... 146 B.37 MSP-FET430PIF................................................................................................ 157 B.38 MSP-FET430UIF ............................................................................................... 159 32 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated GND 100nF 330R 10uF/10V 47K 2.2nF GND 330R GND GND green FE4L FE4H GND Ext_PWR Socket: YAMAICHI Type: IC369-0082 Vcc ext int to measure supply current DNP 1 3 5 7 9 11 13 2 4 6 12 14 8 10 SBW C5 R3 C7 R5 C8 1 2 3 J3 1 2 J4 1 2 J6 1 2 3 J5 R2 D1 1 2 3 4 J1 5 6 7 8 J2 DVCC 1 DVSS 8 P1.2/TA1/A2 2 P1.5/TA0/A5/SCLK 3 P1.6/TA1/A6/SDO/SCL 4 TST/SBWTCK 7 RST/SBWTDIO 6 P1.7/A7/SDI/SDA 5 U1 MSP-TS430D8 GND VCC RST/SBWTDIO RST/SBWTDIO RST/SBWTDIO SBWTCK VCC430 TST/SBWTCK TST/SBWTCK TST/SBWTCK P1.5 P1.6 P1.7 P1.2 Date: 28.07.201111:03:35 Sheet: /11 REV: TITLE: Document Number: MSP-TS430D8 + 1.0 MSP-TS430D8 Target Socket Board www.ti.com MSP-TS430D8 B.1 MSP-TS430D8 Figure B-1. MSP-TS430D8 Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 33 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumper J4 Open to disconnect LED D1 LED connected to P1.2 Orient Pin 1 of MSP430 device 14-pin connector for debugging in Spy-Bi-Wire mode only (4-Wire JTAG not available) Jumper J6 Open to measure current Jumper J5 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Connector J3 External power connector Jumper J5 to “ext” MSP-TS430D8 www.ti.com Figure B-2. MSP-TS430D8 Target Socket Module, PCB 34 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430D8 Table B-1. MSP-TS430D8 Bill of Materials Position Ref Des No. per Description Digi-Key Part No. Comment Board 1 J4, J6 2 2-pin header, male, TH SAM1035-02-ND place jumper on header 2 J5 1 3-pin header, male, TH SAM1035-03-ND place jumper on pins 1-2 3 SBW 1 10-pin connector, male, TH HRP10H-ND 4 J3 1 3-pin header, male, TH SAM1035-03-ND 5 C8 1 2.2nF, CSMD0805 Buerklin 53 D 292 6 C7 1 10uF, 10V, 1210ELKO 478-3875-1-ND 7 R5 1 47K, 0805 541-47000ATR-ND 8 C5 1 100nF, CSMD0805 311-1245-2-ND 9 R2, R3 2 330R, 0805 541-330ATR-ND 10 J1, J2 2 4-pin header, TH SAM1029-04-ND DNP: headers enclosed with kit. Keep vias free of solder. 10,1 J1, J2 1 4-pin socket, TH SAM1029-04-ND DNP: receptacles enclosed with kit. 11 U1 1 SO8 Socket: Type IC369-0082 Manuf.: Yamaichi 12 D1 1 red, LED 0603 13 MSP430 2 MSP430G2210, MSP430G2230 DNP: enclosed with kit. Is supplied by TI 14 PCB 1 50,0mmx44,5mm MSP-TS430D8 Rev. 1.0 SLAU278R–May 2009–Revised May 2014 Hardware 35 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated 12pF 12pF GND 100nF 330R 10uF/10V 47K 2.2nF GND 330R 100nF GND GND GND green Ext_PWR Socket: ENPLAS Type: OTS-14-065 Vcc ext int to measure supply current DNP DNP DNP DNP DNP JTAG -> SBW -> JTAG-Mode selection: 4-wire JTAG: Set jumpers J7 to J12 to position 2-3 2-wire "SpyBiWire": Set jumpers J7 to J12 to position 2-1 1 3 5 7 9 11 13 2 4 6 12 14 8 10 JTAG C2 C1 C5 R3 C7 R5 C8 1 2 3 J3 Q1 8 9 10 11 12 13 14 J2 1 2 3 4 5 6 7 J1 1 2 J4 1 2 J6 J5 1 2 3 R2 C3 J7 1 2 3 J8 1 2 3 J9 1 2 3 J10 1 2 3 J11 1 2 3 J12 1 2 3 1 2 3 4 5 6 7 8 9 10 14 13 12 11 D1 P1.0 P1.3 P1.2 P1.1 XOUT XOUT GND XIN XIN VCC RST/SBWTDIO RST/SBWTDIO SBWTCK TEST/SBWTCK TEST/SBWTCK TEST/SBWTCK VCC430 P1.4/TCK P1.4/TCK P1.5/TMS P1.5/TMS P1.6/TDI P1.6/TDI P1.7/TDO P1.7/TDO TDO/SBWTDIO RST/NMI TMS TDI Date: 7/16/2007 8:22:36 AM Sheet: 1/1 REV: TITLE: Document Number: MSP-TS430PW14 + 2.0 MSP-TS430PW14 Target Socket Board MSP-TS430PW14 www.ti.com B.2 MSP-TS430PW14 Figure B-3. MSP-TS430PW14 Target Socket Module, Schematic 36 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumper J4 Open to disconnect LED Orient Pin 1 of MSP430 device Jumper J6 Open to measure current Connector J3 External power connector D1 Jumper J5 to "ext" LED connected to P1.0 Jumpers J7 to J12 Close 1-2 to debug in Spy-Bi-Wire mode. Close 2-3 to debug in 4-wire JTAG mode. Jumper J5 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Connector JTAG For JTAG Tool www.ti.com MSP-TS430PW14 Figure B-4. MSP-TS430PW14 Target Socket Module, PCB SLAU278R–May 2009–Revised May 2014 Hardware 37 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430PW14 www.ti.com Table B-2. MSP-TS430PW14 Bill of Materials Position Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP 2 C7 1 10uF, 10V, Tantal Size 511-1463-2-ND B 3 C3, C5 1 100nF, SMD0805 478-3351-2-ND DNP: C3 4 C8 0 2.2nF, SMD0805 DNP 5 D1 1 green LED, SMD0603 475-1056-2-ND DNP: Headers and receptacles enclosed with kit. Keep vias free of 6 J1, J2 0 7-pin header, TH solder SAM1029-07-ND : Header SAM1213-07-ND : Receptacle J3, J5, J7, Place jumpers on headers J5, J7, J8, 7 J8, J9, J10, 8 3-pin header, male, TH SAM1035-03-ND J9, J10, J11, J12; Pos 1-2 J11, J12 8 J4, J6 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header 9 9 Jumper 15-38-1024-ND Place on: J5, J7-J12; Pos 1-2 10 JTAG 1 14-pin connector, male, HRP14H-ND TH Micro Crystal MS1V-T1K 12 Q1 0 Crystal 32.768kHz, C(Load) = DNP: keep vias free of solder 12.5pF 13 R2, R3 2 330 Ω, SMD0805 541-330ATR-ND 15 R5 1 47k Ω, SMD0805 541-47000ATR-ND 16 U1 1 Socket: OTS-14-0.65-01 Manuf.: Enplas 17 PCB 1 56 x 53 mm 2 layers Adhesive Approximately 6mm For example, 3M 18 plastic feet 4 width, 2mm height Bumpons Part No. SJ- Apply to corners at bottom side 5302 19 MSP430 2 MSP430F2013IPW DNP: enclosed with kit, supplied by TI 38 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430L092 B.3 MSP-TS430L092 Figure B-5. MSP-TS430L092 Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 39 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Connector J3 External power connector Jumper JP3 Open to measure current Jumper JP1 Write enable for EPROM Orient pin 1 of MSP430 device MSP-TS430L092 www.ti.com Settings of the MSP-TS430L092 Target Socket Figure B-6 shows the PCB layout of the MSP-TS430L092 target socket. The following pinning is recommended: • JP1 is write enable for the EPROM. If this is not set, the EPROM can only be read. • JP2 and JP3 connect device supply with boost converter. They can be opened to measure device current consumption. For default operation, they should be closed. Figure B-6. MSP-TS430L092 Target Socket Module, PCB 40 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430L092 Table B-3. MSP-TS430L092 Bill of Materials Pos. Ref Des No. No. Per Description Digi-Key Part No. Comment Board 1 C1, C2 2 330nF, SMD0603 2 C5 1 100n, SMD0603 3 C6 1 10u, SMD0805 4 C10 1 100n, SMD0603 5 EEPROM1 1 M95512 SO08 (SO8) ST Micro M95160R Digikey: 497-8688-1-ND DNP: headers and receptacles enclosed with kit. 7 J1, J2 2 7-pin header, TH Keep vias free of solder. SAM1213-07-ND : Header SAM1035-07-ND : Receptacle 8 J3 1 3-pin header, male, TH SAM1035-03-ND 9 J4, J5 2 FE4L, FE4H 4 pol. Stiftreihe DNP; Keep vias free of solder. 11 J13 1 MICRO_STECKV_10 Reichelt: MicroMaTch- Connector: MM FL 10G 12 JP1, JP2,JP3 3 2-pin header, male, TH SAM1035-02-ND place jumper on header 15 L1 1 33uH, SMD0806 LQH2MCN330K02L Farnell: 151-5557 16 LED1, LED4 2 LEDCHIPLED_0603 Farnell: 1686065 17 Q2 1 BC817-16LT1SMD BC817-16LT1SMD SOT23-BEC 18 R0, R6, R7 3 2K7, SMD0603 19 R1 1 1k, SMD0603 20 R2 1 47k, SMD0603 21 R4,R5, R8, 6 10k, SMD0603 R10, RC, RD 22 RA 1 3.9k, SMD0603 23 RB 1 6.8k, SMD0603 24 U1 1 14 Pin Socket - IC189-0142- Manuf. Yamaichi 146 22 MSP430 2 MSP430L092PWR DNP: Enclosed with kit. Is supplied by TI. SLAU278R–May 2009–Revised May 2014 Hardware 41 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430L092 Active Cable www.ti.com B.4 MSP-TS430L092 Active Cable Figure B-7. MSP-TS430L092 Active Cable Target Socket Module, Schematic 42 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Connector JTAG For JTAG Tool JP2 JP1 www.ti.com MSP-TS430L092 Active Cable Figure B-8 shows the PCB layout for the Active Cable. The following pinning is possible: • JP1 has two jumpers (Jumper 1 and Jumper 2) that can be set as shown in Table B-4. Table B-4. MSP-TS430L092 JP1 Settings Jumper 1 Jumper 2 Description Off Off The active cable has no power and does not function. Off On The active cable receives power from target socket. For this option, the target socket must have its own power supply. On Off The active cable receives power from the JTAG connector. The JTAG connector powers the active cable and the target socket. For On On this option, the target socket must not have its own power source, as this would cause a not defined state. • JP2 is for reset. For the standard MSP-TS430L092, this jumper must be set. It sets the reset pin to high and can also control it. Without this jumper on the MSP-TS430L092, reset is set to zero. Figure B-8. MSP-TS430L092 Active Cable Target Socket Module, PCB SLAU278R–May 2009–Revised May 2014 Hardware 43 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430L092 Active Cable www.ti.com Table B-5. MSP-TS430L092 Active Cable Bill of Materials Pos. Ref Des No. Per Description Digi-Key Part No. Comment Board 1 C1, C3, C5, 4 100nF, SMD0603 C6 2 C2, C4 2 1uF, SMD0805 3 R1, R10 2 10K, SMD0603 4 R2 1 4K7, SMD0603 5 R5, R6, R7, 4 100, SMD0603 R9 6 R8 1 680k, SMD0603 7 R11, R15 2 1K, SMD0603 8 R12 0 SMD0603 DNP 9 R13 0 SMD0603 DNP 10 R14 1 0, SMD0603 11 IC1 1 SN74AUC1G04DBVR Manu: TI 12 IC2, IC3, IC4 3 SN74AUC2G125DCTR Manu: TI 13 J2 1 MICRO_STECKV_10 Reichelt: MicroMaTch- Connector: MM FL 10G 14 JP1 1 2x2 Header JP2Q Put jumper on Position 1 and 2. Do not mix direction. 15 JP2 1 2-pin header, male, TH SAM1035-02-ND place jumper on header 16 JTAG 1 14-pin connector, male, TH HRP14H-ND 17 Q1 1 BC817-25LT1SMD, SOT23- Digi-Key: BC817- BEC 25LT1GOSCT-ND 18 U1, U2 2 TLVH431IDBVR SOT23-5 Manu: TI 44 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430PW24 B.5 MSP-TS430PW24 Figure B-9. MSP-TS430PW24 Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 45 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumper JP2 Open to measure current Orient Pin 1 of MSP430 device D1 LED connected to P1.0 Jumper JP3 Open to disconnect LED Connector J5 External power connector Jumper JP1 to "ext" Jumpers JP4 to JP9 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode Jumper JP1 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Connector JTAG For JTAG Tool MSP-TS430PW24 www.ti.com Figure B-10. MSP-TS430PW24 Target Socket Module, PCB 46 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430PW24 Table B-6. MSP-TS430PW24 Bill of Materials Position Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP 2 C5 1 2.2nF, SMD0805 3 C3, C7 2 10uF, 10V, SMD0805 4 C4, C6, C8 3 100nF, SMD0805 478-3351-2-ND 5 D1 1 green LED, SMD0805 P516TR-ND SAM1029-07- DNP: Headers and receptacles 6 J1, J2 0 12-pin header, TH NDSAM1213-07-ND enclosed with kit. Keep vias free of solder. (Header and Receptacle) J5, JP1, 7 JP4, JP5, 8 3-pin header, male, TH SAM1035-03-ND Place jumper on 1-2 of JP4-JP9 JP6, JP7, Place on 1-2 on JP1 JP8, JP9 8 JP2, JP3 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header 9 9 Jumper 15-38-1024-ND see Pos 7 an 8 10 JTAG 1 14-pin connector, male, HRP14H-ND TH 11 Q1 0 Crystal DNP: keep vias free of solder 12 R1, R7 2 330 Ω, SMD0805 541-330ATR-ND 13 R5, R6, 2 0 Ohm, SMD0805 541-000ATR-ND DNP R5, R6 R8, R9, 14 R4 1 47k Ohm, SMD0805 541-47000ATR-ND 15 U1 1 Socket: OTS 24(28)- Manuf.: Enplas 065-02-00 16 PCB 1 68.5 x 61 mm 2 layers Adhesive Approximately 6mm for example, 3M 17 plastic feet 4 width, 2mm height Bumpons Part No. SJ- Apply to corners at bottom side 5302 18 MSP430 2 MSP430AFE2xx DNP: enclosed with kit, supplied by TI SLAU278R–May 2009–Revised May 2014 Hardware 47 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated ML14 LED3 12pF 12pF GND GND 100nF 560R ML10 JP1Q JP1Q 10uF/10V 50K 10nF 0R 0R 0R - - 0R - U1 SOCK28DW F123 FE14H FE14L 0R GND remove R8 and add R9 (0 Ohm) If external supply voltage: remove R11 and add R10 (0 Ohm) SMD-Footprint Socket: Yamaichi 2.0 MSP-TS430DW28 Target Socket DW28 Type: IC189-0282-042 If external supply voltage: R1, C1, C2 not assembled not assembled 1 3 5 7 9 11 13 2 4 6 12 14 8 10 JTAG D1 C2 C1 C5 R3 BOOTST 1 2 3 4 5 6 7 8 9 10 1 2 J5 J4 1 2 C7 R5 C8 R6 R7 R8 R9 R10 R11 R1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 TST 1 VCC 2 P2.5 3 VSS 4 XOUT 5 XIN 6 RST 7 P2.0 8 P2.1 9 P2.2 10 P2.3 19 P2.4 20 P1.0 21 P1.1 22 P1.2 23 P1.3 24 P1.4 25 P1.5 26 P1.6 27 P1.7 28 P3.0 11 P3.1 12 P3.2 13 P3.3 14 P3.4 15 P3.5 16 P3.6 17 P3.7 18 U2 15 16 17 18 19 20 21 22 23 24 25 26 27 28 J2 J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 R2 1 2 3 J3 Q1 QUARZ3 P1.0 P1.0 P1.3 P1.3 P1.2 P1.2 P1.1 P1.1 RST/NMI RST/NMI RST/NMI RST/NMI RST/NMI TCK TCK TCK TMS TMS TMS TDI TDI TDI TDO TDO TDO XOUT XOUT VCC GND GND GND P2.3 P2.3 P2.4 P2.4 XIN XIN P2.5 P2.5 P2.2 P2.2 P2.1 P2.1 P2.0 P2.0 TST/VPP TST/VPP TST/VPP P3.0 P3.0 P3.1 P3.1 P3.2 P3.2 P3.3 P3.3 P3.7 P3.7 P3.6 P3.6 P3.5 P3.5 P3.4 P3.4 VCC430 Ext_PWR Date: 11/14/2006 1:26:04 PM Sheet: 1/1 REV: TITLE: Document Number: MSP-TS430DW28 + VCC430 MSP-TS430DW28 www.ti.com B.6 MSP-TS430DW28 Figure B-11. MSP-TS430DW28 Target Socket Module, Schematic 48 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumper J4 Open to disconnect LED Orient Pin 1 of MSP430 device Jumper J5 Open to measure current Connector J3 External power connector Remove R8 and jumper R9 D1 LED connected to P1.0 Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool www.ti.com MSP-TS430DW28 Figure B-12. MSP-TS430DW28 Target Socket Module, PCB SLAU278R–May 2009–Revised May 2014 Hardware 49 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430DW28 www.ti.com Table B-7. MSP-TS430DW28 Bill of Materials Position Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP: C1, C2, Cover holes while soldering 2 C5 1 100nF, SMD0805 3 C7 1 10uF, 10V Tantal Elko B 4 C8 1 10nF SMD0805 5 D1 1 LED3 T1 3mm yellow RS: 228-4991 Micro Crystal MS1V-T1K 6 Q1 0 QUARZ, Crystal 32.768kHz, C(Load) = DNP: Cover holes while soldering 12.5pF DNP: Headers and receptacles enclosed with kit. Keep vias free of 7 J1, J2 2 14-pin header, TH male solder. : Header : Receptacle DNP: Headers and receptacles enclosed with kit. Keep vias free of 7.1 2 14-pin header, TH solder. female : Header : Receptacle 8 J3 1 3-Pin Connector, male 9 J4, J5 2 2-Pin Connector, male With jumper 10 BOOTST 0 ML10, 10-Pin Conn., m RS: 482-115 DNP, Cover holes while soldering 11 JTAG 1 ML14, 14-Pin Conn., m RS: 482-121 R1, R2, 12 R6, R7, 4 0R, SMD0805 DNP: R1, R2, R9, R10 R8,R9, R10, R11 13 R3 1 560R, SMD0805 14 R5 1 47K, SMD0805 15 U1 1 SOP28DW socket Yamaichi: IC189-0282- 042 16 U2 0 TSSOP DNP 50 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated 12pF 12pF GND GND 100nF 330R 10uF/10V - 0R GND GND green 2.2nF 47k GND 0R 0R 330R MSP430F12xx If external supply voltage: remove R11 and add R10 (0 Ohm) 3.1 MSP-TS430PW28: OTS-28-0.65-01 Socket: Enplas Vcc int ext Target Socket Board for MSP430's in PW28 package DNP DNP DNP DNP DNP DNP DNP JTAG -> SBW -> JTAG-Mode selection: 4-wire JTAG: Set jumpers JP4 to JP9 to position 2-3 2-wire "SpyBiWire": Set jumpers JP4 to JP9 to position 1-2 DNP 1 3 5 7 9 11 13 2 4 6 12 14 8 10 JTAG C2 C1 C4 R1 1 2 3 4 5 6 7 8 9 10 BOOTST C3 R2 R3 1 2 3 J5 JP1 1 2 3 JP2 1 2 1 2 JP3 D1 C5 R4 JP4 1 2 3 JP5 1 2 3 JP6 1 2 3 JP7 1 2 3 JP8 1 2 3 JP9 1 2 3 R5 R6 1 2 Q1 R7 J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 J2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 U1 TST 1 VCC 2 P2.5 3 VSS 4 XOUT 5 XIN 6 RST 7 P2.0 8 P2.1 9 P2.2 10 P2.3 19 P2.4 20 P1.0 21 P1.1 22 P1.2 23 P1.3 24 P1.4 25 P1.5 26 P1.6 27 P1.7 28 P3.0 11 P3.1 12 P3.2 13 P3.3 14 P3.4 15 P3.5 16 P3.6 17 P3.7 18 P1.0 P1.0 RST/NMI TMS TDI VCC GND GND VCC430 VCC430 P2.0 P1.1 P1.1 P3.3 P3.2 P3.1 P3.0 P2.2 P2.2 XIN/P2.6 XIN/P2.6 XOUT/P2.7 XOUT/P2.7 P2.1 RST/SBWTDIO RST/SBWTDIO RST/SBWTDIO P3.4 P3.5 P3.6 P3.7 P2.3 P2.4 P1.2 P1.3 P1.4/TCK P1.4/TCK P1.5/TMS P1.5/TMS P1.6/TDI P1.6/TDI P1.7/TDO P1.7/TDO TEST/SBWTCK TEST/SBWTCK TEST/SBWTCK TEST/SBWTCK P2.5 TCK/SBWTCK TDO/SBWTDIO XTLGND Ext_PWR + www.ti.com MSP-TS430PW28 B.7 MSP-TS430PW28 Figure B-13. MSP-TS430PW28 Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 51 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumper JP2 Open to measure current Jumper JP3 Open to disconnect LED D1 LED connected to P5.1 Jumper JP1 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Jumper JP4 to JP9: Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode Orient Pin 1 of MSP430 device Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool Connector J5 External power connector Jumper JP1 to “ext” MSP-TS430PW28 www.ti.com Figure B-14. MSP-TS430PW28 Target Socket Module, PCB 52 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430PW28 Table B-8. MSP-TS430PW28 Bill of Materials(1) Pos. Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP: C1, C2 , Cover holes while soldering 2 C3 1 10uF, 10V Tantal Elko B 3 C4 1 100nF, SMD0805 4 C5 0 2.2nF, SMD0805 DNP 5 D1 1 LED green SMD0603 Micro Crystal MS1V-T1K DNP: Cover holes and 6 Q1 0 QUARZ, Crystal 32.768kHz, C(Load) = neighboring holes while 12.5pF soldering DNP: Headers and receptacles enclosed with 7 J1, J2 2 14-pin header, TH male kit.Keep vias free of solder. : Header : Receptacle DNP: headers and receptacles enclosed with 7.1 2 14-pin header, TH female kit.Keep vias free of solder. : Header : Receptacle 8 J5, IP1 1 3-Pin Connector , male JP1, JP4, 8a JP5, JP6, 7 3-Pin Connector , male Jumper on Pos 1-2 JP7, JP8, JP9 9 JP2, JP3 2 2-Pin Connector , male with Jumper 10 BOOTST 0 ML10, 10-Pin Conn. , m RS: 482-115 DNP: Cover holes while soldering 11 JTAG 1 ML14, 14-Pin Conn. , m RS: 482-121 12 R1, R7 2 330R, SMD0805 12 R2, R3, R5, 0 0R, SMD0805 DNP R6 14 R4 1 47K, SMD0805 15 U1 1 SOP28PW socket Enplas: OTS-28-0.65-01 (1) PCB 66 x 79 mm, two layers; Rubber stand off, four pieces SLAU278R–May 2009–Revised May 2014 Hardware 53 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated JTAG Mode selection: 4-wire JTAG: Set jumpers J4 to J9 to position 2-3 2-wire "SpyBiWire": Set jumpers J4 to J9 to position 2-1 MSP-TS430PW28A www.ti.com B.8 MSP-TS430PW28A Figure B-15. MSP-TS430PW28A Target Socket Module, Schematic 54 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumper JP2 Open to measure current Orient Pin 1 of MSP430 device Jumper JP3 Open to disconnect LED D1 LED connected to P1.0 Connector J5 External power connector Jumper JP1 to "ext" Jumpers JP4 to JP9 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool Jumper JP1 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply www.ti.com MSP-TS430PW28A Figure B-16. MSP-TS430PW28A Target Socket Module, PCB (Red) SLAU278R–May 2009–Revised May 2014 Hardware 55 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430PW28A www.ti.com Table B-9. MSP-TS430PW28A Bill of Materials Position Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP 2 C5 1 2.2nF, SMD0805 3 C3 1 10uF, 10V, SMD0805 4 C4, C6, 2 100nF, SMD0805 478-3351-2-ND 5 D1 1 green LED, SMD0805 P516TR-ND DNP: Headers and receptacles 6 J1, J2 0 14-pin header, TH enclosed with kit. Keep vias free of solder: (Header and Receptacle) J5, JP1, 7 JP4, JP5, 8 3-pin header, male, TH SAM1035-03-ND Place jumper on 1-2 of JP4-JP9 JP6, JP7, Place on 1-2 on JP1 JP8, JP9 8 JP2, JP3 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header 9 9 Jumper 15-38-1024-ND see Pos 7 an 8 10 JTAG 1 14-pin connector, male, HRP14H-ND TH 11 BOOTST 0 DNP Keep vias free of solder Micro Crystal MS3V 12 Q1 0 Crystal 32.768kHz, C(Load) = DNP: keep vias free of solder 12.5pF 13 R1, R7 2 330 Ω, SMD0805 541-330ATR-ND 14 R2, R3,R5, 0 0 Ohm, SMD0805 541-000ATR-ND DNP R2, R3,R5, R6 R6, 15 R4 1 47k Ω, SMD0805 541-47000ATR-ND 16 U1 1 Socket: OTS-28-0.65-01 Manuf.: Enplas 17 PCB 1 63.5 x 64.8 mm 2 layers Adhesive Approximately 6mm for example, 3M 18 plastic feet 4 width, 2mm height Bumpons Part No. SJ- Apply to corners at bottom side 5302 19 MSP430 2 MSP430G2553IPW28 DNP: enclosed with kit, supplied by TI 56 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated DNP DNP DNP DNP DNP DNP DNP DNP GND 0R 330R 2.2nF PWR3 GND GND 0R 47K 470nF 100nF 10uF 100nF GND GND 20k/0.1% 10k 10k 10k 10k GND AVSS AVSS 10k 10k 10k 10k GND SAM1029-08-ND1-8 SAM1029-08-ND9-16 MSP430I2040TRHBQFN11T032-003 SAM1029-08-ND17-2417-24 SAM1029-08-ND25-32 1.0 for MSP430i2040 MSP430: Target-Socket MSP-TS430RHB32A DNP <- SBW <- JTAG Vcc int ext Socket: Yamaichi QFN11T032-003 1 3 5 7 9 11 13 2 4 6 12 14 8 10 JTAG R1 R3 C8 J5 1 2 3 1 JP1 2 1 2 JP2 R4 1 2 3 JP4 1 2 3 JP9 1 2 3 JP8 1 2 3 JP7 1 2 3 JP6 1 2 3 JP5 R5 D1 C9 1 2 3 JP3 C14 C12 C13 R2 R6 R8 R9 R10 R11 R12 R13 R14 1 2 3 4 5 6 7 8 J1 9 10 11 12 13 14 15 16 J2 A0.0+ 1 A0.0- 2 A1.0+ 3 A1.0- 4 A2.0+ 5 A2.0- 6 A3.0+ 7 A3.0- 8 VREF 9 AVSS 10 ROSC 11 DVSS 12 VCC 13 VCORE 14 P2.3/VMONIN 28 P2.2/TA1.2 27 P2.1/TA1.1 26 P2.0/TA1.0/CLKIN 25 P1.7/UCB0SDA/UCB0SIMO/TA1CLK 24 P1.6/UCB0SCL/UCB0SOMI/TA0.2 23 P1.5/UCB0CLK/TA0.1 22 P1.4/UCB0STE/TA0.0 21 P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI 20 P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK 19 P1.1/UCA0CLK/SMCLK/TMS 18 P1.0/UCA0STE/MCLK/TCK 17 TEST/SBWTCK 16 RST/NMI/SBWTDIO 15 U1 P2.4/TA1.0 29 P2.5/TA0.0 30 P2.6/TA0.1 31 P2.7/TA0.2 32 17 18 19 20 21 22 23 24 J3 25 26 27 28 29 30 31 32 J4 TMS TMS TDI TDI TDO TDO TDO VCC GND GND P1.4 P1.4 DVCC DVCC DVCC AVSS M M I I O O RST/NMI RST/NMI TCK TCK TCK C TEST/SBWTCK C TEST/SBWTCK VCORE A0.0+ A0.0- A1.0+ A1.0- VREF ROSC RST RST RST A2.0+ A2.0- A3.0+ A3.0- P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 www.ti.com MSP-TS430RHB32A B.9 MSP-TS430RHB32A Figure B-17. MSP-TS430RHB32A Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 57 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Orient Pin 1 of MSP430 device D1 LED connected to P1.4 Jumper JP1 Open to measure current Connector J5 External power connector Jumper JP3 to “ext” Connector JTAG For JTAG Tool Jumper JP4 to JP9 Close 1-2 to debug in Spy-Bi-Wire mode Close 3-4 to debug in 4-wire JTAG mode Jumper JP3 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Jumper JP2 Open to disconnect LED P1.4 14 1 2 GND GND VCC 1 2 3 3 2 1 8 5 1 16 9 17 20 24 25 30 32 Vcc ext int MSP-TS430RHB32A Rev.: 1.0 RoHS SBW JTAG 1 Curr. Meas. JTAG R1 R3 C8 J5 JP1 JP2 R4 JP4 JP9 JP8 JP7 JP6 JP5 R5 D1 C9 JP3 C14 C13 C12 R2 R6 R8 R9 R10 R11 R12 R13 R14 J1 J2 U1 J3 J4 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 MSP-TS430RHB32A www.ti.com Figure B-18. MSP-TS430RHB32A Target Socket Module, PCB 58 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430RHB32A Table B-10. MSP-TS430RHB32A Bill of Materials Pos. Ref Des No. per Description Digi-Key Part No. Comment Board 1 PCB 1 76.9 x 67.6 mm MSP-TS430RHB32A Rev. 2 layers, red solder mask 1 2 D1 1 green LED, DIODE0805 P516TR-ND 3 JP1, JP2 2 2-pin header, male, TH SAM1035-02-ND place jumper on header 4 JP3, JP4, 7 3-pin header, male, TH SAM1035-03-ND place jumpers on pins 1-2 JP5, JP6, (SBW) JP7, JP8, JP9 5 R1, R4 2 0R, 0805 541-0.0ATR-ND 6 C8 1 2.2nF, CSMD0805 490-1628-2-ND DNP 7 R6, R8, R9, 8 10k, 0805 311-10KARTR-ND DNP R10, R11, R12, R13, R14 8 C12 1 10uF, CSMD0805 445-1371-2-ND 9 R2 1 20k/0.1%, 0805 P20KDACT-ND 10 R5 1 47K, 0805 311-47KARTR-ND 11 C13, C14 2 100nF, CSMD0805 311-1245-2-ND 12 R3 1 330R, 0805 541-330ATR-ND 13 C9 1 470nF, CSMD0805 445-1357-2-ND 14 J1, J2, J3, 1 8-pin header, TH SAM1029-08-ND DNP: headers and J4 receptacles, enclosed with kit. Keep vias free of solder. 15 J1, J2, J3, 1 8-pin receptable, TH SAM1213-08-ND DNP: headers and J4 receptacles, enclosed with kit. Keep vias free of solder. 16 JTAG 1 14-pin connector, male, TH HRP14H-ND 17 U1 1 Socket QFN11T032-003 Manuf.: Yamaichi 18 U1 1 MSP430i2041TRHB DNP: enclosed with kit. Is supplied by TI 19 J5 1 3-pin header, male, TH SAM1035-03-ND 20 Rubber 4 Buerklin: 20H1724 apply to corners at bottom stand off side SLAU278R–May 2009–Revised May 2014 Hardware 59 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated 12pF 12pF GND GND 100nF 560R 10uF/10V 47k 10nF - 0R GND MSP430F2274IDA GND 330R GND yellow If external supply voltage: remove R11 and add R10 (0 Ohm) IC189-0382-037 Socket: 4-wire JTAG: 2-wire "SpyBiWire": JTAG-Mode selection: Set jumpers JP4 to JP9 to position 2-3 Set jumpers JP4 to JP9 to position 2-1 JTAG -> SBW -> Yamaichi DNP DNP DNP DNP DNP DNP DNP 1 3 5 7 9 11 13 2 4 6 12 14 8 10 JTAG C2 C1 C5 R3 1 2 3 4 5 6 7 8 9 10 BOOTST C7 R5 C8 R10 R11 1 2 3 J3 Q1 TEST/SBWTCK 1 P3.5 26 P3.6 27 P1.4/TCK 35 RST/SBWDAT 7 DVCC 2 DVSS 4 P4.7 24 P3.7 28 AVSS 15 AVCC 16 P3.0 11 P3.1 12 P3.2 13 P3.3 14 P4.0 17 P4.1 18 P4.2 19 P3.4 25 P2.5 3 P2.4 30 P2.3 29 P2.2 10 P2.1 9 P2.0 8 P1.5/TMS 36 P1.6/TDI 37 P1.7/TDO 38 P2.7 5 P2.6 6 P4.6 23 P4.5 22 P4.4 21 P4.3 20 P1.0 31 P1.1 32 P1.2 33 P1.3 34 U1 JP1 1 2 3 JP2 1 2 1 2 JP3 1 2 3 JP4 JP5 1 2 3 JP6 1 2 3 JP7 1 2 3 JP8 1 2 3 R1 JP9 1 2 3 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 J1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 20 J2 D1 P1.0 P1.0 RST/NMI TMS TDI VCC GND GND GND VCC430 VCC430 VCC430 TCK/SBWTCK TDO/SBWTDIO TEST/SBWTCK TEST/SBWTCK TEST/SBWTCK TEST/SBWTCK P2.5 P2.0 P2.1 P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 P1.7/TDO P1.7/TDO P1.6/TDI P1.6/TDI P1.5/TMS P1.5/TMS P1.4/TCK P1.4/TCK P1.3 P1.2 P1.1 P1.1 P2.4 P2.3 P3.7 P3.6 P3.5 P3.4 P4.7 P4.6 P4.5 P4.4 P4.3 P2.7/XOUT P2.7/XOUT P2.6/XIN P2.6/XIN RST/SBWTDIO RST/SBWTDIO RST/SBWTDIO P2.2 P2.2 Ext_PWR Date: 6/18/2008 11:04:56 AM Sheet: 1/1 REV: TITLE: Document Number: MSP-TS430DA38 + 1.3 MSP-TS430DA38: Vcc int ext Target Socket Board for MSP430F2247IDA MSP-TS430DA38 www.ti.com B.10 MSP-TS430DA38 Figure B-19. MSP-TS430DA38 Target Socket Module, Schematic 60 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Orient pin 1 of MSP430 device D1 LED connected to P1.0 Connector J3 External power connector Jumper JP1 to "ext" Jumper JP3 Open to disconnect LED Jumper JP2 Open to measure current Jumpers JP4 to JP9 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode Jumper JP1 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool www.ti.com MSP-TS430DA38 Figure B-20. MSP-TS430DA38 Target Socket Module, PCB SLAU278R–May 2009–Revised May 2014 Hardware 61 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430DA38 www.ti.com Table B-11. MSP-TS430DA38 Bill of Materials Pos. Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP 2 C7 1 10uF, 10V, Tantal Size B 511-1463-2-ND 3 C5 1 100nF, SMD0805 478-3351-2-ND 4 C8 0 2.2nF, SMD0805 DNP 5 D1 1 green LED, SMD0603 475-1056-2-ND DNP: headers and receptacles enclosed with 6 J1, J2 0 19-pin header, TH kit.Keep vias free of solder. SAM1029-19-ND : Header SAM1213-19-ND : Receptacle "J3, JP1, Place jumpers on headers 7 JP4, JP5, 8 3-pin header, male, TH SAM1035-03-ND JP1, JP4,JP5, JP6, JP7, JP6, JP7, JP8, JP9; Pos 1-2 JP8, JP9" 8 JP2, JP3 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header 9 9 Jumper 15-38-1024-ND Place on: JP1 - JP9; Pos 1- 2 10 JTAG 1 14-pin connector, male, TH HRP14H-ND 11 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder Micro Crystal MS1V-T1K DNP: Keep vias free of 12 Q1 0 Crystal 32.768kHz, C(Load) = solder 12.5pF 13 R1, R3 2 330 Ω, SMD0805 541-330ATR-ND 14 R10, R11 0 0 Ω, SMD0805 541-000ATR-ND DNP 15 R5 1 47k Ω, SMD0805 541-47000ATR-ND 16 U1 1 Socket: IC189-0382--037 Manuf.: Yamaichi 17 PCB 1 67 x 66 mm 2 layers 18 Adhesive 4 ~6mm width, 2mm height for example, 3M Bumpons Apply to corners at bottom Plastic feet Part No. SJ-5302 side 19 MSP430 2 MSP430F2274IDA DNP: enclosed with kit supplied by TI 62 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430QFN23x0 B.11 MSP-TS430QFN23x0 Figure B-21. MSP-TS430QFN23x0 Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 63 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated D1 LED connected to P1.0 Connector J5 External power connector Jumper JP1 to "ext" Jumper JP3 Open to disconnect LED Jumper JP2 Open to measure current Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool Jumper JP1 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Orient Pin 1 of MSP430 device MSP-TS430QFN23x0 www.ti.com Figure B-22. MSP-TS430QFN23x0 Target Socket Module, PCB 64 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430QFN23x0 Table B-12. MSP-TS430QFN23x0 Bill of Materials Pos. Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP 2 C3 1 10uF, 10V, Tantal Size B 511-1463-2-ND 3 C4 1 100nF, SMD0805 478-3351-2-ND 4 C5 1 10nF, SMD0805 478-1383-2-ND 5 D1 1 green LED, SMD0603 475-1056-2-ND DNP: headers and receptacles enclosed with 6 J1, J2, J3, 0 10-pin header, TH kit.Keep vias free of solder. J4 SAM1034-10-ND : Header SAM1212-10-ND : Receptacle 7 J5, JP1 2 3-pin header, male, TH SAM1035-03-ND Place jumper on header JP1; Pos 1-2. 8 JP2, JP3 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header 9 3 Jumper 15-38-1024-ND Place on: JP1, JP2, JP3 10 JTAG 1 14-pin connector, male, TH HRP14H-ND 11 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder Micro Crystal MS1V-T1K DNP: Keep vias free of 12 Q1 0 Crystal 32.768kHz, C(Load) = solder 12.5pF 13 R1 1 330 Ω, SMD0805 541-330ATR-ND 14 R2, R3 0 0 Ω, SMD0805 541-000ATR-ND DNP 15 R4 1 47k Ω, SMD0805 541-47000ATR-ND 16 U1 1 Socket: QFN-40B-0.5-01 Manuf.: Enplas 17 PCB 1 79 x 66 mm 2 layers 18 Adhesive 4 ~6mm width, 2mm height for example, 3M Bumpons Apply to corners at bottom Plastic feet Part No. SJ-5302 side 19 MSP430 2 MSP430F2370IRHA DNP: enclosed with kit supplied by TI SLAU278R–May 2009–Revised May 2014 Hardware 65 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430RSB40 www.ti.com B.12 MSP-TS430RSB40 Figure B-23. MSP-TS430RSB40 Target Socket Module, Schematic 66 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumper JP2 Open to measure current Orient Pin 1 of MSP430 device Jumper JP3 Open to disconnect LED D1 LED connected to P1.0 Jumpers JP4 to JP9 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode Connector J5 External power connector Jumper JP1 to "ext" Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool Jumper JP1 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply www.ti.com MSP-TS430RSB40 Figure B-24. MSP-TS430RSB40 Target Socket Module, PCB SLAU278R–May 2009–Revised May 2014 Hardware 67 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430RSB40 www.ti.com Table B-13. MSP-TS430RSB40 Bill of Materials Pos. Ref Des No. Per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP: C1, C2 2 C3, C7, C10, 3 10uF, 10V, SMD 0805 445-1371-1-ND DNP C12 C12 3 C4, C6, C8, 3 100nF, SMD0805 311-1245-2-ND DNP C11 C11 4 C5 1 2.2nF, SMD0805 5 C9 1 470nF, SMD0805 6 D1 1 green LED, SMD0805 P516TR-ND DNP: headers and receptacles enclosed with kit. 7 J1, J2, J3, J4 4 10-pin header, TH Keep vias free of solder. : Header : Receptacle DNP: headers and receptacles enclosed with kit. 7.1 4 10-pin header, TH Keep vias free of solder. : Header : Receptacle JP1, JP4,JP5, Jumper: 1-2 on JP1, JP10; 2- 8 JP6, JP7, 9 3-pin header, male, TH SAM1035-03-ND 3 on JP4-JP9 JP8, JP9, J5, JP10 9 JP2, JP3 2 2-pin header, male, TH SAM1035-02-ND place jumper on header 10 JTAG 1 14-pin connector, male, TH HRP14H-ND 11 BOOTST 0 10-pin connector, male, TH DNP. Keep vias free of solder 12 U1 1 QFN-40B-0.4_ Enplas ENPLAS_SOCKET Micro Crystal MS3V-T1R DNP: Q1. Keep vias free of 13 Q1 0 Crystal 32.768kHz, C(Load) = solder 12.5pF Place on: JP1, JP2, JP3, 15 10 Jumper 15-38-1024-ND JP4, JP5, JP6, JP7, JP8, JP9, JP10 16 R1,R7 2 330R SMD0805 R2, R3, R5, 17 R6, R8, R9, 3 0R SMD0805 DNP R2, R3, R5, R6 R10 18 R4 1 47k SMD0805 19 MSP430 2 MSP430F5132 DNP: enclosed with kit. Is supplied by TI 20 Rubber stand 4 select appropriate; for apply to corners at bottom off example, Buerklin: 20H1724 side 68 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430RHA40A B.13 MSP-TS430RHA40A Figure B-25. MSP-TS430RHA40A Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 69 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumper JP2 Open to measure current Connector J5 External power connector Jumper JP1 to "ext" Jumpers JP4 to JP9 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode D1 LED connected to P1.0 Jumper JP3 Open to disconnect LED Orient Pin 1 of MSP430 device Jumper JP1 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool MSP-TS430RHA40A www.ti.com Figure B-26. MSP-TS430RHA40A Target Socket Module, PCB 70 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430RHA40A Table B-14. MSP-TS430RHA40A Bill of Materials Position Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP: C1, C2 2 C5 0 2.2nF, SMD0805 DNP C12 3 C3, C7 2 10uF, 10V, SMD0805 5 DNP C11 4 C4, C6 2 100nF, SMD0805 478-3351-2-ND 5 C9 1 470nF, SMD0805 6 D1 1 green LED, SMD0805 P516TR-ND DNP: headers and receptacles enclosed with kit. Keep vias free of 7 J1, J2, J3, 4 10-pin header, TH solder. J4 : Header : Receptacle DNP: headers and receptacles enclosed with kit. Keep vias free of 7.1 4 10-pin header, TH solder. : Header : Receptacle J5, JP1, 8 JP4, JP5, 8 3-pin header, male, TH SAM1035-03-ND Place jumper on 1-2 of JP4-JP9; JP6, JP7, Place on 1-2 on JP1 JP8, JP9 9 JP2, JP3 2 2-pin header, male, TH SAM1035-02-ND place jumper on header 10 9 Jumper 15-38-1024-ND see Pos 8 an 9 11 JTAG 1 14-pin connector, male, HRP14H-ND TH 12 BOOTST 0 10-pin connector, male, DNP. Keep vias free of solder TH 13 U1 1 Socket: QFN-40B-0.5-01 Manuf.: Enplas Micro Crystal MS3V-T1R 14 Q1 0 Crystal 32.768kHz, C(Load) = DNP: Q1. Keep vias free of solder 12.5pF 15 R1,R7 2 330R SMD0805 541-330ATR-ND R2, R3, 16 R5, R6, 2 0 Ohm, SMD0805 541-000ATR-ND DNP:R2, R3, R5, R6 R8, R9, 17 R4 1 47k SMD0805 18 PCB 1 79 x 66 mm 2 layers Rubber select appropriate; for 19 stand off 4 example, Buerklin: apply to corners at bottom side 20H1724 20 MSP430 2 MSP430N5736IRHA DNP: enclosed with kit. Is supplied by TI SLAU278R–May 2009–Revised May 2014 Hardware 71 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated ML14 LED3 12pF 12pF GND GND 100nF 560R ML10 JP1Q JP1Q 10uF/10V 47K 10nF 0R 0R GND 0R 0R 10uF/10V GND IC51-1387.KS-15186 100nF 1.3 MSP-TS430DL48 Target Socket DL48 Q1, C1, C2 not assembled 1 3 5 7 9 11 13 2 4 6 12 14 8 10 JTAG D1 C2 C1 C5 R3 BOOTST 1 2 3 4 5 6 7 8 9 10 1 2 J5 J4 1 2 C7 R5 C8 R6 R7 1 2 3 J3 Q1 QUARZ3 J2 1 3 5 2 4 6 7 9 8 10 11 13 15 12 14 16 17 19 18 20 21 23 22 24 1 3 5 2 4 6 7 9 8 10 11 13 15 12 14 16 17 19 18 20 21 23 22 24 J1 R12 R4 JP1 1 2 3 1 2 3 JP2 C4 U1 TDO/TDI 1 TDI/TCLK 2 TMS 3 TCK 4 RST/NMI 5 DVCC 6 DVSS 7 XIN 8 XOUT 9 AVSS 10 AVCC 11 VREF+ 12 P6.0 13 P6.1 14 P6.2 15 P6.3 16 P6.4 17 P6.5 18 P6.6 19 P6.7 20 P2.5 39 P2.4 40 P2.3 41 P2.2 42 P2.1 43 P2.0 44 COM0 45 P5.2 46 P5.3 47 P5.4 48 LCDREF 29 LCDCAP 30 P5.1 31 P5.0 32 P5.5 33 P5.6 34 P5.7 35 S5 36 P2.7 37 P2.6 38 P1.7 21 P1.6 22 P1.5 23 P1.4 24 P1.0 28 P1.1 27 P1.2 26 P1.3 25 C3 P1.0 P1.0 RST/NMI RST/NMI RST/NMI TCK TCK TCK TMS TMS TDI TDI TDO TDO XOUT XOUT GND GND GND XIN XIN BSL_TX VCC BSL_RX Ext_PWR Date: 11/14/2006 1:24:44 PM Sheet: 1/1 REV: TITLE: Document Number: MSP-TS430DL48 + + Vcc ext int int ext Vcc MSP-TS430DL48 www.ti.com B.14 MSP-TS430DL48 Figure B-27. MSP-TS430DL48 Target Socket Module, Schematic 72 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumper J4 Open to disconnect LED D1 LED connected to P1.0 Orient pin 1 of MSP430 device Jumper J5 Open to measure current Connector J3 External power connector Jumper JP2 to "ext" Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool Jumper JP2 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply www.ti.com MSP-TS430DL48 Figure B-28. MSP-TS430DL48 Target Socket Module, PCB SLAU278R–May 2009–Revised May 2014 Hardware 73 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430DL48 www.ti.com Table B-15. MSP-TS430DL48 Bill of Materials Pos. Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP 2 C4, C7 2 10uF, 10V, Tantal Size B 511-1463-2-ND 3 C3, C5 2 100nF, SMD0805 478-3351-2-ND 4 C8 1 10nF, SMD0805 478-1383-2-ND 5 D1 1 yellow LED, TH, 3mm, T1 511-1251-ND DNP: Headers and receptacles enclosed with 6 J1, J2 0 24-pin header, TH kit.Keep vias free of solder. SAM1034-12-ND : Header SAM1212-12-ND : Receptacle 7 J3, JP1, JP2 2 3-pin header, male, TH SAM1035-03-ND Place jumper on header JP1; Pos 1-2. DNP: JP2 8 J4, J5 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header 9 3 Jumper 15-38-1024-ND Place on: JP1, J4, J5 10 JTAG 1 14-pin connector, male, TH HRP14H-ND 11 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder Micro Crystal MS1V-T1K DNP: Keep vias free of 12 Q1 0 Crystal 32.768kHz, C(Load) = solder 12.5pF 13 R3 1 560 Ω, SMD0805 541-560ATR-ND 14 R4, R6, R7, 2 0 Ω, SMD0805 541-000ATR-ND DNP: R6, R7 R12 15 R5 1 47k Ω, SMD0805 541-47000ATR-ND 16 U1 1 Socket: IC51-1387 KS- Manuf.: Yamaichi 15186 17 PCB 1 58 x 66 mm 2 layers 18 Adhesive 4 ~6mm width, 2mm height for example, 3M Bumpons Apply to corners at bottom Plastic feet Part No. SJ-5302 side 19 MSP430 2 MSP430F4270IDL DNP: Enclosed with kit supplied by TI 74 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430RGZ48B B.15 MSP-TS430RGZ48B Figure B-29. MSP-TS430RGZ48B Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 75 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumper JP2 Open to disconnect LED Connector J5 External power connector Jumper JP3 to "ext" Jumpers JP5 to JP10 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode D1 LED connected to P1.0 Jumper JP1 Open to measure current Orient Pin 1 of MSP430 device Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool Jumper JP3 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply MSP-TS430RGZ48B www.ti.com Figure B-30. MSP-TS430RGZ48B Target Socket Module, PCB 76 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430RGZ48B Table B-16. MSP-TS430RGZ48B Bill of Materials Position Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP 2 C3, C4 0 47pF, SMD0805 DNP 3 C6, C7, 3 10uF, 6.3V, SMD0805 C12 4 C5, C11, 4 100nF, SMD0805 311-1245-2-ND C13, C14 5 C8 1 2.2nF, SMD0805 6 C9 1 470nF, SMD0805 478-1403-2-ND 7 D1 1 green LED, SMD0805 P516TR-ND J1, J2, J3, SAM1029-12-ND DNP: Headers and receptacles 8 J4 0 12-pin header, TH (Header) SAM1213-12- enclosed with kit. Keep vias free of ND (Receptacle) solder: 9 J5 1 3-pin header, male, TH JP3, JP5, place jumpers on pins 2-3 on JP5, 10 JP6, JP7, 7 3-pin header, male, TH SAM1035-03-ND JP6, JP7, JP8, JP9, JP10 place JP8, JP9, jumpers on pins 1-2 on JP3, JP10 11 JP1, JP2 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header 12 9 Jumper 15-38-1024-ND See Pos. 10and Pos. 11 13 JTAG 1 14-pin connector, male, HRP14H-ND TH 14 BOOTST 0 10-pin connector, male, "DNP Keep vias free of solder" TH Micro Crystal MS3V-T1R 15 Q1 0 Crystal 32.768kHz, C(Load) = DNP: Q1 Keep vias free of solder 12.5pF 16 Q2 0 Crystal Q2: 4MHz Buerklin: DNP: Q2 Keep vias free of solder 78D134 Insulating http://www.ettinger.de/Ar 17 disk to Q2 0 Insulating disk to Q2 t_Detail.cfm?ART_ART NUM=70.08.121 18 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND R1, R2, R4, R6, 19 R8, 3 0 Ohm, SMD0805 541-000ATR-ND DNP: R6, R8, R9, R10, R11,R12 R9,R10, R11, R12 20 R5 1 47k Ω, SMD0805 541-47000ATR-ND 21 U1 1 Socket: QFN11T048- Manuf.: Yamaichi 008_A101121_RGZ48 22 PCB 1 81 x 76 mm 2 layers Adhesive Approximately 6mm for example, 3M 23 plastic feet 4 width, 2mm height Bumpons Part No. SJ- Apply to corners at bottom side 5302 24 MSP430 2 MSP430F5342IRGZ DNP: enclosed with kit, supplied by TI SLAU278R–May 2009–Revised May 2014 Hardware 77 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated DNP DNP DNP GND GND 100nF 330R 0R - GND GND 47k 1.1nF GND 0R 0R 0R 1uF/10V QUARZ5 1uF/10V 100nF green DNP yellow (DNP) DNP red (DNP) 0R GND DNP DNP 0R 0R QUARZ5 EVQ11 0R DNP DNP If external supply voltage: remove R3 and add R2 (0 Ohm) 1.3 Ext_PWR MSP-TS430RGZ48C Vcc int ext Target Socket Board for MSP430FR58xx, FR59xx IRGZ DNP DNP DNP DNP DNP JTAG -> SBW -> JTAG-Mode selection: 4-wire JTAG: Set jumpers JP3 to JP8 to position 2-3 2-wire "SpyBiWire": Set jumpers JP3 to JP8 to position 1-2 connection by via DNP DNP 1 3 5 7 9 11 13 2 4 6 12 14 8 10 JTAG C2 C1 C4 R1 1 2 3 4 5 6 7 8 9 10 BOOTST R3 R2 1 2 3 J2 J1 1 2 3 JP1 1 2 1 2 JP9 R4 C5 1 2 3 JP3 1 2 3 JP4 1 2 3 JP5 1 2 3 JP6 1 2 3 JP7 1 2 3 JP8 R5 R6 R7 C3 Q1 C7 C6 D1 R10 1 2 JP10 D2 R11 1 2 JP11 D3 R12 JP2 1 2 C8 C9 R9 R8 Q2 SV4 1 2 3 4 5 6 7 8 9 10 11 12 SV1 1 2 3 4 5 6 7 8 9 10 11 12 SV2 1 2 3 4 5 6 7 8 9 10 11 12 SV3 1 2 3 4 5 6 7 8 9 10 11 12 1 1_P1.0 2 2_P1.1 3 3_P1.2 4 4_P3.0 5 5_P3.1 6 6_P3.2 7 7_P3.3 8 8_P4.7 9 9_P1.3 10 10_P1.4 11 11_P1.5 12 12_PJ.0_TDO 13 13_PJ.1_TDI 14 14_PJ.2_TMS 15 15_PJ.3/TCK 16 16_P4.0 17 17_P4.1 18 18_P4.2 19 19_P4.3 20 20_P2.5 21 21_P2.6 22 22_TEST/SBWTCK 23 23_RST/SBWTDIO 24 24_P2.0 25_P2.1 25 26_P2.2 26 27_P3.4 27 28_P3.5 28 29_P3.6 29 30_P3.7 30 31_P1.6 31 32_P1.7 32 33_P4.4 33 34_P4.5 34 35_P4.6 35 36_DVSS 36 37_DVCC 37 38_P2.7 38 39_P2.3 39 40_P2.4 40 41_AVSS 41 42_HFXIN 42 43_HFXOUT 43 44_AVSS 44 45_LFXIN 45 46_LFXOUT 46 47_AVSS 47 48_AVCC 48 U1 SW1 R13 TP1TP2 SW2 R14 P1.0 P1.0 RST/NMI TMS TDI VCC GND P1.1 P1.1 RST/SBWTDIO RST/SBWTDIO RST/SBWTDIO TCK/SBWTCK TDO/SBWTDIO PJ.0/TDO PJ.0/TDO PJ.2/TMS PJ.2/TMS PJ.3/TCK PJ.3/TCK PJ.1/TDI PJ.1/TDI P1.2 P1.2 P2.0 P2.0 P2.1 P2.1 P1.3 P1.3 P1.4 P1.5 AVCC AVCC AVSS AVSS AVSS AVSS LFXOUT LFXIN LFGND HFGND HFXOUT HFXIN P2.4 P2.3 P2.7 DVCC DVCC DVCC DVCC DVSS DVSS P4.6 P4.5 P4.4 P1.7 P1.6 P3.7 P3.6 P3.5 P3.4 P2.2 P2.6 P2.5 P4.3 P4.2 P4.1 P4.0 P4.7 P3.3 P3.2 P3.1 P3.0 TEST/SBWTCK1 TEST/SBWTCK TEST/SBWTCK TEST/SBWTCK MSP-TS430RGZ48C www.ti.com B.16 MSP-TS430RGZ48C Figure B-31. MSP-TS430RGZ48C Target Socket Module, Schematic 78 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumper JP1 Open to measure current Connector J2 External power connector Jumper J1 to "ext" Jumpers JP3 to JP8 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode Switch SW1 Device reset LEDs connected to P1.0, P1.1, P1.2 via JP9, JP10, JP11 (only D1 assembled) Orient Pin 1 of MSP430 device Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool Jumper J1 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Jumper JP2 Analog/digital power Switch SW2 Connected to P1.3 HF ands LF oscillators with capacitors and resistors to connect pinheads www.ti.com MSP-TS430RGZ48C Figure B-32. MSP-TS430RGZ48C Target Socket Module, PCB Table B-17. MSP-TS430RGZ48C Revision History Revision Comments 1.2 Initial release LFOSC pins swapped at SV1 (9-10). 1.3 HFOSC pins swapped at SV1 (6-7). BOOTST pin 4 now directly connected to the device RST/SBWTDIO pin. SLAU278R–May 2009–Revised May 2014 Hardware 79 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430RGZ48C www.ti.com Table B-18. MSP-TS430RGZ48C Bill of Materials Number Pos Ref Des Per Description Digi-Key Part Number Comment Board 1 SV1, SV2, SV3, 4 12-pin header, TH DNP: headers and receptacles enclosed with kit. SV4 Keep vias free of solder. SAM1029-12-ND : Header : Receptacle 1.1 SV1, SV2, SV3, 4 12-pin receptable, TH DNP: headers and receptacles enclosed with kit. SV4 Keep vias free of solder. : Header SAM1213-12-ND : Receptacle 2 JP1, JP2, JP9 3 2-pin header, male, TH SAM1035-02-ND Place jumper on header 3 JP10, JP11 2 2-pin header, male, TH SAM1035-02-ND DNP 4 J1, JP3, JP4, JP5, 7 3-pin header, male, TH SAM1035-03-ND Place jumpers on pins 2-3 JP6, JP7, JP8 5 J2 1 3-pin header, male, TH SAM1035-03-ND 6 JP1, JP2, JP9, J1, 10 Jumper 15-38-1024-ND Place on: JP1, JP2, JP9, J1, JP3, JP4, JP5, JP6, JP3, JP4, JP5, JP7, JP8 JP6, JP7, JP8 7 R2, R3, R5, R6, 9 DNP, 0805 DNP R8, R9, R10, R11, R14 8 R12, R13, R7 3 0R, 0805 541-000ATR-ND 9 C5 1 1.1nF, CSMD0805 490-1623-2-ND 10 C3, C7 2 1uF, 10V, CSMD0805 490-1702-2-ND 11 R4 1 47k, 0805 541-47000ATR-ND 12 C4, C6 2 100nF, CSMD0805 311-1245-2-ND 13 R1 1 330R, 0805 541-330ATR-ND 14 C1, C2, C8, C9 4 DNP, CSMD0805 DNP 15 SW1, SW2 2 EVQ-11L05R P8079STB-ND DNP 16 BOOTST 1 10-pin connector, male, TH HRP10H-ND DNP, keep vias free of solder 17 JTAG 1 14-pin connector, male, TH HRP14H-ND 18 Q1 1 DNP: MS3V-TR1 (32768kHz, depends on application Micro Crystal, DNP, enclosed in kit, keep vias 20ppm, 12.5pF) free of solder 19 Q2 1 DNP, Christal depends on application DNP, keep vias free of solder 20 U1 1 Socket: QFN11T048-008 Manuf.: Yamaichi A101121-001 20.1 U1 1 MSP430FR5969IRGZ DNP: enclosed with kit. Is supplied by TI. 21 D1 1 green LED, DIODE0805 P516TR-ND 22 D3 1 red (DNP), DIODE0805 DNP 23 D2 1 yellow (DNP), DIODE0805 DNP 24 TP1, TP2 2 Testpoint DNP, keep pads free of solder 25 Rubber stand off 4 Buerklin: 20H1724 apply to corners at bottom side 26 PCB 1 79.6 x 91.0 mm MSP-TS430RGZ48C 2 layers, black solder mask Rev. 1.2 80 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated ML14 LED3 0R 12pF 12pF 12pF 12pF GND GND 0R 100nF 560R ML10 JP1Q JP1Q 10uF/6,3V 10uF/10V 47K 10nF 0R 0R 0R - - 0R - 0R 0R FE16-1-1 FE16-1-2 FE16-1-3 FE16-1-4 PWR3 GNDGND - MSP64PM not assembled not assembled not assembled not assembled enhancement reserved for future JTAG 1 3 5 7 9 11 13 2 4 6 12 14 8 10 D1 R2 C2 C1 C3 C4 R1 C5 R3 BOOTST 1 2 3 4 5 6 7 8 9 10 J7 1 2 J6 1 2 C6 C7 R5 C8 R6 R7 R8 R9 R10 R11 R12 R13 R14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 J1 J2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 J3 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 J4 J5 1 2 3 R4 Q1 LFXTCLK XTCLK U2 DVCC 2 3 4 5 6 7 XIN XOUT 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 TDO TDI TMS TCK RST 59 60 61 AVSS DVSS AVCC RST/NMI TCK TMS TDI TDO VCC Date: 3/14/2006 10:46:30 AM Sheet: 1/1 REV: TITLE: Document Number: MSP-TS430PM64 + + 1 MSP-TS430PM64 Target Socket PM64 Yamaichi IC51-0644-807 Socket: 1.2 for F14x and F41x Open J6 if LCD is connected If external supply voltage: remove R8 and add R9 (0 Ohm) If external supply voltage: remove R11 and add R10 (0 Ohm) For BSL usage add: R6 R7 R13 R14 MSP430F14x : 0 0 open open MSP430F41x : open open 0 0 www.ti.com MSP-TS430PM64 B.17 MSP-TS430PM64 NOTE: Connections between the JTAG header and pins XOUT and XIN are no longer required and should not be made. Figure B-33. MSP-TS430PM64 Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 81 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Connector J5 External power connection Remove R8 and jumper R9 D1 LED connected to pin 12 Jumper J6 Open to disconnect LED Jumper J7 Open to measure current Orient Pin 1 of MSP430 device Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool MSP-TS430PM64 www.ti.com Figure B-34. MSP-TS430PM64 Target Socket Module, PCB 82 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430PM64 Table B-19. MSP-TS430PM64 Bill of Materials Pos. Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP 1.1 C3, C4 0 47pF, SMD0805 DNP: Only recommendation. Check your crystal spec. 2 C6, C7 1 10uF, 10V, Tantal Size B 511-1463-2-ND DNP: C6 3 C5 1 100nF, SMD0805 478-3351-2-ND 4 C8 1 10nF, SMD0805 478-1383-2-ND 5 C9 1 470nF, SMD0805 478-1403-2-ND 6 D1 1 green LED, SMD0805 P516TR-ND DNP: Headers and receptacles enclosed with 7 J1, J2, J3, J4 0 16-pin header, TH kit.Keep vias free of solder. SAM1029-16-ND : Header SAM1213-16-ND : Receptacle 8 J5 1 3-pin header, male, TH SAM1035-03-ND 9 J6, J7 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header 11 2 Jumper 15-38-1024-ND Place on: J6, J7 12 JTAG 1 14-pin connector, male, TH HRP14H-ND 13 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder Q1: Micro Crystal MS1V-T1K DNP: Keep vias free of 14 Q1, Q2 0 Crystal 32.768kHz, C(Load) = solder 12.5pF 15 R3 1 330 Ω, SMD0805 541-330ATR-ND R1, R2, R4, R6, R7, R8, DNP: R4, R6, R7, R9, R10, 16 R9, R10, 3 0 Ω, SMD0805 541-000ATR-ND R11, R12, R13, R14 R11, R12, R13, R14 17 R5 1 47k Ω, SMD0805 541-47000ATR-ND 18 U1 1 Socket: IC51-0644-807 Manuf.: Yamaichi 19 PCB 1 78 x 75 mm 2 layers 20 Rubber 4 select appropriate Apply to corners at bottom standoff side 21 MSP430 22 MSP430F2619IPM DNP: Enclosed with kit MSP430F417IPM supplied by TI SLAU278R–May 2009–Revised May 2014 Hardware 83 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated 0R 12pF 12pF GND GND 0R 100nF 330R 10uF/6.3V 0R 0R 0R 0R PWR3 GND 47k 2.2nF 330R GND GND 100nF GND 0R 0R MSP-TS430PM64A Target Socket DNP Yamaichi IC51-0644-807 Socket: DNP 1.1 for F4152 Open JP1 if LCD is connected JTAG -> SBW -> DNP DNP DNP DNP DNP DNP DNP Vcc ext int TEST/SBWTCK RST/SBWTDIO P7.0/TDO P7.1/TDI P7.2/TMS P7.3/TCK ADD LCD-CAP! DNP DNP JTAG 1 3 5 7 9 11 13 2 4 6 12 14 8 10 R2 C2 C1 R1 C5 R3 BOOTST 1 2 3 4 5 6 7 8 9 10 C6 R10 R11 R13 R14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 J1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 J2 J3 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 J4 J5 1 2 3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 11 12 13 14 15 10 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 Q1 R4 C3 1 2 3 JP4 JP5 1 2 3 JP6 1 2 3 JP7 1 2 3 JP8 1 2 3 R6 JP9 1 2 3 1 2 JP1 JP2 1 2 JP3 1 2 3 D1 C4 R5 R7 RST/NMI TMS TDI VCC GND XTLGND TCK/SBWTCK TDO/SBWTDIO VCC430 VCC430 VCC430 P5.1 P5.1 AVCC AVCC AVSS AVSS P1.0 P1.1 XIN XOUT A A A B B B C C D D E E F F Date: 3/29/2011 3:07:02 PM Sheet: 1/1 REV: TITLE: Document Number: MSP-TS430PM64A + TEST/SBWTCK RST/SBWTDIO If supplied locally: populate R10 (0R), remove R11 If supplied by interface: populate R11 (0R), remove R10 MSP-TS430PM64A www.ti.com B.18 MSP-TS430PM64A Figure B-35. MSP-TS430PM64A Target Socket Module, Schematic 84 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumper JP2 Open to measure current Jumper JP1 Open to disconnect LED D1 LED connected to P5.1 Jumper JP3 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Jumpers JP4 to JP9 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode Orient Pin 1 ofMSP430 device Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool Connector J5 External power connector Jumper JP3 to "ext" www.ti.com MSP-TS430PM64A Figure B-36. MSP-TS430PM64A Target Socket Module, PCB SLAU278R–May 2009–Revised May 2014 Hardware 85 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430PM64A www.ti.com Table B-20. MSP-TS430PM64A Bill of Materials Pos. Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2, 0 12pF, SMD0805 DNP 2 C3 0 2.2nF, SMD0805 DNP 3 C6, 1 10uF, 10V, Tantal Size B 511-1463-2-ND 4 C4, C5 2 100nF, SMD0805 478-3351-2-ND 5 D1 1 green LED, SMD0805 P516TR-ND DNP: Headers and receptacles enclosed with kit. 6 J1, J2, J3, J4 0 16-pin header, TH Keep vias free of solder. SAM1029-16-ND : Header SAM1213-16-ND : Receptacle J5, JP3, JP4, 7 JP5, JP6, 8 3-pin header, male, TH SAM1035-03-ND JP7, JP8, JP9 8 JP1, JP2 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header 9 2 Jumper 15-38-1024-ND Place on: J6, J7 10 JTAG 1 14-pin connector, male, TH HRP14H-ND 11 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder Micro Crystal MS1V-T1K DNP: Keep vias free of 12 Q1 0 Crystal 32.768kHz, C(Load) = solder 12.5pF 13 R3, R6 2 330 Ω, SMD0805 541-330ATR-ND R1, R2, R5, 14 R7, R9, R10, 2 0 Ω, SMD0805 541-000ATR-ND DNP: R5, R7, R9, R10, R11, R11, R13, R13, R14 R14 15 R4 1 47k Ω, SMD0805 541-47000ATR-ND 16 U1 1 Socket: IC51-0644-807 Manuf.: Yamaichi 17 PCB 1 78 x 75 mm 4 layers 18 Rubber stand 4 select appropriate Apply to corners at bottom off side 19 MSP430 2 MSP430F4152IPM DNP: Enclosed with kit supplied by TI 86 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430RGC64B B.19 MSP-TS430RGC64B Figure B-37. MSP-TS430RGC64B Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 87 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumper JP2 Open to disconnect LED Connector J5 External power connector Jumpers JP5 to JP10 Jumper JP3 to "ext" Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode D1 LED connected to P1.0 If the system should be supplied via LDOI (J6), close JP4 and set JP3 to "ext" Orient Pin 1 of MSP430 device Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool Jumper JP3 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Jumper JP1 Open to measure current MSP-TS430RGC64B www.ti.com Figure B-38. MSP-TS430RGC64B Target Socket Module, PCB 88 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430RGC64B Table B-21. MSP-TS430RGC64B Bill of Materials Pos. Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP 2 C3, C4 0 47pF, SMD0805 DNP 3 C6, C7, C10 3 10uF, 6.3V, SMD0805 C5, C11, 4 C13, C14, 5 100nF, SMD0805 311-1245-2-ND C15 5 C8 1 2.2nF, SMD0805 6 C9 1 470nF, SMD0805 478-1403-2-ND 7 C16 1 4.7uF, SMD0805 8 C17 1 220nF, SMD0805 9 D1 1 green LED, SMD0805 P516TR-ND J1, J2, J3, SAM1029-16-ND DNP: Headers and receptacles 10 J4 0 16-pin header, TH (Header) SAM1213-16- enclosed with kit. Keep vias free of ND (Receptacle) solder: 11 J5 , J6 2 3-pin header, male, TH JP3, JP5, place jumpers on pins 2-3 on JP5, JP6, 12 JP6, JP7, 7 3-pin header, male, TH SAM1035-03-ND JP7, JP8, JP9, JP10 place jumpers on JP8, JP9, pins 1-2 on JP3, JP10 13 JP1, JP2, 3 2-pin header, male, TH SAM1035-02-ND Place jumper on header JP4 14 10 Jumper 15-38-1024-ND See Pos. 12 and Pos. 13 15 JTAG 1 14-pin connector, male, HRP14H-ND TH 16 BOOTST 0 10-pin connector, male, "DNP Keep vias free of solder" TH Micro Crystal MS3V-T1R 17 Q1 0 Crystal 32.768kHz, C(Load) = DNP: Q1 Keep vias free of solder 12.5pF 18 Q2 0 Crystal Q2: 4MHz Buerklin: DNP: Q2 Keep vias free of solder 78D134 Insulating http://www.ettinger.de/Art 19 disk to Q2 0 Insulating disk to Q2 _Detail.cfm?ART_ARTNU M=70.08.121 20 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND R1, R2, R4, 21 R6, R8, 3 0 Ohm, SMD0805 541-000ATR-ND DNP: R6, R8, R9, R10, R11,R12 R9,R10, R11, R12 22 R5 1 47k Ω, SMD0805 541-47000ATR-ND 23 U1 1 Socket: QFN11T064-006- Manuf.: Yamaichi N-HSP 24 PCB 1 85 x 76 mm 2 layers Adhesive Approximately 6mm for example, 3M 25 plastic feet 4 width, 2mm height Bumpons Part No. SJ- Apply to corners at bottom side 5302 26 D3,D4 27 MSP430 2 MSP430F5310 RGC DNP: enclosed with kit, supplied by TI SLAU278R–May 2009–Revised May 2014 Hardware 89 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430RGC64C www.ti.com B.20 MSP-TS430RGC64C The MSP-TS430RGC64C target board has been designed with the option to operate with the target device DVIO input voltage supplied via header J6 (see Figure B-39). This development platform does not supply the 1.8-V DVIO rail on board and it MUST be provided by external power supply for proper device operation. For correct JTAG connection, programming, and debug operation, it is important to follow this procedure: 1. Make sure that the VCC and DVIO voltage supplies are OFF and that the power rails are fully discharged to 0 V. 2. Enable the 1.8-V external DVIO power supply. 3. Enable the 1.8-V to 3.6-V VCC power supply (alternatively, this supply can be provided from the MSPFET430UIF JTAG debugger interface). 4. Connect the MSP-FET430UIF JTAG connector to the target board. 5. Start the debug session using IAR or CCS IDE. For more information on debugging the MSP4and MSP430F525x, see the device-specific data sheets (MSP430F522x: SLAS718; MSP430F525x: SLAS903) and Designing with MSP430F522x and MSP430F521x Devices (SLAA558). For debugging of devices (MSP430F524x and MSP430F523x) without use of the DVIO power domain, short JP4 with the jumper. 90 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated 1.1 MSP-TS430RGC64C TI Friesing Tools MSP430 1 1 12/14/10 S.G. 1 2 3 4 5 6 A B C D A B C D Design: Appr.: Rev.: Comment: Drawing#: Revision: File: Page: Size: Title of Schematic of Mentor Pads Logic V9 Date: Name: 1 2 3 4 5 6 MSP-TS430RGC64C.sch <-- SBW <-- JTAG ext int VCC DVIO Power Circle BSL 1 P6.0/CB0/A0 2 P6.1/CB1/A1 3 P6.2/CB2/A2 4 P6.3/CB3/A3 5 P6.4/CB4/A4 6 P6.5/CB5/A5 7 P6.6/CB6/A6 8 P6.7/CB7/A7 9 P5.0/A8/VEREF+ 10 P5.1/A9/VEREF- 11 AVCC 12 P5.4/XIN 13 P5.5/XOUT 14 AVSS 15 DVCC 16 DVSS 17 VCORE 18 P1.0/TA0CLK/ACLK 19 P1.1/TA0.0 20 P1.2/TA0.1 21 P1.3/TA0.2 22 P1.4/TA0.3 23 P1.5/TA0.4 24 P1.6/TA1CLK/CBOUT 25 P1.7/TA1.0 26 P2.0/TA1.1 27 P2.1/TA1.2 28 P2.2/TA2CLK/SMCLK 29 P2.3/TA2.0 30 P2.4/TA2.1 31 P2.5/TA2.2 32 P2.6/RTCCLK/DMAE0 P2.7/UCB0STE/UCA0CLK 33 P3.0/UCB0SIMO/UCB0SDA 34 P3.1/UCB0SOMI/UCB0SCL 35 P3.2/UCB0CLK/UCA0STE 36 P3.3/UCA0TXD/UCA0SIMO 37 P3.4/UCA0RXD/UCA0SOMI 38 DVSS 39 DVIO 40 P4.0/PM_UCB1STE 41 P4.1/PM_UCB1SIMO 42 P4.2/PM_UCB1SOMI 43 P4.3/PM_UCB1CLK 44 P4.4/PM_UCA1TXD 45 P4.5/PM_UCA1RXD 46 P4.6/PM_NONE 47 P4.7/PM_NONE 48 49 P7.0/TB0.0 50 P7.1/TB0.1 51 P7.2/TB0.2 52 P7.3/TB0.3 53 P7.4/TB0.4 54 P7.5/TB0.5 55 BSLEN 56 RST/NMI 57 P5.2/XT2IN 58 P5.3/XT2OUT 59 TEST/SBWTCK 60 PJ.0/TDO 61 PJ.1/TDI/TCLK 62 PJ.2/TMS 63 PJ.3/TCK 64 RSTDVCC/SBWTDIO 65 THERMAL_1 66 THERMAL_2 67 THERMAL_3 68 THERMAL_4 69 THERMAL_5 70 THERMAL_6 71 THERMAL_7 72 THERMAL_8 U1 MSP430F5229 2 1 4 3 6 5 8 7 10 9 12 11 14 13 JTAG 1 2 3 4 5 6 7 8 9 0 1 BOOTST CN-ML10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 J2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 J3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 J4 1 2 3 JP5 PINHEAD_1X3 1 2 3 JP6 PINHEAD_1X3 1 2 3 JP7 PINHEAD_1X3 1 2 3 JP8 PINHEAD_1X3 1 2 3 JP9 PINHEAD_1X3 1 2 3 JP10 PINHEAD_1X3 1 2 3 J5 PINHEAD_1X3 R7 330R 1 2 3 JP3 C10 10uF C14 100nF C5 10uF C6 100nF R1 0R R2 0R R6 0R R8 0R C1 12pF C2 12pF C7 10uF C13 100nF 1 2 JP2 R3 330R 1 2 D1 ??? R4 0R C9 470nF R5 47K C8 2.2nF R11 0R R12 0R C16 4.7uF tbd C3 tbd C4 R9 0R R10 0R C15 100nF 1 2 3 J6 PINHEAD_1X3 1 2 JP4 PINHEAD_1X2 D3 Q2 QUARZ_4PIN 26MHz/ASX53 Q1 1 2 JP1 PINHEAD_1X2 SHC1 SHORTCUT2 GND GND GND GND XTLGND VCORE GND GND DVCC DVCC GND XTLGND2 GND GND DVCC GND RST/NMI TCK TMS TDI TDO RSTDVCC_SBWTDIO TDO RST/NMI TCK C TCK M TMS I TDI O TDO DVCC P1.2/TA0.1 P1.1/TA0.0 TEST/SBWTCK C M I O DVCC P1.1/TA0.0 P1.2/TA0.1 RSTDVCC_SBWTDIO TEST/SBWTCK AVSS www.ti.com MSP-TS430RGC64C Figure B-39. MSP-TS430RGC64C Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 91 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Connector J5 External power connector for DVCC Set jumper JP3 to "ext" IMPORTANT NOTE: Rev1.0 of the board does not have connection from pin 4 of BOOTST to pin 64 of MCU. To use BSL, these pins should be connected by a wire. Jumper JP2 Open to disconnect LED D1 LED connected to P1.0 Orient Pin 1 of MSP430 device Jumper JP4 For F524x devices, close. For F522x, F523x, and F525x devices, close only if one power supply is used for VCC and DVIO, and if VCC is not higher then 1.98 V. Otherwise, supply DVIO over J6. Do not close if VCC > 1.98 V, as it may damage the chip. Ÿ Ÿ Connector J6 External power connector to supply DVIO Jumpers JP5 to JP10 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool Jumper JP3 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Jumper JP1 Open to measure current MSP-TS430RGC64C www.ti.com Figure B-40. MSP-TS430RGC64C Target Socket Module, PCB 92 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430RGC64C Table B-22. MSP-TS430RGC64C Bill of Materials Item Qty Reference Value Description Comment Supplier No. 1 0 C1, C2 12pF CAP, SMD, Ceramic, 0805 DNP C1 C2 2 0 C3, C4 tbd CAP, SMD, Ceramic, 0805 DNP C3 C4 4 3 C5, C7, C10 10uF CAP, SMD, Ceramic, 0805 5 5 C8 C6 C13-15 100nF CAP, SMD, Ceramic, 0805 Digi-Key: 311-1245-2-ND 5 5 C8 2.2nF CAP, SMD, Ceramic, 0805 6 1 C9 470nF CAP, SMD, Ceramic, 0805 Digi-Key: 478-1403-2-ND 7 1 C16 4.7uF CAP, SMD, Ceramic, 0805 8 1 D1 Green LED LED, SMD, 0805 DNP: headers and receptacles enclosed with 9 4 J1-J4 16-pin header Pin header 1x16: Grid: 100mil kit. Keep vias free of (2.54 mm) solder. : Header SAM1029-16-ND : Receptacle SAM1213-16-ND 10 2 J5, J6 3-pin header, male, TH Pin header 1x3: Grid: 100mil SAM1035-03-ND (2.54 mm) 11 JP5, JP6, JP7, 3-pin header, male, TH Pinheader 1x3: Grid: 100mil place jumpers on pins 2-3 SAM1035-03-ND JP8, JP9, JP10 (2.54 mm) 12 JP3 3-pin header, male, TH Pin header 1x3: Grid: 100mil place jumper on pins 1-2 SAM1035-03-ND (2.54 mm) 13 JP1, JP2, JP4 2-pin header, male, TH Pin header 1x2; Grid: 100mil place jumper on header SAM1035-02-ND (2.54 mm) Place on: JP1, JP2, JP3, 14 10 Jumper JP4, JP5, JP6, JP7, JP8, 15-38-1024-ND JP9, JP10 15 1 JTAG 2x7Pin,Wanne Header, THD, Male 2x7 Pin, HRP14H-ND Wanne, 100mil spacing 16 0 BOOTST 2x5Pin,Wanne Header, THD, Male 2x5 Pin, DNP Wanne, 100mil spacing 17 1 Q1 26MHz/ASX53 CRYSTAL, SMD, 5x3MM, Only Kit. 26MHz 18 0 Q2 26MHz/ASX53 CRYSTAL, SMD, 5x3MM, 300-8219-1-ND 26MHz 19 1 D3 LL103A DIODE, SMD, SOD123, Buerklin: 24S3406 Schottky 20 2 R3, R7 330 Ohm, SMD0805 541-330ATR-ND 21 1 R5 47k Ohm, SMD0805 RES, SMD, 0805, 1/8W, x% 541-47000ATR-ND R1, R2, R4, DNP: R6, R8, R9, R10, 22 R6, R8, R9, 0 Ohm, SMD0805 RES, SMD, 0805, 1/8W, x% R11,R12 541-000ATR-ND R10, R11, R12 23 1 U1 Socket: QFN11T064-006-N- Manuf.: Yamaichi HSP 24 2 MSP430 MSP430F5229IRGCR IC, MCU, SMD, 9.15x9.15mm Thermal Pad with Socket 25 4 Rubber stand Rubber stand off apply to corners at bottom Buerklin: 20H1724 off side 26 1 PCB 84 x 76 mm 84 x 76 mm SLAU278R–May 2009–Revised May 2014 Hardware 93 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430RGC64USB www.ti.com B.21 MSP-TS430RGC64USB Due to the use of diodes in the power chain, the voltage on the MSP430F5xx device is approximately 0.3 V lower than is set by the debugging tool. Set the voltage in the IDE to 0.3 V higher than desired; for example, to run the MCU at 3.0 V, set it to 3.3 V. Figure B-41. MSP-TS430RGC64USB Target Socket Module, Schematic 94 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Orient Pin 1 of MSP430 device Jumpers JP5 to JP10 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode Jumper JP3 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Connector JTAG For JTAG Tool USB1 USB connector Connector J5 External power connector Jumper JP3 to "ext" Jumper JP2 Open to disconnect LED D1 LED connected to P1.0 Jumper JP1 Open to measure current www.ti.com MSP-TS430RGC64USB Figure B-42. MSP-TS430RGC64USB Target Socket Module, PCB SLAU278R–May 2009–Revised May 2014 Hardware 95 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430RGC64USB www.ti.com Table B-23. MSP-TS430RGC64USB Bill of Materials Pos. Ref Des No. Per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP: C1, C2 1.1 C3, C4 2 47pF, SMD0805 2 C6, C7 2 10uF, 6.3V, Tantal Size B 511-1463-2-ND 3 C5, C11, 4 100nF, SMD0805 311-1245-2-ND C13, C14 3.1 C10, C12 0 10uF, SMD0805 DNP: C10, C12 4 C8 1 2.2nF, SMD0805 5 C9 1 470nF, SMD0805 478-1403-2-ND 6 D1 1 green LED, SMD0805 P516TR-ND DNP: headers and receptacles enclosed with kit. 7 J1, J2, J3, J4 4 16-pin header, TH Keep vias free of solder. SAM1029-16-ND : Header SAM1213-16-ND : Receptacle 8 J5 1 3-pin header, male, TH SAM1035-03-ND JP5, JP6, 9 JP7, JP8, 6 3-pin header, male, TH SAM1035-03-ND place jumpers on pins 2-3 JP9, JP10 10 JP1, JP2, 3 2-pin header, male, TH SAM1035-02-ND place jumper on header JP4 11 JP3 1 3-pin header, male, TH SAM1035-03-ND place jumper on pins 1-2 Place on: JP1, JP2, JP3, 12 10 Jumper 15-38-1024-ND JP4, JP5, JP6, JP7, JP8, JP9, JP10 13 JTAG 1 14-pin connector, male, TH HRP14H-ND Q1: Micro Crystal MS1V-T1K DNP: Q1 14 Q1 0 Crystal 32.768kHz, C(Load) = Keep vias free of solder" 12.5pF 15 Q2 1 Crystal Q2: 4MHz Buerklin: 78D134 16 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND R1, R2, R4, 17 R6, R8, R9, 2 0 Ω, SMD0805 541-000ATR-ND DNP: R4, R6, R8, R9, R12 R12 18 R10 1 100 Ω, SMD0805 Buerklin: 07E500 18 R11 1 1M Ω, SMD0805 18 R5 1 47k Ω, SMD0805 541-47000ATR-ND 19 U1 1 Socket: QFN11T064-006 Manuf.: Yamaichi 20 PCB 1 79 x 77 mm 2 layers 21 Rubber stand 4 Buerklin: 20H1724 apply to corners at bottom off side 22 MSP430 2 MSP430F5509 RGC DNP: enclosed with kit. Is supplied by TI Insulating http://www.ettinger.de/Art_De 23 disk to Q2 1 Insulating disk to Q2 tail.cfm?ART_ARTNUM=70.0 8.121 27 C33 1 220n SMD0603 Buerklin: 53D2074 28 C35 1 10p SMD0603 Buerklin: 56D102 29 C36 1 10p SMD0603 Buerklin: 56D102 30 C38 1 220n SMD0603 Buerklin: 53D2074 31 C39 1 4u7 SMD0603 Buerklin: 53D2086 32 C40 1 0.1u SMD0603 Buerklin: 53D2068 33 D2, D3, D4 3 LL103A Buerklin: 24S3406 96 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430RGC64USB Table B-23. MSP-TS430RGC64USB Bill of Materials (continued) Pos. Ref Des No. Per Description Digi-Key Part No. Comment Board 34 IC7 1 TPD4E004 Manu: TI 36 LED 0 JP3QE SAM1032-03-ND DNP 37 LED1 0 LEDCHIPLED_0603 FARNELL: 852-9833 DNP 38 LED2 0 LEDCHIPLED_0603 FARNELL: 852-9868 DNP 39 LED3 0 LEDCHIPLED_0603 FARNELL: 852-9841 DNP 40 R13, R15, 0 470R Buerklin: 07E564 DNP R16 41 R33 1 1k4 / 1k5 Buerklin: 07E612 42 R34 1 27R Buerklin: 07E444 43 R35 1 27R Buerklin: 07E444 44 R36 1 33k Buerklin: 07E740 45 S1 0 PB P12225STB-ND DNP 46 S2 0 PB P12225STB-ND DNP 46 S3 1 PB P12225STB-ND 47 USB1 1 USB_RECEPTACLE FARNELL: 117-7885 SLAU278R–May 2009–Revised May 2014 Hardware 97 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430PN80 www.ti.com B.22 MSP-TS430PN80 NOTE: For MSP430F47x and MSP430FG47x devices: Connect pins 7 and 10 (GND) externally to DVSS (see data sheet). Connect load capacitance on Vref pin 60 when SD16 is used (see data sheet). For use of BSL: connect pin 1 of BOOST to pin 58 of U1 and pin 3 of BOOST to pin 57 of U1. Figure B-43. MSP-TS430PN80 Target Socket Module, Schematic 98 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Connector J5 External power connector Jumper JP1 to "ext" D1 LED connected to pin 12 Jumper J6 Open to disconnect LED Orient Pin 1 of MSP430 device Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool Jumper JP1 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Jumper JP2 Open to measure current www.ti.com MSP-TS430PN80 Figure B-44. MSP-TS430PN80 Target Socket Module, PCB SLAU278R–May 2009–Revised May 2014 Hardware 99 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430PN80 www.ti.com Table B-24. MSP-TS430PN80 Bill of Materials Pos. Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP: C1, C2 1.1 C3, C4 0 47pF, SMD0805 DNP: Only recommendation. Check your crystal spec. 2 C6, C7 1 10uF, 10V, Tantal Size B 511-1463-2-ND 3 C5 1 100nF, SMD0805 478-3351-2-ND 4 C8 1 10nF, SMD0805 478-1383-2-ND 5 D1 1 green LED, SMD0603 475-1056-2-ND DNP: Headers and receptacles enclosed with 6 J1, J2, J3, J4 0 25-pin header, TH kit.Keep vias free of solder. SAM1029-20-ND : Header SAM1213-20-ND : Receptacle 7 J5, JP1 2 3-pin header, male, TH SAM1035-03-ND 8 J6, JP2 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header 9 3 Jumper 15-38-1024-ND Place on: J6, JP2, JP1/Pos1- 2 10 JTAG 1 14-pin connector, male, TH HRP14H-ND 11 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder Q1: Micro Crystal MS1V-T1K DNP: Keep vias free of 12 Q1, Q2 0 Crystal 32.768kHz, C(Load) = solder 12.5pF 13 R3 1 560 Ω, SMD0805 541-560ATR-ND R1, R2, R4, DNP: R4, R6, R7, R10, R11, 14 R6, R7, R10, 2 0 Ω, SMD0805 541-000ATR-ND R12 R11, R12 15 R5 1 47k Ω, SMD0805 541-47000ATR-ND 16 U1 1 Socket: IC201-0804-014 Manuf.: Yamaichi 17 PCB 1 77 x 77 mm 2 layers 18 Adhesive 4 ~6mm width, 2mm height for example, 3M Bumpons Apply to corners at bottom Plastic feet Part No. SJ-5302 side 19 MSP430 2 MSP430FG439IPN DNP: Enclosed with kit supplied by TI 100 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430PN80A B.23 MSP-TS430PN80A Figure B-45. MSP-TS430PN80A Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 101 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Connector J5 External power connector Jumper JP3 to "ext" Orient Pin 1 of MSP430 device Jumpers JP5 to JP10 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode D1 LED connected to P1.0 Jumper JP2 Open to disconnect LED Connector J6 If the system is supplied via LDOI, close JP4 and set JP3 to external Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool Jumper JP3 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Jumper JP1 Open to measure current MSP-TS430PN80A www.ti.com Figure B-46. MSP-TS430PN80A Target Socket Module, PCB 102 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430PN80A Table B-25. MSP-TS430PN80A Bill of Materials Position Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP 2 C3, C4 0 47pF, SMD0805 DNP 3 C6, C7, 3 10uF, 6.3V, SMD0805 DNP C10 C10, C12 C5, C11, 4 C13, C14, 5 100nF, SMD0805 311-1245-2-ND C15 5 C8 1 2.2nF, SMD0805 6 C9 1 470nF, SMD0805 478-1403-2-ND 7 C16 1 4.7uF, SMD0805 8 C17 1 220nF, SMD0805 9 D1 1 green LED, SMD0805 P516TR-ND J1, J2, J3, SAM1029-20-ND DNP: Headers and receptacles 10 J4 0 20-pin header, TH (Header) SAM1213-20- enclosed with kit. Keep vias free of ND (Receptacle) solder: 11 J5 , J6 2 3-pin header, male, TH JP3, JP5, place jumpers on pins 2-3 on JP5, 12 JP6, JP7, 7 3-pin header, male, TH SAM1035-03-ND JP6, JP7, JP8, JP9, JP10 place JP8, JP9, jumpers on pins 1-2 on JP3, JP10 13 JP1, JP2, 3 2-pin header, male, TH SAM1035-02-ND Place jumper on header JP4 14 10 Jumper 15-38-1024-ND See Pos. 12 and Pos. 13 15 JTAG 1 14-pin connector, male, HRP14H-ND TH 16 BOOTST 0 10-pin connector, male, "DNP Keep vias free of solder" TH Micro Crystal MS3V-T1R 17 Q1 0 Crystal 32.768kHz, C(Load) = DNP: Q1 Keep vias free of solder 12.5pF 18 Q2 0 Crystal Q2: 4MHz Buerklin: DNP: Q2 Keep vias free of solder 78D134 Insulating http://www.ettinger.de/Ar 19 disk to Q2 0 Insulating disk to Q2 t_Detail.cfm?ART_ART NUM=70.08.121 20 D3,D4 2 LL103A Buerklin: 24S3406 21 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND R1, R2, R4, R6, 22 R8, 3 0 Ohm, SMD0805 541-000ATR-ND DNP: R6, R8, R9, R10, R11,R12 R9,R10, R11, R12 23 R5 1 47k Ω, SMD0805 541-47000ATR-ND 24 U1 1 Socket:IC201-0804-014 Manuf.: Yamaichi 25 PCB 1 77 x 91 mm 2 layers Adhesive Approximately 6mm for example, 3M 26 plastic feet 4 width, 2mm height Bumpons Part No. SJ- Apply to corners at bottom side 5302 27 MSP430 2 MSP430F5329IPN DNP: enclosed with kit, supplied by TI SLAU278R–May 2009–Revised May 2014 Hardware 103 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430PN80USB www.ti.com B.24 MSP-TS430PN80USB Due to the use of diodes in the power chain, the voltage on the MSP430F5xx device is approximately 0.3 V lower than is set by the debugging tool. Set the voltage in the IDE to 0.3 V higher than desired; for example, to run the MCU at 3.0 V, set it to 3.3 V. NOTE: R11 should be populated. Figure B-47. MSP-TS430PN80USB Target Socket Module, Schematic 104 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumper JP3 1-2 (int): Power supply via JTAG debug interface 2-3 (ext): External power supply Connector J5 External power connector Jumper JP3 to "ext" USB Connector Button S3 BSL invoke Jumper JP4 Close for USB bus powered device Jumper JP2 Open to disconnect LED D1 LED connected to P1.0 Jumper JP1 Open to measure current Jumpers JP5 to JP10 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode Connector JTAG For JTAG Tool Orient Pin 1 of MSP430 device www.ti.com MSP-TS430PN80USB Figure B-48. MSP-TS430PN80USB Target Socket Module, PCB SLAU278R–May 2009–Revised May 2014 Hardware 105 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430PN80USB www.ti.com Table B-26. MSP-TS430PN80USB Bill of Materials Pos. Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP: C1, C2 1.1 C3, C4 2 47pF, SMD0805 2 C6, C7 2 10uF, 6.3V, Tantal Size B 511-1463-2-ND 3 C5, C11, 4 100nF, SMD0805 311-1245-2-ND C13, C14 3.1 C10, C12 0 10uF, SMD0805 311-1245-2-ND DNP: C10, C12 4 C8 1 2.2nF, SMD0805 5 C9 1 470nF, SMD0805 478-1403-2-ND 6 D1 1 green LED, SMD0805 P516TR-ND DNP: headers and 7 J1, J2, J3, 4 20-pin header, TH SAM1029-20-ND receptacles enclosed with J4 kit. Keep vias free of solder. DNP: headers and receptacles enclosed with kit. Keep vias free of 7.1 4 20-pin header, TH solder. SAM1213-20-ND : Header : Receptacle 8 J5 1 3-pin header, male, TH SAM1035-03-ND JP5, JP6, 9 JP7, 6 3-pin header, male, TH SAM1035-03-ND Place jumpers on pins 2-3 JP8,JP9, JP10 10 JP1, JP2 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header JP4 1 SAM1035-02-ND Place jumper only on one pin 11 JP3 1 3-pin header, male, TH SAM1035-03-ND Place jumper on pins 1-2 Place on: JP1, JP2, JP3, 12 10 Jumper 15-38-1024-ND JP4, JP5, JP6, JP7, JP8, JP9, JP10 13 JTAG 1 14-pin connector, male, TH HRP14H-ND Micro Crystal MS1V-T1K DNP: Q1 Keep vias free of 14 Q1 0 Crystal 32.768kHz, C(Load) = solder 12.5pF 15 Q2 1 Crystal "Q2: 4MHzBuerklin: 78D134" 16 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND R1, R2, R4, 17 R6, R8, R9, 2 0 Ω, SMD0805 541-000ATR-ND DNP: R4, R6, R8, R9, R12 R12 18 R10 1 100 Ω, SMD0805 Buerklin: 07E500 18 R11 0 1M Ω, SMD0805 DNP 18 R5 1 47k Ω, SMD0805 541-47000ATR-ND 19 U1 1 Socket:IC201-0804-014 Manuf.: Yamaichi 20 PCB 1 79 x 77 mm 2 layers 21 Rubber 4 Buerklin: 20H1724 Apply to corners at bottom standoff side 22 MSP430 2 MSP430F5529 DNP: Enclosed with kit supplied by TI Insulating http://www.ettinger.de/Art_ 23 disk to Q2 1 Insulating disk to Q2 Detail.cfm?ART_ARTNUM =70.08.121 27 C33 1 220n Buerklin: 53D2074 106 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430PN80USB Table B-26. MSP-TS430PN80USB Bill of Materials (continued) Pos. Ref Des No. per Description Digi-Key Part No. Comment Board 28 C35 1 10p Buerklin: 56D102 29 C36 1 10p Buerklin: 56D102 30 C38 1 220n Buerklin: 53D2074 31 C39 1 4u7 Buerklin: 53D2086 32 C40 1 0.1u Buerklin: 53D2068 33 D2, D3, D4 3 LL103A Buerklin: 24S3406 34 IC7 1 TPD4E004 Manu: TI 36 LED 0 JP3QE SAM1032-03-ND DNP 37 LED1 0 LEDCHIPLED_0603 FARNELL: 852-9833 DNP 38 LED2 0 LEDCHIPLED_0603 FARNELL: 852-9868 DNP 39 LED3 0 LEDCHIPLED_0603 FARNELL: 852-9841 DNP 40 R13, R15, 0 470R Buerklin: 07E564 DNP R16 41 R33 1 1k4 Buerklin: 07E612 42 R34 1 27R Buerklin: 07E444 43 R35 1 27R Buerklin: 07E444 44 R36 1 33k Buerklin: 07E740 45 S1 0 PB P12225STB-ND DNP 46 S2 0 PB P12225STB-ND DNP 46 S3 1 PB P12225STB-ND 47 USB1 1 USB_RECEPTACLE FARNELL: 117-7885 SLAU278R–May 2009–Revised May 2014 Hardware 107 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430PZ100 www.ti.com B.25 MSP-TS430PZ100 NOTE: Connections between the JTAG header and pins XOUT and XIN are no longer required and should not be made. Figure B-49. MSP-TS430PZ100 Target Socket Module, Schematic 108 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Connector J5 External power connection Remove R8 and jumper R9 D1 LED connected to pin 12 Jumper J6 Open to disconnect LED Orient Pin 1 of MSP430 device Jumper J7 Open to measure current Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool www.ti.com MSP-TS430PZ100 Figure B-50. MSP-TS430PZ100 Target Socket Module, PCB SLAU278R–May 2009–Revised May 2014 Hardware 109 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430PZ100 www.ti.com Table B-27. MSP-TS430PZ100 Bill of Materials Pos. Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP DNP: Only 1b C3, C4 0 47pF, SMD0805 recommendation. Check your crystal spec. 2 C6, C7 1 10uF, 10V, Tantal Size B 511-1463-2-ND DNP: C6 3 C5 1 100nF, SMD0805 478-3351-2-ND 4 C8 1 10nF, SMD0805 478-1383-2-ND 5 C9 1 470nF, SMD0805 478-1403-2-ND 6 D1 1 yellow LED, TH, 3mm, T1 511-1251-ND DNP: Headers and receptacles enclosed with 7 J1, J2, J3, 0 25-pin header, TH kit.Keep vias free of solder. J4 SAM1029-25-ND : Header SAM1213-25-ND : Receptacle 8 J5 1 3-pin header, male, TH SAM1035-03-ND 9 J6, J7 2 2-pin header, male, TH SAM1035-02-ND place jumper on header 10 2 Jumper 15-38-1024-ND Place on: J6, J7 11 JTAG 1 14-pin connector, male, TH HRP14H-ND 12 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder Q1: Micro Crystal MS1V- DNP: Keep vias free of 13 Q1, Q2 0 Crystal T1K 32.768kHz, C(Load) = solder 12.5pF 14 R3 1 330 Ω, SMD0805 541-330ATR-ND R1, R2, R4, 15 R8, R9, R10, 3 0 Ω, SMD0805 541-000ATR-ND DNP: R4, R9, R10, R12 R11, R12 16 R5 1 47k Ω, SMD0805 541-47000ATR-ND 17 U1 1 Socket: IC201-1004-008 or Manuf.: Yamaichi IC357-1004-53N 18 PCB 1 82 x 90 mm 2 layers 19 Adhesive 4 ~6mm width, 2mm height for example, 3M Bumpons Apply to corners at bottom Plastic feet Part No. SJ-5302 side 20 MSP430 2 MSP430FG4619IPZ DNP: enclosed with kit supplied by TI 110 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430PZ100A B.26 MSP-TS430PZ100A Figure B-51. MSP-TS430PZ100A Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 111 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumper JP1 Open to measure current Jumper JP2 Open to disconnect LED D1 LED connected to P5.1 Jumper JP3 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Orient Pin 1 of MSP430 Device Connector J5 External power connector Jumper JP3 to "ext" Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool MSP-TS430PZ100A www.ti.com Figure B-52. MSP-TS430PZ100A Target Socket Module, PCB 112 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430PZ100A Table B-28. MSP-TS430PZ100A Bill of Materials Pos. Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP DNP: Only 1b C3, C4 0 47pF, SMD0805 recommendation. Check your crystal spec. 2 C7, C9 2 10uF, 10V, Tantal Size B 511-1463-2-ND 3 C5, C11, 3 100nF, SMD0805 311-1245-2-ND C14 4 C8 1 10nF, SMD0805 478-1358-1-ND 5 C6 0 470nF, SMD0805 478-1403-2-ND DNP 6 D1 1 green LED, SMD0805 67-1553-1-ND DNP: Headers and receptacles enclosed with 7 J1, J2, J3, 0 25-pin header, TH kit.Keep vias free of solder. J4 SAM1029-25-ND : Header SAM1213-25-ND : Receptacle 8 J5 1 3-pin header, male, TH SAM1035-03-ND 10 JP1, JP2 2 2-pin header, male, TH SAM1035-02-ND pPlace jumper on header 11 JP3 1 3-pin header, male, TH SAM1035-03-ND Place jumper on pins 1-2 12 3 Jumper 15-38-1024-ND Place on: JP1, JP2, JP3 13 JTAG 1 14-pin connector, male, TH HRP14H-ND 14 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder Q1: Micro Crystal MS1V- DNP: Keep vias free of 15 Q1, Q2 0 Crystal T1K 32.768kHz, C(Load) = solder 12.5pF 16 R3 1 330 Ω, SMD0805 541-330ATR-ND R1, R2, R4, 17 R6, R7, R8, 2 0 Ω, SMD0805 541-000ATR-ND DNP: R4, R6, R7, R8, R9, R9, R10, R10, R11, R12 R11, R12 18 R5 1 47k Ω, SMD0805 541-47000ATR-ND 19 U1 1 Socket: IC357-1004-53N Manuf.: Yamaichi 20 PCB 1 90 x 82 mm 4 layers 21 Rubber 4 Select appropriate Apply to corners at bottom standoff side 22 MSP430 2 MSP430F47197IPZ DNP: Enclosed with kit supplied by TI SLAU278R–May 2009–Revised May 2014 Hardware 113 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430PZ100B www.ti.com B.27 MSP-TS430PZ100B Figure B-53. MSP-TS430PZ100B Target Socket Module, Schematic 114 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Connector J5 External power connector Jumper JP3 to "ext" Jumper JP1 Open to measure current Orient Pin 1 of MSP430 device Jumpers JP5 to JP10 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode JP11, JP12, JP13 Connect 1-2 to connect AUXVCCx with DVCC or drive AUXVCCx externally D1 LED connected to P1.0 Jumper JP2 Open to disconnect LED Jumper JP3 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool www.ti.com MSP-TS430PZ100B Figure B-54. MSP-TS430PZ100B Target Socket Module, PCB SLAU278R–May 2009–Revised May 2014 Hardware 115 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430PZ100B www.ti.com Table B-29. MSP-TS430PZ100B Bill of Materials Position Ref Des No. per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP C4, C5, 2 C6 , C7, 6 100nF, SMD0805 311-1245-2-ND C8, C9 3 C10, C26 2 470 nF, SMD0805 478-1403-2-ND 4 C11, C12 1 10 uF / 6.3 V SMD0805 C12 DNP C13, C14, 5 C16, C18, 6 4.7 uF SMD0805 C19, C29 6 D1 1 green LED, SMD0805 P516TR-ND J1, J2, J3, SAM1029-25-ND DNP: Headers and receptacles 7 J4 0 25-pin header, TH (Header) SAM1213-25- enclosed with kit. Keep vias free of ND (Receptacle) solder: 8 J5 1 3-pin header, male, TH JP3, JP5, place jumpers on pins 2-3 on JP5, 9 JP6, JP7, 7 3-pin header, male, TH SAM1035-03-ND JP6, JP7, JP8, JP9, JP10 place JP8, JP9, jumpers on pins 1-2 on JP3, JP10 10 JP1, JP2, 3 2-pin header, male, TH SAM1035-02-ND Place jumper on header JP4 11 JP11, 3 4-pin header, male, TH place jumper on header 1-2 JP12, JP13 12 13 Jumper 15-38-1024-ND See Pos. 9 and Pos. 10 and Pos. 11 15 JTAG 1 14-pin connector, male, HRP14H-ND TH 16 BOOTST 0 10-pin connector, male, "DNP Keep vias free of solder" TH 17 Q1 0 Crystal DNP: Q1 Keep vias free of solder 21 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND R1, R2, 22 R4, R6, 2 0 Ohm, SMD0805 541-000ATR-ND DNP: R4, R6, R8, R10, R11 R8, R10, R11 23 R5 1 47k Ω, SMD0805 541-47000ATR-ND 24 U1 1 Socket: IC357-1004-53N Manuf.: Yamaichi 25 PCB 1 90 x 82 mm 2 layers Adhesive Approximately 6mm for example, 3M 26 plastic feet 4 width, 2mm height Bumpons Part No. SJ- Apply to corners at bottom side 5302 27 MSP430 2 MSP430F6733IPZ DNP: enclosed with kit, supplied by TI 116 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated DNP DNP DNP DNP DNP DNP 0R 12pF 12pF 47pF 47pF GND 0R 100nF 330R 10uF/6.3V 10uF/6.3V 2.2nF PWR3 GND GND GND 0R GND 330R 47K 100nF 100nF P516TR-ND 470nF 100nF 100nF 0R 0R 0R 0R GND VCC 100nF GND 100nF 100nF GND 100nF LL103A GND 4.7n HCTC_XTL_4 HCTC_XTL_4 HCTC_XTL_4 HCTC_XTL_4 GND 0R 0R GND GND GND 4.7uF GND 100nF 220nF GND VCC LL103A 1.1 MSP430: Target-Socket MSP-TS430PZ100C Socket: Yamaichi IC201-1004-008 LFXTCLK <- SBW <- JTAG Vcc int ext DNP DNP DNP DNP DNP DNP BSL-Rx BSL-Tx DNP 1 3 5 7 9 11 13 2 4 6 12 14 8 10 JTAG R2 C2 C1 C3 C4 C5 R1 R3 C6 C7 C8 1 2 3 J5 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 44 43 42 41 37 38 39 40 17 18 19 20 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 U1 QFP100PZ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 J1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 J2 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 J3 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 J4 1 JP1 2 1 JP2 2 R4 1 2 3 JP5 1 2 3 JP6 1 2 3 JP7 1 2 3 JP8 1 2 3 JP9 1 2 3 R7 JP10 R5 C11 C12 D1 C9 C13 C10 R6 R8 R9 R12 1 2 3 JP3 C17 C18 C19 C14 D3 C16 1 2 3 JP11 4 1 2 Q1G$1 3 4 Q1G$2 2 1 Q2G$1 4 3 Q2G$2 1 2 3 4 5 6 7 8 9 10 BOOTST R10 R11 C15 C20 C21 1 JP4 2 D4 1 2 3 J6 TMS TMS TDI TDI TDO TDO TDO XOUT VCC GND GND GND XIN P1.0 DVCC1 DVCC1 DVCC1 DVCC1 DVCC1 DVCC1 AVCC XT2OUT AVSS AVSS AVSS M M I I O O XT2IN RST/NMI RST/NMI TCK TCK TCK C C TEST/SBWTCK TEST/SBWTCK TEST/SBWTCK RST RST RST XTLGND2 XTLGND1 PU.0 PU.1 P1.6 P1.7 P8.0 P8.1 P8.2 VBAK VBAT VBAT VBAT P1.1 P1.1 P1.2 P1.2 LDOI LDOI LDOO LDOO BSL Interface LDOI/LDOO Interface + + Note: If the system should be supplied via LDOI (J6) close JP4 and set JP3 to external www.ti.com MSP-TS430PZ100C B.28 MSP-TS430PZ100C Figure B-55. MSP-TS430PZ100C Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 117 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated If the system should be supplied via LDOI (J6), close JP4 and set JP3 to external Jumper JP2 Open to disconnect LED D1 LED connected to P1.0 Orient Pin 1 of MSP430 device LDOI/LDOO 14 1 2 GND GND VCC 1 05 11 5 2 0 25 26 30 3540 45 50 75 70 65 60 55 51 100 95 90 85 80 76 1 2 3 123 123 123 123 123 3 2 1 1 2 3 4 10 1 2 1 2 3 1 SBW JTAG Vcc int ext GND VBAT DVCC JTAG R2 C2 C1 C3 C4 R1 C5 R3 + C6 + C7 C8 J5 U1 J1 J2 J3 J4 JP1 JP2 R4 JP5 JP6 JP7 JP8 JP9 JP10 R7 R5 C11 C12 D1 C9 C13 C10 R6 R8 R9 R12 JP3 C17 C18 C19 C14 D3 C16 JP11 Q1 Q2 BOOTST R10 R11 C15 C20 C21 JP4 D4 J6 Jumpers JP5 to JP10 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode Jumper JP3 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool Connector J5 External power connector Jumper JP3 to "ext" Jumper JP1 Open to measure current MSP-TS430PZ100C www.ti.com Figure B-56. MSP-TS430PZ100C Target Socket Module, PCB 118 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430PZ100C Table B-30. MSP-TS430PZ100C Bill of Materials Number Pos. Ref Des Per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP: C1, C2 1.1 C3, C4 2 47pF, SMD0805 DNP: C3, C4 2 C6, C7 2 10uF, 6.3V, Tantal Size B 511-1463-2-ND C5, C11, 3 C13, C14, 6 100nF, SMD0805 311-1245-2-ND C19, C20 3.1 C10, C12, 0 100nF, SMD0805 311-1245-2-ND DNP: C10, C12,C18, C17 C18,17 4 C8 1 2.2nF, SMD0805 Buerklin 53 D 292 5 C9 1 470nF, SMD0805 478-1403-2-ND 6 D1 1 green LED, SMD0805 P516TR-ND 7 J1, J2, J3, 4 25-pin header, TH SAM1029-25-ND DNP: headers and receptacles enclosed J4 with kit. Keep vias free of solder. 7.1 4 25-pin header, TH SAM1213-25-ND DNP: headers and receptacles enclosed with kit. Keep vias free of solder. 8 J5, J6 2 3-pin header, male, TH SAM1035-03-ND JP5, JP6, 9 JP7, 6 3-pin header, male, TH SAM1035-03-ND place jumpers on pins 2-3 JP8,JP9, JP10 10 JP1, JP2 2 2-pin header, male, TH SAM1035-02-ND place jumper on header 10.1 JP4 1 2-pin header, male, TH SAM1035-02-ND place jumper on header 11 JP3 1 3-pin header, male, TH SAM1035-03-ND place jumper on pins 1-2 12 10 Jumper 15-38-1024-ND Place on: JP1, JP2, JP3, JP4, JP5, JP6, JP7, JP8, JP9, JP10 13 JTAG 1 14-pin connector, male, TH HRP14H-ND 14 BOOTST 1 10-pin connector, male, TH HRP10H-ND DNP, keep vias free of solder 15 Q1 0 Crystal DNP: Q1 Keep vias free of solder 16 Q2 1 Crystal DNP: Q2 Keep vias free of solder 17 R3, R7 2 330 Ohm, SMD0805 541-330ATR-ND R1, R2, R4, 18 R6, R8, R9, 3 0 Ohm, SMD0805 541-000ATR-ND DNP: R6, R8, R9, R10, R11, R12 R10, R11, R12 19 R5 1 47k Ohm, SMD0805 541-47000ATR-ND 20 U1 1 Socket: IC357-1004-53N Manuf.: Yamaichi 21 PCB 1 79.5 x 99.5 mm MSP-TS430PZ100C 2 layers Rev 1.0 22 Rubber 4 Buerklin: 20H1724 apply to corners at bottom side stand off 23 MSP430 2 MSP430F643x DNP: enclosed with kit. Is supplied by TI. 24 C16 1 4.7 nF SMD0603 Buerklin 53 D 2042 26 D3, D4 2 LL103A Buerklin: 24S3406 27 JP11 1 4-pin header, male, TH SAM1035-04-ND Place jumper on Pin 1 and Pin 2 28 C15 1 4.7 uF, SMD0805 Buerklin 53 D 2430 29 C21 1 220nF, SMD0805 Buerklin 53 D 2381 SLAU278R–May 2009–Revised May 2014 Hardware 119 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430PZ100C www.ti.com 120 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated DNP Socket: Yamaichi IC201-1004-008 DNP DNP GND GND 100nF 330R 0R - GND GND 47k 1.1nF GND 0R 0R QUARZ5 1uF/10V 1uF/10V 100nF green DNP yellow (DNP) DNP red (DNP) 0R GND DNP DNP 0R 0R QUARZ5 EVQ11 0R DNP DNP MSP430FR698XPZ FE25-1A1 FE25-1A2 FE25-1A3 FE25-1A4 100nF GND 100nF GND 1uF/10V 100nF GND GND 470nF GND 0R 4u7 GND If external supply voltage: remove R3 and add R2 (0 Ohm) Ext_PWR MSP-TS430PZ100D Vcc int ext Target Socket Board for MSP430FR698xPZ, FR688xPZ DNP DNP DNP DNP DNP JTAG -> SBW -> JTAG-Mode selection: 4-wire JTAG: Set jumpers JP3 to JP8 to position 2-3 2-wire "SpyBiWire": Set jumpers JP3 to JP8 to position 1-2 connection by via DNP DNP Petersen 1099/1/001/01.1 1.2 DNP DNP DNP DNP DNP DNP DNP 1 3 5 7 9 11 13 2 4 6 12 14 8 10 JTAG C2 C1 C4 R1 1 2 3 4 5 6 7 8 9 10 BSL R3 R2 1 2 3 J2 1 2 3 J1 1 2 JP1 1 2 JP9 R4 C5 1 2 3 JP3 1 2 3 JP4 1 2 3 JP5 1 2 3 JP6 1 2 3 JP7 1 2 3 JP8 R5 R6 Q1 C3 C7 C6 D1 R10 1 2 JP10 D2 R11 1 2 JP11 D3 R12 1 2 JP2 C8 C9 R9 R8 Q2 SW1 R13 TP1TP2 SW2 R14 1 P4.3/UCA0SOMI/UCA0RXD/UCB1STE 2 P1.4/UCB0CLK/UCA0STE/TA1.0/S1 3 P1.5/UCB0STE/UCA0CLK/TA0.0/S0 4 P1.6/UCB0SIMO/USB0SDA/TA0.1 5 P1.7/UCB0SOMI/UCB0SCL/TA0.2 6 R33/LCDCAP 7 P6.0/R23 8 P6.1/R13/LCDREF 9 P6.2/COUT/R03 10 P6.3/COM0 11 P6.4/TB0.0/COM1 12 P6.5/TB0.1/COM2 13 P6.6/TB0.2/COM3 14 P2.4/TB0.3/COM4/S43 15 P2.5/TB0.4/COM5/S42 16 P2.6/TB0.5/COM6/S41 17 P2.7/TB0.6/COM7/S40 18 P10.2/TA1.0/SMCLK/S39 19 P5.0/TA1.1/MCLK/S38 20 P5.1/TA1.2/S37 21 P5.2/TA1.0/TA1CLK/ACLK/S36 22 P5.3/UCB1STE/S35 23 P3.0/UCB1CLK/S34 24 P3.1/UCB1SIMO/UCB1SDA/S33 25 P3.2/UCB1SOMI/UCB1SCL/S32 26 DVSS1 27 DVCC1 28 TEST/SBWTCK 29 XRST/NMI/SBWTDIO 30 PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1 31 PJ.1/TDI/TCLK/MCLK/SRSCG0 32 PJ.2/TMS/ACLK/SROSCOFF 33 PJ.3/TCK/COUT/SRCPUOFF 34 P6.7/TA0CLK/S31 35 P7.5/TA0.2/S30 36 P7.6/TA0.1/S29 37 P10.1/TA0.0/S28 38 P7.7/TA1.2/TB0OUTH/S27 39 P3.3/TA1.1/TB0CLK/S26 40 P3.4/UCA1SIMO/UCA1TXD/TB0.0/S25 41 P3.5/UCA1SOMI/UCA1RXD/TB0.1/S24 42 P3.6/UCA1CLK/TB0.2/S23 43 P3.7/UCA1STE/TB0.3/S22 44 P8.0/RTCCLK/S21 45 P8.1/DMAE0/S20 46 P8.2/S19 47 P8.3/MCLK/S18 48 P2.3/UCA0STE/TB0OUTH 49 P2.2/UCA0CLK/TB0.4/RTCCLK 50 P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0 P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK51 P7.0/TA0CLK/S17 52 P7.1/TA0.0/S16 53 P7.2/TA0.1/S15 54 P7.3/TA0.2/S14 55 P7.4/SMCLK/S13 56 DVSS2 57 DVCC2 58 P8.4/A7/C7 59 P8.5/A6/C6 60 P8.6/A5/C5 61 P8.7/A4/C4 62 P1.3/ESITEST4/TA1.2/A3/C3 63 P1.2/TA1.1/TA0CLK/COUT/A2/C2 64 P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VEREF+65 P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VEREF66 P9.0/ESICH0/ESITEST0/A8/C8 67 P9.1/ESICH1/ESITEST1/A9/C9 68 P9.2/ESICH2/ESITEST2/A10/C10 69 P9.3/ESICH3/ESITEST3/A11/C11 70 P9.4/ESICI0/A12/C12 71 P9.5/ESICI1/A13/C13 72 P9.6/ESICI2/A14/C14 73 P9.7/ESICI3/A15/C15 74 ESIVCC 75 ESIVSS 76 ESICI 77 ESICOM 78 AVCC1 79 AVSS3 80 PJ.7/HFXOUT 81 PJ.6/HFXIN 82 AVSS1 83 P4.2/UCA0SIMO/UCA0TXD/UCB1CLK 100 DVCC3 99 DVSS3 98 P4.1/UCB1SOMI/UCB1SCL/ACLK/S2 97 P4.0/UCB1SIMO/UCB1SDA/MCLK/S3 96 P10.0/SMCLK/S4 95 P4.7/UCB1SOMI/UCB1SCL/TA1.2/S5 94 P4.6/UCB1SIMO/UCB1SDA/TA1.1/S6 93 P4.5/UCB1CLK/TA1.0/S7 92 P4.4/UCB1STE/TA1CLK/S8 91 P5.7/UCA1STE/TB0CLK/S9 90 P5.6/UCA1CLK/S10 89 P5.5/UCA1SOMI/UCA1RXD/S11 88 P5.4/UCA1SIMO/UCA1TXD/S12 87 AVSS2 86 PJ.5/LFXOUT 85 PJ.4/LFXIN 84 IC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 J3 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 J4 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 J5 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 J6 C10 C11 1 2 JP12 C12 C13 C14 R7 P1.0 C15 P1.0 RST/NMI TMS TDI VCC GND P1.1 P1.1 TCK/SBWTCK TDO/SBWTDIO PJ.0/TDO PJ.0/TDO PJ.2/TMS PJ.2/TMS PJ.3/TCK PJ.3/TCK PJ.1/TDI PJ.1/TDI P1.2 P1.2 BSLTX BSLTX BSLRX BSLRX P1.3 P1.3 AVCC AVCC AVSS AVSS AVSS AVSS LFXOUT LFXIN LFGND HFGND HFXIN HFXOUT DVCC DVCC DVCC DVCC DVCC DVCC DVCC DVCC DVCC DVSS DVSS DVSS DVSS TEST/SBWTCK1 TEST/SBWTCK TEST/SBWTCK TEST/SBWTCK LCDCAP LCDCAP ESIVCC ESIVCC ESICOM ESICOM ESIVSS RST/SBWTDIO RST/SBWTDIO RST/SBWTDIO 1 2 3 4 5 6 1 2 3 4 5 6 Titel: Datum: Bearb.: Seite 1/1 MSP-TS430PZ100D 7/9/2013 5:23:25 PM A3 A B C D E F G H I A B C D E F G H I File: Dok: Rev.: www.ti.com MSP-TS430PZ100D B.29 MSP-TS430PZ100D Figure B-57. MSP-TS430PZ100D Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 121 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated 1 Vcc ext int Vcc GND GND JTAG SBW RESET Ext. Pwr. PWR DVCC AVCC TCK TMS TDI TDO RST/SBWTDIO TEST/SBWTCK GND GND P1.3 ESIVCC 14 1 2 10 1 2 1 1 1 1 1 1 1 1 25 5 10 15 20 50 45 40 35 30 26 51 75 55 60 65 70 76 80 85 90 95 100 MSP-TS430PZ100D Rev. 1.2 RoHS Q2 Q1 P1.0 P1.1 P1.2 JTAG C2 C1 C4 R1 BSL R2 R3 J2 J1 JP1 JP9 C5 R4 JP3 JP4 JP5 JP6 JP7 JP8 R5 R6 C3 C6 C7 D1 R10 JP10 D2 R11 JP11 D3 R12 JP2 C8 C9 R8 R9 SW1 R13 TP2 TP1 SW2 R14 IC1 J3 J4 J5 J6 C10 C11 JP12 C12 C13 C14 R7 C15 Orient Pin 1 of MSP430 device LEDs connected to P1.0, P1.1, P1.2 via JP9, JP10, JP11 (only D1 assembled) Switch SW2 Connected to P1.3 Jumper JP1 Open to measure current Connector J2 External power connector Jumper J1 to “ext” Connector BSL For Bootstrap Loader Tool Connector JTAG For JTAG Tool Jumper JP3 to JP8 Close 1-2 to debug in Spy-Bi-Wire mode Close 3-4 to debug in 4-wire JTAG mode Jumper J1 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Switch SW1 Device reset HF and LF oscillators with capacitors and resistors to connect pinheads MSP-TS430PZ100D www.ti.com Figure B-58. MSP-TS430PZ100D Target Socket Module, PCB 122 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430PZ100D Table B-31. MSP-TS430PZ100D Bill of Materials Number Pos. Ref Des Per Description Digi-Key Part No. Comment Board 1 PCB 1 90.0 x 100.0 mm MSP-TS430PZ100D 2 layers, white solder mask Rev 1.2 2 JP1, JP2, 3 2-pin header, male, TH SAM1035-02-ND place jumper on header JP9 3 JP10, JP11, 3 2-pin header, male, TH SAM1035-02-ND DNP, keep pads free of solder JP12 4 J1 1 3-pin header, male, TH SAM1035-03-ND place jumpers on pins 1-2 5 JP3, JP4, 6 3-pin header, male, TH SAM1035-03-ND place jumpers on pins 2-3 JP5, JP6, JP7, JP8 6 J2 1 3-pin header, male, TH SAM1035-03-ND 7 R2, R3, R5, 6 0R, 0805 541-0.0ATR-ND DNP R6, R8, R9 8 R7, R12, 3 0R, 0805 541-0.0ATR-ND R13 9 C5 1 1.1nF, CSMD0805 490-1623-2-ND 10 C3, C7 2 1uF/10V, CSMD0805 490-1702-2-ND 11 C12 1 1uF/10V, CSMD0805 490-1702-2-ND DNP 12 R4 1 47k, 0805 541-47KATR-ND 13 C4, C6, 4 100nF, CSMD0805 490-1666-1-ND C10, C11 14 C13 1 100nF, CSMD0805 490-1666-1-ND DNP 15 C15 1 4u7, CSMD0805 445-1370-1-ND DNP 16 R1 1 330R, 0805 541-330ATR-ND 17 C14 1 470nF, CSMD0805 587-1290-2-ND DNP 18 R10, R11 2 330R, 0805 541-330ATR-ND DNP 19 R14 1 47k, 0805 541-47KATR-ND DNP 20 C1, C2, C8, 4 DNP, CSMD0805 DNP C9 21 SW2 1 EVQ-11L05R P8079STB-ND DNP 22 SW1 1 EVQ-11L05R P8079STB-ND DNP 23 J3, J4, J5, 4 25-pin header, TH DNP: headers and receptacles enclosed J6 with kit. Keep vias free of solder. SAM1029-25-ND : Header 24 J3, J4, J5, 4 25-pin receptacle, TH DNP: headers and receptacles enclosed J6 with kit. Keep vias free of solder. SAM1213-25-ND : Receptacle 25 TP1, TP2 2 Testpoint DNP, keep pads free of solder 26 BSL 1 10-pin connector, male, TH HRP10H-ND DNP, keep vias free of solder 27 JTAG 1 14-pin connector, male, TH HRP14H-ND 28 IC1 1 Socket: IC201-1004-008 Manuf. Yamaichi 29 IC1 1 MSP430FR6989 DNP: enclosed with kit. Is supplied by TI 30 Q1 1 DNP: MS3V-TR1 depends on application Micro Crystal, DNP, enclosed in kit, keep (32768kHz/20ppm/12,5pF) vias free of solder 31 Q2 1 DNP, Crystal depends on application DNP, keep vias free of solder 32 D1 1 green LED, DIODE0805 P516TR-ND 33 D3 1 red (DNP), DIODE0805 DNP 34 D2 1 yellow (DNP), DIODE0805 DNP 35 Rubber 4 Buerklin: 20H1724 apply to corners at bottom side stand off SLAU278R–May 2009–Revised May 2014 Hardware 123 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430PZ5x100 www.ti.com B.30 MSP-TS430PZ5x100 Figure B-59. MSP-TS430PZ5x100 Target Socket Module, Schematic 124 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Connector J5 External power connector Jumper JP3 to "ext" Jumper JP1 Open to measure current Jumper JP2 Open to disconnect LED D1 LED connected to P1.0 Jumpers JP5 to JP10 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode Jumper JP3 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool Orient Pin 1 ofMSP430 device www.ti.com MSP-TS430PZ5x100 Figure B-60. MSP-TS430PZ5x100 Target Socket Module, PCB SLAU278R–May 2009–Revised May 2014 Hardware 125 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430PZ5x100 www.ti.com Table B-32. MSP-TS430PZ5x100 Bill of Materials Pos. Ref Des No. Per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP 1b C3, C4 47pF, SMD0805 DNP: Only recommendation. Check your crystal spec. 2 C6, C7 2 10uF, 10V, Tantal Size B 511-1463-2-ND C5, C10, 3 C11, C12, 4 100nF, SMD0805 311-1245-2-ND DNP: C12, C14 C13, C14 4 C8 0 2.2nF, SMD0805 DNP 5 C9 1 470nF, SMD0805 478-1403-2-ND 6 D1 1 green LED, SMD0805 67-1553-1-ND DNP: headers and receptacles enclosed with kit. 7 J1, J2, J3, J4 0 25-pin header, TH Keep vias free of solder. SAM1029-25-ND : Header SAM1213-25-ND : Receptacle 8 J5 1 3-pin header, male, TH SAM1035-03-ND JP5, JP6, 9 JP7, JP8, 6 3-pin header, male, TH SAM1035-03-ND Place jumpers on pins 2-3 JP9, JP10 10 JP1, JP2 2 2-pin header, male, TH SAM1035-02-ND Place jumper on header 11 JP3 1 3-pin header, male, TH SAM1035-03-ND Place jumper on pins 1-2 12 9 Jumper 15-38-1024-ND Place on JP1, JP2, JP3, JP5, JP6, JP7, JP8, JP9, JP10 13 JTAG 1 14-pin connector, male, TH HRP14H-ND 14 BOOTST 0 10-pin connector, male, TH DNP: Keep vias free of solder Q1: Micro Crystal MS1V-T1K DNP: Keep vias free of 15 Q1, Q2 0 Crystal 32.768kHz, C(Load) = solder 12.5pF 16 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND R1, R2, R4, 17 R6, R8, R9, 3 0 Ω, SMD0805 541-000ATR-ND DNP: R6, R8, R9, R10, R11, R10, R11, R12 R12 18 R5 1 47k Ω, SMD0805 541-47000ATR-ND 19 U1 1 Socket: IC357-1004-53N Manuf.: Yamaichi 20 PCB 1 90 x 82 mm 2 layers 21 Rubber 4 Select appropriate Apply to corners at bottom standoff side 22 MSP430 2 MSP430F5438IPZ DNP: Enclosed with kit supplied by TI 126 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430PZ100USB B.31 MSP-TS430PZ100USB Due to the use of diodes in the power chain, the voltage on the MSP430F5xx device is approximately 0.3 V lower than is set by the debugging tool. Set the voltage in the IDE to 0.3 V higher than desired; for example, to run the MCU at 3.0 V, set it to 3.3 V. Figure B-61. MSP-TS430PZ100USB Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 127 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Jumpers LED 1, 2, 3 Open to disconnect LED1, LED2, LED3 LED1, D2, D3 LEDs connected to P8.0, LE LE P8.1, P8.2 Orient Pin 1 of MSP430 device Jumpers JP5 to JP10 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode Jumper JP3 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply Connector JTAG For JTAG Tool USB1 USB connector Connector J5 External power connector Jumper JP3 to "ext" Jumper JP2 Open to disconnect LED D1 LED connected to P1.0 Jumper JP1 Open to measure current MSP-TS430PZ100USB www.ti.com Figure B-62. MSP-TS430PZ100USB Target Socket Module, PCB 128 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430PZ100USB Table B-33. MSP-TS430PZ100USB Bill of Materials Pos. Ref Des No. Per Description Digi-Key Part No. Comment Board 1 C1, C2 0 12pF, SMD0805 DNP: C1, C2 1.1 C3, C4 2 47pF, SMD0805 2 C6, C7 2 10uF, 6.3V, Tantal Size B 511-1463-2-ND C5, C11, 3 C13, C14, 5 100nF, SMD0805 311-1245-2-ND C19 3.1 C10, C12, 0 100nF, SMD0805 311-1245-2-ND DNP: C10, C12,C18, C17 C18, C17 4 C8 1 2.2nF, SMD0805 5 C9 1 470nF, SMD0805 478-1403-2-ND 6 D1 1 green LED, SMD0805 P516TR-ND DNP: headers and receptacles enclosed with kit. 7 J1, J2, J3, J4 4 25-pin header, TH SAM1029-25-ND Keep vias free of solder. : Header : Receptacle DNP: headers and receptacles enclosed with kit. 7.1 4 25-pin header, TH SAM1213-25-ND Keep vias free of solder. : Header : Receptacle 8 J5 1 3-pin header, male, TH SAM1035-03-ND JP5, JP6, 9 JP7, JP8, 6 3-pin header, male, TH SAM1035-03-ND place jumpers on pins 2-3 JP9, JP10 10 JP1, JP2, 3 2-pin header, male, TH SAM1035-02-ND place jumper on header JP4 11 JP3 1 3-pin header, male, TH SAM1035-03-ND place jumper on pins 1-2 Place on: JP1, JP2, JP3, 12 10 Jumper 15-38-1024-ND JP4, JP5, JP6, JP7, JP8, JP9, JP10 13 JTAG 1 14-pin connector, male, TH HRP14H-ND Micro Crystal MS1V-T1K DNP: Q1. Keep vias free of 14 Q1 0 Crystal 32.768kHz, C(Load) = solder 12.5pF 15 Q2 1 Crystal Q2: 4MHz, Buerklin: 78D134 16 R3, R7 2 330 Ω, SMD0805 541-330ATR-ND R1, R2, R4, 17 R6, R8, R9, 3 0 Ω, SMD0805 541-000ATR-ND DNP: R6, R8, R9, R12 R12 18 R10 1 100 Ω, SMD0805 Buerklin: 07E500 18 R11 1 1M Ω, SMD0603 not existing in Rev 1.0 18 R5 1 47k Ω, SMD0805 541-47000ATR-ND 19 U1 1 Socket:IC201-1004-008 Manuf.: Yamaichi 20 PCB 1 79 x 77 mm 2 layers 21 Rubber stand 4 Buerklin: 20H1724 apply to corners at bottom off side 22 MSP430 2 MSP430F6638IPZ DNP: enclosed with kit. Is supplied by TI Insulating http://www.ettinger.de/Art_De 23 disk to Q2 1 Insulating disk to Q2 tail.cfm?ART_ARTNUM=70.0 8.121 24 C16 1 4.7 nF SMD0603 27 C33 1 220n SMD0603 Buerklin: 53D2074 28 C35, C36 2 10p SMD0603 Buerklin: 56D102 SLAU278R–May 2009–Revised May 2014 Hardware 129 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-TS430PZ100USB www.ti.com Table B-33. MSP-TS430PZ100USB Bill of Materials (continued) Pos. Ref Des No. Per Description Digi-Key Part No. Comment Board 30 C38 1 220n SMD0603 Buerklin: 53D2074 31 C39 1 4u7 SMD0603 Buerklin: 53D2086 32 C40 1 0.1u SMD0603 Buerklin: 53D2068 33 D2, D3, D4 3 LL103A Buerklin: 24S3406 34 IC7 1 TPD4E004 Manu: TI 35 LED 0 JP3QE SAM1032-03-ND DNP 36 LED1, LED2, 0 LEDCHIPLED_0603 FARNELL: 852-9833 DNP LED3 37 R13, R15, 0 470R SMD0603 Buerklin: 07E564 DNP R16 38 R33 1 1k4 / 1k5 SMD0603 Buerklin: 07E612 39 R34 1 27R SMD0603 Buerklin: 07E444 40 R35 1 27R SMD0603 Buerklin: 07E444 41 R36 1 33k SMD0603 Buerklin: 07E740 42 S1, S2, S3 1 PB P12225STB-ND DNP S1 and S2. (Only S3) 43 USB1 1 USB_RECEPTACLE FARNELL: 117-7885 44 JP11 1 4-pin header, male, TH SAM1035-04-ND place jumper only on Pin 1 130 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated 0R 12pF 12pF GND GND 0R 100nF 330R 2.2nF 0R 0R PWR3 GND 330R 47K 0R 0R 100nF 4.7uF GND GND 100nF 470nF 0R QUARZ5 100nF 10uF/6,3V 10uF/6,3V 100nF 4.7uF 4.7uF 100nF 4.7uF 4.7uF 4.7uF 470nF FE04-1 VCC GND GND 100nF 4.7uF GND GND GND GND GND VCC1 VCC1 VCC1 VCC1 VCC1 GND GND GND GND GND GND AVSS AVSS DVCC AVCC GND VCC VCC GND MSP430: Target-Socket MSP-TS430PEU128 for F6779 Petersen 1080/1/001/01.1 DNP LFXTCLK DNP <- SBW <- JTAG DNP Vcc int ext DNP DNP DNP DNP DNP DNP DNP DVDSYS 1.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 J1 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 J2 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 J3 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 J4 1 3 5 7 9 11 13 2 4 6 12 14 8 10 JTAG R2 C2 C1 R1 C5 R3 1 2 3 4 5 6 7 8 9 10 BOOTST C3 R10 R11 J5 1 2 3 1 2 JP1 JP2 1 2 1 2 3 JP5 1 2 3 JP6 1 2 3 JP7 1 2 3 JP8 1 2 3 JP9 1 2 3 JP10 R7 R5 D1 R6 R8 C6 C29 C7 C10 R4 Q1 JP12 1 2 3 4 1 2 3 4 JP11 JP131 2 3 4 C4 C11 C12 C8 C13 C14 C9 C16 C19 C18 C26 1 2 JP4 JP3 1 2 3 4 C15 C17 TP1 TP2 IC1 MSP430F677XIPEU# XIN 1 XOUT 2 AUXVCC3 3 RTCCAP1 4 RTCCAP0 5 P1.5/SMCLK/CB0/A5 6 P1.4/MCLK/SDCLK/CB1/A4 7 P1.3/ADC10CLK/TACLK/RTCCLK/A3 8 P1.2/ACLK/TA3.1/A2 9 P1.1/TA2.1/VEREF+/A1 10 P1.0/TA1.1/TA0.0/VEREF-/A0 11 P2.4/PM_TA2.0 12 P2.5/PM_UCB0SOMI/PM_UCB0SCL 13 P2.6/PM_USB0SIMO/PM_UCB0SDA 14 P2.7/PM_UCB0CLK 15 P3.0/PM_UCA0RXD/PM_UCA0SOMI 16 P3.1/PM_UCA0TXD/PM_UCA0SIMO 17 P3.2/PM_UCA0CLK 18 P3.3/PM_UCA1CLK 19 P3.4/PM_UCA1RXD/PM_UCA1SOMI 20 P3.5/PM_UCA1TXD/PM_UCA1SIMO 21 COM0 22 COM1 23 P1.6/COM2 24 P1.7/COM3 25 P5.0/COM4 26 P5.1/COM5 27 P5.2/COM6 28 P5.3/COM7 29 LCDCAP/R33 30 P5.4/SDCLK/R23 31 P5.5/SD0DIO/LCDREF/R13 32 P5.6/SD1DIO/R03 33 P5.7/SD2DIO/CB2 34 P6.0/SD3DIO 35 P3.6/PM_UCA2RXD/PM_UCA2SOMI 36 P3.7/PM_UCA2TXD/PM_UCA2SIMO 37 P4.0/PM_UCA2CLK 38 P4.1/PM_UCA3RXD/PM_UCA3SOMI 39 P4.2/PM_UCA3TXD/PM_UCA3SIMO 40 P4.3/PM_UCA3CLK 41 P4.4/PM_UCB1SOMI/PM_UCB1SCL 42 P4.5/PM_UCB1SIMO/PM_UCB1SDA 43 P4.6/PM_UCB1CLK 44 P4.7/PM_TA3.0 45 P6.1/SD4DIO/S39 46 P6.2/SD5DIO/S38 47 P6.3/SD6DIO/S37 48 P6.4/S36 49 P6.5/S35 50 P6.6/S34 51 P6.7/S33 52 P7.0/S32 53 P7.1/S31 54 P7.2/S30 55 P7.3/S29 56 P7.4/S28 57 P7.5/S27 58 P7.6/S26 59 P7.7/S25 60 P8.0/S24 61 P8.1/S23 62 P8.2/S22 63 P8.3/S21 64 P8.4/S20 65 P8.5/S19 66 P8.6/S18 67 P8.7/S17 68 DVSYS 69 DVSS2 70 P9.0/S16 71 P9.1/S15 72 P9.2/S14 73 P9.3/S13 74 P9.4/S12 75 P9.5/S11 76 P9.6/S10 77 P9.7/S9 78 P10.0/S8 79 P10.1/S7 80 P10.2/S6 81 P10.3/S5 82 P10.4/S4 83 P10.5/S3 84 P10.6/S2 85 P10.7/S1 86 P11.0/S0 87 P11.1/TA3.1/CB3 88 P11.2/TA1.1 89 P11.3/TA2.1 90 P11.4/CBOUT 91 P11.5/TACLK/RTCCLK 92 P2.0/PM_TA0.0 93 P2.1/PM_TA0.1 94 P2.2/PM_TA0.2 95 P2.3/PM_TA1.0 96 TEST/SBWTCK 97 PJ.0/TDO 98 PJ.1/TDI/TCLK 99 PJ.2/TMS 100 PJ.3/TCK 101 ~RST/NMI/SBWTDIO 102 SD0P0 103 SD0N0 104 SD1P0 105 SD1N0 106 SD2P0 107 SD2N0 108 SD3P0 109 SD3N0 110 VASYS2 111 AVSS2 112 VREF 113 SD4P0 114 SD4N0 115 SD5P0 116 SD5N0 117 SD6P0 118 SD6N0 119 AVSS1 120 AVCC 121 VASYS1 122 AUXVCC2 123 AUXVCC1 124 VDSYS 125 DVCC 126 DVSS1 127 VCORE 128 P1.0 P1.0 P2.0 P2.0 P2.1 P2.1 SD0P0 SD0N0 SD1P0 SD1N0 SD2P0 SD2N0 SD3P0 SD3N0 SD4P0 SD4N0 SD5P0 SD5N0 SD6P0 SD6N0 VASYS1/2 VASYS1/2 VASYS1/2 VASYS1/2 TMS TMS TDI TDI TDO TDO TDO XOUT GND GND XIN DVCC AVCC DVDSYS DVDSYS DVDSYS DVDSYS AVSS AVSS PJ.2 PJ.2 PJ.1 PJ.1 PJ.0 PJ.0 RST/NMI RST/NMI TCK TCK TCK PJ.3 PJ.3 TEST/SBWTCK TEST/SBWTCK TEST/SBWTCK TEST/SBWTCK RST RST RST RST LCDCAP LCDCAP VREF VREF VEREF+ VEREF+ VCORE AUXVCC2 AUXVCC2 AUXVCC1 AUXVCC1 AUXVCC3 AUXVCC3 1 2 3 4 5 6 1 2 3 4 5 6 Titel: Datum: Bearb.: Seite 1/1 MSP-TS430PEU128 22.05.2012 09:37:33 A3 A B C D E F G H I A B C D E F G H I File: Dok: Rev.: www.ti.com MSP-TS430PEU128 B.32 MSP-TS430PEU128 Figure B-63. MSP-TS430PEU128 Target Socket Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 131 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated 1 P1.0 SBW JTAG DVDSYS ext int MSP-TS430PEU128 Rev. 1.1 RoHS DVCC AUXVCC GND AUXVCC1 AUXVCC2 AUXVCC3 GND GND RST/NMI TCK TDI TDO TEST/SBWTCK TMS 1 25 5 10 15 20 30 35 40 45 50 55 60 64 65 90 70 75 80 85 95 100 128 125 120 115 110 105 14 1 2 10 1 2 GND GND VCC 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1 1 2 3 4 1234 1234 1 J1 J2 J3 J4 JTAG R2 C2 C1 R1 C5 R3 BOOTST C3 R10 R11 J5 JP1 JP2 JP5 JP6 JP7 JP8 JP9 JP10 R7 R5 D1 R6 R8 C6 C29 C7 C10 R4 JP12 JP11 JP13 C4 C11 C12 C8 C13 C14 C9 C16 C19 C18 C26 JP4 JP3 C15 C17 TP1 TP2 IC1 Connector J5 External power connector Jumper JP3 to "ext" Jumper JP1 Open to measure current Orient Pin 1 of MSP430 device Jumpers JP5 to JP10 Close 1-2 to debug in Spy-Bi-Wire mode Close 2-3 to debug in 4-wire JTAG mode JP11, JP12, JP13 Connect 1-2 to connect AUXVCCx with DVCC or drive AUXVCCx externally D1 LED connected to P1.0 Jumper JP2 Open to disconnect LED Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool Jumper JP3 1-2 (int): Power supply via JTAG interface 2-3 (ext): External power supply MSP-TS430PEU128 www.ti.com Figure B-64. MSP-TS430PEU128 Target Socket Module, PCB NOTE: The MSP-TS430PEU128 Rev 1.1 ships with the following modifications: • R7 value is changed to 0 Ω instead of 330 Ω. • JTAG pin 8 is connected only to JP5 pin 3, and not to pin 2. • JP5 pin 2 is connected to IC1 pin 97. • BOOTST pin 7 is connected to IC1 pin 97. 132 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-TS430PEU128 Table B-34. MSP-TS430PEU128 Bill of Materials Pos. Ref Des No. Per Description Digi-Key Part No. Comment Board 1 PCB 1 94x119.4mm, 4 layers MSP-TS430PEU128 4 layers, green solder mask Rev. 1.1 2 D1 1 green LED, DIODE0805 516-1434-1-ND 3 JP1, JP2, JP4 3 2-pin header, male, TH SAM1035-02-ND Place jumper on header 4 JP5, JP6, JP7, JP8, 6 3-pin header, male, TH SAM1035-03-ND Place jumpers on pins 1-2 (SBW) JP9, JP10 5 JP11, JP12, JP13 3 4-pin header, male, TH SAM1035-04-ND Place jumpers on pins 1-2 (AVCC=VCC) 6 JP3 1 4-pin header, male, TH SAM1035-04-ND Place jumpers on pins 1-2 JP1, JP2, JP3, JP4, Jumper WM4592-ND 7 JP5, JP6, JP7, JP8, 13 JP9, JP10, JP11, JP12, JP13 8 R1, R2, R4, R6, R8 5 0R, 0805 541-0.0ATR-ND 9 R10, R11 2 0R, 0805 541-0.0ATR-ND DNP 10 C3 1 2.2nF, CSMD0805 490-1628-2-ND DNP 11 C13, C14, C16, 7 4.7uF, 6.3V, CSMD0805 587-1302-2-ND C17, C18, C19, C29 12 C11 1 10uF, 6.3V, CSMD0805 445-1372-2-ND 13 C12 1 10uF, 6.3V, CSMD0805 445-1372-2-ND DNP 14 C1, C2 2 12pF, CSMD0805 490-5531-2-ND DNP 15 R5 1 47K, 0805 311-47KARTR-ND 16 C4, C5, C6, C7, C8, 6 100nF, CSMD0805 311-1245-2-ND C15 17 C9 1 100nF, CSMD0805 311-1245-2-ND DNP 18 R3, R7 2 330R, 0805 541-330ATR-ND 19 C10, C26 2 470nF, CSMD0805 587-1282-2-ND 20 BOOTST 1 10-pin connector, male, TH HRP10H-ND DNP, keep vias free of solder 21 JTAG 1 14-pin connector, male, TH HRP14H-ND 22 IC1 Socket 1 Socket: IC500-1284-009P Manuf. Yamaichi 23 IC1 2 MSP430F67791IPEU DNP: enclosed with kit. Is supplied by TI 24 J5 1 3-pin header, male, TH SAM1035-03-ND 25 Q1 1 Crystal: MS3V-T1R 32.768kHz DNP: Crystal enclosed with kit. Keep vias 12.5pF ±20ppm free of solder 26 TP1, TP2 2 Test point DNP, keep vias free of solder 27 J2,J4 2 26-pin header, TH SAM1029-26-ND DNP: Headers enclosed with kit. Keep vias free of solder. 28 J2,J4 2 26-pin receptable, TH SAM1213-26-ND DNP: Receptacles enclosed with kit. Keep vias free of solder. 29 J1, J3 2 38-pin header, TH SAM1029-38-ND DNP: Headers enclosed with kit. Keep vias free of solder. 30 J1, J3 2 38-pin receptable, TH SAM1213-38-ND DNP: Receptacles enclosed with kit. Keep vias free of solder. 31 Rubber feet 4 Rubber feet Buerklin: 20H1724 apply to bottom side corners SLAU278R–May 2009–Revised May 2014 Hardware 133 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Power Management VCC01 = external VCC Vdd = DVCC Vdda1 = AVDD_RF / AVCC_RF Vdda2 = AVCC Port connectors CON1 .. CON3 = Port1 .. Port3 of cc430 CON4 = spare CON5 = 1: XIN 2: XOUT CON6 = Vdd, GND, Vcore, COM0, LCDCAP CON7 = Vdda1, Vdda2, GND, AGND CON8 = JTAG_BASE (JTAG Port) CON9 = Vdd, GND, AGND (May be addedclose to therespective pins to reduce emissions at 5GHz toel vel required byETSI) EM430F5137RF900 www.ti.com B.33 EM430F5137RF900 Figure B-65. EM430F5137RF900 Target board, Schematic 134 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated JTAG connector External power connector CON12 GND GND VCC Open to disconnect LEDs jumper JP5/JP10 LED D2 (red) connected to P3.6 via JP10 LED D1 (green) connected to P1.0 via JP5 RF - Crystal Q1 26 MHz RF - Signal SMA Reset button S1 Push-button S2 connected to P1.7 Jumper JP1 Close JTAG position to debug in JTAG mode Jumper JP2 Close EXT for external supply Close INT for JTAG supply Close SBW position to debug in Spy-Bi-Wire mode Jumper JP1 Spy-Bi-Wire mode Footprint for 32kHz crystal Use 0 resistor for R431/R441 to make XIN/XOUT available on connector port5 ! Open to measure current jumper JP3 www.ti.com EM430F5137RF900 Figure B-66. EM430F5137RF900 Target board, PCB The battery pack that is included with the EM430F5137RF900 kit may be connected to CON12. Ensure correct battery insertion regarding the polarity as indicated in battery holder. SLAU278R–May 2009–Revised May 2014 Hardware 135 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated EM430F5137RF900 www.ti.com Table B-35. EM430F5137RF900 Bill of Materials Item Reference No. per Description Value Manufacturer's Part Manufacturer Comment Board Number 1 Q1 1 ( CUSTOMER SUPPLY ) CRYSTAL, 26M ASX-531(CS) AKER SMT, 4P, 26MHz ELECTRONIC C1-C5, C082, C222, C271, CAPACITOR, SMT, 0402, CER, 16V, 2 C281, C311, 14 10%, 0.1uF 0.1uF 0402YC104KAT2A AVX C321, C341, C412, C452 3 C071 1 CAPACITOR, SMT, 0603, CERAMIC, 0.47uF 0603YD474KAT2A AVX 0.47uF, 16V, 10%, X5R 4 R401 1 RES0402, 47.0K 47kΩ CRCW04024702F10 DALE 0 5 CON11 1 HEADER, THU, MALE, 14P, 2X7, 09 18 514 6323 HARTING 25.4x9.2x9.45mm 6 CON10 0 HEADER, THU, MALE, 10P, 2X5, 09 18 510 6323 HARTING DNP 20.32x9.2x9.45mm 7 D1 1 LED, SMT, 0603, GREEN, 2.1V active APT1608MGC KINGBRIGHT 8 D2 1 LED, SMT, 0603, RED, 2.0V active APT1608EC KINGBRIGHT 9 Q3 0 UNINSTALLED CRYSTAL, SMT, 3P, 32.768k MS1V-T1K (UN) MICRO DNP MS1V (Customer Supply) CRYSTAL 10 CON12 1 HEADER, THU, MALE, 3P, 1x3, 22-03-5035 MOLEX 9.9x4.9x5.9mm 11 C251, C261 2 50V, 5%, 27pF 27pF GRM36COG270J50 MURATA 12 L341 1 FERRITE, SMT, 0402, 1.0kΩ, 250mA 1kΩ BLM15HG102SN1D MURATA 13 C293 1 CAPACITOR, SMT, 0402, CERAMIC, 100pF GRM1555C1H101JZ MURATA 100pF, 50V, 0.25pF, C0G(NP0) 01 14 L304 1 INDUCTOR, SMT, 0402, 2.2nH, 0.1nH, 0.0022uH LQP15MN2N2B02 MURATA 220mA, 500MHz 15 L303, L305 2 INDUCTOR, SMT, 0402, 15nH, 2%, 0.015uH LQW15AN15NG00 MURATA 450mA, 250MHz 16 L292, L302 2 INDUCTOR, SMT, 0402, 18nH, 2%, 0.018uH LQW15AN18NG00 MURATA 370mA, 250MHz 17 C291 1 CAPACITOR, SMT, 0402, CERAMIC, 1pF GRM1555C1H1R0W MURATA 1pF, 50V, 0.05pF, C0G(NP0) Z01 18 C303 1 CAPACITOR, SMT, 0402, CERAMIC, 8.2pF GRM1555C1H8R2W MURATA 8.2pF, 50V, 0.05pF, C0G(NP0) Z01 19 C292, C301- 4 CAPACITOR, SMT, 0402, CERAMIC, 1.5pF GRM1555C1H1R5W MURATA C302, C304 1.5pF, 50V, 0.05pF, C0G(NP0) Z01 20 L291, L301 2 INDUCTOR, SMT, 0402, 12nH, 2%, 0.012uH LQW15AN12NG00 MURATA 500mA, 250MHz C282, C312, CAPACITOR, SMT, 0402, CERAMIC, GRM1555C1H2R0B 21 C351, C361, 5 2pF, 50V, 0.1pF, C0G 2.0pF Z01 Murata C371 22 L1 1 INDUCTOR, SMT, 0402, 6.2nH, 0.1nH, 6.2nH LQP15MN6N2B02 Murata 130mA, 500MHz 23 S1-S2 2 ULTRA-SMALL TACTILE SWITCH, SMT, B3U-1000P OMRON 2P, SPST-NO, 1.2x3x2.5mm, 0.05A, 12V R4-R5, R051, UNINSTALLED RESISTOR/JUMPER, 24 R061, R431, 0 SMT, 0402, 0 Ω, 5%, 1/16W 0Ω ERJ-2GE0R00X PANASONIC DNP R441 24a R7 1 RESISTOR/JUMPER, SMT, 0402, 0 Ω, 0Ω ERJ-2GE0R00X PANASONIC 5%, 1/16W 25 R2-R3, R6 3 RESISTOR, SMT, 0402, THICK FILM, 330Ω ERJ-2GEJ331 PANASONIC 5%, 1/16W, 330 26 C431, C441 0 CAPACITOR, SMT, 0402, CER, 12pF, 12pF ECJ-0EC1H120J PANASONIC 50V, 5%, NPO 27 C401 1 CAPACITOR, SMT, 0402, CER, 2200pF, 0.0022uF ECJ-0EB1H222K PANASONIC 50V, 10%, X7R 28 R331 1 RESISTOR, SMT, THICK FILM, 56K, 56kΩ ERJ-2GEJ563 PANASONIC 1/16W, 5% 29 C081, C221, 4 CAPACITOR, SMT, 0603, CERAMIC, 10uF ECJ-1VB0J106M PANASONIC C411, C451 10uF, 6.3V, 20%, X5R 136 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com EM430F5137RF900 Table B-35. EM430F5137RF900 Bill of Materials (continued) Item Reference No. per Description Value Manufacturer's Part Manufacturer Comment Board Number 30 R1 1 RESISTOR/JUMPER, SMT, 0402, 0 Ω, 0Ω ERJ-2GE0R00X PANASONIC 5%, 1/16W 31 C041 0 UNINSTALLED CAP CERAMIC 4.7UF 4.7uF ECJ-1VB0J475K Panasonic DNP 6.3V X5R 0603 32 X1 1 SMA STRIGHT JACK, SMT 32K10A-40ML5 ROSENBERGER 33 Q2 0 Crystal, SMT, 32.768 kHz 32.768k MS3V-T1R Micro Crystal DNP 34 U1 1 DUT, SMT, PQFP, RGZ-48, 0.5mmLS, CC430F52x1 TI 7.15x7.15x1mm, THRM.PAD 35 JP1 1 Pin Connector 2x4pin 61300821121 WUERTH 36 CON1-CON9 0 Pin Connector 2x4pin 61300821121 WUERTH DNP 37 JP2 1 Pin Connector 1x3pin 61300311121 WUERTH 38 JP3, JP5, 3 Pin Connector 1x2pin 61300211121 WUERTH JP10 38a JP7, CON13 0 Pin Connector 1x2pin 61300211121 WUERTH DNP 39 JP4 1 Pin Connector 2x2pin 61300421121 WUERTH DNP 40 JP1a 1 Pin Connector 2x3pin 61300621121 WUERTH SLAU278R–May 2009–Revised May 2014 Hardware 137 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Power Management VCC01 = external VCC Vdd = DVCC Vdda1 = AVDD_RF / AVCC_RF Vdda2 = AVCC Port connectors CON1 .. CON5 = Port1 .. Port5 of cc430 CON6 = Vdd, GND, Vcore, COM0, LCDCAP CON7 = Vdda1, Vdda2, GND, AGND CON8 = JTAG_BASE (JTAG Port) CON9 = Vdd, GND, AGND (May beaddedcol se to therespective pins to reduce emissions at 5GHz to el vel required by ETSI) EM430F6137RF900 www.ti.com B.34 EM430F6137RF900 Figure B-67. EM430F6137RF900 Target board, Schematic 138 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated CON12 External power connector Jumper JP2 to "EXT" Jumpers JP5, JP10 Open to disconnect LEDs D2 LED (red) connected to P3.6 via JP10 D1 LED (green) connected to P1.0 via JP5 Crystal Q1 RF - 26 MHz X1 RF - Signal SMA Button S1 Reset Push-button S2 Connected to P1.7 Q2/Q3 Footprint for 32-kHz crystal Jumper JP3 Open to measure current GND GND VCC C392 C422 L451 Jumper JP1 in Spy-Bi-Wire mode Jumper JP2 Close INT for power supply via JTAG interface Close EXT to external power supply (CON12) Jumper JP1 Close SBW position to debug in Spy-Bi-Wire mode Close JTAG position to debug in 4-wire JTAG mode R541 and R551 Use 0- resistor to make P5.0 and P5.1 available on connector Port 5 W Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool www.ti.com EM430F6137RF900 Figure B-68. EM430F6137RF900 Target Board, PCB The battery pack that is included with the EM430F6137RF900 kit may be connected to CON12. Ensure correct battery insertion regarding the polarity as indicated in battery holder. SLAU278R–May 2009–Revised May 2014 Hardware 139 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated EM430F6137RF900 www.ti.com Table B-36. EM430F6137RF900 Bill of Materials No. Pos. Ref Des per Description Part No. Manufacturer Board 1 Q1 1 ( CUSTOMER SUPPLY ) CRYSTAL, SMT, ASX-531(CS) AKER 4P, 26MHz ELECTRONIC C1-C5, C112, C252, C381, CAPACITOR, SMT, 0402, CER, 16V, 10%, 2 C391, C421, 14 0.1uF 0402YC104KAT2A AVX C431, C451, C522, C562 3 C101 1 CAPACITOR, SMT, 0603, CERAMIC, 0.47uF, 0603YD474KAT2A AVX 16V, 10%, X5R 4 R511 1 RES0402, 47.0K CRCW04024702F100 DALE 5 CON11 1 HEADER, THU, MALE, 14P, 2X7, 09 18 514 6323 HARTING 25.4x9.2x9.45mm, 90deg 7 D1 1 LED, SMT, 0603, GREEN, 2.1V APT1608MGC KINGBRIGHT 8 D2 1 LED, SMT, 0603, RED, 2.0V APT1608EC KINGBRIGHT 10 CON12 1 HEADER, THU, MALE, 3P, 1x3, 22-03-5035 MOLEX 9.9x4.9x5.9mm 11 C361, C371 2 50V, ±5%, 27pF GRM36COG270J50 MURATA 12 L451 1 FERRITE, SMT, 0402, 1.0kΩ, 250mA BLM15HG102SN1D MURATA 13 C403 1 CAPACITOR, SMT, 0402, CERAMIC, 100pF, GRM1555C1H101JZ01 MURATA 50V, ±0.25pF, C0G(NP0) 14 L414 1 INDUCTOR, SMT, 0402, 2.2nH, ±0.2nH, LQW15AN2N2C10 MURATA 1000mA, 250MHz 15 L413, L415 2 INDUCTOR, SMT, 0402, 15nH, ±5%, 460mA, LQW15AN15NJ00 MURATA 250MHz 16 L402, L412 2 INDUCTOR, SMT, 0402, 18nH, ±5%, 370mA, LQW15AN18NJ00 MURATA 250MHz 17 C401 1 CAPACITOR, SMT, 0402, CER, 1pF, 50V, GJM1555C1H1R0CB01D MURATA ±0.25pF, NP0 18 C413 1 CAPACITOR, SMT, 0402, CERAMIC, 8.2pF, GRM1555C1H8R2CZ01 MURATA 50V, ±0.25pF, C0G(NP0) 19 C402, C411- 4 CAPACITOR, SMT, 0402, CERAMIC, 1.5pF, GRM1555C1H1R5CZ01 MURATA C412, C414 50V, ±0.25pF, C0G(NP0) 20 L401, L411 2 INDUCTOR, SMT, 0402, 12nH, ±5%, 500mA, LQW15AN12NJ00 MURATA 250MHz 21 C46-C48, 5 CAPACITOR, SMT, 0402, CERAMIC, 2.0pF, GRM1555C1H2R0CZ01 Murata C392, C422 50V, ±0.25pF, C0G(NP0) 22 L1 1 INDUCTOR, SMT, 0402, 6.2nH, ±0.1nH, LQW15AN6N2D00 Murata 700mA, 250MHz 23 S1-S2 2 ULTRA-SMALL TACTILE SWITCH, SMT, 2P, B3U-1000P OMRON SPST-NO, 1.2x3x2.5mm, 0.05A, 12V 24 R7 1 RESISTOR/JUMPER, SMT, 0402, 0 Ω, 5%, ERJ-2GE0R00X (UN) PANASONIC 1/16W 25 R2-R3, R6 3 RESISTOR, SMT, 0402, THICK FILM, 5%, ERJ-2GEJ331 PANASONIC 1/16W, 330 27 C511 1 CAPACITOR, SMT, 0402, CER, 2200pF, ECJ-0EB1H222K PANASONIC 50V, 10%, X7R 28 C111, C251, 4 CAPACITOR, SMT, 0603, CERAMIC, 10uF, ECJ-1VB0J106M PANASONIC C521, C561 6.3V, 20%, X5R 28a C041 1 CAP CERAMIC 4.7UF 6.3V X5R 0603 ECJ-1VB0J475M PANASONIC 29 R441 1 RESISTOR, SMT, THICK FILM, 56K, 1/16W, ERJ-2RKF5602 PANASONIC 1% 30 R1 1 RESISTOR/JUMPER, SMT, 0402, 0 Ω, 5%, ERJ-2GE0R00X PANASONIC 1/16W 31 X1 1 SMA STRIGHT JACK, SMT 32K10A-40ML5 ROSENBERGER 140 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com EM430F6137RF900 Table B-36. EM430F6137RF900 Bill of Materials (continued) No. Pos. Ref Des per Description Part No. Manufacturer Board 33 U1 1 DUT, SMT, PQFP, RGC-64, 0.5mmLS, CC430F6137 TI 9.15x9.15x1mm, THRM.PAD 34 JP1 1 Pin Connector 2x4pin 61300821121 WUERTH 35 JP2 1 Pin Connector 1x3pin 61300311121 WUERTH 36a JP3, JP5, JP10 3 Pin Connector 1x2pin 61300211121 WUERTH 38 JP1a 1 Pin Connector 2x3pin 61300621121 WUERTH SLAU278R–May 2009–Revised May 2014 Hardware 141 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated EM430F6147RF900 www.ti.com B.35 EM430F6147RF900 Figure B-69. EM430F6147RF900 Target Board, Schematic 142 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Orient pin 1 of MSP430 device D1 LED (green) connected to P1.0 via JP5 Jumpers JP5 and JP10 Open to disconnect LEDs D2 LED (red) connected to P3.6 via JP10 Jumpers JP6 and JP8 Close 1-2 for Bypass mode Jumper JP9 Close 2-3 for TPS mode TPS status Connector JTAG For JTAG Tool Connector BOOTST For Bootstrap Loader Tool TPS62730 Jumper JP2 Close INT: Power supply via JTAG interface Close EXT: External power supply Button S2 Connected to P1.7 32-kHz crystal R554 and R551 Use 0- resistor to make P5.0 and P5.1 available on connector Port 5 W Button S1 Reset Jumper JP3 Open to measure current CON12 External poser connector Jumper JP2 to "EXT" Crystal Q1 RF - 26 MHz SMA1 RF - Signal SMA Jumper JP1 Close JTAG position to debug in JTAG mode Close SBW position to debug in Spy-BI-Wire mode www.ti.com EM430F6147RF900 Figure B-70. EM430F6147RF900 Target Board, PCB The battery pack which comes with the EM430F6147RF900 kit may be connected to CON12. Ensure correct battery insertion regarding the polarity as indicated in battery holder. SLAU278R–May 2009–Revised May 2014 Hardware 143 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated EM430F6147RF900 www.ti.com Table B-37. EM430F6147RF900 Bill of Materials No. Pos. Ref Des per Description Part No. Manufacturer Board 1 Q1 1 ( CUSTOMER SUPPLY ) CRYSTAL, SMT, ASX-531(CS) AKER 4P, 26MHz ELECTRONIC C1-5 C112 C252 C381 CAPACITOR, SMT, 0402, CER, 16V, 10%, 2 C391 C421 14 0.1uF 0402YC104KAT2A AVX C431 C451 C522 C562 3 C101 1 CAPACITOR, SMT, 0603, CERAMIC, 0.47uF, 0603YD474KAT2A AVX 16V, 10%, X5R 4 R511 1 RES0402, 47.0K CRCW04024702F100 DALE 5 CON11 1 HEADER, THU, MALE, 14P, 2X7, 09 18 514 6323 HARTING 25.4x9.2x9.45mm, 90deg 7 D1 1 LED, SMT, 0603, GREEN, 2.1V APT1608MGC KINGBRIGHT 8 D2 1 LED, SMT, 0603, RED, 2.0V APT1608EC KINGBRIGHT 10 CON12 1 HEADER, THU, MALE, 3P, 1x3, 22-03-5035 MOLEX 9.9x4.9x5.9mm 11 C361, C371 2 50V, ±5%, 27pF GRM36COG270J50 MURATA 12 L451 1 Inductor, SMD, 0402, 12nH, 5%, 370mA LQW15AN12NJ00 MURATA 13 C403 1 CAPACITOR, SMT, 0402, CERAMIC, 100pF, GRM1555C1H101JZ01 MURATA 50V, ±0.25pF, C0G(NP0) 14 L414 1 INDUCTOR, SMT, 0402, 2.2nH, ±0.2nH, LQW15AN2N2C10 MURATA 1000mA, 250MHz 15 L413 1 Inductor, SMD, 0402, 15nH, 5%, 370mA, LQW15AN15NJ00 MURATA 250MHz 15 L415 1 INDUCTOR,SMT,0402,15nH,±5%,460mA,250 LQW15AN15NJ00 MURATA MHz 16 L402, L412 2 Inductor, SMD, 0402, 18nH, 5%, 460mA, LQW15AN18NJ00 MURATA 250MHz 17 C401 1 CAPACITOR, SMT, 0402, CER, 1pF, 50V, GJM1555C1H1R0CB01D MURATA ±0.25pF, NP0 18 C413 1 CAPACITOR, SMT, 0402, CERAMIC, 8.2pF, GRM1555C1H8R2CZ01 MURATA 50V, ±0.25pF, C0G(NP0) 19 C402, C411- 4 CAPACITOR, SMT, 0402, CERAMIC, 1.5pF, GRM1555C1H1R5CZ01 MURATA C412, C414 50V, ±0.25pF, C0G(NP0) 20 L1, L401, L411 3 INDUCTOR, SMT, 0402, 12nH, ±5%, 500mA, LQW15AN12NJ00 MURATA 250MHz 21 C46-C48, 4 CAPACITOR, SMT, 0402, CERAMIC, 2.0pF, GRM1555C1H2R0CZ01 MURATA C392 50V, ±0.25pF, C0G(NP0) 22 L2 1 Inductor, SMD, 0805, 2.2uH, 20%, 600mA, LQM21PN2R2MC0 MURATA 50MHz 23 S1-S2 2 ULTRA-SMALL TACTILE SWITCH, SMT, 2P, B3U-1000P OMRON SPST-NO, 1.2x3x2.5mm, 0.05A, 12V 24 R1, R7, R551, 4 RESISTOR/JUMPER, SMT, 0402, 0 Ω, 5%, ERJ-2GE0R00X (UN) PANASONIC R554 1/16W 25 R2-R3, R6 3 RESISTOR, SMT, 0402, THICK FILM, 5%, ERJ-2GEJ331 PANASONIC 1/16W, 330 27 C511 1 CAPACITOR, SMT, 0402, CER, 2200pF, ECJ-0EB1H222K PANASONIC 50V, 10%, X7R 28 C111, C251, 4 CAPACITOR, SMT, 0603, CERAMIC, 1uF, ECJ-1VB0J105K PANASONIC C521, C561 6.3V, 20%, X5R 28a C041 1 CAP CERAMIC 4.7UF 6.3V X5R 0603 ECJ-1VB0J475M PANASONIC 29 R441 1 RESISTOR, SMT, THICK FILM, 56K, 1/16W, ERJ-2RKF5602 PANASONIC 1% 30 X1 1 SMA STRIGHT JACK, SMT 32K10A-40ML5 ROSENBERGER 144 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com EM430F6147RF900 Table B-37. EM430F6147RF900 Bill of Materials (continued) No. Pos. Ref Des per Description Part No. Manufacturer Board 31 U1 1 DUT, SMT, PQFP, RGC-64, 0.5mmLS, CC430F6147 TI 9.15x9.15x1mm, THRM.PAD 33 U2 1 IC, Step Down Converter with Bypass Mode TPS62370 TI for Low Power Wireless 34 JP1 1 Pin Connector 2x4pin 61300821121 WUERTH 35 JP2, JP6, JP8 3 Pin Connector 1x3pin 61300311121 WUERTH 36a JP3, JP5, JP9, 4 Pin Connector 1x2pin 61300211121 WUERTH JP10 38 JP1a 1 Pin Connector 2x3pin 61300621121 WUERTH 38 C7 1 Capacitor, Ceramic, 1206, 16V, X5R, 20% GRM31CR61C226ME15L MURATA 38 C8-9 2 CAP, SMD, Ceramic, 0402, 2.2uF, X5R GRM155R60J225ME15D MURATA 38 C041 1 CAP, SMD, Ceramic, 0603, 4.7uF, 16V, 10%, MURATA X5R SLAU278R–May 2009–Revised May 2014 Hardware 145 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-FET www.ti.com B.36 MSP-FET The MSP-FET is a powerful flash emulation tool to quickly begin application development on MSP430 microcontrollers. It includes a USB interface to program and debug the MSP430 in-system through the JTAG interface or the pin-saving Spy-Bi-Wire (2-wire JTAG) protocol. The enclosed MSP-FET development tool supports development with all MSP430 devices and is designed for use in conjunction with PCBs that contain MSP430 devices; for example, the MSP430 target socket boards. B.36.1 Features • USB debugging interface to connect a MSP430 MCU to a PC for real-time in-system programming and debugging • Software configurable supply voltage between 1.8 V and 3.6 V at 100 mA • Supports JTAG Security Fuse blow to protect code • Supports all MSP430 boards with JTAG header • Supports both JTAG and Spy-Bi-Wire (2-wire JTAG) debug protocols B.36.2 Release Notes The MSP-FET is supported by MSP Debug Stack (MSPDS) revision 3.4.0.20 and higher. Observe the following MSPDS-specific MSP-FET limitations. B.36.2.1 MSPDS 3.4.0.20 Limitations • EEM access to F149 and L092 devices is possible only when JTAG speed is set to slow. • Poly Fuse Blow in Spy-Bi-Wire mode is in beta state and is not officially supported. • The UART backchannel function is not implemented (even though an additional COM port is shown on the PC). B.36.2.2 MSPDS UART Backchannel Implementation In MSPDS v3.4.1.0 and later, the UART backchannel function is implemented and supported for the MSPFET. The baud rates that are supported depend on the target configuration and the debug settings. Table B-38 shows which baud rates are supported with certain configuration combinations. A green cell with ✓ means that the corresponding baud rate is supported without any data loss with the specified combination of settings. A red cell with ✗ means that the corresponding baud rate is not supported (data loss is expected) with the specified combination of settings. Table B-38. UART Backchannel Implementation Target MCLK Frequency: 1 MHz 1 MHz 8 MHz 8 MHz 1 MHz 1 MHz 8 MHz 8 MHz Debugger: Active Active Active Active Inactive Inactive Inactive Inactive Flow Control: No Yes No Yes No Yes No Yes 4800 baud ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ 9600 baud ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ 19200 baud ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ 28800 baud ✗ ✓ ✓ ✓ ✓ ✓ ✓ ✓ 38400 baud ✗ ✓ ✗ ✓ ✗ ✓ ✓ ✓ 57200 baud ✗ ✓ ✗ ✓ ✗ ✓ ✗ ✓ 115200 baud ✗ ✗ ✗ ✓ ✗ ✗ ✗ ✓ 146 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-FET Figure B-71. MSP-FET Top View Figure B-72. MSP-FET Bottom View SLAU278R–May 2009–Revised May 2014 Hardware 147 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-FET Rev 1.2 1 3/12/2014 3/12/2014 C 4 A B C D Date E Sheet of F 4 2 1 Title 3 1 A B C D E Size Number F 2 3 Rev 1 A 5 General power supply Additional supply LED USB interface Host MCU DVCC1 DVCC3 DVCC2 AVCC1 Debug i/f USB BSL activation VBUS bypass 1 P6.4/CB4/A4 2 P6.5/CB5/A5 3 P6.6/CB6/A6/DAC0 4 P6.7/CB7/A7/DAC1 5 P7.4/CB8/A12 6 P7.5/CB9/A13 7 P7.6/CB10/A14/DAC0 8 P7.7/CB11/A15/DAC1 9 P5.0/VREF+/VEREF+ 10 P5.1/VREF-/VEREF- 11 AVCC1 12 AVSS1 13 XIN 14 XOUT 15 AVSS2 16 P5.6/ADC12CLK/DMAE0 17 P2.0/P2MAP0 18 P2.1/P2MAP1 19 P2.2/P2MAP2 20 P2.3/P2MAP3 21 P2.4/P2MAP4 22 P2.5/P2MAP5 23 P2.6/P2MAP6/R03 24 P2.7/P2MAP7/LCDREF/ 25 DVCC1 26 DVSS1 27 VCORE(2) 28 P5.2/R23 29 LCDCAP/R33 30 COM0 31 P5.3/COM1/S42 32 P5.4/COM2/S41 33 P5.5/COM3/S40 34 P1.0/TA0CLK/ACLK/S3 35 P1.1/TA0.0/S38 36 P1.2/TA0.1/S37 37 P1.3/TA0.2/S36 38 P1.4/TA0.3/S35 39 P1.5/TA0.4/S34 40 P1.6/TA0.1/S33 41 P1.7/TA0.2/S32 42 P3.0/TA1CLK/CBOUT/S 43 P3.1/TA1.0/S30 44 P3.2/TA1.1/S29 45 P3.3/TA1.2/S28 46 P3.4/TA2CLK/SMCLK/S 47 P3.5/TA2.0/S26 48 P3.6/TA2.1/S25 49 P3.7/TA2.2/S24 50 P4.0/TB0.0/S23 P4.1/TB0.1/S22 51 P4.2/TB0.2/S21 52 P4.3/TB0.3/S20 53 P4.4/TB0.4/S19 54 P4.5/TB0.5/S18 55 P4.6/TB0.6/S17 56 P4.7/TB0OUTH/SVMOUT57 P8.0/TB0CLK/S1558 P8.1/UCB1STE 59 P8.2/UCA1TXD 60 P8.3/UCA1RXD 61 P8.4/UCB1CLK/UCA1ST62 DVSS2 63 DVCC2 64 P8.5/UCB1SIMO 65 P8.6/UCB1SOMI 66 P8.7/S8 67 P9.0/S7 68 P9.1/S6 69 P9.2/S5 70 P9.3/S4 71 P9.4/S3 72 P9.5/S2 73 P9.6/S1 74 P9.7/S0 75 VSSU 76 PU.0/DP 77 PUR 78 PU.1/DM 79 VBUS 80 81 VUSB V18 82 AVSS3 83 P7.2/XT2IN 84 P7.3/XT2OUT 85 VBAK 86 87 VBAT P5.7/RTCCLK 88 DVCC3 89 DVSS3 90 TEST/SBWTCK 91 PJ.0/TDO 92 93 PJ.1/TDI/TCLK PJ.2/TMS 94 PJ.3/TCK 95 RST/NMI/SBWTDIO96 P6.0/CB0/A0 97 P6.1/CB1/A1 98 99 P6.2/CB2/A2 100 P6.3/CB3/A3 U1 MSP430F6638IPZR C6 100n + C5 10uF/6.3V C7 100n C9 100n C11 100n 0R R1 C15 68p C16 470n C17 220n C18 4.7n D1 D2 R47 470R 0R R50 1 IO1 2 IO2 3 GND IO3 4 IO4 5 VCC 6 U5 TPD4E004DRYR 1k4 R2 C14 4.7u, dnp C23 100n 33k R60 C31 10p C33 10p R61 1M R62 100R J5 C8 220n 3 1 2 P1 0R R17 A C D7 B0530W-7-F R76 27k C70 4.7u, dnp C71 100n R85 0R, dnp C55 1n R3 27R R45 27R R46 470R + C12 10uF/6.3V 1 2 3 4 5 6 7 11 10 J1 R28 4k7 R30 4k7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCC_DT_REF VCC_DCDC_REF VCC_DT2TRGT_CTRL VCC_SUPPLY2TRGT_CTRL LED1 TDIOFF_CTRL PWM_SETVF FPGA_TCK FPGA_TDI FPGA_TMS FPGA_TDO FPGA_TRST VF2TEST_CTRL VF2TDI_CTRL AVCC_POD VCC_POD33 VCC_POD33 VCC_POD33 VREF+ VCORE VBAK MCU_DMAE0 DCDC_PULSE MCU_P2.2 MCU_P2.3 MCU_P2.4 MCU_P2.5 MCU_P2.6 MCU_P2.7 MCU_P1.0 MCU_P1.1 MCU_P1.2 MCU_P1.3 MCU_P1.4 MCU_P1.5 MCU_P1.6 MCU_P1.7 MCU_P3.0 MCU_P3.1 MCU_P3.2 MCU_P3.3 MCU_P3.4 MCU_P3.5 MCU_P3.6 MCU_P3.7 MCU_P4.0 MCU_P4.1 MCU_P4.2 MCU_P4.3 MCU_P4.4 MCU_P4.5 MCU_P4.6 MCU_P4.7 MCU_P8.1 MCU_P8.2 MCU_P8.3 PUR PU.1/DM PU.0/DP VBUS VUSB AVCC_POD VCC_POD33 VCC_POD33 VCC_POD33 AVCC_POD VCC_POD33 VREF+ VCORE V18 V18 VBAK HOST_TEST HOST_RST FPGA_RESET LED0 LED1 PUR VUSB PU.1/DM PU.0/DP DCDC_RST HOST_SCL HOST_SDA DCDC_IO0 LED0 A_VBUS5 VBUS A_VCC_SUPPLY_HOST DCDC_TEST A_VF MCU_P9.5 DCDC_IO1 HOST_TCK HOST_TMS HOST_TDI HOST_TDO VCC_POD33 HOST_RST VCC_POD33 GND1 VBUS5 MCU_P2.1 GND1 GND1 VCC_DT2SUPPLY_CTRL A_VCC_DT A_VCC_DT_BSR A_VCC_SENSE0_TRGT VCC_POD33 VCC_DT_SENSE MSP-FET www.ti.com B.36.3 Schematics Figure B-73. MSP-FET USB Debugger, Schematic (1 of 5) 148 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-FET Rev 1.2 3/12/2014 5 1 A 2 Rev 3 2 F Size Number A B C D E 1 3 Title 1 2 4 F Sheet of E Date A B C D 4 C 3/12/2014 VCC_PUMP VCC_JTAG FPGA 1 GND 2 GAA2/IO51RSB1 3 IO52RSB1 4 GAB2/IO53RSB1 5 IO95RSB1 6 GAC2/IO94RSB1 7 IO93RSB1 8 IO92RSB1 9 GND 10 GFB1/IO87RSB1 11 GFB0/IO86RSB1 12 VCOMPLF 13 GFA0/IO85RSB1 14 VCCPLF 15 GFA1/IO84RSB1 16 GFA2/IO83RSB1 17 VCC 18 VCCIB1 19 GEC1/IO77RSB1 20 GEB1/IO75RSB1 21 GEB0/IO74RSB1 22 GEA1/IO73RSB1 23 GEA0/IO72RSB1 24 VMV1 25 GNDQ 26 GEA2/IO71RSB1 27 FF/GEB2/IO70RSB1 28 GEC2/IO69RSB1 29 IO68RSB1 30 IO67RSB1 31 IO66RSB1 32 IO65RSB1 33 IO64RSB1 34 IO63RSB1 35 IO62RSB1 36 IO61RSB1 37 VCC 38 GND 39 VCCIB1 40 IO60RSB1 41 IO59RSB1 42 IO58RSB1 43 IO57RSB1 44 GDC2/IO56RSB1 45 GDB2/IO55RSB1 46 GDA2/IO54RSB1 47 TCK 48 TDI 49 TMS 50 VMV1 GND 51 VPUMP 52 NC 53 TDO 54 TRST 55 VJTAG 56 GDA1/IO49RSB057 GDC0/IO46RSB058 GDC1/IO45RSB059 GCC2/IO43RSB060 GCB2/IO42RSB061 GCA0/IO40RSB062 GCA1/IO39RSB063 GCC0/IO36RSB064 GCC1/IO35RSB065 VCCIB0 66 GND 67 VCC 68 IO31RSB0 69 GBC2/IO29RSB070 GBB2/IO27RSB071 IO26RSB0 72 GBA2/IO25RSB073 VMV0 74 GNDQ 75 GBA1/IO24RSB076 GBA0/IO23RSB077 GBB1/IO22RSB078 GBB0/IO21RSB079 GBC1/IO20RSB080 81 GBC0/IO19RSB0 IO18RSB0 82 IO17RSB0 83 IO15RSB0 84 IO13RSB0 85 IO11RSB0 86 87 VCCIB0 GND 88 VCC 89 IO10RSB0 90 IO09RSB0 91 IO08RSB0 92 93 GAC1/IO07RSB0 GAC0/IO06RSB094 GAB1/IO05RSB095 GAB0/IO04RSB096 GAA1/IO03RSB097 GAA0/IO02RSB098 99 IO01RSB0 100 IO00RSB0 U2 A3PN125-VQG100 R4 1k R5 1k 1 2 L3 33n + C19 10uF/6.3V C20 100n C21 10n C22 100n C34 10n C35 100n C36 10n C37 100n C38 10n C39 100n C40 10n C41 100n C42 10n C43 100n C44 10n C45 100n C46 10n C47 100n C48 10n C49 100n C50 10n C51 100n C52 10n R44 27R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCC_PLF VCC_POD15 VCC_POD15 VCC_POD15 VCC_POD15 VCC_POD33 VCC_POD33 VCC_POD33 VCC_POD33 VCC_POD33 VCC_POD33 VCC_POD33 VCC_POD33 VCC_POD33 FPGA_TCK FPGA_TDI FPGA_TMS FPGA_TRST MCU_DMAE0 MCU_P2.2 MCU_P2.3 MCU_P2.4 MCU_P2.5 MCU_P2.6 MCU_P1.0 MCU_P1.1 MCU_P1.2 MCU_P1.3 MCU_P1.4 MCU_P1.5 MCU_P1.6 MCU_P1.7 MCU_P3.0 MCU_P3.1 MCU_P3.2 MCU_P3.3 MCU_P3.4 MCU_P3.5 MCU_P3.6 MCU_P3.7 MCU_P4.0 MCU_P4.1 MCU_P4.2 MCU_P4.3 MCU_P4.4 MCU_P4.5 MCU_P4.6 MCU_P4.7 MCU_P8.1 MCU_P8.2 MCU_P8.3 FPGA_IO_TCK FPGA_DIR_CTRL_TCK FPGA_IO_TMS FPGA_DIR_CTRL_TMS FPGA_IO_TDI FPGA_DIR_CTRL_TDI FPGA_IO_TDO FPGA_DIR_CTRL_TDO MCU_P2.7 FPGA_DIR_CTRL_RST FPGA_IO_TEST FPGA_DIR_CTRL_TEST FPGA_IO_UART_TXD FPGA_DIR_CTRL_UART_TXD FPGA_IO_UART_RXD FPGA_DIR_CTRL_UART_RXD FPGA_IO_UART_CTS FPGA_DIR_CTRL_UART_CTS FPGA_IO_UART_RTS FPGA_DIR_CTRL_UART_RTS FPGA_TDO FPGA_RESET VCC_POD15 VCC_POD15 VCC_POD33 VCC_PLF VCC_POD33 VCC_POD33 FPGA_IO_RST FPGA_TP0 FPGA_TP1 FPGA_TP2 MCU_P9.5 MCU_P2.1 www.ti.com MSP-FET Figure B-74. MSP-FET USB Debugger, Schematic (2 of 5) SLAU278R–May 2009–Revised May 2014 Hardware 149 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated 3/12/2014 3/12/2014 C 4 A B C D Date E Sheet of F 4 2 1 3 1 A B C D E Size Number F 2 3 Rev 3 A 1 5 S/W controlled DCDC converter DCDC MCU reference voltage DT level shifter supply DCDC calibration switch DCDC MCU DCDC MCU debug i/f DT current measurement shunt DT current sense MSP-FET Rev 1.2 Energy measurement method protected under U.S. Patent Application 13/329,073 and subsequent patent applications 1 DVCC 2 P1.0/TA0CLK 3 P1.1/TA0.0 4 P1.2/TA0.1 5 P1.3/ADC10CLK 6 P1.4/TA0.2 7 P1.5/TA0.0 P1.6/TA0.1 8 P1.7/SDI 9 NMI-RST 10 TEST/SBWTCK 11 XOUT/P2.7 12 XIN/P2.6 13 DVSS 14 U4 MSP430G2452PW MSP430G2452PW 1 2 L4 R53 R55 R56 R64 1 2 3 D4 R65 220k C28 33p R63 C53 100n 1 NO1 2 COM1 3 NO2 4 COM2 5 IN2 6 IN3 7 GND NO3 8 COM3 9 COM4 10 NO4 11 IN4 12 IN1 13 V+ 14 U20 TS3A4751PWR TS3A4751PWR C13 1n, dnp C56 4.7u + C57 2.2u C63 100n R19 1 A1 2 A2 C1,C2 3 D8 C66 1n 0R R20 R23180k R25150k R15 220k 1 G 2 S 3 D Q3 R26 27k, dnp 1 IN 2 GND 3 EN NR 4 OUT 5 U7 TPS73401DDCT C54 1n C26 2.2u R24160k C24 1n C62 10n C29 4.7u C10 1u 2E B1 C 3 Q4 R6 220k C1 33p R7 220k C65 100n 5 IN- 4 IN+ 6 OUT 1 REF 2 GND 3 V+ U10 INA21XDCK INA214AIDCKT C67 10p C68 1n 10R R49 10R R54 R57 0.2 C69 2.2u C72 2.2u C73 2.2u 1 1 DCDC_CAL0 DCDC_CAL2 DCDC_TEST DCDC_RST HOST_SDA DCDC_CAL1 VCC_POD33 DCDC_PULSE DCDC_IO0 VCC_DCDC_REF A_VCC_SUPPLY VBUS5 VCC_SUPPLY A_VCC_SUPPLY DCDC_CAL0 VCC_SUPPLY VCC_DT DCDC_CAL1 DCDC_CAL2 DCDC_RST VCC_POD33 GND1 GND1 GND1 GND1 GND1 VBUS GND1 GND1 GND1 DCDCGND GND1 DCDCGND DCDCGND DCDCGND DCDCGND DCDCGND GND1 VCC_SUPPLY GND1 GND1 VCC_DT_REF GND1 DCDC_IO1 VCC_DT HOST_SCL VCC_DT_BSR VCC_SUPPLY A_VCC_SUPPLY_HOST VCC_SUPPLY VCC_POD33 VCC_DT_SENSE VCC_DT VCC_DT_BSR GND1 GND1 GND1 MSP-FET www.ti.com Figure B-75. MSP-FET USB Debugger, Schematic (3 of 5) 150 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated 3/12/2014 5 1 A 4 Rev 3 2 F Size Number A B C D E 1 3 1 2 4 F Sheet of E Date A B C D 4 C 3/12/2014 VF = +5V ... 6.5V Fuse blow step-up converter Fuse voltage multiplexer / VCC_DT to level shifters ESD protection Target MCU connector DT level shifters MSP-FET Rev 1.2 S1 D1 IN2 GND S2 D2 IN1 VDD U6 ADG821BRMZ-REEL7 D5 dnp MMSZ5232B-7-F R13 100R R14 2k2 S1 D1 IN2 GND S2 D2 IN1 VDD U9 ADG821BRMZ-REEL7 L2 33u C30 330n E B C Q1 BC817-16LT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 J6 R35 100R 1 IO1 2 IO2 3 IO3 4 IO4 IO5 5 IO6 6 IO7 7 IO8 8 9 GND U3 TPD8E003DQD TPD8E003DQDR 1 IO1 2 IO2 3 IO3 4 IO4 IO5 5 IO6 6 IO7 7 IO8 8 9 GND U21 TPD8E003DQD TPD8E003DQDR R22 47k R29 47k R42 1k D3 dnp DDZ9692-7 1 VCCA 2 GND 3 A B 4 DIR 5 VCCB 6 U12 SN74LVC1T45DCKR 1 VCCA 2 GND 3 A B 4 DIR 5 VCCB 6 U13 SN74LVC1T45DCKR 1 VCCA 2 GND 3 A B 4 DIR 5 VCCB 6 U14 SN74LVC1T45DCKR 1 VCCA 2 GND 3 A B 4 DIR 5 VCCB 6 U15 SN74LVC1T45DCKR 1 VCCA 2 GND 3 A B 4 DIR 5 VCCB 6 U16 SN74LVC1T45DCKR 1 VCCA 2 GND 3 A B 4 DIR 5 VCCB 6 U17 SN74LVC1T45DCKR 1 VCCA 2 GND 3 A B 4 DIR 5 VCCB 6 U22 SN74LVC1T45DCKR 1 VCCA 2 GND 3 A B 4 DIR 5 VCCB 6 U26 SN74LVC1T45DCKR 1 VCCA 2 GND 3 A B 4 DIR 5 VCCB 6 U27 SN74LVC1T45DCKR 1 VCCA 2 GND 3 A B 4 DIR 5 VCCB 6 U28 SN74LVC1T45DCKR R27 47k R31 47k R84 47k, dnp R86 47k R87 47k R88 47k R89 47k R90 47k R91 47k R92 47k R93 47k R94 47k R95 47k R96 47k R97 47k R98 47k R99 47k R100 47k R101 47k R102 47k C77 100n C78 100n C79 100n C80 100n C82 100n C83 100n C84 100n C85 100n R32 100R R33 100R R34 100R R37 100R R38 100R R39 100R R40 100R R41 100R R43 100R A C D10 B0530W-7-F A C D6 DNP B0530W-7-F + C74 100u/10V R48 47k R58 47k R59 47k 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VF VF2TDI_CTRL VF VF2TEST_CTRL TDIOFF_CTRL VF TC_TDI_FD VF_TDI VBUS VF TC_TEST_FD VF_TEST TC_TEST_BSR TC_TDI_BSR TC_TDO_FD VCC_SENSE0_TRGT TC_TMS_FD TC_TCK_FD TC_UART_CTS_FD TC_RST_FD TC_UART_TXD_FD TC_UART_RTS_FD TC_UART_RXD_FD VCC_SUPPLY_TRGT TC_TDI_BSR TC_TEST_BSR VCC_SUPPLY_TRGT TC_TDO_FD TC_TCK_FD TC_TEST_BSR VCC_SENSE0_TRGT TC_TMS_FD TC_TDI_BSR TC_UART_CTS_FD TC_UART_RTS_FD TC_UART_RXD_FD TC_RST_FD TC_UART_TXD_FD VCC_JTAGLDO_TRGT VCC_JTAGLDO_TRGT VCC_DT2TRGT_CTRL VCC_DT_TRGT VCC_DT GND1 PWM_SETVF VCC_POD33 FPGA_IO_TCK FPGA_DIR_CTRL_TCK TC_TCK_FD VCC_DT_TRGT VCC_DT_TRGT VCC_POD33 FPGA_IO_TMS FPGA_DIR_CTRL_TMS TC_TMS_FD VCC_DT_TRGT VCC_DT_TRGT VCC_POD33 FPGA_IO_TDI FPGA_DIR_CTRL_TDI TC_TDI_FD VCC_DT_TRGT VCC_DT_TRGT VCC_POD33 FPGA_IO_TDO FPGA_DIR_CTRL_TDO TC_TDO_FD VCC_DT_TRGT VCC_DT_TRGT VCC_POD33 FPGA_IO_RST FPGA_DIR_CTRL_RST TC_RST_FD VCC_DT_TRGT VCC_DT_TRGT VCC_POD33 FPGA_IO_TEST FPGA_DIR_CTRL_TEST TC_TEST_FD VCC_DT_TRGT VCC_DT_TRGT VCC_POD33 FPGA_IO_UART_TXD FPGA_DIR_CTRL_UART_TXD TC_UART_TXD_FD VCC_DT_TRGT VCC_DT_TRGT VCC_POD33 FPGA_IO_UART_RXD FPGA_DIR_CTRL_UART_RXD TC_UART_RXD_FD VCC_DT_TRGT VCC_DT_TRGT VCC_POD33 FPGA_IO_UART_CTS FPGA_DIR_CTRL_UART_CTS TC_UART_CTS_FD VCC_DT_TRGT VCC_DT_TRGT VCC_POD33 FPGA_IO_UART_RTS FPGA_DIR_CTRL_UART_RTS TC_UART_RTS_FD VCC_DT_TRGT VCC_DT_TRGT VCC_POD33 GND1 VCC_DT_TRGT GND1 GND1 GND1 GND1 GND1 GND1 GND1 GND1 GND1 GND1 GND1 GND1 GND1 GND1 GND1 GND1 VCC_POD33 GND1 GND1 VF_TDI VF_TEST www.ti.com MSP-FET Figure B-76. MSP-FET USB Debugger, Schematic (4 of 5) SLAU278R–May 2009–Revised May 2014 Hardware 151 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated 3/12/2014 3/12/2014 C 4 A B C D Date E Sheet of F 4 2 1 3 1 A B C D E Size Number F 2 3 Rev 5 A 1 5 MSP-FET power supply Target power switch Analog inputs to Host MCU Test points Common debug and test i/f MSP-FET Rev 1.2 R80R R11 150k C3 33p R51 240k R52 150k C27 33p R12 270k R36 150k C4 33p TP3 TP0 TP4 TP5 TP6 TP1 TP2 R10 150k R21 47k 1 2 3 4 5 6 7 8 J4 HEADER_1X8_50MIL_A 1 2 3 4 5 6 7 8 J2 HEADER_1X8_50MIL_A 1 2 3 4 5 6 7 8 J3 HEADER_1X8_50MIL_A C32 33p R78 150k R79 150k TP7 TP9 TP8 TP11 R16 47k 1 NO1 2 V+ 3 IN1 4 COM2 NO2 5 GND 6 IN2 7 COM1 8 U18 TS5A21366RSE TS5A21366RSER 1 EN1 2 IN 3 EN2 GND 4 OUT2 5 OUT1 6 U19 TLV7111533D C25 10n C58 1u C59 1u C61 1u C2 33p R9 150k R18 150k 1 1 1 1 1 1 VCC_SENSE0_TRGT A_VCC_SENSE0_TRGT VBUS5 A_VBUS5 VF A_VF DCDC_PULSE VCC_SUPPLY FPGA_TP0 FPGA_TP1 FPGA_TP2 VBUS GND1 VBUS HOST_TEST HOST_TDO HOST_TDI HOST_TMS HOST_TCK HOST_RST DCDC_RST DCDC_TEST VCC_POD33 FPGA_TRST FPGA_TCK FPGA_TMS FPGA_TDI FPGA_TDO GND1 GND1 A_VCC_SUPPLY_HOST VCC_POD15 VBUS5 VCC_DT A_VCC_DT GND1 DCDC_IO0 DCDC_IO1 VCC_DT HOST_SCL HOST_SDA VCC_SUPPLY_TRGT VCC_SUPPLY_TRGT VBUS VCC_SUPPLY2TRGT_CTRL VCC_SUPPLY VCC_DT VCC_DT2SUPPLY_CTRL GND1 GND1 GND1 VCC_POD15 VBUS VCC_POD33 PWRGND PWRGND PWRGND PWRGND PWRGND VCC_DT_BSR A_VCC_DT_BSR MSP-FET www.ti.com Figure B-77. MSP-FET USB Debugger, Schematic (5 of 5) 152 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-FET B.36.4 Layout Figure B-78. MSP-FET USB Debugger, PCB (Top) Figure B-79. MSP-FET USB Debugger, PCB (Bottom) B.36.5 LED Signals The MSP-FET shows its operating states using two LEDs, one green and one red. Table B-39 lists all available operation modes. An or icon indicates that the LED is off, an or icon indicates that the LED is on, and an or icon indicates that the LED flashes. Table B-39. MSP-FET LED Signals Function Power LED Mode LED MSP-FET not connected to PC, or MSP-FET not ready; for example, after a major firmware update. Connect or reconnect MSP-FET to PC. MSP-FET connected and ready MSP-FET waiting for data transfer Ongoing data transfer An error has occurred; for example, target VCC overcurrent. Unplug MSP-FET from target, and cycle the power off and on. Check target connection, and reconnect MSP-FET. Firmware update in progress. Do not disconnect MSP-FET while both LEDs are blinking. SLAU278R–May 2009–Revised May 2014 Hardware 153 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-FET www.ti.com B.36.6 JTAG Target Connector Figure B-80 shows the pinout of the JTAG connector. Figure B-80. JTAG Connector Pinout Table B-40. JTAG Connector Pin State by Operating Mode Pin Name After Power-Up When JTAG Protocol is When Spy-Bi-Wire Protocol Selected is Selected 1 TDO/TDI Hi-Z, pulled up to 3.3 V In, TDO In and Out, SBWTDIO 2 VCC_TOOL 3.3 V VCC VCC 3 TDI/VPP Hi-Z, pulled up to 3.3 V Out, TDI Hi-Z, pulled up to VCC 4 VCC_TARGET In, external VCC sense In, external VCC sense In, external VCC sense 5 TMS Hi-Z, pulled up to 3.3 V Out, TMS Hi-Z, pulled up to VCC 6 N/C N/C N/C N/C 7 TCK Hi-Z, pulled up to 3.3 V Out, TCK Out, SBWTCK 8 TEST/VPP Out, Gnd Out, TEST Hi-Z, pulled up to VCC 9 GND Ground Ground Ground 10 UART_CTS/SPI_CLK/I2C_SCL Hi-Z, pulled up to 3.3 V Out, Target UART Clear-To- Out, Target UART Clear-To- Send Handshake input Send Handshake input 11 RST Out, VCC Out, RST Out 12 UART_TXD/SPI_SOMI/I2C_SDA Hi-Z, pulled up to 3.3 V In, Target UART TXD output In, Target UART TXD output 13 UART_RTS Hi-Z, pulled up to 3.3 V In, Target UART Ready-to- In, Target UART Ready-to- Send Handshake output Send Handshake output 14 UART_RXD/SPI_SIMO Hi-Z, pulled up to 3.3 V Out, Target UART RXD input Out, Target UART RXD input 154 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated 12 UART_TXD 11 RST 8 TEST 7 TCK 5 TMS 3 TDI 1 TDO/TDI 2 VCC_TOOL - USB Power 10 UART_CTS 14 UART_RXD 13 UART_RTS Pin Signal www.ti.com MSP-FET Figure B-81 shows the state of each pin in the connector after power-up. Figure B-81. Pin States After Power-Up SLAU278R–May 2009–Revised May 2014 Hardware 155 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-FET www.ti.com B.36.7 Specifications Table B-41 shows the physical and electrical specifications of the MSP-FET. Table B-41. Specifications Mechanical Size (without cables) 80 mm x 50 mm x 20 mm Interfaces USB interface USB 2.0, full speed Target interface JTAG 14-pin See Table B-40 for pinout JTAG cable length 20 cm (max) JTAG and Spy-Bi-Wire Interface, Electrical Power supply USB powered, 200 mA (max) Target output voltage 1.8 V to 3.6 V Selectable in 0.1-V steps. VCC_TOOL available from JTAG pin 2. VCC_TOOL Target output current 100 mA (max) Current supplied through JTAG pin 2 Target output overcurrent 160 mA (max) detection level JTAG signal overcurrent 30 mA (max) Total current supplied through JTAG pins 1, 3, 5, 7, 8, 10, 11, 12, 13, 14 detection level External target supply Supported (1.8 V to 3.6 V) Connect external target voltage VCC_TARGET to JTAG pin 4. JTAG and SBW signals are regulated to external target voltage ±100 mV. Fuse blow Supported For devices with poly-fuse JTAG and Spy-Bi-Wire Interface, Timing JTAG clock speed 8 MHz (max) Protocol speed selectable by software Spy‑Bi‑Wire clock speed 8 MHz (max) Protocol speed selectable by software. System limitations due to external RC components on reset pin (SBWTDIO) might apply. JTAG and Spy-Bi-Wire Interface, Speed Flash write speed (JTAG) Up to 20 kB/sec Flash write speed Up to 7 kB/sec (Spy‑Bi‑Wire) FRAM write speed (JTAG) Up to 50 kB/sec FRAM write speed Up to 14 kB/sec (Spy‑Bi‑Wire) EnergyTrace™ Technology Target output current ± 2%, ± 500 nA For target output voltage = 1.8 V to 3.6 V, target output current <75 mA accuracy and USB voltage = 5 V constant during and after calibration B.36.8 MSP-FET Revision History Revision numbers are printed on the PCB and are stored in nonvolatile memory in firmware. Table B-42 shows the revision history of the MSP-FET. Table B-42. MSP-FET Revision History Revision Date Comments Revision 1.2 March 2014 Initial release 156 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-FET430PIF B.37 MSP-FET430PIF Figure B-82. MSP-FET430PIF FET Interface Module, Schematic SLAU278R–May 2009–Revised May 2014 Hardware 157 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-FET430PIF www.ti.com Figure B-83. MSP-FET430PIF FET Interface Module, PCB 158 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-FET430UIF B.38 MSP-FET430UIF Figure B-84. MSP-FET430UIF USB Interface, Schematic (1 of 4) SLAU278R–May 2009–Revised May 2014 Hardware 159 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-FET430UIF www.ti.com Figure B-85. MSP-FET430UIF USB Interface, Schematic (2 of 4) 160 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-FET430UIF Figure B-86. MSP-FET430UIF USB Interface, Schematic (3 of 4) SLAU278R–May 2009–Revised May 2014 Hardware 161 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-FET430UIF www.ti.com Figure B-87. MSP-FET430UIF USB Interface, Schematic (4 of 4) 162 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com MSP-FET430UIF Figure B-88. MSP-FET430UIF USB Interface, PCB SLAU278R–May 2009–Revised May 2014 Hardware 163 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated MSP-FET430UIF www.ti.com B.38.1 MSP-FET430UIF Revision History Revision 1.3 • Initial released hardware version Assembly change on 1.3 (May 2005) • R29, R51, R42, R21, R22, R74: value changed from 330R to 100R Changes 1.3 to 1.4 (Aug 2005) • J5: VBUS and RESET additionally connected • R29, R51, R42, R21, R22, R74: value changed from 330R to 100R • U1, U7: F1612 can reset TUSB3410; R44 = 0R added • TARGET-CON.: pins 6, 10, 12, 13, 14 disconnected from GND • Firmware-upgrade option through BSL: R49, R52, R53, R54 added; R49, R52 are currently DNP • Pullups on TCK and TMS: R78, R79 added • U2: Changed from SN74LVC1G125DBV to SN74LVC1G07DBV NOTE: Using a locally powered target board with hardware revision 1.4 Using an MSP-FET430UIF interface hardware revision 1.4 with populated R62 in conjunction with a locally powered target board is not possible. In this case, the target device RESET signal is pulled down by the FET tool. It is recommended to remove R62 to eliminate this restriction. This component is located close to the 14-pin connector on the MSP-FET430UIF PCB. See the schematic and PCB drawings in this document for the exact location of this component. Assembly change on 1.4a (January 2006) • R62: not populated 164 Hardware SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Appendix C SLAU278R–May 2009–Revised May 2014 Hardware Installation Guide This section describes the hardware installation process of the following USB debug interfaces on a PC running Windows XP: • MSP-FET430UIF • eZ430-F2013 • eZ430-RF2500 • eZ430-Chronos • eZ430-RF2780 • eZ430-RF2560 • MSP-WDSxx "Metawatch" • LaunchPad (MSP-EXP430G2) • MSP-EXP430FR5739 • MSP-EXP430F5529 The installation procedure for other supported versions of Windows is very similar and, therefore, not shown here. Topic ........................................................................................................................... Page C.1 Hardware Installation ........................................................................................ 166 SLAU278R–May 2009–Revised May 2014 Hardware Installation Guide 165 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Hardware Installation www.ti.com C.1 Hardware Installation Table C-1 shows the USB VIDs and PIDs used in MSP430 tools. Table C-1. USB VIDs and PIDs Used in MSP430 Tools Tool USB VID USB PID INF File Name eZ430-F2013 0x0451 0xF430 usbuart3410.inf eZ430-RF2500 0x0451 0xF432 430CDC.inf eZ430-RF2780 0x0451 0xF432 430CDC.inf eZ430-RF2560 0x0451 0xF432 430CDC.inf MSP-WDSxx "Metawatch" 0x0451 0xF432 430CDC.inf eZ430-Chronos 0x0451 0xF432 430CDC.inf MSP-FET430UIF(1) 0x2047 0x0010 msp430tools.inf MSP-FET 0x2047 0x0204 msp430tools.inf eZ-FET 0x2047 0x0203 msp430tools.inf LaunchPad (MSP-EXP430G2) 0x0451 0xF432 430CDC.inf MSP-EXP430FR5739 0x0451 0xF432 430CDC.inf MSP-EXP430F5529 0x0451 0xF432 430CDC.inf (1) The older MSP-FET430UIF used with IAR versions before v5.20.x and CCS versions before v5.1 has VID 0x0451 and PID 0xF430. With the firmware update, it is updated to the 0x2047 and 0x0010, respectively. 1. Before connecting of the USB Debug Interface with a USB cable to a USB port of the PC the one of IDEs (CCS or IAR) should be installed. The IDE installation isntalls also drivers for USB Debug Interfaces without user interaction. After IDE installation the USB Debug Interface can be connected and will be ready to work within few seconds. 2. The driver can be also installed manually. After plug in the USB Debug Interface to USB port of the PC the Hardware Wizard starts automatically and opens the "Found New Hardware Wizard" window. 3. Select "Install from a list or specific location (Advanced)" (see Figure C-1). Figure C-1. Windows XP Hardware Wizard 166 Hardware Installation Guide SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com Hardware Installation 4. Browse to the folder where the driver information files are located (see Figure C-2). For CCS, the default folder is: c:\ti\ccsv5\ccs_base\emulation\drivers\msp430\USB_CDC, or c:\ti\ccsv5\ccs_base\emulation\drivers\msp430\USB_FET_XP_XX, or c:\ti\ccsv5\ccs_base\emulation\drivers\msp430\USB_eZ-RF depending of firmware version of the tool. For IAR Embedded Workbench, the default folder is: \Embedded Workbench x.x\430\drivers\TIUSBFET\eZ430-UART, or \Embedded Workbench x.x\430\drivers\. Figure C-2. Windows XP Driver Location Selection Folder 5. The Wizard generates a message that an appropriate driver has been found. SLAU278R–May 2009–Revised May 2014 Hardware Installation Guide 167 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Hardware Installation www.ti.com 6. The wizard installs the driver files. 7. The wizard shows a message that it has finished the installation of the software USB Debug Interface. 8. The USB debug interface is installed and ready to use. The Device Manager lists a new entry as shown in Figure C-3, Figure C-4, or Figure C-5. Figure C-3. Device Manager Using USB Debug Interface using VID/PID 0x2047/0x0010 168 Hardware Installation Guide SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com Hardware Installation Figure C-4. Device Manager Using USB Debug Interface with VID/PID 0x0451/0xF430 SLAU278R–May 2009–Revised May 2014 Hardware Installation Guide 169 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Hardware Installation www.ti.com Figure C-5. Device Manager Using USB Debug Interface With VID/PID 0x0451/0xF432 170 Hardware Installation Guide SLAU278R–May 2009–Revised May 2014 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated www.ti.com Revision History Revision History Changes from Q Revision (January 2014) to R Revision ............................................................................................... Page • In Table 1-1, added support for "BT5190, F5438A" to "eZ430-RF2560" column ............................................... 12 • Added Section 1.10...................................................................................................................... 14 • Added MSP-TS430RHB32A to Table 1-2 ............................................................................................ 15 • Added MSP-TS430PZ100D to Table 1-2............................................................................................. 16 • Added Section 1.17...................................................................................................................... 18 • Updated descriptive labels on all PCB figures in Appendix B ..................................................................... 31 • In Table B-1, updated Description for Position 13................................................................................... 35 • Added Section B.9 MSP-TS430RHB32A............................................................................................. 57 • In Table B-18, updated Description of Pos 20.1 and Comment of Pos 15. ...................................................... 80 • In Table B-28, corrected the device in the Description column for Pos. 22 .................................................... 113 • Added Section B.29 MSP-TS430PZ100D .......................................................................................... 121 • In Table B-33, corrected the device in the Description column for Pos. 22 .................................................... 129 • Added Section B.36 and all of its subsections ..................................................................................... 146 • Added rows for MSP-FET and eZ-FET to Table C-1.............................................................................. 166 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. SLAU278R–May 2009–Revised May 2014 Revision History 171 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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Hardware User Guide AT90USBKey Hardware User Guide User Guide 1 7627A–AVR–04/06 Section 1 Introduction ........................................................................................... 1-3 1.1 Overview ...................................................................................................1-3 1.2 AT90USBKey Features............................................................................1-4 Section 2 Using the AT90USBKey ....................................................................... 2-5 2.1 Overview ...................................................................................................2-5 2.2 Power Supply ............................................................................................2-6 2.3 Reset.........................................................................................................2-8 2.4 On-board Resources.................................................................................2-9 2.5 In-System Programming .........................................................................2-13 2.6 Debugging...............................................................................................2-14 Section 3 Troubleshooting Guide ....................................................................... 3-15 Section 4 Technical Specifications ..................................................................... 4-16 Section 5 Technical Support............................................................................... 5-17 Section 6 Complete Schematics......................................................................... 6-18 AT90USBKey Hardware User Guide 1-3 7627A–AVR–04/06 Section 1 Introduction Congratulations on acquiring the AVR® AT90USBKey. This kit is designed to give designers a quick start to develop code on the AVR® and for prototyping and testing of new designs with the AT90USB microcontroller family. 1.1 Overview This document describes the AT90USBKey dedicated to the AT90USB AVR microcontroller. This board is designed to allow an easy evaluation of the product using demonstration software. To increase its demonstrative capabilities, this stand alone board has numerous onboard resources: USB, joystick, data-flash and temperature sensor. Figure 1-1 . AT90USBKey Introduction 1-4 AT90USBKey Hardware User Guide 7627A–AVR–04/06 1.2 AT90USBKey Features The AT90USBKey provides the following features: 􀀀 AT90USB QFN64 􀀀 AVR Studio® software interface (1) 􀀀 USB software interface for Device Firmware Upgrade (DFU bootloader) (2) 􀀀 Power supply flagged by “VCC-ON” LED: – regulated 3.3V – from an external battery connector (for reduced host or OTG operation) – from the USB interface (USB device bus powered application) 􀀀 JTAG interface (connector not mounted): – for on-chip ISP – for on-chip debugging using JTAG ICE 􀀀 Serial interfaces: – 1 USB full/low speed device/host/OTG interface 􀀀 On-board resources: – 4+1-ways joystick – 2 Bi-Color LEDs – temperature sensor – serial dataflash memories – all microcontroller I/O ports access on 2x8pin headers (not mounted) 􀀀 On-board RESET button 􀀀 On-board HWB button to force bootloader section execution at reset. 􀀀 System clock: – 8 MHz crystal Notes: 1. The AVRUSBKey is supported by AVR Studio®, version 4.12 or higher. For up-todate information on this and other AVR tool products, please consult our web site. The most recent version of AVR Studio®, AVR tools and this User Guide can be found in the AVR section of the Atmel web site, http://www.atmel.com. 2. ATMEL Flip®, In System Programming Version 3 or Higher shall be used for Device Firmware Upgrade. Please consult Atmel web site to retrieve the latex version of Flip and the DFU bootloader Hex file if needed. AT90USBKey Hardware User Guide 2-5 7627A–AVR–04/06 Section 2 Using the AT90USBKey This chapter describes the AVRUSBKey and all its resources. 2.1 Overview Figure 2-1 . AT90USBKey Overview Using the AT90USBKey 2-6 AT90USBKey Hardware User Guide 7627A–AVR–04/06 2.2 Power Supply 2.2.1 Power Supply Sources The on-board power supply circuitry allows two power supply configurations: 􀀀 from USB connector 􀀀 from battery connector USB powered When used as a USB device bus powered application, the AVRUSBKey can be directly powered via the USB VBUS power supply line. Battery powered The external battery connector should be used when the AT90USBKey is used as a USB host. This mode allows the AT90USBKey to provide a 5V power supply from its VBUS pin. – Need of a female battery clip – Input supply from 8 up to 15V DC (min. 100mA) Figure 2-2 . Power supply schematic VCC3 IN 1 GND 2 OUT 3 U5 LM340 VBUS VBAT D4 LL4148 - C16 4.7uF R19 124k 1% U3out=1.25*(1+(R15+R18)/R19) 100k 1% R18 D3 LL4148 C17 220nF VCC3 5V R15 100k 1% MTA Ext power supply 1 2 J8 C18 100nF OUT 1 IN 2 GND 3 OUT 4 FAULT SHDN 8 7 CC 6 SET 5 U4 LP3982 C15 33nF D6 LL4148 Using the AT90USBKey AT90USBKey Hardware User Guide 2-7 7627A–AVR–04/06 2.2.2 VBUS Generator When using the AT90USB microcontroller in USB host mode, the AT90USBKey should provide a 5V power supply over the VBUS pin of its USB mini AB connector. A couple of transistors allows the UVCON pin of the AT90USB to control the VBUS generation (See Figure 2-3). In this mode the AT90USBKey is powered by external battery power supply source. Figure 2-3 . VBUS generator schematic 2.2.3 “POWER-ON“ LED The POWER-ON LED (“D1”) is always lit when power is applied to AVRUSBKey regardless of the power supply source. R25 100k Q1 BC847B - C19 4.7uF R24 10k M1 FDV304P/FAI UVCON 5V VBUS Using the AT90USBKey 2-8 AT90USBKey Hardware User Guide 7627A–AVR–04/06 2.3 Reset Although the AT90USB has its on-chip RESET circuitry (c.f. AT90USB Datasheet, section “System Control and Reset), the AVRUSBKey provides to the AT90USB a RESET signal witch can come from two different sources: Figure 2-4 . Reset Implementation 2.3.1 Power-on RESET The on-board RC network acts as power-on RESET. 2.3.2 RESET Push Button By pressing the RESET push button on the AVRUSBKey, a warm RESET of the AT90USB is performed. 2.3.3 Main Clock XTAL To use the USB interface of the AT90USB, the clock source should always be a crystal or external clock oscillator (the internal 8MHz RC oscillator can not be used to operate with the USB interface). Only the following crystal frequency allows proper USB operations: 2MHz, 4MHz, 6MHz, 8MHz, 12MHz, 16MHz. The AT90USBKey comes with a default 8MHz crystal oscillator. RST VCC R6 47k C8 220nF RESET Using the AT90USBKey AT90USBKey Hardware User Guide 2-9 7627A–AVR–04/06 2.4 On-board Resources 2.4.1 USB The AVRUSBKey is supplied with a standard USB mini A-B receptacle. The mini AB receptacle allows to connect both a mini A plug or a mini B plug connectors. Figure 2-5 . USB mini A-B Receptacle When connected to a mini B plug, the AT90USB operates as an “USB device” (the ID pin of the plug is unconnected) and when connected to a mini A plug, the AT90USB operates as a “USB host” (the ID pin of the A plug is tied to ground). 2.4.2 Joystick The 4+1 ways joystick offers an easy user interface implementation for a USB application (it can emulate mouse movements, keyboard inputs...). Pushing the push-button causes the corresponding signal to be pulled low, while releasing (not pressed) causes an H.Z state on the signal. The user must enable internal pull-ups on the microcontroller input pins, removing the need for an external pull-up resistors on the push-button. Figure 2-6 . Joystick Schematic C7 1uF VBUS R4 0 GND VBUS 1-V_BUS 3-D+ 2-D- 4-ID 5-GND SHIELD USB_MiniAB J3 VBUS VBUS GND R3 22 R2 22 D+ DUID CR1 CR2 UCAP Select 5 Lef t 7 Up 3 Right 6 Down 4 Com1 1 Com2 2 SW3 TPA511G PE[7..0] PB[7..0] PB5 PB6 PB7 PE4 PE5 Using the AT90USBKey 2-10 AT90USBKey Hardware User Guide 7627A–AVR–04/06 2.4.3 LEDs The AT90USBKey includes 2 bi-color LEDs (green/red) implemented on one line. They are connected to the high nibble of “Port D” of AT90USB (PORTD[4..7]). To light on a LED, the corresponding port pin must drive a high level. To light off a LED, the corresponding port pin must drive a low level. Figure 2-7 . LEDs Implementation schematic Table 2-1 . Leds references 2.4.4 Temperature Sensor The temperature sensor uses a thermistor (R29), or temperature-sensitive resistor. This thermistor have a negative temperature coefficient (NTC), meaning the resistance goes up as temperature goes down. Of all passive temperature measurement sensors, thermistors have the highest sensitivity (resistance change per degree of temperature change). Thermistors do not have a linear temperature/resistance curve. The voltage over the NTC can be found using the A/D converter (connected to channel 0). See the AT90USB Datasheet for how to use the ADC. The thermistor value (RT) is calculate with the following expression: Where: RT = Thermistor value (Ω) at T temperature (°Kelvin) RH = Second resistor of the bridge -100 KΩ ±10% at 25°C VADC0 = Voltage value on ADC-0 input (V) VCC = Board power supply LED Reference AT90USB Connection Color D2 PORTD.4 Red PORTD.5 Green D5 PORTD.6 Green PORTD.7 Red D2 D5 1k R14 1k R17 LEDs In-line Grouped LEDs PD4 PD5 PD7 PD[7..0] PD6 1k R22 1k R23 RT (RH ⋅ VADC0) VCC VADC0 – = ⁄ ( ) Using the AT90USBKey AT90USBKey Hardware User Guide 2-11 7627A–AVR–04/06 The NTC thermistor used in AT90USBKey has a resistance of 100 KΩ ±5% at 25°C (T0) and a beta-value of 4250 ±3%. By the use of the following equation, the temperature (T) can be calculated: Where: RT = Thermistor value (Ω) at T temperature (°Kelvin) ß = 4250 ±3% R0 = 100 KΩ ±5% at 25°C T0 = 298 °K (273 °K + 25°K) The following cross table also can be used. It is based on the above equation. Table 2-2 . Thermistor Values versus Temperature Temp. (°C) RT (KΩ) Temp. (°C) RT (KΩ) Temp. (°C) RT (KΩ) Temp. (°C) RT (KΩ) -20 1263,757 10 212,958 40 50,486 70 15,396 -19 1182,881 11 201,989 41 48,350 71 14,851 -18 1107,756 12 191,657 42 46,316 72 14,329 -17 1037,934 13 181,920 43 44,380 73 13,828 -16 973,006 14 172,740 44 42,537 74 13,347 -15 912,596 15 164,083 45 40,781 75 12,885 -14 856,361 16 155,914 46 39,107 76 12,442 -13 803,984 17 148,205 47 37,513 77 12,017 -12 755,175 18 140,926 48 35,992 78 11,608 -11 709,669 19 134,051 49 34,542 79 11,215 -10 667,221 20 127,555 50 33,159 80 10,838 -9 627,604 21 121,414 51 31,840 81 10,476 -8 590,613 22 115,608 52 30,580 82 10,128 -7 556,056 23 110,116 53 29,378 83 9,793 -6 523,757 24 104,919 54 28,229 84 9,471 -5 493,555 25 100,000 55 27,133 85 9,161 -4 465,300 26 95,342 56 26,085 86 8,863 -3 438,854 27 90,930 57 25,084 87 8,576 -2 414,089 28 86,750 58 24,126 88 8,300 -1 390,890 29 82,787 59 23,211 89 8,035 0 369,145 30 79,030 60 22,336 90 7,779 1 348,757 31 75,466 61 21,498 91 7,533 2 329,630 32 72,085 62 20,697 92 7,296 3 311,680 33 68,876 63 19,930 93 7,067 4 294,826 34 65,830 64 19,196 94 6,847 T β RT R0 ⎝ ln-------⎠ ⎛ ⎞ β T0 + ------ = ------------------------------- Using the AT90USBKey 2-12 AT90USBKey Hardware User Guide 7627A–AVR–04/06 Figure 2-8 . Thermistor Schematic 2.4.5 Data Flash memory For mass-storage class demonstration purpose, the AT90USBKey provides two on-chip serial Flash memories (AT45DB642D) connected to the AT90USB Serial Port Interface (SPI). The data-flash chip select signals are connected to PortE bit 0 and bit 1 of the AT90USB (See Figure 2-9). Figure 2-9 . On-board data flash schematic 5 278,995 35 62,937 65 18,493 95 6,635 6 264,119 36 60,188 66 17,820 96 6,430 7 250,134 37 57,576 67 17,174 97 6,233 8 236,981 38 55,093 68 16,556 98 6,043 9 224,606 39 52,732 69 15,964 99 5,860 Temp. (°C) RT (KΩ) Temp. (°C) RT (KΩ) Temp. (°C) RT (KΩ) Temp. (°C) RT (KΩ) PF[7..0] R29 R27 100k PF0 VCC PE0 VCC3 VCC3 PB[7..0] PB1 R9 100k RESET PB3 PB2 SI 1 SCK 2 RESET 3 CS 4 WP VCC 5 GND 6 SO 7 8 U2 AT45DB642D CASON8 PE1 VCC3 VCC3 RESET PB1 R10 100k PB3 PB2 SI 1 SCK 2 RESET 3 CS 4 WP VCC 5 GND 6 SO 7 8 U3 AT45DB642D CASON8 R12 100k R11 100k Using the AT90USBKey AT90USBKey Hardware User Guide 2-13 7627A–AVR–04/06 2.5 In-System Programming 2.5.1 Programming with USB bootloader: DFU (Device Firmware Upgrade) AT90USB part comes with a default factory pre-programmed USB bootloader located in the on-chip boot section of the AT90USB. This is the easiest and fastest way to reprogram the device directly over the USB interface. The “Flip” PC side application, is available from the Atmel website, offers a flexible an user friendly interface to reprogram the application over the USB bus. The HWB pin of the AT90USB allows to force the bootloader section execution after reset. (Refer to AT90USB datasheet section “boot loader support”). To force bootloader execution, operate as follow: 􀀀 Press both “RST” and “HWB” push buttons 􀀀 First release the “RST” push button 􀀀 Release the “HWB” push button For more information about the USB bootloader and “Flip” application, please refer to the “USB bootloader datasheet document” and “Flip’s user manual”. Note: The HWB pin is active only if the HWBE fuse is set (default factory configuration). 2.5.2 Programming with AVR JTAGICEmKII The AT90USB can be programmed using specific JTAG link. To use the AVR JTAGICEmkII with an AT90USBKey an optional HE10 connector should be soldered to J9 footprint. Then the JTAG probe can be connected to the AT90USBKey as shown in Figure 2-10. Note: When the JTAGEN Fuse is unprogrammed, the four TAP pins are normal port pins, and the TAP controller is in reset. When programmed, the input TAP signals are internally pulled high and the JTAG is enabled for Boundary-scan and programming. The AT90USB device is shipped with this fuse programmed. Using the AT90USBKey 2-14 AT90USBKey Hardware User Guide 7627A–AVR–04/06 Figure 2-10 . Connecting AVR JTAG ICE to AVRUSBKey The Flash, EEPROM and all Fuse and Lock Bit options ISP-programmable can be programmed individually or with the sequential automatic programming option. Note: See AVR Studio® on-line Help for information. 2.6 Debugging 2.6.1 Debugging with AVR JTAG ICE mkII The AT90USBKey can be used for debugging with JTAG ICE MK II. Connect the JTAG ICE mkII as shown in Figure 2-10, for debugging, please refer to AVR Studio® Help information. When using JTAG ICE MK II for debugging, and as AT90USB parts are factory configured with the higher security level set, a chip erase operation will be performed on the part before debugging. Thus the on-chip flash bootloader will be erased. It can be restored after the debug session using the bootloader hex file available from ATMEL website. AT90USBKey Hardware User Guide 3-15 7627A–AVR–04/06 Section 3 Troubleshooting Guide Figure 3-1 . Troubleshooting Guide Problem Reason Solution The Green “VCC-ON” LED is not on No power supply Verify the power supply source (check AVRUSBKey does not battery charge or USB connection). work The AT90USB cannot be programmed The AVR JTAG ICE probe is not connected Connect the JTAG ICE 10-PIN header to the correct AVRUSBKey JTAG header (page 13) The memory lock bits are programmed Erase the memory before programming with JTAG ICE. The fuse bits are wrongly programmed Check the fuse bits with JTAG ICE Can not connect to USB bootloader Force bootloader execution with HWB under reset. USB bootloader erased after a JTAG debugging session: reprogram the USB bootloader with JTAG. AVR Studio does not detect the AVR JTAG ICE. Serial/USB cable is not connected, or power is off Connect serial cable to RS232 (STK500 - AVR ISP) and check power connections Connect serial cable to USB (JATG ICE MKII, AVR ISPmkIIl) and check power connections PC COM port is in use Disable other programs that are using PC COM port. Change PC COM port AVR Studio does not detect COM port. Disable COM port auto-detection in AVR Studio file menu. Force COM port to correct COM port AT90USBKey Hardware User Guide 4-16 7627A–AVR–04/06 Section 4 Technical Specifications 􀀀 System Unit – Physical Dimensions.....................................................L=90 x W=30 x H=8 mm – Weight ...........................................................................................................12 g 􀀀 Operating Conditions – Internal Voltage Supply ............................................................................... 3.3V – External Voltage Supply .........................................................................8V -15V 􀀀 Connections – USB Connector ......................................................................Mini AB receptacle – USB Communications .......................................................Full speed/low speed – JTAG Connector.................................................... Footprint for HE10 connector – All ports connectors.............................................................J1, J2, J4, J5, J6, J7 – Battery connector ....................................................................... MTA right angle AT90USBKey Hardware User Guide 5-17 7627A–AVR–04/06 Section 5 Technical Support For Technical support, please contact avr@atmel.com. When requesting technical support, please include the following information: 􀀀 Which target AVR device is used (complete part number) 􀀀 Target voltage and speed 􀀀 Clock source and fuse setting of the AVR 􀀀 Programming method (ISP, JTAG or specific Boot-Loader) 􀀀 Hardware revisions of the AVR tools, found on the PCB 􀀀 Version number of AVR Studio. This can be found in the AVR Studio help menu. 􀀀 PC operating system and version/build 􀀀 PC processor type and speed 􀀀 A detailed description of the problem AT90USBKey Hardware User Guide 6-18 7627A–AVR–04/06 Section 6 Complete Schematics On the next pages, the following documents of AT90USBKey are shown: 􀀀 Complete schematics, 􀀀 Bill of materials. Complete Schematics AT90USBKey Hardware User Guide 6-19 7627A–AVR–04/06 Figure 6-1 . Schematics, 1 of 2 C7 1uF C3216-A VBUS RST RST DTSM-3 AVCC PD[7..0] PD[7..0] PA0 UCAP Capacitor Closed to the MCU VCC PA1 R4 0 R0603 PE0 PF7 PE2 PE1 PE4 PE3 PE6 PE[7..0] PE5 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 J2 1.27 mm Dual H1.27-10 PE7 PA3 UGND (not mounted) PE2 VCC PA[7..0] PF0 PA2 RESET PA4 PF2 Reset Circuit UVCON VBUS PA5 HWB HWB DTSM-3 R1 0 R0603 PF4 RESET UGND R8 0 R0603 PA6 AGND C1 100nF C0603 PF1 UCAP PA7 (not mounted) (not mounted) (not mounted) PF3 PE2 PF[7..0] PC7 R5 0 R0603 VCC C9 220nF C0603 (not mounted) PE4 VCC PB[7..0] PB[7..0] PE5 PC6 VCC AVCC C2 100nF C0603 GND Title Size Document Number Rev Date: Sheet of 1.0.0 CPU A4 Monday , January 09, 2006 1 2 PE6 PF6 PC5 PD0 PD2 PD1 PD4 PD3 PD6 PD[7..0] PD5 (not mounted) 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 J4 1.27 mm Dual H1.27-10 PD7 PC4 QFN64 VCC PB0 VCC Ferrite & capacitors closed to the MCU PB0 PB2 PB1 PB4 PB1 PB3 PB6 PB[7..0] PB5 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 J6 1.27 mm Dual H1.27-10 PB7 PA0 1-V_BUS 3-D+ 2-D- 4-ID 5-GND SHIELD USB_MiniABF J3 MINI_USBC PA2 PA1 PA4 PA3 PA6 PA[7..0] PB2 PA5 PC3 PF[7..0] 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 J7 1.27 mm Dual H1.27-10 PA7 R6 47k R0603 PE7 2 UVcc 3 D- 4 D+ 5 UGND 6 UCAP 7 VBUS 8 PE3 9 PB0 10 PB1 11 PB2 12 PB3 13 PB4 14 PB5 15 PB6 16 PB7 17 PD0 25 PD1 26 PD2 27 PD3 28 PD4 29 PD5 30 PD6 31 PD7 32 PE4 18 PE5 19 AREF 62 RESET 20 GND 53 GND 63 GND 22 XTAL2 23 XTAL1 24 PE0 PE1 33 34 PE6 1 PE2 43 PC0 PC1 35 PC2 36 PC3 37 PC4 38 PC5 39 PC6 40 PC7 41 42 PA7 PA6 44 PA5 45 PA4 46 PA3 47 48 PA2 PA1 49 PA0 50 51 PF7 PF6 54 PF5 55 PF4 56 PF3 57 PF2 58 PF1 59 PF0 60 61 VCC 52 VCC 21 AVCC 64 AT90USB128 U1 QFN64 PB3 UVCON PE7 C5 100nF C0603 VCC DECOUPLING CAPACITORS CLOSED TO THE DEVICE VBUS MCU Pin3 PC2 PB4 Y1 8MHz CRYSTAL 8MHz 49US C11 15pF C0603 C10 15pF C0603 PC1 PB5 PC0 PC2 PC1 PC4 PC3 PC6 PC[7..0] PC5 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 J5 1.27 mm Dual H1.27-10 PC7 VBUS AREF PC0 PB6 PE[7..0] PE1 PB7 VCC PF0 PE0 C8 220nF C0603 UGND UGND PC[7..0] PC[7..0] C3 100nF C0603 GND PF1 R3 22 R0603 R7 47k R0603 R2 22 R0603 RESET D+ C4 100nF C0603 DUID PE3 PF2 A90USB Key VCC GND PD0 XTAL2 PD1 PD2 PF5 PF3 PD3 AGND CR1 PGB0010603 R0603 CR2 PGB0010603 R0603 PD4 XTAL1 VCC PD5 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 J1 1.27 mm Dual H1.27-10 PD6 DECOUPLING CAPACITORS CLOSED TO THE DEVICE MCU Pin52 RESISTORS CLOSED TO THE DEVICE PD7 PF4 VCC XTAL2 VCC UCAP PF7 UVCC D+ D- RESISTORS Closed to the MCU PF5 Bootloader Activation C6 100nF C0603 VCC PA[7..0] VCC AREF DECOUPLING CAPACITORS CLOSED TO THE DEVICE MCU Pin21 PF6 XTAL1 Complete Schematics 6-20 AT90USBKey Hardware User Guide 7627A–AVR–04/06 Figure 6-2 . Schematics, 2 of 2 PE0 VCC3 !!! R21 not mounted D2 IN 1 GND 2 OUT 3 U5 LM340 - C14 4.7uF VCC3 When mounting R21: R20 not mounted U4 not mounted Allows to generate 3.3V from U1 internal regulator CAUTION: R21 default not mounted !!! VBUS generator f or OTG/HOST mode 1F 1.0.0 Power & Interf aces A4 Saturday , February 18, 2006 2 2 1k R17 LEDs In-line Grouped LEDs PD4 PD5 PD7 PD[7..0] PD6 1k R22 C17 220nF VBat Mon. VCC 1k R23 VCC3 - C19 4.7uF 5V PE1 VCC3 VCC3 VCC3 DECOUPLING CAPACITOR CLOSE TO THE DEVICE C13 100nF RESET PB1 R10 100k PB3 PB2 SI 1 SCK 2 RESET 3 CS 4 WP VCC 5 GND 6 SO 7 8 U3 AT45DB642D CASON8 R12 100k R24 10k R15 100k 1% MTA Ext power supply 1 2 J8 C18 100nF VCC OUT 1 IN 2 GND 3 OUT 4 FAULT SHDN 8 7 CC 6 SET 5 U4 LP3982 C15 33nF R11 100k (not mounted) M1 D6 FDV304P/FAI LL4148 R16 0 R20 0 UCAP UVCON R21 0 VCC VBUS Complete Schematics AT90USBKey Hardware User Guide 6-21 7627A–AVR–04/06 Table 6-1 . Bill of material Item Q.ty Reference Part Tech. Characteristics Package 1 2 CR1,CR2 ESD protection (PGB0010603) 2 10 C1,C2,C3,C4,C5,C6,C12, C13, C18, C20 100nF 50V-10% Ceramic CASE 0603 3 1 C7 1uF 10Vmin ±10% EIA/IECQ 3216 4 3 C8,C9, C17 220nF 50V-10% Ceramic CASE 0603 5 2 C10, C11 15pF 50V-5% Ceramic CASE 0603 6 3 C14, C16, C19 4.7uF 10Vmin ±10% EIA/IECQ 3216 7 1 C15 33nF 50V-5% Ceramic CASE 0603 8 2 D2,D5 LED BI-COLOUR/ LSGT670 I=10 mA_ PLCC-4 9 1 D1 TOPLED/ LPM676-K2M1 I=10 mA_ PLCC-2 10 2 D3,D4 DII LL4148-7 i=200mA max LL-34 11 1 J3 USB mini AB receptacle Surface mount 12 0 J9 CON 2x5 (2.54mm) (Not Mounted) 13 0 J1,J2,J4,J5,J6,J7 1.27 mm Dual header (Not Mounted) 14 1 J8 Connector MTA 2 cts right angle 15 1 M1 FDV304P/FAI SOT23 16 1 Q1 BC847B IC peak=200mA SOT23 17 2 R2,R3 22 1/16W-5% SMD CASE 0603 18 1 R5 68k 1/16W-5% SMD CASE 0603 19 2 R6,R7 47k 1/16W-5% SMD CASE 0603 20 7 R1,R4,R5,R8,R16,R20, R26 0 CASE 0603 21 0 R21 0 (Not Mounted) CASE 0603 22 1 R28 220k 1/16W-5% SMD CASE 0603 23 7 R9,R10,R11,R12,R25,R27,R3 0 100k 1/16W-5% SMD CASE 0603 24 5 R13,R14,R17,R22,R23 1k 1/16W-5% SMD CASE 0603 25 2 R24,R28 10k 1/16W-5% SMD CASE 0603 26 1 R29 NCP18WF104J03RB 100K - ß=4250 CASE 0603 27 2 R15,R18 100k 1% 1/16W-1% SMD CASE 0603 28 1 R19 120k 1% 1/16W-1% SMD CASE 0603 29 2 SW1,SW2 PUSH-BUTTON / DTSM31N 6x3.5mm - 1.6N See DS 30 1 SW3 TPA511G 4 ways joystick + center CMS mount 31 1 U1 AT90USB1287 QFN64 32 2 U2,U3 AT45DB642D CASON8 33 1 U4 LP3982IMM-ADJ Vin Max 6V, 300mA MSOP8 34 1 U6 LM340MP5.0 35 1 Y1 8MHz CRYSTAL H=4mm HC49/4H Printed on recycled paper. 7627A–AVR–04/06 /xM © Atmel Corporation 2006. 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Copyright  2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1A 1Y 2A 2Y 3A 3Y GND VCC 6A 6Y 5A 5Y 4A 4Y SN5404 . . . J PACKAGE SN54LS04, SN54S04 . . . J OR W PACKAGE SN7404, SN74S04 . . . D, N, OR NS PACKAGE SN74LS04 . . . D, DB, N, OR NS PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1A 2Y 2A VCC 3A 3Y 4A 1Y 6A 6Y GND 5Y 5A 4Y SN5404 . . . W PACKAGE (TOP VIEW) 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 6Y NC 5A NC 5Y 2A NC 2Y NC 3A SN54LS04, SN54S04 . . . FK PACKAGE (TOP VIEW) 1Y 1A NC 4Y 4A 6A 3Y GND NC NC − No internal connection VCC      !"   #!$% &"' &!   #" #" (" "  ") !" && *+' &! #", &"  ""%+ %!&" ",  %% #""'  #&! #%  - ./.010 %% #"" " ""& !%" ("*" "&'  %% (" #&! #&! #", &"  ""%+ %!&" ",  %% #""'          SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN7404N SN7404N PDIP − N Tube SN74LS04N SN74LS04N Tube SN74S04N SN74S04N Tube SN7404D 7404 Tape and reel SN7404DR SOIC − D Tube SN74LS04D LS04 0°C to 70°C Tape and reel SN74LS04DR 0 70 Tube SN74S04D S04 Tape and reel SN74S04DR Tape and reel SN7404NSR SN7404 SOP − NS Tape and reel SN74LS04NSR 74LS04 Tape and reel SN74S04NSR 74S04 SSOP − DB Tape and reel SN74LS04DBR LS04 Tube SN5404J SN5404J Tube SNJ5404J SNJ5404J CDIP − J Tube SN54LS04J SN54LS04J Tube SN54S04J SN54S04J Tube SNJ54LS04J SNJ54LS04J −55°C to 125°C Tube SNJ54S04J SNJ54S04J Tube SNJ5404W SNJ5404W CFP − W Tube SNJ54LS04W SNJ54LS04W Tube SNJ54S04W SNJ54S04W LCCC − FK Tube SNJ54LS04FK SNJ54LS04FK Tube SNJ54S04FK SNJ54S04FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each inverter) INPUT A OUTPUT Y H L L H          SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 logic diagram (positive logic) 1A 2A 3A 4A 5A 6A 1Y 2Y 3Y 4Y 5Y 6Y Y = A          SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 schematics (each gate) Input A VCC Output Y GND 130 Ω 1 kΩ 1.6 kΩ ’04 4 kΩ Input A VCC Output Y GND 20 kΩ 120 Ω ’LS04 8 kΩ 12 kΩ 1.5 kΩ 3 kΩ 4 kΩ Input A VCC Output Y GND 2.8 kΩ 900 Ω ’S04 50 Ω 3.5 kΩ 250 Ω 500 Ω Resistor values shown are nominal.          SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI: ’04, ’S04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V ’LS04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN5404 SN7404 UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current −0.4 −0.4 mA IOL Low-level output current 16 16 mA TA Operating free-air temperature −55 125 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST SN5404 SN7404 CONDITIONS‡ UNIT MIN TYP§ MAX MIN TYP§ MAX VIK VCC = MIN, II = − 12 mA −1.5 −1.5 V VOH VCC = MIN, VIL = 0.8 V, IOH = −0.4 mA 2.4 3.4 2.4 3.4 V VOL VCC = MIN, VIH = 2 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V II VCC = MAX, VI = 5.5 V 1 1 mA IIH VCC = MAX, VI = 2.4 V 40 40 μA IIL VCC = MAX, VI = 0.4 V −1.6 −1.6 mA IOS¶ VCC = MAX −20 −55 −18 −55 mA ICCH VCC = MAX, VI = 0 V 6 12 6 12 mA ICCL VCC = MAX, VI = 4.5 V 18 33 18 33 mA ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § All typical values are at VCC = 5 V, TA = 25°C. ¶ Not more than one output should be shorted at a time.          SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) FROM TO SN5404 PARAMETER SN7404 (INPUT) (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tPLH A Y RL = 400 Ω, CL = 15 pF 12 22 ns tPHL 8 15 recommended operating conditions (see Note 3) SN54LS04 SN74LS04 UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current −0.4 −0.4 mA IOL Low-level output current 4 8 mA TA Operating free-air temperature −55 125 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS† SN54LS04 SN74LS04 UNIT MIN TYP‡ MAX MIN TYP‡ MAX VIK VCC = MIN, II = − 18 mA −1.5 −1.5 V VOH VCC = MIN, VIL = MAX, IOH = −0.4 mA 2.5 3.4 2.7 3.4 V VOL VCC = MIN, VIH = 2 V IOL = 4 mA 0.25 0.4 0.4 V IOL = 8 mA 0.25 0.5 II VCC = MAX, VI = 7 V 0.1 0.1 mA IIH VCC = MAX, VI = 2.7 V 20 20 μA IIL VCC = MAX, VI = 0.4 V −0.4 −0.4 mA IOS§ VCC = MAX −20 −100 −20 −100 mA ICCH VCC = MAX, VI = 0 V 1.2 2.4 1.2 2.4 mA ICCL VCC = MAX, VI = 4.5 V 3.6 6.6 3.6 6.6 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2) FROM TO SN54LS04 PARAMETER SN74LS04 (INPUT) (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tPLH A Y RL = 2 kΩ, CL = 15 pF 9 15 ns tPHL 10 15          SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 recommended operating conditions (see Note 3) SN54S04 SN74S04 UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current −1 −1 mA IOL Low-level output current 20 20 mA TA Operating free-air temperature −55 125 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS† SN54S04 SN74S04 UNIT MIN TYP‡ MAX MIN TYP‡ MAX VIK VCC = MIN, II = − 18 mA −1.2 −1.2 V VOH VCC = MIN, VIL = 0.8 V, IOH = −1 mA 2.5 3.4 2.7 3.4 V VOL VCC = MIN, VIH = 2 V, IOL = 20 mA 0.5 0.5 V II VCC = MAX, VI = 5.5 V 1 1 mA IIH VCC = MAX, VI = 2.7 V 50 50 μA IIL VCC = MAX, VI = 0.5 V −2 −2 mA IOS§ VCC = MAX −40 −100 −40 −100 mA ICCH VCC = MAX, VI = 0 V 15 24 15 24 mA ICCL VCC = MAX, VI = 4.5 V 30 54 30 54 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) FROM TO SN54S04 PARAMETER SN74S04 (INPUT) (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tPLH A Y RL = 280 Ω, CL = 15 pF 3 4.5 ns tPHL 3 5 tPLH A Y RL = 280 Ω, CL = 50 pF 4.5 ns tPHL 5          SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION SERIES 54/74 AND 54S/74S DEVICES tPHL tPLH tPLH tPHL LOAD CIRCUIT FOR 3-STATE OUTPUTS High-Level Pulse Low-Level Pulse VOLTAGE WAVEFORMS PULSE DURATIONS Input Out-of-Phase Output (see Note D) 3 V 0 V VOL VOH VOH VOL In-Phase Output (see Note D) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC RL Test Point From Output Under Test CL (see Note A) LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS (see Note B) VCC RL From Output Under Test CL (see Note A) Test Point (see Note B) VCC RL From Output Under Test CL (see Note A) Test Point 1 kΩ NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO≈ 50 Ω; tr and tf ≤ 7 ns for Series 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time, with one input transition per measurement. S1 S2 tPHZ tPZL tPLZ tPZH 3 V 3 V 0 V 0 V th tsu VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Timing Input Data Input 3 V 0 V Output Control (low-level enabling) Waveform 1 (see Notes C and D) Waveform 2 (see Notes C and D) ≈1.5 V VOH − 0.5 V VOL + 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V tw 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V VOH VOL Figure 1. Load Circuits and Voltage Waveforms          SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PARAMETER MEASUREMENT INFORMATION SERIES 54LS/74LS DEVICES tPHL tPLH tPLH tPHL LOAD CIRCUIT FOR 3-STATE OUTPUTS High-Level Pulse Low-Level Pulse VOLTAGE WAVEFORMS PULSE DURATIONS Input Out-of-Phase Output (see Note D) 3 V 0 V VOL VOH VOH VOL In-Phase Output (see Note D) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC RL Test Point From Output Under Test CL (see Note A) LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS (see Note B) VCC RL From Output Under Test CL (see Note A) Test Point (see Note B) VCC RL From Output Under Test CL (see Note A) Test Point 5 kΩ NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time, with one input transition per measurement. S1 S2 tPHZ tPZL tPLZ tPZH 3 V 3 V 0 V 0 V th tsu VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Timing Input Data Input 3 V 0 V Output Control (low-level enabling) Waveform 1 (see Notes C and D) Waveform 2 (see Notes C and D) ≈1.5 V VOH − 0.5 V VOL + 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V tw 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V VOL VOH Figure 2. Load Circuits and Voltage Waveforms PACKAGE OPTION ADDENDUM www.ti.com 2-May-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples JM38510/00105BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00105BCA JM38510/00105BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00105BDA JM38510/07003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 07003BCA JM38510/07003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 07003BDA JM38510/30003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 30003B2A JM38510/30003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003BCA JM38510/30003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003BDA JM38510/30003SCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003SCA JM38510/30003SDA ACTIVE CFP W 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003SDA M38510/00105BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00105BCA M38510/00105BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00105BDA M38510/07003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 07003BCA M38510/30003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 30003B2A M38510/30003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003BCA M38510/30003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003BDA M38510/30003SCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003SCA M38510/30003SDA ACTIVE CFP W 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 30003SDA PACKAGE OPTION ADDENDUM www.ti.com 2-May-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN5404J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN5404J SN54LS04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54LS04J SN54S04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54S04J SN7404D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404 SN7404DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404 SN7404DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404 SN7404DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404 SN7404DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404 SN7404DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404 SN7404N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN7404N SN7404N3 OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70 SN7404NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN7404N SN74LS04D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 SN74LS04J OBSOLETE CDIP J 14 TBD Call TI Call TI 0 to 70 PACKAGE OPTION ADDENDUM www.ti.com 2-May-2014 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74LS04N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS04N SN74LS04N3 OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70 SN74LS04NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS04N SN74LS04NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS04 SN74LS04NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS04 SN74S04D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04 SN74S04DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04 SN74S04DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04 SN74S04DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04 SN74S04DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04 SN74S04DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04 SN74S04N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74S04N SN74S04N3 OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70 SN74S04NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74S04N SN74S04NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74S04 SN74S04NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74S04 SN74S04NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74S04 SNJ5404J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5404J SNJ5404W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5404W PACKAGE OPTION ADDENDUM www.ti.com 2-May-2014 Addendum-Page 4 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SNJ54LS04FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54LS 04FK SNJ54LS04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54LS04J SNJ54LS04W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54LS04W SNJ54S04FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54S 04FK SNJ54S04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54S04J SNJ54S04W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54S04W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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OTHER QUALIFIED VERSIONS OF SN5404, SN54LS04, SN54LS04-SP, SN54S04, SN7404, SN74LS04, SN74S04 : • Catalog: SN7404, SN74LS04, SN54LS04, SN74S04 • Military: SN5404, SN54LS04, SN54S04 • Space: SN54LS04-SP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN7404DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LS04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74S04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74S04NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN7404DR SOIC D 14 2500 367.0 367.0 38.0 SN74LS04DR SOIC D 14 2500 367.0 367.0 38.0 SN74S04DR SOIC D 14 2500 367.0 367.0 38.0 SN74S04NSR SO NS 14 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated 1FEATURES 1 2 3 4 5 6 7 8 2IN+ 2IN– 2OUT V CC+ V CC– 1IN+ 1IN– 1OUT NE5532, NE5532A . . . D, P, OR PS PACKAGE SA5532, SA5532A . . . D OR P PACKAGE (TOP VIEW) DESCRIPTION/ORDERING INFORMATION NE5532, NE5532A SA5532, SA5532A www.ti.com................................................................................................................................................... SLOS075I–NOVEMBER 1979–REVISED APRIL 2009 DUAL LOW-NOISE OPERATIONAL AMPLIFIERS · Equivalent Input Noise Voltage: 5 nV/√Hz Typ at 1 kHz · Unity-Gain Bandwidth: 10 MHz Typ · Common-Mode Rejection Ratio: 100 dB Typ · High DC Voltage Gain: 100 V/mV Typ · Peak-to-Peak Output Voltage Swing 26 V Typ With VCC± = ±15 V and RL = 600 Ω · High Slew Rate: 9 V/ms Typ The NE5532, NE5532A, SA5532, and SA5532A are high-performance operational amplifiers combining excellent dc and ac characteristics. They feature very low noise, high output-drive capability, high unity-gain and maximum-output-swing bandwidths, low distortion, high slew rate, input-protection diodes, and output short-circuit protection. These operational amplifiers are compensated internally for unity-gain operation. These devices have specified maximum limits for equivalent input noise voltage. ORDERING INFORMATION(1) TA PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING NE5532P NE5532P PDIP – P Tube of 50 NE5532AP NE5532AP Tube of 75 NE5532D N5532 Reel of 2500 NE5532DR 0°C to 70°C SOIC – D Tube of 75 NE5532AD N5532A Reel of 2500 NE5532ADR NE5532PSR N5532 SOP – PS Reel of 2000 NE5532APSR N5532A SA5532P SA5532P PDIP – P Tube of 50 SA5532AP SA5532AP Tube of 75 SA5532D –40°C to 85°C SA5532 Reel of 2500 SA5532DR SOIC – D Tube of 75 SA5532AD SA5532A Reel of 2500 SA5532ADR (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1979–2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. OUT VCC– VCC+ 36 pF 37 pF 14 pF 7 pF 15 W 460 W 15 W IN+ IN– Component values shown are nominal. ABSOLUTE MAXIMUM RATINGS(1) NE5532, NE5532A SA5532, SA5532A SLOS075I–NOVEMBER 1979–REVISED APRIL 2009................................................................................................................................................... www.ti.com SCHEMATIC (EACH AMPLIFIER) over operating free-air temperature range (unless otherwise noted) VCC+ 22 V VCC Supply voltage(2) VCC– –22 V Input voltage, either input(2) (3) VCC± Input current(4) ±10 mA Duration of output short circuit(5) Unlimited D package 97°C/W qJA Package thermal impedance(6) (7) P package 85°C/W PS package 95°C/W TJ Operating virtual-junction temperature 150°C Tstg Storage temperature range –65°C to 150°C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–. (3) The magnitude of the input voltage must never exceed the magnitude of the supply voltage. (4) Excessive input current will flow if a differential input voltage in excess of approximately 0.6 V is applied between the inputs, unless some limiting resistance is used. (5) The output may be shorted to ground or either power supply. Temperature and/or supply voltages must be limited to ensure the maximum dissipation rating is not exceeded. (6) The package thermal impedance is calculated in accordance with JESD 51-7. (7) Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 2 Submit Documentation Feedback Copyright © 1979–2009, Texas Instruments Incorporated Product Folder Link(s): NE5532 NE5532A SA5532 SA5532A RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS NE5532, NE5532A SA5532, SA5532A www.ti.com................................................................................................................................................... SLOS075I–NOVEMBER 1979–REVISED APRIL 2009 MIN MAX UNIT VCC+ Supply voltage 5 15 V VCC– Supply voltage –5 –15 V NE5532, NE5532A 0 70 TA Operating free-air temperature °C SA5532, SA5532A –40 85 VCC± = ±15 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT TA = 25°C 0.5 4 VIO Input offset voltage VO = 0 mV TA = Full range(2) 5 TA = 25°C 10 150 IIO Input offset current nA TA = Full range(2) 200 TA = 25°C 200 800 IIB Input bias current nA TA = Full range(2) 1000 VICR Common-mode input-voltage range ±12 ±13 V V Maximum peak-to-peak output-voltage OPP swing RL ≥ 600 Ω, VCC± = ±15 V 24 26 V TA = 25°C 15 50 RL ≥ 600 Ω, VO = ±10 V Large-signal differential-voltage TA = Full range(2) 10 AVD amplification V/mV TA = 25°C 25 100 RL ≥ 2 kΩ, VO±10 V TA = Full range(2) 15 A Small-signal differential-voltage vd amplification f = 10 kHz 2.2 V/mV BOM Maximum output-swing bandwidth RL = 600 Ω, VO = ±10 V 140 kHz B1 Unity-gain bandwidth RL = 600 Ω, CL = 100 pF 10 MHz ri Input resistance 30 300 kΩ zo Output impedance AVD = 30 dB, RL = 600 Ω, f = 10 kHz 0.3 Ω CMRR Common-mode rejection ratio VIC = VICR min 70 100 dB k Supply-voltage rejection ratio SVR (ΔV VCC± = ±9 V to ±15 V, VO = 0 80 100 dB CC±/ΔVIO) IOS Output short-circuit current 10 38 60 mA ICC Total supply curent VO = 0, No load 8 16 mA Crosstalk attenuation (VO1/VO2) V01 = 10 V peak, f = 1 kHz 110 dB (1) All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. (2) Full temperature ranges are: –40°C to 85°C for the SA5532 and SA5532A, and 0°C to 70°C for the NE5532 and NE5532A. Copyright © 1979–2009, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): NE5532 NE5532A SA5532 SA5532A OPERATING CHARACTERISTICS NE5532, NE5532A SA5532, SA5532A SLOS075I–NOVEMBER 1979–REVISED APRIL 2009................................................................................................................................................... www.ti.com VCC± = ±15 V, TA = 25°C (unless otherwise noted) NE5532, SA5532 NE5532A, SA5532A PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX SR Slew rate at unity gain 9 9 V/ms Overshoot factor VI = 100 mV, RL = 600 Ω, 10 10 % AVD = 1, CL = 100 pF f = 30 Hz 8 8 10 Vn Equivalent input noise voltage nV/√Hz f = 1 kHz 5 5 6 f = 30 Hz 2.7 2.7 In Equivalent input noise current pA/√Hz f = 1 kHz 0.7 0.7 4 Submit Documentation Feedback Copyright © 1979–2009, Texas Instruments Incorporated Product Folder Link(s): NE5532 NE5532A SA5532 SA5532A PACKAGE OPTION ADDENDUM www.ti.com 17-May-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples NE5532AD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532ADE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532ADG4 ACTIVE SOIC D 8 TBD Call TI Call TI 0 to 70 NE5532ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532ADRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532AIP OBSOLETE PDIP P 8 TBD Call TI Call TI -40 to 85 NE5532AP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5532AP NE5532APE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5532AP NE5532APSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532APSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532A NE5532APSRG4 ACTIVE SO PS 8 TBD Call TI Call TI 0 to 70 NE5532D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 NE5532DE4 ACTIVE SOIC D 8 TBD Call TI Call TI 0 to 70 NE5532DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 NE5532DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 N5532 NE5532DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 NE5532DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 PACKAGE OPTION ADDENDUM www.ti.com 17-May-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples NE5532IP OBSOLETE PDIP P 8 TBD Call TI Call TI -40 to 85 NE5532P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5532P NE5532PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE5532P NE5532PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 NE5532PSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 NE5532PSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N5532 SA5532AD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A SA5532ADE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 SA5532ADG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A SA5532ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A SA5532ADRE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 SA5532ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532A SA5532AP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA5532AP SA5532APE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA5532AP SA5532D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532 SA5532DE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 SA5532DG4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 SA5532DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532 SA5532DRE4 ACTIVE SOIC D 8 TBD Call TI Call TI -40 to 85 PACKAGE OPTION ADDENDUM www.ti.com 17-May-2014 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SA5532DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA5532 SA5532P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA5532P SA5532PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA5532P (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. PACKAGE OPTION ADDENDUM www.ti.com 17-May-2014 Addendum-Page 4 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant NE5532ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE5532APSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 NE5532DR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 NE5532DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE5532DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE5532PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SA5532ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SA5532DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) NE5532ADR SOIC D 8 2500 340.5 338.1 20.6 NE5532APSR SO PS 8 2000 367.0 367.0 38.0 NE5532DR SOIC D 8 2500 364.0 364.0 27.0 NE5532DR SOIC D 8 2500 340.5 338.1 20.6 NE5532DRG4 SOIC D 8 2500 340.5 338.1 20.6 NE5532PSR SO PS 8 2000 367.0 367.0 38.0 SA5532ADR SOIC D 8 2500 340.5 338.1 20.6 SA5532DR SOIC D 8 2500 340.5 338.1 20.6 PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2013 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated LM386 LM386 Low Voltage Audio Power Amplifier Literature Number: SNAS545A LM386 Low Voltage Audio Power Amplifier General Description The LM386 is a power amplifier designed for use in low voltage consumer applications. The gain is internally set to 20 to keep external part count low, but the addition of an external resistor and capacitor between pins 1 and 8 will increase the gain to any value from 20 to 200. The inputs are ground referenced while the output automatically biases to one-half the supply voltage. The quiescent power drain is only 24 milliwatts when operating from a 6 volt supply, making the LM386 ideal for battery operation. Features n Battery operation n Minimum external parts n Wide supply voltage range: 4V–12V or 5V–18V n Low quiescent current drain: 4mA n Voltage gains from 20 to 200 n Ground referenced input n Self-centering output quiescent voltage n Low distortion: 0.2% (AV = 20, VS = 6V, RL = 8W, PO = 125mW, f = 1kHz) n Available in 8 pin MSOP package Applications n AM-FM radio amplifiers n Portable tape player amplifiers n Intercoms n TV sound systems n Line drivers n Ultrasonic drivers n Small servo drivers n Power converters Equivalent Schematic and Connection Diagrams DS006976-1 Small Outline, Molded Mini Small Outline, and Dual-In-Line Packages DS006976-2 Top View Order Number LM386M-1, LM386MM-1, LM386N-1, LM386N-3 or LM386N-4 See NS Package Number M08A, MUA08A or N08E August 2000 LM386 Low Voltage Audio Power Amplifier © 2000 National Semiconductor Corporation DS006976 www.national.com Absolute Maximum Ratings (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (LM386N-1, -3, LM386M-1) 15V Supply Voltage (LM386N-4) 22V Package Dissipation (Note 3) (LM386N) 1.25W (LM386M) 0.73W (LM386MM-1) 0.595W Input Voltage ±0.4V Storage Temperature −65°C to +150°C Operating Temperature 0°C to +70°C Junction Temperature +150°C Soldering Information Dual-In-Line Package Soldering (10 sec) +260°C Small Outline Package (SOIC and MSOP) Vapor Phase (60 sec) +215°C Infrared (15 sec) +220°C See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices. Thermal Resistance qJC (DIP) 37°C/W qJA (DIP) 107°C/W qJC (SO Package) 35°C/W qJA (SO Package) 172°C/W qJA (MSOP) 210°C/W qJC (MSOP) 56°C/W Electrical Characteristics (Notes 1, 2) TA = 25°C Parameter Conditions Min Typ Max Units Operating Supply Voltage (VS) LM386N-1, -3, LM386M-1, LM386MM-1 4 12 V LM386N-4 5 18 V Quiescent Current (IQ) VS = 6V, VIN = 0 4 8 mA Output Power (POUT) LM386N-1, LM386M-1, LM386MM-1 VS = 6V, RL = 8W, THD = 10% 250 325 mW LM386N-3 VS = 9V, RL = 8W, THD = 10% 500 700 mW LM386N-4 VS = 16V, RL = 32W, THD = 10% 700 1000 mW Voltage Gain (AV) VS = 6V, f = 1 kHz 26 dB 10 μF from Pin 1 to 8 46 dB Bandwidth (BW) VS = 6V, Pins 1 and 8 Open 300 kHz Total Harmonic Distortion (THD) VS = 6V, RL = 8W, POUT = 125 mW 0.2 % f = 1 kHz, Pins 1 and 8 Open Power Supply Rejection Ratio (PSRR) VS = 6V, f = 1 kHz, CBYPASS = 10 μF 50 dB Pins 1 and 8 Open, Referred to Output Input Resistance (RIN) 50 kW Input Bias Current (IBIAS) VS = 6V, Pins 2 and 3 Open 250 nA Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified. Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 3: For operation in ambient temperatures above 25°C, the device must be derated based on a 150°C maximum junction temperature and 1) a thermal resistance of 107°C/W junction to ambient for the dual-in-line package and 2) a thermal resistance of 170°C/W for the small outline package. LM386 www.national.com 2 Application Hints GAIN CONTROL To make the LM386 a more versatile amplifier, two pins (1 and 8) are provided for gain control. With pins 1 and 8 open the 1.35 kW resistor sets the gain at 20 (26 dB). If a capacitor is put from pin 1 to 8, bypassing the 1.35 kW resistor, the gain will go up to 200 (46 dB). If a resistor is placed in series with the capacitor, the gain can be set to any value from 20 to 200. Gain control can also be done by capacitively coupling a resistor (or FET) from pin 1 to ground. Additional external components can be placed in parallel with the internal feedback resistors to tailor the gain and frequency response for individual applications. For example, we can compensate poor speaker bass response by frequency shaping the feedback path. This is done with a series RC from pin 1 to 5 (paralleling the internal 15 kW resistor). For 6 dB effective bass boost: R . 15 kW, the lowest value for good stable operation is R = 10 kW if pin 8 is open. If pins 1 and 8 are bypassed then R as low as 2 kW can be used. This restriction is because the amplifier is only compensated for closed-loop gains greater than 9. INPUT BIASING The schematic shows that both inputs are biased to ground with a 50 kW resistor. The base current of the input transistors is about 250 nA, so the inputs are at about 12.5 mV when left open. If the dc source resistance driving the LM386 is higher than 250 kW it will contribute very little additional offset (about 2.5 mV at the input, 50 mV at the output). If the dc source resistance is less than 10 kW, then shorting the unused input to ground will keep the offset low (about 2.5 mV at the input, 50 mV at the output). For dc source resistances between these values we can eliminate excess offset by putting a resistor from the unused input to ground, equal in value to the dc source resistance. Of course all offset problems are eliminated if the input is capacitively coupled. When using the LM386 with higher gains (bypassing the 1.35 kW resistor between pins 1 and 8) it is necessary to bypass the unused input, preventing degradation of gain and possible instabilities. This is done with a 0.1 μF capacitor or a short to ground depending on the dc source resistance on the driven input. LM386 3 www.national.com Typical Performance Characteristics Quiescent Supply Current vs Supply Voltage DS006976-5 Power Supply Rejection Ratio (Referred to the Output) vs Frequency DS006976-12 Peak-to-Peak Output Voltage Swing vs Supply Voltage DS006976-13 Voltage Gain vs Frequency DS006976-14 Distortion vs Frequency DS006976-15 Distortion vs Output Power DS006976-16 Device Dissipation vs Output Power—4W Load DS006976-17 Device Dissipation vs Output Power—8W Load DS006976-18 Device Dissipation vs Output Power—16W Load DS006976-19 LM386 www.national.com 4 Typical Applications Amplifier with Gain = 20 Minimum Parts DS006976-3 Amplifier with Gain = 200 DS006976-4 Amplifier with Gain = 50 DS006976-6 Low Distortion Power Wienbridge Oscillator DS006976-7 Amplifier with Bass Boost DS006976-8 Square Wave Oscillator DS006976-9 LM386 5 www.national.com Typical Applications (Continued) Note 4: Twist Supply lead and supply ground very tightly. Note 5: Twist speaker lead and ground very tightly. Note 6: Ferrite bead in Ferroxcube K5-001-001/3B with 3 turns of wire. Note 7: R1C1 band limits input signals. Note 8: All components must be spaced very closely to IC. Frequency Response with Bass Boost DS006976-10 AM Radio Power Amplifier DS006976-11 LM386 www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted SO Package (M) Order Number LM386M-1 NS Package Number M08A LM386 7 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Lead (0.118” Wide) Molded Mini Small Outline Package Order Number LM386MM-1 NS Package Number MUA08A LM386 www.national.com 8 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com Dual-In-Line Package (N) Order Number LM386N-1, LM386N-3 or LM386N-4 NS Package Number N08E LM386 Low Voltage Audio Power Amplifier National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Communications and Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2011, Texas Instruments Incorporated LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1  2-kV ESD Protection for: − LM224K, LM224KA − LM324K, LM324KA − LM2902K, LM2902KV, LM2902KAV  Wide Supply Ranges − Single Supply . . . 3 V to 32 V (26 V for LM2902) − Dual Supplies . . . 1.5 V to 16 V (13 V for LM2902)  Low Supply-Current Drain Independent of Supply Voltage . . . 0.8 mA Typ  Common-Mode Input Voltage Range Includes Ground, Allowing Direct Sensing Near Ground  Low Input Bias and Offset Parameters − Input Offset Voltage . . . 3 mV Typ A Versions . . . 2 mV Typ − Input Offset Current . . . 2 nA Typ − Input Bias Current . . . 20 nA Typ A Versions . . . 15 nA Typ  Differential Input Voltage Range Equal to Maximum-Rated Supply Voltage . . . 32 V (26 V for LM2902)  Open-Loop Differential Voltage Amplification . . . 100 V/mV Typ  Internal Frequency Compensation description/ordering information These devices consist of four independent high-gain frequency-compensated operational amplifiers that are designed specifically to operate from a single supply over a wide range of voltages. Operation from split supplies also is possible if the difference between the two supplies is 3 V to 32 V (3 V to 26 V for the LM2902), and VCC is at least 1.5 V more positive than the input common-mode voltage. The low supply-current drain is independent of the magnitude of the supply voltage. Applications include transducer amplifiers, dc amplification blocks, and all the conventional operational-amplifier circuits that now can be more easily implemented in single-supply-voltage systems. For example, the LM124 can be operated directly from the standard 5-V supply that is used in digital systems and provides the required interface electronics, without requiring additional ±15-V supplies. PRODUCTION DATA information is current as of publication date. Copyright  2010, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1OUT 1IN− 1IN+ VCC 2IN+ 2IN− 2OUT 4OUT 4IN− 4IN+ GND 3IN+ 3IN− 3OUT LM124 . . . D, J, OR W PACKAGE LM124A . . . J OR W PACKAGE LM224, LM224A, LM224K, LM224KA . . . D OR N PACKAGE LM324, LM324K . . . D, N, NS, OR PW PACKAGE LM324A . . . D, DB, N, NS, OR PW PACKAGE LM324KA . . . D, N, NS, OR PW PACKAGE LM2902 . . . D, N, NS, OR PW PACKAGE LM2902K . . . D, DB, N, NS, OR PW PACKAGE LM2902KV, LM2902KAV . . . D OR PW PACKAGE (TOP VIEW) 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 4IN+ NC GND NC 3IN+ 1IN+ NC VCC NC 2IN+ LM124, LM124A . . . FK PACKAGE (TOP VIEW) 1IN− 1OUT NC 3IN− 4IN− 2IN− 2OUT NC NC − No internal connection 3OUT 4OUT On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ORDERING INFORMATION TA VIOmax AT 25°C MAX TESTED VCC PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP (N) Tube of 25 LM324N LM324N LM324KN LM324KN Tube of 50 LM324D Reel of 2500 LM324DR LM324 SOIC (D) Reel of 2500 LM324DRG3 Tube of 50 LM324KD LM324K 7 mV 30 V Reel of 2500 LM324KDR Reel of 2000 LM324NSR LM324 SOP (NS) Tube of 50 LM324KNS LM324K Reel of 2000 LM324KNSR Tube of 90 LM324PW L324 TSSOP (PW) Reel of 2000 LM324PWR Tube of 90 LM324KPW L324K 0°C to 70°C Reel of 2000 LM324KPWR PDIP (N) Tube of 25 LM324AN LM324AN Tube of 25 LM324KAN LM324KAN Tube of 50 LM324AD LM324A SOIC (D) Reel of 2500 LM324ADR Tube of 50 LM324KAD LM324KA Reel of 2500 LM324KADR 3 mV 30 V Reel of 2000 LM324ANSR LM324A SOP (NS) Tube of 50 LM324KANS LM324KA Reel of 2000 LM324KANSR SSOP (DB) Reel of 2000 LM324ADBR LM324A Tube of 90 LM324APW L324A TSSOP (PW) Reel of 2000 LM324APWR Tube of 90 LM324KAPW L324KA Reel of 2000 LM324KAPWR PDIP (N) Tube of 25 LM224N LM224N LM224KN LM224KN 5 mV 30 V Tube of 50 LM224D LM224 SOIC (D) Reel of 2500 LM224DR Tube of 50 LM224KD LM224K 25°C to 85°C Reel of 2500 LM224KDR −PDIP (N) Tube of 25 LM224AN LM224AN Tube of 25 LM224KAN LM224KAN 3 mV 30 V Tube of 50 LM224AD LM224A SOIC (D) Reel of 2500 LM224ADR Tube of 50 LM224KAD LM224KA Reel of 2500 LM224KADR † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 ORDERING INFORMATION (CONTINUED) TA VIOmax AT 25°C MAX TESTED VCC PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP (N) Tube of 25 LM2902N LM2902N Tube of 25 LM2902KN LM2902KN Tube of 50 LM2902D LM2902 SOIC (D) Reel of 2500 LM2902DR Tube of 50 LM2902KD LM2902K Reel of 2500 LM2902KDR Reel of 2000 LM2902NSR LM2902 26 V SOP (NS) Tube of 50 LM2902KNS LM2902K 7 mV Reel of 2000 LM2902KNSR −40°C to 125°C SSOP (DB) Tube of 80 LM2902KDB L2902K 40 125 Reel of 2000 LM2902KDBR Tube of 90 LM2902PW L2902 TSSOP (PW) Reel of 2000 LM2902PWR Tube of 90 LM2902KPW L2902K Reel of 2000 LM2902KPWR 32 V SOIC (D) Reel of 2500 LM2902KVQDR L2902KV TSSOP (PW) Reel of 2000 LM2902KVQPWR L2902KV 2 mV 32 V SOIC (D) Reel of 2500 LM2902KAVQDR L2902KA TSSOP (PW) Reel of 2000 LM2902KAVQPWR L2902KA CDIP (J) Tube of 25 LM124J LM124J CFP (W) Tube of 25 LM124W LM124W 5 mV 30 V LCCC (FK) Tube of 55 LM124FK LM124FK 55°C to 125°C SOIC (D) Tube of 50 LM124D −LM124 Reel of 2500 LM124DR CDIP (J) Tube of 25 LM124AJ LM124AJ 2 mV 30 V CFP (W) Tube of 25 LM124AW LM124AW LCCC (FK) Tube of 55 LM124AFK LM124AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. symbol (each amplifier) − + IN− IN+ OUT LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 schematic (each amplifier) To Other Amplifiers ≈6-μA Current Regulator VCC OUT GND IN− IN+ ≈100-μA Current Regulator ≈50-μA Current Regulator COMPONENT COUNT (total device) Epi-FET Transistors Diodes Resistors Capacitors 1 95 4 11 4 ≈6-μA Current Regulator † ESD protection cells - available on LM324K and LM324KA only † † LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† LM2902 ALL OTHER DEVICES UNIT Supply voltage, VCC (see Note 1) ±13 or 26 ±16 or 32 V Differential input voltage, VID (see Note 2) ±26 ±32 V Input voltage, VI (either input) −0.3 to 26 −0.3 to 32 V Duration of output short circuit (one amplifier) to ground at (or below) TA = 25°C, VCC ≤ 15 V (see Note 3) Unlimited Unlimited D package 86 86 DB package 96 96 Package thermal impedance, θJA (see Notes 4 and 5) N package 80 80 °C/W NS package 76 76 PW package 113 113 FK package 5.61 Package thermal impedance, JC (see Notes 6 and 7) J package 15.05 °C/W W package 14.65 Operating virtual junction temperature, TJ 150 150 °C Case temperature for 60 seconds FK package 260 °C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds J or W package 300 300 °C Storage temperature range, Tstg −65 to 150 −65 to 150 °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values (except differential voltages and VCC specified for the measurement of IOS) are with respect to the network GND. 2. Differential voltages are at IN+, with respect to IN−. 3. Short circuits from outputs to VCC can cause excessive heating and eventual destruction. 4. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/JA. Operating at the absolute maximum TJ of 150°C can affect reliability. 5. The package thermal impedance is calculated in accordance with JESD 51-7. 6. Maximum power dissipation is a function of TJ(max), JC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) − TC)/JC. Operating at the absolute maximum TJ of 150°C can affect reliability. 7. The package thermal impedance is calculated in accordance with MIL-STD-883. ESD protection TEST CONDITIONS TYP UNIT Human-Body Model LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV ±2 kV LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics at specified free-air temperature, VCC = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS† TA LM124 LM224 LM324 LM324K UNIT ‡ MIN TYP§ MAX MIN TYP§ MAX V Input offset voltage VCC = 5 V to MAX, 25°C 3 5 3 7 VIO mV VIC = VICRmin, VO = 1.4 V Full range 7 9 I Input offset current V 1 4 V 25°C 2 30 2 50 IIO VO = 1.4 nA Full range 100 150 I Input bias current V 1 4 V 25°C −20 −150 −20 −250 IIB VO = 1.4 nA Full range −300 −500 25°C 0 to 0 to V Common-mode V 5 V to MAX VCC − 1.5 VCC − 1.5 VICR V input voltage range VCC = Full range 0 to 0 to VCC − 2 VCC − 2 RL = 2 kΩ 25°C VCC − 1.5 VCC − 1.5 V High-level RL = 10 kΩ 25°C VOH V output voltage V MAX RL = 2 kΩ Full range 26 26 p g VCC = RL ≥ 10 kΩ Full range 27 28 27 28 VOL Low-level output voltage RL ≤ 10 kΩ Full range 5 20 5 20 mV A Large-signal differential voltage VCC = 15 V, VO = 1 V to 11 V, 25°C 50 100 25 100 AVD V/mV amplification RL ≥ 2 kΩ Full range 25 15 CMRR Common-mode rejection ratio VIC = VICRmin 25°C 70 80 65 80 dB k Supply-voltage kSVR rejection ratio 25°C 65 100 65 100 dB (ΔVCC /ΔVIO) VO1/VO2 Crosstalk attenuation f = 1 kHz to 20 kHz 25°C 120 120 dB VCC = 15 V, V 1 V Source CC 25°C −20 −30 −60 −20 −30 −60 VID = V, VO = 0 Full range −10 −10 mA IO Output current VCC = 15 V, V 1 V Sink 25°C 10 20 10 20 O p CC VID = −V, VO = 15 V Full range 5 5 VID = −1 V, VO = 200 mV 25°C 12 30 12 30 μA IOS Short-circuit output current VCC at 5 V, GND at −5 V VO = 0, 25°C ±40 ±60 ±40 ±60 mA Supply current VO = 2.5 V, No load Full range 0.7 1.2 0.7 1.2 ICC (four amplifiers) VCC = MAX, VO = 0.5 VCC, No load Full range 1.4 3 1.4 3 mA † All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. MAX VCC for testing purposes is 26 V for LM2902 and 30 V for the others. ‡ Full range is −55°C to 125°C for LM124, −25°C to 85°C for LM224, and 0°C to 70°C for LM324. § All typical values are at TA = 25°C. LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 electrical characteristics at specified free-air temperature, VCC = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS† T ‡ LM2902 LM2902V TA UNIT MIN TYP§ MAX MIN TYP§ MAX V 5 V t Non-A-suffix 25°C 3 7 3 7 V Input offset voltage VCC = to devices Full range 10 10 VIO MAX, mV VIC = VICRmin, V 1 4 V A-suffix 25°C 1 2 IC ICR VO = 1.4 devices Full range 4 ΔVIO/ΔT Input offset voltage temperature drift RS = 0 Ω Full range 7 μV/°C I Input offset current V 1 4 V 25°C 2 50 2 50 IIO VO = 1.4 nA Full range 300 150 ΔIIO/ΔT Input offset current temperature drift Full range 10 pA/°C I Input bias current V 1 4 V 25°C −20 −250 −20 −250 IIB VO = 1.4 nA Full range −500 −500 25°C 0 to 0 to V Common-mode V 5 V to MAX VCC − 1.5 VCC − 1.5 VICR V input voltage range VCC = Full range 0 to 0 to VCC − 2 VCC − 2 RL = 2 kΩ 25°C V High-level RL = 10 kΩ 25°C VCC − 1.5 VCC − 1.5 VOH V output voltage V MAX RL = 2 kΩ Full range 22 26 p g VCC = RL ≥ 10 kΩ Full range 23 24 27 VOL Low-level output voltage RL ≤ 10 kΩ Full range 5 20 5 20 mV A Large-signal differential voltage VCC = 15 V, VO = 1 V to 11 V, 25°C 25 100 25 100 AVD V/mV amplification RL ≥ 2 kΩ Full range 15 15 CMRR Common-mode rejection ratio VIC = VICRmin 25°C 50 80 60 80 dB k Supply-voltage kSVR rejection ratio 25°C 50 100 60 100 dB (ΔVCC /ΔVIO) VO1/VO2 Crosstalk attenuation f = 1 kHz to 20 kHz 25°C 120 120 dB VCC = 15 V, V 1 V S CC 25°C −20 −30 −60 −20 −30 −60 VID = V, VO = 0 Source Full range −10 −10 mA IO Output current VCC = 15 V, V 1 V Sink 25°C 10 20 10 20 CC VID = −V, VO = 15 V Full range 5 5 VID = −1 V, VO = 200 mV 25°C 30 12 40 μA IOS Short-circuit output current VCC at 5 V, GND at −5 V VO = 0, 25°C ±40 ±60 ±40 ±60 mA Supply current VO = 2.5 V, No load Full range 0.7 1.2 0.7 1.2 ICC (four amplifiers) VCC = MAX, VO = 0.5 VCC, No load Full range 1.4 3 1.4 3 mA † All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. MAX VCC for testing purposes is 26 V for LM2902 and 32 V for LM2902V. ‡ Full range is −40°C to 125°C for LM2902. § All typical values are at TA = 25°C. LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − MARCH 2010 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics at specified free-air temperature, VCC = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS† TA ‡ LM124A LM224A LM324A, T LM324KA UNIT A MIN TYP§ MAX MIN TYP§ MAX MIN TYP § MAX V Input offset voltage VCC = 5 V to 30 V, 25°C 2 2 3 2 3 VIO mV VIC = VICRmin, VO = 1.4 V Full range 4 4 5 I Input offset current V 1 4 V 25°C 10 2 15 2 30 IIO VO = 1.4 nA Full range 30 30 75 I Input bias current V 1 4 V 25°C −50 −15 −80 −15 −100 IIB VO = 1.4 nA Full range −100 −100 −200 V Common-mode input V 30 V 25°C 0 to VCC − 1.5 0 to VCC − 1.5 0 to VCC − 1.5 VICR V voltage range VCC = Full range 0 to VCC − 2 0 to VCC − 2 0 to VCC − 2 RL = 2 kΩ 25°C VCC − 1.5 VCC − 1.5 VCC − 1.5 VOH High-level output voltage V 30 V High RL = 2 kΩ Full range 26 26 26 V VCC = RL ≥ 10 kΩ Full range 27 27 28 27 28 VOL Low-level output voltage RL ≤ 10 kΩ Full range 20 5 20 5 20 mV A Large-signal differential VCC = 15 V, VO = 1 V to 11 V, 25°C 50 100 50 100 25 100 AVD V/mV voltage amplification RL ≥ 2 kΩ Full range 25 25 15 CMRR Common-mode rejection ratio VIC = VICRmin 25°C 70 70 80 65 80 dB kSVR Supply-voltage rejection ratio (ΔVCC /ΔVIO) 25°C 65 65 100 65 100 dB VO1/VO2 Crosstalk attenuation f = 1 kHz to 20 kHz 25°C 120 120 120 dB VCC = 15 V, V 1 V Source 25°C −20 −20 −30 −60 −20 −30 −60 VID = V, VO = 0 Full range −10 −10 −10 mA IO Output current VCC = 15 V, V 1 V Sink 25°C 10 10 20 10 20 VID = −V, VO = 15 V Full range 5 5 5 VID = −1 V, VO = 200 mV 25°C 12 12 30 12 30 μA IOS Short-circuit output current VCC at 5 V, GND at −5 V, VO = 0 25°C ±40 ±60 ±40 ±60 ±40 ±60 mA Supply current VO = 2.5 V, No load Full range 0.7 1.2 0.7 1.2 0.7 1.2 ICC (four amplifiers) VCC = 30 V, VO = 15 V, No load Full range 1.4 3 1.4 3 1.4 3 mA † All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. ‡ Full range is −55°C to 125°C for LM124A, −25°C to 85°C for LM224A, and 0°C to 70°C for LM324A. § All typical values are at TA = 25°C. LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066T − SEPTEMBER 1975 − REVISED MARCH 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 operating conditions, VCC = ±15 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT SR Slew rate at unity gain RL = 1 MΩ, CL = 30 pF, VI = ±10 V (see Figure 1) 0.5 V/μs B1 Unity-gain bandwidth RL = 1 MΩ, CL = 20 pF (see Figure 1) 1.2 MHz Vn Equivalent input noise voltage RS = 100 Ω, VI = 0 V, f = 1 kHz (see Figure 2) 35 nV/√Hz VO − + RL CL VI VCC+ VCC− Figure 1. Unity-Gain Amplifier VO − + 100 Ω VCC+ VCC− RS 900 Ω VI = 0 V Figure 2. Noise-Test Circuit PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 5962-7704301VCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-7704301VC A LM124JQMLV 5962-9950403V9B ACTIVE XCEPT KGD 0 100 TBD Call TI N / A for Pkg Type -55 to 125 5962-9950403VCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9950403VC A LM124AJQMLV 77043012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043012A LM124FKB 7704301CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301CA LM124JB 7704301DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301DA LM124WB 77043022A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043022A LM124AFKB 7704302CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302CA LM124AJB 7704302DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302DA LM124AWB JM38510/11005BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510 /11005BCA LM124ADR OBSOLETE SOIC D 14 TBD Call TI Call TI -55 to 125 LM124AFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043022A LM124AFKB LM124AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 LM124AJ LM124AJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302CA LM124AJB LM124AWB ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704302DA LM124AWB LM124D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124 LM124DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124 PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM124DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124 LM124DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 LM124 LM124FKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 77043012A LM124FKB LM124J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 LM124J LM124JB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301CA LM124JB LM124N OBSOLETE PDIP N 14 TBD Call TI Call TI -55 to 125 LM124W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 LM124W LM124WB ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 7704301DA LM124WB LM224AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A LM224ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A LM224ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A LM224ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -25 to 85 LM224A LM224ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A LM224ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224A LM224AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224AN LM224ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224AN LM224D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224 LM224DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224 LM224DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224 PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM224DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -25 to 85 LM224 LM224DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224 LM224DRG3 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -25 to 85 LM224 LM224DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224 LM224KAD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224KA LM224KAN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224KAN LM224KANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224KAN LM224KDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224K LM224KDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224K LM224KDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 LM224K LM224KN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224KN LM224KNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224KN LM224N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224N PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 4 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM224NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 LM224N LM2902D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DRG3 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM2902 LM2902DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902KAVQDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA LM2902KAVQDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA LM2902KAVQPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA LM2902KAVQPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KA LM2902KD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KDB ACTIVE SSOP DB 14 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KDBE4 ACTIVE SSOP DB 14 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KDBG4 ACTIVE SSOP DB 14 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KDE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 5 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM2902KDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 LM2902KN LM2902KNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 LM2902KN LM2902KNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KNSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KNSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902K LM2902KPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902K LM2902KVQDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV LM2902KVQDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV LM2902KVQPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV LM2902KVQPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902KV PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 6 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM2902N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 LM2902N LM2902NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 LM2902N LM2902NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM2902 LM2902PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 125 LM2902PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWRE4 ACTIVE TSSOP PW 14 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWRG3 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L2902 LM2902PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 L2902 LM2902QN OBSOLETE PDIP N 14 TBD Call TI Call TI -40 to 125 LM324AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI LM324ADBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 7 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM324ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 LM324A LM324ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324AN LM324ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324AN LM324ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324A LM324APW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A LM324APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A LM324APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A LM324APWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI LM324APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 L324A LM324APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A LM324APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324A LM324D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 8 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM324DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 LM324 LM324DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324DRG3 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LM324 LM324DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324KAD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KAN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324KAN LM324KANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324KAN LM324KANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324KA LM324KAPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA LM324KAPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 9 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM324KAPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA LM324KAPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA LM324KAPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA LM324KAPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324KA LM324KD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KDE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324KN LM324KNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324KN LM324KNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KNSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KNSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324K LM324KPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K LM324KPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K LM324KPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 10 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM324KPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K LM324KPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K LM324KPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324K LM324N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU | CU SN N / A for Pkg Type 0 to 70 LM324N LM324NE3 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU SN N / A for Pkg Type 0 to 70 LM324N LM324NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 LM324N LM324NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM324 LM324PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324 LM324PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324 LM324PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324 LM324PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI 0 to 70 LM324PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 L324 LM324PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324 LM324PWRG3 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 L324 LM324PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 L324 LM324Y OBSOLETE DIESALE Y 0 TBD Call TI Call TI M38510/11005BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510 /11005BCA PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 11 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM124, LM124-SP, LM124M, LM2902 : • Catalog: LM124, LM124 • Automotive: LM2902-Q1 PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Addendum-Page 12 • Enhanced Product: LM2902-EP • Military: LM124M, LM124M • Space: LM124-SP, LM124-SP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Enhanced Product - Supports Defense, Aerospace and Medical Applications • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant LM124DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224ADR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM224ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM224KADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM224KDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM2902DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM2902DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM2902DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM2902DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM2902KAVQPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM2902KAVQPWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM2902KDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM2902KNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 LM2902KPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2013 Pack Materials-Page 1 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant LM2902KVQPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM2902KVQPWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM2902NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 LM2902PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM2902PWRG3 TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 LM2902PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 LM324ADR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM324ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 LM324APWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 LM324APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324DR SOIC D 14 2500 330.0 16.4 6.55 9.05 2.1 8.0 16.0 Q1 LM324DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM324DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 LM324DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324KADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324KANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 LM324KAPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324KDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 LM324KNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 LM324KPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM324PWRG3 TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 LM324PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2013 Pack Materials-Page 2 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM124DR SOIC D 14 2500 367.0 367.0 38.0 LM224ADR SOIC D 14 2500 364.0 364.0 27.0 LM224ADR SOIC D 14 2500 333.2 345.9 28.6 LM224ADRG4 SOIC D 14 2500 333.2 345.9 28.6 LM224ADRG4 SOIC D 14 2500 367.0 367.0 38.0 LM224DR SOIC D 14 2500 367.0 367.0 38.0 LM224DRG3 SOIC D 14 2500 364.0 364.0 27.0 LM224KADR SOIC D 14 2500 367.0 367.0 38.0 LM224KDR SOIC D 14 2500 367.0 367.0 38.0 LM2902DR SOIC D 14 2500 333.2 345.9 28.6 LM2902DR SOIC D 14 2500 367.0 367.0 38.0 LM2902DRG3 SOIC D 14 2500 364.0 364.0 27.0 LM2902DRG4 SOIC D 14 2500 333.2 345.9 28.6 LM2902KAVQPWR TSSOP PW 14 2000 367.0 367.0 35.0 LM2902KAVQPWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 LM2902KDR SOIC D 14 2500 367.0 367.0 38.0 LM2902KNSR SO NS 14 2000 367.0 367.0 38.0 LM2902KPWR TSSOP PW 14 2000 367.0 367.0 35.0 LM2902KVQPWR TSSOP PW 14 2000 367.0 367.0 35.0 LM2902KVQPWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2013 Pack Materials-Page 3 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM2902NSR SO NS 14 2000 367.0 367.0 38.0 LM2902PWR TSSOP PW 14 2000 367.0 367.0 35.0 LM2902PWRG3 TSSOP PW 14 2000 364.0 364.0 27.0 LM2902PWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 LM324ADBR SSOP DB 14 2000 367.0 367.0 38.0 LM324ADR SOIC D 14 2500 364.0 364.0 27.0 LM324ADR SOIC D 14 2500 367.0 367.0 38.0 LM324ADRG4 SOIC D 14 2500 367.0 367.0 38.0 LM324ANSR SO NS 14 2000 367.0 367.0 38.0 LM324APWR TSSOP PW 14 2000 364.0 364.0 27.0 LM324APWR TSSOP PW 14 2000 367.0 367.0 35.0 LM324APWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 LM324DR SOIC D 14 2500 385.0 388.0 194.0 LM324DR SOIC D 14 2500 364.0 364.0 27.0 LM324DR SOIC D 14 2500 333.2 345.9 28.6 LM324DRG3 SOIC D 14 2500 364.0 364.0 27.0 LM324DRG4 SOIC D 14 2500 333.2 345.9 28.6 LM324KADR SOIC D 14 2500 367.0 367.0 38.0 LM324KANSR SO NS 14 2000 367.0 367.0 38.0 LM324KAPWR TSSOP PW 14 2000 367.0 367.0 35.0 LM324KDR SOIC D 14 2500 367.0 367.0 38.0 LM324KNSR SO NS 14 2000 367.0 367.0 38.0 LM324KPWR TSSOP PW 14 2000 367.0 367.0 35.0 LM324PWR TSSOP PW 14 2000 367.0 367.0 35.0 LM324PWRG3 TSSOP PW 14 2000 364.0 364.0 27.0 LM324PWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2013 Pack Materials-Page 4 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01 28 PINS SHOWN Gage Plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 Seating Plane 7,90 9,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 A 28 1 16 20 6,50 6,50 14 0,05 MIN 5,90 5,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 0,15 M 0°–8° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated User's Guide SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U This User’s Guide describes the operation, use, features and characteristics of the TLV320AIC3254EVMU. This small form factor evaluation module (EVM) is a programmable USB audio device that features the TLV320AIC3254 Audio Codec with miniDSP. Figure 1. TLV321AIC3254EVM-U Angle View The following related documents are available through the Texas Instruments Web site at www.ti.com. EVM-Compatible Device Data Sheets Device Literature Number TLV320AIC3254 SLAS549 TAS1020B SLES025 Contents 1 EVM Overview ............................................................................................................... 3 2 EVM Description and Basics .............................................................................................. 4 3 AIC3254EVM-U Control Software ........................................................................................ 7 Appendix A TLV320AIC3254EVM Schematic ............................................................................... 15 Appendix B TLV320AIC3254EVM Bill of Materials ......................................................................... 16 Appendix C Writing Scripts ..................................................................................................... 18 List of Figures 1 TLV321AIC3254EVM-U Angle View ..................................................................................... 1 2 Bottom and Top Views ..................................................................................................... 4 3 Default Input and Output Signals ......................................................................................... 5 4 Sounds and Audio Devices Properties................................................................................... 6 5 Main Panel Window ........................................................................................................ 8 6 Compatibility Tab............................................................................................................ 9 7 Playback Configurations and Controls.................................................................................. 10 8 Associated Script and Description ...................................................................................... 10 9 Tip Strip Example.......................................................................................................... 11 10 Status Flags Panel ........................................................................................................ 12 11 Register Tables Panel .................................................................................................... 13 SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 1 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com 12 Command Line interface Panel.......................................................................................... 14 List of Tables 1 TLV320AIC3254EVM Bill of Materials .................................................................................. 16 2 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com EVM Overview 1 EVM Overview 1.1 Features • Small USB Stick form factor EVM for the TLV320AIC3254 Audio Codec. • USB connection to the PC provides power, control and streaming audio for easy evaluation. • Pre-programmed EEPROM boots the TLV320AIC3254 as a fully functional USB Audio Device when connected to a PC. • Easy to use AIC3254 Control Software (CS) configures and controls the TLV320AIC3254. The TLV320AIC3254EVM-U is a universal serial bus (USB)-based audio device for use with a personal computer running the Microsoft Windows™ XP operating system 1.2 Introduction The TLV320AIC3254EVM-U is a USB Audio Device with programmable inputs and outputs, effects and extensive routing capabilities. It is a simple platform to evaluate the TLV320AIC3254 miniDSP Audio Codec. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 3 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated EVM Description and Basics www.ti.com 2 EVM Description and Basics This section provides information on the analog input and output, digital control, power, and general connection of the TLV320AIC3254EVM-U. 2.1 TLV320AIC3254EVM-U Hardware Description The TLV320AIC3254EVM-U has 2 stereo analog input connectors (Line-in and Mic-in) and 2 stereo analog output connectors (Line-Out and Headphone-Out) that are routed to the TLV320AIC3254. Digital audio as well as control data communicated between the PC and the EVM are interpreted by the TAS1020B USB Streaming Controller. Control data is communicated to the TLV320AIC3254 via the I2C protocol; audio data is communicated via the I2S protocol. An on-board 32KB EEPROM is capable of storing TLV320AIC3254 commands (scripts) as well as the TAS1020B firmware. A push button is provided to cycle between scripts along with an LED that provides the user feedback regarding the script that is currently loaded. The EEPROM Manager in the AIC3254 CS is used to write new scripts into the EEPROM. Figure 2. Bottom and Top Views 4 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com EVM Description and Basics The table below summarizes the audio jacks available to connect analog inputs and outputs to the TLV320AIC3254, as well as a switch. Designator Label Associated Pin Description J1 L IN (LINE IN) IN2_L / IN2_R Line Input. External electric microphone input. J2 MIC IN (MIC IN) IN3_L / IN3_R MICBIAS is connected to both tip and ring through resistors. Line output. Only high impedance loads should J3 L OUT (LINE OUT) LOL / LOR be connected to this output (e.g. external Class-D amplifier). J4 HP OUT (HEADPHONE) HPL / HPR Headphone output. Cycles through scripts SW1 SW1 N/A loaded in the on-board EEPROM. 2.2 Getting Started Evaluation can start right out of the box. Simply connect the TLV320AIC3254EVM-U to an available USB port, connect stereo headphones to HP OUT and start playing audio with any media player. By default, when the TLV320AIC3254EVM-U is connected, the TLV320AIC3254 is automatically configured to play and record stereo audio through all four jacks, as shown below. Figure 3. Default Input and Output Signals To adjust playback volume, open “Sounds and Audio Devices” in the “Control Panel” and click the “Volume” button of the “Sound playback” section of the “Audio” tab. Ensure USB-miniEVM is selected as the default playback and recording device. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 5 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated EVM Description and Basics www.ti.com Figure 4. Sounds and Audio Devices Properties Pressing SW1 on the EVM once will set a flat response at the outputs (LED D1 blinks once). Pressing SW1 again will switch to bass and treble boost (LED D1 blinks twice). The following section explains the software installation procedure which allows programming of the audio device. 6 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com AIC3254EVM-U Control Software 3 AIC3254EVM-U Control Software The AIC3254 Control Software (CS) is an intuitive, easy-to-use, powerful tool to learn, evaluate, and control the TLV320AIC3254. This tool was specifically designed to make learning the TLV320AIC3254 software easy. The following sections describe the operation and installation of this software NOTE: For configuration of the codec, the TLV320AIC3254 block diagram located in SLAS549 is a good reference to help determine the signal routing. 3.1 AIC3254EVM-U CS Setup This section provides setup instructions for the AIC3254EVM-U CS. To install the AIC3254EVM-U software: 1. Download the latest version of the AIC3254EVM-U Control Software (CS) located in the TLV320AIC3254EVM-U Product Folder. 2. Open the self-extracting installation file. 3. Extract the software to a known folder. 4. Install the EVM software by double-clicking the Setup executable, and follow the directions. The user may be prompted to restart their computer. This installs all the AIC3254EVM-U software and required drivers onto the PC. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 7 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated AIC3254EVM-U Control Software www.ti.com 3.2 AIC3254EVM-U CS Usage The following sections describe the AIC3254EVM-U CS usage. 3.2.1 Main Panel Window The Firmware Name and Version boxes provide The Main Panel window, shown in the figure below, information about the firmware loaded into the EVM's provides easy access to all the features of the EEPROM. AIC3254 CS. The USB-MODEVM Interface drop-down menu allows the user to select which communication protocol the TAS1020B USB Controller uses to communicate with the TLV320AIC3254. The TLV320AIC3254 supports I2C Standard, I2C Fast, and 8-bit register SPI. However, this EVM only supports I2C. The USB Interface selection is global to all panels, including the Command-Line Interface. The Panel Selection Tree provides access to typical configurations, features, and other panels that allow the user to control the TLV320AIC3254. The tree is divided into several categories which contain items that pop up panels. A panel can be opened by double-clicking any item inside a category in the Panel Selection Tree. Below the Panel Selection Tree are three buttons that pop up the following: • Status Flags - Allows the user to monitor the TLV320AIC3254 status flags. • Register Tables - A tool to monitor register pages. • Command-Line Interface - A tool to execute/generate scripts and monitor register activity. The USB LED indicates if the EVM is recognized by the software and the ACTIVITY LED illuminates every time a command request is sent. The dialog box at the bottom of the Main Panel provides feedback of the current status of the software. Figure 5. Main Panel Window 8 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com AIC3254EVM-U Control Software If running the software in Windows Vista or Windows 7, right-click the AIC3254EVM-U CS shortcut and select Properties. Configure the Compatibility tab as shown in Figure 6 Figure 6. Compatibility Tab 3.2.2 Typical Configurations This category can help users to quickly become familiar with the TLV320AIC3254. Each of the panels that can be accessed through this menu have controls relevant to the selected configuration; a tab shows the script that will be loaded for that particular configuration. Each script includes a brief description of the selected configuration. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 9 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated AIC3254EVM-U Control Software www.ti.com Figure 7. Playback Configurations and Controls Figure 8. Associated Script and Description 3.2.3 Control Categories The Digital Settings, Analog Settings, and Signal Processing categories provide control of many registers and other features of the TLV320AIC3254 . These categories are intended for the advanced user. Hovering the mouse cursor on top of a control displays a tip strip that contains page, register, and bit information. As an example, hovering on top of IN1_R of the Audio Inputs panel, as shown in Figure 9 displays p1_r55_b7-6 which means that this control writes to Page 1/Register 55/Bits D7 to D6. 10 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com AIC3254EVM-U Control Software Figure 9. Tip Strip Example Before changing a control, see the data sheet to ensure that a particular control is compatible with the current state of the codec. As an example, some controls in the Analog Setup panel must be modified in a particular order as described in the data sheet. Other controls must only be modified with a specific hardware setup, such as powering up the AVDD LDO. All controls update their status with respect to the register contents in the following conditions: • A panel is opened. • The Execute Command Buffer button in the Command-Line Interface is pressed (if enabled). • The Refresh button at the bottom right of a panel is pressed SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 11 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated AIC3254EVM-U Control Software www.ti.com 3.2.4 Status Flags Panel The TLV320AIC3254 status flags can monitored in the Status Flags panel (Figure 10) which is located below in the Panel Selection Tree . Pressing the POLL button continuously reads all the registers relevant to each flag and updates those flags accordingly. The rate at which the registers are read can be modified by changing the value in the Polling Interval numeric control. Note that a smaller interval reduces responsiveness of other controls, especially volume sliders, due to bandwidth limitations. By default, the polling interval is 200 ms and can be set to a minimum of 20 ms. The Sticky Flags tab contains indicators whose corresponding register contents clear every time a read is performed to that register. To read all the sticky flags, click the Read Sticky Flags button. Figure 10. Status Flags Panel 12 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com AIC3254EVM-U Control Software 3.2.5 Register Tables Panel The contents of configuration and coefficient pages of the TLV320AIC3254 can be accessed through the Register Tables panel (Figure 11). The Page Number control changes to the page to be displayed in the register table. The register table contains page information such as the register name, reset value, current value, and a bitmap of the current value. The contents of the selected page can be exported into a spreadsheet by clicking the Dump to Spreadsheet button. Figure 11. Register Tables Panel SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM-U 13 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated AIC3254EVM-U Control Software www.ti.com 3.2.6 Command-line Interface Panel The Command-Line Interface panel provides a means to communicate with the TLV320AIC3254 using a simple scripting language (described in Appendix C). The TAS1020B USB Controller handles all communication between the PC and the TLV320AIC3254. A script is loaded into the command buffer, either by loading a script file using the File menu or by pasting text from the clipboard using the Ctrl-V key combination (Figure 12). When the command buffer is executed, the return data packets which result from each individual command are displayed in the Command History control. This control is an array (with a maximum size of 100 elements) that contains information about each command as well as status. The Interface box displays the interface used for a particular command in the Command History array. The Command box displays the type of command executed (i.e., write, read) for a particular interface. The Flag Retries box displays the number of read iterations performed by a Wait for Flag command (see Appendix C for details). The Register Data array displays the register number and data bytes that correspond to a particular command. The Information tab provides additional information related to the Command History as well as additional settings. The Syntax and Examples tabs provide useful information related to the scripting language. The File menu provides some options for working with scripts. The first option, Open Script File..., loads a command file script into the command buffer. This script can then be executed by pressing the Execute Command Buffer button. The contents of the Command Buffer can be saved using the Save Script File... option. Both the Command Buffer and Command History can be cleared by clicking their corresponding Clear buttons Figure 12. Command Line interface Panel 14 TLV320AIC3254EVM-U SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com Appendix A TLV320AIC3254EVM Schematic The schematic diagram for the TLV320AIC3254EVM is provided as a reference. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM Schematic 15 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated DOUT DIN WCLK BCLK MCLK SCLK SDA SCL RESET~ DESIGN LEAD: EDGE #: DATE: FILENAME: SCH REV: PCB REV: SHEET: OF: LEAD # DRAWN BY: PAGE INFO: TI FILENAME DATE OF BY SHEET REV REV C12 0402 0.1ufd/6.3V C16 0603 10ufd/6.3V GND TLV320AIC3254RHB U1 QFN32-RHB 25 26 27 28 29 30 31 32 6 8 4 1 2 3 5 7 16 15 14 13 12 11 10 9 21 24 22 23 19 20 18 17 C15 0805 22ufd/6.3V C11 0402 0.1ufd/6.3V GND GND GND C5 0603 0.47ufd/16V C6 0603 0.47ufd/16V GND C13 0603 .047ufd/25V C9 0603 1.0ufd/16V C14 0603 .047ufd/25V C8 0603 1.0ufd/16V GND GND GND C10 0805 22ufd/6.3V C7 0402 0.1ufd/6.3V GND GND GND C1 0603 0.47ufd/16V C2 0603 0.47ufd/16V C3 0603 10ufd/6.3V GND R4 0603 4.7K +3.3V +3.3V +3.3V J1 LEFT RIGHT Shield 2 4 1 3 6 5 J2 LEFT RIGHT Shield 2 4 1 3 6 5 J3 LEFT RIGHT Shield 2 4 1 3 6 5 J4 LEFT RIGHT Shield 2 4 1 3 6 5 C17 1210 100ufd/6.3V C18 1210 100ufd/6.3V R1 0603 1.2K R2 0603 1.2K C4 0402 0.1ufd/6.3V TLV320AIC3254RHB U1 41 40 39 38 37 36 35 34 33 QFN32-RHB GND GND GND GND GND GND GND GND GND GND C35 0603 10ufd/6.3V R3 100 0603 R5 100 0603 TLV320AIC3254_RHB_USB_EVM TLV320AIC3254_RHB_USB_EVM STEVE LEGGIO JULY 09, 2009 B B 1 4 TLV320AIC3254_RHB_USB_EVM SL LINE IN MIC IN LINE OUT HEADPHONE 6508852 SDA SCL DOUT WCLK BCLK DIN MCLK SCLK RESET~ LEAD # TI FILENAME DATE OF DRAWN BY SHEET PCB REV SCH REV BY: SHEET: OF: REV: REV: FILENAME: DATE: DESIGN LEAD: EDGE #: PAGE INFO: U2 13 14 15 17 18 19 20 22 31 30 29 27 26 25 23 24 32 34 35 36 40 39 38 37 21 8 4 28 16 33 42 41 12 11 10 9 7 6 5 45 44 43 2 1 48 3 47 46 R9 0603 1.50K C26 0603 47pfd/50v C27 0603 47pfd/50v C22 0603 1000pfd/50V 1 2 3 4 5 6 7 8 J5 TYPEA_SMT-RA NC NC CASE CASE Data+ GND +5V Data- R12 0603 100K C30 0603 1.0ufd/16V C28 0402 0.1ufd/6.3V C25 0402 0.1ufd/6.3V C29 0402 0.1ufd/6.3V C24 0402 0.1ufd/6.3V D1 0805 Yellow C23 0805 100pfd/50V C19 0402 0.1ufd/6.3V +3.3V GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +5V +5V +3.3V GND GND GND GND C33 0603 0.1ufd/50V C34 0805 10ufd/16V C32 0805 10ufd/16V 1 2 3 4 Y1 SMT-8002 6MHz/3.3V Vcc OUT OE GND GND +3.3V 1 2 SW1 GND C31 0603 0.1ufd/50V R14 0603 10K +3.3V GND +5V VR1 5 3 2 1 SOT230DBV5 3.3V/400mA 4 1 2 3 4 5 6 7 8 U3 MSOP8-DGK R13 0603 649 R8 0603 30.9K R10 0603 27.4 R11 0603 27.4 R6 0603 2.7K/5% R7 0603 2.7K/5% EEPROM USB INPUT +5.0V USB INPUT +3.3V OUTPUT POWER SUPPLY TLV320AIC3254_RHB_USB_EVM SL 2 4 B B JULY 09, 2009 STEVE LEGGIO TLV320AIC3254_RHB_USB_EVM TLV320AIC3254_RHB_USB_EVM GPIO 6508852 www.ti.com Appendix B TLV320AIC3254EVM Bill of Materials The complete bill of materials for the TLV320AIC3254EVM is provided as a reference. Table 1. TLV320AIC3254EVM Bill of Materials PCB Qty Value Ref Des Description Vendor Part number 1 U1 ULTRA LO PWR ST AUDIO CODEC Texas TLV320AIC3254 W/EMBEDDED MINI DSP QFN32- Instruments RHB RHB ROHS RESISTORS Qty Value Ref Des Description Vendor Part number 1 1.5k R9 RESISTOR SMD0603 1.50K OHM DIGI-KEY P1.50KHCT 1% THICK FILM 1/10W ROHS 3 100k R3,R5,R12 RESISTOR SMD0603 100K OHM 1% DIGI-KEY P100KHCT THICK FILM 1/10W ROHS 1 1.7k R4 RESISTOR SMD0603 4.7K OHMS DIGI-KEY P4.7KGCT 1% 1/10W ROHS 1 10k R14 RESISTOR SMD0603 10K 5% 1/10W DIGI-KEY P10KGCT ROHS 2 1.2k R1,R2 RESISTOR SMD0603 1.2K OHMS DIGI-KEY P1.2KGCT 5% 1/10W ROHS 1 649 R13 RESISTOR SMD0603 THICK FILM DIGI-KEY 311-649HRCT 649 OHMS 1% 1/10W ROHS 1 30.9k R8 RESISTOR SMD0603 30.9K OHMS 541-30.9KHCT 1% 1/10W ROHS 2 27.4k R10,R11 RESISTOR SMD0603 27.4 OHMS DIGI-KEY P27.4HCT 1% 1/10W ROHS 2 2.7k R6,R7 RESISTOR SMD0603 2.7K OHMS DIGI-KEY P2.7KGCT 5% 1/10W ROHS 2 100 R3,R5 RESISTOR SMD0603 100 OHM DIGI-KEY 541-100HCT 1/10W 1% ROHS CAPACITORS Qty Value Ref Des Description Vendor Part number 9 0.1μF C4,C7,C11,C12,C19,C24,C25,C28,C29 CAP SMD0402 CERM 0.1UFD 6.3V DIGI-KEY 445-1266-1 10% X5R ROHS 3 10μF C3,C16, C35 CAP SMD0603 CERM 10UFD 6.3V DIGI-KEY PCC2395CT 20% X5R ROHS 2 22μF C10,C15 CAP SMD0805 CERM 22UFD 6.3V DIGI-KEY 445-1422-1 20% X5R ROHS 2 47pF C26,C27 CAP SMD0603 CERM 47PFD 50V DIGI-KEY PCC470ACVCT 5% NPO ROHS 1 1000pF C22 CAP SMD0603 CERM 1000PFD 50V DIGI-KEY 445-1293-1 5% COG ROHS 1 1μF C30 CAP SMD0603 CERM 1.0UFD 16V DIGI-KEY 445-1604-1 5% X7R ROHS 4 0.47μF C1,C2,C5,C6 CAP SMD0603 CERM 0.47UFD 16V DIGI-KEY 478-1248-1 10% X5R ROHS 2 0.47μF C13,C14 CAP SMD0603 CERM 0.47UFD 25V DIGI-KEY PCC1771CT 10% X7R ROHS 2 1μF C8,C9 CAP SMD0603 CERM 1.0UFD 16V DIGI-KEY PCC2224CT 10% X5R ROHS 1 100pF C23 CAP SMD0805 CERM 100PFD 50V DIGI-KEY 490-1615-1 5% C0G ROHS 2 0.1μF C31,C33 CAP SMD0603 CERM 0.1UFD 50V DIGI-KEY 445-1314-1 10% X7R ROHS 16 TLV320AIC3254EVM Bill of Materials SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com Appendix B Table 1. TLV320AIC3254EVM Bill of Materials (continued) 2 10μF C32,C34 CAP SMD0805 CERM 10UFD 16V DIGI-KEY 490-3886-1 10% X5R ROHS 2 100μF C17,C18 CAP SMD1210 CERM 100UFD 6.3V DIGI-KEY 490-3390-1 20% X5R ROHS INTEGRATED CIRCUITS Qty Value Ref Des Description Vendor Part number 1 U2 USB STREAMING CONTROLLER DIGI-KEY 296-13041-5 TQFP48-PFB ROHS 1 VR1 VOLT REG 3.3V 400MA LDO CAP- DIGI-KEY 296-15819-1 FREE NMOS SOT23-DBV5 ROHS 1 U3 256K I2C SERIAL EEPROM,MSOP-8 DIGI-KEY 24AA256-I/MSND 1 D1 LED, YELLOW 2.0V SMD0805 DIGI-KEY 67-1554-1 ROHS 1 Y1 OSCILLATOR SMT 6MHz 3.3V OUT- DIGI-KEY 788- ENABLE ROHS 8002AI133E- 6.0T MISCELLANEOUS ITEMS Qty Value Ref Des Description Vendor Part number 1 J5 JACK-USB MALE TYPEA SMT-RA DIGI-KEY WM17118 4PIN ROHS J 4 J1,J2,J3,J4 ACK AUDIO MINI(3.5MM ,4-COND DIGI-KEY CP-43516SJCT PCB-RA ROHS 1 SW1 SWITCH, MOM, 160G SMT 4X3MM DIGI-KEY EG4344CT ROHS ATTENTION: All components must be Rhos compliant. Some part numbers may be either leaded or Rhos. Verify that purchased components are Rhos compliant. SLAU295A–September 2009–Revised October 2012 TLV320AIC3254EVM Bill of Materials 17 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com Appendix C Writing Scripts A script is simply a text file that contains data to send to the serial control buses. Each line in a script file is one command. No provision is made for extending lines beyond one line, except for the > command. A line is terminated by a carriage return. The first character of a line is the command. Commands are: I Set interface bus to use r Read from the serial control bus w Write to the serial control bus > Extend repeated write commands to lines below a w # Comment b Break d Delay f Wait for Flag The first command, I, sets the interface to use for the commands to follow. This command must be followed by one of the following parameters: i2cstd Standard mode I2C bus i2cfast Fast mode I2C bus spi8 SPI bus with 8-bit register addressing spi16 SPI bus with 16-bit register addressing For example, if a fast mode I2C bus is to be used, the script begins with: I i2cfast A double quoted string of characters following the b command can be added to provide information to the user about each breakpoint. When the script is executed, the software's command handler halts as soon as a breakpoint is detected and displays the string of characters within the double quotes. The Wait for Flag command, f, reads a specified register and verifies if the bitmap provided with the command matches the data being read. If the data does not match, the command handler retries for up to 200 times. This feature is useful when switching buffers in parts that support the adaptive filtering mode. The command f syntax follows: f [i2c address] [register] [D7][D6][D5][D4][D3][D2][D1][D0] where 'i2c address' and 'register' are in hexadecimal format and 'D7' through 'D0' are in binary format with values of 0, 1 or X for don't care. Anything following a comment command # is ignored by the parser, provided that it is on the same line. The delay command d allows the user to specify a time, in milliseconds, that the script pauses before proceeding. The delay time is entered in decimal format. A series of byte values follows either a read or write command. Each byte value is expressed in hexadecimal, and each byte must be separated by a space. Commands are interpreted and sent to the TAS1020B by the program. The first byte following an r (read) or w (write) command is the I2C slave address of the device (if I2C is used) or the first data byte to write (if SPI is usednote that SPI interfaces are not standardized on protocols, so the meaning of this byte varies with the device being addressed on the SPI bus). The second byte is the starting register address that data will be written to (again, with I2C; SPI varies. Following these two bytes are data, if writing; if reading, the third byte value is the number of bytes to read, (expressed in hexadecimal). 18 Writing Scripts SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated www.ti.com Appendix C For example, to write the values 0xAA 0x55 to an I2C device with a slave address of 0x30, starting at a register address of 0x03, the user writes: #example script I i2cfast w 30 03 AA 55 r 30 03 02 This script begins with a comment, specifies that a fast I2C bus will be used, then writes 0xAA 0x55 to the I2C slave device at address 0x30, writing the values into registers 0x03 and 0x04. The script then reads back two bytes from the same device starting at register address 0x03. Note that the slave device value does not change. It is unnecessary to set the R/W bit for I2C devices in the script; the read or write commands does that. If extensive repeated write commands are sent and commenting is desired for a group of bytes, the > command can be used to extend the bytes to other lines that follow. A usage example for the > command follows: #example script for '>' command I i2cfast # Write AA and BB to registers 3 and 4, respectively w 30 03 AA BB # Write CC, DD, EE and FF to registers 5, 6, 7 and 8, respectively > CC DD EE FF # Place a commented breakpoint b "AA BB CC DD EE FF was written, starting at register 3" # Read back all six registers, starting at register 3 r 30 03 06 The following example demonstrates usage of the Wait for Flag command, f: #example script for 'wait for flag' command I i2cfast # Switch to Page 44 w 30 00 2C # Switch buffers w 30 01 05 # Wait for bit D0 to clear. 'x' denotes a don't care. f 30 01 xxxxxxx0 Any text editor can be used to write these scripts; Jedit is an editor that is highly recommended for general usage. For more information, go to: http://www.jedit.org. Once the script is written, it can be used in the command window by running the program, and then selecting Open Script File... from the File menu. Locate the script and open it. The script is then displayed in the command buffer. The user can also edit the script once it is in the buffer and save it by selecting Save Script File... from the File menu. SLAU295A–September 2009–Revised October 2012 Writing Scripts 19 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Appendix C www.ti.com Once the script is in the command buffer, it can be executed by pressing the Execute Command Buffer button. If there are breakpoints in the script, the script executes to that point, and the user is presented with a dialog box with a button to press to continue executing the script. When ready to proceed, push that button and the script continues. 20 Writing Scripts SLAU295A–September 2009–Revised October 2012 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated  SLLS025A − JULY 1986  Copyright  1986, Texas Instruments Incorporated Revision Information POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 • Dual Circuits Capable of Driving High-Capacitance Loads at High Speeds • Output Supply Voltage Range up to 24 V • Low Standby Power Dissipation description The SN75372 is a dual NAND gate interface circuit designed to drive power MOSFETs from TTL inputs. It provides high current and voltage levels necessary to drive large capacitive loads at high speeds. The device operates from a VCC1 of 5 V and a VCC2 of up to 24 V. The SN75372 is characterized for operation from 0°C to 70°C. schematic (each driver) VCC1 VCC2 To Other Driver To Other Driver Output Y GND Input A Enable E 1Y 7 2Y 6 E 2 EN 1A 1 2A 3 logic symbol† TTL/MOS 1 2 3 4 8 7 6 5 1A E 2A GND VCC1 1Y 2Y VCC2 D OR P PACKAGE (TOP VIEW) † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.      !"#   $"%&! '#( '"! !  $#!! $# )# #  #* "# '' +,( '"! $!#- '#  #!#&, !&"'# #-  && $##(       SLLS025A − JULY 1986 3−2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Supply voltage range, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 25 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Peak output current, VO (tw < 10 ms, duty cycle < 50%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values are with respect to network GND. DISSIPATION RATING TABLE PACKAGE TA = 25°C DERATING FACTOR TA = 70°C 25 POWER RATING ABOVE TA = 25°C 70 POWER RATING D 725 mW 5.8 mW/°C 464 mW P 1000 mW 8.0 mW/°C 640 mW recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC1 4.75 5 5.25 V Supply voltage, VCC2 4.75 20 24 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V High-level output current, IOH −10 mA Low-level output current, IOL 40 mA Operating free-air temperature, TA 0 70 °C       SLLS025A − JULY 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of VCC1, VCC2, and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Input clamp voltage II = − 12 mA −1.5 V VOH High-level output voltage VIL = 0.8 V, IOH = −50 μA VCC2−1.3 VCC2−0.8 V VIL = 0.8 V, IOH = − 10 mA VCC2−2.5 VCC2−1.8 VIH = 2 V, IOL = 10 mA 0.15 0.3 VOL Low-level output voltage VCC2 = 15 V to 24 V, IOL = 40 mA VIH = 2 V, 0.25 0.5 V VF Output clamp-diode forward voltage VI = 0, IF = 20 mA 1.5 V II Input current at maximum input VI = 5.5 V 1 mA voltage IIH High-level input current Any A VI = 2.4 V 40 A Any E 80 μA IIL Low-level input current Any A VI = 0.4 V −1 −1.6 mA Any E −2 −3.2 ICC1(H) Supply current from VCC1, both outputs high 2 4 mA ICC2(H) Supply current from VCC2, both outputs high VCC1 = 5.25 V, All inputs at 0 V, VCC2 = 24 V, No load 0.5 mA ICC1(L) Supply current from VCC1, both outputs low 16 24 mA ICC2(L) Supply current from VCC2, both outputs low VCC1 = 5.25 V, All inputs at 5 V, VCC2 = 24 V, No load 7 13 mA ICC2(S) Supply current from VCC2, standby condition VCC1 = 0, All inputs at 5 V, VCC2 = 24 V, No load 0.5 mA † All typical values are at VCC1 = 5 V, VCC2 = 20 V, and TA = 25°C. switching characteristics, VCC1 = 5 V, VCC2 = 20 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tDLH Delay time, low-to-high-level output 20 35 ns tDHL Delay time, high-to-low-level output 10 20 ns tTLH Transition time, low-to-high-level output CL = 390 pF, RD = 10 Ω, See Figure 1 20 30 ns tTHL Transition time, high-to-low-level output 20 30 ns tPLH Propagation delay time, low-to-high-level output 10 40 65 ns tPHL Propagation delay time, high-to-low-level output 10 30 50 ns       SLLS025A − JULY 1986 3−4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PARAMETER MEASUREMENT INFORMATION 10% 5 V 2.4 V VCC1 TEST CIRCUIT Input GND VCC2 Pulse Generator (see Note A) Output CL = 390 pF (see Note B) 20 V RD Input Output VOLTAGE WAVEFORMS ≤ 10 ns 90% 1.5 V 0.5 μs tDHL tTLH VCC2−3 V 2 V 0 V VOH ≤ 10 ns 90% 1.5 V 10% tPHL tPHL tDLH tTHL VCC2−3 V 2 V VOL 3 V NOTES: A. The pulse generator has the following characteristics: PRR = 1 MHz, ZO ≈ 50 Ω. B. CL includes probe and jig capacitance. Figure 1. Test Circuit and Voltage Waveforms, Each Driver TYPICAL CHARACTERISTICS −1 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT −10 −100 0.3 0.2 0.1 0 0 20 40 60 0.4 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 0.5 80 100 VCC2−0.5 VCC2−1 VCC2−1.5 VCC2−2 VCC2−2.5 VCC2−3 VCC1 = 5 V VCC2 = 20 V VI = 0.8 V TA = 25°C TA = 70°C TA = 0°C VVO0HH − High-Level Output Voltage − V IOL − Low-Level Output Current − mA VCC1 = 5 V VCC2 = 20 V VI = 2 V TA = 70°C TA = 0°C VVOOLL − Low-Level Output Voltage − V IOH − High-Level Output Current − mA VCC2 − 0.01 − 0.1 Figure 2 Figure 3       SLLS025A − JULY 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TYPICAL CHARACTERISTICS 10 20 40 100 400 1000 f − Frequency − kHz POWER DISSIPATION (BOTH DRIVERS) vs FREQUENCY 200 400 200 0 800 1000 1200 12 600 8 4 0 0 0.5 1 1.5 16 20 VOLTAGE TRANSFER CHARACTERISTICS 24 2 2.5 VI − Input Voltage − V VVO) − Output Voltage − V VCC1 = 5 V VCC2 = 20 V No Load TA = 25°C VCC1 = 5 V VCC2 = 20 V Input: 3-V Square Wave 50% Duty Cycle TA = 25°C CL = 600 pF CL = 1000 pF CL = 2000 pF CL = 4000 pF CL = 400 pF PPDT − Power Dissipation − mW Allowable in P Package Only Figure 4 Figure 5 PROPAGATION DELAY TIME, HIGH-TO-LOW-LEVEL OUTPUT vs FREE-AIR TEMPERATURE PROPAGATION DELAY TIME, LOW-TO-HIGH-LEVEL OUTPUT vs FREE-AIR TEMPERATURE 100 80 20 0 0 10 20 30 40 50 60 High-to-Low-Level Output − ns 140 180 200 70 80 60 160 120 40 TA − Free-Air Temperature − °C tkPSLVHR − Propagation Delay Time, Low-to-High-Level Output − ns ktSPVHRL − Propagation Delay Time, TA − Free-Air Temperature − °C 100 80 20 0 140 180 200 60 160 120 40 0 10 20 30 40 50 60 70 80 CL = 50 pF CL = 200 pF CL = 1000 pF CL = 2000 pF CL = 4000 pF VCC1 = 5 V VCC2 = 20 V RD = 10 Ω See Figure 1 CL = 4000 pF CL = 2000 pF CL = 1000 pF VCC1 = 5 V VCC2 = 20 V RD = 10 Ω See Figure 1 CL = 200 pF CL = 390 pF CL = 50 pF CL = 390 pF Figure 6 Figure 7       SLLS025A − JULY 1986 3−6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TYPICAL CHARACTERISTICS 0 5 10 15 PROPAGATION DELAY TIME, LOW-TO-HIGH-LEVEL OUTPUT vs VCC2 SUPPLY VOLTAGE 20 25 100 80 20 0 140 180 200 60 160 120 40 Low-to-High-Level Output − ns VCC2 − Supply Voltage − V PROPAGATION DELAY TIME, HIGH-TO-LOW-LEVEL OUTPUT vs VCC2 SUPPLY VOLTAGE 100 80 20 0 140 180 200 60 160 120 40 0 5 10 15 20 25 VCC2 − Supply Voltage − V tPLH − Propagation Delay Time, VCC1 = 5 V RD = 10 Ω TA = 25°C See Figure 1 CL = 2000 pF CL = 1000 pF CL = 200 pF CL = 390 pF CL = 50 pF VCC1 = 5 V RD = 10 Ω TA = 25°C See Figure 1 CL = 4000 pF CL = 2000 pF CL = 1000 pF CL = 390 pF CL = 200 pF CL = 50 pF CL = 4000 pF High-to-Low-Level Output − ns tPLH − Propagation Delay Time, Figure 8 Figure 9 0 1000 2000 3000 4000 VCC1 = 5 V VCC2 = 20 V TA = 25°C See Figure 1 Low-to-High-Level Output − ns 100 80 20 0 140 180 200 60 160 120 40 PROPAGATION DELAY TIME, LOW-TO-HIGH-LEVEL OUTPUT vs LOAD CAPACITANCE CL − Load Capacitance − pF RD = 10 Ω RD = 0 RD = 24 Ω 100 80 20 0 140 180 200 60 160 120 40 0 1000 2000 3000 4000 CL − Load Capacitance − pF VCC1 = 5 V VCC2 = 20 V TA = 25°C See Figure 1 RD = 24 Ω RD = 10 Ω PROPAGATION DELAY TIME, HIGH-TO-LOW-LEVEL OUTPUT vs LOAD CAPACITANCE RD = 0 ktSPVLRH − Propagation Delay Time, High-to-Low-Level Output − ns ktSPVLRH − Propagation Delay Time, Figure 10 Figure 11 NOTE: For RD = 0, operation with CL > 2000 pF violates absolute maximum current rating.       SLLS025A − JULY 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 THERMAL INFORMATION power dissipation precautions Significant power may be dissipated in the SN75372 driver when charging and discharging high-capacitance loads over a wide voltage range at high frequencies. Figure 5 shows the power dissipated in a typical SN75372 as a function of load capacitance and frequency. Average power dissipated by this driver is derived from the equation PT(AV) = PDC(AV) + PC(AV) = PS(AV) where PDC(AV) is the steady-state power dissipation with the output high or low, PC(AV) is the power level during charging or discharging of the load capacitance, and PS(AV) is the power dissipation during switching between the low and high levels. None of these include energy transferred to the load, and all are averaged over a full cycle. The power components per driver channel are PC(AV)  C V2 C f tHL tLH tH tL T = 1/f where the times are as defined in Figure 14. Figure 12. Output Voltage Waveform PDC(AV) = PHtH + PLtL T PS(AV) = PLHtLH + PHLtHL T PL, PH, PLH, and PHL are the respective instantaneous levels of power dissipation, C is the load capacitance. VC is the voltage across the load capacitance during the charge cycle shown by the equation VC = VOH − VOL PS(AV) may be ignored for power calculations at low frequencies. In the following power calculation, both channels are operating under identical conditions: VOH =19.2 V and VOL = 0.15 V with VCC1 = 5 V, VCC2 = 20 V, VC = 19.05 V, C = 1000 pF, and the duty cycle = 60%. At 0.5 MHz, PS(AV) is negligible and can be ignored. When the output voltage is high, ICC2 is negligible and can be ignored. On a per-channel basis using data sheet values, PDC(AV)  (5 V) 2 mA 2  (20 V) 0 mA 2  (0.6)(5 V) 16 mA 2  (20 V) 7 mA 2  (0.4) PDC(AV) = 47 mW per channel Power during the charging time of the load capacitance is PC(AV) = (1000 pF) (19.05 V)2 (0.5 MHz) = 182 mW per channel Total power for each driver is PT(AV) = 47 mW + 182 mW = 229 mW and total package power is PT(AV) = (229) (2) = 458 mW.       SLLS025A − JULY 1986 3−8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 APPLICATION INFORMATION driving power MOSFETs The drive requirements of power MOSFETs are much lower than comparable bipolar power transistors. The input impedance of a FET consists of a reverse biased PN junction that can be described as a large capacitance in parallel with a very high resistance. For this reason, the commonly used open-collector driver with a pullup resistor is not satisfactory for high-speed applications. In Figure 12(a), an IRF151 power MOSFET switching an inductive load is driven by an open-collector transistor driver with a 470-Ω pullup resistor. The input capacitance (Ciss) specification for an IRF151 is 4000 pF maximum. The resulting long turn-on time due to the combination of Ciss and the pullup resistor is shown in Figure 12(b). 5 V 7 4 8 3 5 2 1 6 VVO0HH − − Gate Voltage − V TLC555P 1/2 SN75447 470 Ω 48 V M VOL t − Time − μs (b) (a) IRF151 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 Figure 13. Power MOSFET Drive Using SN75447       SLLS025A − JULY 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 APPLICATION INFORMATION A faster, more efficient drive circuit uses an active pullup as well as an active pulldown output configuration, referred to as a totem-pole output. The SN75372 driver provides the high speed, totem-pole drive desired in an application of this type, see Figure 13(a). The resulting faster switching speeds are shown in Figure 13(b). 5 V TLC555P 1/2 SN75372 M t − Time − μs (b) (a) IRF151 48 V 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 VVO0HH − VVOOLL − Gate Voltage − V 7 4 8 3 5 2 1 6 Figure 14. Power MOSFET Drive Using SN75372 Power MOSFET drivers must be capable of supplying high peak currents to achieve fast switching speeds as shown by the equation Ipk  VC tr where C is the capacitive load, and tr is the desired drive time. V is the voltage that the capacitance is charged to. In the circuit shown in Figure 13(a), V is found by the equation V = VOH − VOL Peak current required to maintain a rise time of 100 ns in the circuit of Figure 13(a) is IPK  (30)4(109) 100(109)  120 mA Circuit capacitance can be ignored because it is very small compared to the input capacitance of the IRF151. With a VCC of 5 V, and assuming worst-cast conditions, the gate drive voltage is 3 V. For applications in which the full voltage of VCC2 must be supplied to the MOSFET gate, the SN75374 quad MOSFET driver should be used. PACKAGE OPTION ADDENDUM www.ti.com 19-Jun-2010 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN75372D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN75372DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN75372DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN75372DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN75372DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN75372P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Contact TI Distributor or Sales Office SN75372PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Contact TI Distributor or Sales Office SN75372PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN75372PSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN75372PSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. PACKAGE OPTION ADDENDUM www.ti.com 19-Jun-2010 Addendum-Page 2 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN75372DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN75372PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75372DR SOIC D 8 2500 340.5 338.1 20.6 SN75372PSR SO PS 8 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1  Meets IEEE Standard 488-1978 (GPIB)  8-Channel Bidirectional Transceivers  Power-Up/Power-Down Protection (Glitch Free)  Designed to Implement Control Bus Interface  SN75161B Designed for Single Controller  SN75162B Designed for Multiple Controllers  High-Speed, Low-Power Schottky Circuitry  Low Power Dissipation . . . 72 mW Max Per Channel  Fast Propagation Times . . . 22 ns Max  High-Impedance pnp Inputs  Receiver Hysteresis . . . 650 mV Typ  Bus-Terminating Resistors Provided on Driver Outputs  No Loading of Bus When Device Is Powered Down (VCC = 0) description The SN75161B and SN75162B eight-channel, general-purpose interface bus transceivers are monolithic, high-speed, low-power Schottky devices designed to meet the requirements of IEEE Standard 488-1978. Each transceiver is designed to provide the bus-management and data-transfer signals between operating units of a single- or multiple-controller instrumentation system. When combined with the SN75160B octal bus transceiver, the SN75161B or SN75162B provides the complete 16-wire interface for the IEEE-488 bus. The SN75161B and SN75162B feature eight driver-receiver pairs connected in a front-to-back configuration to form input/output (I/O) ports at both the bus and terminal sides. A powerup/- down disable circuit is included on all bus and receiver outputs. This provides glitch-free operation during VCC power up and power down. PRODUCTION DATA information is current as of publication date. Copyright W 1995, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SC TE REN IFC NDAC NRFD DAV EOI ATN SRQ NC GND 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 VCC NC REN IFC NDAC NRFD DAV EOI ATN SRQ NC DC (TOP VIEW) TE REN IFC NDAC NRFD DAV EOI ATN SRQ GND VCC REN IFC NDAC NRFD DAV EOI ATN SRQ DC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GPIB I/O Ports Terminal I/O Ports (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SC TE REN IFC NDAC NRFD DAV EOI ATN SRQ GND VCC NC REN IFC NDAC NRFD DAV EOI ATN SRQ DC (TOP VIEW) NC–No internal connection SN75161B . . . DW OR N PACKAGE SN75162B . . . DW PACKAGE SN75162B . . . N PACKAGE GPIB I/O Ports Terminal I/O Ports GPIB I/O Ports Terminal I/O Ports SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) The direction of data through these driver-receiver pairs is determined by the DC, TE, and SC (on SN75162B) enable signals. The SC input on the SN75162B allows the REN and IFC transceivers to be controlled independently. The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high impedance to the bus when supply voltage VCC is 0. The drivers are designed to handle loads up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV for increased noise immunity. All receivers have 3-state outputs to present a high impedance to the terminal when disabled. The SN75161B and SN75162B are characterized for operation from 0°C to 70°C. Function Tables SN75161B RECEIVE/TRANSMIT CONTROLS BUS-MANAGEMENT CHANNELS DATA-TRANSFER CHANNELS DC TE ATN† ATN† SRQ REN IFC EOI DAV NDAC NRFD (Controlled by DC) (Controlled by TE) H H H R T R R T T R R H H L R L L H T R T T R R T T L L L T H L X R T R R R R T T L H X T R T T T T R R H = high level, L = low level, R = receive, T = transmit, X = irrelevant Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side. Data transfer is noninverting in both directions. † ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only. SN75162B RECEIVE/TRANSMIT CONTROLS BUS-MANAGEMENT CHANNELS DATA-TRANSFER CHANNELS SC DC TE ATN† ATN† SRQ REN IFC EOI DAV NDAC NRFD (Controlled by DC) (Controlled by SC) (Controlled by TE) H H H R T T T R R H H L R L L H T R R R T T L L L T H L X R T R R T T L H X T R T T R R H T T L R R H = high level, L = low level, R = receive, T = transmit, X = irrelevant Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side. Data transfer is noninverting in both directions. † ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only. SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CHANNEL-IDENTIFICATION TABLE NAME IDENTITY CLASS DC Direction Control TE Talk Enable Control SC System Control (SN75162B only) ATN Attention SRQ Service Request REN Remote Enable Bus IFC Interface Clear Management EOI End of Identity DAV Data Valid NDAC Not Data Accepted Data NRFD Not Ready for Data Transfer SN75161B logic symbol† EN3 1 ATN 8 1 ATN 13 1 1 EOI 7 3 EOI 14 1 3 SRQ 1 SRQ 12 1 1 REN 2 1 REN 19 1 1 IFC 3 1 IFC 18 1 1 DAV 6 2 DAV 15 1 2 NDAC 4 2 NDAC 17 1 2 2 1 16 NRFD 2 EN1/G4 EN2/G5 5 4 5 NRFD TE 1 DC 11 This symbol is in accordance with IEEE Std 91-1984 and IEC Publication 617-12. Designates 3-state outputs Designates passive-pullup outputs  9 SN75161B logic diagram (positive logic) NRFD 5 NRFD 16 NDAC 4 NDAC 17 DAV 6 DAV 15 IFC 3 IFC 18 REN 2 REN 19 SRQ 9 SRQ 12 EOI 7 EOI 14 11 DC 1 TE 13 ATN 8 ATN SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75162B logic symbol† EN3 . 1 ATN 1 ATN 14 1 1 EOI 6 EOI 1 6 SRQ 1 SRQ 1 1 REN REN 1 3 IFC IFC 1 DAV 2 DAV 1 2 NDAC 2 NDAC 1 2 2 1 NRFD 2 EN1/G4 EN2/G5 5 4 NRFD TE DC This symbol is in accordance with IEEE Std 91-1984 and IEC Publication 617-12. Designates 3-state outputs Designates passive-pullup outputs  EN3 12 2 1 15 SC 13 20 19 16 18 17 9 8 10 3 4 7 5 6 3 3 3 Pin numbers shown are for the N package. SN75162B logic diagram (positive logic) NRFD NRFD NDAC NDAC DAV DAV IFC IFC REN REN SRQ SRQ EOI EOI DC TE ATN ATN 12 2 1 14 15 13 20 19 16 18 17 9 8 10 3 4 7 5 6 SC SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 schematics of inputs and outputs NOM 4 kW R(eq) 1.7 kW NOM 10 kW NOM VCC GND Input/Output Port Input/Output Port GND VCC NOM 10 kW NOM 4 kW NOM 1.7 kW NOM 9 kW GND Input VCC NOM 4 kW EQUIVALENT OF ALL CONTROL INPUTS TYPICAL OF SRQ, NDAC, AND NRFD GPIB I/O PORT Circuit inside dashed lines is on the driver outputs only. TYPICAL OF ALL I/O PORTS EXCEPT SRQ, NDAC, AND NRFD GPIB I/O PORTS Driver output R(eq) = 30 W NOM Receiver output R(eq) = 110 W NOM Circuit inside dashed lines is on the driver outputs only. R(eq) = equivalent resistor absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Low-level driver output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16) inch from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network ground terminal. SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DISSIPATION RATING TABLE PACKAGE TA 3 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING DW (20 pin) 1125 mW 9.0 mW/°C 720 mW DW (24 pin) 1350 mW 10.8 mW/°C 864 mW N (20 pin) 1150 mW 9.2 mW/°C 736 mW N (22 pin) 1700 mW 13.6 mW/°C 1088 mW recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.75 5 5.25 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V High level output current IOH Bus ports with 3-state outputs –5.2 mA High-current, Terminal ports –800 mA Low level output current IOL Bus ports 48 Low-current, mA Terminal ports 16 Operating free-air temperature, TA 0 70 °C SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Input clamp voltage II = – 18 mA –0.8 –1.5 V Vhys Hysteresis voltage (VIT+ – VIT–) Bus See Figure 7 0.4 0.65 V VOH‡ High level output voltage Terminal IOH = – 800 mA 2.7 3.5 High-V Bus IOH = – 5.2 mA 2.5 3.3 VOL Low level output voltage Terminal IOL = 16 mA 0.3 0.5 Low-V Bus IOL = 48 mA 0.35 0.5 II Input current at maximum Terminal VI = 5 5 V 0 2 100 mA input voltage 5.5 0.2 IIH High-level input current Terminal and VI = 2.7 V 0.1 20 mA IIL Low-level input current control inputs VI = 0.5 V –10 –100 mA VI/O(b ) Voltage at bus port Driver disabled II(bus) = 0 2.5 3.0 3.7 bus) V II(bus) = – 12 mA –1.5 VI(bus) = – 1.5 V to 0.4 V –1.3 VI(bus) = 0.4 V to 2.5 V 0 –3.2 Power on Driver disabled VI(b ) = 2 5 V to 3 7 V 2.5 mA II/O(bus) Current into bus port bus) 2.5 3.7 –3.2 ( ) VI(bus) = 3.7 V to 5 V 0 2.5 VI(bus) = 5 V to 5.5 V 0.7 2.5 Power off VCC = 0, VI(bus) = 0 V to 2.5 V –40 mA IOS Short circuit output current Terminal –15 –35 –75 Short-mA Bus –25 –50 –125 ICC Supply current No load, TE, DE, and SC low 110 mA CI/O(b ) Bus port capacitance VCC = 5 V to 0, bus) Bus-CC 16 pF VI/O = 0 to 2 V, f = 1 MHz † All typical values are at VCC = 5 V, TA = 25°C. ‡ VOH applies for 3-state outputs only. SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low- to high-level output Terminal Bus CL = 30 pF, 14 20 ns tPHL Propagation delay time, high- to low-level output L See Figure 1 14 20 tPLH Propagation delay time, low- to high-level output Terminal Bus (SRQ,NDAC, NRFD) CL = 30 pF, See Figure 1 29 35 ns tPLH Propagation delay time, low- to high-level output Bus Terminal CL = 30 pF, 10 20 ns tPHL Propagation delay time, high- to low-level output L See Figure 2 15 22 tPZH Output enable time to high level Bus (ATN 60 tPHZ Output disable time from high level TE,DC, ATN, EOI, REN, See Figure 3 45 ns tPZL Output enable time to low level or SC , , IFC, and 60 tPLZ Output disable time from low level DAV) 55 tPZH Output enable time to high level 55 tPHZ Output disable time from high level TE,DC, Terminal See Figure 4 50 ns tPZL Output enable time to low level or SC 45 tPLZ Output disable time from low level 55 SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PARAMETER MEASUREMENT INFORMATION VOLTAGE WAVEFORMS LOAD CIRCUIT 480 W 200 W (see Note A) CL = 30 pF Test Point 5 V Output Bus Input Terminal See Note B VOH VOH 0 V 3 V tPHL 2.2 V 1.0 V 1.5 V tPLH 1.5 V From (Bus) Output Under Test NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle, tr 3 6 ns, tf 3 6 ns, ZO = 50 W. Figure 1. Terminal-to-Bus Load Circuit and Voltage Waveforms See Note B 1.5 V tPLH 1.5 V 1.5 V 1.5 V tPHL 3 V 0 V VOH VOL Bus Input Output From (Terminal) Output Under Test 4.3 V Test Point CL = 30 pF (see Note A) 240 W 3 kW LOAD CIRCUIT VOLTAGE WAVEFORMS Terminal NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle, tr 3 6 ns, tf 3 6 ns, ZO = 50 W. Figure 2. Bus-to-Terminal Load Circuit and Voltage Waveforms SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle, tr 3 6 ns, tf 3 6 ns, ZO = 50 W. S1 Open tPHZ 1.5 V 3 V 0 V S1 Closed 1 V 3.5 V VOL Input Control See Note B 1.5 V tPZH S1 VOLTAGE WAVEFORMS 2 V tPZL 90% 0.5 V tPLZ VOH 0 V Bus Output Bus Output 5 V Test Point CL = 15 pF (see Note A) 200 W 480 W LOAD CIRCUIT From (Bus) Output Under Test Figure 3. Bus Enable and Disable Times Load Circuit and Voltage Waveforms SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PARAMETER MEASUREMENT INFORMATION Output 90% Terminal S1 Open S1 Closed Terminal tPHZ VOLTAGE WAVEFORMS Output 0 V VOH tPLZ 0.7 V tPZL 1.5 V tPZH 1.5 V See Note B Control Input VOL 4 V 1 V 0 V 3 V 1.5 V LOAD CIRCUIT 3 kW 240 W Test Point S1 4.3 V CL = 15 pF (see Note A) From (Terminal) Output Under Test NOTES: A. CL includes probe and jig capacitance. B. The Input pulse is supplied by a generator having the following characteristics: PRR 3 1 MHz, 50% duty cycle, tr 3 6 ns, tf 3 6 ns, ZO = 50 W. Figure 4. Terminal Enable and Disable Times Load Circuit and Voltage Waveforms SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS VOH – High-Level Output Voltage – V TERMINAL I/O PORTS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3.5 3 2.5 2 1.5 1 0.5 –5 –10 –15 –20 –25 –30 –35 0 –40 4 0 TA = 25°C VCC = 5 V IOH – High-Level Output Current – mA Figure 5 IOL – Low-Level Output Current – mA – Low-Level Output Voltage – V TERMINAL I/O PORTS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT TA = 25°C VCC = 5 V 0.5 0.4 0.3 0.2 0.1 10 20 30 40 50 0 60 0.6 0 VOL Figure 6 2 – Output Voltage – V TERMINAL I/O PORTS OUTPUT VOLTAGE vs BUS INPUT VOLTAGE VIT– TA = 25°C No Load VCC = 5 V 3.5 3 2.5 2 1.5 1 0.5 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 4 VI – Bus Input Voltage – V 0 VO VIT+ Figure 7 SN75161B, SN75162B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS SLLS005B – OCTOBER 1980 – REVISED MAY 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TYPICAL CHARACTERISTICS IOH – High-Level Output Current – mA – High-Level Output Voltage – V GPIB I/O PORTS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT TA = 25°C VCC = 5 V 3 2 1 –10 –20 –40 –30 –50 0 –60 0 0 VOH Figure 8 IOL – Low-Level Output Current – mA – Low-Level Output Voltage – V GPIB I/O PORTS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT TA = 25°C VCC = 5 V 0.5 0.4 0.3 0.2 0.1 10 20 30 40 50 60 70 80 90 0 100 0.6 0 VOL Figure 9 Figure 10 VI – Input Voltage – V VO – Output Voltage – V GPIB I/O PORTS OUTPUT VOLTAGE vs THERMAL INPUT VOLTAGE TA = 25°C No Load VCC = 5 V 3 2 1 1 1.1 1.2 1.3 1.4 1.5 1.6 0 4 0.9 1.7 – Current – mA GPIB I/O PORTS CURRENT vs VOLTAGE 2 1 0 –1 –2 –3 –6 –1 0 1 2 3 4 5 –7 6 VI/O – Voltage – V –2 TA = 25°C VCC = 5 V ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ The Unshaded Area Conforms to Paragraph 3.5.3 of IEEE Standard 488-1978 II/O –5 –4 Figure 11 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) SN75161BDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75161BDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75161BDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75161BDWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75161BDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75161BN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75161BNE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75162BDW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BDWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BDWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BDWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BDWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BDWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75162BN OBSOLETE PDIP N 22 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated 6 O 6 (1.8639 V 2.1962 10 3.88 10 ) T 1481.96   u u    GND NC V+ VO LMT88 LMT88 www.ti.com SNIS175 –MARCH 2013 LMT88 2.4V, 10μA, SC70, DSBGA Temperature Sensor Check for Samples: LMT88 1FEATURES DESCRIPTION The LMT88 is a precision analog output CMOS 2• Cost-Effective Alternative to Thermistors integrated-circuit temperature sensor that operates • Rated for full −55°C to +130°C range over a −55°C to 130°C temperature range. The • Available in an SC70 Package power supply operating range is 2.4 V to 5.5 V. The • Predictable Curvature Error transfer function of LMT88 is predominately linear, yet • Suitable for Remote Applications has a slight predictable parabolic curvature. The accuracy of the LMT88 when specified to a parabolic transfer function is ±1.5°C at an ambient temperature APPLICATIONS of 30°C. The temperature error increases linearly and • Industrial reaches a maximum of ±2.5°C at the temperature • HVAC range extremes. The temperature range is affected by the power supply voltage. At a power supply • Disk Drives voltage of 2.7 V to 5.5 V the temperature range • Automotive extremes are 130°C and −55°C. Decreasing the • Portable Medical Instruments power supply voltage to 2.4 V changes the negative extreme to −30°C, while the positive remains at • Computers 130°C. • Battery Management The LMT88 quiescent current is less than 10 μA. • Printers Therefore, self-heating is less than 0.02°C in still air. • Power Supply Modules Shutdown capability for the LMT88 is intrinsic • FAX Machines because its inherent low power consumption allows it to be powered directly from the output of many logic • Mobile Phones gates or does not necessitate shutdown at all. • Automotive The LMT88 is a cost-competitive alternative to thermistors. TYPICAL APPLICATION Full-Range Celsius (Centigrade) Temperature Sensor (−55°C TO 130°C) Operating From a Single LI-Ion Battery Cell space space VO = (−3.88×10−6×T2) + (−1.15×10−2×T) + 1.8639 space where: T is temperature, and VO is the measured output voltage of the LMT88. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. LMT88 GND NC V+ VO 1 4 3 5 GND 2 LMT88 SNIS175 –MARCH 2013 www.ti.com Figure 1. Output Voltage vs Temperature Table 1. Output Voltage vs Temperature TEMPERATURE (T) TYPICAL VO 130°C 303 mV 100°C 675 mV 80°C 919 mV 30°C 1515 mV 25°C 1574 mV 0°C 1863.9 mV –30°C 2205 mV −40°C 2318 mV −55°C 2485 mV CONNECTION DIAGRAMS GND (pin 2) may be grounded or left floating. For optimum thermal conductivity to the pc board ground plane, pin 2 must be grounded. NC (pin 1) must be left floating or grounded. Other signal traces must not be connected to this pin. Figure 2. SC70-5 Top View 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMT88 LMT88 www.ti.com SNIS175 –MARCH 2013 ABSOLUTE MAXIMUM RATINGS(1) VALUES Supply Voltage 6.5V to −0.2V Output Voltage (V+ + 0.6 V) to −0.6 V Output Current 10 mA Input Current at any pin (2) 5 mA Storage Temperature −65°C to 150°C Maximum Junction Temperature (TJMAX) 150°C Human Body Model 2500 V ESD Susceptibility (3) Machine Model 250 V Soldering process must comply with the Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.(4) (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For specified specifications and test conditions, see the ELECTRICAL CHARACTERISTICS. The specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. (2) When the input voltage (VI) at any pin exceeds power supplies (VI < GND or VI > V+), the current at that pin should be limited to 5 mA. (3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. (4) Reflow temperature profiles are different for lead-free and non-lead-free packages. OPERATION RATINGS Specified Temperature Range: TMIN ≤ TA ≤ TMAX LMT88 with 2.4 V ≤ V+≤ 2.7 V −30°C ≤ TA ≤ 130°C LMT88 with 2.7 V ≤ V+≤ 5.5 V −55°C ≤ TA ≤ 130°C Supply Voltage Range (V+) 2.4 V to 5.5 V Thermal Resistance, θJA (1) SC70 415°C/W (1) The junction to ambient thermal resistance (θJA) is specified without a heat sink in still air using the printed circuit board layout shown in PCB Layouts Used For Thermal Measurements. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LMT88 LMT88 SNIS175 –MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise noted, these specifications apply for V+ = +2.7 VDC. Boldface limits apply for TA = TJ = TMIN to TMAX ; all other limits TA = TJ = 25°C; Unless otherwise noted. PARAMETER CONDITIONS TYPICAL(1) MAX(2) UNIT (Limit) TA = 25°C to 30°C ±1.5 ±4.0 °C (max) TA = 130°C ±5.0 °C (max) TA = 125°C ±5.0 °C (max) TA = 100°C ±4.7 °C (max) Temperature to Voltage Error TA = 85°C ±4.6 °C (max) VO = (−3.88×10−6×T2) + (−1.15×10−2×T) + 1.8639V(3) TA = 80°C ±4.5 °C (max) TA = 0°C ±4.4 °C (max) TA = –30°C ±4.7 °C (min) TA = –40°C ±4.8 °C (max) TA = –55°C ±5.0 °C (max) Output Voltage at 0°C 1.8639 V Variance from Curve ±1.0 °C Non-Linearity (4) –20°C ≤ TA ≤ 80°C ±0.4% Sensor Gain (Temperature Sensitivity or Average Slope) –30°C ≤ T −11.0 mV/°C (min) to equation: V A ≤ 100°C −11.77 O=−11.77 mV/ °C×T+1.860V −12.6 mV/°C (max) Output Impedance 0 μA ≤ IL ≤ 16 μA (5) (6) 160 Ω (max) Load Regulation(7) 0 μA ≤ IL ≤ 16 μA (5) (6) −2.5 mV (max) 2.4 V ≤ V+ ≤ 5.0V 3.7 mV/V (max) Line Regulation(8) 5.0 V ≤ V+ ≤ 5.5 V 11 mV (max) 2.4V ≤ V+ ≤ 5.0V 4.5 7 μA (max) Quiescent Current 5.0V ≤ V+ ≤ 5.5V 4.5 9 μA (max) 2.4V ≤ V+ ≤ 5.0V 4.5 10 μA (max) Change of Quiescent Current 2.4 V ≤ V+ ≤ 5.5V 0.7 μA Temperature Coefficient of Quiescent Current −11 nA/°C Shutdown Current V+ ≤ 0.8 V 0.02 μA (1) Typicals are at TJ = TA = 25°C and represent most likely parametric norm. (2) Limits are specified to TI's AOQL (Average Outgoing Quality Level). (3) Accuracy is defined as the error between the measured and calculated output voltage at the specified conditions of voltage, current, and temperature (expressed in°C). (4) Non-Linearity is defined as the deviation of the calculated output-voltage-versus-temperature curve from the best-fit straight line, over the temperature range specified. (5) Negative currents are flowing into the LMT88. Positive currents are flowing out of the LMT88. Using this convention the LMT88 can at most sink −1 μA and source 16 μA. (6) Load regulation or output impedance specifications apply over the supply voltage range of 2.4V to 5.5V. (7) Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output due to heating effects can be computed by multiplying the internal dissipation by the thermal resistance. (8) Line regulation is calculated by subtracting the output voltage at the highest supply input voltage from the output voltage at the lowest supply input voltage. 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMT88 6 O 6 (1.8639 V 2.1962 10 3.88 10 T 1481.96   u  u   LMT88 www.ti.com SNIS175 –MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS PCB Layouts Used For Thermal Measurements Figure 4. Layout Used For No Heat Sink Measurements Figure 5. Layout Used For Measurements With Small Heat Sink LMT88 TRANSFER FUNCTION The LMT88 transfer function can be described in different ways with varying levels of precision. A simple linear transfer function, with good accuracy near 25°C, is VO = −11.69 mV/°C × T + 1.8663 V (1) Over the full operating temperature range of −55°C to 130°C, best accuracy can be obtained by using the parabolic transfer function. VO = (−3.88×10−6×T2) + (−1.15×10−2×T) + 1.8639 (2) solving for T: (3) A linear transfer function can be used over a limited temperature range by calculating a slope and offset that give best results over that range. A linear transfer function can be calculated from the parabolic transfer function of the LMT88. The slope of the linear transfer function can be calculated using the following equation: m = −7.76 × 10−6× T − 0.0115, (4) where T is the middle of the temperature range of interest and m is in V/°C. For example for the temperature range of TMIN = −30 to TMAX = +100°C: T = 35°C (5) and m = −11.77 mV/°C (6) The offset of the linear transfer function can be calculated using the following equation: b = (VOP(TMAX) + VOP(T) − m × (TMAX+T))/2 (7) where: VOP(TMAX) is the calculated output voltage at TMAX using the parabolic transfer function for VO VOP(T) is the calculated output voltage at T using the parabolic transfer function for VO. Using this procedure the best fit linear transfer function for many popular temperature ranges was calculated in Table 2. As shown in Table 2 the error that is introduced by the linear transfer function increases with wider temperature ranges. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LMT88 LMT88 SNIS175 –MARCH 2013 www.ti.com Table 2. First Order Equations Optimized for Different Temperature Ranges TEMPERATURE RANGE MAXIMUM DEVIATION OF LINEAR EQUATION LINEAR EQUATION Tmin (°C) Tmax (°C) FROM PARABOLIC EQUATION (°C) −55 130 VO = −11.79 mV/°C × T + 1.8528 V ±1.41 −40 110 VO = −11.77 mV/°C × T + 1.8577 V ±0.93 −30 100 VO = −11.77 mV/°C × T + 1.8605 V ±0.70 -40 85 VO = −11.67 mV/°C × T + 1.8583 V ±0.65 −10 65 VO = −11.71 mV/°C × T + 1.8641 V ±0.23 35 45 VO = −11.81 mV/°C × T + 1.8701 V ±0.004 20 30 VO = –11.69 mV/°C × T + 1.8663 V ±0.004 MOUNTING The LMT88 can be applied easily in the same way as other integrated-circuit temperature sensors. It can be glued or cemented to a surface. The temperature that the LMT88 is sensing will be within about +0.02°C of the surface temperature to which the LMT88's leads are attached to. This presumes that the ambient air temperature is almost the same as the surface temperature; if the air temperature were much higher or lower than the surface temperature, the actual temperature measured would be at an intermediate temperature between the surface temperature and the air temperature. To ensure good thermal conductivity the backside of the LMT88 die is directly attached to the pin 2 GND pin. The tempertures of the lands and traces to the other leads of the LMT88 will also affect the temperature that is being sensed. Alternatively, the LMT88 can be mounted inside a sealed-end metal tube, and can then be dipped into a bath or screwed into a threaded hole in a tank. As with any IC, the LMT88 and accompanying wiring and circuits must be kept insulated and dry, to avoid leakage and corrosion. This is especially true if the circuit may operate at cold temperatures where condensation can occur. Printed-circuit coatings and varnishes such as Humiseal and epoxy paints or dips are often used to ensure that moisture cannot corrode the LMT88 or its connections. The thermal resistance junction to ambient (θJA) is the parameter used to calculate the rise of a device junction temperature due to its power dissipation. For the LMT88 the equation used to calculate the rise in the die temperature is as follows: TJ = TA + θJA [(V+ IQ) + (V+ − VO) IL] where IQ is the quiescent current and ILis the load current on the output. Since the LMT88's junction temperature is the actual temperature being measured care should be taken to minimize the load current that the LMT88 is required to drive. 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMT88 OUT Heavy Capacitive Load, Wiring, Etc. LMT88 + d R C OUT Heavy Capacitive Load, Wiring, Etc. LMT88 + d R C 0.1 μF Bypass Optional 0.1 μF Bypass Optional OUT Heavy Capacitive Load, Wiring, Etc. LMT88 + d To A High-Impedance Load LMT88 www.ti.com SNIS175 –MARCH 2013 The tables shown in Table 3 summarize the rise in die temperature of the LMT88 without any loading, and the thermal resistance for different conditions. Table 3. Temperature Rise of LMT88 Due to Self-Heating and Thermal Resistance (θJA)(1) SC70-5 SC70-5 NO HEAT SINK SMALL HEAT SINK θJA TJ − TA θJA TJ − TA (°C/W) (°C) (°C/W) (°C) Still air 412 0.2 350 0.19 Moving air 312 0.17 266 0.15 (1) See PCB Layouts Used For Thermal Measurements for PCB layout samples. CAPACITIVE LOADS The LMT88 handles capacitive loading well. Without any precautions, the LMT88 can drive any capacitive load less than 300 pF as shown in Figure 6. Over the specified temperature range the LMT88 has a maximum output impedance of 160 Ω. In an extremely noisy environment it may be necessary to add some filtering to minimize noise pickup. It is recommended that 0.1 μF be added from V+ to GND to bypass the power supply voltage, as shown in . In a noisy environment it may even be necessary to add a capacitor from the output to ground with a series resistor as shown in . A 1 μF output capacitor with the 160 Ω maximum output impedance and a 200 Ω series resistor will form a 442 Hz lowpass filter. Since the thermal time constant of the LMT88 is much slower, the overall response time of the LMT88 will not be significantly affected. Figure 6. LMT88 No Decoupling Required for Capacitive Loads Less Than 300 pF R (Ω) C (μF) 200 1 470 0.1 680 0.01 1 k 0.001 spacer between the table and graphic Figure 7. LMT88 with Filter for Noisy Environment and Capacitive Loading Greater Than 300 pF Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LMT88 GND 0.1 PF V+ VO LMT88 GND NC 0.1 PF V+ (+5.0V) 1 k ADCV0831 LM4040BIM3-4.1 GND VIN V+ 6 5 4 1 3 2 3 2 1 4 5 CS DO CLK 470 Ÿ LMT88 SHUTDOWN +VS VO Any logic device output 4.1V R1 R3 R2 LM4040 U3 0.1 PF R4 VOUT V+ VT VTemp + - U1 V+ LMT88 U2 (High = overtemp alarm) VT1 VT2 VTEMP VOUT VT1 = R1 + R2||R3 (4.1)R2 VT2 = R2 + R1||R3 (4.1)R2||R3 LM7211 LMT88 SNIS175 –MARCH 2013 www.ti.com NOTE Either placement of resistor as shown above is just as effective. APPLICATION CIRCUITS Figure 8. Centigrade Thermostat Figure 9. Conserving Power Dissipation with Shutdown Figure 10. Suggested Connection to a Sampling Analog to Digital Converter Input Stage Most CMOS ADCs found in ASICs have a sampled data comparator input structure that is notorious for causing grief to analog output devices such as the LMT88 and many op amps. The cause of this grief is the requirement of instantaneous charge of the input sampling capacitor in the ADC. This requirement is easily accommodated by the addition of a capacitor. Since not all ADCs have identical input stages, the charge requirements will vary necessitating a different value of compensating capacitor. This ADC is shown as an example only. If a digital output temperature is required please refer to devices such as the LM74. 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMT88 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples LMT88DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 130 T9C LMT88DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 130 T9C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant LMT88DCKR SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMT88DCKT SC70 DCK 5 250 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMT88DCKR SC70 DCK 5 3000 210.0 185.0 35.0 LMT88DCKT SC70 DCK 5 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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As such, the goods being provided may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically found in the end product incorporating the goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may not meet the technical requirements of the directive. Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM User’s Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact the TI application engineer. Persons handling the product must have electronics training and observe good laboratory practice standards. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2002, Texas Instruments Incorporated EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the supply voltage range of 3 V to 3.6 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the supply range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than 125°C. The EVM is designed to operate properly with certain components above 125°C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User’s Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2002, Texas Instruments Incorporated Information About Cautions and Warnings v Preface Read This First About This Manual This EVM user’s guide provides information about the 2-GBPS differential repeater evaluation module. How to Use This Manual This document contains the following chapters:  Chapter 1 — Introduction  Chapter2 — Setup and Equipment Required  Chapter 3 — EVM Construction Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. Related Documentation From Texas Instruments vi Related Documentation From Texas Instruments To obtain a copy of any of the following TI document, call the Texas Instruments Literature Response Center at (800) 477-8924 or the Product Information Center (PIC) at (972) 644-5580. When ordering, identify this booklet by its title and literature number. Updated documents can also be obtained through our website at www.ti.com. Data Sheet: Literature Number: SN65LVDS100/101 SLLS516 SN65CML100 SLLS547 FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. Contents vii Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Signal Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2 Setup and Equipment Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Applying an Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Observing an Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4 Typical Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 3 EVM Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4 Board Layer Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Figures 1-1 EVM With SN65LVDS100 Installed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-2 Schematic of EVM Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2-1 TIA/EIA-644-A LVDS Driver Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-2 EVM Power Connections for SN65LVDS100 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-3 External Termination for Differential CML or LVPECL Inputs to EVM . . . . . . . . . . . . . . . . . 2-4 2-4 External Termination for Single-Ended LVPECL Inputs to EVM . . . . . . . . . . . . . . . . . . . . . . 2-5 2-5 Typical Output From SN65LVDS100 EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Tables 1-1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Contents viii Introduction 1-1 Introduction The 2-GBPS differential repeater evaluation module (EVM) allows evaluation of the SN65LVDS100, SN65LVDS101, and SN65CML100 differential repeaters/ translators. This user’s guide gives a brief overview of the EVM, setup and operation instructions, and typical test results that can be expected. Topic Page 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Signal Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Chapter 1 Overview 1-2 1.1 Overview The 2-GBPS differential repeater evaluation module (EVM) is designed for evaluation of the SN65LVDS100, SN65LVDS101, and SN65CML100 differential repeaters/ translators. The SN65LVDS100 and SN65LVDS101 devices both incorporate wide common-mode range receivers, allowing receipt of LVDS, LVPECL, or CML input signals. The SN65LVDS100 provides an LVDS output, the SN65LVDS101 incorporates an LVPECL output driver, and the SN65CML100 delivers a CML output. Both devices provide a VBB reference voltage to support receiving of single-ended LVPECL input signals, or biasing of ac-coupled inputs. The EVM can be ordered with the SN65LVDS100, SN65LVDS101, or SN65CML100 installed. Orderable EVM part numbers are shown in Table 1-1. Table 1-1. Ordering Information EVM Part Number Installed Device SN65LVDS100EVM SN65LVDS100DGK SN65LVDS101EVM SN65LVDS101DGK SN65CML100EVM SN65CML100DGK Detailed information relating to the SN65LVDS100, SN65LVDS101, and SN65CML100 can be found in the device data sheet, a copy of which is shipped as part of the EVM or available from www.ti.com. A picture of the EVM, with an SN65LVDS100 device installed, is shown in Figure 1-1. Figure 1-1. EVM With SN65LVDS100 Installed Signal Paths Introduction 1-3 1.2 Signal Paths A partial schematic of the EVM is shown in Figure 1-2 and a full schematic is in chapter 3. Edge-mount SMA connectors (J4, J5, J6, and J7) are provided for data input and output connections. Three power jacks (J1, J2, and J3) are used to provide power to and a ground reference, for the EVM. The use of these power jacks is addressed later. Chapter 3 also provides a parts list for the EVM, as well as an indication of which components are installed when shipped. Figure 1-2. Schematic of EVM Signal Path NC A B Vbb VCC Y Z GND R5 Uninstalled JMP2 1 2 C12 .010 μF DUT_MSOP8 DUT1 VCC01 VCC C11 .010 μF R2 Uninstalled J6 GND J7 GND R4 Uninstalled R3 Uninstalled J4 R1 100 Ω GND J5 GND 1 1 1 2 3 4 8 7 6 5 1 1 1-4 Setup and Equipment Required 2-1 Setup and Equipment Required This chapter examines the setup and use of the evaluation module and the results of operation. Topic Page 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Applying an Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Observing an Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4 Typical Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Chapter 2 Overview 2-2 2.1 Overview LVDS driver output characteristics are specified in the TIA/EIA-644 standard. LVDS drivers nominally provide a 350-mV differential signal, with a 1.25-V offset from ground. These levels are attained when driving a 100-Ω differential line-termination test load (see Figure 2-1). In real applications, there may be a ground potential between a driver and receiver(s). The driver must drive the common-mode load presented by the receiver inputs and the differential load. A TIA/EIA-644-A compliant LVDS driver is required to maintain its differential output with up to 32 standard receivers. The receiver load is represented by the 3.74-kΩ resistors shown in Figure 2-1. Figure 2-1. TIA/EIA-644-A LVDS Driver Test Load _ + A B VOD 100 Ω 3.74 kΩ 3.74 kΩ 0 V ≤ Vtest ≤ 2.4 V D LVPECL drivers are generally loaded with 50-Ω resistors to a termination bias voltage, VT. VT is usually 2-V below the supply voltage of the driver circuit. When the driver operates from a 3.3-V supply, VT is set to approximately 1.3 V. CML drivers are generally loaded with 50-Ω resistors to a termination voltage, VTT. VTT can either be equivalent to the supply voltage of the driver circuit (equal to VCC) or set to 2.5 V or 1.8 V, irrelevant to the supply voltage. If desired, the SN65CML100 can be configured to drive a dual 50-Ω load. In this configuration one 50-Ω resistor (tied to the termination voltage VTT) is placed near the output of the SN65CML100 and a second 50-Ω resistor (also tied to VTT) is placed near the end of the transmission line. The EVM has been designed to support the SN65LVDS100 LVDS-output device, the SN65LVDS101 LVPECL-output device, and the SN65CML100 CML-output device. By using the three power jacks (J1, J2, and J3), as well as installing termination resistors (R2, R3, and R4), different methods of termination and probing can be used to evaluate the device output characteristics. The typical setup for the SN65LVDS100 is shown in Figure 2-2. Applying an Input Setup and Equipment Required 2-3 Figure 2-2. EVM Power Connections for SN65LVDS100 Evaluation Pattern Generator Oscilloscope EVM Power Supply 1 + - Power Supply 2 + - EVM VCC GND DUT GND 1.22V 3.3V Matched Cables SMA to SMA Matched Cables SMA to SMA J2 J7 J6 J5 J4 J3 J1 100 Ω 50 Ω 50 Ω Warning Power jacks J1, J2, and J3 are not insulated on the backside of the EVM. Place on a nonconductive surface. 2.2 Applying an Input LVDS inputs should be applied to SMA connectors J4 and J5, while keeping R1 installed. The EVM comes with a 100-Ω termination resistor (R1) installed across the differential inputs. This 100-Ω resistor represents an LVDS termination. When using a general-purpose signal generator with 50-Ω output impedance, make sure that the signal levels are between 0 V to 4 V with respect to J3. A signal generator such as the Advantest D3186 can simulate LVDS, LVPECL, or CML inputs. When using LVPECL or CML drivers for the input signal, termination external to the EVM must be provided (see Figure 2-3). LVPECL drivers should be terminated with 50-Ω pulldowns to VT, while CML drivers should be terminated Applying an Input 2-4 with 50-Ω pullups to VTT. When using external terminations, the onboard termination resistor R1 should be removed from the EVM. It should be noted that the signal quality at the receiver input may be degraded when external terminations are used, as a significant stub exists from the external termination network to the receiver input. The user needs to verify that the transition time of the input signal, coupled with the stub length, does not lead to reflection problems. These concerns would be addressed in a real application where the terminations are placed close to the receiver input. Figure 2-3. External Termination for Differential CML or LVPECL Inputs to EVM Select VT for LVPECL or Select VTT for CML Select VT for LVPECL or Select VTT for CML 50 Ω 50 Ω OUT OUT Signal Source EVM BOARD NOTES: A. Locate 50-Ω resistors as close to the EVM as possible B. Remove R1 A B Y Z Finally, as mentioned above, the SN65LVDS100, SN65LVDS101, and SN65CML100 devices provide a VBB reference voltage output. This output can be used with an externally terminated, single-ended, LVPECL input to convert from a single-ended input to a differential output. The same cautions that are mentioned above concerning signal quality and reflections apply. When using VBB as a single-ended reference, R1 should be removed while R5 and JMP2 should be installed. The single-ended input signal is applied to J4. This setup directly connects the VBB output to the DUT receiver B input via a 0-Ω connection (see Figure 2-4). Observing an Output Setup and Equipment Required 2-5 Figure 2-4. External Termination for Single-Ended LVPECL Inputs to EVM 50 Ω OUT Signal Source EVM BOARD NOTES: A. Add jumper Jmp2 and 0-Ω R5 B. Remove R1 A B Y Z 2.3 Observing an Output Direct connection to an oscilloscope with 50-Ω internal terminations to ground is accomplished without R2, R3, and R41. The outputs are available at J6 and J7 for direct connection to oscilloscope inputs. Matched length cables must be used when connecting the EVM to a scope to avoid inducing skew between the noninverting (+) and inverting (-) outputs. The three power jacks (J1, J2, and J3) are used to provide power and a ground reference for the EVM. The power connections to the EVM determine the common-mode load to the device. As mentioned earlier, LVDS drivers have limited common-mode driver capability. When connecting the EVM outputs directly to oscilloscope inputs, setting of the oscilloscope common-mode offset voltage is required, as the oscilloscope presents low common-mode load impedance to the device. Returning to Figure 2-2, power supply 1 is used to provide the required 3.3 V to the EVM. Power supply 2 is used to offset the EVM ground relative to the DUT ground. The EVM ground is connected to the oscilloscope ground through the returns on SMA connectors J6 and J7. With power applied as shown in Figure 2-2, the common-mode voltage seen by the SN65LVDS100 is approximately equal to the reference voltage being used inside the device preventing significant common-mode current to flow. Optimum device setup can be confirmed by adjusting the voltage on power supply 2 until its current is minimized. It is important to note that use of the dual supplies and offsetting the EVM ground relative to the DUT ground are simply steps needed for the test and evaluation of devices. Actual designs would include high-impedance receivers, which would not require the setup steps outlined above. 1 As delivered R2, R3, and R4 are not installed Typical Test Results 2-6 LVPECL drivers need a 50-Ω termination to VT. A modification of Figure 2-2 and the above instructions are used when evaluating an SN65LVDS101 with a direct connection to a 50-Ω oscilloscope. With power supply 1 in Figure 2-2 set to 3.3 V, power supply 2 should be set to 1.3 V (2 V below VCC) to provide the correct termination voltage. CML drivers need a 50-Ω termination to VTT (VTT is either VCC, 2.5 V, or 1.8 V). A modification of Figure 2-2 and the instructions for the SN65LVDS100 are used when evaluating a SN65CML100 with direct connection to a 50-Ω oscilloscope. With power supply 1 in Figure 2-2 set to 3.3 V, power supply 2 should be set to either VCC (3.3 V), 2.5 V, or 1.8 V to provide the correct termination voltage. Dual termination of the output can be achieved by placing 49.9-Ω resistors at R2 and R3 and connecting to an oscilloscope as described above. If the EVM outputs are to be evaluated with a high-impedance probe, direct probing on the EVM is supported via installation of R2, R3, and R4. LVDS outputs can be observed by installing R4, a 100-Ω resistor. LVPECL outputs can be observed by installing R2 and R3 (49.9-Ω resistors), and setting power supply 2 to 1.3 V. CML outputs can be observed by setting power supply 2 to VTT and installing 49.9-Ω resistors at R2 and R3 for single termination, or 24.9-Ω resistors at R2 and R3 for dual termination (Note that power supply 2 must be able to sink current.) 2.4 Typical Test Results Figure 2-5 shows a typical test result obtained with the EVM. Figure 2-5 shows the output of an SN65LVDS100 being driven directly into a 50-Ω oscilloscope. For this figure, the SN65LVDS100 was stimulated with an HP 3-GBPS BERT. The input data was pseudorandom data at 2 GBPS and with a random record length of 223-1. The BERT drove two electrically matched one-meter cables with an electrical length of 3.667 ns. These cables were then connected to the EVM inputs. The EVM outputs were connected through another set of electrically matched one-meter cables and terminated by a TDS8000 oscilloscope’s 50-Ω resistors to ground. Typical Test Results Setup and Equipment Required 2-7 Figure 2-5. Typical Output From SN65LVDS100 EVM 2-8 EVM Construction 3-1 EVM Construction This chapter lists the EVM components and examines the construction of the evaluation module. Topic Page 3.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4 Board Layer Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Chapter 3 Schematic 3-2 3.1 Schematic NC A B Vbb VCC Y Z GND R5 Uninstalled JMP2 1 2 C12 .010 μF DUT_MSOP8 DUT1 VCC01 VCC C11 .010 μF R2 Uninstalled J6 GND J7 GND R4 Uninstalled R3 Uninstalled J4 R1 100 Ω GND J5 GND 1 1 1 2 3 4 8 7 6 5 1 1 VCC VCC01 + + + + C1 10 μF C6 10 μF C2 68 μF C7 68 μF C3 1 μF C8 1 μF C4 0.1 μF C9 0.1 μF C5 0.001 μF 109 0.001 μF J1 -1 J2 -1 J3 -1 MNTH1 MNTH2 MNTH3 MNTH4 Bill of Materials EVM Construction 3-3 3.2 Bill of Materials ITEM QTY MFG MFG PART NO. REF. DES. DESCRIPTION VALUE OR FUNCTION NOT INSTALLED 1 2 Sprague 293D106X0035D2W C1,C6 Capacitor, SMT, TANT 35 V, 10%, 10 μF 2 2 AVX 12063G105ZATRA C3,C8 Capacitor, SMT1206 25 V, 80 -20%, 1.0 μF 3 2 AVX 12065C104JATMA C4,C9 Capacitor, SMT1206 50 V, 5%, 0.1 μF 4 2 Sprague 592D686X0010R2T C2,C7 Capacitor, SMT, TANT 10 V, 20%, 68 μF, Low ESR 5 2 Murata GRM39X7R103K50V C11, C12 Capacitor, SMT0603 50 V,±10%, 0.010 μF 6 2 AVX 06033G102JATMA C5,C10 Capacitor, SMT0603 25 V, 5%, 0.001 μF 7 3 ITT-Pomona 3267 J1, J2, J3 Connector, banana jack Bannana jack 8 4 EF Johnson 142-0701-801 J4, J5, J6, J7 Connector SMA Jack, end launch, 0.062 9 1 Dale CRCW0603100F R1 Resistor, SMT,0603 100 Ω 10 2 R2, R3 Resistor, SMT, 0603 49.9 Ω R2, R3 11 1 R4 Resistor, SMT, 0603 100 Ω R4 12 1 R5 Resistor, SMT, 0603 0 Ω R5 13 1 AMP 4-103239-0x2 JMP2 Header Male, 2 pin, 0.100 CC 14 1 TI SN65LVDS100† SN65LVDS101† DUT1 IC, SMT, 8P 2-GBPS differential repeater/translator 15 3 Screws 16 3 Nuts 17 1 User’s manual 18 1 Data sheet † Only one is installed Board Stackup 3-4 3.3 Board Stackup 9 Copper Foil CH A1 Copper Foil CH A1 .0062 PREPREG .0062 PREPREG CORE .015 C1/0 A1 .0122 PREPREG CORE .015 C0/1 A1 SECTION A - A NO SCALE TOP SIDE-SIGNAL/GND FILL (LAYER 1) INT1-GND PLANE (LAYER 2) INT2-VCC SPLIT PLANE (LAYER 3) 9 BOTTOM SIDE-GND PLANE (LAYER 4) Symbol Diameter (in) 0.0160 0.0320 0.0400 0.0500 0.1250 0.2720 Plated Yes Yes Yes Yes Yes Yes Quantity 49 82343 Through Holes 3.000 A A 3.000 DATUM 0,0 TOP SIDE SHOWN DRILL 0.250 0.250 NN THIS IS AN IMPEDANCE CONTROLLED BOARD. GENERAL NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL FABRICATION ITEMS MUST MEET OR EXCEED BEST INDUSTRY PRACTICE. IPC-A 600C ( Commercial Std.) 2.LAMINATE MATERIAL: NELCO N4000-13 (DO NOT USE - 13SI) 3. COOPER WEIGHT:1 OZ. START INTERNAL AND 1/2 OZ. START EXTERNAL 4. FINISHED BOARD THICKNESS: .062 ±10% 5. MAXIMUM WARP AND TWIST TO BE .005 INCH PER INCH 6 MINIMUM COPPER WALL THICKNESS OF PLATED-THRU HOLES TO BE .001 INCH 7 MINIMUM ANNULAR RING OF PLATED-THRU HOLES TO BE .002 INCH 8. MINIMUM ALLOWABLE LINE REDUCTION TO BE 20% OR .002 WHICHEVER IS GREATER 9. 0.013 INCH SIGNAL LINES ON LAYER 1 TO BE IMPEDANCE CONTROLLED 50 OHMS TO GND ±10% 0.010 INCH SIGNAL LINES ON LAYER 1 TO BE IMPEDANCE CONTROLLED 100 OHMS TO EACH OTHER ±10% 10. DIELECTRIC CONSTANTS ARE: CORE: 3.2 PREPREG:3.2 PROCESS NOTES: 1. CIRCUITRY ON OUTER LAYERS TO BE PLATED WITH TIN LEAD 2. SOLDERMASK BOTH SIDES PER ARTWORK: GREEN LPI 3. SILKSCREEN BOTH SIDE PER ARTWORK: COLOR=WHITE 4 N 6434666A PWA, BENCH, EVALUATION BOARD, SN65LVDS100/101D, EVM 10/31/01 Board Layer Patterns EVM Construction 3-5 3.4 Board Layer Patterns (Not to Scale) Layer 1 - Signal/GND Fill (Top Side) Layer 2 - GND Plane (INT1) Board Layer Patterns 3-6 Layer 3 - VCC Split Plane (INT2) Layer 4 - GND Plane (Bottom Side) ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Piccolo Microcontrollers Check for Samples: TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051, TMS320F28050 1 TMS320F2805x ( Piccolo™) MCUs 1.1 Features 123 • Highlights • Programmable Control Law Accelerator (CLA) – High-Efficiency 32-Bit CPU ( TMS320C28x™) – 32-Bit Floating-Point Math Accelerator – 60-MHz Device – Executes Code Independently of the Main – Single 3.3-V Supply CPU – Integrated Power-on and Brown-out Resets • Low Device and System Cost: – Two Internal Zero-pin Oscillators – Single 3.3-V Supply – Up to 42 Multiplexed GPIO Pins – No Power Sequencing Requirement – Three 32-Bit CPU Timers – Integrated Power-on Reset and Brown-out – On-Chip Flash, SARAM, Message RAM, OTP, Reset CLA Data ROM, Boot ROM, Secure ROM – Low Power Memory – No Analog Support Pins – Dual-Zone Security Module • Clocking: – Serial Port Peripherals (SCI/SPI/I2C/eCAN) – Two Internal Zero-pin Oscillators – Enhanced Control Peripherals – On-Chip Crystal Oscillator/External Clock • Enhanced Pulse Width Modulator (ePWM) Input • Enhanced Capture (eCAP) – Dynamic PLL Ratio Changes Supported • Enhanced Quadrature Encoder Pulse – Watchdog Timer Module (eQEP) – Missing Clock Detection Circuitry – Analog Peripherals • Up to 42 Individually Programmable, • One 12-Bit Analog-to-Digital Converter Multiplexed GPIO Pins With Input Filtering (ADC) • Peripheral Interrupt Expansion (PIE) Block That • One On-Chip Temperature Sensor Supports All Peripheral Interrupts • Up to Seven Comparators With up to • Three 32-Bit CPU Timers Three Integrated Digital-to-Analog • Independent 16-Bit Timer in Each ePWM Converters (DACs) Module • One Buffered Reference DAC • On-Chip Memory • Up to Four Programmable Gain – Flash, SARAM, Message RAM, OTP, CLA Amplifiers (PGAs) Data ROM, Boot ROM, Secure ROM Available • Up to Four Digital Filters • 128-Bit Security Key and Lock – 80-Pin Package – Protects Secure Memory Blocks • High-Efficiency 32-Bit CPU ( TMS320C28x™) – Prevents Firmware Reverse Engineering – 60 MHz (16.67-ns Cycle Time) • Serial Port Peripherals – 16 x 16 and 32 x 32 MAC Operations – Three SCI (UART) Modules – 16 x 16 Dual MAC – One SPI Module – Harvard Bus Architecture – One Inter-Integrated-Circuit (I2C) Bus – Atomic Operations – One Enhanced Controller Area Network – Fast Interrupt Response and Processing (eCAN) Bus – Unified Memory Programming Model • Advanced Emulation Features – Code-Efficient (in C/C++ and Assembly) – Analysis and Breakpoint Functions • Endianness: Little Endian – Real-Time Debug via Hardware • 80-Pin PN Low-Profile Quad Flatpack (LQFP) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2Piccolo, TMS320C28x, C28x, TMS320C2000, Code Composer Studio, XDS510, XDS560 are trademarks of Texas Instruments. 3All other trademarks are the property of their respective owners. ADVANCE INFORMATION concerns new products in the sampling or preproduction Copyright © 2012, Texas Instruments Incorporated phase of development. Characteristic data and other specifications are subject to change without notice. ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 1.2 Description The F2805x Piccolo™ family of microcontrollers provides the power of the C28x™ core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, as well as providing a high level of analog integration. An internal voltage regulator allows for single rail operation. Analog comparators with internal 6-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead/latency. The Analog Front End (AFE) contains up to seven comparators with up to three integrated Digital-to- Analog Converters (DACs), one VREFOUT-buffered DAC, up to four Programmable Gain Amplifiers (PGAs), and up to four digital filters. The Programmable Gain Amplifiers (PGAs) are capable of amplifying the input signal in three discrete gain modes. The actual gain itself depends on the resistors defined by the user at the bipolar input end. The actual number of AFE peripherals will depend upon the 2805x device number. See Table 2-1 for more details. 2 TMS320F2805x ( Piccolo™) MCUs Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION M0 SARAM 1Kx16 (0-wait) 16-bit Peripheral Bus M1 SARAM 1Kx16 (0-wait) SCI-A, B C (4L FIFO) SCI- , SCI- SPISIMOA SPISOMIA SPICLKA SPISTEA ePWM1–ePWM7 SPI-A (4L FIFO) I2C-A (4L FIFO) 32-Bit Peripheral Bus GPIO MUX C28x CPU (60 MHz) PIE (up to 96 interrupts) CPU Timer 0 CPU Timer 1 CPU Timer 2 TRST TCK TDI TMS TDO OSC1, OSC2, Ext, PLL, LPM, WD X2 32-bit Peripheral Bus (CLA-accessible) EPWMxA EPWMxB SDAx SCLx SCIRXDx GPIO Mux LPM Wakeup CLA + Message RAMs ADC 0-wait Result Regs Boot ROM 12Kx16 (0-wait) Non-Secure L0 SARAM (2Kx16) (0-wait, Secure) CLA Data RAM2 COMP + Digital COMPAn Filter COMPBn 32-bit Peripheral Bus (CLA-accessible) eCAN-A (32-mbox) eCAP ECAPx CANTXx CANRXx eQEP EQEPxA EQEPxB EQEPxI EQEPxS SCITXDx X1 GPIO MUX Program- mable Gain Amps VREG POR/ BOR Memory Bus Memory Bus TZx Secure ROM (A) 2Kx16 (0-wait) Secure L1 DPSARAM (1Kx16) (0-wait, Secure) CLA Data RAM0 L2 DPSARAM (1Kx16) (0-wait, Secure) CLA Data RAM1 L3 DPSARAM (4Kx16) (0-wait, Secure) CLA Program RAM CLA Data ROM (4Kx16) CTRIPnOUT ADC 3.75 MSPS 32-bit Peripheral Bus (CLA-accessible) CLA Bus XRS GPIO Mux XCLKIN 3 External Interrupts Memory Bus EPWMSYNCI EPWMSYNCO PSWD Dual- Zone Security Module + ECSL OTP/Flash Wrapper Z1/Z2 User OTP Secure PUMP FLASH 28055, 28054: 64K x 16, 10 Sectors 28053, 28052, 28051: 32K x 16, 5 Sectors 28050: 16K x 16, 3 Sectors Secure TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 1.3 Functional Block Diagram A. Stores Secure Copy Code Functions on all devices. B. Not all peripheral pins are available at the same time due to multiplexing. Figure 1-1. Functional Block Diagram Copyright © 2012, Texas Instruments Incorporated TMS320F2805x ( Piccolo™) MCUs 3 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 1 TMS320F2805x ( Piccolo™) MCUs .................. 1 5.1 Power Sequencing ................................. 58 1.1 Features ............................................. 1 5.2 Clocking ............................................ 60 1.2 Description ........................................... 2 5.3 Interrupts ............................................ 63 1.3 Functional Block Diagram ........................... 3 6 Peripheral Information and Timings ............... 68 2 Device Overview ........................................ 5 6.1 Parameter Information .............................. 68 2.1 Device Characteristics ............................... 5 6.2 Control Law Accelerator (CLA) ..................... 69 2.2 Memory Maps ........................................ 8 6.3 Analog Block ........................................ 72 2.3 Brief Descriptions ................................... 15 6.4 Serial Peripheral Interface (SPI) .................... 91 2.4 Register Map ....................................... 26 6.5 Serial Communications Interface (SCI) ........... 100 2.5 Device Emulation Registers ........................ 28 6.6 Enhanced Controller Area Network (eCAN) ...... 103 2.6 VREG, BOR, POR .................................. 30 6.7 Inter-Integrated Circuit (I2C) ...................... 107 2.7 System Control ..................................... 32 6.8 Enhanced Pulse Width Modulator (ePWM) ....... 110 2.8 Low-power Modes Block ........................... 40 6.9 Enhanced Capture Module (eCAP) ............... 118 2.9 Thermal Design Considerations .................... 40 6.10 Enhanced Quadrature Encoder Pulse (eQEP) .... 120 3 Device Pins ............................................. 41 6.11 JTAG Port ......................................... 123 3.1 Pin Assignments .................................... 41 6.12 General-Purpose Input/Output (GPIO) ............ 125 3.2 Terminal Functions ................................. 42 7 Device and Documentation Support ............. 136 4 Device Operating Conditions ....................... 50 7.1 Device Support .................................... 136 4.1 Absolute Maximum Ratings ........................ 50 7.2 Documentation Support ........................... 138 4.2 Recommended Operating Conditions .............. 50 7.3 Community Resources ............................ 138 4.3 Electrical Characteristics Over Recommended 8 Mechanical Packaging and Orderable Operating Conditions (Unless Otherwise Noted) ... 51 Information ............................................ 139 4.4 Current Consumption ............................... 52 8.1 Thermal Data for Package ........................ 139 4.5 Flash Timing ........................................ 56 8.2 Packaging Information ............................ 139 5 Power, Reset, Clocking, and Interrupts ........... 58 4 Contents Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 2 Device Overview 2.1 Device Characteristics Table 2-1 lists the features of the TMS320F2805x devices. Copyright © 2012, Texas Instruments Incorporated Device Overview 5 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 2-1. TMS320F2805x Hardware Features FEATURE 28055 28054 28053 28052 28051 28050 (60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz) Package Type 80-Pin PN 80-Pin PN 80-Pin PN 80-Pin PN 80-Pin PN 80-Pin PN LQFP LQFP LQFP LQFP LQFP LQFP Instruction cycle 16.67 ns 16.67 ns 16.67 ns 16.67 ns 16.67 ns 16.67 ns Control Law Accelerator (CLA) Yes No Yes No No No On-chip flash (16-bit word) 64K 64K 32K 32K 32K 16K On-chip SARAM (16-bit word) 10K 10K 10K 10K 8K 6K Dual-zone security for on-chip Flash, SARAM, OTP, Yes Yes Yes Yes Yes Yes and Secure ROM blocks Boot ROM (12K x 16) Yes Yes Yes Yes Yes Yes One-time programmable (OTP) ROM 1K 1K 1K 1K 1K 1K (16-bit word) ePWM outputs 14 14 14 14 14 14 eCAP inputs 1 1 1 1 1 1 eQEP modules 1 1 1 1 1 1 Watchdog timer Yes Yes Yes Yes Yes Yes MSPS 3.75 3.75 3.75 3.75 2 2 Conversion Time 267 ns 267 ns 267 ns 267 ns 500 ns 500 ns 12-Bit ADC Channels 16 16 16 16 16 16 Temperature Sensor Yes Yes Yes Yes Yes Yes Dual Yes Yes Yes Yes Yes Yes Sample-and-Hold Programmable Gain Amplifier (PGA) 4 4 4 4 4 3 (Gains = ~3, ~6, ~11) Fixed Gain Amplifier 3 3 3 3 3 4 (Gain = ~3) Comparators 7 7 7 7 7 6 Internal Comparator Reference DACs 3 3 3 3 3 2 Buffered Reference DAC 1 1 1 1 1 1 32-Bit CPU timers 3 3 3 3 3 3 Inter-integrated circuit (I2C) 1 1 1 1 1 1 Enhanced Controller Area Network (eCAN) 1 1 1 1 1 1 Serial Peripheral Interface (SPI) 1 1 1 1 1 1 Serial Communications Interface (SCI) 3 3 3 3 3 3 0-pin Oscillators 2 2 2 2 2 2 I/O pins (shared) GPIO 42 42 42 42 42 42 External interrupts 3 3 3 3 3 3 Supply voltage (nominal) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 6 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 2-1. TMS320F2805x Hardware Features (continued) FEATURE 28055 28054 28053 28052 28051 28050 (60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz) T: –40ºC to 105ºC Yes Yes Yes Yes Yes Yes Temperature options S: –40ºC to 125ºC Yes Yes Yes Yes Yes Yes Product status(1) TMX TMX TMX TMX TMX TMX (1) See Section 7.1.2, Device and Development Support Tool Nomenclature, for descriptions of device stages. The "TMX" product status denotes an experimental device that is not necessarily representative of the final device's electrical specifications. Copyright © 2012, Texas Instruments Incorporated Device Overview 7 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.2 Memory Maps In Figure 2-1, Figure 2-2, Figure 2-3, and Figure 2-4, the following apply: • Memory blocks are not to scale. • Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are restricted to data memory only. A user program cannot access these memory maps in program space. • Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline order. • Certain memory ranges are EALLOW protected against spurious writes after configuration. 8 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION M0 Vector RAM (Enabled if VMAP = 0) M0 SARAM (1K x 16, 0-Wait) 0x00 0000 0x00 0040 0x00 0400 M1 SARAM (1K x 16, 0-Wait) Data Space Prog Space Reserved 0x00 2000 Reserved Peripheral Frame 1 (1K x 16, Protected) 0x00 6000 Peripheral Frame 3 (1.5K x 16, Protected) 0x00 6400 Peripheral Frame 1 (1.5K x 16, Protected) 0x00 6A00 Peripheral Frame 2 (4K x 16, Protected) 0x00 7000 Reserved 0x00 0800 Peripheral Frame 0 0x00 1580 Peripheral Frame 0 0x00 0D00 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) 0x00 1400 0x00 0E00 0x00 1500 0x00 1480 CPU-to-CLA Message RAM CLA-to-CPU Message RAM CLA Registers Peripheral Frame 0 0x00 8000 L0 DPSARAM (2K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 2) 0x00 8800 L1 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 0) 0x00 8C00 L2 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 1) 0x00 9000 L3 DPSARAM (4K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Prog RAM) 0x3D 7800 User OTP, Zone 2 Passwords (512 x 16) 0x3D 7A00 User OTP, Zone 1 Passwords (512 x 16) 0x00 F000 CLA Data ROM (4K x 16) 0x00 A000 Reserved 0x01 0000 Reserved 0x3D 7C00 Reserved 0x3D 7E00 Calibration Data FLASH (64K x 16, 10 Sectors, Dual Secure Zone + ECSL) (Z1/Z2 User-Selectable Security Zone Per Sector) 0x3E 8000 0x3F 7FFF Zone 1 Secure Copy Code ROM (1K x 16) 0x3F 8000 Zone 2 Secure Copy Code ROM (1K x 16) 0x3F 8400 0x3D 7FCB Configuration Data 0x3F FFC0 0x3F D000 Vector (32 Vectors, Enabled if VMAP = 1) Boot ROM (12K x 16, 0-Wait) 0x3D 7FF0 Reserved 0x3F 8800 Reserved TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 A. CLA-specific registers and RAM apply to the 28055 device only. Figure 2-1. 28055 and 28054 Memory Map Copyright © 2012, Texas Instruments Incorporated Device Overview 9 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION M0 Vector RAM (Enabled if VMAP = 0) M0 SARAM (1K x 16, 0-Wait) 0x00 0000 0x00 0040 0x00 0400 M1 SARAM (1K x 16, 0-Wait) Data Space Prog Space Reserved 0x00 2000 Reserved Peripheral Frame 1 (1K x 16, Protected) 0x00 6000 Peripheral Frame 3 (1.5K x 16, Protected) 0x00 6400 Peripheral Frame 1 (1.5K x 16, Protected) 0x00 6A00 Peripheral Frame 2 (4K x 16, Protected) 0x00 7000 Reserved 0x00 0800 Peripheral Frame 0 0x00 1580 Peripheral Frame 0 0x00 0D00 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) 0x00 1400 0x00 0E00 0x00 1500 0x00 1480 CPU-to-CLA Message RAM CLA-to-CPU Message RAM CLA Registers Peripheral Frame 0 0x00 8000 L0 DPSARAM (2K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 2) 0x00 8800 L1 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 0) 0x00 8C00 L2 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 1) 0x00 9000 L3 DPSARAM (4K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Prog RAM) 0x3D 7800 User OTP, Zone 2 Passwords (512 x 16) 0x3D 7A00 User OTP, Zone 1 Passwords (512 x 16) 0x00 F000 CLA Data ROM (4K x 16) 0x00 A000 Reserved 0x01 0000 Reserved 0x3D 7C00 Reserved 0x3D 7E00 Calibration Data FLASH (32K x 16, 5 Sectors, Dual Secure Zone + ECSL) (Z1/Z2 User-Selectable Security Zone Per Sector) 0x3F 0000 0x3F 7FFF Zone 1 Secure Copy Code ROM (1K x 16) 0x3F 8000 Zone 2 Secure Copy Code ROM (1K x 16) 0x3F 8400 0x3D 7FCB Configuration Data 0x3F FFC0 0x3F D000 Vector (32 Vectors, Enabled if VMAP = 1) Boot ROM (12K x 16, 0-Wait) 0x3D 7FF0 Reserved 0x3F 8800 Reserved TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com A. CLA-specific registers and RAM apply to the 28053 device only. Figure 2-2. 28053 and 28052 Memory Map 10 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION M0 Vector RAM (Enabled if VMAP = 0) M0 SARAM (1K x 16, 0-Wait) 0x00 0000 0x00 0040 0x00 0400 M1 SARAM (1K x 16, 0-Wait) Data Space Prog Space Reserved 0x00 2000 Reserved Peripheral Frame 1 (1K x 16, Protected) 0x00 6000 Peripheral Frame 3 (1.5K x 16, Protected) 0x00 6400 Peripheral Frame 1 (1.5K x 16, Protected) 0x00 6A00 Peripheral Frame 2 (4K x 16, Protected) 0x00 7000 Reserved 0x00 0800 Peripheral Frame 0 0x00 1580 Peripheral Frame 0 0x00 0D00 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) 0x00 1400 0x00 0E00 0x00 1500 0x00 1480 CPU-to-CLA Message RAM CLA-to-CPU Message RAM CLA Registers Peripheral Frame 0 0x00 8000 0x00 8800 L1 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 0) 0x00 8C00 L2 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 1) 0x00 9000 L3 DPSARAM (4K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Prog RAM) 0x3D 7800 User OTP, Zone 2 Passwords (512 x 16) 0x3D 7A00 User OTP, Zone 1 Passwords (512 x 16) 0x00 F000 CLA Data ROM (4K x 16) 0x00 A000 Reserved 0x01 0000 Reserved 0x3D 7C00 Reserved 0x3D 7E00 Calibration Data FLASH (32K x 16, 5 Sectors, Dual Secure Zone + ECSL) (Z1/Z2 User-Selectable Security Zone Per Sector) 0x3F 0000 0x3F 7FFF Zone 1 Secure Copy Code ROM (1K x 16) 0x3F 8000 Zone 2 Secure Copy Code ROM (1K x 16) 0x3F 8400 0x3D 7FCB Configuration Data 0x3F FFC0 0x3F D000 Vector (32 Vectors, Enabled if VMAP = 1) Boot ROM (12K x 16, 0-Wait) 0x3D 7FF0 Reserved 0x3F 8800 Reserved Reserved TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Figure 2-3. 28051 Memory Map Copyright © 2012, Texas Instruments Incorporated Device Overview 11 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION M0 Vector RAM (Enabled if VMAP = 0) M0 SARAM (1K x 16, 0-Wait) 0x00 0000 0x00 0040 0x00 0400 M1 SARAM (1K x 16, 0-Wait) Data Space Prog Space Reserved 0x00 2000 Reserved Peripheral Frame 1 (1K x 16, Protected) 0x00 6000 Peripheral Frame 3 (1.5K x 16, Protected) 0x00 6400 Peripheral Frame 1 (1.5K x 16, Protected) 0x00 6A00 Peripheral Frame 2 (4K x 16, Protected) 0x00 7000 Reserved 0x00 0800 Peripheral Frame 0 0x00 1580 Peripheral Frame 0 0x00 0D00 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) 0x00 1400 0x00 0E00 Peripheral Frame 0 0x00 8000 L0 DPSARAM (2K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL) 0x00 8800 L1 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL) 0x00 8C00 L2 DPSARAM (1K x 16) (0-Wait, Z1 or Z2 Secure Zone + ECSL) 0x00 9000 0x3D 7800 User OTP, Zone 2 Passwords (512 x 16) 0x3D 7A00 User OTP, Zone 1 Passwords (512 x 16) 0x00 F000 0x00 A000 Reserved 0x01 0000 Reserved 0x3D 7C00 Reserved 0x3D 7E00 Calibration Data FLASH (16K x 16, 3 Sectors, Dual Secure Zone + ECSL) (Z1/Z2 User-Selectable Security Zone Per Sector) 0x3F 4000 0x3F 7FFF Zone 1 Secure Copy Code ROM (1K x 16) 0x3F 8000 Zone 2 Secure Copy Code ROM (1K x 16) 0x3F 8400 0x3D 7FCB Configuration Data 0x3F FFC0 0x3F D000 Vector (32 Vectors, Enabled if VMAP = 1) Boot ROM (12K x 16, 0-Wait) 0x3D 7FF0 Reserved 0x3F 8800 Reserved Reserved Reserved Reserved TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 2-4. 28050 Memory Map 12 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 2-2. Addresses of Flash Sectors in F28055 and F28054 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3E 8000 – 0x3E 8FFF Sector J (4K x 16) 0x3E 9000 – 0x3E 9FFF Sector I (4K x 16) 0x3E A000 – 0x3E BFFF Sector H (8K x 16) 0x3E C000 – 0x3E DFFF Sector G (8K x 16) 0x3E E000 – 0x3E FFFF Sector F (8K x 16) 0x3F 0000 – 0x3F 1FFF Sector E (8K x 16) 0x3F 2000 – 0x3F 3FFF Sector D (8K x 16) 0x3F 4000 – 0x3F 5FFF Sector C (8K x 16) 0x3F 6000 – 0x3F 6FFF Sector B (4K x 16) 0x3F 7000 – 0x3F 7FFF Sector A (4K x 16) Table 2-3. Addresses of Flash Sectors in F28053, F28052, and F28051 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3F 0000 – 0x3F 1FFF Sector E (8K x 16) 0x3F 2000 – 0x3F 3FFF Sector D (8K x 16) 0x3F 4000 – 0x3F 5FFF Sector C (8K x 16) 0x3F 6000 – 0x3F 6FFF Sector B (4K x 16) 0x3F 7000 – 0x3F 7FFF Sector A (4K x 16) Table 2-4. Addresses of Flash Sectors in F28050 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3F 4000 – 0x3F 5FFF Sector C (8K x 16) 0x3F 6000 – 0x3F 6FFF Sector B (4K x 16) 0x3F 7000 – 0x3F 7FFF Sector A (4K x 16) Copyright © 2012, Texas Instruments Incorporated Device Overview 13 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these blocks to be write/read peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as written. Because of the pipeline, a write immediately followed by a read to different memory locations will appear in reverse order on the memory bus of the CPU. This action can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The CPU supports a block protection mode where a region of memory can be protected so that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable, and by default, it protects the selected zones. The wait-states for the various spaces in the memory map area are listed in Table 2-5. Table 2-5. Wait-States AREA WAIT-STATES (CPU) COMMENTS M0 and M1 SARAMs 0-wait Fixed Peripheral Frame 0 0-wait Peripheral Frame 1 0-wait (writes) Cycles can be extended by peripheral generated ready. 2-wait (reads) Back-to-back write operations to Peripheral Frame 1 registers will incur a 1-cycle stall (1-cycle delay). Peripheral Frame 2 0-wait (writes) Fixed. Cycles cannot be extended by the peripheral. 2-wait (reads) Peripheral Frame 3 0-wait (writes) Assumes no conflict between CPU and CLA. 2-wait (reads) Cycles can be extended by peripheral-generated ready. L0 SARAM 0-wait data and program Assumes no CPU conflicts L1 SARAM 0-wait data and program Assumes no CPU conflicts L2 SARAM 0-wait data and program Assumes no CPU conflicts L3 SARAM 0-wait data and program Assumes no CPU conflicts OTP Programmable Programmed via the Flash registers. 1-wait minimum 1-wait is minimum number of wait states allowed. FLASH Programmable Programmed via the Flash registers. 0-wait Paged min 1-wait Random min Random ≥ Paged FLASH Password 16-wait fixed Wait states of password locations are fixed. Boot-ROM 0-wait 14 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 2.3 Brief Descriptions 2.3.1 CPU The 2805x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28xbased controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. Each C28x-based controller, including the 2805x device, is a very efficient C/C++ engine, enabling users to develop not only their system control software in a high-level language, but also enabling development of math algorithms using C/C++. The device is as efficient at MCU math tasks as it is at system control tasks. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems efficiently. Add to this feature the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The device has an 8-leveldeep protected pipeline with pipelined memory accesses. This pipelining enables the device to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance. 2.3.2 Control Law Accelerator (CLA) The C28x control law accelerator is a single-precision (32-bit) floating-point unit that extends the capabilities of the C28x CPU by adding parallel processing. The CLA is an independent processor with its own bus structure, fetch mechanism, and pipeline. Eight individual CLA tasks, or routines, can be specified. Each task is started by software or a peripheral such as the ADC, ePWM, eCAP, eQEP, or CPU Timer 0. The CLA executes one task at a time to completion. When a task completes the main CPU is notified by an interrupt to the PIE and the CLA automatically begins the next highest-priority pending task. The CLA can directly access the ADC Result registers, ePWM, eCAP, eQEP, and the Comparator and DAC registers. Dedicated message RAMs provide a method to pass additional data between the main CPU and the CLA. 2.3.3 Memory Bus (Harvard Bus Architecture) As with many MCU-type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows: Highest: Data Writes (Simultaneous data and program writes cannot occur on the memory bus.) Program Writes (Simultaneous data and program writes cannot occur on the memory bus.) Data Reads Program Reads (Simultaneous program reads and fetches cannot occur on the memory bus.) Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.) Copyright © 2012, Texas Instruments Incorporated Device Overview 15 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.3.4 Peripheral Bus To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version supports both 16- and 32-bit accesses (called peripheral frame 1). The third version supports CLA access and both 16- and 32-bit accesses (called peripheral frame 3). 2.3.5 Real-Time JTAG and Analysis The devices implement the standard IEEE 1149.1 JTAG (1) interface for in-circuit based debug. Additionally, the devices support real-time mode of operation allowing modification of the contents of memory, peripheral, and register locations while the processor is running and executing code and servicing interrupts. The user can also single step through non-time-critical code while enabling timecritical interrupts to be serviced without interference. The device implements the real-time mode in hardware within the CPU. This feature is unique to the 28x family of devices, and requires no software monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or data/address watch-points and generating various user-selectable break events when a match occurs. These devices do not support boundary scan; however, IDCODE and BYPASS features are available if the following considerations are taken into account. The IDCODE does not come by default. The user needs to go through a sequence of SHIFT IR and SHIFT DR state of JTAG to get the IDCODE. For BYPASS instruction, the first shifted DR value would be 1. 2.3.6 Flash The F28055 and F28054 devices contain 64K x 16 of embedded flash memory, segregated into six 8K x 16 sectors and four 4K x 16 sectors. The F28053, F28052, and F28051 devices contain 32K x 16 of embedded flash memory, segregated into three 8K x 16 sectors and two 4K x 16 sectors. The F28050 device contains 16K x 16 of embedded flash memory, segregated into one 8K x 16 sector and two 4K x 16 sectors. The devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 – 0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase or program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, the flash/OTP can be used to execute code or store data information. NOTE The Flash and OTP wait-states can be configured by the application. This feature allows applications running at slower frequencies to configure the flash to use fewer wait-states. Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register. With this mode enabled, effective performance of linear code execution will be much faster than the raw performance indicated by the wait-state configuration alone. The exact performance gain when using the Flash pipeline mode is application-dependent. For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5). (1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture 16 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 2.3.7 M0, M1 SARAMs All devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer, which makes for easier programming in high-level languages. 2.3.8 L0 SARAM, and L1, L2, and L3 DPSARAMs The device contains up to 8K x 16 of single-access RAM. To ascertain the exact size for a given device, see the device-specific memory map figures in Section 2.2. This block is mapped to both program and data space. Block L0 is 2K in size and is dual mapped to both program and data space. Blocks L1 and L2 are both 1K in size, and together with L0, are shared with the CLA which can ultilize these blocks for its data space. Block L3 is 4K in size and is shared with the CLA which can ultilize this block for its program space. DPSARAM refers to the dual-port configuration of these blocks. 2.3.9 Boot ROM The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the bootloader software what boot mode to use on power up. The user can select to boot normally or to download new software from an external connection or to select boot software that is programmed in the internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math-related algorithms. Table 2-6. Boot Mode Selection MODE GPIO37/TDO GPIO34/COMP2OUT/ TRST MODE COMP3OUT 3 1 1 0 GetMode 2 1 0 0 Wait (see Section 2.3.10 for description) 1 0 1 0 SCI 0 0 0 0 Parallel IO EMU x x 1 Emulation Boot 2.3.9.1 Emulation Boot When the emulator is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In this case, the boot ROM detects that an emulator is connected and uses the contents of two reserved SARAM locations in the PIE vector table to determine the boot mode. If the content of either location is invalid, then the Wait boot option is used. All boot mode options can be accessed in emulation boot. 2.3.9.2 GetMode The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another boot option by programming two locations in the OTP. If the content of either OTP location is invalid, then boot to flash is used. One of the following loaders can be specified: SCI, SPI, I2C, CAN, or OTP. Copyright © 2012, Texas Instruments Incorporated Device Overview 17 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.3.9.3 Peripheral Pins Used by the Bootloader Table 2-7 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table to see if these conflict with any of the peripherals you would like to use in your application. Table 2-7. Peripheral Bootload Pins BOOTLOADER PERIPHERAL LOADER PINS SCI SCIRXDA (GPIO28) SCITXDA (GPIO29) Parallel Boot Data (GPIO31,30,5:0) 28x Control (GPIO26) Host Control (GPIO27) SPI SPISIMOA (GPIO16) SPISOMIA (GPIO17) SPICLKA (GPIO18) SPISTEA (GPIO19) I2C SDAA (GPIO28) SCLA (GPIO29) CAN CANRXA (GPIO30) CANTXA (GPIO31) 2.3.10 Security The TMS320F2805x device supports high levels of security with a dual-zone (Z1/Z2) feature to protect user's firmware from being reverse-engineered. The dual-zone feature enables the user to co-develop application software with a third-party or sub-contractor by preventing visibility into each other's software IP. The security features a 128-bit password (hardcoded for 16 wait states) for each zone, which the user programs into the USER-OTP. Each zone has its own dedicated USER-OTP, which needs to be programmed by the user with the required security settings, including the 128-bit password. Since OTP cannot be erased, in order to provide the user with the flexibility of changing security-related settings and passwords multiple times, a 32-bit link pointer is stored at the beginning of each USER-OTP. Considering the fact that user can only flip a ‘1’ in USER-OTP to ‘0’, the most significant bit position in the link pointer, programmed as 0, defines the USER-OTP region (zone-select) for each zone in which security-related settings and passwords are stored. Table 2-8. Location of Zone-Select Block Based on Link Pointer Zx LINK POINTER VALUE ADDRESS OFFSET FOR ZONE-SELECT 32’bxx111111111111111111111111111111 0x10 32’bxx111111111111111111111111111110 0x20 32’bxx11111111111111111111111111110x 0x30 32’bxx1111111111111111111111111110xx 0x40 32’bxx111111111111111111111111110xxx 0x50 32’bxx11111111111111111111111110xxxx 0x60 32’bxx1111111111111111111111110xxxxx 0x70 32’bxx111111111111111111111110xxxxxx 0x80 32’bxx11111111111111111111110xxxxxxx 0x90 32’bxx1111111111111111111110xxxxxxxx 0xa0 32’bxx111111111111111111110xxxxxxxxx 0xb0 32’bxx11111111111111111110xxxxxxxxxx 0xc0 32’bxx1111111111111111110xxxxxxxxxxx 0xd0 32’bxx111111111111111110xxxxxxxxxxxx 0xe0 32’bxx11111111111111110xxxxxxxxxxxxx 0xf0 18 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 2-8. Location of Zone-Select Block Based on Link Pointer (continued) Zx LINK POINTER VALUE ADDRESS OFFSET FOR ZONE-SELECT 32’bxx1111111111111110xxxxxxxxxxxxxx 0x100 32’bxx111111111111110xxxxxxxxxxxxxxx 0x110 32’bxx11111111111110xxxxxxxxxxxxxxxx 0x120 32’bxx1111111111110xxxxxxxxxxxxxxxxx 0x130 32’bxx111111111110xxxxxxxxxxxxxxxxxx 0x140 32’bxx11111111110xxxxxxxxxxxxxxxxxxx 0x150 32’bxx1111111110xxxxxxxxxxxxxxxxxxxx 0x160 32’bxx111111110xxxxxxxxxxxxxxxxxxxxx 0x170 32’bxx11111110xxxxxxxxxxxxxxxxxxxxxx 0x180 32’bxx1111110xxxxxxxxxxxxxxxxxxxxxxx 0x190 32’bxx111110xxxxxxxxxxxxxxxxxxxxxxxx 0x1a0 32’bxx11110xxxxxxxxxxxxxxxxxxxxxxxxx 0x1b0 32’bxx1110xxxxxxxxxxxxxxxxxxxxxxxxxx 0x1c0 32’bxx110xxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1d0 32’bxx10xxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1e0 32’bxx0xxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1f0 Table 2-9. Zone-Select Block Organization in USER-OTP 16-BIT ADDRESS OFFSET (WITH RESPECT TO OFFSET OF ZONE-SELECT) CONTENT 0x0 Zx-EXEONLYRAM 0x1 0x2 Zx-EXEONLYSECT 0x3 0x4 Zx-GRABRAM 0x5 0x6 Zx-GRABSECT 0x7 0x8 Zx-CSMPSWD0 0x9 0xa Zx-CSMPSWD1 0xb 0xc Zx-CSMPSWD2 0xd 0xe Zx-CSMPSWD3 0xf The Dual Code Security Module (DCSM) is used to protect the Flash/OTP/Lx SARAM blocks/CLA/Secure ROM content. Individual flash sectors and SARAM blocks can be attached to any of the secure zone at start-up time. Secure ROM and the CLA are always attached to Z1. Resources attached to (owned by) one zone do not have any access to code running in the other zone when it is secured. Individual flash sectors, as well as SARAM blocks, can be further protected by enabling the EXEONLY protection. EXEONLY flash sectors or SARAM blocks do not have READ/WRITE access. Only code execution is allowed from such memory blocks. Copyright © 2012, Texas Instruments Incorporated Device Overview 19 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com The security feature prevents unauthorized users from examining memory contents via the JTAG port, executing code from external memory, or trying to boot load an undesirable software that would export the secure memory contents. To enable access to the secure blocks of a particular zone, the user must write a 128-bit value in the zone’s CSMKEY registers that matches the values stored in the password locations in USER-OTP. If the 128 bits of the password locations in USER-OTP of a particular zone are all ones (un-programmed), then the security for that zone gets UNLOCKED as soon as a dummy read is done to the password locations in USER-OTP (the value in the CSMKEY register becomes "Don’t care" in this case). In addition to the DCSM, the Emulation Code Security Logic (ECSL) has been implemented for each zone to prevent unauthorized users from stepping through secure code. A halt inside secure code will trip the ECSL and break the emulation connection. To allow emulation of secure code while maintaining DCSM protection against secure memory reads, the user must write the lower 64 bits of the USER-OTP password into the zone's CSMKEY register to disable the ECSL. Note that dummy reads of all 128 bits of the password for that particular zone in USER-OTP must still be performed. If the lower 64 bits of the password locations of a particular zone are all zeros, then the ECSL for that zone gets disabled as soon as a dummy read is done to the password locations in USER-OTP (the value in the CSMKEY register becomes "Don’t care" in this case). When initially debugging a device with the password locations in OTP (that is, secured), the CPU will start running and may execute an instruction that performs an access to ECSL-protected area. If the CPU execution is halted when the program counter belongs to the secure code region, the ECSL will trip and cause the emulator connection to be cut. The solution is to use the Wait boot option. The Wait boot option will sit in a loop around a software breakpoint to allow an emulator to be connected without tripping security. The user can then exit this mode once the emulator is connected by using one of the emulation boot options as described in the Boot ROM chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5). 2805x devices do not support hardware wait-in-reset mode. To prevent reverse-engineering of the code in secure zone, unauthorized users are prevented from looking at the CPU registers in the CCS Expressions Window. The values in the Expressions Window for all of these registers, except for PC and some status bits, display false values when code is running from a secure zone. This feature gets disabled if the zone is unlocked. NOTE • The USER-OTP contains security-related settings for their respective zone. Execution is not allowed from the USER-OTP; therefore, the user should not keep any code/data in this region. • The 128-bit password must not be programmed to zeros. Doing so would permanently lock the device. • The user must try not to write into the CPU registers through the debugger watch window when code is running/halted from/inside secure zone. This may corrupt the execution of the actual program. 20 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Disclaimer Dual Code Security Module Disclaimer THE DUAL CODE SECURITY MODULE (DCSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE DCSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE DCSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE DCSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS. 2.3.11 Peripheral Interrupt Expansion (PIE) Block The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F2805x devices, 54 of the possible 96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. Eight CPU clock cycles are needed to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled or disabled within the PIE block. Copyright © 2012, Texas Instruments Incorporated Device Overview 21 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.3.12 External Interrupts (XINT1–XINT3) The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be selected for negative, positive, or both negative and positive edge triggering and can also be enabled or disabled. These interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. There are no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept inputs from GPIO0–GPIO31 pins. 2.3.13 Internal Zero-Pin Oscillators, Oscillator, and PLL The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 12 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer to Section 5.2 for timing details. The PLL block can be set in bypass mode. 2.3.14 Watchdog Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either generate an interrupt or a device reset. 2.3.15 Peripheral Clocking The clocks to each individual peripheral can be enabled or disabled to reduce power consumption when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled relative to the CPU clock. 2.3.16 Low-power Modes The devices are full-static CMOS devices. Three low-power modes are provided: IDLE: Place CPU in low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that need to function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog timer will wake the processor from IDLE mode. STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the interrupt event HALT: This mode basically shuts down the device and places the device in the lowest possible power consumption mode. If the internal zero-pin oscillators are used as the clock source, the HALT mode turns them off, by default. To keep these oscillators from shutting down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin oscillators may thus be used to clock the CPU-watchdog in this mode. If the on-chip crystal oscillator is used as the clock source, the crystal oscillator is shut down in this mode. A reset or an external signal (through a GPIO pin) or the CPUwatchdog can wake the device from this mode. The CPU clock (OSCCLK) and WDCLK should be from the same clock source before attempting to put the device into HALT or STANDBY. 22 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 2.3.17 Peripheral Frames 0, 1, 2, 3 (PFn) The device segregates peripherals into four sections. The mapping of peripherals is as follows: PF0: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table Flash: Flash Waitstate Registers Timers: CPU-Timers 0, 1, 2 Registers DCSM: Dual Zone Security Module Registers ADC: ADC Result Registers CLA Control Law Accelrator Registers and Message RAMs PF1: GPIO: GPIO MUX Configuration and Control Registers eCAN: Enhanced Control Area Network Configuration and Control Registers eCAP: Enhanced Capture Module and Registers eQEP: Enhanced Quadrature Encoder Pulse Module and Registers PF2: SYS: System Control Registers SCI: Serial Communications Interface (SCI) Control and RX/TX Registers SPI: Serial Port Interface (SPI) Control and RX/TX Registers ADC: ADC Status, Control, and Configuration Registers I2C: Inter-Integrated Circuit Module and Registers XINT: External Interrupt Registers PF3: ePWM: Enhanced Pulse Width Modulator Module and Registers Comparators and Comparator Modules Digital Filters: eCAP: Enhanced Capture Module and Registers eQEP: Enhanced Quadrature Encoder Pulse Module and Registers ADC: ADC Status, Control, and Configuration Registers ADC: ADC Result Registers DAC: DAC Control Registers 2.3.18 General-Purpose Input/Output (GPIO) Multiplexer Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This muxing enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also select the number of input qualification cycles. This selection is to filter unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power modes. Copyright © 2012, Texas Instruments Incorporated Device Overview 23 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.3.19 32-Bit CPU-Timers (0, 1, 2) CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, the counter is automatically reloaded with a 32-bit period value. CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and can be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS. CPU-Timer 2 is connected to INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use. CPU-Timer 2 can be clocked by any one of the following: • SYSCLKOUT (default) • Internal zero-pin oscillator 1 (INTOSC1) • Internal zero-pin oscillator 2 (INTSOC2) • External clock source 2.3.20 Control Peripherals The devices support the following peripherals that are used for embedded control and communication: ePWM: The enhanced PWM peripheral supports independent/complementary PWM generation, adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. The type 1 module found on 2805x devices also supports increased dead-band resolution, enhanced SOC and interrupt generation, and advanced triggering including trip functions based on comparator outputs. eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in continuous/one-shot capture modes. This peripheral can also be configured to generate an auxiliary PWM signal. eQEP: The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed measurement using capture unit and high-speed measurement using a 32-bit unit timer. This peripheral has a watchdog timer to detect motor stall and input error detection logic to identify simultaneous edge transition in QEP signals. ADC: The ADC block is a 12-bit converter. The ADC has up to 16 single-ended channels pinned out, depending on the device. The ADC also contains two sample-and-hold units for simultaneous sampling. Comparator and Each comparator block consists of one analog comparator along with an Digital Filter internal 6-bit reference for supplying one input of the comparator. The Subsystems: comparator output signal filtering is achieved using the Digital Filter present on each input line and qualifies the output of the COMP/DAC subsystem. The filtered or unfiltered output of the COMP/DAC subsystem can be configured to be an input to the Digital Compare submodule of the ePWM peripheral. There is also a configurable option to bring the output of the COMP/DAC subsystem onto the GPIO’s. 24 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 2.3.21 Serial Port Peripherals The devices support the following serial communication peripherals: SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. The SPI contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. SCI: The serial communications interface is a two-wire asynchronous serial port, commonly known as UART. The SCI contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. I2C: The inter-integrated circuit (I2C) module provides an interface between an MCU and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit and receive up to 8-bit data to and from the MCU through the I2C module. The I2C contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. eCAN: The eCAN is the enhanced version of the CAN peripheral. The eCAN supports 32 mailboxes, time stamping of messages, and is CAN 2.0B-compliant. Copyright © 2012, Texas Instruments Incorporated Device Overview 25 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.4 Register Map The devices contain four peripheral register spaces. The spaces are categorized as follows: Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 2-10. Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See Table 2-11. Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See Table 2-12. Peripheral Frame 3: These are peripherals that are mapped to CLA in addition to their respective Peripheral Frame. See Table 2-13. Table 2-10. Peripheral Frame 0 Registers(1) NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED(2) Device Emulation Registers 0x00 0880 – 0x00 0984 261 Yes System Power Control Registers 0x00 0985 – 0x00 0987 3 Yes FLASH Registers(3) 0x00 0A80 – 0x00 0ADF 96 Yes ADC registers (0 wait read only) 0x00 0B00 – 0x00 0B0F 16 No DCSM Zone 1 Registers 0x00 0B80 – 0x00 0BBF 64 Yes DCSM Zone 2 Registers 0x00 0BC0 – 0x00 0BEF 48 Yes CPU-TIMER0, CPU-TIMER1, CPU-TIMER2 0x00 0C00 – 0x00 0C3F 64 No Registers PIE Registers 0x00 0CE0 – 0x00 0CFF 32 No PIE Vector Table 0x00 0D00 – 0x00 0DFF 256 No CLA Registers 0x00 1400 – 0x00 147F 128 Yes CLA to CPU Message RAM (CPU writes ignored) 0x00 1480 – 0x00 14FF 128 NA CPU to CLA Message RAM (CLA writes ignored) 0x00 1500 – 0x00 157F 128 NA (1) Registers in Frame 0 support 16-bit and 32-bit accesses. (2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction disables writes to prevent stray code or pointers from corrupting register contents. (3) The Flash Registers are also protected by the Dual Code Security Module (DCSM). Table 2-11. Peripheral Frame 1 Registers NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED eCAN-A Registers 0x00 6000 – 0x00 61FF 512 (1) eCAP1 Registers 0x00 6A00 – 0x00 6A1F 32 No eQEP1 Registers 0x00 6B00 – 0x00 6B3F 64 (1) GPIO Registers 0x00 6F80 – 0x00 6FFF 128 (1) (1) Some registers are EALLOW protected. See the module reference guide for more information. 26 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 2-12. Peripheral Frame 2 Registers NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED System Control Registers 0x00 7010 – 0x00 702F 32 Yes SPI-A Registers 0x00 7040 – 0x00 704F 16 No SCI-A Registers 0x00 7050 – 0x00 705F 16 No NMI Watchdog Interrupt Registers 0x00 7060 – 0x00 706F 16 Yes External Interrupt Registers 0x00 7070 – 0x00 707F 16 Yes ADC Registers 0x00 7100 – 0x00 717F 128 (1) I2C-A Registers 0x00 7900 – 0x00 793F 64 (1) (1) Some registers are EALLOW protected. See the module reference guide for more information. Table 2-13. Peripheral Frame 3 Registers NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED ADC registers 0x00 0B00 – 0x00 0B0F 16 No (0 wait read only) DAC Control Registers 0x00 6400 – 0x00 640F 16 Yes DAC, PGA, Comparator, and Filter Enable 0x00 6410 – 0x00 641F 16 Yes Registers SWITCH Registers 0x00 6420 – 0x00 642F 16 Yes Digital Filter and Comparator Control Registers 0x00 6430 – 0x00 647F 80 Yes LOCK Registers 0x00 64F0 – 0x00 64FF 16 Yes ePWM1 registers 0x00 6800 – 0x00 683F 64 (1) ePWM2 registers 0x00 6840 – 0x00 687F 64 (1) ePWM3 registers 0x00 6880 – 0x00 68BF 64 (1) ePWM4 registers 0x00 68C0 – 0x00 68FF 64 (1) ePWM5 registers 0x00 6900 – 0x00 693F 64 (1) ePWM6 registers 0x00 6940 – 0x00 697F 64 (1) ePWM7 registers 0x00 6980 – 0x00 69BF 64 (1) eCAP1 Registers 0x00 6A00 – 0x00 6A1F 32 No eQEP1 Registers 0x00 6B00 – 0x00 6B3F 64 (1) (1) Some registers are EALLOW protected. See the module reference guide for more information. Copyright © 2012, Texas Instruments Incorporated Device Overview 27 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.5 Device Emulation Registers These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 2-14. Table 2-14. Device Emulation Registers NAME ADDRESS SIZE (x16) DESCRIPTION EALLOW RANGE PROTECTED DEVICECNF 0x0880 – 2 Device Configuration Register Yes 0x0881 PARTID 0x0882 1 PARTID Register TMS320F28055 0x0105 TMS320F28054 0x0104 TMS320F28053 0x0103 No TMS320F28052 0x0102 TMS320F28051 0x0101 TMS320F28050 0x0100 REVID 0x0883 1 Revision ID 0x0000 - Silicon Rev. 0 - TMX No Register DC1 0x0886 – 2 Device Capability Register 1. 0x0887 The Device Capability Register is predefined by the part and Yes can be used to verify features. If any bit is “zero” in this register, the module is not present. See Table 2-15. DC2 0x0888 – 2 Device Capability Register 2. 0x0889 The Device Capability Register is predefined by the part and Yes can be used to verify features. If any bit is “zero” in this register, the module is not present. See Table 2-16. DC3 0x088A – 2 Device Capability Register 3. 0x088B The Device Capability Register is predefined by the part and Yes can be used to verify features. If any bit is “zero” in this register, the module is not present. See Table 2-17. Table 2-15. Device Capability Register 1 (DC1) Field Descriptions(1) BIT FIELD TYPE DESCRIPTION 31–30 RSVD R = 0 Reserved 29–22 PARTNO R These 8 bits set the PARTNO field value in the PARTID register for the device. They are readable in the PARTID[7:0] register bits. 21–14 RSVD R = 0 Reserved 13 CLA R CLA is present when this bit is set. 12–7 RSVD R = 0 Reserved 6 L3 R L3 is present when this bit is set. 5 L2 R L2 is present when this bit is set. 4 L1 R L1 is present when this bit is set. 3 L0 R L0 is present when this bit is set. 2 RSVD R = 0 Reserved 1–0 RSVD R = 0 Reserved (1) All reserved bits should not be written to but if any use case demands that they must be written to, then software must write the same value that is read back from the reserved bits. These bits are reserved for future enhancements. 28 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 2-16. Device Capability Register 2 (DC2) Field Descriptions(1) BIT FIELD TYPE DESCRIPTION 31–28 RSVD R = 0 Reserved 27 eCAN-A R eCAN-A is present when this bit is set. 26–17 RSVD R = 0 Reserved 16 EQEP-1 R eQEP-1 is present when this bit is set. 15–13 RSVD R = 0 Reserved 12 ECAP-1 R eCAP-1 is present when this bit is set. 11–9 RSVD R = 0 Reserved 8 I2C-A R I2C-A is present when this bit is set. 7–5 RSVD R = 0 Reserved 4 SPI-A R SPI-A is present when this bit is set. 3 RSVD R = 0 Reserved 2 SCI-C R SCI-C is present when this bit is set. 1 SCI-B R SCI-B is present when this bit is set. 0 SCI-A R SCI-A is present when this bit is set. (1) All reserved bits should not be written to but if any use case demands that they must be written to, then software must write the same value that is read back from the reserved bits. These bits are reserved for future enhancements. Table 2-17. Device Capability Register 3 (DC3) Field Descriptions(1) BIT FIELD TYPE DESCRIPTION 31–20 RSVD R = 0 Reserved 19 CTRIPFIL7 R CTRIPFIL7(B7) is present when this bit is set. 18 CTRIPFIL6 R CTRIPFIL6(B6) is present when this bit is set. 17 CTRIPFIL5 R CTRIPFIL5(B4) is present when this bit is set. 16 CTRIPFIL4 R CTRIPFIL4(A6) is present when this bit is set. 15 CTRIPFIL3 R CTRIPFIL3(B1) is present when this bit is set. 14 CTRIPFIL2 R CTRIPFIL2(A3) is present when this bit is set. 13 CTRIPFIL1 R CTRIPFIL1(A1) is present when this bit is set. 12–8 RSVD R = 0 Reserved 7 RSVD R = 0 Reserved 6 ePWM7 R ePWM7 is present when this bit is set. 5 ePWM6 R ePWM6 is present when this bit is set. 4 ePWM5 R ePWM5 is present when this bit is set. 3 ePWM4 R ePWM4 is present when this bit is set. 2 ePWM3 R ePWM3 is present when this bit is set. 1 ePWM2 R ePWM2 is present when this bit is set. 0 ePWM1 R ePWM1 is present when this bit is set. (1) All reserved bits should not be written to but if any use case demands that they must be written to, then software must write the same value that is read back from the reserved bits. These bits are reserved for future enhancements. Copyright © 2012, Texas Instruments Incorporated Device Overview 29 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.6 VREG, BOR, POR Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip voltage regulator (VREG) to generate the VDD voltage from the VDDIO supply. This feature eliminates the cost and space of a second external regulator on an application board. Additionally, internal power-on reset (POR) and brown-out reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode. 2.6.1 On-chip Voltage Regulator (VREG) A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors are required on each VDD pin to stabilize the generated voltage, power need not be supplied to these pins to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the primary concern of the application. 2.6.1.1 Using the On-chip VREG To utilize the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended operating voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by the core logic will be generated by the VREG. Each VDD pin requires on the order of 1.2 μF (minimum) capacitance for proper regulation of the VREG. These capacitors should be located as close as possible to the VDD pins. 2.6.1.2 Disabling the On-chip VREG To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to the VDD pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied high. 30 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION I/O Pin In Out DIR (0 = Input, 1 = Output) (Force Hi-Z When High) SYSRS C28x Core Sync RS XRS PLL + Clocking Logic MCLKRS VREGHALT Deglitch Filter On-Chip Voltage Regulator (VREG) VREGENZ POR/BOR Generating Module XRS Pin SYSCLKOUT WDRST (A) JTAG TCK Detect Logic PBRS (B) Internal Weak PU TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 2.6.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit The purpose of the POR is to create a clean reset throughout the device during the entire power-up procedure. The trip point is a looser, lower trip point than the BOR, which watches for dips in the VDD or VDDIO rail during device operation. The POR function is present on both VDD and VDDIO rails at all times. After initial device power-up, the BOR function is present on VDDIO at all times, and on VDD when the internal VREG is enabled (VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the voltages is below their respective trip point. Additionally, when the internal voltage regulator is enabled, an over-voltage protection circuit will tie XRS low if the VDD rail rises above its trip point. See Section 4.3 for the various trip points as well as the delay time for the device to release the XRS pin after the undervoltage or over-voltage condition is removed. Figure 2-5 shows the VREG, POR, and BOR. To disable both the VDD and VDDIO BOR functions, a bit is provided in the BORCFG register. See the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5) for details. A. WDRST is the reset signal from the CPU-watchdog. B. PBRS is the reset signal from the POR/BOR module. Figure 2-5. VREG + POR + BOR + Reset Signal Connectivity Copyright © 2012, Texas Instruments Incorporated Device Overview 31 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.7 System Control This section describes the oscillator and clocking mechanisms, the watchdog function and the low power modes. Table 2-18. PLL, Clocking, Watchdog, and Low-Power Mode Registers NAME ADDRESS SIZE (x16) DESCRIPTION(1) BORCFG 0x00 0985 1 BOR Configuration Register XCLK 0x00 7010 1 XCLKOUT Control PLLSTS 0x00 7011 1 PLL Status Register CLKCTL 0x00 7012 1 Clock Control Register PLLLOCKPRD 0x00 7013 1 PLL Lock Period INTOSC1TRIM 0x00 7014 1 Internal Oscillator 1 Trim Register INTOSC2TRIM 0x00 7016 1 Internal Oscillator 2 Trim Register LOSPCP 0x00 701B 1 Low-Speed Peripheral Clock Prescaler Register PCLKCR0 0x00 701C 1 Peripheral Clock Control Register 0 PCLKCR1 0x00 701D 1 Peripheral Clock Control Register 1 LPMCR0 0x00 701E 1 Low Power Mode Control Register 0 PCLKCR3 0x00 7020 1 Peripheral Clock Control Register 3 PLLCR 0x00 7021 1 PLL Control Register SCSR 0x00 7022 1 System Control and Status Register WDCNTR 0x00 7023 1 Watchdog Counter Register PCLKCR4 0x00 7024 1 Peripheral Clock Control Register 4 WDKEY 0x00 7025 1 Watchdog Reset Key Register WDCR 0x00 7029 1 Watchdog Control Register (1) All registers in this table are EALLOW protected. 32 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION PCLKCR0/1/3/4 (System Ctrl Regs) LOSPCP (System Ctrl Regs) I/O Clock Enables LSPCLK Peripheral Registers SPI-A, SCI-A, SCI-B, SCI-C SYSCLKOUT Clock Enables Peripheral Registers I/O eCAP1, eQEP1 Clock Enables Peripheral Registers ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6, ePWM7 I/O Clock Enables Peripheral Registers I/O I2C-A Clock Enables ADC 9 Ch 12-Bit ADC Registers Clock Enables AFE AFE Registers 7 Ch GPIO Mux Analog C28x Core CLKIN Peripheral I/O eCAN-A Registers /2 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Figure 2-6 shows the various clock domains that are discussed. Figure 2-7 shows the various clock sources (both internal and external) that can provide a clock for device operation. A. CLKIN is the clock into the CPU. CLKIN is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as SYSCLKOUT). Figure 2-6. Clock and Reset Domains Copyright © 2012, Texas Instruments Incorporated Device Overview 33 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION INTOSC1TRIM Reg (A) Internal OSC 1 (10 MHz) OSCE CLKCTL[INTOSC1OFF] WAKEOSC CLKCTL[INTOSC1HALT] INTOSC2TRIM Reg (A) Internal OSC 2 (10 MHz) OSCE CLKCTL[INTOSC2OFF] CLKCTL[INTOSC2HALT] 1 = Turn OSC Off 1 = Ignore HALT 1 = Turn OSC Off 1 = Ignore HALT XCLK[XCLKINSEL] 0 = GPIO38 1 = GPIO19 GPIO19 or GPIO38 CLKCTL[XCLKINOFF] 0 0 1 (Crystal) OSC XCLKIN X1 X2 CLKCTL[XTALOSCOFF] 0 = OSC on (default on reset) 1 = Turn OSC off 0 1 0 1 OSC1CLK OSCCLKSRC1 WDCLK OSC2CLK 0 1 CLKCTL[WDCLKSRCSEL] (OSC1CLK on XRS reset) CLKCTL[OSCCLKSRCSEL] CLKCTL[TRM2CLKPRESCALE] CLKCTL[TMR2CLKSRCSEL] OSCCLKSRC2 11 Prescale /1, /2, /4, /8, /16 00 01, 10, 11 CPUTMR2CLK SYNC Edge Detect 10 01 CLKCTL[OSCCLKSRC2SEL] SYSCLKOUT WAKEOSC (Oscillators enabled when this signal is high) EXTCLK XTAL XCLKIN (OSC1CLK on XRS reset) OSCCLK PLL Missing-Clock-Detect Circuit (B) CPU-Watchdog TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com A. Register loaded from TI OTP-based calibration function. B. See Section 2.7.4 for details on missing clock detection. Figure 2-7. Clock Tree 34 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION External Clock Signal (Toggling 0−VDDIO) XCLKIN/GPIO19/38 X2 NC X1 X1 X2 Crystal XCLKIN/GPIO19/38 Turn off XCLKIN path in CLKCTL register Rd CL1 CL2 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 2.7.1 Internal Zero-Pin Oscillators The F2805x devices contain two independent internal zero-pin oscillators. By default both oscillators are turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings, unused oscillators may be powered down by the user. The center frequency of these oscillators is determined by their respective oscillator trim registers, written to in the calibration routine as part of the boot ROM execution. See Section 5.2.1 for more information on these oscillators. 2.7.2 Crystal Oscillator Option The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in Table 2-19. Furthermore, ESR range = 30 to 150 Ω. Table 2-19. Typical Specifications for External Quartz Crystal(1) FREQUENCY (MHz) Rd (Ω) CL1 (pF) CL2 (pF) 5 2200 18 18 10 470 15 15 15 0 15 15 20 0 12 12 (1) Cshunt should be less than or equal to 5 pF. Figure 2-8. Using the On-chip Crystal Oscillator NOTE 1. CL1 and CL2 are the total capacitance of the circuit board and components excluding the IC and crystal. The value is usually approximately twice the value of the crystal's load capacitance. 2. The load capacitance of the crystal is described in the crystal specifications of the manufacturers. 3. TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the MCU chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will produce proper start up and stability over the entire operating range. Figure 2-9. Using a 3.3-V External Oscillator Copyright © 2012, Texas Instruments Incorporated Device Overview 35 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.7.3 PLL-Based Clock Module The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. The watchdog module can be re-enabled (if need be) after the PLL module has stabilized, which takes 1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL (VCOCLK) is at least 50 MHz. Table 2-20. PLL Settings SYSCLKOUT (CLKIN) PLLCR[DIV] VALUE(1) (2) PLLSTS[DIVSEL] = 0 or 1(3) PLLSTS[DIVSEL] = 2 PLLSTS[DIVSEL] = 3 0000 (PLL bypass) OSCCLK/4 (Default)(1) OSCCLK/2 OSCCLK 0001 (OSCCLK * 1)/4 (OSCCLK * 1)/2 (OSCCLK * 1)/1 0010 (OSCCLK * 2)/4 (OSCCLK * 2)/2 (OSCCLK * 2)/1 0011 (OSCCLK * 3)/4 (OSCCLK * 3)/2 (OSCCLK * 3)/1 0100 (OSCCLK * 4)/4 (OSCCLK * 4)/2 (OSCCLK * 4)/1 0101 (OSCCLK * 5)/4 (OSCCLK * 5)/2 (OSCCLK * 5)/1 0110 (OSCCLK * 6)/4 (OSCCLK * 6)/2 (OSCCLK * 6)/1 0111 (OSCCLK * 7)/4 (OSCCLK * 7)/2 (OSCCLK * 7)/1 1000 (OSCCLK * 8)/4 (OSCCLK * 8)/2 (OSCCLK * 8)/1 1001 (OSCCLK * 9)/4 (OSCCLK * 9)/2 (OSCCLK * 9)/1 1010 (OSCCLK * 10)/4 (OSCCLK * 10)/2 (OSCCLK * 10)/1 1011 (OSCCLK * 11)/4 (OSCCLK * 11)/2 (OSCCLK * 11)/1 1100 (OSCCLK * 12)/4 (OSCCLK * 12)/2 (OSCCLK * 12)/1 (1) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog reset only. A reset issued by the debugger or the missing clock detect logic has no effect. (2) This register is EALLOW protected. See the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5) for more information. (3) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes the PLLSTS[DIVSEL] configuration to /1.) PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1. Table 2-21. CLKIN Divide Options PLLSTS [DIVSEL] CLKIN DIVIDE 0 /4 1 /4 2 /2 3 /1 36 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 The PLL-based clock module provides four modes of operation: • INTOSC1 (Internal Zero-pin Oscillator 1): INTOSC1 is the on-chip internal oscillator 1. INTOSC1 can provide the clock for the Watchdog block, core and CPU-Timer 2. • INTOSC2 (Internal Zero-pin Oscillator 2): INTOSC2 is the on-chip internal oscillator 2. INTOSC2 can provide the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be independently chosen for the Watchdog block, core and CPU-Timer 2. • Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external crystal/resonator attached to the device to provide the time base. The crystal/resonator is connected to the X1/X2 pins. Some devices may not have the X1/X2 pins. See Table 3-1 for details. • External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows the on-chip (crystal) oscillator to be bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin. Note that the XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected as GPIO19 or GPIO38 via the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit disables this clock input (forced low). If the clock source is not used or the respective pins are used as GPIOs, the user should disable at boot time. Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that clock source must be disabled (using the CLKCTL register) before switching clocks. Table 2-22. Possible PLL Configuration Modes PLL MODE REMARKS PLLSTS[DIVSEL] CLKIN AND SYSCLKOUT Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block is disabled in this mode. The PLL block being disabled can be useful in reducing 0, 1 OSCCLK/4 PLL Off system noise and for low-power operation. The PLLCR register must first be set to 2 OSCCLK/2 0x0000 (PLL Bypass) before entering this mode. The CPU clock (CLKIN) is 3 OSCCLK/1 derived directly from the input clock on either X1/X2, X1 or XCLKIN. PLL Bypass is the default PLL configuration upon power-up or after an external 0, 1 OSCCLK/4 PLL Bypass reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or 2 OSCCLK/2 while the PLL locks to a new frequency after the PLLCR register has been 3 OSCCLK/1 modified. In this mode, the PLL itself is bypassed but the PLL is not turned off. Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the 0, 1 OSCCLK * n/4 PLL Enable PLLCR the device will switch to PLL Bypass mode until the PLL locks. 2 OSCCLK * n/2 3 OSCCLK * n/1 2.7.4 Loss of Input Clock (NMI Watchdog Function) The 2805x devices may be clocked from either one of the internal zero-pin oscillators (INTOSC1 or INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of the clock source, in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will issue a limpmode clock at its output. This limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1–5 MHz. When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt. Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired immediately or the NMI watchdog counter can issue a reset when the counter overflows. In addition to this action, the Missing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect the input clock failure and initiate necessary corrective action such as switching over to an alternative clock source (if available) or initiate a shut-down procedure for the system. If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a preprogrammed time interval. Figure 2-10 shows the interrupt mechanisms involved. Copyright © 2012, Texas Instruments Incorporated Device Overview 37 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION NMIFLG[NMINT] 1 0 Generate Interrupt Pulse When Input = 1 NMINT Latch Clear Set Clear NMIFLGCLR[NMINT] XRS 0 NMICFG[CLOCKFAIL] Latch Clear Clear Set XRS NMIFLG[CLOCKFAIL] NMI Watchdog SYSCLKOUT SYSRS NMIRS NMIWDPRD[15:0] NMIWDCNT[15:0] NMIFLGCLR[CLOCKFAIL] SYNC? NMIFLGFRC[CLOCKFAIL] SYSCLKOUT See System Control Section CLOCKFAIL TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 2-10. NMI-watchdog 2.7.5 CPU-Watchdog Module The CPU-watchdog module on the 2805x device is similar to the one used on the 281x, 280x, and 283xx devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this occurrence, the user must disable the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets the watchdog counter. Figure 2-11 shows the various functional blocks within the watchdog module. Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPUwatchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog counter stops decrementing (that is, the watchdog counter does not change with the limp-mode clock). NOTE The CPU-watchdog is different from the NMI watchdog. The CPU-watchdog is the legacy watchdog that is present in all 28x devices. NOTE Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism by which the MCU will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent the capacitor from getting fully charged. Such a circuit would also help in detecting failure of the flash memory. 38 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION /512 WDCLK WDCR (WDPS[2:0]) WDCLK WDCNTR(7:0) WDKEY(7:0) Good Key 1 0 1 WDCR (WDCHK[2:0]) Bad WDCHK Key WDCR (WDDIS) Clear Counter SCSR (WDENINT) Watchdog Prescaler Generate Output Pulse (512 OSCCLKs) 8-Bit Watchdog Counter CLR WDRST WDINT Watchdog 55 + AA Key Detector XRS Core-reset WDRST(A) Internal Pullup TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 A. The WDRST signal is driven low for 512 OSCCLK cycles. Figure 2-11. CPU-watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM block so that the signal can wake the device from STANDBY (if enabled). See Section 2.8, Low-power Modes Block, for more details. In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode. In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset. Copyright © 2012, Texas Instruments Incorporated Device Overview 39 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 2.8 Low-power Modes Block Table 2-23 summarizes the various modes. Table 2-23. Low-power Modes MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT EXIT(1) IDLE 00 On On On XRS, CPU-watchdog interrupt, any enabled interrupt STANDBY 01 On Off Off XRS, CPU-watchdog interrupt, GPIO (CPU-watchdog still running) Port A signal, debugger(2) Off (on-chip crystal oscillator and XRS, GPIO Port A signal, debugger(2), HALT(3) 1X PLL turned off, zero-pin oscillator Off Off CPU-watchdog and CPU-watchdog state dependent on user code.) (1) The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-power mode will not be exited and the device will go back into the indicated low power mode. (2) The JTAG port can still function even if the CPU clock (CLKIN) is turned off. (3) The WDCLK must be active for the device to go into HALT mode. The various low-power modes operate as follows: IDLE Mode: This mode is exited by any enabled interrupt that is recognized by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0. STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must select which signals will wake the device in the GPIOLPMSEL register. The selected signals are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register. HALT Mode: CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT mode. The user selects the signal in the GPIOLPMSEL register. NOTE The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them in when the IDLE instruction was executed. See the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5) for more details. 2.9 Thermal Design Considerations Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal application reports IC Package Thermal Metrics (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices (literature number SPRA963) help to understand the thermal metrics and definitions. 40 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 41 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 21 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 80 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 VSSA VSS VDDIO GPIO26/SCIRXDC TEST2 GPIO9/EPWM5B/SCITXDB GPIO30/CANRXA/SCIRXDB/EPWM7A GPIO31/CANTXA/SCITXDB/EPWM7B GPIO27/SCITXDC PFCGND ADCINB7 (op-amp) ADCINB0 ADCINB6 (op-amp) ADCINB5 M2GND ADCINB4 (op-amp) ADCINB3 ADCINA7 ADCINA6 (op-amp) VREFLO GPIO23/EQEP1I/SCIRXDB GPIO11/EPWM6B/SCIRXDB GPIO5/EPWM3B/SPISIMOA/ECAP1 GPIO4/EPWM3A GPIO40/EPWM7A GPIO10/EPWM6A/ADCSOCBO GPIO3/EPWM2B/SPISOMIA/CTRIPM2OUT (COMP2OUT) GPIO2/EPWM2A GPIO1/EPWM1B/CTRIPM1OUT (COMP1OUT) GPIO0/EPWM1A VDDIO VREGENZ VSS VDD GPIO34/CTRIPM2OUT (COMP2OUT)/CTRIPPFCOUT (COMP3OUT) GPIO15/TZ1/CTRIPM1OUT/SCIRXDB GPIO13/TZ2/CTRIPM2OUT GPIO14/TZ3/CTRIPPFCOUT/SCITXDB GPIO20/EQEP1A/EPWM7A/CTRIPM1OUT (COMP1OUT) GPIO21/EQEP1B/EPWM7B/CTRIPM2OUT (COMP2OUT) VDDA GPIO22/EQEP1S/SCITXDB XRS GPIO32/SDAA/EPWMSYNCI/EQEP1S GPIO33/SCLA/EPWMSYNCO/EQEP1I GPIO24/ECAP1/EPWM7A GPIO42/EPWM7B/SCITXDC/CTRIPM1OUT (COMP1OUT) VDD VSS TRST ADCBGOUT/ADCINA4 ADCINA5 ADCINA3 (op-amp) ADCINA2 ADCINA1 (op-amp) M1GND ADCINB2 ADCINB1 (op-amp) ADCINA0/VREFOUT VREFHI GPIO29/SCITXDA/SCLA/ /CTRIPPFCOUTTZ3 GPIO36/TMS GPIO35/TDI GPIO37/TDO GPIO38/TCK/XCLKIN GPIO39/SCIRXDC/CTRIPPFCOUT GPIO19/XCLKIN/ /SCIRXDB/ECAP1SPISTEA VDD VSS X1 X2 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO GPIO7/EPWM4B/SCIRXDA GPIO16/SPISIMOA/EQEP1S/ /CTRIPM2OUTTZ2 GPIO12/ /CTRIPM1OUT/SCITXDATZ1 GPIO25 GPIO8/EPWM5A/ADCSOCAO GPIO17/SPISOMIA/EQEP1I/ /CTRIPPFCOUTTZ3 GPIO18/SPICLKA/SCITXDB/XCLKOUT GPIO28/SCIRXDA/SDAA/TZ2/CTRIPM2OUT TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 3 Device Pins 3.1 Pin Assignments Figure 3-1 shows the 80-pin PN Low-Profile Quad Flatpack (LQFP) pin assignments. Figure 3-1. 2805x 80-Pin PN LQFP (Top View) Copyright © 2012, Texas Instruments Incorporated Device Pins 41 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 3.2 Terminal Functions Table 3-1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 2-1 for details. Inputs are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. NOTE: When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 pins could glitch during power up. If this behavior is unacceptable in an application, 1.8 V could be supplied externally. There is no power-sequencing requirement when using an external 1.8-V supply. However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered prior to the 1.9-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins prior to or simultaneously with the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V. Table 3-1. Terminal Functions(1) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. JTAG JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an active high test pin and must be maintained low at all times during normal device operation. TRST 9 I An external pull-down resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. (↓) TCK See I See GPIO38. JTAG test clock with internal pullup. (↑) GPIO38 TMS See I See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is GPIO36 clocked into the TAP controller on the rising edge of TCK.. (↑) TDI See I See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected GPIO35 register (instruction or data) on a rising edge of TCK. (↑) TDO See O/Z See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register GPIO37 (instruction or data) are shifted out of TDO on the falling edge of TCK. (8 mA drive) FLASH TEST2 39 I/O Test Pin. Reserved for TI. Must be left unconnected. (1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown 42 Device Pins Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. CLOCK See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same See frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. The value of XCLKOUT GPIO18 O/Z XCLKOUT is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin. See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to See GND and the on-chip crystal oscillator must be disabled via bit 14 in the CLKCTL register. If a XCLKIN GPIO19 I crystal/resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. and NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock for normal GPIO38 device operation may need to incorporate some hooks to disable this path during debug using the JTAG connector. This action is to prevent contention with the TCK signal, which is active during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to clock the device. On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator X1 52 I must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, this pin must be tied to GND. (I) X2 51 O On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, X2 must be left unconnected. (O) RESET Device Reset (in) and Watchdog Reset (out). The device has a built-in power-on-reset (POR) and brown-out-reset (BOR) circuitry. As such, no external circuitry is needed to generate a reset pulse. During a power-on or brown-out condition, this pin is driven low by the device. See Section 4.3, Electrical Characteristics, for thresholds of the POR/BOR block. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS XRS 8 I/O pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. If need be, an external circuitry may also drive this pin to assert a device reset. In this case, TI recommends that this pin be driven by an open-drain device. An R-C circuit must be connected to this pin for noise immunity reasons. Regardless of the source, a device reset causes the device to terminate execution. The program counter points to the address contained at the location 0x3FFFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain with an internal pullup. (I/OD) Copyright © 2012, Texas Instruments Incorporated Device Pins 43 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. ADC, COMPARATOR, ANALOG I/O ADCINA7 24 I ADC Group A, Channel 7 input ADCINA6 23 I ADC Group A, Channel 6 input (op-amp) ADCINA5 10 I ADC Group A, Channel 5 input ADCBGOUT 11 O ADCINA4 I ADC Group A, Channel 4 input ADCINA3 12 I ADC Group A, Channel 3 input (op-amp) ADCINA2 13 I ADC Group A, Channel 2 input ADCINA1 14 I ADC Group A, Channel 1 input (op-amp) ADCINA0 18 I ADC Group A, Channel 0 input VREFOUT Voltage Reference out from buffered DAC V ADC External Reference – used when in ADC external reference mode and used as VREFOUT REFHI 19 I reference ADCINB7 31 I ADC Group B, Channel 7 input (op-amp) ADCINB6 29 I ADC Group B, Channel 6 input (op-amp) ADCINB5 28 I ADC Group B, Channel 5 input ADCINB4 26 I ADC Group B, Channel 4 input (op-amp) ADCINB3 25 I ADC Group B, Channel 3 input ADCINB2 16 I ADC Group B, Channel 2 input ADCINB1 17 I ADC Group B, Channel 1 input (op-amp) ADCINB0 30 I ADC Group B, Channel 0 input VREFLO 22 I ADC Low Reference (always tied to ground) 44 Device Pins Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. CPU AND I/O POWER VDDA 20 Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin. VSSA 21 Analog Ground Pin VDD 6 CPU and Logic Digital Power Pins – no supply source needed when using internal VREG. Tie VDD 54 with 1.2 μF (minimum) ceramic capacitor (10% tolerance) to ground when using internal V VREG. Higher value capacitors may be used, but could impact supply-rail ramp-up time. DD 73 VDDIO 38 Digital I/O and Flash Power Pin – Single Supply source when VREG is enabled VDDIO 70 VSS 7 VSS 37 Digital Ground Pins VSS 53 VSS 72 M1GND 15 Ground pin for M1 channel M2GND 27 Ground pin for M2 channel PFCGND 32 Ground pin for PFC channel VOLTAGE REGULATOR CONTROL SIGNAL VREGENZ 71 I Internal VREG Enable/Disable – pull low to enable VREG, pull high to disable VREG GPIO AND PERIPHERAL SIGNALS (1) GPIO0 69 I/O/Z General-purpose input/output 0 EPWM1A O Enhanced PWM1 Output A GPIO1 68 I/O/Z General-purpose input/output 1 EPWM1B O Enhanced PWM1 Output B CTRIPM1OUT O CTRIPM1 CTRIPxx output (COMP1OUT) (Direct output of Comparator 1) GPIO2 67 I/O/Z General-purpose input/output 2 EPWM2A O Enhanced PWM2 Output A GPIO3 66 I/O/Z General-purpose input/output 3 EPWM2B O Enhanced PWM2 Output B SPISOMIA I/O SPI-A slave out, master in CTRIPM2OUT O CTRIPM2 CTRIPxx output (COMP2OUT) (Direct output of Comparator 2) GPIO4 63 I/O/Z General-purpose input/output 4 EPWM3A O Enhanced PWM3 output A GPIO5 62 I/O/Z General-purpose input/output 5 EPWM3B O Enhanced PWM3 output B SPISIMOA I/O SPI-A slave in, master out ECAP1 I/O Enhanced Capture input/output 1 (1) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the GPIO block and the path to the JTAG block from a pin is enabled or disabled based on the condition of the TRST signal. See the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5) for details. Copyright © 2012, Texas Instruments Incorporated Device Pins 45 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. GPIO6 50 I/O/Z General-purpose input/output 6 EPWM4A O Enhanced PWM4 output A EPWMSYNCI I External ePWM sync pulse input EPWMSYNCO O External ePWM sync pulse output GPIO7 49 I/O/Z General-purpose input/output 7 EPWM4B O Enhanced PWM4 output B SCIRXDA I SCI-A receive data GPIO8 45 I/O/Z General-purpose input/output 8 EPWM5A O Enhanced PWM5 output A ADCSOCAO O ADC start-of-conversion A GPIO9 36 I/O/Z General-purpose input/output 9 EPWM5B O Enhanced PWM5 output B SCITXDB O SCI-B transmit data GPIO10 65 I/O/Z General-purpose input/output 10 EPWM6A O Enhanced PWM6 output A ADCSOCBO O ADC start-of-conversion B GPIO11 61 I/O/Z General-purpose input/output 11 EPWM6B O Enhanced PWM6 output B SCIRXDB I SCI-B receive data GPIO12 48 I/O/Z General-purpose input/output 12 TZ1 I Trip Zone input 1 CTRIPM1OUT O CTRIPM1 CTRIPxx output SCITXDA O SCI-A transmit data GPIO13 76 I/O/Z General-purpose input/output 13 TZ2 I Trip zone input 2 CTRIPM2OUT O CTRIPM2 CTRIPxx output GPIO14 77 I/O/Z General-purpose input/output 14 TZ3 I Trip zone input 3 CTRIPPFCOUT O CTRIPPFC output SCITXDB O SCI-B transmit data GPIO15 75 I/O/Z General-purpose input/output 15 TZ1 I Trip zone input 1 CTRIPM1OUT O CTRIPM1 CTRIPxx output SCIRXDB I SCI-B receive data GPIO16 47 I/O/Z General-purpose input/output 16 SPISIMOA I/O SPI-A slave in, master out EQEP1S I/O Enhanced QEP1 strobe TZ2 I Trip Zone input 2 CTRIPM2OUT O CTRIPM2 CTRIPxx output GPIO17 44 I/O/Z General-purpose input/output 17 SPISOMIA I/O SPI-A slave out, master in EQEP1I I/O Enhanced QEP1 index TZ3 I Trip zone input 3 CTRIPPFCOUT O CTRIPPFC output 46 Device Pins Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. GPIO18 43 I/O/Z General-purpose input/output 18 SPICLKA I/O SPI-A clock input/output SCITXDB O SCI-B transmit data XCLKOUT O/Z Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. The value of XCLKOUT is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin. GPIO19 55 I/O/Z General-purpose input/output 19 XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken not to enable this path for clocking if this path is being used for the other periperhal functions SPISTEA I/O SPI-A slave transmit enable input/output SCIRXDB I SCI-B receive data ECAP1 I/O Enhanced Capture input/output 1 GPIO20 78 I/O/Z General-purpose input/output 20 EQEP1A I Enhanced QEP1 input A EPWM7A O Enhanced PWM7 output A CTRIPM1OUT O CTRIPM1 CTRIPxx output (COMP1OUT) (Direct output of Comparator 1) GPIO21 79 I/O/Z General-purpose input/output 21 EQEP1B I Enhanced QEP1 input B EPWM7B O Enhanced PWM7 output B CTRIPM2OUT O CTRIPM2 CTRIPxx output (COMP2OUT) (Direct output of Comparator 2) GPIO22 1 I/O/Z General-purpose input/output 22 EQEP1S I/O Enhanced QEP1 strobe SCITXDB O SCI-B transmit data GPIO23 80 I/O/Z General-purpose input/output 23 EQEP1I I/O Enhanced QEP1 index SCIRXDB I SCI-B receive data GPIO24 4 I/O/Z General-purpose input/output 24 ECAP1 I/O Enhanced Capture input/output 1 EPWM7A O Enhanced PWM7 output A GPIO25 46 I/O/Z General-purpose input/output 25 GPIO26 40 I/O/Z General-purpose input/output 26 SCIRXDC I SCI-C receive data GPIO27 33 I/O/Z General-purpose input/output 27 SCITXDC O SCI-C transmit data GPIO28 42 I/O/Z General-purpose input/output 28 SCIRXDA I SCI-A receive data SDAA I/OD I2C data open-drain bidirectional port TZ2 I Trip zone input 2 CTRIPM2OUT O CTRIPM2 CTRIPxx output Copyright © 2012, Texas Instruments Incorporated Device Pins 47 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. GPIO29 41 I/O/Z General-purpose input/output 29 SCITXDA O SCI-A transmit data SCLA I/OD I2C clock open-drain bidirectional port TZ3 I Trip zone input 3 CTRIPPFCOUT O CTRIPPFC output GPIO30 35 I/O/Z General-purpose input/output 30 CANRXA I CAN receive SCIRXDB I SCI-B receive data EPWM7A O Enhanced PWM7 output A GPIO31 34 I/O/Z General-purpose input/output 31 CANTXA O CAN transmit SCITXDB O SCI-B transmit data EPWM7B O Enhanced PWM7 output B GPIO32 2 I/O/Z General-purpose input/output 32 SDAA I/OD I2C data open-drain bidirectional port EPWMSYNCI I Enhanced PWM external sync pulse input EQEP1S I/O Enhanced QEP1 strobe GPIO33 3 I/O/Z General-Purpose Input/Output 33 SCLA I/OD I2C clock open-drain bidirectional port EPWMSYNCO O Enhanced PWM external synch pulse output EQEP1I I/O Enhanced QEP1 index GPIO34 74 I/O/Z General-Purpose Input/Output 34 CTRIPM2OUT O CTRIPM2 CTRIPxx output (COMP2OUT) (Direct output of Comparator 2) CTRIPPFCOUT O CTRIPPFC output (COMP3OUT) (Direct output of Comparator 3) GPIO35 59 I/O/Z General-Purpose Input/Output 35 TDI I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK GPIO36 60 I/O/Z General-Purpose Input/Output 36 TMS I JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. GPIO37 58 I/O/Z General-Purpose Input/Output 37 TDO O/Z JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive) GPIO38 57 I/O/Z General-Purpose Input/Output 38 TCK I JTAG test clock with internal pullup XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken to not enable this path for clocking if this path is being used for the other functions. 48 Device Pins Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL PN I/O/Z DESCRIPTION NAME PIN NO. GPIO39 56 I/O/Z General-Purpose Input/Output 39 SCIRXDC I SCI-C receive data CTRIPPFCOUT O CTRIPPFC output GPIO40 64 I/O/Z General-Purpose Input/Output 40 EPWM7A O Enhanced PWM7 output A GPIO42 5 I/O/Z General-Purpose Input/Output 42 EPWM7B O Enhanced PWM7 output B SCITXDC O SCI-C transmit data CTRIPM1OUT O CTRIPM1 CTRIPxx output (COMP1OUT) (Direct output of Comparator 1) Copyright © 2012, Texas Instruments Incorporated Device Pins 49 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 4 Device Operating Conditions 4.1 Absolute Maximum Ratings(1) (2) Supply voltage range, VDDIO (I/O and Flash) with respect to VSS –0.3 V to 4.6 V Supply voltage range, VDD with respect to VSS –0.3 V to 2.5 V Analog voltage range, VDDA with respect to VSSA –0.3 V to 4.6 V Input voltage range, VIN (3.3 V) –0.3 V to 4.6 V Output voltage range, VO –0.3 V to 4.6 V Input clamp current, IIK (VIN < 0 or VIN > VDDIO)(3) ±20 mA Output clamp current, IOK (VO < 0 or VO > VDDIO) ±20 mA Junction temperature range, TJ (4) –40°C to 150°C Storage temperature range, Tstg (4) –65°C to 150°C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 4.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to VSS, unless otherwise noted. (3) Continuous clamp current per pin is ± 2 mA. (4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963). 4.2 Recommended Operating Conditions MIN NOM MAX UNIT Device supply voltage, I/O, VDDIO (1) 2.97 3.3 3.63 V Device supply voltage CPU, VDD (When internal 1.71 1.8 1.995 VREG is disabled and 1.8 V is supplied externally) V Supply ground, VSS 0 V Analog supply voltage, VDDA (1) 2.97 3.3 3.63 V Analog ground, VSSA 0 V Device clock frequency (system clock) 2 60 MHz High-level input voltage, VIH (3.3 V) 2 VDDIO + 0.3 V Low-level input voltage, VIL (3.3 V) VSS – 0.3 0.8 V High-level output source current, VOH = VOH(MIN) , IOH All GPIO pins –4 mA Group 2(2) –8 mA Low-level output sink current, VOL = VOL(MAX), IOL All GPIO pins 4 mA Group 2(2) 8 mA Junction temperature, TJ T version –40 105 °C S version –40 125 (1) VDDIO and VDDA should be maintained within approximately 0.3 V of each other. (2) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO28, GPIO29, GPIO30, GPIO31, GPIO36, GPIO37 50 Device Operating Conditions Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 4.3 Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOH = IOH MAX 2.4 VOH High-level output voltage V IOH = 50 μA VDDIO – 0.2 VOL Low-level output voltage IOL = IOL MAX 0.4 V Pin with pullup All GPIO pins –80 –140 –205 enabled VDDIO = 3.3 V, VIN = 0 V I Input current XRS pin –230 –300 –375 IL (low level) μA Pin with pulldown VDDIO = 3.3 V, VIN = 0 V ±2 enabled Pin with pullup VDDIO = 3.3 V, VIN = VDDIO ±2 Input current enabled IIH (high level) μA Pin with pulldown VDDIO = 3.3 V, VIN = VDDIO 28 50 80 enabled I Output current, pullup or OZ pulldown disabled VO = VDDIO or 0 V ±2 μA CI Input capacitance 2 pF VDDIO BOR trip point Falling VDDIO 2.78 V VDDIO BOR hysteresis 35 mV Supervisor reset release delay Time after BOR/POR/OVR event is removed to XRS 400 800 μs time release VREG VDD output Internal VREG on 1.9 V (1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage (VDD) go out of range. Copyright © 2012, Texas Instruments Incorporated Device Operating Conditions 51 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 4.4 Current Consumption Table 4-1. TMS320F2805x Current Consumption at 60-MHz SYSCLKOUT VREG ENABLED VREG DISABLED MODE TEST CONDITIONS IDDIO (1) IDDA (2) IDD IDDIO (1) IDDA (2) TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX The following peripheral clocks are enabled: • ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6, ePWM7 • eCAP1 • eQEP1 • eCAN-A • CLA • SCI-A, SCI-B, SCI-C • SPI-A Operational • ADC 100 mA(6) 40 mA 90 mA(6) 17 mA 40 mA (Flash) • I2C-A • COMPA1, COMPA3, COMPB1, COMPA6, COMPB4, COMPB5, COMPB7 • CPU-TIMER0, CPU-TIMER1, CPU-TIMER2 All PWM pins are toggled at 60 kHz. All I/O pins are left unconnected.(4)(5) Code is running out of flash with 2 wait-states. XCLKOUT is turned off. Flash is powered down. IDLE XCLKOUT is turned off. 13 mA 15 μA 13 mA 300 μA 15 μA All peripheral clocks are turned off. Flash is powered down. STANDBY 4 mA 15 μA 4 mA 300 μA 15 μA Peripheral clocks are off. Flash is powered down. HALT Peripheral clocks are off. 30 μA 15 μA 15 μA 150 μA 15 μA Input clock is disabled.(7) (1) IDDIO current is dependent on the electrical loading on the I/O pins. (2) In order to realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register. (3) The TYP numbers are applicable over room temperature and nominal voltage. (4) The following is done in a loop: • Data is continuously transmitted out of SPI-A, SCI-A, SCI-B, SCI-C, eCAN-A, and I2C-A ports. • The hardware multiplier is exercised. • Watchdog is reset. • ADC is performing continuous conversion. • GPIO17 is toggled. (5) CLA is continuously performing polynomial calculations. (6) For F2805x devices that do not have CLA, subtract the IDD current number for CLA (see Table 4-2) from the IDD (VREG disabled)/IDDIO (VREG enabled) current numbers shown in Table 4-1 for operational mode. (7) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator. NOTE The peripheral-I/O multiplexing implemented in the device prevents all available peripherals from being used at the same time because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If the clocks to all the peripherals are turned on at the same time, the current drawn by the device will be more than the numbers specified in the current consumption tables. 52 Device Operating Conditions Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 4.4.1 Reducing Current Consumption The 2805x devices incorporate a method to reduce the device current consumption. Since each peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current consumption even further. Table 4-2 indicates the typical reduction in current consumption achieved by turning off the clocks. Table 4-2. Typical Current Consumption by Various Peripherals (at 60 MHz)(1) PERIPHERAL IDD CURRENT MODULE(2) REDUCTION (mA) ADC 2(3) I2C 3 ePWM 2 eCAP 2 eQEP 2 SCI 2 SPI 2 COMP/DAC 1 PGA 2 CPU-TIMER 1 Internal zero-pin oscillator 0.5 CAN 2.5 CLA 20 (1) All peripheral clocks (except CPU Timer clock) are disabled upon reset. Writing to or reading from peripheral registers is possible only after the peripheral clocks are turned on. (2) For peripherals with multiple instances, the current quoted is per module. For example, the 2 mA value quoted for ePWM is for one ePWM module. (3) This number represents the current drawn by the digital portion of the ADC module. Turning off the clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC (IDDA) as well. NOTE IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off. NOTE The baseline IDD current (current when the core is executing a dummy loop with no peripherals enabled) is 40 mA, typical. To arrive at the IDD current for a given application, the current-drawn by the peripherals (enabled by that application) must be added to the baseline IDD current. Following are other methods to reduce power consumption further: • The flash module may be powered down if code is run off SARAM. This method results in a current reduction of 18 mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail. • Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function. Copyright © 2012, Texas Instruments Incorporated Device Operating Conditions 53 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Operational Power vs Frequency 200 250 300 350 400 450 500 0 10 20 30 40 50 60 70 SYSCLKOUT (MHz) Operational Power (mW) Operational Current vs Frequency 0 20 40 60 80 100 120 140 0 10 20 30 40 50 60 70 SYSCLKOUT (MHz) Operational Current (mA) IDDIO IDDA TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 4.4.2 Current Consumption Graphs (VREG Enabled) Figure 4-1. Typical Operational Current Versus Frequency (F2805x) Figure 4-2. Typical Operational Power Versus Frequency (F2805x) 54 Device Operating Conditions Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Typical CLA operational current vs SYSCLKOUT 0 5 10 15 20 25 10 15 20 25 30 35 40 45 50 55 60 SYSCLKOUT (MHz) CLA operational IDDIO current (mA) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Figure 4-3. Typical CLA Operational Current Versus SYSCLKOUT Copyright © 2012, Texas Instruments Incorporated Device Operating Conditions 55 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 4.5 Flash Timing Table 4-3. Flash/OTP Endurance for T Temperature Material(1) ERASE/PROGRAM TEMPERATURE MIN TYP MAX UNIT Nf Flash endurance for the array (write/erase cycles) 0°C to 105°C (ambient) 20000 50000 cycles NOTP OTP endurance for the array (write cycles) 0°C to 30°C (ambient) 1 write (1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. Table 4-4. Flash/OTP Endurance for S Temperature Material(1) ERASE/PROGRAM MIN TYP MAX UNIT TEMPERATURE Nf Flash endurance for the array (write/erase cycles) 0°C to 125°C (ambient) 20000 50000 cycles NOTP OTP endurance for the array (write cycles) 0°C to 30°C (ambient) 1 write (1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. Table 4-5. Flash Parameters at 60-MHz SYSCLKOUT PARAMETER TEST MIN TYP MAX UNIT CONDITIONS Program Time 16-Bit Word 50 μs 8K Sector 250 ms 4K Sector 125 ms Erase Time(1) 8K Sector 2 s 4K Sector 2 s IDDP (2) VDD current consumption during Erase/Program cycle VREG disabled 80 mA IDDIOP (2) VDDIO current consumption during Erase/Program cycle 60 IDDIOP (2) VDDIO current consumption during Erase/Program cycle VREG enabled 120 mA (1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent programming operations. (2) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. Table 4-6. Flash/OTP Access Timing PARAMETER MIN MAX UNIT ta(fp) Paged Flash access time 40 ns ta(fr) Random Flash access time 40 ns ta(OTP) OTP access time 60 ns Table 4-7. Flash Data Retention Duration PARAMETER TEST CONDITIONS MIN MAX UNIT tretention Data retention duration TJ = 55°C 15 years 56 Device Operating Conditions Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION OTP Wait State 1 round up to the next highest integer, or 1, whichever is larger ú ú û ù ê ê ë é - ÷ ÷ ø ö ç ç è æ = t t c(SCO) a(OTP) FlashRandom Wait State 1 round up to the next highest integer, or 1, whichever is larger ú ú û ù ê ê ë é - ÷ ÷ ø ö ç ç è æ = × t t c(SCO) a(f r) FlashPage Wait State 1 round up to the next highest integer ( ) ( ) ú ú û ù ê ê ë é - ÷ ÷ ø ö ç ç è æ = · t t c SCO a f p TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 4-8. Minimum Required Flash/OTP Wait-States at Different Frequencies SYSCLKOUT SYSCLKOUT PAGE RANDOM OTP (MHz) (ns) WAIT-STATE(1) WAIT-STATE(1) WAIT-STATE 60 16.67 2 2 3 55 18.18 2 2 3 50 20 1 1 2 45 22.22 1 1 2 40 25 1 1 2 35 28.57 1 1 2 30 33.33 1 1 1 (1) Page and random wait-state must be ≥ 1. The equations to compute the Flash page wait-state and random wait-state in Table 4-8 are as follows: The equation to compute the OTP wait-state in Table 4-8 is as follows: Copyright © 2012, Texas Instruments Incorporated Device Operating Conditions 57 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION tw(RSL1) th(boot-mode) (C) V V (3.3 V) DDIO, DDA INTOSC1 X1/X2 XRS (D) Boot-Mode Pins V (1.8 V) DD XCLKOUT I/O Pins User-code dependent User-code dependent Boot-ROM execution starts Peripheral/GPIO function Based on boot code GPIO pins as input GPIO pins as input (state depends on internal PU/PD) (E) tOSCST User-code dependent Address/Data/ Control (Internal) Address/data valid, internal boot-ROM code execution phase td(EX) User-code execution phase tINTOSCST (A) (B) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 5 Power, Reset, Clocking, and Interrupts 5.1 Power Sequencing There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to prevent the I/Os from glitching during power up or power down (GPIO19, GPIO34–38 do not have glitch-free I/Os). No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for analog pins, this value is 0.7 V above VDDA) prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results. A. Upon power up, SYSCLKOUT is OSCCLK/4. Since the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0, SYSCLKOUT is further divided by 4 before SYSCLKOUT appears at XCLKOUT. XCLKOUT = OSCCLK/16 during this phase. B. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that XCLKOUT will not be visible at the pin until explicitly configured by user code. C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. D. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry. E. The internal pullup or pulldown will take effect when BOR is driven high. Figure 5-1. Power-on Reset 58 Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION th(boot-mode) (A) tw(RSL2) INTOSC1 X1/X2 XRS Boot-Mode Pins XCLKOUT I/O Pins Address/Data/ Control (Internal) Boot-ROM Execution Starts User-Code Execution Starts User-Code Dependent User-Code Execution Phase User-Code Dependent User-Code Execution Peripheral/GPIO Function User-Code Dependent GPIO Pins as Input (State Depends on Internal PU/PD) GPIO Pins as Input Peripheral/GPIO Function td(EX) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 5-1. Reset (XRS) Timing Requirements MIN MAX UNIT th(boot-mode) Hold time for boot-mode pins 1000tc(SCO) cycles tw(RSL2) Pulse duration, XRS low on warm reset 32tc(OSCCLK) cycles Table 5-2. Reset (XRS) Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT tw(RSL1) Pulse duration, XRS driven by device 600 μs tw(WDRS) Pulse duration, reset pulse generated by watchdog 512tc(OSCCLK) cycles td(EX) Delay time, address/data valid after XRS high 32tc(OSCCLK) cycles tINTOSCST Start up time, internal zero-pin oscillator 3 μs tOSCST (1) On-chip crystal-oscillator start-up time 1 10 ms (1) Dependent on crystal/resonator and board design. A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. Figure 5-2. Warm Reset Copyright © 2012, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 59 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION OSCCLK SYSCLKOUT Write to PLLCR OSCCLK * 2 (Current CPU Frequency) OSCCLK/2 (CPU frequency while PLL is stabilizing with the desired frequency. This period (PLL lock-up time t ) is 1 ms long.) p OSCCLK * 4 (Changed CPU frequency) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 5-3 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is complete, SYSCLKOUT reflects the new operating frequency, OSCCLK x 4. Figure 5-3. Example of Effect of Writing Into PLLCR Register 5.2 Clocking 5.2.1 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock options available on the 2805x MCUs. Table 5-3 lists the cycle times of various clocks. Table 5-3. 2805x Clock Table and Nomenclature (60-MHz Devices) MIN NOM MAX UNIT tc(SCO), Cycle time 16.67 500 ns SYSCLKOUT Frequency 2 60 MHz tc(LCO), Cycle time 16.67 66.67(2) ns LSPCLK(1) Frequency 15(2) 60 MHz tc(ADCCLK), Cycle time 16.67 ns ADC clock Frequency 60 MHz (1) Lower LSPCLK will reduce device power consumption. (2) This value is the default reset value if SYSCLKOUT = 60 MHz. Table 5-4. Device Clocking Requirements/Characteristics MIN NOM MAX UNIT On-chip oscillator (X1/X2 pins) tc(OSC), Cycle time 50 200 ns (Crystal/Resonator) Frequency 5 20 MHz External oscillator/clock source tc(CI), Cycle time (C8) 33.3 200 ns (XCLKIN pin) — PLL Enabled Frequency 5 30 MHz External oscillator/clock source tc(CI), Cycle time (C8) 33.33 250 ns (XCLKIN pin) — PLL Disabled Frequency 4 30 MHz Limp mode SYSCLKOUT Frequency range 1 to 5 MHz (with /2 enabled) tc(XCO), Cycle time (C1) 66.67 2000 ns XCLKOUT Frequency 0.5 15 MHz PLL lock time(1) tp 1 ms (1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum). 60 Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Zero-Pin Oscillator Frequency Movement With Temperature 9.6 9.7 9.8 9.9 10 10.1 10.2 10.3 10.4 10.5 10.6 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (°C) Output Frequency (MHz) Typical Max TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 5-5. Internal Zero-Pin Oscillator (INTOSC1, INTOSC2) Characteristics PARAMETER MIN TYP MAX UNIT Internal zero-pin oscillator 1 (INTOSC1) at 30°C(1) (2) Frequency 10.000 MHz Internal zero-pin oscillator 2 (INTOSC2) at 30°C(1) (2) Frequency 10.000 MHz Step size (coarse trim) 55 kHz Step size (fine trim) 14 kHz Temperature drift(3) 3.03 4.85 kHz/°C Voltage (VDD) drift(3) 175 Hz/mV (1) In order to achieve better oscillator accuracy (10 MHz ± 1% or better) than shown, see the Oscillator Compensation Guide Application Report (literature number SPRAB84). Refer to Figure 5-4 for TYP and MAX values. (2) Frequency range ensured only when VREG is enabled, VREGENZ = VSS. (3) Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (VDD) gradient. For example: • Increase in temperature will cause the output frequency to increase per the temperature coefficient. • Decrease in voltage (VDD) will cause the output frequency to decrease per the voltage coefficient. Figure 5-4. Zero-Pin Oscillator Frequency Movement With Temperature Copyright © 2012, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 61 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION C4 C3 XCLKOUT(B) XCLKIN(A) C5 C9 C10 C1 C8 C6 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 5.2.2 Clock Requirements and Characteristics Table 5-6. XCLKIN Timing Requirements - PLL Enabled NO. MIN MAX UNIT C9 tf(CI) Fall time, XCLKIN 6 ns C10 tr(CI) Rise time, XCLKIN 6 ns C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45 55 % C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45 55 % Table 5-7. XCLKIN Timing Requirements - PLL Disabled NO. MIN MAX UNIT C9 tf(CI) Fall time, XCLKIN Up to 20 MHz 6 ns 20 MHz to 30 MHz 2 C10 tr(CI) Rise time, XCLKIN Up to 20 MHz 6 ns 20 MHz to 30 MHz 2 C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45 55 % C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45 55 % The possible configuration modes are shown in Table 2-22. Table 5-8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1) (2) over recommended operating conditions (unless otherwise noted) NO. PARAMETER MIN MAX UNIT C3 tf(XCO) Fall time, XCLKOUT 5 ns C4 tr(XCO) Rise time, XCLKOUT 5 ns C5 tw(XCOL) Pulse duration, XCLKOUT low H – 2 H + 2 ns C6 tw(XCOH) Pulse duration, XCLKOUT high H – 2 H + 2 ns (1) A load of 40 pF is assumed for these parameters. (2) H = 0.5tc(XCO) A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate the timing parameters only and may differ based on actual configuration. B. XCLKOUT configured to reflect SYSCLKOUT. Figure 5-5. Clock Timing 62 Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION CPU TIMER 2 CPU TIMER 0 Watchdog Peripherals (SPI, SCI, ePWM, I2C, eCAP, ADC, eQEP, CLA, eCAN) TINT0 XINT1 Interrupt Control XINT1 XINT1CR(15:0) Interrupt Control XINT2 XINT2CR(15:0) GPIO MUX WDINT INT1 to INT12 NMI XINT2CTR(15:0) XINT3CTR(15:0) CPU TIMER 1 TINT2 Low Power Modes LPMINT WAKEINT Sync SYSCLKOUT MUX XINT2 XINT3 ADC XINT2SOC GPIOXINT1SEL(4:0) GPIOXINT2SEL(4:0) GPIOXINT3SEL(4:0) Interrupt Control XINT3 XINT3CR(15:0) XINT3CTR(15:0) NMI interrupt with watchdog function (See the NMI Watchdog section.) NMIRS System Control (See the System Control section.) INT14 INT13 GPIO0.int GPIO31.int CLOCKFAIL CPUTMR2CLK C28 Core MUX MUX TINT1 PIE Up to 96 Interrupts TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 5.3 Interrupts Figure 5-6 shows how the various interrupt sources are multiplexed. Figure 5-6. External and PIE Interrupt Sources Copyright © 2012, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 63 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION INT12 MUX INT11 INT2 INT1 CPU (Flag) (Enable) INTx INTx.8 PIEIERx[8:1] PIEIFRx[8:1] MUX INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 From Peripherals or External Interrupts (Enable) (Flag) IFR[12:1] IER[12:1] Global Enable INTM 1 0 PIEACKx (Enable/Flag) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. Table 5-9 shows the interrupts used by 2805x devices. The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior. When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth. Figure 5-7. Multiplexing of Interrupts Using the PIE Block 64 Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 5-9. PIE MUXed Peripheral Interrupt Vector Table(1) INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 INT1.y WAKEINT TINT0 ADCINT9 XINT2 XINT1 Reserved ADCINT2 ADCINT1 (LPM/WD) (TIMER 0) (ADC) Ext. int. 2 Ext. int. 1 – (ADC) (ADC) 0xD4E 0xD4C 0xD4A 0xD48 0xD46 0xD44 0xD42 0xD40 INT2.y Reserved EPWM7_TZINT EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT – (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1) 0xD5E 0xD5C 0xD5A 0xD58 0xD56 0xD54 0xD52 0xD50 INT3.y Reserved EPWM7_INT EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT – (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1) 0xD6E 0xD6C 0xD6A 0xD68 0xD66 0xD64 0xD62 0xD60 INT4.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved ECAP1_INT – – – – – – – (eCAP1) 0xD7E 0xD7C 0xD7A 0xD78 0xD76 0xD74 0xD72 0xD70 INT5.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved EQEP1_INT – – – – – – – (eQEP1) 0xD8E 0xD8C 0xD8A 0xD88 0xD86 0xD84 0xD82 0xD80 INT6.y Reserved Reserved Reserved Reserved Reserved Reserved SPITXINTA SPIRXINTA – – – – – – (SPI-A) (SPI-A) 0xD9E 0xD9C 0xD9A 0xD98 0xD96 0xD94 0xD92 0xD90 INT7.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved – – – – – – – – 0xDAE 0xDAC 0xDAA 0xDA8 0xDA6 0xDA4 0xDA2 0xDA0 INT8.y Reserved Reserved SCITXINTC SCIRXINTC Reserved Reserved I2CINT2A I2CINT1A – – (SCI-C) (SCI-C) – – (I2C-A) (I2C-A) 0xDBE 0xDBC 0xDBA 0xDB8 0xDB6 0xDB4 0xDB2 0xDB0 INT9.y Reserved Reserved ECAN1_INTA ECAN0_INTA SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA – – (CAN-A) (CAN-A) (SCI-B) (SCI-B) (SCI-A) (SCI-A) 0xDCE 0xDCC 0xDCA 0xDC8 0xDC6 0xDC4 0xDC2 0xDC0 INT10.y ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1 (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ePWM16) (ePWM15) (ePWM14) (ePWM13) (ePWM12) (ePWM11) (ePWM10) (ePWM9) 0xDDE 0xDDC 0xDDA 0xDD8 0xDD6 0xDD4 0xDD2 0xDD0 INT11.y CLA1_INT8 CLA1_INT7 CLA1_INT6 CLA1_INT5 CLA1_INT4 CLA1_INT3 CLA1_INT2 CLA1_INT1 (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (ePWM16) (ePWM15) (ePWM14) (ePWM13) (ePWM12) (ePWM11) (ePWM10) (ePWM9) 0xDEE 0xDEC 0xDEA 0xDE8 0xDE6 0xDE4 0xDE2 0xDE0 INT12.y LUF LVF Reserved Reserved Reserved Reserved Reserved XINT3 (CLA) (CLA) – – – – – Ext. Int. 3 0xDFE 0xDFC 0xDFA 0xDF8 0xDF6 0xDF4 0xDF2 0xDF0 (1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts: • No peripheral within the group is asserting interrupts. • No peripheral interrupts are assigned to the group (for example, PIE group 7). Copyright © 2012, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 65 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 5-10. PIE Configuration and Control Registers NAME ADDRESS SIZE (x16) DESCRIPTION(1) PIECTRL 0x0CE0 1 PIE, Control Register PIEACK 0x0CE1 1 PIE, Acknowledge Register PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register PIEIER10 0x0CF4 1 PIE, INT10 Group Enable Register PIEIFR10 0x0CF5 1 PIE, INT10 Group Flag Register PIEIER11 0x0CF6 1 PIE, INT11 Group Enable Register PIEIFR11 0x0CF7 1 PIE, INT11 Group Flag Register PIEIER12 0x0CF8 1 PIE, INT12 Group Enable Register PIEIFR12 0x0CF9 1 PIE, INT12 Group Flag Register Reserved 0x0CFA – 6 Reserved 0x0CFF (1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected. 66 Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION XINT1, XINT2, XINT3 tw(INT) Interrupt Vector td(INT) Address bus (internal) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 5.3.1 External Interrupts Table 5-11. External Interrupt Registers NAME ADDRESS SIZE (x16) DESCRIPTION XINT1CR 0x00 7070 1 XINT1 configuration register XINT2CR 0x00 7071 1 XINT2 configuration register XINT3CR 0x00 7072 1 XINT3 configuration register XINT1CTR 0x00 7078 1 XINT1 counter register XINT2CTR 0x00 7079 1 XINT2 counter register XINT3CTR 0x00 707A 1 XINT3 counter register Each external interrupt can be enabled, disabled, or qualified using positive, negative, or both positive and negative edge. For more information, see the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5). 5.3.1.1 External Interrupt Electrical Data/Timing Table 5-12. External Interrupt Timing Requirements(1) TEST CONDITIONS MIN MAX UNIT tw(INT) (2) Pulse duration, INT input low/high Synchronous 1tc(SCO) cycles With qualifier 1tc(SCO) + tw(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-45. (2) This timing is applicable to any GPIO pin configured for ADCSOC functionality. Table 5-13. External Interrupt Switching Characteristics(1) over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT td(INT) Delay time, INT low/high to interrupt-vector fetch tw(IQSW) + 12tc(SCO) cycles (1) For an explanation of the input qualifier parameters, see Table 6-45. Figure 5-8. External Interrupt Timing Copyright © 2012, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 67 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Transmission Line 4.0 pF 1.85 pF Z0 = 50 W (A) Tester Pin Electronics Data Sheet Timing Reference Point Output Under Test 42 W 3.5 nH Device Pin (B) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6 Peripheral Information and Timings 6.1 Parameter Information 6.1.1 Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their Letters and symbols and their meanings: meanings: a access time H High c cycle time (period) L Low d delay time V Valid f fall time X Unknown, changing, or don't care level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width) 6.1.1.1 General Notes on Timing Parameters All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document. 6.1.2 Test Load Circuit This test load circuit is used to measure all switching characteristics provided in this document. A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing. Figure 6-1. 3.3-V Test Load Circuit 68 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.2 Control Law Accelerator (CLA) 6.2.1 Control Law Accelerator Device-Specific Information The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Timecritical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasks frees up the main CPU to perform other system and communication functions concurently. The following is a list of major features of the CLA. • Clocked at the same rate as the main CPU (SYSCLKOUT). • An independent architecture allowing CLA algorithm execution independent of the main C28x CPU. – Complete bus architecture: • Program address bus and program data bus • Data address bus, data read bus, and data write bus – Independent eight-stage pipeline. – 12-bit program counter (MPC) – Four 32-bit result registers (MR0–MR3) – Two 16-bit auxillary registers (MAR0, MAR1) – Status register (MSTF) • Instruction set includes: – IEEE single-precision (32-bit) floating-point math operations – Floating-point math with parallel load or store – Floating-point multiply with parallel add or subtract – 1/X and 1/sqrt(X) estimations – Data type conversions. – Conditional branch and call – Data load and store operations • The CLA program code can consist of up to eight tasks or interrupt service routines. – The start address of each task is specified by the MVECT registers. – No limit on task size as long as the tasks fit within the CLA program memory space. – One task is serviced at a time through to completion. There is no nesting of tasks. – Upon task completion, a task-specific interrupt is flagged within the PIE. – When a task finishes, the next highest-priority pending task is automatically started. • Task trigger mechanisms: – C28x CPU via the IACK instruction – Task1 to Task7: the corresponding ADC, ePWM, eQEP, or eCAP module interrupt. For example: • Task1: ADCINT1 or EPWM1_INT • Task2: ADCINT2 or EPWM2_INT • Task4: ADCINT4 or EPWM4_INT or EQEPx_INT or ECAPx_INT • Task7: ADCINT7 or EPWM7_INT or EQEPx_INT or ECAPx_INT – Task8: ADCINT8 or by CPU Timer 0 or EQEPx_INT or ECAPx_INT • Memory and Shared Peripherals: – Two dedicated message RAMs for communication between the CLA and the main CPU. – The C28x CPU can map CLA program and data memory to the main CPU space or CLA space. – The CLA has direct access to the CLA Data ROM that stores the math tables required by the routines in the CLA Math Library. – The CLA has direct access to the ADC Result registers, comparator and DAC registers, eCAP, eQEP, and ePWM registers. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 69 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION CLA_INT1 to CLA_INT8 MVECT1 MIFR MIER MIFRC MVECT2 MIRUN MPERINT1 to MPERINT8 PIE Main 28x CPU CLA Program Memory MMEMCFG MIOVF MICLR MCTL MICLROVF MPISRCSEL1 MVECT3 MVECT4 MVECT5 MVECT6 MVECT7 MVECT8 PU BUS INT11 INT12 Peripheral Interrupts ADCINT1 to ADCINT8 EPWM1_INT to EPWM7_INT ECAP1_INT EQEP1_INT CPU Timer 0 Map to CLA or CPU Space Main CPU Read/Write Data Bus CLA Program Address Bus CLA Program Data Bus Map to CLA or CPU Space CLA Data Memory CLA Data ROM Comparator + DAC Registers ePWM Registers eCAP Registers eQEP Registers ADC Result Registers CLA Shared Message RAMs Main CPU Bus MR0(32) MPC(12) MR1(32) MR3(32) MAR0(32) MSTF(32) MR2(32) MAR1(32) CLA Data Read Address Bus CLA Data Write Data Bus CLA Data Write Address Bus CLA Data Read Data Bus MEALLOW Main CPU Read Data Bus CLA Execution Registers CLA Control Registers SYSCLKOUT CLAENCLK SYSRS LVF LUF IACK CLA Data Bus TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 6-2. CLA Block Diagram 70 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.2.2 Control Law Accelerator Register Descriptions Table 6-1. CLA Control Registers REGISTER NAME CLA1 SIZE (x16) EALLOW DESCRIPTION(1) ADDRESS PROTECTED MVECT1 0x1400 1 Yes CLA Interrupt/Task 1 Start Address MVECT2 0x1401 1 Yes CLA Interrupt/Task 2 Start Address MVECT3 0x1402 1 Yes CLA Interrupt/Task 3 Start Address MVECT4 0x1403 1 Yes CLA Interrupt/Task 4 Start Address MVECT5 0x1404 1 Yes CLA Interrupt/Task 5 Start Address MVECT6 0x1405 1 Yes CLA Interrupt/Task 6 Start Address MVECT7 0x1406 1 Yes CLA Interrupt/Task 7 Start Address MVECT8 0x1407 1 Yes CLA Interrupt/Task 8 Start Address MCTL 0x1410 1 Yes CLA Control Register MMEMCFG 0x1411 1 Yes CLA Memory Configure Register MPISRCSEL1 0x1414 2 Yes Peripheral Interrupt Source Select Register 1 MIFR 0x1420 1 Yes Interrupt Flag Register MIOVF 0x1421 1 Yes Interrupt Overflow Register MIFRC 0x1422 1 Yes Interrupt Force Register MICLR 0x1423 1 Yes Interrupt Clear Register MICLROVF 0x1424 1 Yes Interrupt Overflow Clear Register MIER 0x1425 1 Yes Interrupt Enable Register MIRUN 0x1426 1 Yes Interrupt RUN Register MPC(2) 0x1428 1 – CLA Program Counter MAR0(2) 0x142A 1 – CLA Aux Register 0 MAR1(2) 0x142B 1 – CLA Aux Register 1 MSTF(2) 0x142E 2 – CLA STF Register MR0(2) 0x1430 2 – CLA R0H Register MR1(2) 0x1434 2 – CLA R1H Register MR2(2) 0x1438 2 – CLA R2H Register MR3(2) 0x143C 2 – CLA R3H Register (1) All registers in this table are DCSM protected (2) The main C28x CPU has read only access to this register for debug purposes. The main CPU cannot perform CPU or debugger writes to this register. Table 6-2. CLA Message RAM ADDRESS RANGE SIZE (x16) DESCRIPTION 0x1480 – 0x14FF 128 CLA to CPU Message RAM 0x1500 – 0x157F 128 CPU to CLA Message RAM Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 71 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Digital Value = 0, when input £ 0 V V V Input Analog Voltage V Digital Value 4096 REFHI REFLO REFLO - - = ´ when 0 V input VREFHI < < Digital Value = 4095, when input VREFHI ³ Digital Value = 0, when input £ 0 V 3.3 Input Analog Voltage V Digital Value 4096 REFLO - = ´ when 0 V < input < 3.3 V Digital Value = 4095, when input ³ 3.3 V TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.3 Analog Block 6.3.1 Analog-to-Digital Converter (ADC) 6.3.1.1 Analog-to-Digital Converter Device-Specific Information The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sampleand- hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to 16 analog input channels. The converter can be configured to run with an internal bandgap reference to create true-voltage based conversions or with a pair of external voltage references (VREFHI/VREFLO) to create ratiometric-based conversions. Contrary to previous ADC types, this ADC is not sequencer-based. The user can easily create a series of conversions from a single trigger. However, the basic principle of operation is centered around the configurations of individual conversions, called SOCs, or Start-Of-Conversions. Functions of the ADC module include: • 12-bit ADC core with built-in dual sample-and-hold (S/H) • Simultaneous sampling or sequential sampling modes • Full range analog input: 0 V to 3.3 V fixed, or VREFHI/VREFLO ratiometric. The digital value of the input analog voltage is derived by: – Internal Reference (VREFLO = VSSA. VREFHI must not exceed VDDA when using either internal or external reference modes.) – External Reference (VREFHI/VREFLO connected to external references. VREFHI must not exceed VDDA when using either internal or external reference modes.) • Runs at full system clock, no prescaling required • Up to 16-channel, multiplexed inputs • 16 SOCs, configurable for trigger, sample window, and channel • 16 result registers (individually addressable) to store conversion values • Multiple trigger sources – S/W – software immediate start – ePWM 1–7 – GPIO XINT2 – CPU Timer 0, CPU Timer 1, CPU Timer 2 – ADCINT1, ADCINT2 • 9 flexible PIE interrupts, can configure interrupt request after any conversion 72 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 6-3. ADC Configuration and Control Registers REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED ADCCTL1 0x7100 1 Yes Control 1 Register ADCCTL2 0x7101 1 Yes Control 2 Register ADCINTFLG 0x7104 1 No Interrupt Flag Register ADCINTFLGCLR 0x7105 1 No Interrupt Flag Clear Register ADCINTOVF 0x7106 1 No Interrupt Overflow Register ADCINTOVFCLR 0x7107 1 No Interrupt Overflow Clear Register INTSEL1N2 0x7108 1 Yes Interrupt 1 and 2 Selection Register INTSEL3N4 0x7109 1 Yes Interrupt 3 and 4 Selection Register INTSEL5N6 0x710A 1 Yes Interrupt 5 and 6 Selection Register INTSEL7N8 0x710B 1 Yes Interrupt 7 and 8 Selection Register INTSEL9N10 0x710C 1 Yes Interrupt 9 Selection Register (reserved Interrupt 10 Selection) SOCPRICTL 0x7110 1 Yes SOC Priority Control Register ADCSAMPLEMODE 0x7112 1 Yes Sampling Mode Register ADCINTSOCSEL1 0x7114 1 Yes Interrupt SOC Selection 1 Register (for 8 channels) ADCINTSOCSEL2 0x7115 1 Yes Interrupt SOC Selection 2 Register (for 8 channels) ADCSOCFLG1 0x7118 1 No SOC Flag 1 Register (for 16 channels) ADCSOCFRC1 0x711A 1 No SOC Force 1 Register (for 16 channels) ADCSOCOVF1 0x711C 1 No SOC Overflow 1 Register (for 16 channels) ADCSOCOVFCLR1 0x711E 1 No SOC Overflow Clear 1 Register (for 16 channels) ADCSOC0CTL to 0x7120 – 1 Yes SOC0 Control Register to SOC15 Control Register ADCSOC15CTL 0x712F ADCREFTRIM 0x7140 1 Yes Reference Trim Register ADCOFFTRIM 0x7141 1 Yes Offset Trim Register COMPHYSTCTL 0x714C 1 Yes Comparator Hysteresis Control Register ADCREV 0x714F 1 No Revision Register Table 6-4. ADC Result Registers (Mapped to PF0) REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED ADCRESULT0 to 0xB00 – 1 No ADC Result 0 Register to ADC Result 15 Register ADCRESULT15 0xB0F Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 73 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION PF0 (CPU) PF2 (CPU) SYSCLKOUT ADCENCLK ADC Channels ADC Core 12-Bit 0-Wait Result Registers ADCINT 1 ADCINT 9 ADCTRIG 1 TINT 0 PIE CPUTIMER 0 ADCTRIG 2 TINT 1 CPUTIMER 1 ADCTRIG 3 TINT 2 CPUTIMER 2 ADCTRIG 4 XINT 2SOC XINT 2 ADCTRIG 5 SOCA 1 EPWM 1 ADCTRIG 6 SOCB 1 ADCTRIG 7 SOCA 2 EPWM 2 ADCTRIG 8 SOCB 2 ADCTRIG 9 SOCA 3 EPWM 3 ADCTRIG 10 SOCB 3 ADCTRIG 11 SOCA 4 EPWM 4 ADCTRIG 12 SOCB 4 ADCTRIG 13 SOCA 5 EPWM 5 ADCTRIG 14 SOCB 5 ADCTRIG 15 SOCA 6 EPWM 6 ADCTRIG 16 SOCB 6 ADCTRIG 17 SOCA 7 EPWM 7 ADCTRIG 18 SOCB 7 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 6-3. ADC Connections ADC Connections if the ADC is Not Used TI recommends that the connections for the analog power pins be kept, even if the ADC is not used. Following is a summary of how the ADC pins should be connected, if the ADC is not used in an application: • VDDA – Connect to VDDIO • VSSA – Connect to VSS • VREFLO – Connect to VSS • ADCINAn, ADCINBn, VREFHI – Connect to VSSA When the ADC module is used in an application, unused ADC input pins should be connected to analog ground (VSSA). When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings. 74 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.3.1.2 Analog-to-Digital Converter Electrical Data/Timing Table 6-5. ADC Electrical Characteristics PARAMETER MIN TYP MAX UNIT DC SPECIFICATIONS Resolution 12 Bits ADC clock 0.5 60 MHz Sample Window (see Table 6-6) 28055, 28054, 28053, 10 63 ADC 28052 Clocks 28051, 28050 24 63 ACCURACY INL (Integral nonlinearity)(1) –4 4 LSB DNL (Differential nonlinearity), no missing codes –1 1.5 LSB Offset error (2) Executing a single self- –20 0 20 LSB recalibration(3) Executing periodic self- –4 0 4 recalibration(4) Overall gain error with internal reference –60 60 LSB Overall gain error with external reference –40 40 LSB Channel-to-channel offset variation –4 4 LSB Channel-to-channel gain variation –4 4 LSB ADC temperature coefficient with internal reference –50 ppm/°C ADC temperature coefficient with external reference –20 ppm/°C VREFLO –100 μA VREFHI 100 μA ANALOG INPUT Analog input voltage with internal reference 0 3.3 V Analog input voltage with external reference VREFLO VREFHI V VREFLO input voltage VSSA 0.66 V VREFHI input voltage(5) 2.64 VDDA V with VREFLO = VSSA 1.98 VDDA Input capacitance 5 pF Input leakage current ±2 μA (1) INL will degrade when the ADC input voltage goes above VDDA. (2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external reference. (3) For more details, see the TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051, TMS320F28050 Piccolo MCU Silicon Errata (literature number SPRZ362). (4) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be performed as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset Calibration" section in the Analog-to-Digital Converter and Comparator chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5). (5) VREFHI must not exceed VDDA when using either internal or external reference modes. Table 6-6. ACQPS Values(1) OVERLAP MODE NONOVERLAP MODE Non-PGA {9, 10, 23, 36, 49, 62} {15, 16, 28, 29, 41, 42, 54, 55} PGA {23, 36, 49, 62} {15, 16, 28, 29, 41, 42, 54, 55} (1) ACQPS = 6 can be used for the first sample if it is thrown away. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 75 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION ADCSOCAO ADCSOCBO or tw(ADCSOCL) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 6-7. ADC Power Modes ADC OPERATING MODE CONDITIONS IDDA UNITS Mode A – Operating Mode ADC Clock Enabled 13 mA Bandgap On (ADCBGPWD = 1) Reference On (ADCREFPWD = 1) ADC Powered Up (ADCPWDN = 1) Mode B – Quick Wake Mode ADC Clock Enabled 4 mA Bandgap On (ADCBGPWD = 1) Reference On (ADCREFPWD = 1) ADC Powered Up (ADCPWDN = 0) Mode C – Comparator-Only Mode ADC Clock Enabled 1.5 mA Bandgap On (ADCBGPWD = 1) Reference On (ADCREFPWD = 0) ADC Powered Up (ADCPWDN = 0) Mode D – Off Mode ADC Clock Enabled 0.075 mA Bandgap On (ADCBGPWD = 0) Reference On (ADCREFPWD = 0) ADC Powered Up (ADCPWDN = 0) 6.3.1.2.1 External ADC Start-of-Conversion Electrical Data/Timing Table 6-8. External ADC Start-of-Conversion Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(HCO ) cycles Figure 6-4. ADCSOCAO or ADCSOCBO Timing 6.3.1.2.2 Internal Temperature Sensor Table 6-9. Temperature Sensor Coefficient(1) PARAMETER(2) MIN TYP MAX UNIT TSLOPE Degrees C of temperature movement per measured ADC LSB change 0.18(3) (4) °C/LSB of the temperature sensor TOFFSET ADC output at 0°C of the temperature sensor 1750 LSB (1) The accuracy of the temperature sensor for sensing absolute temperature (temperature in degrees) is not specified. The primary use of the temperature sensor should be to compensate the internal oscillator for temperature drift (this operation is assured as per Table 5-5). (2) The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be adjusted accordingly in external reference mode to the external reference voltage. (3) ADC temperature coeffieicient is accounted for in this specification (4) Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values relative to an initial value. 76 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION ac Rs ADCIN C 5 pF p C 1.6 pF h Switch Typical Values of the Input Circuit Components: Switch Resistance (R ): 3.4 k on W Sampling Capacitor (C ): 1.6 pF h Parasitic Capacitance (C ): 5 pF p Source Resistance (R ): 50 s W 28x DSP Source Signal 3.4 kW Ron ADCPWDN/ ADCBGPWD/ ADCREFPWD/ ADCENABLE Request for ADC Conversion td(PWD) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.3.1.2.3 ADC Power-Up Control Bit Timing Table 6-10. ADC Power-Up Delays PARAMETER(1) MIN MAX UNIT td(PWD) Delay time for the ADC to be stable after power up 1 ms (1) Timings maintain compatibility to the ADC module. The 2805x ADC supports driving all 3 bits at the same time td(PWD) ms before first conversion. Figure 6-5. ADC Conversion Timing Figure 6-6. ADC Input Impedance Model Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 77 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION SOC0 ADCCLK ADCRESULT 0 S/H Window Pulse to Core ADCCTL1.INTPULSEPOS ADCSOCFLG1.SOC0 ADCINTFLG.ADCINTx SOC1 SOC2 0 2 9 15 22 24 37 Result 0 Latched ADCSOCFLG1.SOC1 ADCSOCFLG1.SOC2 ADCRESULT 1 EOC0 Pulse EOC1 Pulse Conversion 0 13 ADC Clocks Minimum 7 ADCCLKs 6 ADCCLKs Conversion 1 13 ADC Clocks Minimum 7 ADCCLKs 2 ADCCLKs 1 ADCCLK Analog Input SOC1 Sample Window SOC0 Sample Window SOC2 Sample Window TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.3.1.2.4 ADC Sequential and Simultaneous Timings A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the converter. Figure 6-7. Timing Example for Sequential Mode / Late Interrupt Pulse 78 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Conversion 0 13 ADC Clocks Minimum 7 ADCCLKs SOC0 ADCCLK ADCRESULT 0 S/H Window Pulse to Core ADCCTL1.INTPULSEPOS ADCSOCFLG1.SOC0 ADCINTFLG.ADCINTx SOC1 SOC2 9 15 22 24 37 6 ADCCLKs 0 2 Result 0 Latched Conversion 1 13 ADC Clocks Minimum 7 ADCCLKs ADCSOCFLG1.SOC1 ADCSOCFLG1.SOC2 ADCRESULT 1 EOC0 Pulse EOC1 Pulse EOC2 Pulse 2 ADCCLKs Analog Input SOC1 Sample Window SOC0 Sample Window SOC2 Sample Window TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the converter. Figure 6-8. Timing Example for Sequential Mode / Early Interrupt Pulse Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 79 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Conversion 0 (A) 13 ADC Clocks Minimum 7 ADCCLKs SOC0 (A/B) ADCCLK ADCRESULT 0 S/H Window Pulse to Core ADCCTL1.INTPULSEPOS ADCSOCFLG1.SOC0 ADCINTFLG .ADCINTx SOC2 (A/B) 9 22 24 37 19 ADCCLKs 0 2 Result 0 (A) Latched Conversion 0 (B) 13 ADC Clocks Minimum 7 ADCCLKs ADCSOCFLG1.SOC1 ADCSOCFLG1.SOC2 ADCRESULT 1 Result 0 (B) Latched Conversion 1 (A) 13 ADC Clocks ADCRESULT 2 50 EOC0 Pulse EOC1 Pulse EOC2 Pulse 1 ADCCLK 2 ADCCLKs 2 ADCCLKs Analog Input B SOC0 Sample B Window SOC2 Sample B Window Analog Input A SOC0 Sample A Window SOC2 Sample A Window TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the converter. Figure 6-9. Timing Example for Simultaneous Mode / Late Interrupt Pulse 80 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION ADCCLK 0 2 9 SOC0 Sample B Window Analog Input B Analog Input A SOC0 Sample A Window 37 50 SOC2 Sample B Window SOC2 Sample A Window 22 24 ADCCTL1.INTPULSEPOS ADCSOCFLG1.SOC0 ADCSOCFLG1.SOC1 ADCSOCFLG1.SOC2 S/H Window Pulse to Core SOC0 (A/B) SOC2 (A/B) ADCRESULT 0 2 ADCCLKs Result 0 (A) Latched ADCRESULT 1 Result 0 (B) Latched ADCRESULT 2 EOC0 Pulse EOC1 Pulse EOC2 Pulse Minimum 7 ADCCLKs Conversion 0 (A) 13 ADC Clocks 2 ADCCLKs Minimum 7 ADCCLKs Conversion 1 (A) 13 ADC Clocks Conversion 0 (B) 13 ADC Clocks ADCINTFLG.ADCINTx 19 ADCCLKs TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the converter. Figure 6-10. Timing Example for Simultaneous Mode / Early Interrupt Pulse Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 81 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION 6.02 (SINAD 1.76) N - = TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.3.1.2.5 Detailed Descriptions Integral Nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as level one-half LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two points. Differential Nonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes. Zero Offset Zero error is the difference between the ideal input voltage and the actual input voltage that just causes a transition from an output code of zero to an output code of one. Gain Error The first code transition should occur at an analog value one-half LSB above negative full scale. The last transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Signal-to-Noise Ratio + Distortion (SINAD) SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. Spurious Free Dynamic Range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. 82 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.3.2 Analog Front End (AFE) 6.3.2.1 Analog Front End Device-Specific Information The Analog Front End (AFE) contains up to seven comparators with up to three integrated Digital-to- Analog Converters (DACs), one VREFOUT-buffered DAC, up to four Programmable Gain Amplifiers (PGAs), and up to four digital filters. Figure 6-11 and Figure 6-12 show the AFE. The comparator output signal filtering is achieved using the Digital Filter present on selective input line and qualifies the output of the COMP/DAC subsystem (see Figure 6-13). The filtered or unfiltered output of the COMP/DAC subsystem can be configured to be an input to the Digital Compare submodule of the ePWM peripheral. Note: The Analog inputs are brought in through the AFE subsystem rather than through an AIO Mux, which is not present. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 83 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION ADC VREFHI V /A0 REFOUT B7 PGA G~ = 3, 6, 11 _ + Cmp1 _ + Cmp1 V Buffered DAC Output COMPB7 REFOUT DFSS DAC5 6-bit DAC6 6-bit B7 VREFHI A0 PFCGND B0 A2 A4 B2 A1 PGA G~ = 3, 6, 11 M1GND _ + Cmp2 DAC1 6-bit COMPA1H DFSS _ + Cmp3 COMPA1L DFSS ADCINSWITCH A1 A3 PGA G~ = 3, 6, 11 M1GND Cmp4 COMPA3H DFSS _ + Cmp5 COMPA3L DFSS A3 B1 PGA G~ = 3, 6, 11 M1GND _ + Cmp6 COMPB1H DFSS _ + Cmp7 COMPB1L DFSS B1 DAC2 6-bit Temp Sensor ADCCTL1.TEMPCONV A5 A5 ADCCTL1.REFLOCONV B5 A7 B3 B5 VREFLO B0 A2 A4 B2 _ + ADCINSWITCH VREFLO A7 B3 A6 GAIN AMP G~ = 3 M2GND B4 GAIN AMP G~ = 3 M2GND B6 GAIN AMP G~ = 3 M2GND A6 B4 B6 Legend Cmp - Comparator DFSS - Comparator Trip/Digital Filter Subsystem Block GAIN AMP - Fixed Gain Amplifier PGA - Programmable Gain Amplifier TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 6-11. 28055, 28054, 28053, 28052, and 28051 Analog Front End (AFE) 84 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION ADC VREFHI V /A0 REFOUT _ + Cmp1 V Buffered DAC Output REFOUT DAC6 6-bit VREFHI A0 B0 A2 A4 B2 A1 PGA G~ = 3, 6, 11 M1GND _ + Cmp2 DAC1 6-bit COMPA1H DFSS _ + Cmp3 COMPA1L DFSS ADCINSWITCH A1 A3 PGA G~ = 3, 6, 11 M1GND Cmp4 COMPA3H DFSS _ + Cmp5 COMPA3L DFSS A3 B1 PGA G~ = 3, 6, 11 M1GND _ + Cmp6 COMPB1H DFSS _ + Cmp7 COMPB1L DFSS B1 DAC2 6-bit Temp Sensor ADCCTL1.TEMPCONV A5 A5 ADCCTL1.REFLOCONV B5 A7 B3 B5 VREFLO B0 A2 A4 B2 _ + ADCINSWITCH VREFLO A7 B3 A6 GAIN AMP G~ = 3 M2GND B4 GAIN AMP G~ = 3 M2GND A6 B4 B6 GAIN AMP G~ = 3 M2GND B6 B7 GAIN AMP G~ = 3 PFCGND B7 Legend Cmp - Comparator DFSS - Comparator Trip/Digital Filter Subsystem Block GAIN AMP - Fixed Gain Amplifier PGA - Programmable Gain Amplifier TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Figure 6-12. 28050 Analog Front End (AFE) Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 85 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION ePWM 1-7 DCAH DCAL DCBH DCBL D C T R I P S E L GPIO MUX CTRIPOUTPOL SYSCLK Digital Filter CTRIPOUTBYP 1 0 CTRIPxxOUTEN CTRIPOUTxxSTS CTRIPOUTxxFLG CTRIPOUTLATEN 0 1 CTRIPFILCTRL REGISTER CTRIPBYP 0 1 COMPxxPOL COMPxxH 0 1 COMPxxPOL COMPxxL COMPxINPEN ENABLES CTRIPEN (to all ePWM modules) CTRIPxx0CTLREGISTER 0 1 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 6-13. Comparator Trip/Digital Filter Subsystem 86 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.3.2.2 Analog Front End Register Descriptions Table 6-11. DAC Control Registers REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED DAC1CTL 0x6400 1 Yes DAC1 Control Register DAC2CTL 0x6401 1 Yes DAC2 Control Register DAC3CTL 0x6402 1 Yes DAC3 Control Register DAC4CTL 0x6403 1 Yes DAC4 Control Register DAC5CTL 0x6404 1 Yes DAC5 Control Register VREFOUTCTL 0x6405 1 Yes VREFOUT DAC Control Register Table 6-12. DAC, PGA, Comparator, and Filter Enable Registers REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED DACEN 0x6410 1 Yes DAC Enables Register VREFOUTEN 0x6411 1 Yes VREFOUT Enable Register PGAEN 0x6412 1 Yes Programmable Gain Amplifier Enable Register COMPEN 0x6413 1 Yes Comparator Enable Register AMPM1_GAIN 0x6414 1 Yes Motor Unit 1 PGA Gain Controls Register AMPM2_GAIN 0x6415 1 Yes Motor Unit 2 PGA Gain Controls Register AMP_PFC_GAIN 0x6416 1 Yes PFC PGA Gain Controls Register Table 6-13. SWITCH Registers REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED ADCINSWITCH 0x6421 1 Yes ADC Input-Select Switch Control Register Reserved 0x6422 – 7 Yes Reserved 0x6428 COMPHYSTCTL 0x6429 1 Yes Comparator Hysteresis Control Register Table 6-14. Digital Filter and Comparator Control Registers REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED CTRIPA1ICTL 0x6430 1 Yes CTRIPA1 Filter Input and Function Control Register CTRIPA1FILCTL 0x6431 1 Yes CTRIPA1 Filter Parameters Register CTRIPA1FILCLKCTL 0x6432 1 Yes CTRIPA1 Filter Sample Clock Control Register Reserved 0x6433 1 Yes Reserved CTRIPA3ICTL 0x6434 1 Yes CTRIPA3 Filter Input and Function Control Register CTRIPA3FILCTL 0x6435 1 Yes CTRIPA3 Filter Parameters Register CTRIPA3FILCLKCTL 0x6436 1 Yes CTRIPA3 Filter Sample Clock Control Register Reserved 0x6437 1 Yes Reserved CTRIPB1ICTL 0x6438 1 Yes CTRIPB1 Filter Input and Function Control Register CTRIPB1FILCTL 0x6439 1 Yes CTRIPB1 Filter Parameters Register CTRIPB1FILCLKCTL 0x643A 1 Yes CTRIPB1 Filter Sample Clock Control Register Reserved 0x643B 1 Yes Reserved Reserved 0x643C 1 Yes Reserved CTRIPM1OCTL 0x643D 1 Yes CTRIPM1 CTRIP Filter Output Control Register CTRIPM1STS 0x643E 1 Yes CTRIPM1 CTRIPxx Outputs Status Register CTRIPM1FLGCLR 0x643F 1 Yes CTRIPM1 CTRIPxx Flag Clear Register Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 87 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 6-14. Digital Filter and Comparator Control Registers (continued) REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED Reserved 0x6440 – 16 Yes Reserved 0x644F CTRIPA6ICTL 0x6450 1 Yes CTRIPA6 Filter Input and Function Control Register CTRIPA6FILCTL 0x6451 1 Yes CTRIPA6 Filter Parameters Register CTRIPA6FILCLKCTL 0x6452 1 Yes CTRIPA6 Filter Sample Clock Control Register Reserved 0x6453 1 Yes Reserved CTRIPB4ICTL 0x6454 1 Yes CTRIPB4 Filter Input and Function Control Register CTRIPB4FILCTL 0x6455 1 Yes CTRIPB4 Filter Parameters Register CTRIPB4FILCLKCTL 0x6456 1 Yes CTRIPB4 Filter Sample Clock Control Register Reserved 0x6457 1 Yes Reserved CTRIPB6ICTL 0x6458 1 Yes CTRIPB6 Filter Input and Function Control Register CTRIPB6FILCTL 0x6459 1 Yes CTRIPB6 Filter Parameters Register CTRIPB6FILCLKCTL 0x645A 1 Yes CTRIPB6 Filter Sample Clock Control Register Reserved 0x645B 1 Yes Reserved Reserved 0x645C 1 Yes Reserved CTRIPM2OCTL 0x645D 1 Yes CTRIPM2 CTRIP Filter Output Control Register CTRIPM2STS 0x645E 1 Yes CTRIPM2 CTRIPxx Outputs Status Register CTRIPM2FLGCLR 0x645F 1 Yes CTRIPM2 CTRIPxx Flag Clear Register Reserved 0x6460 – 16 Yes Reserved 0x646F CTRIPB7ICTL 0x6470 1 Yes CTRIPB7 Filter Input and Function Control Register CTRIPB7FILCTL 0x6471 1 Yes CTRIPB7 Filter Parameters Register CTRIPB7FILCLKCTL 0x6472 1 Yes CTRIPB7 Filter Sample Clock Control Register Reserved 0x6473 – 9 Yes Reserved 0x647B Reserved 0x647C 1 Yes Reserved CTRIPPFCOCTL 0x647D 1 Yes CTRIPPFC CTRIPxx Outputs Status Register CTRIPPFCSTS 0x647E 1 Yes CTRIPPFC CTRIPxx Flag Clear Register CTRIPPFCFLGCLR 0x647F 1 Yes CTRIPPFC COMP Test Control Register Table 6-15. LOCK Registers REGISTER NAME ADDRESS SIZE EALLOW DESCRIPTION (x16) PROTECTED LOCKCTRIP 0x64F0 1 Yes Lock Register for CTRIP Filters Register Reserved 0x64F1 1 Yes Reserved LOCKDAC 0x64F2 1 Yes Lock Register for DACs Register Reserved 0x64F3 1 Yes Reserved LOCKAMPCOMP 0x64F4 1 Yes Lock Register for Amplifiers and Comparators Register Reserved 0x64F5 1 Yes Reserved LOCKSWITCH 0x64F6 1 Yes Lock Register for Switches Register 88 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.3.2.3 Programmable Gain Amplifier Electrical Data/Timing Table 6-16. Op-Amp Linear Output and ADC Sampling Time Across Gain Settings MINIMUM INTERNAL RESISTOR RATIO EQUIVALENT GAIN FROM LINEAR OUTPUT RANGE ADC SAMPLING TIME INPUT TO OUTPUT OF OP-AMP TO ACHIEVE SETTLING ACCURACY 10 11 0.6 V to VDDA – 0.6 V 384 ns (ACQPS = 23) 5 6 0.6 V to VDDA – 0.6 V 384 ns (ACQPS = 23) 2 3 0.6 V to VDDA – 0.6 V 384 ns (ACQPS = 23) Table 6-17. PGA Gain Stage: DC Accuracy Across Gain Settings COMPENSATED COMPENSATED INPUT INTERNAL RESISTOR RATIO EQUIVALENT GAIN FROM GAIN-ERROR DRIFT ACROSS OFFSET-ERROR ACROSS INPUT TO OUTPUT TEMPERATURE AND SUPPLY TEMPERATURE AND SUPPLY VARIATIONS VARIATIONS IN mV 10 11 < ±2.5% < ±8 mV 5 6 < ±1.5% < ±8 mV 2 3 < ±1.0% < ±8 mV 6.3.2.4 Comparator Block Electrical Data/Timing Table 6-18. Electrical Characteristics of the Comparator/DAC PARAMETER MIN TYP MAX UNITS Comparator Comparator Input Range VSSA – VDDA V Comparator response time to PWM Trip Zone (Async) 65 ns Comparator large step response time to PWM Trip Zone (Async) 95 ns Input Offset TBD mV Input Hysteresis(1) TBD mV DAC DAC Output Range VDDA / 26 – VDDA V DAC resolution 6 bits DAC Gain –1.5 % DAC Offset 10 mV Monotonic Yes INL 0.2 LSB (1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration, which results in an effective 100-kΩ feedback resistance between the output of the comparator and the non-inverting input of the comparator. There is an option to disable the hysteresis and, with it, the feedback resistance; see the Analog-to-Digital Converter and Comparator chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5) for more information on this option if needed in your system. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 89 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.3.2.5 VREFOUT Buffered DAC Electrical Data Table 6-19. Electrical Characteristics of VREFOUT Buffered DAC PARAMETER MIN TYP MAX UNITS VREFOUT Programmable Range 6 56 LSB VREFOUT resolution 6 bits VREFOUT Gain –1.5 % VREFOUT Offset 10 mV Monotonic Yes INL ±0.2 LSB Load 3 kΩ 100 pF 90 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION (SPIBRR 1) LSPCLK Baud rate + = when SPIBRR = 3 to127 4 LSPCLK Baud rate = when SPIBRR = 0,1, 2 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.4 Serial Peripheral Interface (SPI) 6.4.1 Serial Peripheral Interface Device-Specific Information The device includes the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The SPI module features include: • Four external pins: – SPISOMI: SPI slave-output/master-input pin – SPISIMO: SPI slave-input/master-output pin – SPISTE: SPI slave transmit-enable pin – SPICLK: SPI serial-clock pin NOTE: All four pins can be used as GPIO if the SPI module is not used. • Two operational modes: master and slave Baud rate: 125 different programmable rates. • Data word length: one to sixteen data bits • Four clocking schemes (controlled by clock polarity and clock phase bits) include: – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. – Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. • Simultaneous receive and transmit operation (transmit function can be disabled in software) • Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. • Nine SPI module control registers: Located in control register frame beginning at address 7040h. NOTE All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect. Enhanced feature: • 4-level transmit/receive FIFO • Delayed transmit control • Bi-directional 3-wire SPI mode support • Audio data receive support via SPISTE inversion Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 91 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION S SPICTL.0 SPI INT FLAG SPI INT ENA SPISTS.6 S Clock Polarity Talk LSPCLK SPI Bit Rate State Control Clock Phase Receiver Overrun Flag SPICTL.4 Overrun INT ENA SPICCR.3 - 0 SPIBRR.6 - 0 SPICCR.6 SPICTL.3 SPIDAT.15 - 0 SPICTL.1 M S M Master/Slave SPISTS.7 SPIDAT Data Register M S SPI Char SPICTL.2 SPISIMO SPISOMI SPICLK SW2 S M M S SW3 To CPU M SW1 RX FIFO _0 RX FIFO _1 ----- RX FIFO _3 TX FIFO Registers TX FIFO _0 TX FIFO _1 ----- TX FIFO _3 RX FIFO Registers 16 16 16 TX Interrupt Logic RX Interrupt Logic SPIINT SPITX SPIFFOVF FLAG SPIFFRX.15 TX FIFO Interrupt RX FIFO Interrupt SPIRXBUF SPITXBUF SPIFFTX.14 SPIFFENA SPISTE 16 3 2 1 0 6 5 4 3 2 1 0 TW TW TW SPIPRI.0 TRIWIRE SPIPRI.1 STEINV STEINV SPIRXBUF Buffer Register SPITXBUF Buffer Register TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 6-14 is a block diagram of the SPI in slave mode. A. SPISTE is driven low by the master for a slave device. Figure 6-14. SPI Module Block Diagram (Slave Mode) 92 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.4.2 Serial Peripheral Interface Register Descriptions The SPI port operation is configured and controlled by the registers listed in Table 6-20. Table 6-20. SPI-A Registers NAME ADDRESS SIZE (x16) EALLOW PROTECTED DESCRIPTION(1) SPICCR 0x7040 1 No SPI-A Configuration Control Register SPICTL 0x7041 1 No SPI-A Operation Control Register SPISTS 0x7042 1 No SPI-A Status Register SPIBRR 0x7044 1 No SPI-A Baud Rate Register SPIRXEMU 0x7046 1 No SPI-A Receive Emulation Buffer Register SPIRXBUF 0x7047 1 No SPI-A Serial Input Buffer Register SPITXBUF 0x7048 1 No SPI-A Serial Output Buffer Register SPIDAT 0x7049 1 No SPI-A Serial Data Register SPIFFTX 0x704A 1 No SPI-A FIFO Transmit Register SPIFFRX 0x704B 1 No SPI-A FIFO Receive Register SPIFFCT 0x704C 1 No SPI-A FIFO Control Register SPIPRI 0x704F 1 No SPI-A Priority Control Register (1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. 6.4.3 Serial Peripheral Interface Master Mode Electrical Data/Timing Table 6-21 lists the master mode timing (clock phase = 0) and Table 6-22 lists the timing (clock phase = 1). Figure 6-15 and Figure 6-16 show the timing waveforms. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 93 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 6-21. SPI Master Mode External Timing (Clock Phase = 0)(1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN OR SPI WHEN (SPIBRR + 1) IS ODD NO. SPIBRR = 0 OR 2 AND SPIBRR > 3 UNIT MIN MAX MIN MAX 1 tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns 2 tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) ns (clock polarity = 0) tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) (clock polarity = 1) 3 tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) ns (clock polarity = 0) tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) (clock polarity = 1) 4 td(SPCH-SIMO)M Delay time, SPICLK high to SPISIMO 10 10 ns valid (clock polarity = 0) td(SPCL-SIMO)M Delay time, SPICLK low to SPISIMO 10 10 valid (clock polarity = 1) 5 tv(SPCL-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 ns SPICLK low (clock polarity = 0) tv(SPCH-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 SPICLK high (clock polarity = 1) 8 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK 26 26 ns low (clock polarity = 0) tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK 26 26 high (clock polarity = 1) 9 tv(SPCL-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 ns SPICLK low (clock polarity = 0) tv(SPCH-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 SPICLK high (clock polarity = 1) (1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1) (3) tc(LCO) = LSPCLK cycle time (4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. (5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6). 94 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION 9 4 SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be Valid Master Out Data Is Valid SPISTE (A) 1 2 3 5 8 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 6-15. SPI Master Mode External Timing (Clock Phase = 0) Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 95 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 6-22. SPI Master Mode External Timing (Clock Phase = 1)(1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN SPI WHEN (SPIBRR + 1) IS ODD NO. OR SPIBRR = 0 OR 2 AND SPIBRR > 3 UNIT MIN MAX MIN MAX 1 tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns 2 tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) ns (clock polarity = 0) tw(SPCL))M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO (clock polarity = 1) 3 tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) ns (clock polarity = 0) tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) (clock polarity = 1) 6 tsu(SIMO-SPCH)M Setup time, SPISIMO data valid 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 ns before SPICLK high (clock polarity = 0) tsu(SIMO-SPCL)M Setup time, SPISIMO data valid 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 before SPICLK low (clock polarity = 1) 7 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 ns SPICLK high (clock polarity = 0) tv(SPCL-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 SPICLK low (clock polarity = 1) 10 tsu(SOMI-SPCH)M Setup time, SPISOMI before 26 26 ns SPICLK high (clock polarity = 0) tsu(SOMI-SPCL)M Setup time, SPISOMI before 26 26 SPICLK low (clock polarity = 1) 11 tv(SPCH-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10 ns SPICLK high (clock polarity = 0) tv(SPCL-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10 SPICLK low (clock polarity = 1) (1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) (3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. (4) tc(LCO) = LSPCLK cycle time (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). 96 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Data Valid 11 SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master in data must be valid Master out data Is valid 1 7 6 10 3 2 SPISTE(A) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 6-16. SPI Master Mode External Timing (Clock Phase = 1) Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 97 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION 20 15 SPISIMO SPISOMI SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO data must be valid SPISOMI data Is valid 19 16 14 13 12 SPISTE(A) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.4.4 Serial Peripheral Interface Slave Mode Electrical Data/Timing Table 6-23 lists the slave mode external timing (clock phase = 0) and Table 6-24 (clock phase = 1). Figure 6-17 and Figure 6-18 show the timing waveforms. Table 6-23. SPI Slave Mode External Timing (Clock Phase = 0)(1) (2) (3) (4) (5) NO. MIN MAX UNIT 12 tc(SPC)S Cycle time, SPICLK 4tc(LCO) ns 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S 14 tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S 15 td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) 21 ns td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 21 16 tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0.75tc(SPC)S ns tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0.75tc(SPC)S 19 tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 26 ns tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 26 20 tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 ns tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 (1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) (3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. (4) tc(LCO) = LSPCLK cycle time (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6-17. SPI Slave Mode External Timing (Clock Phase = 0) 98 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Data Valid 22 SPISIMO SPISOMI SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO data must be valid SPISOMI data is valid 21 12 18 17 14 13 SPISTE(A) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 6-24. SPI Slave Mode External Timing (Clock Phase = 1)(1) (2) (3) (4) NO. MIN MAX UNIT 12 tc(SPC)S Cycle time, SPICLK 8tc(LCO) ns 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC) S 14 tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC) S ns tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S 17 tsu(SOMI-SPCH)S Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125tc(SPC)S ns tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125tc(SPC)S 18 tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low 0.75tc(SPC)S ns (clock polarity = 1) tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high 0.75tc(SPC) S (clock polarity = 0) 21 tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 26 ns tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 26 22 tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high 0.5tc(SPC)S – 10 ns (clock polarity = 0) tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low 0.5tc(SPC)S – 10 (clock polarity = 1) (1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) (3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. (4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6-18. SPI Slave Mode External Timing (Clock Phase = 1) Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 99 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION (BRR 1) * 8 LSPCLK Baud rate + = when BRR ¹ 0 16 LSPCLK Baud rate = when BRR = 0 TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.5 Serial Communications Interface (SCI) 6.5.1 Serial Communications Interface Device-Specific Information The 2805x devices include three serial communications interface (SCI) modules (SCI-A, SCI-B, SCI-C). Each SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are doublebuffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register. Features of each SCI module include: • Two external pins: – SCITXD: SCI transmit-output pin – SCIRXD: SCI receive-input pin NOTE: Both pins can be used as GPIO if not used for SCI. – Baud rate programmable to 64K different rates: • Data-word format – One start bit – Data-word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits • Four error-detection flags: parity, overrun, framing, and break detection • Two wake-up multiprocessor modes: idle-line and address bit • Half- or full-duplex operation • Double-buffered receive and transmit functions • Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. – Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty) – Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions) • Separate enable bits for transmitter and receiver interrupts (except BRKDT) • NRZ (non-return-to-zero) format NOTE All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect. Enhanced features: • Auto baud-detect hardware logic • 4-level transmit/receive FIFO 100 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TX FIFO _0 LSPCLK WUT Frame Format and Mode Even/Odd Enable Parity SCI RX Interrupt select logic BRKDT RXRDY SCIRXST.6 SCICTL1.3 8 SCICTL2.1 RX/BK INT ENA SCIRXD SCIRXST.1 TXENA SCI TX Interrupt select logic TX EMPTY TXRDY SCICTL2.0 TX INT ENA SCITXD RXENA SCIRXD RXWAKE SCICTL1.6 RX ERR INT ENA TXWAKE SCITXD SCICCR.6 SCICCR.5 SCITXBUF.7-0 SCIHBAUD. 15 - 8 Baud Rate MSbyte Register SCILBAUD. 7 - 0 Transmitter-Data Buffer Register 8 SCICTL2.6 SCICTL2.7 Baud Rate LSbyte Register RXSHF Register TXSHF Register SCIRXST.5 1 TX FIFO _1 ----- TX FIFO _3 8 TX FIFO registers TX FIFO TX Interrupt Logic TXINT SCIFFTX.14 RX FIFO _3 SCIRXBUF.7-0 Receive Data Buffer register SCIRXBUF.7-0 ----- RX FIFO_1 RX FIFO _0 8 RX FIFO registers SCICTL1.0 RX Interrupt Logic RXINT RX FIFO SCIFFRX.15 RXFFOVF RX Error SCIRXST.7 RX Error FE OE PE SCIRXST.4 - 2 To CPU To CPU AutoBaud Detect logic SCICTL1.1 SCIFFENA Interrupts Interrupts TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Figure 6-19 shows the SCI module block diagram. Figure 6-19. Serial Communications Interface (SCI) Module Block Diagram Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 101 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.5.2 Serial Communications Interface Register Descriptions The SCI port operation is configured and controlled by the registers listed in Table 6-25. Table 6-25. SCI-A Registers(1) NAME ADDRESS SIZE (x16) EALLOW DESCRIPTION PROTECTED SCICCRA 0x7050 1 No SCI-A Communications Control Register SCICTL1A 0x7051 1 No SCI-A Control Register 1 SCIHBAUDA 0x7052 1 No SCI-A Baud Register, High Bits SCILBAUDA 0x7053 1 No SCI-A Baud Register, Low Bits SCICTL2A 0x7054 1 No SCI-A Control Register 2 SCIRXSTA 0x7055 1 No SCI-A Receive Status Register SCIRXEMUA 0x7056 1 No SCI-A Receive Emulation Data Buffer Register SCIRXBUFA 0x7057 1 No SCI-A Receive Data Buffer Register SCITXBUFA 0x7059 1 No SCI-A Transmit Data Buffer Register SCIFFTXA(2) 0x705A 1 No SCI-A FIFO Transmit Register SCIFFRXA(2) 0x705B 1 No SCI-A FIFO Receive Register SCIFFCTA(2) 0x705C 1 No SCI-A FIFO Control Register SCIPRIA 0x705F 1 No SCI-A Priority Control Register (1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. (2) These registers are new registers for the FIFO mode. 102 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.6 Enhanced Controller Area Network (eCAN) 6.6.1 Enhanced Controller Area Network Device-Specific Information The CAN module (eCAN-A) has the following features: • Fully compliant with CAN protocol, version 2.0B • Supports data rates up to 1 Mbps • Thirty-two mailboxes, each with the following properties: – Configurable as receive or transmit – Configurable with standard or extended identifier – Has a programmable receive mask – Supports data and remote frame – Composed of 0 to 8 bytes of data – Uses a 32-bit time stamp on receive and transmit message – Protects against reception of new message – Holds the dynamically programmable priority of transmit message – Employs a programmable interrupt scheme with two interrupt levels – Employs a programmable alarm on transmission or reception time-out • Low-power mode • Programmable wake-up on bus activity • Automatic reply to a remote request message • Automatic retransmission of a frame in case of loss of arbitration or error • 32-bit local network time counter synchronized by a specific message (communication in conjunction with mailbox 16) • Self-test mode – Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, thereby eliminating the need for another node to provide the acknowledge bit. NOTE For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 4.6875 kbps. The F2805x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and exceptions. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 103 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Mailbox RAM (512 Bytes) 32-Message Mailbox of 4 x 32-Bit Words Memory Management Unit CPU Interface, Receive Control Unit, Timer Management Unit eCAN Memory (512 Bytes) Registers and Message Objects Control Message Controller 32 32 eCAN Protocol Kernel Receive Buffer Transmit Buffer Control Buffer Status Buffer Enhanced CAN Controller 32 eCAN0INT eCAN1INT Controls Address Data 32 SN65HVD23x 3.3-V CAN Transceiver CAN Bus TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Figure 6-20. eCAN Block Diagram and Interface Circuit Table 6-26. 3.3-V eCAN Transceivers PART NUMBER SUPPLY LOW-POWER SLOPE VREF OTHER TVOLTAGE MODE CONTROL A SN65HVD230 3.3 V Standby Adjustable Yes – –40°C to 85°C SN65HVD230Q 3.3 V Standby Adjustable Yes – –40°C to 125°C SN65HVD231 3.3 V Sleep Adjustable Yes – –40°C to 85°C SN65HVD231Q 3.3 V Sleep Adjustable Yes – –40°C to 125°C SN65HVD232 3.3 V None None None – –40°C to 85°C SN65HVD232Q 3.3 V None None None – –40°C to 125°C SN65HVD233 3.3 V Standby Adjustable None Diagnostic Loopback –40°C to 125°C SN65HVD234 3.3 V Standby and Sleep Adjustable None – –40°C to 125°C SN65HVD235 3.3 V Standby Adjustable None Autobaud Loopback –40°C to 125°C ISO1050 3–5.5 V None None None Built-in Isolation –55°C to 105°C Low Prop Delay Thermal Shutdown Failsafe Operation Dominant Time-Out 104 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION Mailbox Enable - CANME Mailbox Direction - CANMD Transmission Request Set - CANTRS Transmission Request Reset - CANTRR Transmission Acknowledge - CANTA Abort Acknowledge - CANAA Received Message Pending - CANRMP Received Message Lost - CANRML Remote Frame Pending - CANRFP Global Acceptance Mask - CANGAM Master Control - CANMC Bit-Timing Configuration - CANBTC Error and Status - CANES Transmit Error Counter - CANTEC Receive Error Counter - CANREC Global Interrupt Flag 0 - CANGIF0 Global Interrupt Mask - CANGIM Mailbox Interrupt Mask - CANMIM Mailbox Interrupt Level - CANMIL Overwrite Protection Control - CANOPC TX I/O Control - CANTIOC RX I/O Control - CANRIOC Time Stamp Counter - CANTSC Global Interrupt Flag 1 - CANGIF1 Time-Out Control - CANTOC Time-Out Status - CANTOS Reserved eCAN-A Control and Status Registers 61E8h-61E9h Message Identifier - MSGID Message Control - MSGCTRL Message Data Low - MDL Message Data High - MDH Message Mailbox (16 Bytes) Control and Status Registers 6000h 603Fh Local Acceptance Masks (LAM) (32 x 32-Bit RAM) 6040h 607Fh 6080h 60BFh 60C0h 60FFh eCAN-A Memory (512 Bytes) Message Object Time Stamps (MOTS) (32 x 32-Bit RAM) Message Object Time-Out (MOTO) (32 x 32-Bit RAM) 6100h-6107h Mailbox 0 6108h-610Fh Mailbox 1 6110h-6117h Mailbox 2 6118h-611Fh Mailbox 3 eCAN-A Memory RAM (512 Bytes) 6120h-6127h Mailbox 4 61E0h-61E7h Mailbox 28 61E8h-61EFh Mailbox 29 61F0h-61F7h Mailbox 30 61F8h-61FFh Mailbox 31 61EAh-61EBh 61ECh-61EDh 61EEh-61EFh TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Figure 6-21. eCAN-A Memory Map NOTE If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled if the eCAN RAM (LAM, MOTS, MOTO, and mailbox RAM) is used as generalpurpose RAM. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 105 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.6.2 Enhanced Controller Area Network Register Descriptions The CAN registers listed in Table 6-27 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary. Table 6-27. CAN Register Map(1) REGISTER NAME eCAN-A SIZE (x32) DESCRIPTION ADDRESS CANME 0x6000 1 Mailbox enable CANMD 0x6002 1 Mailbox direction CANTRS 0x6004 1 Transmit request set CANTRR 0x6006 1 Transmit request reset CANTA 0x6008 1 Transmission acknowledge CANAA 0x600A 1 Abort acknowledge CANRMP 0x600C 1 Receive message pending CANRML 0x600E 1 Receive message lost CANRFP 0x6010 1 Remote frame pending CANGAM 0x6012 1 Global acceptance mask CANMC 0x6014 1 Master control CANBTC 0x6016 1 Bit-timing configuration CANES 0x6018 1 Error and status CANTEC 0x601A 1 Transmit error counter CANREC 0x601C 1 Receive error counter CANGIF0 0x601E 1 Global interrupt flag 0 CANGIM 0x6020 1 Global interrupt mask CANGIF1 0x6022 1 Global interrupt flag 1 CANMIM 0x6024 1 Mailbox interrupt mask CANMIL 0x6026 1 Mailbox interrupt level CANOPC 0x6028 1 Overwrite protection control CANTIOC 0x602A 1 TX I/O control CANRIOC 0x602C 1 RX I/O control CANTSC 0x602E 1 Time stamp counter (Reserved in SCC mode) CANTOC 0x6030 1 Time-out control (Reserved in SCC mode) CANTOS 0x6032 1 Time-out status (Reserved in SCC mode) (1) These registers are mapped to Peripheral Frame 1. 106 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.7 Inter-Integrated Circuit (I2C) 6.7.1 Inter-Integrated Circuit Device-Specific Information The device contains one I2C Serial Port. Figure 6-22 shows how the I2C peripheral module interfaces within the device. The I2C module has the following features: • Compliance with the Philips Semiconductors I2C-bus specification (version 2.1): – Support for 1-bit to 8-bit format transfers – 7-bit and 10-bit addressing modes – General call – START byte mode – Support for multiple master-transmitters and slave-receivers – Support for multiple slave-transmitters and master-receivers – Combined master transmit/receive and receive/transmit mode – Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate) • One 4-word receive FIFO and one 4-word transmit FIFO • One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions: – Transmit-data ready – Receive-data ready – Register-access ready – No-acknowledgment received – Arbitration lost – Stop condition detected – Addressed as slave • An additional interrupt that can be used by the CPU when in FIFO mode • Module enable/disable capability • Free data format mode Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 107 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION I2CXSR I2CDXR I2CRSR I2CDRR Clock Synchronizer Prescaler Noise Filters Arbitrator I2C INT Peripheral Bus Interrupt to CPU/PIE SDA SCL Control/Status Registers CPU I2C Module TX FIFO RX FIFO FIFO Interrupt to CPU/PIE TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the SYSCLKOUT rate. B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off. Figure 6-22. I2C Peripheral Module Interfaces 6.7.2 Inter-Integrated Circuit Register Descriptions The registers in Table 6-28 configure and control the I2C port operation. Table 6-28. I2C-A Registers NAME ADDRESS EALLOW DESCRIPTION PROTECTED I2COAR 0x7900 No I2C own address register I2CIER 0x7901 No I2C interrupt enable register I2CSTR 0x7902 No I2C status register I2CCLKL 0x7903 No I2C clock low-time divider register I2CCLKH 0x7904 No I2C clock high-time divider register I2CCNT 0x7905 No I2C data count register I2CDRR 0x7906 No I2C data receive register I2CSAR 0x7907 No I2C slave address register I2CDXR 0x7908 No I2C data transmit register I2CMDR 0x7909 No I2C mode register I2CISRC 0x790A No I2C interrupt source register I2CPSC 0x790C No I2C prescaler register I2CFFTX 0x7920 No I2C FIFO transmit register I2CFFRX 0x7921 No I2C FIFO receive register I2CRSR – No I2C receive shift register (not accessible to the CPU) I2CXSR – No I2C transmit shift register (not accessible to the CPU) 108 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.7.3 Inter-Integrated Circuit Electrical Data/Timing Table 6-29. I2C Timing TEST CONDITIONS MIN MAX UNIT fSCL SCL clock frequency I2C clock module frequency is between 400 kHz 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately vil Low level input voltage 0.3 VDDIO V Vih High level input voltage 0.7 VDDIO V Vhys Input hysteresis 0.05 VDDIO V Vol Low level output voltage 3 mA sink current 0 0.4 V tLOW Low period of SCL clock I2C clock module frequency is between 1.3 μs 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately tHIGH High period of SCL clock I2C clock module frequency is between 0.6 μs 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately lI Input current with an input voltage –10 10 μA between 0.1 VDDIO and 0.9 VDDIO MAX Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 109 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.8 Enhanced Pulse Width Modulator (ePWM) 6.8.1 Enhanced Pulse Width Modulator Device-Specific Information The devices contain up to seven enhanced PWM Modules (ePWM1–ePWM7). Figure 6-23 shows a block diagram of multiple ePWM modules. Figure 6-24 shows the signal interconnections with the ePWM. See the Enhanced Pulse Width Modulator (ePWM) Module chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5) for more details. 110 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION EPWM1TZINT PIE EPWM1INT EPWM2TZINT EPWM2INT EPWMxTZINT EPWMxINT CTRIP Output Subsystem SOCA1 ADC SOCB1 SOCA2 SOCB2 SOCAx SOCBx EPWM1SYNCI EPWM2SYNCI EPWM1SYNCO EPWM2SYNCO EPWM1 Module EPWM2 Module EPWMxSYNCI EPWMx Module CTRIPxx TZ6 TZ6 TZ1 to TZ3 TZ5 CLOCKFAIL TZ4 EQEP1ERR EMUSTOP TZ5 CLOCKFAIL TZ4 EQEP1ERR EMUSTOP EPWM1ENCLK TBCLKSYNC EPWM2ENCLK TBCLKSYNC TZ5 TZ6 EPWMxENCLK TBCLKSYNC CLOCKFAIL TZ4 EQEP1ERR EMUSTOP EPWM1B C28x CPU System Control eQEP1 TZ1 to TZ3 TZ1 to TZ3 EPWM1SYNCO EPWM2B eCAPI EPWMxB EQEP1ERR EPWMxA EPWM2A EPWM1A G P I O M U X ADCSOCBO ADCSOCAO Peripheral Bus Pulse Stretch (32 SYSCLKOUT Cycles, Active-Low Output) SOCA1 SOCA2 SPCAx Pulse Stretch (32 SYSCLKOUT Cycles, Active-Low Output) SOCB1 SOCB2 SPCBx EPWMSYNCI TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Figure 6-23. ePWM Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 111 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TBPRD Shadow (24) TBPRD Active (24) Counter Up/Down (16 Bit) TCBNT Active (16) TBCTL[PHSEN] CTR=PRD 16 Phase Control CTR=ZERO CTR_Dir CTR=ZERO CTR=CMPB Disabled TBCTL[SYNCOSEL] EPWMxSYNCO Time-Base (TB) TBPHS Active (24) Sync In/Out Select Mux CTR=PRD CTR=ZERO CTR=CMPA CTR=CMPB CTR_Dir DCAEVT1.soc (A) DCBEVT1.soc (A) Event Trigger and Interrupt (ET) EPWMxINT EPWMxSOCA EPWMxSOCB EPWMxSOCA EPWMxSOCB ADC Action Qualifier (AQ) EPWMA Dead Band (DB) EPWMB PWM Chopper (PC) Trip Zone (TZ) EPWMxA EPWMxB CTR=ZERO EPWMxTZINT TZ1 to TZ3 EMUSTOP CLOCKFAIL EQEP1ERR DCAEVT1.force (A) DCAEVT2.force (A) DCBEVT1.force (A) DCBEVT2.force (A) CTR=CMPA 16 CTR=CMPB 16 CMPB Active (16) CMPB Shadow (16) CTR=PRD or ZERO DCAEVT1.inter DCBEVT1.inter DCAEVT2.inter DCBEVT2.inter EPWMxSYNCI TBCTL[SWFSYNC] (Software Forced Sync) DCAEVT1.sync DCBEVT1.sync CMPA Active (24) CMPA Shadow (24) TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ signals. Figure 6-24. ePWM Sub-Modules Showing Critical Internal Signal Interconnections 112 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.8.2 Enhanced Pulse Width Modulator Register Descriptions Table 6-30 and Table 6-31 show the complete ePWM register set per module. Table 6-30. ePWM1–ePWM4 Control and Status Registers NAME ePWM1 ePWM2 ePWM3 ePWM4 SIZE (x16) / DESCRIPTION #SHADOW TBCTL 0x6800 0x6840 0x6880 0x68C0 1 / 0 Time Base Control Register TBSTS 0x6801 0x6841 0x6881 0x68C1 1 / 0 Time Base Status Register Reserved 0x6802 0x6842 0x6882 0x68C2 1 / 0 Reserved TBPHS 0x6803 0x6843 0x6883 0x68C3 1 / 0 Time Base Phase Register TBCTR 0x6804 0x6844 0x6884 0x68C4 1 / 0 Time Base Counter Register TBPRD 0x6805 0x6845 0x6885 0x68C5 1 / 1 Time Base Period Register Set Reserved 0x6806 0x6846 0x6886 0x68C6 1 / 1 Reserved CMPCTL 0x6807 0x6847 0x6887 0x68C7 1 / 0 Counter Compare Control Register Reserved 0x6808 0x6848 0x6888 0x68C8 1 / 1 Reserved CMPA 0x6809 0x6849 0x6889 0x68C9 1 / 1 Counter Compare A Register Set CMPB 0x680A 0x684A 0x688A 0x68CA 1 / 1 Counter Compare B Register Set AQCTLA 0x680B 0x684B 0x688B 0x68CB 1 / 0 Action Qualifier Control Register For Output A AQCTLB 0x680C 0x684C 0x688C 0x68CC 1 / 0 Action Qualifier Control Register For Output B AQSFRC 0x680D 0x684D 0x688D 0x68CD 1 / 0 Action Qualifier Software Force Register AQCSFRC 0x680E 0x684E 0x688E 0x68CE 1 / 1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x680F 0x684F 0x688F 0x68CF 1 / 1 Dead-Band Generator Control Register DBRED 0x6810 0x6850 0x6890 0x68D0 1 / 0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6811 0x6851 0x6891 0x68D1 1 / 0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6812 0x6852 0x6892 0x68D2 1 / 0 Trip Zone Select Register(1) TZDCSEL 0x6813 0x6853 0x6893 0x98D3 1 / 0 Trip Zone Digital Compare Register TZCTL 0x6814 0x6854 0x6894 0x68D4 1 / 0 Trip Zone Control Register(1) TZEINT 0x6815 0x6855 0x6895 0x68D5 1 / 0 Trip Zone Enable Interrupt Register(1) TZFLG 0x6816 0x6856 0x6896 0x68D6 1 / 0 Trip Zone Flag Register (1) TZCLR 0x6817 0x6857 0x6897 0x68D7 1 / 0 Trip Zone Clear Register(1) TZFRC 0x6818 0x6858 0x6898 0x68D8 1 / 0 Trip Zone Force Register(1) ETSEL 0x6819 0x6859 0x6899 0x68D9 1 / 0 Event Trigger Selection Register ETPS 0x681A 0x685A 0x689A 0x68DA 1 / 0 Event Trigger Prescale Register ETFLG 0x681B 0x685B 0x689B 0x68DB 1 / 0 Event Trigger Flag Register ETCLR 0x681C 0x685C 0x689C 0x68DC 1 / 0 Event Trigger Clear Register (1) Registers that are EALLOW protected. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 113 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 6-30. ePWM1–ePWM4 Control and Status Registers (continued) NAME ePWM1 ePWM2 ePWM3 ePWM4 SIZE (x16) / DESCRIPTION #SHADOW ETFRC 0x681D 0x685D 0x689D 0x68DD 1 / 0 Event Trigger Force Register PCCTL 0x681E 0x685E 0x689E 0x68DE 1 / 0 PWM Chopper Control Register Reserved 0x6820 0x6860 0x68A0 0x68E0 1 / 0 Reserved Reserved 0x6821 - - - 1 / 0 Reserved Reserved 0x6826 - - - 1 / 0 Reserved Reserved 0x6828 0x6868 0x68A8 0x68E8 1 / 0 Reserved Reserved 0x682A 0x686A 0x68AA 0x68EA 1 / W(2) Reserved TBPRDM 0x682B 0x686B 0x68AB 0x68EB 1 / W(2) Time Base Period Register Mirror Reserved 0x682C 0x686C 0x68AC 0x68EC 1 / W(2) Reserved CMPAM 0x682D 0x686D 0x68AD 0x68ED 1 / W(2) Compare A Register Mirror DCTRIPSEL 0x6830 0x6870 0x68B0 0x68F0 1 / 0 Digital Compare Trip Select Register (1) DCACTL 0x6831 0x6871 0x68B1 0x68F1 1 / 0 Digital Compare A Control Register(1) DCBCTL 0x6832 0x6872 0x68B2 0x68F2 1 / 0 Digital Compare B Control Register(1) DCFCTL 0x6833 0x6873 0x68B3 0x68F3 1 / 0 Digital Compare Filter Control Register(1) DCCAPCT 0x6834 0x6874 0x68B4 0x68F4 1 / 0 Digital Compare Capture Control Register(3) DCFOFFSET 0x6835 0x6875 0x68B5 0x68F5 1 / 1 Digital Compare Filter Offset Register DCFOFFSETCNT 0x6836 0x6876 0x68B6 0x68F6 1 / 0 Digital Compare Filter Offset Counter Register DCFWINDOW 0x6837 0x6877 0x68B7 0x68F7 1 / 0 Digital Compare Filter Window Register DCFWINDOWCNT 0x6838 0x6878 0x68B8 0x68F8 1 / 0 Digital Compare Filter Window Counter Register DCCAP 0x6839 0x6879 0x68B9 0x68F9 1 / 1 Digital Compare Counter Capture Register (2) W = Write to shadow register (3) Registers that are EALLOW protected. 114 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 Table 6-31. ePWM5–ePWM7 Control and Status Registers NAME ePWM5 ePWM6 ePWM7 SIZE (x16) / DESCRIPTION #SHADOW TBCTL 0x6900 0x6940 0x6980 1 / 0 Time Base Control Register TBSTS 0x6901 0x6941 0x6981 1 / 0 Time Base Status Register Reserved 0x6902 0x6942 0x6982 1 / 0 Reserved TBPHS 0x6903 0x6943 0x6983 1 / 0 Time Base Phase Register TBCTR 0x6904 0x6944 0x6984 1 / 0 Time Base Counter Register TBPRD 0x6905 0x6945 0x6985 1 / 1 Time Base Period Register Set Reserved 0x6906 0x6946 0x6986 1 / 1 Reserved CMPCTL 0x6907 0x6947 0x6987 1 / 0 Counter Compare Control Register Reserved 0x6908 0x6948 0x6988 1 / 1 Reserved CMPA 0x6909 0x6949 0x6989 1 / 1 Counter Compare A Register Set CMPB 0x690A 0x694A 0x698A 1 / 1 Counter Compare B Register Set AQCTLA 0x690B 0x694B 0x698B 1 / 0 Action Qualifier Control Register For Output A AQCTLB 0x690C 0x694C 0x698C 1 / 0 Action Qualifier Control Register For Output B AQSFRC 0x690D 0x694D 0x698D 1 / 0 Action Qualifier Software Force Register AQCSFRC 0x690E 0x694E 0x698E 1 / 1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x690F 0x694F 0x698F 1 / 1 Dead-Band Generator Control Register DBRED 0x6910 0x6950 0x6990 1 / 0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6911 0x6951 0x6991 1 / 0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6912 0x6952 0x6992 1 / 0 Trip Zone Select Register(1) TZDCSEL 0x6913 0x6953 0x6993 1 / 0 Trip Zone Digital Compare Register TZCTL 0x6914 0x6954 0x6994 1 / 0 Trip Zone Control Register(1) TZEINT 0x6915 0x6955 0x6995 1 / 0 Trip Zone Enable Interrupt Register(1) TZFLG 0x6916 0x6956 0x6996 1 / 0 Trip Zone Flag Register (1) TZCLR 0x6917 0x6957 0x6997 1 / 0 Trip Zone Clear Register(1) TZFRC 0x6918 0x6958 0x6998 1 / 0 Trip Zone Force Register(1) ETSEL 0x6919 0x6959 0x6999 1 / 0 Event Trigger Selection Register ETPS 0x691A 0x695A 0x699A 1 / 0 Event Trigger Prescale Register ETFLG 0x691B 0x695B 0x699B 1 / 0 Event Trigger Flag Register ETCLR 0x691C 0x695C 0x699C 1 / 0 Event Trigger Clear Register ETFRC 0x691D 0x695D 0x699D 1 / 0 Event Trigger Force Register PCCTL 0x691E 0x695E 0x699E 1 / 0 PWM Chopper Control Register Reserved 0x6920 0x6960 0x69A0 1 / 0 Reserved Reserved - - - 1 / 0 Reserved Reserved - - - 1 / 0 Reserved Reserved 0x6928 0x6968 0x69A8 1 / 0 Reserved Reserved 0x692A 0x696A 0x69AA 1 / W(2) Reserved TBPRDM 0x692B 0x696B 0x69AB 1 / W(2) Time Base Period Register Mirror Reserved 0x692C 0x696C 0x69AC 1 / W(2) Reserved CMPAM 0x692D 0x696D 0x69AD 1 / W(2) Compare A Register Mirror DCTRIPSEL 0x6930 0x6970 0x69B0 1 / 0 Digital Compare Trip Select Register (1) DCACTL 0x6931 0x6971 0x69B1 1 / 0 Digital Compare A Control Register(1) DCBCTL 0x6932 0x6972 0x69B2 1 / 0 Digital Compare B Control Register(1) DCFCTL 0x6933 0x6973 0x69B3 1 / 0 Digital Compare Filter Control Register(1) DCCAPCT 0x6934 0x6974 0x69B4 1 / 0 Digital Compare Capture Control Register(1) (1) Registers that are EALLOW protected. (2) W = Write to shadow register Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 115 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com Table 6-31. ePWM5–ePWM7 Control and Status Registers (continued) NAME ePWM5 ePWM6 ePWM7 SIZE (x16) / DESCRIPTION #SHADOW DCFOFFSET 0x6935 0x6975 0x69B5 1 / 1 Digital Compare Filter Offset Register DCFOFFSETCNT 0x6936 0x6976 0x69B6 1 / 0 Digital Compare Filter Offset Counter Register DCFWINDOW 0x6937 0x6977 0x69B7 1 / 0 Digital Compare Filter Window Register DCFWINDOWCNT 0x6938 0x6978 0x69B8 1 / 0 Digital Compare Filter Window Counter Register DCCAP 0x6939 0x6979 0x69B9 1 / 1 Digital Compare Counter Capture Register 6.8.3 Enhanced Pulse Width Modulator Electrical Data/Timing PWM refers to PWM outputs on ePWM1–7. Table 6-32 shows the PWM timing requirements and Table 6- 33, switching characteristics. Table 6-32. ePWM Timing Requirements(1) MIN MAX UNIT tw(SYCIN) Sync input pulse width Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles With input qualifier 1tc(SCO) + tw(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-45. Table 6-33. ePWM Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tw(PWM) Pulse duration, PWMx output high/low 33.33 ns tw(SYNCOUT) Sync output pulse width 8tc(SCO) cycles td(PWM)tza Delay time, trip input active to PWM forced high no pin load 25 ns Delay time, trip input active to PWM forced low td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z 20 ns 116 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION PWM (B) TZ (A) SYSCLK tw(TZ) td(TZ-PWM)HZ TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.8.3.1 Trip-Zone Input Timing Table 6-34. Trip-Zone Input Timing Requirements(1) MIN MAX UNIT tw(TZ) Pulse duration, TZx input low Asynchronous 2tc(TBCLK) cycles Synchronous 2tc(TBCLK) cycles With input qualifier 2tc(TBCLK) + tw(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-45. A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6 B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software. Figure 6-25. PWM Hi-Z Characteristics Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 117 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TSCTR (counter−32 bit) RST CAP1 (APRD active) LD CAP2 (ACMP active) LD CAP3 (APRD shadow) LD CAP4 (ACMP shadow) LD Continuous / Oneshot Capture Control LD1 LD2 LD3 LD4 32 32 PRD [0−31] CMP [0−31] CTR [0−31] eCAPx Interrupt Trigger and Flag control to PIE CTR=CMP 32 32 32 32 32 ACMP shadow Event Pre-scale CTRPHS (phase register−32 bit) SYNCOut SYNCIn Event qualifier Polarity select Polarity select Polarity select Polarity select CTR=PRD CTR_OVF 4 PWM compare logic CTR [0−31] PRD [0−31] CMP [0−31] CTR=CMP CTR=PRD OVF CTR_OVF APWM mode Delta−mode SYNC Capture events 4 CEVT[1:4] APRD shadow 32 32 MODE SELECT TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.9 Enhanced Capture Module (eCAP) 6.9.1 Enhanced Capture Module Device-Specific Information The device contains an enhanced capture module (eCAP1). Figure 6-26 shows a functional block diagram of a module. Figure 6-26. eCAP Functional Block Diagram The eCAP module is clocked at the SYSCLKOUT rate. The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for low power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off. 118 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.9.2 Enhanced Capture Module Register Descriptions Table 6-35 shows the eCAP Control and Status Registers. Table 6-35. eCAP Control and Status Registers NAME eCAP1 SIZE (x16) EALLOW PROTECTED DESCRIPTION TSCTR 0x6A00 2 Time-Stamp Counter CTRPHS 0x6A02 2 Counter Phase Offset Value Register CAP1 0x6A04 2 Capture 1 Register CAP2 0x6A06 2 Capture 2 Register CAP3 0x6A08 2 Capture 3 Register CAP4 0x6A0A 2 Capture 4 Register Reserved 0x6A0C – 0x6A12 8 Reserved ECCTL1 0x6A14 1 Capture Control Register 1 ECCTL2 0x6A15 1 Capture Control Register 2 ECEINT 0x6A16 1 Capture Interrupt Enable Register ECFLG 0x6A17 1 Capture Interrupt Flag Register ECCLR 0x6A18 1 Capture Interrupt Clear Register ECFRC 0x6A19 1 Capture Interrupt Force Register Reserved 0x6A1A – 0x6A1F 6 Reserved 6.9.3 Enhanced Capture Module Electrical Data/Timing Table 6-36 shows the eCAP timing requirement and Table 6-37 shows the eCAP switching characteristics. Table 6-36. Enhanced Capture (eCAP) Timing Requirement(1) MIN MAX UNIT tw(CAP) Capture input pulse width Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles With input qualifier 1tc(SCO) + tw(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-45. Table 6-37. eCAP Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT tw(APWM) Pulse duration, APWMx output high/low 20 ns Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 119 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION QWDTMR QWDPRD 16 UTIME QWDOG QUPRD QUTMR 32 UTOUT WDTOUT Quadrature Capture Unit (QCAP) QCPRDLAT QCTMRLAT 16 QFLG QEPSTS QEPCTL Registers Used by Multiple Units QCLK QDIR QI QS PHE PCSOUT Quadrature Decoder (QDU) QDECCTL 16 Position Counter/ Control Unit (PCCU) QPOSLAT QPOSSLAT 16 QPOSILAT EQEPxAIN EQEPxBIN EQEPxIIN EQEPxIOUT EQEPxIOE EQEPxSIN EQEPxSOUT EQEPxSOE GPIO MUX EQEPxA/XCLK EQEPxB/XDIR EQEPxS EQEPxI QPOSCMP QEINT QFRC 32 QCLR QPOSCTL 32 16 QPOSCNT QPOSMAX QPOSINIT PIE EQEPxINT Enhanced QEP (eQEP) Peripheral System Control Registers QCTMR QCPRD 16 16 QCAPCTL EQEPxENCLK SYSCLKOUT To CPU Data Bus TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.10 Enhanced Quadrature Encoder Pulse (eQEP) 6.10.1 Enhanced Quadrature Encoder Pulse Device-Specific Information The device contains one enhanced quadrature encoder pulse (eQEP) module. Figure 6-27 shows the eQEP functional block diagram. Figure 6-27. eQEP Functional Block Diagram 120 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.10.2 Enhanced Quadrature Encoder Pulse Register Descriptions Table 6-38 shows the eQEP Control and Status Registers. Table 6-38. eQEP Control and Status Registers eQEP1 eQEP1 NAME ADDRESS SIZE(x16)/ REGISTER DESCRIPTION #SHADOW QPOSCNT 0x6B00 2/0 eQEP Position Counter QPOSINIT 0x6B02 2/0 eQEP Initialization Position Count QPOSMAX 0x6B04 2/0 eQEP Maximum Position Count QPOSCMP 0x6B06 2/1 eQEP Position-compare QPOSILAT 0x6B08 2/0 eQEP Index Position Latch QPOSSLAT 0x6B0A 2/0 eQEP Strobe Position Latch QPOSLAT 0x6B0C 2/0 eQEP Position Latch QUTMR 0x6B0E 2/0 eQEP Unit Timer QUPRD 0x6B10 2/0 eQEP Unit Period Register QWDTMR 0x6B12 1/0 eQEP Watchdog Timer QWDPRD 0x6B13 1/0 eQEP Watchdog Period Register QDECCTL 0x6B14 1/0 eQEP Decoder Control Register QEPCTL 0x6B15 1/0 eQEP Control Register QCAPCTL 0x6B16 1/0 eQEP Capture Control Register QPOSCTL 0x6B17 1/0 eQEP Position-compare Control Register QEINT 0x6B18 1/0 eQEP Interrupt Enable Register QFLG 0x6B19 1/0 eQEP Interrupt Flag Register QCLR 0x6B1A 1/0 eQEP Interrupt Clear Register QFRC 0x6B1B 1/0 eQEP Interrupt Force Register QEPSTS 0x6B1C 1/0 eQEP Status Register QCTMR 0x6B1D 1/0 eQEP Capture Timer QCPRD 0x6B1E 1/0 eQEP Capture Period Register QCTMRLAT 0x6B1F 1/0 eQEP Capture Timer Latch QCPRDLAT 0x6B20 1/0 eQEP Capture Period Latch Reserved 0x6B21 – 31/0 0x6B3F Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Timings 121 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 SPRS797 –NOVEMBER 2012 www.ti.com 6.10.3 Enhanced Quadrature Encoder Pulse Electrical Data/Timing Table 6-39 shows the eQEP timing requirement and Table 6-40 shows the eQEP switching characteristics. Table 6-39. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements(1) TEST CONDITIONS MIN MAX UNIT tw(QEPP) QEP input period Synchronous 2tc(SCO) cycles With input qualifier 2[1tc(SCO) + tw(IQSW)] cycles tw(INDEXH) QEP Index Input High time Synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) +tw(IQSW) cycles tw(INDEXL) QEP Index Input Low time Synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) + tw(IQSW) cycles tw(STROBH) QEP Strobe High time Synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) + tw(IQSW) cycles tw(STROBL) QEP Strobe Input Low time Synchronous 2tc(SCO) cycles With input qualifier 2tc(SCO) +tw(IQSW) cycles (1) For an explanation of the input qualifier parameters, see Table 6-45. Table 6-40. eQEP Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX UNIT td(CNTR)xin Delay time, external clock to counter increment 4tc(SCO) cycles td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 6tc(SCO) cycles 122 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 ADVANCE INFORMATION TRST 1 0 C28x Core TCK/GPIO38 TCK XCLKIN GPIO38_in GPIO38_out TDO GPIO37_out TDO/GPIO37 GPIO37_in 1 0 TMS TMS/GPIO36 GPIO36_out GPIO36_in 1 1 0 TDI TDI/GPIO35 GPIO35_out GPIO35_in 1 TRST TRST = 0: JTAG Disabled (GPIO Mode) = 1: JTAG Mode TRST TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797 –NOVEMBER 2012 6.11 JTAG Port 6.11.1 JTAG Port Device-Specific Informatio