AD8307 Data Sheet - Analog Devices - Farnell Element 14 - Revenir à l'accueil

 

 

Branding Farnell element14 (France)

 

Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Recherche intégrée

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

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Voltage Level Translation

Puce électronique / Microchip :

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Raspberry Pi board B product overview

Logiciels :

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Introduction to Cadsoft EAGLE PCB Design Software in Chinese

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Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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Ben's Autodesk 123D Tutorial Trailer

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Ben's CadSoft EAGLE Tutorial Trailer

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Ben Heck's Soldering Tutorial Trailer

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Ben Heck's AVR Dev Board tutorial

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Ben Heck's Pinball Tutorial Trailer

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Ben Heck's Interface Tutorial Trailer

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First Stage with Python and PiFace Digital

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Cypress - Getting Started with PSoC® 3 - Part 2

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

Autres documentations :
 Farnell-MSP430-Hardw..> 29-Jul-2014 10:36  1.1M  

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 [TXT] Farnell-Full-Datashe..> 15-Jul-2014 17:08 951K  

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Low Cost, Low Power, True RMS-to-DC Converter Data Sheet AD736 Rev. I Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1988–2012 Analog Devices, Inc. All rights reserved. FEATURES Converts an ac voltage waveform to a dc voltage and then converts to the true rms, average rectified, or absolute value 200 mV rms full-scale input range (larger inputs with input attenuator) High input impedance: 1012 Ω Low input bias current: 25 pA maximum High accuracy: ±0.3 mV ± 0.3% of reading RMS conversion with signal crest factors up to 5 Wide power supply range: +2.8 V, −3.2 V to ±16.5 V Low power: 200 μA maximum supply current Buffered voltage output No external trims needed for specified accuracy Related device: the AD737—features a power-down control with standby current of only 25 μA; the dc output voltage is negative and the output impedance is 8 kΩ GENERAL DESCRIPTION The AD736 is a low power, precision, monolithic true rms-to-dc converter. It is laser trimmed to provide a maximum error of ±0.3 mV ± 0.3% of reading with sine wave inputs. Furthermore, it maintains high accuracy while measuring a wide range of input waveforms, including variable duty-cycle pulses and triac (phase)-controlled sine waves. The low cost and small size of this converter make it suitable for upgrading the performance of non-rms precision rectifiers in many applications. Compared to these circuits, the AD736 offers higher accuracy at an equal or lower cost. The AD736 can compute the rms value of both ac and dc input voltages. It can also be operated as an ac-coupled device by adding one external capacitor. In this mode, the AD736 can resolve input signal levels of 100 μV rms or less, despite variations in temperature or supply voltage. High accuracy is also maintained for input waveforms with crest factors of 1 to 3. In addition, crest factors as high as 5 can be measured (introducing only 2.5% additional error) at the 200 mV full-scale input level. The AD736 has its own output buffer amplifier, thereby pro-viding a great deal of design flexibility. Requiring only 200 μA of power supply current, the AD736 is optimized for use in portable multimeters and other battery-powered applications. FUNCTIONAL BLOCK DIAGRAM CC8kΩ–VSCAVCOMVINCAVOUTFULL WAVERECTIFIERRMSCORE8kΩCF(OPT)CFBIASSECTION+VS00834-001 Figure 1. The AD736 allows the choice of two signal input terminals: a high impedance FET input (1012 Ω) that directly interfaces with High-Z input attenuators and a low impedance input (8 kΩ) that allows the measurement of 300 mV input levels while operating from the minimum power supply voltage of +2.8 V, −3.2 V. The two inputs can be used either single ended or differentially. The AD736 has a 1% reading error bandwidth that exceeds 10 kHz for the input amplitudes from 20 mV rms to 200 mV rms while consuming only 1 mW. The AD736 is available in four performance grades. The AD736J and AD736K grades are rated over the 0°C to +70°C and −20°C to +85°C commercial temperature ranges. The AD736A and AD736B grades are rated over the −40°C to +85°C industrial temperature range. The AD736 is available in three low cost, 8-lead packages: PDIP, SOIC, and CERDIP. PRODUCT HIGHLIGHTS 1. The AD736 is capable of computing the average rectified value, absolute value, or true rms value of various input signals. 2. Only one external component, an averaging capacitor, is required for the AD736 to perform true rms measurement. 3. The low power consumption of 1 mW makes the AD736 suitable for many battery-powered applications. 4. A high input impedance of 1012 Ω eliminates the need for an external buffer when interfacing with input attenuators. 5. A low impedance input is available for those applications that require an input signal up to 300 mV rms operating from low power supply voltages. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1  Low Supply-Voltage Range: 1.8 V to 3.6 V  Ultralow Power Consumption − Active Mode: 330 μA at 1 MHz, 2.2 V − Standby Mode: 1.1 μA − Off Mode (RAM Retention): 0.2 μA  Five Power-Saving Modes  Wake-Up From Standby Mode in Less Than 6 μs  16-Bit RISC Architecture, 125-ns Instruction Cycle Time  Three-Channel Internal DMA  12-Bit Analog-to-Digital (A/D) Converter With Internal Reference, Sample-and-Hold, and Autoscan Feature  Dual 12-Bit Digital-to-Analog (D/A) Converters With Synchronization  16-Bit Timer_A With Three Capture/Compare Registers  16-Bit Timer_B With Three or Seven Capture/Compare-With-Shadow Registers  On-Chip Comparator  Serial Communication Interface (USART0), Functions as Asynchronous UART or Synchronous SPI or I2CTM Interface  Serial Communication Interface (USART1), Functions as Asynchronous UART or Synchronous SPI Interface  Supply Voltage Supervisor/Monitor With Programmable Level Detection  Brownout Detector  Bootstrap Loader I2C is a registered trademark of Philips Incorporated.  Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse  Family Members Include − MSP430F155 16KB+256B Flash Memory 512B RAM − MSP430F156 24KB+256B Flash Memory 1KB RAM − MSP430F157 32KB+256B Flash Memory, 1KB RAM − MSP430F167 32KB+256B Flash Memory, 1KB RAM − MSP430F168 48KB+256B Flash Memory, 2KB RAM − MSP430F169 60KB+256B Flash Memory, 2KB RAM − MSP430F1610 32KB+256B Flash Memory 5KB RAM − MSP430F1611 48KB+256B Flash Memory 10KB RAM − MSP430F1612 55KB+256B Flash Memory 5KB RAM  Available in 64-Pin QFP Package (PM) and 64-Pin QFN Package (RTD)  For Complete Module Descriptions, See the MSP430x1xx Family User’s Guide, Literature Number SLAU049 description The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 μs. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection. PRODUCTION DATA information is current as of publication date. Copyright © 2011, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) The MSP430F15x/16x/161x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit A/D converter, dual 12-bit D/A converter, one or two universal serial synchronous/asynchronous communication interfaces (USART), I2C, DMA, and 48 I/O pins. In addition, the MSP430F161x series offers extended RAM addressing for memory-intensive applications and large C-stack requirements. Typical applications include sensor systems, industrial control applications, hand-held meters, etc. AVAILABLE OPTIONS T PACKAGED DEVICES TA PLASTIC 64-PIN QFP (PM) PLASTIC 64-PIN QFN (RTD) −40°C to 85°C MSP430F155IPM MSP430F156IPM MSP430F157IPM MSP430F167IPM MSP430F168IPM MSP430F169IPM MSP430F1610IPM MSP430F1611IPM MSP430F1612IPM MSP430F155IRTD MSP430F156IRTD MSP430F157IRTD MSP430F167IRTD MSP430F168IRTD MSP430F169IRTD MSP430F1610IRTD MSP430F1611IRTD MSP430F1612IRTD † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. DEVELOPMENT TOOL SUPPORT All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging and programming through easy to use development tools. Recommended hardware options include the following:  Debugging and Programming Interface − MSP-FET430UIF (USB) − MSP-FET430PIF (Parallel Port)  Debugging and Programming Interface with Target Board − MSP-FET430U64 (PM package)  Standalone Target Board − MSP-TS430PM64 (PM package)  Production Programmer − MSP-GANG430 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 pin designation, MSP430F155, MSP430F156, and MSP430F157 17 18 19 P5.4/MCLK P5.3 P5.2 P5.1 P5.0 P4.7/TBCLK P4.6 P4.5 P4.4 P4.3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7 P3.6 P3.5/URXD0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DVCC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6/DAC0 P6.7/A7/DAC1/SVSIN VREF+ XIN XOUT VeREF+ VREF−/VeREF− P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 25 26 27 28 29 53 52 51 50 49 30 31 32 PM, RTD PACKAGE (TOP VIEW) AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC P2.6/ADC12CLK/DMAE0 P2.7/TA0 P3.0/STE0 P3.1/SIMO0/SDA P3.2/SOMI0 P3.3/UCLK0/SCL P3.4/UTXD0 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pin designation, MSP430F167, MSP430F168, MSP430F169 17 18 19 P5.4/MCLK P5.3/UCLK1 P5.2/SOMI1 P5.1/SIMO1 P5.0/STE1 P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7/URXD1 P3.6/UTXD1 P3.5/URXD0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DVCC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6/DAC0 P6.7/A7/DAC1/SVSIN VREF+ XIN XOUT VeREF+ VREF−/VeREF− P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 25 26 27 28 29 53 52 51 50 49 30 31 32 PM, RTD PACKAGE (TOP VIEW) AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC P2.6/ADC12CLK/DMAE0 P2.7/TA0 P3.0/STE0 P3.1/SIMO0/SDA P3.2/SOMI0 P3.3/UCLK0/SCL P3.4/UTXD0 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 pin designation, MSP430F1610, MSP430F1611, MSP430F1612 17 18 19 P5.4/MCLK P5.3/UCLK1 P5.2/SOMI1 P5.1/SIMO1 P5.0/STE1 P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7/URXD1 P3.6/UTXD1 P3.5/URXD0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DVCC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6/DAC0 P6.7/A7/DAC1/SVSIN VREF+ XIN XOUT VeREF+ VREF−/VeREF− P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 25 26 27 28 29 53 52 51 50 49 30 31 32 PM, RTD PACKAGE (TOP VIEW) AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC P2.6/ADC12CLK/DMAE0 P2.7/TA0 P3.0/STE0 P3.1/SIMO0/SDA P3.2/SOMI0 P3.3/UCLK0/SCL P3.4/UTXD0 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram, MSP430F15x Oscillator ACLK SMCLK CPU Incl. 16 Reg. Bus Conv MCB XIN XOUT P2 P3 P4 XT2IN XT2OUT TMS TCK MDB, 16 Bit MAB, 16 Bit MCLK 4 TDI/TCLK TDO/TDI P5 P6 MAB, 4 Bit DVCC DVSS AVCC AVSS RST/NMI System Clock ROSC P1 32KB Flash 24KB Flash 16KB Flash 1KB RAM 1KB RAM 512B RAM ADC12 12-Bit 8 Channels <10μs Conv. DAC12 12-Bit 2 Channels Voltage out DMA Controller 3 Channels Watchdog Timer 15/16-Bit Timer_B3 3 CC Reg Shadow Reg Timer_A3 3 CC Reg Test JTAG Emulation Module I/O Port 1/2 16 I/Os, with Interrupt Capability I/O Port 3/4 16 I/Os POR SVS Brownout Comparator A USART0 UART Mode SPI Mode I2C Mode I/O Port 5/6 16 I/Os MDB, 16-Bit MDB, 8 Bit MAB, 16-Bit 8 8 8 8 8 8 functional block diagram, MSP430F16x Oscillator ACLK SMCLK CPU Incl. 16 Reg. Bus Conv MCB XIN XOUT P2 P3 P4 XT2IN XT2OUT TMS TCK MDB, 16 Bit MAB, 16 Bit MCLK 4 TDI/TCLK TDO/TDI P5 P6 MAB, 4 Bit DVCC DVSS AVCC AVSS RST/NMI System Clock ROSC P1 Hardware Multiplier MPY, MPYS MAC,MACS 60KB Flash 48KB Flash 32KB Flash 2KB RAM 2KB RAM 1KB RAM ADC12 12-Bit 8 Channels <10μs Conv. DAC12 12-Bit 2 Channels Voltage out DMA Controller 3 Channels Watchdog Timer 15/16-Bit Timer_B7 7 CC Reg Shadow Reg Timer_A3 3 CC Reg Test JTAG Emulation Module I/O Port 1/2 16 I/Os, with Interrupt Capability I/O Port 3/4 16 I/Os POR SVS Brownout Comparator A USART0 UART Mode SPI Mode I2C Mode USART1 UART Mode SPI Mode I/O Port 5/6 16 I/Os MDB, 16-Bit MDB, 8 Bit MAB, 16-Bit 8 8 8 8 8 8 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 functional block diagram, MSP430F161x Oscillator ACLK SMCLK CPU Incl. 16 Reg. Bus Conv MCB XIN XOUT P2 P3 P4 XT2IN XT2OUT TMS TCK MDB, 16 Bit MAB, 16 Bit MCLK 4 TDI/TCLK TDO/TDI P5 P6 MAB, 4 Bit DVCC DVSS AVCC AVSS RST/NMI System Clock ROSC P1 Hardware Multiplier MPY, MPYS MAC,MACS 55KB Flash 48KB Flash 32KB Flash 5KB RAM 10KB RAM 5KB RAM ADC12 12-Bit 8 Channels <10μs Conv. DAC12 12-Bit 2 Channels Voltage out DMA Controller 3 Channels Watchdog Timer 15/16-Bit Timer_B7 7 CC Reg Shadow Reg Timer_A3 3 CC Reg Test JTAG Emulation Module I/O Port 1/2 16 I/Os, with Interrupt Capability I/O Port 3/4 16 I/Os POR SVS Brownout Comparator A USART0 UART Mode SPI Mode I2C Mode USART1 UART Mode SPI Mode I/O Port 5/6 16 I/Os MDB, 16-Bit MDB, 8 Bit MAB, 16-Bit 8 8 8 8 8 8 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL DESCRIPTION NAME NO. I/O AVCC 64 Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12 and DAC12. AVSS 62 Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12 and DAC12. DVCC 1 Digital supply voltage, positive terminal. Supplies all digital parts. DVSS 63 Digital supply voltage, negative terminal. Supplies all digital parts. P1.0/TACLK 12 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input P1.1/TA0 13 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit P1.2/TA1 14 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 15 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK 16 I/O General-purpose digital I/O pin/SMCLK signal output P1.5/TA0 17 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output P1.6/TA1 18 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output P1.7/TA2 19 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output P2.0/ACLK 20 I/O General-purpose digital I/O pin/ACLK output P2.1/TAINCLK 21 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK P2.2/CAOUT/TA0 22 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL receive P2.3/CA0/TA1 23 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input P2.4/CA1/TA2 24 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input P2.5/Rosc 25 I/O General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency P2.6/ADC12CLK/ DMAE0 26 I/O General-purpose digital I/O pin/conversion clock – 12-bit ADC/DMA channel 0 external trigger P2.7/TA0 27 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output P3.0/STE0 28 I/O General-purpose digital I/O pin/slave transmit enable – USART0/SPI mode P3.1/SIMO0/SDA 29 I/O General-purpose digital I/O pin/slave in/master out of USART0/SPI mode, I2C data − USART0/I2C mode P3.2/SOMI0 30 I/O General-purpose digital I/O pin/slave out/master in of USART0/SPI mode P3.3/UCLK0/SCL 31 I/O General-purpose digital I/O pin/external clock input − USART0/UART or SPI mode, clock output – USART0/SPI mode, I2C clock − USART0/I2C mode P3.4/UTXD0 32 I/O General-purpose digital I/O pin/transmit data out – USART0/UART mode P3.5/URXD0 33 I/O General-purpose digital I/O pin/receive data in – USART0/UART mode P3.6/UTXD1† 34 I/O General-purpose digital I/O pin/transmit data out – USART1/UART mode P3.7/URXD1† 35 I/O General-purpose digital I/O pin/receive data in – USART1/UART mode P4.0/TB0 36 I/O General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output P4.1/TB1 37 I/O General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out1 output P4.2/TB2 38 I/O General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out2 output P4.3/TB3† 39 I/O General-purpose digital I/O pin/Timer_B, capture: CCI3A/B input, compare: Out3 output P4.4/TB4† 40 I/O General-purpose digital I/O pin/Timer_B, capture: CCI4A/B input, compare: Out4 output P4.5/TB5† 41 I/O General-purpose digital I/O pin/Timer_B, capture: CCI5A/B input, compare: Out5 output P4.6/TB6† 42 I/O General-purpose digital I/O pin/Timer_B, capture: CCI6A input, compare: Out6 output P4.7/TBCLK 43 I/O General-purpose digital I/O pin/Timer_B, clock signal TBCLK input P5.0/STE1† 44 I/O General-purpose digital I/O pin/slave transmit enable – USART1/SPI mode P5.1/SIMO1† 45 I/O General-purpose digital I/O pin/slave in/master out of USART1/SPI mode P5.2/SOMI1† 46 I/O General-purpose digital I/O pin/slave out/master in of USART1/SPI mode P5.3/UCLK1† 47 I/O General-purpose digital I/O pin/external clock input – USART1/UART or SPI mode, clock output – USART1/SPI mode † 16x, 161x devices only MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 Terminal Functions (Continued) TERMINAL DESCRIPTION NAME NO. I/O P5.4/MCLK 48 I/O General-purpose digital I/O pin/main system clock MCLK output P5.5/SMCLK 49 I/O General-purpose digital I/O pin/submain system clock SMCLK output P5.6/ACLK 50 I/O General-purpose digital I/O pin/auxiliary clock ACLK output P5.7/TBOUTH/ SVSOUT 51 I/O General-purpose digital I/O pin/switch all PWM digital output ports to high impedance − Timer_B TB0 to TB6/SVS comparator output P6.0/A0 59 I/O General-purpose digital I/O pin/analog input a0 – 12-bit ADC P6.1/A1 60 I/O General-purpose digital I/O pin/analog input a1 – 12-bit ADC P6.2/A2 61 I/O General-purpose digital I/O pin/analog input a2 – 12-bit ADC P6.3/A3 2 I/O General-purpose digital I/O pin/analog input a3 – 12-bit ADC P6.4/A4 3 I/O General-purpose digital I/O pin/analog input a4 – 12-bit ADC P6.5/A5 4 I/O General-purpose digital I/O pin/analog input a5 – 12-bit ADC P6.6/A6/DAC0 5 I/O General-purpose digital I/O pin/analog input a6 – 12-bit ADC/DAC12.0 output P6.7/A7/DAC1/ SVSIN 6 I/O General-purpose digital I/O pin/analog input a7 – 12-bit ADC/DAC12.1 output/SVS input RST/NMI 58 I Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices). TCK 57 I Test clock. TCK is the clock input port for device programming test and bootstrap loader start TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal TMS 56 I Test mode select. TMS is used as an input port for device programming and test. VeREF+ 10 I Input for an external reference voltage VREF+ 7 O Output of positive terminal of the reference voltage in the ADC12 VREF−/VeREF− 11 I Negative terminal for the reference voltage for both sources, the internal reference voltage, or an external applied reference voltage XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 O Output terminal of crystal oscillator XT1 XT2IN 53 I Input port for crystal oscillator XT2. Only standard crystals can be connected. XT2OUT 52 O Output terminal of crystal oscillator XT2 QFN Pad NA NA QFN package pad connection to DVSS recommended (RTD package only) General-Purpose Register Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5 R12 R13 General-Purpose Register General-Purpose Register R6 R7 General-Purpose Register General-Purpose Register R8 R9 General-Purpose Register General-Purpose Register R10 R11 General-Purpose Register General-Purpose Register R14 R15 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; Table 2 shows the address modes. Table 1. Instruction Word Formats Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 −−−> R5 Single operands, destination only e.g., CALL R8 PC −−>(TOS), R8−−> PC Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0 Table 2. Address Mode Descriptions ADDRESS MODE S D SYNTAX EXAMPLE OPERATION Register   MOV Rs,Rd MOV R10,R11 R10 −−> R11 Indexed   MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)−−> M(6+R6) Symbolic (PC relative)   MOV EDE,TONI M(EDE) −−> M(TONI) Absolute   MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT) Indirect  MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6) Indirect autoincrement  MOV @Rn+,Rm MOV @R10+,R11 M(R10) −−> R11 R10 + 2−−> R10 Immediate  MOV #X,TONI MOV #45,TONI #45 −−> M(TONI) NOTE: S = source D = destination MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software:  Active mode AM − All clocks are active  Low-power mode 0 (LPM0) − CPU is disabled − ACLK and SMCLK remain active. MCLK is disabled  Low-power mode 1 (LPM1) − CPU is disabled − ACLK and SMCLK remain active. MCLK is disabled − DCO’s dc generator is disabled if DCO not used in active mode  Low-power mode 2 (LPM2) − CPU is disabled − MCLK and SMCLK are disabled − DCO’s dc generator remains enabled − ACLK remains active  Low-power mode 3 (LPM3) − CPU is disabled − MCLK and SMCLK are disabled − DCO’s dc generator is disabled − ACLK remains active  Low-power mode 4 (LPM4) − CPU is disabled − ACLK is disabled − MCLK and SMCLK are disabled − DCO’s dc generator is disabled − Crystal oscillator is stopped MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External Reset Watchdog Flash memory WDTIFG KEYV (see Note 1) Reset 0FFFEh 15, highest NMI Oscillator Fault Flash memory access violation NMIIFG (see Notes 1 and 3) OFIFG (see Notes 1 and 3) ACCVIFG (see Notes 1 and 3) (Non)maskable (Non)maskable (Non)maskable 0FFFCh 14 Timer_B7 (see Note 5) TBCCR0 CCIFG (see Note 2) Maskable 0FFFAh 13 Timer_B7 (see Note 5) TBCCR1 to TBCCR6 CCIFGs, TBIFG (see Notes 1 and 2) Maskable 0FFF8h 12 Comparator_A CAIFG Maskable 0FFF6h 11 Watchdog timer WDTIFG Maskable 0FFF4h 10 USART0 receive URXIFG0 Maskable 0FFF2h 9 USART0 transmit I2C transmit/receive/others UTXIFG0 I2CIFG (see Note 4) Maskable 0FFF0h 8 ADC12 ADC12IFG (see Notes 1 and 2) Maskable 0FFEEh 7 Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6 Timer_A3 TACCR1 and TACCR2 CCIFGs, TAIFG (see Notes 1 and 2) Maskable 0FFEAh 5 I/O port P1 (eight flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0FFE8h 4 USART1 receive URXIFG1 Maskable 0FFE6h 3 USART1 transmit UTXIFG1 Maskable 0FFE4h 2 I/O port P2 (eight flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0FFE2h 1 DAC12 DMA DAC12_0IFG, DAC12_1IFG DMA0IFG, DMA1IFG, DMA2IFG (see Notes 1 and 2) Maskable 0FFE0h 0, lowest NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module. 3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. 4. I2C interrupt flags located in the module 5. Timer_B7 in MSP430F16x/161x family has 7 CCRs; Timer_B3 in MSP430F15x family has 3 CCRs; in Timer_B3 there are only interrupt flags TBCCR0, 1 and 2 CCIFGs and the interrupt-enable bits TBCCR0, 1 and 2 CCIEs. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 special function registers Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access. interrupt enable 1 and 2 7 6 5 4 0 UTXIE0 OFIE WDTIE 3 2 1 rw-0 rw-0 rw-0 Address 0h URXIE0 ACCVIE NMIIE rw-0 rw-0 rw-0 WDTIE: Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured as general-purpose timer. OFIE: Oscillator fault interrupt enable NMIIE: Nonmaskable interrupt enable ACCVIE: Flash memory access violation interrupt enable URXIE0: USART0: UART and SPI receive-interrupt enable UTXIE0: USART0: UART and SPI transmit-interrupt enable 7 6 5 4 0 UTXIE1 3 2 1 rw-0 rw-0 Address 01h URXIE1 URXIE1†: USART1: UART and SPI receive interrupt enable UTXIE1†: USART1: UART and SPI transmit interrupt enable † URXIE1 and UTXIE1 are not present in MSP430F15x devices. interrupt flag register 1 and 2 7 6 5 4 0 UTXIFG0 OFIFG WDTIFG 3 2 1 rw-0 rw-1 rw-(0) Address 02h URXIFG0 NMIIFG rw-1 rw-0 WDTIFG: Set on watchdog-timer overflow (in watchdog mode) or security key violation Reset on VCC power-on, or a reset condition at the RST/NMI pin in reset mode OFIFG: Flag set on oscillator fault NMIIFG: Set via RST/NMI pin URXIFG0: USART0: UART and SPI receive flag UTXIFG0: USART0: UART and SPI transmit flag 7 6 5 4 0 UTXIFG1 3 2 1 rw-1 rw-0 Address 03h URXIFG1 URXIFG1‡: USART1: UART and SPI receive flag UTXIFG1‡: USART1: UART and SPI transmit flag ‡ URXIFG1 and UTXIFG1 are not present in MSP430F15x devices. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 module enable registers 1 and 2 7 6 5 4 0 UTXE0 3 2 1 rw-0 rw-0 Address 04h URXE0 USPIE0 URXE0: USART0: UART mode receive enable UTXE0: USART0: UART mode transmit enable USPIE0: USART0: SPI mode transmit and receive enable 7 6 5 4 0 UTXE1 3 2 1 rw-0 rw-0 Address 05h URXE1 USPIE1 URXE1†: USART1: UART mode receive enable UTXE1†: USART1: UART mode transmit enable USPIE1†: USART1: SPI mode transmit and receive enable † URXE1, UTXE1, and USPIE1 are not present in MSP430F15x devices. rw-0: Legend: rw: Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset by PUC. SFR Bit Not Present in Device MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 memory organization, MSP430F15x MSP430F155 MSP430F156 MSP430F157 Memory Main: interrupt vector Main: code memory Size Flash Flash 16KB 0FFFFh − 0FFE0h 0FFFFh − 0C000h 24KB 0FFFFh − 0FFE0h 0FFFFh − 0A000h 32KB 0FFFFh − 0FFE0h 0FFFFh − 08000h Information memory Size Flash 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h Boot memory Size ROM 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h RAM Size 512B 03FFh − 0200h 1KB 05FFh − 0200h 1KB 05FFh − 0200h Peripherals 16-bit 8-bit 8-bit SFR 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h 0FFh − 010h 0Fh − 00h memory organization, MSP430F16x MSP430F167 MSP430F168 MSP430F169 Memory Main: interrupt vector Main: code memory Size Flash Flash 32KB 0FFFFh − 0FFE0h 0FFFFh − 08000h 48KB 0FFFFh − 0FFE0h 0FFFFh − 04000h 60KB 0FFFFh − 0FFE0h 0FFFFh − 01100h Information memory Size Flash 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h Boot memory Size ROM 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h RAM Size 1KB 05FFh − 0200h 2KB 09FFh − 0200h 2KB 09FFh − 0200h Peripherals 16-bit 8-bit 8-bit SFR 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h 0FFh − 010h 0Fh − 00h memory organization, MSP430F161x MSP430F1610 MSP430F1611 MSP430F1612 Memory Main: interrupt vector Main: code memory Size Flash Flash 32KB 0FFFFh − 0FFE0h 0FFFFh − 08000h 48KB 0FFFFh − 0FFE0h 0FFFFh − 04000h 55KB 0FFFFh − 0FFE0h 0FFFFh − 02500h RAM (Total) Size 5KB 024FFh − 01100h 10KB 038FFh − 01100h 5KB 024FFh − 01100h Extended Size 3KB 024FFh − 01900h 8KB 038FFh − 01900h 3KB 024FFh − 01900h Mirrored Size 2KB 018FFh − 01100h 2KB 018FFh − 01100h 2KB 018FFh − 01100h Information memory Size Flash 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h 256 Byte 010FFh − 01000h Boot memory Size ROM 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h RAM (mirrored at 018FFh - 01100h) Size 2KB 09FFh − 0200h 2KB 09FFh − 0200h 2KB 09FFh − 0200h Peripherals 16-bit 8-bit 8-bit SFR 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h 0FFh − 010h 0Fh − 00h MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 bootstrap loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089. BSL FUNCTION PM, RTD PACKAGE PINS Data Transmit 13 - P1.1 Data Receive 22 - P2.2 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:  Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size.  Segments 0 to n may be erased in one step, or each segment may be individually erased.  Segments A and B can be erased individually, or as a group with segments 0 to n. Segments A and B are also called information memory.  New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use. Segment 0 w/ Interrupt Vectors Segment 1 Segment 2 Segment n-1 Segment n† Segment A Segment B Main Memory Info Memory 32KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 48KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 08400h 083FFh 08200h 081FFh 08000h 024FFh 01100h 010FFh 01080h 0107Fh 01000h 04400h 043FFh 04200h 041FFh 04000h 038FFh 01100h 010FFh 01080h 0107Fh 01000h RAM (’F161x only) 48KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 60KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 04400h 043FFh 04200h 041FFh 04000h 010FFh 01080h 0107Fh 01000h 01400h 013FFh 01200h 011FFh 01100h 010FFh 01080h 0107Fh 01000h 24KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 32KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 0A400h 0A3FFh 0A200h 0A1FFh 0A000h 010FFh 01080h 0107Fh 01000h 08400h 083FFh 08200h 081FFh 08000h 010FFh 01080h 0107Fh 01000h 16KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 0C400h 0C3FFh 0C200h 0C1FFh 0C000h 010FFh 01080h 0107Fh 01000h MSP430F15x and MSP430F16x MSP430F161x 55KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 02800h 027FFh 02600h 025FFh 02500h 024FFh 01100h 010FFh 01080h 0107Fh 01000h † MSP430F169 and MSP430F1612 flash segment n = 256 bytes. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number SLAU049. DMA controller The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral. oscillator and system clock The clock system in the MSP430F15x and MSP430F16x(x) family of devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The basic clock module provides the following clock signals:  Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.  Main clock (MCLK), the system clock used by the CPU.  Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. brownout, supply voltage supervisor (SVS) The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must insure the default DCO settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min). digital I/O There are six 8-bit I/O ports implemented—ports P1 through P6:  All individual I/O bits are independently programmable.  Any combination of input, output, and interrupt conditions is possible.  Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.  Read/write access to port-control registers is supported by all instructions. watchdog timer The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. hardware multiplier (MSP430F16x/161x only) The multiplication operation is supported by a dedicated peripheral module. The module performs 1616, 168, 816, and 88 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 USART0 The MSP430F15x and the MSP430F16x(x) have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin), asynchronous UART and I2C communication protocols using double-buffered transmit and receive channels. The I2C support is compliant with the Philips I2C specification version 2.1 and supports standard mode (up to 100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit and 10-bit device addressing modes are supported, as well as master and slave modes. The USART0 also supports 16-bit-wide I2C data transfers and has two dedicated DMA channels to maximize bus throughput. Extensive interrupt capability is also given in the I2C mode. USART1 (MSP430F16x/161x only) The MSP430F16x(x) devices have a second hardware universal synchronous/asynchronous receive transmit (USART1) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. With the exception of I2C support, operation of USART1 is identical to USART0. Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. TIMER_A3 SIGNAL CONNECTIONS INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER 12 - P1.0 TACLK TACLK ACLK ACLK Timer NA SMCLK SMCLK 21 - P2.1 TAINCLK INCLK 13 - P1.1 TA0 CCI0A 13 - P1.1 22 - P2.2 TA0 CCI0B CCR0 TA0 17 - P1.5 DVSS GND 27 - P2.7 DVCC VCC 14 - P1.2 TA1 CCI1A 14 - P1.2 CAOUT (internal) CCI1B CCR1 TA1 18 - P1.6 DVSS GND 23 - P2.3 DVCC VCC ADC12 (internal) 15 - P1.3 TA2 CCI2A 15 - P1.3 ACLK (internal) CCI2B CCR2 TA2 19 - P1.7 DVSS GND 24 - P2.4 DVCC VCC Timer_B3 (MSP430F15x only) Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 Timer_B7 (MSP430F16x/161x only) Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. TIMER_B3/B7 SIGNAL CONNECTIONS† INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER 43 - P4.7 TBCLK TBCLK ACLK ACLK Timer NA SMCLK SMCLK 43 - P4.7 TBCLK INCLK 36 - P4.0 TB0 CCI0A 36 - P4.0 36 - P4.0 TB0 CCI0B CCR0 TB0 ADC12 (internal) DVSS GND DVCC VCC 37 - P4.1 TB1 CCI1A 37 - P4.1 37 - P4.1 TB1 CCI1B CCR1 TB1 ADC12 (internal) DVSS GND DVCC VCC 38 - P4.2 TB2 CCI2A 38 - P4.2 38 - P4.2 TB2 CCI2B CCR2 TB2 DVSS GND DVCC VCC 39 - P4.3 TB3 CCI3A 39 - P4.3 39 - P4.3 TB3 CCI3B CCR3 TB3 DVSS GND DVCC VCC 40 - P4.4 TB4 CCI4A 40 - P4.4 40 - P4.4 TB4 CCI4B CCR4 TB4 DVSS GND DVCC VCC 41 - P4.5 TB5 CCI5A 41 - P4.5 41 - P4.5 TB5 CCI5B CCR5 TB5 DVSS GND DVCC VCC 42 - P4.6 TB6 CCI6A 42 - P4.6 ACLK (internal) CCI6B CCR6 TB6 DVSS GND DVCC VCC † Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only). MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Comparator_A The primary function of the comparator_A module is to support precision slope analog−to−digital conversions, battery−voltage supervision, and monitoring of external analog signals. ADC12 The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. DAC12 The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode, and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous operation. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 peripheral file map PERIPHERAL FILE MAP DMA DMA channel 2 transfer size DMA2SZ 01F6h DMA channel 2 destination address DMA2DA 01F4h DMA channel 2 source address DMA2SA 01F2h DMA channel 2 control DMA2CTL 01F0h DMA channel 1 transfer size DMA1SZ 01EEh DMA channel 1 destination address DMA1DA 01ECh DMA channel 1 source address DMA1SA 01EAh DMA channel 1 control DMA1CTL 01E8h DMA channel 0 transfer size DMA0SZ 01E6h DMA channel 0 destination address DMA0DA 01E4h DMA channel 0 source address DMA0SA 01E2h DMA channel 0 control DMA0CTL 01E0h DMA module control 1 DMACTL1 0124h DMA module control 0 DMACTL0 0122h DAC12 DAC12_1 data DAC12_1DAT 01CAh DAC12_1 control DAC12_1CTL 01C2h DAC12_0 data DAC12_0DAT 01C8h DAC12_0 control DAC12_0CTL 01C0h ADC12 Interrupt-vector-word register ADC12IV 01A8h Inerrupt-enable register ADC12IE 01A6h Inerrupt-flag register ADC12IFG 01A4h Control register 1 ADC12CTL1 01A2h Control register 0 ADC12CTL0 01A0h Conversion memory 15 ADC12MEM15 015Eh Conversion memory 14 ADC12MEM14 015Ch Conversion memory 13 ADC12MEM13 015Ah Conversion memory 12 ADC12MEM12 0158h Conversion memory 11 ADC12MEM11 0156h Conversion memory 10 ADC12MEM10 0154h Conversion memory 9 ADC12MEM9 0152h Conversion memory 8 ADC12MEM8 0150h Conversion memory 7 ADC12MEM7 014Eh Conversion memory 6 ADC12MEM6 014Ch Conversion memory 5 ADC12MEM5 014Ah Conversion memory 4 ADC12MEM4 0148h Conversion memory 3 ADC12MEM3 0146h Conversion memory 2 ADC12MEM2 0144h Conversion memory 1 ADC12MEM1 0142h Conversion memory 0 ADC12MEM0 0140h MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) ADC12 ADC memory-control register15 ADC12MCTL15 08Fh (continued) ADC memory-control register14 ADC12MCTL14 08Eh ADC memory-control register13 ADC12MCTL13 08Dh ADC memory-control register12 ADC12MCTL12 08Ch ADC memory-control register11 ADC12MCTL11 08Bh ADC memory-control register10 ADC12MCTL10 08Ah ADC memory-control register9 ADC12MCTL9 089h ADC memory-control register8 ADC12MCTL8 088h ADC memory-control register7 ADC12MCTL7 087h ADC memory-control register6 ADC12MCTL6 086h ADC memory-control register5 ADC12MCTL5 085h ADC memory-control register4 ADC12MCTL4 084h ADC memory-control register3 ADC12MCTL3 083h ADC memory-control register2 ADC12MCTL2 082h ADC memory-control register1 ADC12MCTL1 081h ADC memory-control register0 ADC12MCTL0 080h Timer_B7/ Capture/compare register 6 TBCCR6 019Eh Timer_B3 (see Note 1) Capture/compare register 5 TBCCR5 019Ch Capture/compare register 4 TBCCR4 019Ah Capture/compare register 3 TBCCR3 0198h Capture/compare register 2 TBCCR2 0196h Capture/compare register 1 TBCCR1 0194h Capture/compare register 0 TBCCR0 0192h Timer_B register TBR 0190h Capture/compare control 6 TBCCTL6 018Eh Capture/compare control 5 TBCCTL5 018Ch Capture/compare control 4 TBCCTL4 018Ah Capture/compare control 3 TBCCTL3 0188h Capture/compare control 2 TBCCTL2 0186h Capture/compare control 1 TBCCTL1 0184h Capture/compare control 0 TBCCTL0 0182h Timer_B control TBCTL 0180h Timer_B interrupt vector TBIV 011Eh Timer_A3 Reserved 017Eh Reserved 017Ch Reserved 017Ah Reserved 0178h Capture/compare register 2 TACCR2 0176h Capture/compare register 1 TACCR1 0174h Capture/compare register 0 TACCR0 0172h Timer_A register TAR 0170h Reserved 016Eh Reserved 016Ch Reserved 016Ah Reserved 0168h NOTE 1: Timer_B7 in MSP430F16x/161x family has seven CCRs, Timer_B3 in MSP430F15x family has three CCRs. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) Timer_A3 Capture/compare control 2 TACCTL2 0166h (continued) Capture/compare control 1 TACCTL1 0164h Capture/compare control 0 TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh Hardware Sum extend SUMEXT 013Eh Multiplier (MSP430F16x and Result high word RESHI 013Ch MSP430F161x Result low word RESLO 013Ah only) Second operand OP2 0138h Multiply signed +accumulate/operand1 MACS 0136h Multiply+accumulate/operand1 MAC 0134h Multiply signed/operand1 MPYS 0132h Multiply unsigned/operand1 MPY 0130h Flash Flash control 3 FCTL3 012Ch Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h Watchdog Watchdog Timer control WDTCTL 0120h USART1 Transmit buffer U1TXBUF 07Fh (MSP430F16x and MSP430F161x Receive buffer U1RXBUF 07Eh only) Baud rate U1BR1 07Dh Baud rate U1BR0 07Ch Modulation control U1MCTL 07Bh Receive control U1RCTL 07Ah Transmit control U1TCTL 079h USART control U1CTL 078h USART0 Transmit buffer U0TXBUF 077h (UART or SPI mode) Receive buffer U0RXBUF 076h Baud rate U0BR1 075h Baud rate U0BR0 074h Modulation control U0MCTL 073h Receive control U0RCTL 072h Transmit control U0TCTL 071h USART control U0CTL 070h USART0 2 I2C interrupt vector I2CIV 011Ch (I2C mode) I2C slave address I2CSA 011Ah I2C own address I2COA 0118h I2C data I2CDR 076h I2C SCLL I2CSCLL 075h I2C SCLH I2CSCLH 074h I2C PSC I2CPSC 073h I2C data control I2CDCTL 072h I2C transfer control I2CTCTL 071h USART control U0CTL 070h I2C data count I2CNDAT 052h I2C interrupt flag I2CIFG 051h I2C interrupt enable I2CIE 050h MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) Comparator_A Comparator_A port disable CAPD 05Bh Comparator_A control2 CACTL2 05Ah Comparator_A control1 CACTL1 059h Basic Clock Basic clock system control2 BCSCTL2 058h Basic clock system control1 BCSCTL1 057h DCO clock frequency control DCOCTL 056h BrownOUT, SVS SVS control register (reset by brownout signal) SVSCTL 055h Port P6 Port P6 selection P6SEL 037h Port P6 direction P6DIR 036h Port P6 output P6OUT 035h Port P6 input P6IN 034h Port P5 Port P5 selection P5SEL 033h Port P5 direction P5DIR 032h Port P5 output P5OUT 031h Port P5 input P5IN 030h Port P4 Port P4 selection P4SEL 01Fh Port P4 direction P4DIR 01Eh Port P4 output P4OUT 01Dh Port P4 input P4IN 01Ch Port P3 Port P3 selection P3SEL 01Bh Port P3 direction P3DIR 01Ah Port P3 output P3OUT 019h Port P3 input P3IN 018h Port P2 Port P2 selection P2SEL 02Eh Port P2 interrupt enable P2IE 02Dh Port P2 interrupt-edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h Port P1 Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt-edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h Special Functions SFR module enable 2 ME2 005h SFR module enable 1 ME1 004h SFR interrupt flag2 IFG2 003h SFR interrupt flag1 IFG1 002h SFR interrupt enable2 IE2 001h SFR interrupt enable1 IE1 000h MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA Storage temperature, Tstg: Unprogrammed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C Programmed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 85°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse. recommended operating conditions MIN NOM MAX UNIT Supply voltage during program execution, VCC (AVCC = DVCC = VCC) MSP430F15x/16x/161x 1.8 3.6 V Supply voltage during flash memory programming, VCC (AVCC = DVCC = VCC) MSP430F15x/16x/161x 2.7 3.6 V Supply voltage during program execution, SVS enabled (see Note 1), VCC (AVCC = DVCC = VCC) MSP430F15x/16x/161x 2 3.6 V Supply voltage, VSS (AVSS = DVSS = VSS) 0 0 V Operating free-air temperature range, TA MSP430F15x/16x/161x −40 85 °C LFXT1 t l f f LF selected, XTS=0 Watch crystal 32.768 kHz crystal frequency, f(LFXT1) XT1 selected, XTS=1 Ceramic resonator 450 8000 kHz (see Notes 2 and 3) XT1 selected, XTS=1 Crystal 1000 8000 kHz XT2 crystal frequency f Ceramic resonator 450 8000 frequency, f(XT2) kHz Crystal 1000 8000 Processor frequency (signal MCLK) f VCC = 1.8 V DC 4.15 MCLK), f(System) MHz VCC = 3.6 V DC 8 NOTES: 1. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply voltage. POR is going inactive when the VCC is raised above the minimum supply voltage plus the hysteresis of the SVS circuitry. 2. In LF mode, the LFXT1 oscillator requires a watch crystal. A 5.1-MΩ resistor from XOUT to VSS is recommended when VCC < 2.5 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 4.15 MHz at VCC ≥ 2.2 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 8 MHz at VCC ≥ 2.8 V. 3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal. f (MHz) 1.8 V 2.7 V 3 V 3.6 V ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 4.15 MHz 8.0 MHz Supply Voltage − V Supply voltage range, ’F15x/16x/161x, during flash memory programming Supply voltage range, ’F15x/16x/161x, during program execution Figure 1. Frequency vs Supply Voltage, MSP430F15x/16x/161x MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) MSP430F15x/16x supply current into AVCC + DVCC excluding external current (AVCC = DVCC = VCC) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 1 MHz, T 40°C to 85°C 2.2 V 330 400 A I f(ACLK) = 32,768 Hz XTS=0, SELM=(0,1) TA = −3 V 500 600 μA I(AM) Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 4,096 Hz, T 40°C to 85°C 2.2 V 2.5 7 A f(ACLK) = 4,096 Hz XTS=0, SELM=3 TA = −3 V 9 20 μA I Low-power mode, (LPM0) f(MCLK) = 0 MHz, f(SMCLK) = 1 MHz, f 32 768 Hz T 40°C to 85°C 2.2 V 50 60 I(LPM0) A ( ) ( ) f(ACLK) = 32,768 XTS=0, SELM=(0,1) (see Note 1) TA = −3 V 75 90 μA I Low-power mode, (LPM2), f f 0 MHz T 40°C to 85°C 2.2 V 11 14 I(LPM2) f(MCLK) = f(SMCLK) = MHz, A f(ACLK) = 32.768 Hz, SCG0 = 0 TA = −3 V 17 22 μA TA = −40°C 1.1 1.6 Low-power mode (LPM3) TA = 25°C 2.2 V 1.1 1.6 I mode, f(MCLK) = f(SMCLK) = 0 MHz, TA = 85°C 2.2 3.0 I(LPM3) A f(ACLK) = 32,768 Hz, SCG0 = 1 ( Nt 2) TA = −40°C 2.2 2.8 μA (see Note TA = 25°C 3 V 2.0 2.6 TA = 85°C 3.0 4.3 Low-power mode, (LPM4) TA = −40°C 0.1 0.5 I(LPM4) f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz, TA = 25°C 2.2V / 3 V 0.2 0.5 μA f(ACLK) = 0 Hz, SCG0 = 1 TA = 85°C 1.3 2.5 NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. 2. WDT is clocked by f(ACLK) = 32,768 Hz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current consumption in LPM2 and LPM3 are measured with ACLK selected. Current consumption of active mode versus system frequency I(AM) = I(AM) [1 MHz] × f(System) [MHz] Current consumption of active mode versus supply voltage I(AM) = I(AM) [3 V] + 210 μA/V × (VCC – 3 V) MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) MSP430F161x supply current into AVCC + DVCC excluding external current (AVCC = DVCC = VCC) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 1 MHz, T 40°C to 85°C 2.2 V 330 400 A I f(ACLK) = 32,768 Hz XTS=0, SELM=(0,1) TA = −3 V 500 600 μA I(AM) Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 4,096 Hz, T 40°C to 85°C 2.2 V 2.5 7 A f(ACLK) = 4,096 Hz XTS=0, SELM=3 TA = −3 V 9 20 μA I Low-power mode, (LPM0) f(MCLK) = 0 MHz, f(SMCLK) = 1 MHz, f 32 768 Hz T 40°C to 85°C 2.2 V 50 60 I(LPM0) A ( ) ( ) f(ACLK) = 32,768 XTS=0, SELM=(0,1) (see Note 1) TA = −3 V 75 95 μA I Low-power mode, (LPM2), f f 0 MHz T 40°C to 85°C 2.2 V 11 14 I(LPM2) f(MCLK) = f(SMCLK) = MHz, A f(ACLK) = 32.768 Hz, SCG0 = 0 TA = −3 V 17 22 μA TA = −40°C 1.3 1.6 Low-power mode (LPM3) TA = 25°C 2.2 V 1.3 1.6 I mode, f(MCLK) = f(SMCLK) = 0 MHz, TA = 85°C 3.0 6.0 I(LPM3) A f(ACLK) = 32,768 Hz, SCG0 = 1 ( Nt 2) TA = −40°C 2.6 3.0 μA (see Note TA = 25°C 3 V 2.6 3.0 TA = 85°C 4.4 8.0 Low-power mode, (LPM4) TA = −40°C 0.2 0.5 I(LPM4) f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz, TA = 25°C 2.2V / 3 V 0.2 0.5 μA f(ACLK) = 0 Hz, SCG0 = 1 TA = 85°C 2.0 5.0 NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. 2. WDT is clocked by f(ACLK) = 32,768 Hz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current consumption in LPM2 and LPM3 are measured with ACLK selected. Current consumption of active mode versus system frequency I(AM) = I(AM) [1 MHz] × f(System) [MHz] Current consumption of active mode versus supply voltage I(AM) = I(AM) [3 V] + 210 μA/V × (VCC – 3 V) MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs − ports P1, P2, P3, P4, P5, P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI) PARAMETER VCC MIN TYP MAX UNIT V Positive going input threshold voltage 2.2 V 1.1 1.5 VIT+ Positive-V 3 V 1.5 1.98 V Negative going input threshold voltage 2.2 V 0.4 0.9 VIT− Negative-V 3 V 0.9 1.3 V Input voltage hysteresis (V V ) 2.2 V 0.3 1.1 Vhys VIT+ − VIT−) V 3 V 0.5 1 inputs Px.x, TAx, TBx PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT t External interrupt timing Port P1, P2: P1.x to P2.x, external trigger 2.2 V 62 t(int) ns signal for the interrupt flag (see Note 1) 3 V 50 TA0, TA1, TA2 2.2 V 62 t(cap) Timer_A, Timer_B capture timing TB0, TB1, TB2, TB3, TB4, TB5, TB6 (see Note 2) 3 V 50 ns f(TAext) Timer_A, Timer_B clock frequency TACLK TBCLK INCLK: t = t 2.2 V 8 MHz f(TBext) externally applied to pin TACLK, TBCLK, t(H) t(L) 3 V 10 f(TAint) Timer A Timer B clock frequency SMCLK or ACLK signal selected 2.2 V 8 MHz f(TBint) Timer_A, Timer_3 V 10 NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals shorter than t(int). 2. Seven capture/compare registers in ’F16x/161x and three capture/compare registers in ’F15x. leakage current − ports P1, P2, P3, P4, P5, P6 (see Note 1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Ilkg(Px.y) Leakage current Port Px V(Px.y) (see Note 2) 2.2 V/3 V ±50 nA NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The port pin must be selected as input. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − ports P1, P2, P3, P4, P5, P6 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOH(max) = −1.5 mA, VCC = 2.2 V, See Note 1 VCC−0.25 VCC V High level output voltage IOH(max) = −6 mA, VCC = 2.2 V, See Note 2 VCC−0.6 VCC VOH High-V IOH(max) = −1.5 mA, VCC = 3 V, See Note 1 VCC−0.25 VCC IOH(max) = −6 mA, VCC = 3 V, See Note 2 VCC−0.6 VCC IOL(max) = 1.5 mA, VCC = 2.2 V, See Note 1 VSS VSS+0.25 V Low level output voltage IOL(max) = 6 mA, VCC = 2.2 V, See Note 2 VSS VSS+0.6 VOL Low-V IOL(max) = 1.5 mA, VCC = 3 V, See Note 1 VSS VSS+0.25 IOL(max) = 6 mA, VCC = 3 V, See Note 2 VSS VSS+0.6 NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum specified voltage drop. 2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum specified voltage drop. output frequency PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f (1 ≤ x ≤ 6 0≤ y ≤ 7) CL = 20 pF, f(Px.y) 6, 0 ≤ V 2 2 V / 3 V DC f MHz IL = ±1.5 mA VCC = 2.2 fSystem f(ACLK) f P2.0/ACLK, P5.6/ACLK P5 4/MCLK C 20 pF V 2 2 V / 3 V fSystem MHz f(MCLK) f(SMCLK) P5.4/MCLK, P1.4/SMCLK, P5.5/SMCLK CL = VCC = 2.2 P1.0/TACLK f(ACLK) = f(LFXT1) = f(XT1) 40% 60% CL = 20 pF f(ACLK) = f(LFXT1) = f(LF) 30% 70% VCC = 2.2 V / 3 V f(ACLK) = f(LFXT1) 50% P1.1/TA0/MCLK, f(MCLK) = f(XT1) 40% 60% t(Xdc) Duty cycle of output frequency CL = 20 pF, VCC = 2.2 V / 3 V f(MCLK) = f(DCOCLK) 50%− 15 ns 50% 50%+ 15 ns P1.4/TBCLK/SMCLK, f(SMCLK) = f(XT2) 40% 60% CL = 20 pF, VCC = 2.2 V / 3 V f(SMCLK) = f(DCOCLK) 50%− 15 ns 50% 50%+ 15 ns MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − ports P1, P2, P3, P4, P5, P6 (continued) Figure 2 VOL − Low-Level Output Voltage − V 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 VCC = 2.2 V P3.5 TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TA = 25°C TA = 85°C IOL − Low-Level Output Current − mA Figure 3 VOL − Low-Level Output Voltage − V 0 10 20 30 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VCC = 3 V P3.5 TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TA = 25°C TA = 85°C IOL − Low-Level Output Current − mA Figure 4 VOH − High-Level Output Voltage − V −25 −20 −15 −10 −5 0 0.0 0.5 1.0 1.5 2.0 2.5 VCC = 2.2 V P3.5 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE TA = 25°C TA = 85°C IOH− High-Level Output Current − mA Figure 5 VOH − High-Level Output Voltage − V −45 −35 −25 −15 −5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VCC = 3 V P3.5 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE TA = 25°C TA = 85°C IOH− High-Level Output Current − mA MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) wake-up LPM3 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(LPM3) Delay time VCC = 2.2 V/3 V, fDCO ≥ fDCO43 6 μs RAM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRAMh See Note 1 CPU HALTED 1.6 V NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution should take place during this supply voltage condition. Comparator_A (see Note 1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT I CAON=1 CARSEL=0 CAREF=0 2.2 V 25 40 I(DD) 1, 0, μA 3 V 45 60 I CAON=1, CARSEL=0, CAREF 1/2/3 no load at 2.2 V 30 50 I(Refladder/Refdiode) CAREF=3, μA P2.3/CA0/TA1 and P2.4/CA1/TA2 3 V 45 71 V(IC) Common-mode input voltage CAON =1 2.2 V/3 V 0 VCC−1 V V(Ref025) Voltage @ 0.25 VCC node VCC PCA0=1, CARSEL=1, CAREF=1, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 2.2 V/3 V 0.23 0.24 0.25 V(Ref050) Voltage @ 0.5VCC node VCC PCA0=1, CARSEL=1, CAREF=2, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 2.2 V/3 V 0.47 0.48 0.5 V (see Figure 6 and Figure 7) PCA0=1, CARSEL=1, CAREF=3, no load at P2 3/CA0/TA1 and 2.2 V 390 480 540 V(RefVT) P2.3/mV P2.4/CA1/TA2 TA = 85°C 3 V 400 490 550 V(offset) Offset voltage See Note 2 2.2 V/3 V −30 30 mV Vhys Input hysteresis CAON=1 2.2 V/3 V 0 0.7 1.4 mV TA = 25°C, Overdrive 10 mV, 2.2 V 130 210 300 ns t 25 Without filter: CAF=0 3 V 80 150 240 t(response LH) TA = 25°C, Overdrive 10 mV, 2.2 V 1.4 1.9 3.4 μs 25 With filter: CAF=1 3 V 0.9 1.5 2.6 TA = 25°C, Overdrive 10 mV, 2.2 V 130 210 300 ns t 25 Without filter: CAF=0 3 V 80 150 240 t(response HL) TA = 25°C, Overdrive 10 mV, 2.2 V 1.4 1.9 3.4 μs 25 With filter: CAF=1 3 V 0.9 1.5 2.6 NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) TA − Free-Air Temperature − °C 400 450 500 550 600 650 −45 −25 −5 15 35 55 75 95 VCC = 3 V Figure 6. V(RefVT) vs Temperature, VCC = 3 V V(REFVT) − Reference Volts −mV Typical Figure 7. V(RefVT) vs Temperature, VCC = 2.2 V TA − Free-Air Temperature − °C 400 450 500 550 600 650 −45 −25 −5 15 35 55 75 95 VCC = 2.2 V V(REFVT) − Reference Volts −mV Typical _ + CAON 0 1 V+ 0 1 CAF Low Pass Filter τ ≈ 2.0 μs To Internal Modules Set CAIFG Flag CAOUT V− VCC 1 0 V 0 Figure 8. Block Diagram of Comparator_A Module Overdrive VCAOUT V+ t(response) V− 400 mV Figure 9. Overdrive Definition MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) POR/brownout reset (BOR) (see Notes 1 and 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(BOR) 2000 μs VCC(Start) dVCC/dt ≤ 3 V/s (see Figure 10) 0.7 × V(B_IT−) V V(B_IT−) Brownout dVCC/dt ≤ 3 V/s (see Figure 10 through Figure 12) 1.71 V Vhys(B_IT−) dVCC/dt ≤ 3 V/s (see Figure 10) 70 130 180 mV t(reset) Pulse length needed at RST/NMI pin to accepted reset internally, VCC = 2.2 V/3 V 2 μs NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT−) + Vhys(B_IT−) is ≤ 1.8 V. 2. During power up, the CPU begins code execution following a period of tBOR(delay) after VCC = V(B_IT−) + Vhys(B_IT−). The default DCO settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. See the MSP430x1xx Family User’s Guide (SLAU049) for more information on the brownout/SVS circuit. typical characteristics 0 1 t d(BOR) VCC V(B_IT−) Vhys(B_IT−) VCC(Start) BOR Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 typical characteristics (continued) VCC(min) VCC 3 V tpw 0 0.5 1 1.5 2 0.001 1 1000 Vcc = 3 V typical conditions 1 ns 1 ns tpw − Pulse Width − μs VCC(min)− V tpw − Pulse Width − μs Figure 11. VCC(min) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 0 0.5 1 1.5 2 Vcc = 3 V typical conditions VCC(min) tpw tpw − Pulse Width − μs VCC(min)− V 3 V 0.001 1 1000 tf tr tpw − Pulse Width − μs tf = tr Figure 12. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) SVS (supply voltage supervisor/monitor) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT t dVCC/dt > 30 V/ms (see Figure 13) 5 150 t(SVSR) μs dVCC/dt ≤ 30 V/ms 2000 td(SVSon) SVSON, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V 150 300 μs tsettle VLD ≠ 0‡ 12 μs V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 13) 1.55 1.7 V VLD = 1 70 120 155 mV Vhys(SVS_IT−) VCC/dt ≤ 3 V/s (see Figure 13) VLD = 2 to 14 V(SVS_IT−) x 0.004 V(SVS_IT−) x 0.008 VCC/dt ≤ 3 V/s (see Figure 13), External voltage applied on A7 VLD = 15 4.4 10.4 mV VLD = 1 1.8 1.9 2.05 VLD = 2 1.94 2.1 2.25 VLD = 3 2.05 2.2 2.37 VLD = 4 2.14 2.3 2.48 VLD = 5 2.24 2.4 2.6 VLD = 6 2.33 2.5 2.71 VCC/dt ≤ 3 V/s (see Figure 13 and Figure 14) VLD = 7 2.46 2.65 2.86 V(SVS IT ) VLD = 8 2.58 2.8 3 SVS_IT−) V VLD = 9 2.69 2.9 3.13 VLD = 10 2.83 3.05 3.29 VLD = 11 2.94 3.2 3.42 VLD = 12 3.11 3.35 3.61† VLD = 13 3.24 3.5 3.76† VLD = 14 3.43 3.7† 3.99† VCC/dt ≤ 3 V/s (see Figure 13 and Figure 14), External voltage applied on A7 VLD = 15 1.1 1.2 1.3 ICC(SVS) (see Note 1) VLD ≠ 0, VCC = 2.2 V/3 V 10 15 μA † The recommended operating voltage range is limited to 3.6 V. ‡ tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV. NOTE 1: The current consumption of the SVS module is not included in the ICC current consumption data. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 typical characteristics VCC(start) AVCC V(B_IT−) Brownout Region V(SVSstart) V(SVS_IT−) Software sets VLD >0: SVS is active td(SVSR) undefined Vhys(SVS_IT−) 0 1 td(BOR) Brownout 0 1 td(SVSon) td(BOR) 0 1 Set POR Brownout Region SVS Circuit is Active From VLD > to VCC < V(B_IT−) SVS out Vhys(B_IT−) Figure 13. SVS Reset (SVSR) vs Supply Voltage 0 0.5 1 1.5 2 VCC VCC 1 ns 1 ns VCC(min) tpw tpw − Pulse Width − μs VCC(min)− V 3 V 1 10 1000 tf tr t − Pulse Width − μs 100 tpw 3 V tf = tr Rectangular Drop Triangular Drop VCC(min) Figure 14. VCC(min): Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1) MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) DCO (see Note 1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT f R 0 DCO 3 MOD 0 DCOR 0 T 25°C 2.2 V 0.08 0.12 0.15 f(DCO03) Rsel = 0, = 3, = 0, = 0, TA = MHz 3 V 0.08 0.13 0.16 f R 1 DCO 3 MOD 0 DCOR 0 T 25°C 2.2 V 0.14 0.19 0.23 f(DCO13) Rsel = 1, = 3, = 0, = 0, TA = MHz 3 V 0.14 0.18 0.22 f R 2 DCO 3 MOD 0 DCOR 0 T 25°C 2.2 V 0.22 0.30 0.36 f(DCO23) Rsel = 2, = 3, = 0, = 0, TA = MHz 3 V 0.22 0.28 0.34 f R 3 DCO 3 MOD 0 DCOR 0 T 25°C 2.2 V 0.37 0.49 0.59 f(DCO33) Rsel = 3, = 3, = 0, = 0, TA = MHz 3 V 0.37 0.47 0.56 f R 4 DCO 3 MOD 0 DCOR 0 T 25°C 2.2 V 0.61 0.77 0.93 f(DCO43) Rsel = 4, = 3, = 0, = 0, TA = MHz 3 V 0.61 0.75 0.90 f R 5 DCO 3 MOD 0 DCOR 0 T 25°C 2.2 V 1 1.2 1.5 f(DCO53) Rsel = 5, = 3, = 0, = 0, TA = MHz 3 V 1 1.3 1.5 f R 6 DCO 3 MOD 0 DCOR 0 T 25°C 2.2 V 1.6 1.9 2.2 f(DCO63) Rsel = 6, = 3, = 0, = 0, TA = MHz 3 V 1.69 2.0 2.29 f R 7 DCO 3 MOD 0 DCOR 0 T 25°C 2.2 V 2.4 2.9 3.4 f(DCO73) Rsel = 7, = 3, = 0, = 0, TA = MHz 3 V 2.7 3.2 3.65 f(DCO47) Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C 2.2 V/3 V fDCO40 × 1.7 fDCO40 × 2.1 fDCO40 × 2.5 MHz f R 7 DCO 7 MOD 0 DCOR 0 T 25°C 2.2 V 4 4.5 4.9 f(DCO77) Rsel = 7, = 7, = 0, = 0, TA = MHz 3 V 4.4 4.9 5.4 SRsel SR = fRsel+1 / fRsel 2.2 V/3 V 1.35 1.65 2 SDCO SDCO = f(DCO+1) / f(DCO) 2.2 V/3 V 1.07 1.12 1.16 D Temperature drift R 4 DCO 3 MOD 0 (see Note 2) 2.2 V −0.31 −0.36 −0.40 Dt drift, Rsel = 4, = 3, = %/°C 3 V −0.33 −0.38 −0.43 DV Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0 (see Note 2) 2.2 V/3 V 0 5 10 %/V NOTES: 1. The DCO frequency may not exceed the maximum system frequency defined by parameter processor frequency, f(System). 2. This parameter is not production tested. 2.2 3 fDCO_0 Max Min ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ Max Min fDCO_7 0 1 2 3 4 5 6 7 DCO f DCOCLK 1 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ VCC − V Frequency Variance Figure 15. DCO Characteristics MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) main DCO characteristics  Individual devices have a minimum and maximum operation frequency. The specified parameters for f(DCOx0) to f(DCOx7) are valid for all devices.  All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.  DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO.  Modulation control bits MOD0 to MOD4 select how often f(DCO+1) is used within the period of 32 DCOCLK cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to: faverage  32f(DCO) f(DCO1) MODf(DCO) (32MOD)f(DCO1) DCO when using ROSC (see Note 1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT f DCO output frequency Rsel = 4, DCO = 3, MOD = 0, DCOR = 1, 2.2 V 1.8±15% MHz fDCO, TA = 25°C 3 V 1.95±15% MHz Dt, Temperature drift Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 2.2 V/3 V ±0.1 %/°C Dv, Drift with VCC variation Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 2.2 V/3 V 10 %/V NOTES: 1. ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C. crystal oscillator, LFXT1 oscillator (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT C Integrated input capacitance XTS=0; LF oscillator selected, VCC = 2.2 V/3 V 12 CXIN pF XTS=1; XT1 oscillator selected, VCC = 2.2 V/3 V 2 C Integrated output capacitance XTS=0; LF oscillator selected, VCC = 2.2 V/3 V 12 CXOUT pF XTS=1; XT1 oscillator selected, VCC = 2.2 V/3 V 2 VIL I t l l t XIN VCC = 2.2 V/3 V ( N 2) XTS = 0 or 1 XT1 or LF modes VSS 0.2 × VCC V V Input levels at CC see Note XTS = 0, LF mode 0.9 × VCC VCC VIH XTS = 1, XT1 mode 0.8 × VCC VCC NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator. crystal oscillator, XT2 oscillator (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CXIN Integrated input capacitance VCC = 2.2 V/3 V 2 pF CXOUT Integrated output capacitance VCC = 2.2 V/3 V 2 pF VIL Input levels at XIN V = 2 2 V/3 V (see Note 2) VSS 0.2 × VCC V VIH VCC 2.2 0.8 × VCC VCC V NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator. USART0, USART1 (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t( ) USART0/USART1: deglitch time VCC = 2.2 V 200 430 800 τ) ns VCC = 3 V 150 280 500 NOTE 1: The signal applied to the USART0/USART1 receive signal/terminal (URXD0/1) should meet the timing requirements of t(τ) to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD0/1 line. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, power supply and input range conditions (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AVCC Analog supply voltage AVCC and DVCC are connected together AVSS and DVSS are connected together V(AVSS) = V(DVSS) = 0 V 2.2 3.6 V V(P6.x/Ax) Analog input voltage range (see Note 2) All P6.0/A0 to P6.7/A7 terminals. Analog inputs selected in ADC12MCTLx register and P6Sel.x=1 0 ≤ x ≤ 7; V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC) 0 VAVCC V I Operating supply current into AV terminal fADC12CLK = 5.0 MHz ADC12ON 1 REFON 0 2.2 V 0.65 1.3 IADC12 AVCC mA (see Note 3) = 1, = SHT0=0, SHT1=0, ADC12DIV=0 3 V 0.8 1.6 I Operating supply current i t AV t i l fADC12CLK = 5.0 MHz ADC12ON = 0, REFON = 1, REF2_5V = 1 3 V 0.5 0.8 mA IREF+ into AVCC terminal (see Note 4) fADC12CLK = 5.0 MHz ADC12ON 0 2.2 V 0.5 0.8 mA = 0, REFON = 1, REF2_5V = 0 3 V 0.5 0.8 CI † Input capacitance Only one terminal can be selected at one time, P6.x/Ax 2.2 V 40 pF RI † Input MUX ON resistance 0V ≤ VAx ≤ VAVCC 3 V 2000 Ω † Not production tested, limits verified by design NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter. 2. The analog input voltage range must be within the selected reference voltage range VR+ to VR− for valid conversion results. 3. The internal reference supply current is not included in current consumption parameter IADC12. 4. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion. 12-bit ADC, external reference (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VeREF+ Positive external reference voltage input VeREF+ > VREF−/VeREF− (see Note 2) 1.4 VAVCC V VREF− /VeREF− Negative external reference voltage input VeREF+ > VREF−/VeREF− (see Note 3) 0 1.2 V (VeREF+ − VREF−/VeREF−) Differential external reference voltage input VeREF+ > VREF−/VeREF− (see Note 4) 1.4 VAVCC V IVeREF+ Static input current 0V ≤VeREF+ ≤ VAVCC 2.2 V/3 V ±1 μA IVREF−/VeREF− Static input current 0V ≤ VeREF− ≤ VAVCC 2.2 V/3 V ±1 μA NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. 2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. 3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. 4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, built-in reference PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V built-REF2_5V = 1 for 2.5 V IVREF+max ≤ IVREF+≤ IVREF+min VCC = 3 V 2.4 2.5 2.6 VREF+ V Positive built in reference voltage output REF2_5V = 0 for 1.5 V IVREF+max ≤ IVREF+≤ IVREF+min VCC = 2.2 V/3 V 1.44 1.5 1.56 AVCC minimum voltage, REF2_5V = 0, IVREF+max ≤ IVREF+≤ IVREF+min 2.2 AVCC(min) Positive built-in reference REF2_5V = 1, −0.5mA ≤ IVREF+≤ IVREF+min 2.8 V active REF2_5V = 1, −1mA ≤ IVREF+≤ IVREF+min 2.9 I Load current out of VREF+ VCC = 2.2 V 0.01 −0.5 IVREF+ mA terminal VCC = 3 V 0.01 −1 IVREF+ = 500 μA +/− 100 μA Analog input voltage 0 75 V VCC = 2.2 V ±2 LSB I Load-current regulation ~0.75 V, REF2_5V = 0 VCC = 3 V ±2 IL(VREF)+ † Load VREF+ terminal IVREF+ = 500 μA ± 100 μA Analog input voltage ~1.25 V, REF2_5V = 1 VCC = 3 V ±2 LSB I Load current regulation IVREF+ =100 μA → 900 μA, IDL(VREF) + C 5 μF ax 0 5 x V V 3 V 20 ns ‡ VREF+ terminal CVREF+=μF, ~0.5 VREF+ , Error of conversion result ≤ 1 LSB VCC = CVREF+ Capacitance at pin VREF+ (see Note 1) REFON =1, 0 mA ≤ IVREF+ ≤ IVREF+max VCC = 2.2 V/3 V 5 10 μF TREF+ † Temperature coefficient of built-in reference IVREF+ is a constant in the range of 0 mA ≤ IVREF+ ≤ 1 mA VCC = 2.2 V/3 V ±100 ppm/°C tREFON † Settle time of internal reference voltage (see Figure 16 and Note 2) IVREF+ = 0.5 mA, CVREF+ = 10 μF, VREF+ = 1.5 V, VAVCC = 2.2 V 17 ms † Not production tested, limits characterized ‡ Not production tested, limits verified by design NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two capacitors between pins VREF+ and AVSS and VREF−/VeREF− and AVSS: 10 μF tantalum and 100 nF ceramic. 2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external capacitive load. CVREF+ 1 μF 0 1 ms 10 ms 100 ms tREFON tREFON ≈ .66 x CVREF+ [ms] with CVREF+ in μF 100 μF 10 μF Figure 16. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+ MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41 + − 10 μF 100 nF AVSS MSP430F15x MSP430F16x + − + − 10 μF 100 nF 10 μF 100 nF AVCC 10 μF 100 nF DVSS From DVCC Power Supply Apply External Reference + − Apply External Reference [VeREF+] or Use Internal Reference [VREF+] VREF+ or VeREF+ VREF−/VeREF− MSP430F161x Figure 17. Supply Voltage and Reference Voltage Design VREF−/VeREF− External Supply + − 10 μF 100 nF AVSS MSP430F15x MSP430F16x + − 10 μF 100 nF AVCC 10 μF 100 nF DVSS From DVCC Power Supply + − Apply External Reference [VeREF+] or Use Internal Reference [VREF+] VREF+ or VeREF+ Reference Is Internally VREF−/VeREF− Switched to AVSS MSP430F161x Figure 18. Supply Voltage and Reference Voltage Design VREF−/VeREF− = AVSS, Internally Connected MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, timing parameters PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fADC12CLK For specified performance of ADC12 linearity parameters 2.2V/3 V 0.45 5 6.3 MHz fADC12OSC Internal ADC12 oscillator ADC12DIV=0, fADC12CLK=fADC12OSC 2.2 V/ 3 V 3.7 5 6.3 MHz t Conversion time CVREF+ ≥ 5 μF, Internal oscillator, fADC12OSC = 3.7 MHz to 6.3 MHz 2.2 V/ 3 V 2.06 3.51 μs tCONVERT External fADC12CLK from ACLK, MCLK or SMCLK: ADC12SSEL ≠ 0 13×ADC12DIV× 1/fADC12CLK μs tADC12ON ‡ Turn on settling time of the ADC (see Note 1) 100 ns t ‡ Sampling time RS = 400 Ω, RI = 1000 Ω, C 30 pF 3 V 1220 tSample ns CI = τ = [RS + RI] x CI;(see Note 2) 2.2 V 1400 † Not production tested, limits characterized ‡ Not production tested, limits verified by design NOTES: 1. The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already settled. 2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB: tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance. 12-bit ADC, linearity parameters PARAMETER TEST CONDITIONS MIN TYP MAX UNIT E Integral linearity error 1.4 V ≤ (VeREF+ − VREF−/VeREF−) min ≤ 1.6 V 2 2 V/3 V ±2 EI LSB 1.6 V < (VeREF+ − VREF−/VeREF−) min ≤ [VAVCC] 2.2 ±1.7 ED Differential linearity error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−), CVREF+ = 10 μF (tantalum) and 100 nF (ceramic) 2.2 V/3 V ±1 LSB EO Offset error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−), Internal impedance of source RS < 100 Ω, CVREF+ = 10 μF (tantalum) and 100 nF (ceramic) 2.2 V/3 V ±2 ±4 LSB EG Gain error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−), CVREF+ = 10 μF (tantalum) and 100 nF (ceramic) 2.2 V/3 V ±1.1 ±2 LSB ET Total unadjusted error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−), CVREF+ = 10 μF (tantalum) and 100 nF (ceramic) 2.2 V/3 V ±2 ±5 LSB MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 43 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, temperature sensor and built-in VMID PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I Operating supply current into REFON = 0, INCH = 0Ah, 2.2 V 40 120 ISENSOR A AVCC terminal (see Note 1) ADC12ON=NA, TA = 25C 3 V 60 160 μA V (see Note 2) ADC12ON = 1, INCH = 0Ah, 2.2 V 986 VSENSOR mV † TA = 0°C 3 V 986 TC † ADC12ON 1 INCH 0Ah 2.2 V 3.55 3.55±3% TCSENSOR mV/°C = 1, = 3 V 3.55 3.55±3% t Sample time required if channel ADC12ON = 1, INCH = 0Ah, Error of conversion result ≤ 1 2.2 V 30 tSENSOR(sample) s † 10 is selected (see Note 3) LSB 3 V 30 μs I Current into divider at channel 11 ADC12ON 1 INCH 0Bh 2.2 V NA IVMID A (see Note 4) = 1, = 0Bh, 3 V NA μA V AV divider at channel 11 ADC12ON = 1, INCH = 0Bh, 2.2 V 1.1 1.1±0.04 VMID AVCC V VMID is ~0.5 x VAVCC 3 V 1.5 1.50±0.04 t Sample time required if channel ADC12ON = 1, INCH = 0Bh, Error of conversion result ≤ 1 2.2 V 1400 tVMID(sample) ns 11 is selected (see Note 5) LSB 3 V 1220 † Not production tested, limits characterized NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal is high). When REFON = 1, ISENSOR is already included in IREF+. 2. The temperature sensor offset can be as much as ±20C. A single-point calibration is recommended in order to minimize the offset error of the built-in temperature sensor. 3. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on) 4. No additional current is needed. The VMID is used during sampling. 5. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. 12-bit DAC, supply specifications PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT AVCC Analog supply voltage AVCC = DVCC, AVSS = DVSS =0 V 2.20 3.60 V DAC12AMPx=2, DAC12IR=0, DAC12_xDAT=0800h 2.2V/3V 50 110 I Supply Current: DAC12AMPx=2, DAC12IR=1, DAC12_xDAT=0800h , VeREF+=VREF+= AVCC 2.2V/3V 50 110 IDD Single DAC Channel A (see Notes 1 and 2) DAC12AMPx=5, DAC12IR=1, DAC12_xDAT=0800h, VeREF+=VREF+= AVCC 2.2V/3V 200 440 μA DAC12AMPx=7, DAC12IR=1, DAC12_xDAT=0800h, VeREF+=VREF+= AVCC 2.2V/3V 700 1500 PSRR Power supply DAC12_xDAT = 800h, VREF = 1.5 V ΔAVCC = 100mV 2.2V rejection ratio 70 dB (see Notes 3 and 4) DAC12_xDAT = 800h, VREF = 1.5 V or 2.5 V ΔAVCC = 100mV 3V NOTES: 1. No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly. 2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications. 3. PSRR = 20*log{ΔAVCC/ΔVDAC12_xOUT}. 4. VREF is applied externally. The internal reference is not used. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, linearity specifications (see Figure 19) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Resolution (12-bit Monotonic) 12 bits INL Vref = 1.5 V DAC12AMPx = 7, DAC12IR = 1 2.2V ±2 0 ±8 0 LSB Integral nonlinearity (see Note 1) Vref = 2.5 V DAC12AMPx = 7, DAC12IR = 1 3V 2.0 8.0 DNL Vref = 1.5 V DAC12AMPx = 7, DAC12IR = 1 2.2V ±0 4 ±1 0 LSB Differential nonlinearity (see Note 1) Vref = 2.5 V DAC12AMPx = 7, DAC12IR = 1 3V 0.4 1.0 Offset voltage w/o Vref = 1.5 V DAC12AMPx = 7, DAC12IR = 1 2.2V ±21 EO calibration (see Notes 1, 2) Vref = 2.5 V DAC12AMPx = 7, DAC12IR = 1 3V mV Offset voltage with Vref = 1.5 V DAC12AMPx = 7, DAC12IR = 1 2.2V ±2 5 calibration (see Notes 1, 2) Vref = 2.5 V DAC12AMPx = 7, DAC12IR = 1 3V 2.5 dE(O)/dT Offset error temperature coefficient (see Note 1) 2.2V/3V 30 uV/C E Gain error (see Note 1) VREF = 1.5 V 2.2V EG ±3 50 % FSR VREF = 2.5 V 3V 3.50 dE(G)/dT Gain temperature coefficient (see Note 1) 2.2V/3V 10 ppm of FSR/°C Time for offset calibration DAC12AMPx=2 2.2V/3V 100 tOffset_Cal DAC12AMPx=3,5 2.2V/3V 32 ms (see Note 3) DAC12AMPx=4,6,7 2.2V/3V 6 NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and “b” of the first order equation: y = a + b*x. VDAC12_xOUT = EO + (1 + EG) * (VeREF+/4095) * DAC12_xDAT, DAC12IR = 1. 2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON 3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx ={0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may effect accuracy and is not recommended. Positive Negative VR+ Offset Error Gain Error DAC Code DAC VOUT Ideal transfer function RLoad = AVCC CLoad = 100pF 2 DAC Output Figure 19. Linearity Test Load Conditions and Gain/Offset Definition MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 45 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, linearity specifications (continued) DAC12_xDAT − Digital Code −4 −3 −2 −1 0 1 2 3 4 0 512 1024 1536 2048 2560 3072 3584 VCC = 2.2 V, VREF = 1.5V DAC12AMPx = 7 DAC12IR = 1 TYPICAL INL ERROR vs DIGITAL INPUT DATA 4095 INL − Integral Nonlinearity Error − LSB DAC12_xDAT − Digital Code −2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0 0 512 1024 1536 2048 2560 3072 3584 VCC = 2.2 V, VREF = 1.5V DAC12AMPx = 7 DAC12IR = 1 TYPICAL DNL ERROR vs DIGITAL INPUT DATA 4095 DNL − Differential Nonlinearity Error − LSB MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, output specifications PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT No Load, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7 2.2V/3V 0 0.005 V V Output voltage range No Load, VeREF+ = AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7 2.2V/3V AVCC−0.05 AVCC VO (see Note 1, Figure 22) RLoad= 3 kΩ, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7 2.2V/3V 0 0.1 V RLoad= 3 kΩ, VeREF+ = AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7 2.2V/3V AVCC−0.13 AVCC V CL(DAC12) Max DAC12 load capacitance 2.2V/3V 100 pF I Max DAC12 2.2V −0.5 +0.5 mA IL(DAC12) load current 3V −1.0 +1.0 mA RLoad= 3 kΩ VO/P(DAC12) = 0 V DAC12AMPx = 7 DAC12_xDAT = 0h 2.2V/3V 150 250 RO/P(DAC12) Output resistance (see Figure 22) RLoad= 3 kΩ VO/P(DAC12) = AVCC DAC12AMPx = 7 DAC12_xDAT = 0FFFh 2.2V/3V 150 250 Ω RLoad= 3 kΩ 0.3 V < VO/P(DAC12) < AVCC − 0.3 V DAC12AMPx = 7 2.2V/3V 1 4 NOTES: 1. Data is valid after the offset calibration of the output amplifier. RO/P(DAC12_x) Max 0.3 AVCC AVCC −0.3V VOUT Min RLoad AVCC CLoad = 100pF 2 ILoad DAC12 O/P(DAC12_x) Figure 22. DAC12_x Output Resistance Tests MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 47 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) 12-bit DAC, reference input specifications PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Ve Reference input DAC12IR=0 (see Notes 1 and 2) 2.2V/3V AVCC/3 AVCC+0.2 VeREF+ V voltage range DAC12IR=1 (see Notes 3 and 4) 2.2V/3V AVcc AVcc+0.2 DAC12_0 IR = DAC12_1 IR = 0 2.2V/3V 20 MΩ DAC12_0 IR = 1, DAC12_1 IR = 0 2.2V/3V 40 48 56 kΩ Ri(VREF+), Ri Reference input i t DAC12_0 IR = 0, DAC12_1 IR = 1 2.2V/3V (VREF+) Ri(VeREF+) p resistance DAC12_0 IR = DAC12_1 IR =1, DAC12_0 SREFx = DAC12_1 SREFx (see Note 5) 2.2V/3V 20 24 28 kΩ NOTES: 1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC). 2. The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC − VE(O)] / [3*(1 + EG)]. 3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC). 4. The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC − VE(O)] / (1 + EG). 5. When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel reducing the reference input resistance. 12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1 (see Figure 23 and Figure 24) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT DAC12_xDAT = 800h, DAC12AMPx = 0 → {2, 3, 4} 2.2V/3V 60 120 tON DAC12 _ , ErrorV(O) < ±0.5 LSB (see Note ON DAC12AMPx = 0 → {5, 6} 2.2V/3V 15 30 μs on-time 1,Figure 23) DAC12AMPx = 0 → 7 2.2V/3V 6 12 μ S ttli ti DAC12 DAT DAC12AMPx = 2 2.2V/3V 100 200 tS(FS) Settling time, DAC12_xDAT = DAC12AMPx = 3,5 2.2V/3V 40 80 μs full-scale 80h→ F7Fh→ 80h DAC12AMPx = 4,6,7 2.2V/3V 15 30 S ttli ti DAC12 xDAT = DAC12AMPx = 2 2.2V/3V 5 tS(C-C) Settling time, code to code DAC12_3F8h→ 408h→ 3F8h DAC12AMPx = 3,5 2.2V/3V 2 μs BF8h→ C08h→ BF8h DAC12AMPx = 4,6,7 2.2V/3V 1 DAC12 DAT DAC12AMPx = 2 2.2V/3V 0.05 0.12 SR Slew rate DAC12_xDAT = DAC12AMPx = 3,5 2.2V/3V 0.35 0.7 V/μs 80h→ F7Fh→ 80h DAC12AMPx = 4,6,7 2.2V/3V 1.5 2.7 DAC12 DAT DAC12AMPx = 2 2.2V/3V 10 Glitch energy: full-scale DAC12_xDAT = full DAC12AMPx = 3,5 2.2V/3V 10 nV-s 80h→ F7Fh→ 80h DAC12AMPx = 4,6,7 2.2V/3V 10 nV NOTES: 1. RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 23. 2. Slew rate applies to output voltage steps ≥ 200mV. RLoad AVCC CLoad = 100pF 2 DAC Output RO/P(DAC12.x) ILoad Conversion 1 Conversion 2 VOUT Conversion 3 Glitch Energy +/− 1/2 LSB +/− 1/2 LSB tsettleLH tsettleHL = 3 kΩ Figure 23. Settling Time and Glitch Energy Testing MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) Conversion 1 Conversion 2 VOUT Conversion 3 10% tSRLH tSRHL 90% 10% 90% Figure 24. Slew Rate Testing 12-bit DAC, dynamic specifications continued (TA = 25°C unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h 2.2V/3V 40 BW−3dB 3-dB bandwidth, VDC=1.5V, VAC=0.1VPP DAC12AMPx = {5, 6}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h 2.2V/3V 180 kHz (see Figure 25) DAC12AMPx = 7, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h 2.2V/3V 550 Channel to channel crosstalk DAC12_0DAT = 800h, No Load, DAC12_1DAT = 80h<−>F7Fh, RLoad = 3kΩ fDAC12_1OUT = 10kHz @ 50/50 duty cycle 2.2V/3V −80 dB (see Note 1 and Figure 26) DAC12_0DAT = 80h<−>F7Fh, RLoad = 3kΩ, DAC12_1DAT = 800h, No Load fDAC12_0OUT = 10kHz @ 50/50 duty cycle 2.2V/3V −80 NOTES: 1. RLOAD = 3 kΩ, CLOAD = 100 pF VeREF+ AC DC RLoad AVCC CLoad = 100pF 2 ILoad DAC12_x DACx = 3 kΩ Figure 25. Test Conditions for 3-dB Bandwidth Specification DAC12_xDAT 080h VOUT fToggle 7F7h VDAC12_yOUT 080h 7F7h 080h VDAC12_xOUT e REF+ RLoad AVCC CLoad = 100pF 2 ILoad DAC12_1 RLoad AVCC CLoad = 100pF 2 ILoad DAC12_0 DAC0 DAC1 V Figure 26. Crosstalk Test Conditions MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 49 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) flash memory PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(PGM/ ERASE) Program and erase supply voltage 2.7 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from DVCC during program 2.7 V/ 3.6 V 3 5 mA IERASE Supply current from DVCC during erase 2.7 V/ 3.6 V 3 7 mA tCPT Cumulative program time see Note 1 2.7 V/ 3.6 V 4 ms tCMErase Cumulative mass erase time see Note 2 2.7 V/ 3.6 V 200 ms Program/Erase endurance 104 105 cycles tRetention Data retention duration TJ = 25°C 100 years tWord Word or byte program time 35 tBlock, 0 Block program time for 1st byte or word 30 tBlock, 1-63 Block program time for each additional byte or word see Note 3 21 t tBlock, End Block program end-sequence wait time 6 tFTG tMass Erase Mass erase time 5297 tSeg Erase Segment erase time 4819 NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required). 3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG). JTAG interface PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT f TCK input frequency see Note 1 2.2 V 0 5 MHz fTCK 3 V 0 10 MHz RInternal Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2 2.2 V/ 3 V 25 60 90 kΩ NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected. 2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions. JTAG fuse (see Note 1) PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V VFB Voltage level on TDI/TCLK for fuse-blow: F versions 6 7 V IFB Supply current into TDI/TCLK during fuse blow 100 mA tFB Time to blow fuse 1 ms NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION input/output schematics port P1, P1.0 to P1.7, input/output with Schmitt trigger P1.0/TACLK ... P1IN.x Module X IN Pad Logic Interrupt Flag Edge Select Interrupt P1SEL.x P1IES.x P1IFG.x P1IRQ.x P1IE.x EN D Set EN Q P1OUT.x P1DIR.x P1SEL.x Module X OUT Direction Control From Module 0 1 0 1 P1.7/TA2 PnSel.x PnDIR.x Dir. CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x P1Sel.0 P1DIR.0 P1DIR.0 P1OUT.0 DVSS P1IN.0 TACLK† P1IE.0 P1IFG.0 P1IES.0 P1Sel.1 P1DIR.1 P1DIR.1 P1OUT.1 Out0 signal† P1IN.1 CCI0A† P1IE.1 P1IFG.1 P1IES.1 P1Sel.2 P1DIR.2 P1DIR.2 P1OUT.2 Out1 signal† P1IN.2 CCI1A† P1IE.2 P1IFG.2 P1IES.2 P1Sel.3 P1DIR.3 P1DIR.3 P1OUT.3 Out2 signal† P1IN.3 CCI2A† P1IE.3 P1IFG.3 P1IES.3 P1Sel.4 P1DIR.4 P1DIR.4 P1OUT.4 SMCLK P1IN.4 unused P1IE.4 P1IFG.4 P1IES.4 P1Sel.5 P1DIR.5 P1DIR.5 P1OUT.5 Out0 signal† P1IN.5 unused P1IE.5 P1IFG.5 P1IES.5 P1Sel.6 P1DIR.6 P1DIR.6 P1OUT.6 Out1 signal† P1IN.6 unused P1IE.6 P1IFG.6 P1IES.6 P1Sel.7 P1DIR.7 P1DIR.7 P1OUT.7 Out2 signal† P1IN.7 unused P1IE.7 P1IFG.7 P1IES.7 † Signal from or to Timer_A MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 51 APPLICATION INFORMATION input/output schematics (continued) port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt trigger P2IN.x P2OUT.x Pad Logic P2DIR.x P2SEL.x Module X OUT Edge Select Interrupt P2SEL.x P2IES.x P2IFG.x P2IRQ.x P2IE.x Direction Control P2.0/ACLK 0 1 0 1 Interrupt Flag Set EN Q Module X IN EN D Bus Keeper CAPD.X P2.1/TAINCLK P2.2/CAOUT/TA0 P2.6/ADC12CLK/DMAE0 P2.7/TA0 0: Input 1: Output x: Bit Identifier 0 to 2, 6, and 7 for Port P2 From Module PnSel.x PnDIR.x Dir. CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x P2Sel.0 P2DIR.0 P2DIR.0 P2OUT.0 ACLK P2IN.0 unused P2IE.0 P2IFG.0 P2IES.0 P2Sel.1 P2DIR.1 P2DIR.1 P2OUT.1 DVSS P2IN.1 INCLK‡ P2IE.1 P2IFG.1 P2IES.1 P2Sel.2 P2DIR.2 P2DIR.2 P2OUT.2 CAOUT† P2IN.2 CCI0B‡ P2IE.2 P2IFG.2 P2IES.2 P2Sel.6 P2DIR.6 P2DIR.6 P2OUT.6 ADC12CLK¶ P2IN.6 DMAE0# P2IE.6 P2IFG.6 P2IES.6 P2Sel.7 P2DIR.7 P2DIR.7 P2OUT.7 Out0 signal§ P2IN.7 unused P2IE.7 P2IFG.7 P2IES.7 † Signal from Comparator_A ‡ Signal to Timer_A § Signal from Timer_A ¶ ADC12CLK signal is output of the 12-bit ADC module # Signal to DMA, channel 0, 1 and 2 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION input/output schematics (continued) port P2, P2.3 to P2.4, input/output with Schmitt trigger Bus Keeper P2IN.3 P2OUT.3 Pad Logic P2DIR.3 P2SEL.3 Module X OUT Edge Select Interrupt P2SEL.3 P2IES.3 P2IFG.3 P2IRQ.3 P2IE.3 Direction Control From Module P2.3/CA0/TA1 0 1 0 1 Interrupt Flag Set EN Q Module X IN EN D P2IN.4 P2OUT.4 Pad Logic P2DIR.4 P2SEL.4 Module X OUT Edge Select Interrupt P2SEL.4 P2IES.4 P2IFG.4 P2IRQ.4 P2IE.4 Direction Control From Module P2.4/CA1/TA2 0 1 0 1 Interrupt Flag Set EN Q Module X IN EN D Comparator_A − + Reference Block CCI1B CAF CAREF P2CA CAEX CAREF Bus Keeper CAPD.3 CAPD.4 To Timer_A3 0: Input 1: Output 0: Input 1: Output PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x P2Sel.3 P2DIR.3 P2DIR.3 P2OUT.3 Out1 signal† P2IN.3 unused P2IE.3 P2IFG.3 P2IES.3 P2Sel.4 P2DIR.4 P2DIR.4 P2OUT.4 Out2 signal† P2IN.4 unused P2IE.4 P2IFG.4 P2IES.4 † Signal from Timer_A MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 53 APPLICATION INFORMATION input/output schematics (continued) port P2, P2.5, input/output with Schmitt trigger and Rosc function for the basic clock module P2IN.5 P2OUT.5 Pad Logic P2DIR.5 P2SEL.5 Module X OUT Edge Select Interrupt P2SEL.5 P2IES.5 P2IFG.5 P2IRQ.5 P2IE.5 Direction Control P2.5/Rosc 0 1 0 1 Interrupt Flag Set EN Q DCOR Module X IN EN D to 0 1 DC Generator Bus Keeper CAPD.5 DCOR: Control Bit From Basic Clock Module If it Is Set, P2.5 Is Disconnected From P2.5 Pad Internal to Basic Clock Module VCC 0: Input 1: Output From Module PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x P2Sel.5 P2DIR.5 P2DIR.5 P2OUT.5 DVSS P2IN.5 unused P2IE.5 P2IFG.5 P2IES.5 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION input/output schematics (continued) port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt trigger P3.0/STE0 P3IN.x Module X IN Pad Logic EN D P3OUT.x P3DIR.x P3SEL.x Module X OUT Direction Control From Module 0 1 0 1 P3.4/UTXD0 P3.5/URXD0 0: Input 1: Output x: Bit Identifier, 0 and 4 to 7 for Port P3 P3.6/UTXD1‡ P3.7/URXD1¶ PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN P3Sel.0 P3DIR.0 DVSS P3OUT.0 DVSS P3IN.0 STE0 P3Sel.4 P3DIR.4 DVCC P3OUT.4 UTXD0† P3IN.4 Unused P3Sel.5 P3DIR.5 DVSS P3OUT.5 DVSS P3IN.5 URXD0§ P3Sel.6 P3DIR.6 DVCC P3OUT.6 UTXD1‡ P3IN.6 Unused P3Sel.7 P3DIR.7 DVSS P3OUT.7 DVSS P3IN.7 URXD1¶ † Output from USART0 module ‡ Output from USART1 module ‡ Input to USART0 module ¶ Input to USART1 module MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 55 APPLICATION INFORMATION input/output schematics (continued) port P3, P3.1, input/output with Schmitt trigger P3.1/SIMO0/SDA P3IN.1 Pad Logic EN D P3OUT1 P3DIR.1 P3SEL.1 (SI)MO0 or SDAo/p 0 1 0 1 DCM_SIMO SYNC MM STE STC From USART0 SI(MO)0 or SDAi/p To USAET0 0: Input 1: Output MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION input/output schematics (continued) port P3, P3.2, input/output with Schmitt trigger P3.2/SOMI0 P3IN.2 Pad Logic EN D P3OUT.2 P3DIR.2 P3SEL.2 0 1 0 1 DCM_SOMI SYNC MM STE STC SO(MI)0 From USART0 (SO)MI0 To USART0 0: Input 1: Output port P3, P3.3, input/output with Schmitt-trigger P3.3/UCLK0/SCL P3IN.3 Pad Logic EN D P3OUT.3 P3DIR.3 P3SEL.3 UCLK.0 0 1 0 1 DCM_UCLK SYNC MM STE STC From USART0 UCLK0 To USART0 0: Input 1: Output NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always an input. SPI, slave mode: The clock applied to UCLK0 is used to shift data in and out. SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode). I2C, slave mode: The clock applied to SCL is used to shift data in and out. The frequency of the clock source of the module must be  10 times the frequency of the SCL clock. I2C, master mode: To shift data in and out, the clock is supplied via the SCL terminal to all I2C slaves. The frequency of the clock source of the module must be  10 times the frequency of the SCL clock. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 57 APPLICATION INFORMATION input/output schematics (continued) port P4, P4.0 to P4.6, input/output with Schmitt trigger P4OUT.x Module X OUT P4DIR.x Direction Control From Module P4SEL.x D EN 0 1 1 0 Module X IN P4IN.x 0: Input 1: Output Bus Keeper Module IN of pin P5.7/TBOUTH/SVSOUT x: Bit Identifier, 0 to 6 for Port P4 P4.0/TB0 ... P4.6/TB6 P4SEL.7 P4DIR.7 PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN P4Sel.0 P4DIR.0 P4DIR.0 P4OUT.0 Out0 signal† P4IN.0 CCI0A / CCI0B‡ P4Sel.1 P4DIR.1 P4DIR.1 P4OUT.1 Out1 signal† P4IN.1 CCI1A / CCI1B‡ P4Sel.2 P4DIR.2 P4DIR.2 P4OUT.2 Out2 signal† P4IN.2 CCI2A / CCI2B‡ P4Sel.3 P4DIR.3 P4DIR.3 P4OUT.3 Out3 signal† P4IN.3 CCI3A / CCI3B‡ P4Sel.4 P4DIR.4 P4DIR.4 P4OUT.4 Out4 signal† P4IN.4 CCI4A / CCI4B‡ P4Sel.5 P4DIR.5 P4DIR.5 P4OUT.5 Out5 signal† P4IN.5 CCI5A / CCI5B‡ P4Sel.6 P4DIR.6 P4DIR.6 P4OUT.6 Out6 signal† P4IN.6 CCI6A † Signal from Timer_B ‡ Signal to Timer_B MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION input/output schematics (continued) port P4, P4.7, input/output with Schmitt trigger P4.7/TBCLK P4IN.7 Timer_B, Pad Logic EN D P4OUT.7 P4DIR.7 P4SEL.7 0 1 0 1 TBCLK 0: Input 1: Output DVSS port P5, P5.0 and P5.4 to P5.7, input/output with Schmitt trigger P5.0/STE1 P5IN.x Module X IN Pad Logic EN D P5OUT.x P5DIR.x P5SEL.x Module X OUT Direction Control From Module 0 1 0 1 P5.4/MCLK P5.5/SMCLK P5.6/ACLK P5.7/TBOUTH/SVSOUT x: Bit Identifier, 0 and 4 to 7 for Port P5 0: Input 1: Output PnSel.x PnDIR.x Dir. CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN P5Sel.0 P5DIR.0 DVSS P5OUT.0 DVSS P5IN.0 STE.1 P5Sel.4 P5DIR.4 DVCC P5OUT.4 MCLK P5IN.4 unused P5Sel.5 P5DIR.5 DVCC P5OUT.5 SMCLK P5IN.5 unused P5Sel.6 P5DIR.6 DVCC P5OUT.6 ACLK P5IN.6 unused P5Sel.7 P5DIR.7 DVSS P5OUT.7 SVSOUT P5IN.7 TBOUTHiZ NOTE: TBOUTHiZ signal is used by port module P4, pins P4.0 to P4.6. The function of TBOUTHiZ is mainly useful when used with Timer_B7. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 59 APPLICATION INFORMATION input/output schematics (continued) port P5, P5.1, input/output with Schmitt trigger P5.1/SIMO1 P5IN.1 Pad Logic EN D P5OUT.1 P5DIR.1 P5SEL.1 0 1 0 1 DCM_SIMO SYNC MM STE STC (SI)MO1 From USART1 SI(MO)1 To USART1 0: Input 1: Output port P5, P5.2, input/output with Schmitt trigger P5.2/SOMI1 P5IN.2 Pad Logic EN D P5OUT.2 P5DIR.2 P5SEL.2 0 1 0 1 DCM_SOMI SYNC MM STE STC SO(MI)1 From USART1 (SO)MI1 To USART1 0: Input 1: Output MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION input/output schematics (continued) port P5, P5.3, input/output with Schmitt trigger P5.3/UCLK1 P5IN.3 Pad Logic EN D P5OUT.3 P5DIR.3 P5SEL.3 0 1 0 1 DCM_SIMO SYNC MM STE STC UCLK1 From USART1 UCLK1 To USART1 0: Input 1: Output NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P5.3/UCLK1 direction is always input. SPI, slave mode: The clock applied to UCLK1 is used to shift data in and out. SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P5.3/UCLK1 (in slave mode). MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 61 APPLICATION INFORMATION input/output schematics (continued) port P6, P6.0 to P6.5, input/output with Schmitt trigger P6IN.x Module X IN Pad Logic EN D P6OUT.x P6DIR.x P6SEL.x Module X OUT Direction Control From Module 0 1 0 1 Bus Keeper To ADC From ADC 0: Input 1: Output x: Bit Identifier, 0 to 5 for Port P6 P6.0/A0 P6.1/A1 P6.2/A2 P6.3/A3 P6.4/A4 P6.5/A5 NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if the analog signal is in the range of transitions 0→1 or 1←0. The value of the throughput current depends on the driving capability of the gate. For MSP430, it is approximately 100 μA. Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12. PnSel.x PnDIR.x DIR. CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN P6Sel.0 P6DIR.0 P6DIR.0 P6OUT.0 DVSS P6IN.0 unused P6Sel.1 P6DIR.1 P6DIR.1 P6OUT.1 DVSS P6IN.1 unused P6Sel.2 P6DIR.2 P6DIR.2 P6OUT.2 DVSS P6IN.2 unused P6Sel.3 P6DIR.3 P6DIR.3 P6OUT.3 DVSS P6IN.3 unused P6Sel.4 P6DIR.4 P6DIR.4 P6OUT.4 DVSS P6IN.4 unused P6Sel.5 P6DIR.5 P6DIR.5 P6OUT.5 DVSS P6IN.5 unused NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION input/output schematics (continued) port P6, P6.6, input/output with Schmitt trigger 0, if DAC12.0CALON = 0 and DAC12.0AMP > 1 P6OUT.6 DVSS P6DIR.6 P6DIR.6 P6SEL.6 D EN 0 1 1 0 0: Port Active, T-Switch Off 1: T-Switch On, Port Disabled P6.6/A6/DAC0 P6IN.6 Pad Logic 0: Input 1: Output Bus Keeper 1 0 1, if DAC12.0AMP = 1 ’1’, if DAC12.0AMP > 0 1, if DAC12.0AMP >1 + − INCH = 6† a6† †Signal from or to ADC12 MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 63 APPLICATION INFORMATION input/output schematics (continued) port P6, P6.7, input/output with Schmitt trigger 0, if DAC12.0CALON = 0 and DAC12.0AMP > 1 P6OUT.7 DVSS P6DIR.7 P6DIR.7 P6SEL.6 D EN 0 1 1 0 0: Port Active, T-Switch Off 1: T-Switch On, Port Disabled P6.7/A7/ P6IN.7 Pad Logic 0: Input 1: Output Bus Keeper 1 0 1, if DAC12.0AMP = 1 ’1’, if DAC12.0AMP > 0 1, if DAC12.0AMP > 1 + − INCH = 7‡ a7‡ †Signal to SVS Block, Selected if VLD = 15 ‡Signal From or To ADC12 §VLD Control Bits are Located in SVS DAC1/SVSIN To SVS Mux (15)† ’1’, if VLD = 15§ MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger TDI TDO TMS TCK Test JTAG and Emulation Module Burn & Test Fuse Controlled by JTAG Controlled by JTAG Controlled by JTAG DVCC DVCC DVCC During Programming Activity and During Blowing of the Fuse, Pin TDO/TDI Is Used to Apply the Test Input Data for JTAG Circuitry TDO/TDI TDI/TCLK TMS TCK Fuse DVCC MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 65 APPLICATION INFORMATION JTAG fuse check mode MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see Figure 27). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). Time TMS Goes Low After POR TMS ITF ITDI/TCLK Figure 27. Fuse Check Mode Current, MSP430F15x/16x/161x MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Data Sheet Revision History LITERATURE NUMBER SUMMARY SLAS368F In absolute maximum ratings table, changed Tstg min from −40°C to −55°C (page 25) Added Development Tools Support section (page 2) SLAS368G Changed limits on td(SVSon) parameter (page 35) PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples MSP430F155IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F155 MSP430F155IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F155 MSP430F155IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F155 MSP430F155IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F155 MSP430F156IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F156 MSP430F156IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F156 MSP430F156IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F156 MSP430F156IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F156 MSP430F157IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F157 MSP430F157IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F157 MSP430F157IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F157 MSP430F157IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F157 MSP430F1610IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR M430F1610 MSP430F1610IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR M430F1610 MSP430F1610IRTD ACTIVE VQFN RTD 64 TBD Call TI Call TI MSP430F1610IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F1610 MSP430F1610IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F1610 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples MSP430F1611IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F1611 MSP430F1611IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F1611 MSP430F1611IRTD ACTIVE VQFN RTD 64 TBD Call TI Call TI MSP430F1611IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F1611 MSP430F1611IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F1611 MSP430F1612IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR M430F1612 MSP430F1612IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR M430F1612 MSP430F1612IRTD ACTIVE VQFN RTD 64 TBD Call TI Call TI MSP430F1612IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F1612 MSP430F1612IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F1612 MSP430F167IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F167 MSP430F167IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F167 MSP430F167IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F167 MSP430F167IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F167 MSP430F168IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F168 MSP430F168IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F168 MSP430F168IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F168 MSP430F168IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F168 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples MSP430F169IPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F169 MSP430F169IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F169 MSP430F169IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F169 MSP430F169IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR M430F169 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant MSP430F155IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F156IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F157IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F1610IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F1611IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F1612IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F167IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F168IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 MSP430F169IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Sep-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F155IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F156IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F157IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F1610IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F1611IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F1612IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F167IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F168IPMR LQFP PM 64 1000 367.0 367.0 45.0 MSP430F169IPMR LQFP PM 64 1000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 13-Sep-2013 Pack Materials-Page 2 MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 4040152/C 11/96 32 17 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN Gage Plane 0,27 33 16 48 1 0,17 49 64 SQ SQ 10,20 11,80 12,20 9,80 7,50 TYP 1,60 MAX 1,45 1,35 0,08 0,50 0,08 M 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. May also be thermally enhanced plastic with leads connected to the die pads. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated 20 mW Power, 2.3 V to 5.5 V, 75 MHz Complete DDS Data Sheet AD9834 FEATURES Narrow-band SFDR >72 dB 2.3 V to 5.5 V power supply Output frequency up to 37.5 MHz Sine output/triangular output On-board comparator 3-wire SPI® interface Extended temperature range: −40°C to +105°C Power-down option 20 mW power consumption at 3 V 20-lead TSSOP APPLICATIONS Frequency stimulus/waveform generation Frequency phase tuning and modulation Low power RF/communications systems Liquid and gas flow measurement Sensory applications: proximity, motion, and defect detection Test and medical equipment GENERAL DESCRIPTION The AD9834 is a 75 MHz low power DDS device capable of producing high performance sine and triangular outputs. It also has an on-board comparator that allows a square wave to be produced for clock generation. Consuming only 20 mW of power at 3 V makes the AD9834 an ideal candidate for power-sensitive applications.Capability for phase modulation and frequency modulation is provided. The frequency registers are 28 bits; with a 75 MHz clock rate, resolution of 0.28 Hz can be achieved. Similarly, with a 1 MHz clock rate, the AD9834 can be tuned to 0.004 Hz resolution. Frequency and phase modulation are affected by loading registers through the serial interface and toggling the registers using software or the FSELECT pin and PSELECT pin, respectively. The AD9834 is written to using a 3-wire serial interface. This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards. The device operates with a power supply from 2.3 V to 5.5 V. The analog and digital sections are independent and can be run from different power supplies, for example, AVDD can equal 5 V with DVDD equal to 3 V. The AD9834 has a power-down pin (SLEEP) that allows external control of the power-down mode. Sections of the device that are not being used can be powered down to minimize the current consumption. For example, the DAC can be powered down when a clock output is being generated. The part is available in a 20-lead TSSOP. FUNCTIONAL BLOCK DIAGRAM 12ΣMUXMUXCOMPARATORMSBCAP/2.5VDVDDAGNDAVDDMCLKAD9834FSYNCSCLKSDATACOMPIOUTIOUTBDGNDREGULATORREFOUTFS ADJUSTVINFSELECT12-BIT PHASE0 REG12-BIT PHASE1 REGSLEEPRESETPSELECTMUXMUXMUXSIGN BIT OUTVCC2.5VON-BOARDREFERENCE16-BIT CONTROLREGISTERFULL-SCALECONTROL10-BITDACDIVIDEDBY 2SINROMPHASEACCUMULATOR(28-BIT)28-BIT FREQ0REG28-BIT FREQ1REGSERIAL INTERFACEANDCONTROL LOGIC02705-001 Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2003–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9834 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Timing Characteristics ................................................................ 6 Absolute Maximum Ratings ............................................................ 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 14 Theory of Operation ...................................................................... 15 Circuit Description ......................................................................... 16 Numerically Controlled Oscillator Plus Phase Modulator ... 16 SIN ROM ..................................................................................... 16 Digital-to-Analog Converter (DAC) ....................................... 16 Comparator ................................................................................. 16 Regulator ...................................................................................... 17 Output Voltage Compliance ...................................................... 17 Functional Description .................................................................. 18 Serial Interface ............................................................................ 18 Powering Up the AD9834 ......................................................... 18 Latency ......................................................................................... 18 Control Register ......................................................................... 18 Frequency and Phase Registers ................................................ 20 Writing to a Frequency Register ............................................... 21 Writing to a Phase Register ....................................................... 21 RESET Function ......................................................................... 21 SLEEP Function .......................................................................... 21 SIGN BIT OUT Pin .................................................................... 22 The IOUT and IOUTB Pins ...................................................... 22 Applications Information .............................................................. 23 Grounding and Layout .................................................................. 26 Interfacing to Microprocessors ..................................................... 27 AD9834 to ADSP-21xx Interface ............................................. 27 AD9834 to 68HC11/68L11 Interface ....................................... 27 AD9834 to 80C51/80L51 Interface .......................................... 28 AD9834 to DSP56002 Interface ............................................... 28 Outline Dimensions ....................................................................... 29 Ordering Guide .......................................................................... 29 Rev. D | Page 2 of 32 Data Sheet AD9834 REVISION HISTORY 3/14—Rev. C to Rev. D Changes to Table 3 ............................................................................ 7 Deleted Evaluation Board Section ................................................ 29 Changes to Ordering Guide ........................................................... 35 2/11—Rev. B to Rev. C Changes to IDD Parameter, Table 1 .................................................. 5 Changes to FS ADJUST Description, Table 4 ................................ 8 Added Output Voltage Compliance Section................................ 17 Changes to Figure 31 ...................................................................... 23 Changes to Figure 32 ...................................................................... 24 Deleted Using the AD9834 Evaluation Board Section and the Prototyping Area Section ............................................................... 28 Added System Development Platform Section, AD9834 to SPORT Interface Section, Figure 39, and Figure 40; Renumbered Sequentially .............................................................. 29 Changes to XO vs. External Clock Section and Power Supply Section .............................................................................................. 29 Deleted Bill of Materials, Table 19; Renumbered Sequentially .............................................................. 30 Added Evaluation Board Schematics Section and Figure 41 .... 30 Added Figure 42 .............................................................................. 31 Added Evaluation Board Layout Section and Figure 43 ............ 32 Added Figure 44 .............................................................................. 33 Added Figure 45 .............................................................................. 34 Changes to Ordering Guide ........................................................... 35 4/10—Rev. A to Rev. B Changes to Comparator Section ................................................... 15 Added Figure 28 .............................................................................. 16 Changes to Serial Interface Section .............................................. 17 8/06—Rev. 0 to Rev. A Updated Format ................................................................. Universal Changed to 75 MHz Complete DDS ............................... Universal Changes to Features Section ............................................................ 1 Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 6 Changes to Table 3 ............................................................................ 8 Added Figure 10, Figures Renumbered Sequentially ................... 9 Added Figure 16 and Figure 17, Figures Renumbered Sequentially ...................................................................................... 10 Changes to Table 6 .......................................................................... 19 Changes to Writing a Frequency Register Section ..................... 20 Changes to Figure 29 ...................................................................... 21 Changes to Table 19 ........................................................................ 30 Changes to Figure 38 ...................................................................... 28 2/03—Revision 0: Initial Version Rev. D | Page 3 of 32 AD9834 Data Sheet SPECIFICATIONS VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 kΩ, RLOAD = 200 Ω for IOUT and IOUTB, unless otherwise noted. Table 1. Grade B, Grade C1 Parameter2 Min Typ Max Unit Test Conditions/Comments SIGNAL DAC SPECIFICATIONS Resolution 10 Bits Update Rate 75 MSPS IOUT Full Scale3 3.0 mA VOUT Max 0.6 V VOUT Min 30 mV Output Compliance4 0.8 V DC Accuracy Integral Nonlinearity ±1 LSB Differential Nonlinearity ±0.5 LSB DDS SPECIFICATIONS Dynamic Specifications Signal-to-Noise Ratio 55 60 dB fMCLK = 75 MHz, fOUT = fMCLK/4096 Total Harmonic Distortion −66 −56 dBc fMCLK = 75 MHz, fOUT = fMCLK/4096 Spurious-Free Dynamic Range (SFDR) Wideband (0 to Nyquist) −60 −56 dBc fMCLK = 75 MHz, fOUT = fMCLK/75 Narrow Band (±200 kHz) B Grade −78 −67 dBc fMCLK = 50 MHz, fOUT = fMCLK/50 C Grade −74 −65 dBc fMCLK = 75 MHz, fOUT = fMCLK/75 Clock Feedthrough −50 dBc Wake-Up Time 1 ms COMPARATOR Input Voltage Range 1 V p-p AC-coupled internally Input Capacitance 10 pF Input High-Pass Cutoff Frequency 4 MHz Input DC Resistance 5 MΩ Input Leakage Current 10 μA OUTPUT BUFFER Output Rise/Fall Time 12 ns Using a 15 pF load Output Jitter 120 ps rms 3 MHz sine wave, 0.6 V p-p VOLTAGE REFERENCE Internal Reference 1.12 1.18 1.24 V REFOUT Output Impedance5 1 kΩ Reference Temperature Coefficient 100 ppm/°C LOGIC INPUTS Input High Voltage, VINH 1.7 V 2.3 V to 2.7 V power supply 2.0 V 2.7 V to 3.6 V power supply 2.8 V 4.5 V to 5.5 V power supply Input Low Voltage, VINL 0.6 V 2.3 V to 2.7 V power supply 0.7 V 2.7 V to 3.6 V power supply 0.8 V 4.5 V to 5.5 V power supply Input Current, IINH/IINL 10 μA Input Capacitance, CIN 3 pF Rev. D | Page 4 of 32 Data Sheet AD9834 Grade B, Grade C1 Parameter2 Min Typ Max Unit Test Conditions/Comments POWER SUPPLIES AVDD 2.3 5.5 V fMCLK = 75 MHz, fOUT = fMCLK/4096 DVDD 2.3 5.5 V IAA6 3.8 5 mA IDD6 B Grade 2.0 3 mA IDD code dependent (see Figure 8) C Grade 2.7 3.7 mA IDD code dependent (see Figure 8) IAA + IDD6 B Grade 5.8 8 mA C Grade 6.5 8.7 mA Low Power Sleep Mode B Grade 0.5 mA DAC powered down, MCLK running C Grade 0.6 mA DAC powered down, MCLK running 1 B grade: MCLK = 50 MHz; C grade: MCLK = 75 MHz. For specifications that do not specify a grade, the value applies to both grades. 2 Operating temperature range is as follows: B, C versions: −40°C to +105°C, typical specifications are at 25°C. 3 For compliance, with specified load of 200 Ω, IOUT full scale should not exceed 4 mA. 4 Guaranteed by design. 5 Applies when REFOUT is sourcing current. The impedance is higher when REFOUT is sinking current. 6 Measured with the digital inputs static and equal to 0 V or DVDD. RSET6.8kΩIOUT1210-BIT DAC20pFFS ADJUSTAD9834REGULATOR100nFCAP/2.5V10nFREFOUTCOMP10nFAVDDSINROMRLOAD200ΩON-BOARDREFERENCEFULL-SCALECONTROL02705-002 Figure 2. Test Circuit Used to Test the Specifications Rev. D | Page 5 of 32 AD9834 Data Sheet TIMING CHARACTERISTICS DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted. Table 2. Parameter1 Limit at TMIN to TMAX Unit Test Conditions/Comments t1 20/13.33 ns min MCLK period: 50 MHz/75 MHz t2 8/6 ns min MCLK high duration: 50 MHz/75 MHz t3 8/6 ns min MCLK low duration: 50 MHz/75 MHz t4 25 ns min SCLK period t5 10 ns min SCLK high duration t6 10 ns min SCLK low duration t7 5 ns min FSYNC-to-SCLK falling edge setup time t8 MIN 10 ns min FSYNC-to-SCLK hold time t8 MAX t4 − 5 ns max t9 5 ns min Data setup time t10 3 ns min Data hold time t11 8 ns min FSELECT, PSELECT setup time before MCLK rising edge t11A 8 ns min FSELECT, PSELECT setup time after MCLK rising edge t12 5 ns min SCLK high to FSYNC falling edge setup time 1 Guaranteed by design, not production tested. Timing Diagrams MCLKt1t3t202705-003 Figure 3. Master Clock FSELECT,PSELECTVALID DATAVALID DATAVALID DATAMCLKt11At1102705-004 Figure 4. Control Timing D0SCLKFSYNCSDATAD15D14D2D1D15D14t12t7t6t8t5t4t9t1002705-005 Figure 5. Serial Timing Rev. D | Page 6 of 32 Data Sheet AD9834 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Ratings AVDD to AGND −0.3 V to +6 V DVDD to DGND −0.3 V to +6 V AGND to DGND −0.3 V to +0.3 V CAP/2.5V 2.75 V Digital I/O Voltage to DGND −0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND −0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C TSSOP Package θJA Thermal Impedance 143°C/W θJC Thermal Impedance 45°C/W Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature 220°C Reflow Soldering (Pb-Free) Peak Temperature 260°C (+0/–5) Time at Peak Temperature 10 sec to 40 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. D | Page 7 of 32 AD9834 Data Sheet Rev. D | Page 8 of 32 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 REFOUT COMP AVDD DGND CAP/2.5V DVDD FS ADJUST IOUT AGND VIN SCLK FSYNC SIGN BIT OUT PSELECT FSELECT MCLK RESET SLEEP SDATA IOUTB AD9834 TOP VIEW (Not to Scale) 02705-006 Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description ANALOG SIGNAL AND REFERENCE 1 FS ADJUST Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows: IOUT FULL SCALE = 18 × FSADJUST/RSET FSADJUST = 1.15 V nominal, RSET = 6.8 kΩ typical. 2 REFOUT Voltage Reference Output. The AD9834 has an internal 1.20 V reference that is made available at this pin. 3 COMP DAC Bias Pin. This pin is used for decoupling the DAC bias voltage. 17 VIN Input to Comparator. The comparator can be used to generate a square wave from the sinusoidal DAC output. The DAC output should be filtered appropriately before being applied to the comparator to improve jitter. When Bit OPBITEN and Bit SIGN/PIB in the control register are set to 1, the comparator input is connected to VIN. 19, 20 IOUT, IOUTB Current Output. This is a high impedance current source. A load resistor of nominally 200 Ω should be connected between IOUT and AGND. IOUTB should preferably be tied through an external load resistor of 200 Ω to AGND, but it can be tied directly to AGND. A 20 pF capacitor to AGND is also recommended to prevent clock feedthrough. POWER SUPPLY 4 AVDD Positive Power Supply for the Analog Section. AVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling capacitor should be connected between AVDD and AGND. 5 DVDD Positive Power Supply for the Digital Section. DVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling capacitor should be connected between DVDD and DGND. 6 CAP/2.5V The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from DVDD using an on-board regulator (when DVDD exceeds 2.7 V). The regulator requires a decoupling capacitor of typically 100 nF that is connected from CAP/2.5 V to DGND. If DVDD is equal to or less than 2.7 V, CAP/2.5 V should be shorted to DVDD. 7 DGND Digital Ground. 18 AGND Analog Ground. DIGITAL INTERFACE AND CONTROL 8 MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock. 9 FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase accumulator. The frequency register to be used can be selected using Pin FSELECT or Bit FSEL. When Bit FSEL is used to select the frequency register, the FSELECT pin should be tied to CMOS high or low. 10 PSELECT Phase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1, is added to the phase accumulator output. The phase register to be used can be selected using Pin PSELECT or Bit PSEL. When the phase registers are being controlled by Bit PSEL, the PSELECT pin should be tied to CMOS high or low. 11 RESET Active High Digital Input. RESET resets appropriate internal registers to zero; this corresponds to an analog output of midscale. RESET does not affect any of the addressable registers. 12 SLEEP Active High Digital Input. When this pin is high, the DAC is powered down. This pin has the same function as Control Bit SLEEP12. Data Sheet AD9834 Pin No. Mnemonic Description 13 SDATA Serial Data Input. The 16-bit serial data-word is applied to this input. 14 SCLK Serial Clock Input. Data is clocked into the AD9834 on each falling SCLK edge. 15 FSYNC Active Low Control Input. This is the frame synchronization signal for the input data. When FSYNC is taken low, the internal logic is informed that a new word is being loaded into the device. 16 SIGN BIT OUT Logic Output. The comparator output is available on this pin or, alternatively, the MSB from the NCO can be output on this pin. Setting Bit OPBITEN in the control register to 1 enables this output pin. Bit SIGN/PIB determines whether the comparator output or the MSB from the NCO is output on the pin. Rev. D | Page 9 of 32 AD9834 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS MCLK FREQUENCY (MHz)4.000755V3VTA = 25°CIDD ( mA)3.53.02.52.01.51.00.51530456002705-007 Figure 7. Typical Current Consumption (IDD) vs. MCLK Frequency 4.000.51.01.52.02.53.03.5fOUT (Hz)IDD (mA)TA = 25°C5V3V1001k10k100k1M10M100M02705-008 Figure 8. Typical IDD vs. fOUT for fMCLK = 50 MHz MCLK FREQUENCY (MHz)SFDR (dBc)–65–60–90–70–75–80–85AVDD = DVDD = 3VTA = 25°CSFDR dB MCLK/50SFDR dB MCLK/70153045607502705-009 Figure 9. Narrow-Band SFDR vs. MCLK Frequency 0–10–20–30–40–50–60–70–80MCLK FREQUENCY (MHz)SFDR (dBc)010203040506070fOUT = 1MHzSFDR dB MCLK/7AVDD = DVDD = 3VTA = 25°C02705-010 Figure 10. Wideband SFDR vs. MCLK Frequency SFDR (dBc)0–40–80–50–60–70–10–20–3050MHz CLOCK30MHz CLOCKAVDD = DVDD = 3VTA = 25°CfOUT/fMCLK0.0010.010.11.01010002705-011 Figure 11. Wideband SFDR vs. fOUT/fMCLK for Various MCLK Frequencies MCLK FREQUENCY (MHz)SNR (dB)–60–65–70–50–55–40–451.05.010.012.525.050.0TA = 25°CAVDD = DVDD = 3VfOUT = MCLK/409602705-012 Figure 12. SNR vs. MCLK Frequency Rev. D | Page 10 of 32 Data Sheet AD9834 50010007006506005508507508009009505.5V2.3VTEMPERATURE (°C)–4025105WAKE-UP TIME ( μs)02705-013 Figure 13. Wake-Up Time vs. Temperature 1.1501.1251.1001.1751.2001.2501.225TEMPERATURE (°C)V(REFOUT) (V)LOWER RANGEUPPER RANGE–402510502705-014 Figure 14. VREFOUT vs. Temperature FREQUENCY (Hz)(dBc/Hz)–150–110–100–120–130–140–160AVDD = DVDD = 5VTA = 25°C1001k10k100k200k02705-015 Figure 15. Output Phase Noise, fOUT = 2 MHz, MCLK = 50 MHz 0.200–40–2002040608010002705-037TEMPERATURE(°C)DVDD (V)0.180.160.140.120.100.080.060.040.02DVDD=3.3VDVDD=5.5VDVDD=2.3V Figure 16. SIGN BIT OUT Low Level, ISINK = 1 mA 5.51.5–40–2002040608010002705-038TEMPERATURE(°C)DVDD ( V)5.04.54.03.53.02.52.0DVDD=2.3VDVDD=2.7VDVDD=3.3VDVDD=4.5VDVDD=5.5V Figure 17. SIGN BIT OUT High Level, ISINK = 1 mA FREQUENCY (Hz)(dB)0–20–50–90–100–80–70–60–40–30–10RWB 100ST 100 SECVWB 300100k02705-016 Figure 18. fMCLK = 10 MHz; fOUT = 2.4 kHz, Frequency Word = 000FBA9 Rev. D | Page 11 of 32 AD9834 Data Sheet FREQUENCY (Hz)(dB)0–20–50–90–100–80–70–60–40–30–1005MRWB 1kST 50 SECVWB 30002705-017 Figure 19. fMCLK = 10 MHz; fOUT = 1.43 MHz = fMCLK/7, Frequency Word = 2492492 FREQUENCY (Hz)0–20–50–90–100–80–70–60–40–30–1005MRWB 1kST 50 SECVWB 300(dB)02705-018 Figure 20. fMCLK = 10 MHz; fOUT = 3.33 MHz = fMCLK/3, Frequency Word = 5555555 FREQUENCY (Hz)0–20–50–90–100–80–70–60–40–30–100160kRWB 100ST 200 SECVWB 30(dB)02705-019 Figure 21. fMCLK = 50 MHz; fOUT = 12 kHz, Frequency Word = 000FBA9 FREQUENCY (Hz)0–20–50–90–100–80–70–60–40–30–1001.6MRWB 100ST 200 SECVWB 300(dB)02705-020 Figure 22. fMCLK = 50 MHz; fOUT = 120 kHz, Frequency Word = 009D496 FREQUENCY (Hz)0–20–50–90–100–80–70–60–40–30–10025MRWB 1kST 200 SECVWB 300(dB)02705-021 Figure 23. fMCLK = 50 MHz; fOUT = 1.2 MHz, Frequency Word = 0624DD3 FREQUENCY (Hz)(dB)0–20–50–90–100–80–70–60–40–30–10025MRWB 1kST 200 SECVWB 30002705-022 Figure 24. fMCLK = 50 MHz; fOUT = 4.8 MHz, Frequency Word = 189374C Rev. D | Page 12 of 32 Data Sheet AD9834 FREQUENCY (Hz)(dB)0–20–50–90–100–80–70–60–40–30–10025MRWB 1kST 200 SECVWB 30002705-023 Figure 25. fMCLK = 50 MHz; fOUT = 7.143 MHz = fMCLK/7, Frequency Word = 2492492 FREQUENCY (Hz)(dB)0–20–50–90–100–80–70–60–40–30–10025MRWB 1kST 200 SECVWB 30002705-024 Figure 26. fMCLK = 50 MHz; fOUT = 16.667 MHz = fMCLK/3, Frequency Word = 5555555 Rev. D | Page 13 of 32 AD9834 Data Sheet Rev. D | Page 14 of 32 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 LSB below the first code transition (000 . . . 00 to 000 . . . 01), and full scale, a point 0.5 LSB above the last code transition (111 . . . 10 to 111 . . . 11). The error is expressed in LSBs. Differential Nonlinearity (DNL) DNL is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC. A specified DNL of ±1 LSB maximum ensures monotonicity. Output Compliance The output compliance refers to the maximum voltage that can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the output com- pliance are generated, the AD9834 may not meet the specifications listed in the data sheet. Spurious-Free Dynamic Range (SFDR) Along with the frequency of interest, harmonics of the fundamental frequency and images of these frequencies are present at the output of a DDS device. The SFDR refers to the largest spur or harmonic present in the band of interest. The wideband SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 to Nyquist bandwidth. The narrow-band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of ±200 kHz about the fundamental frequency. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD9834, THD is defined as 1 2 3456 V V VVVV THD 2 2222 log 20    where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second harmonic through the sixth harmonic. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in decibels. Clock Feedthrough There is feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the output spectrum of the AD9834. Data Sheet AD9834 THEORY OF OPERATION Sine waves are typically thought of in terms of their magnitude form a(t) = sin (ωt). However, these are nonlinear and not easy to generate except through piecewise construction. On the other hand, the angular information is linear in nature, that is, the phase angle rotates through a fixed angle for each unit of time. The angular rate depends on the frequency of the signal by the traditional rate of ω = 2πf. MAGNITUDEPHASE+10–12p02π4π6π2π4π6π02705-025 Figure 27. Sine Wave Knowing that the phase of a sine wave is linear and given a reference interval (clock period), the phase rotation for that period can be determined. ΔPhase = ωΔt Solving for ω, ω = ΔPhase/Δt = 2πf Solving for f and substituting the reference clock frequency for the reference period (1/fMCLK = Δt), f = ΔPhase × fMCLK/2π The AD9834 builds the output based on this simple equation. A simple DDS chip can implement this equation with three major subcircuits: numerically controlled oscillator + phase modulator, SIN ROM, and digital-to-analog converter (DAC). Each of these subcircuits is discussed in the Circuit Description section. Rev. D | Page 15 of 32 AD9834 Data Sheet CIRCUIT DESCRIPTION The AD9834 is a fully integrated direct digital synthesis (DDS) chip. The chip requires one reference clock, one low precision resistor, and eight decoupling capacitors to provide digitally created sine waves up to 37.5 MHz. In addition to the generation of this RF signal, the chip is fully capable of a broad range of simple and complex modulation schemes. These modulation schemes are fully implemented in the digital domain, allowing accurate and simple realization of complex modulation algorithms using DSP techniques. The internal circuitry of the AD9834 consists of the following main sections: a numerically controlled oscillator (NCO), frequency and phase modulators, SIN ROM, a DAC, a comparator, and a regulator. NUMERICALLY CONTROLLED OSCILLATOR PLUS PHASE MODULATOR This consists of two frequency select registers, a phase accumulator, two phase offset registers, and a phase offset adder. The main component of the NCO is a 28-bit phase accumulator. Continuous time signals have a phase range of 0 π to 2π. Outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. The digital implementation is no different. The accumulator simply scales the range of phase numbers into a multibit digital word. The phase accumulator in the AD9834 is implemented with 28 bits. Therefore, in the AD9834, 2π = 228. Likewise, the ΔPhase term is scaled into this range of numbers: 0 < ΔPhase < 228 − 1. Making these substitutions into the previous equation f = ΔPhase × fMCLK/228 where 0 < ΔPhase < 228 − 1. The input to the phase accumulator can be selected either from the FREQ0 register or FREQ1 register and is controlled by the FSELECT pin or the FSEL bit. NCOs inherently generate con-tinuous phase signals, thus avoiding any output discontinuity when switching between frequencies. Following the NCO, a phase offset can be added to perform phase modulation using the 12-bit phase registers. The contents of one of these phase registers is added to the MSBs of the NCO. The AD9834 has two phase registers, the resolution of these registers being 2π/4096. SIN ROM To make the output from the NCO useful, it must be converted from phase information into a sinusoidal value. Phase informa-tion maps directly into amplitude; therefore, the SIN ROM uses the digital phase information as an address to a look-up table and converts the phase information into amplitude. Although the NCO contains a 28-bit phase accumulator, the output of the NCO is truncated to 12 bits. Using the full resolu-tion of the phase accumulator is impractical and unnecessary because it requires a look-up table of 228 entries. It is necessary only to have sufficient phase resolution such that the errors due to truncation are smaller than the resolution of the 10-bit DAC. This requires the SIN ROM to have two bits of phase resolution more than the 10-bit DAC. The SIN ROM is enabled using the OPBITEN and MODE bits in the control register. This is explained further in Table 18. DIGITAL-TO-ANALOG CONVERTER (DAC) The AD9834 includes a high impedance current source 10-bit DAC capable of driving a wide range of loads. The full-scale output current can be adjusted for optimum power and external load requirements using a single external resistor (RSET). The DAC can be configured for either single-ended or differential operation. IOUT and IOUTB can be connected through equal external resistors to AGND to develop complementary output voltages. The load resistors can be any value required, as long as the full-scale voltage developed across it does not exceed the voltage compliance range. Because full-scale current is controlled by RSET, adjustments to RSET can balance changes made to the load resistors. COMPARATOR The AD9834 can be used to generate synthesized digital clock signals. This is accomplished by using the on-board self-biasing comparator that converts the sinusoidal signal of the DAC to a square wave. The output from the DAC can be filtered externally before being applied to the comparator input. The comparator reference voltage is the time average of the signal applied to VIN. The comparator can accept signals in the range of approximately 100 mV p-p to 1 V p-p. As the comparator input is ac-coupled, to operate correctly as a zero crossing detector, it requires a minimum input frequency of typically 3 MHz. The comparator output is a square wave with an amplitude from 0 V to DVDD. Rev. D | Page 16 of 32 Data Sheet AD9834 The AD9834 is a sampled signal with its output following Nyquist sampling theorem. Specifically, its output spectrum contains the fundamental plus aliased signals (images) that occur at multiples of the reference clock frequency and the selected output frequency. A graphical representation of the sampled spectrum, with aliased images, is shown in Figure 28. The prominence of the aliased images is dependent on the ratio of fOUT to MCLK. If ratio is small, the aliased images are very prominent and of a relatively high energy level as determined by the sin(x)/x roll-off of the quantized DAC output. In fact, depending on the fOUT/reference clock relationship, the first aliased image can be on the order of −3 dB below the fundamental. A low-pass filter is generally placed between the output of the DAC and the input of the comparator to further suppress the effects of aliased images. Obviously, consideration must be given to the relationship of the selected output frequency and the reference clock frequency to avoid unwanted (and unexpected) output anomalies. To apply the AD9834 as a clock generator, limit the selected output frequency to <33% of reference clock frequency, and thereby avoid generating aliased signals that fall within, or close to, the output band of interest (generally dc-selected output frequency). This practice eases the complexity (and cost) of the external filter requirement for the clock generator application. Refer to the AN-837 Application Note for more information. To enable the comparator, Bit SIGN/PIB and Bit OPBITEN in the control resister are set to 1. This is explained further in Table 17. REGULATOR The AD9834 has separate power supplies for the analog and digital sections. AVDD provides the power supply required for the analog section, and DVDD provides the power supply for the digital section. Both of these supplies can have a value of 2.3 V to 5.5 V and are independent of each other. For example, the analog section can be operated at 5 V, and the digital section can be operated at 3 V, or vice versa. The internal digital section of the AD9834 is operated at 2.5 V. An on-board regulator steps down the voltage applied at DVDD to 2.5 V. The digital interface (serial port) of the AD9834 also operates from DVDD. These digital signals are level shifted within the AD9834 to make them 2.5 V compatible. When the applied voltage at the DVDD pin of the AD9834 is equal to or less than 2.7 V, Pin CAP/2.5V and Pin DVDD should be tied together, thus bypassing the on-board regulator. OUTPUT VOLTAGE COMPLIANCE The AD9834 has a maximum current density, set by the RSET, of 4 mA. The maximum output voltage from the AD9834 is VDD − 1.5 V. This is to ensure that the output impedance of the internal switch does not change, affecting the spectral performance of the part. For a minimum supply of 2.3 V, the maximum output voltage is 0.8 V. Specifications in Table 1 are guaranteed with an RSET of 6.8 kΩ and an RLOAD of 200 Ω. 02705-040SYSTEM CLOCKfOUTfC–fOUTfC+fOUT2fC–fOUT2fC+fOUT3fC–fOUT3fC+fOUTfC0HzFIRSTIMAGESECONDIMAGETHIRDIMAGEFOURTHIMAGEFIFTHIMAGESIXTHIMAGE2fC3fCFREQUENCY ( Hz)SIGNAL AMPLITUDEsin x/x ENVELOPEx = π ( f/fC) Figure 28. The DAC Output Spectrum Rev. D | Page 17 of 32 AD9834 Data Sheet FUNCTIONAL DESCRIPTION SERIAL INTERFACE The AD9834 has a standard 3-wire serial interface that is com-patible with SPI, QSPI™, MICROWIRE™, and DSP interface standards. Data is loaded into the device as a 16-bit word under the control of a serial clock input (SCLK). The timing diagram for this operation is given in Figure 5. For a detailed example of programming the AD9833 and AD9834 devices, refer to the AN-1070 Application Note. The FSYNC input is a level triggered input that acts as a frame synchronization and chip enable. Data can only be transferred into the device when FSYNC is low. To start the serial data transfer, FSYNC should be taken low, observing the minimum FSYNC-to-SCLK falling edge setup time (t7). After FSYNC goes low, serial data is shifted into the input shift register of the device on the falling edges of SCLK for 16 clock pulses. FSYNC can be taken high after the 16th falling edge of SCLK, observing the minimum SCLK falling edge to FSYNC rising edge time (t8). Alternatively, FSYNC can be kept low for a multiple of 16 SCLK pulses and then brought high at the end of the data transfer. In this way, a continuous stream of 16-bit words can be loaded while FSYNC is held low, with FSYNC only going high after the 16th SCLK falling edge of the last word is loaded. The SCLK can be continuous, or alternatively, the SCLK can idle high or low between write operations but must be high when FSYNC goes low (t12). POWERING UP THE AD9834 The flow chart in Figure 31 shows the operating routine for the AD9834. When the AD9834 is powered up, the part should be reset. This resets appropriate internal registers to 0 to provide an analog output of midscale. To avoid spurious DAC outputs during AD9834 initialization, the RESET bit/pin should be set to 1 until the part is ready to begin generating an output. RESET does not reset the phase, frequency, or control registers. These registers contain invalid data, and, therefore, should be set to a known value by the user. The RESET bit/pin should then be set to 0 to begin generating an output. The data appears on the DAC output eight MCLK cycles after RESET is set to 0. LATENCY Latency is associated with each operation. When Pin FSELECT and Pin PSELECT change value, there is a pipeline delay before control is transferred to the selected register. When the t11 and t11A timing specifications are met (see Figure 4), FSELECT and PSELECT have latencies of eight MCLK cycles. When the t11 and t11A timing specifications are not met, the latency is increased by one MCLK cycle. Similarly, there is a latency associated with each asynchronous write operation. If a selected frequency/phase register is loaded with a new word, there is a delay of eight to nine MCLK cycles before the analog output changes. There is an uncertainty of one MCLK cycle because it depends on the position of the MCLK rising edge when the data is loaded into the destination register. The negative transition of the RESET and SLEEP functions are sampled on the internal falling edge of MCLK. Therefore, they also have a latency associated with them. CONTROL REGISTER The AD9834 contains a 16-bit control register that sets up the AD9834 as the user wants to operate it. All control bits, except MODE, are sampled on the internal negative edge of MCLK. Table 6 describes the individual bits of the control register. The different functions and the various output options from the AD9834 are described in more detail in the Frequency and Phase Registers section. To inform the AD9834 that the contents of the control register are to be altered, DB15 and DB14 must be set to 0 as shown in Table 5. Table 5. Control Register DB15 DB14 DB13 . . . DB0 0 0 CONTROL bits Rev. D | Page 18 of 32 Data Sheet AD9834 MUXSLEEP12SLEEP1OPBITENIOUTBIOUTCOMPARATORVINSIGN/PIBMUXMSBSIGNBIT OUT01MUX1001DIGITALOUTPUT(ENABLE)(LOWPOWER)10-BITDACDIVIDEBY2SINROMMODE+ OPBITENPHASEACCUMULATOR(28-BIT)02705-026 Figure 29. Function of Control Bits DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 B28 HLB FSEL PSEL PIN/SW RESET SLEEP1 SLEEP12 OPBITEN SIGN/PIB DIV2 0 MODE 0 Table 6. Description of Bits in the Control Register Bit Name Description DB13 B28 Two write operations are required to load a complete word into either of the frequency registers. B28 = 1 allows a complete word to be loaded into a frequency register in two consecutive writes. The first write contains the 14 LSBs of the frequency word and the next write contains the 14 MSBs. The first two bits of each 16-bit word define the frequency register the word is loaded to and should, therefore, be the same for both of the consecutive writes. Refer to Table 10 for the appropriate addresses. The write to the frequency register occurs after both words have been loaded. An example of a complete 28-bit write is shown in Table 11. Note however, that consecutive 28-bit writes to the same frequency register are not allowed, switch between frequency registers to do this type of function. B28 = 0, the 28-bit frequency register operates as two 14-bit registers, one containing the 14 MSBs and the other containing the 14 LSBs. This means that the 14 MSBs of the frequency word can be altered independent of the 14 LSBs, and vice versa. To alter the 14 MSBs or the 14 LSBs, a single write is made to the appropriate frequency address. The Control Bit DB12 (HLB) informs the AD9834 whether the bits to be altered are the 14 MSBs or 14 LSBs. DB12 HLB This control bit allows the user to continuously load the MSBs or LSBs of a frequency register ignoring the remaining 14 bits. This is useful if the complete 28-bit resolution is not required. HLB is used in conjunction with DB13 (B28). This control bit indicates whether the 14 bits being loaded are being transferred to the 14 MSBs or 14 LSBs of the addressed frequency register. DB13 (B28) must be set to 0 to be able to change the MSBs and LSBs of a frequency word separately. When DB13 (B28) = 1, this control bit is ignored. HLB = 1 allows a write to the 14 MSBs of the addressed frequency register. HLB = 0 allows a write to the 14 LSBs of the addressed frequency register. DB11 FSEL The FSEL bit defines whether the FREQ0 register or the FREQ1 register is used in the phase accumulator. See Table 8 to select a frequency register. DB10 PSEL The PSEL bit defines whether the PHASE0 register data or the PHASE1 register data is added to the output of the phase accumulator. See Table 9 to select a phase register. DB9 PIN/SW Functions that select frequency and phase registers, reset internal registers, and power down the DAC can be implemented using either software or hardware. PIN/SW selects the source of control for these functions. PIN/SW = 1 implies that the functions are being controlled using the appropriate control pins. PIN/SW = 0 implies that the functions are being controlled using the appropriate control bits. DB8 RESET RESET = 1 resets internal registers to 0, this corresponds to an analog output of midscale. RESET = 0 disables RESET. This function is explained in the RESET Function section. DB7 SLEEP1 SLEEP1 = 1, the internal MCLK is disabled. The DAC output remains at its present value as the NCO is no longer accumulating. SLEEP1 = 0, MCLK is enabled. This function is explained in the SLEEP Function section. DB6 SLEEP12 SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9834 is used to output the MSB of the DAC data. SLEEP12 = 0 implies that the DAC is active. This function is explained in the SLEEP Function section. Rev. D | Page 19 of 32 AD9834 Data Sheet Bit Name Description DB5 OPBITEN The function of this bit is to control whether there is an output at the SIGN BIT OUT pin. This bit should remain at 0 if the user is not using the SIGN BIT OUT pin. OPBITEN = 1 enables the SIGN BIT OUT pin. OPBITEN = 0, the SIGN BIT OUT output buffer is put into a high impedance state, therefore no output is available at the SIGN BIT OUT pin. DB4 SIGN/PIB The function of this bit is to control what is output at the SIGN BIT OUT pin. SIGN/PIB = 1, the on-board comparator is connected to SIGN BIT OUT. After filtering the sinusoidal output from the DAC, the waveform can be applied to the comparator to generate a square waveform. Refer to Table 17. SIGN/PIB = 0, the MSB (or MSB/2) of the DAC data is connected to the SIGN BIT OUT pin. Bit DIV2 controls whether it is the MSB or MSB/2 that is output. DB3 DIV2 DIV2 is used in association with SIGN/PIB and OPBITEN. Refer to Table 17. DIV2 = 1, the digital output is passed directly to the SIGN BIT OUT pin. DIV2 = 0, the digital output/2 is passed directly to the SIGN BIT OUT pin. DB2 Reserved This bit must always be set to 0. DB1 MODE The function of this bit is to control what is output at the IOUT pin/IOUTB pin. This bit should be set to 0 if the Control Bit OPBITEN = 1. MODE = 1, the SIN ROM is bypassed, resulting in a triangle output from the DAC. MODE = 0, the SIN ROM is used to convert the phase information into amplitude information, resulting in a sinusoidal signal at the output. See Table 18. DB0 Reserved This bit must always be set to 0. FREQUENCY AND PHASE REGISTERS The AD9834 contains two frequency registers and two phase registers. These are described in Table 7. Table 7. Frequency/Phase Registers Register Size Description FREQ0 28 bits Frequency Register 0. When either the FSEL bit or FSELECT pin = 0, this register defines the output frequency as a fraction of the MCLK frequency. FREQ1 28 bits Frequency Register 1. When either the FSEL bit or FSELECT pin = 1, this register defines the output frequency as a fraction of the MCLK frequency. PHASE0 12 bits Phase Offset Register 0. When either the PSEL bit or PSELECT pin = 0, the contents of this register are added to the output of the phase accumulator. PHASE1 12 bits Phase Offset Register 1. When either the PSEL bit or PSELECT pin = 1, the contents of this register are added to the output of the phase accumulator. The analog output from the AD9834 is fMCLK/228 × FREQREG where FREQREG is the value loaded into the selected frequency register. This signal is phase shifted by 2π/4096 × PHASEREG where PHASEREG is the value contained in the selected phase register. Consideration must be given to the relationship of the selected output frequency and the reference clock frequency to avoid unwanted output anomalies. Access to the frequency and phase registers is controlled by both the FSELECT and PSELECT pins, and the FSEL and PSEL control bits. If the Control Bit PIN/SW = 1, the pins control the function; whereas, if PIN/SW = 0, the bits control the function. This is outlined in Table 8 and Table 9. If the FSEL and PSEL bits are used, the pins should be held at CMOS logic high or low. Control of the frequency/phase registers is interchangeable from the pins to the bits. Table 8. Selecting a Frequency Register FSELECT FSEL PIN/SW Selected Register 0 X 1 FREQ0 REG 1 X 1 FREQ1 REG X 0 0 FREQ0 REG X 1 0 FREQ1 REG Table 9. Selecting a Phase Register PSELECT PSEL PIN/SW Selected Register 0 X 1 PHASE0 REG 1 X 1 PHASE1 REG X 0 0 PHASE0 REG X 1 0 PHASE1 REG The FSELECT pin and PSELECT pin are sampled on the internal falling edge of MCLK. It is recommended that the data on these pins does not change within a time window of the falling edge of MCLK (see Figure 4 for timing). If FSELECT or PSELECT changes value when a falling edge occurs, there is an uncertainty of one MCLK cycle because it pertains to when control is transferred to the other frequency/phase register. The flow charts in Figure 32 and Figure 33 show the routine for selecting and writing to the frequency and phase registers of the AD9834. Rev. D | Page 20 of 32 Data Sheet AD9834 WRITING TO A FREQUENCY REGISTER When writing to a frequency register, Bit DB15 and Bit DB14 give the address of the frequency register. Table 10. Frequency Register Bits DB15 DB14 DB13 . . . DB0 0 1 14 FREQ0 REG BITS 1 0 14 FREQ1 REG BITS If the user wants to alter the entire contents of a frequency register, two consecutive writes to the same address must be performed because the frequency registers are 28 bits wide. The first write contains the 14 LSBs, and the second write contains the 14 MSBs. For this mode of operation, Control Bit B28 (DB13) should be set to 1. An example of a 28-bit write is shown in Table 11. Note however that continuous writes to the same frequency register are not recommended. This results in intermediate updates during the writes. If a frequency sweep, or something similar, is required, it is recommended that users alternate between the two frequency registers. Table 11. Writing FFFC000 to FREQ0 REG SDATA Input Result of Input Word 0010 0000 0000 0000 Control word write (DB15, DB14 = 00), B28 (DB13) = 1, HLB (DB12) = X 0100 0000 0000 0000 FREQ0 REG write (DB15, DB14 = 01), 14 LSBs = 0000 0111 1111 1111 1111 FREQ0 REG write (DB15, DB14 = 01), 14 MSBs = 3FFF In some applications, the user does not need to alter all 28 bits of the frequency register. With coarse tuning, only the 14 MSBs are altered; though with fine tuning only the 14 LSBs are altered. By setting Control Bit B28 (DB13) to 0, the 28-bit frequency register operates as two 14-bit registers, one containing the 14 MSBs and the other containing the 14 LSBs. This means that the 14 MSBs of the frequency word can be altered independent of the 14 LSBs, and vice versa. Bit HLB (DB12) in the control register identifies the 14 bits that are being altered. Examples of this are shown in Table 12 and Table 13. Table 12. Writing 3FFF to the 14 LSBs of FREQ1 REG SDATA Input Result of Input Word 0000 0000 0000 0000 Control word write (DB15, DB14 = 00), B28 (DB13) = 0, HLB (DB12) = 0, that is, LSBs 1011 1111 1111 1111 FREQ1 REG write (DB15, DB14 = 10), 14 LSBs = 3FFF Table 13. Writing 00FF to the 14 MSBs of FREQ0 REG SDATA Input Result of Input Word 0001 0000 0000 0000 Control word write (DB15, DB14 = 00), B28 (DB13) = 0, HLB (DB12) = 1, that is, MSBs 0100 0000 1111 1111 FREQ0 REG write (DB15, DB14 = 01), 14 MSBs = 00FF WRITING TO A PHASE REGISTER When writing to a phase register, Bit DB15 and Bit DB14 are set to 11. Bit DB13 identifies which phase register is being loaded. Table 14. Phase Register Bits DB15 DB14 DB13 DB12 DB11 DB0 1 1 0 X MSB 12 PHASE0 bits LSB 1 1 1 X MSB 12 PHASE1 bits LSB RESET FUNCTION The RESET function resets appropriate internal registers to 0 to provide an analog output of midscale. RESET does not reset the phase, frequency, or control registers. When the AD9834 is powered up, the part should be reset. To reset the AD9834, set the RESET pin/bit to 1. To take the part out of reset, set the pin/bit to 0. A signal appears at the DAC output seven MCLK cycles after RESET is set to 0. The RESET function is controlled by both the RESET pin and the RESET control bit. If the Control Bit PIN/SW = 0, the RESET bit controls the function, whereas if PIN/SW = 1, the RESET pin controls the function. Table 15. Applying RESET RESET Pin RESET Bit PIN/SW Bit Result 0 X 1 No reset applied 1 X 1 Internal registers reset X 0 0 No reset applied X 1 0 Internal registers reset The effect of asserting the RESET pin is evident immediately at the output, that is, the zero-to-one transition of this pin is not sampled. However, the negative transition of RESET is sampled on the internal falling edge of MCLK. SLEEP FUNCTION Sections of the AD9834 that are not in use can be powered down to minimize power consumption by using the SLEEP function. The parts of the chip that can be powered down are the internal clock and the DAC. The DAC can be powered down through hardware or software. The pin/bits required for the SLEEP function are outlined in Table 16. Rev. D | Page 21 of 32 AD9834 Data Sheet Table 16. Applying the SLEEP Function SLEEP Pin SLEEP1 Bit SLEEP12 Bit PIN/SW Bit Result 0 X X 1 No power-down 1 X X 1 DAC powered down X 0 0 0 No power-down X 0 1 0 DAC powered down X 1 0 0 Internal clock disabled X 1 1 0 Both the DAC powered down and the internal clock disabled DAC Powered Down This is useful when the AD9834 is used to output the MSB of the DAC data only. In this case, the DAC is not required and can be powered down to reduce power consumption. Internal Clock Disabled When the internal clock of the AD9834 is disabled, the DAC output remains at its present value because the NCO is no longer accumulating. New frequency, phase, and control words can be written to the part when the SLEEP1 control bit is active. The synchronizing clock remains active, meaning that the selected frequency and phase registers can also be changed either at the pins or by using the control bits. Setting the SLEEP1 bit to 0 enables the MCLK. Any changes made to the registers when SLEEP1 is active are observed at the output after a certain latency. The effect of asserting the SLEEP pin is evident immediately at the output, that is, the zero-to-one transition of this pin is not sampled. However, the negative transition of SLEEP is sampled on the internal falling edge of MCLK. SIGN BIT OUT PIN The AD9834 offers a variety of outputs from the chip. The digital outputs are available from the SIGN BIT OUT pin. The available outputs are the comparator output or the MSB of the DAC data. The bits controlling the SIGN BIT OUT pin are outlined in Table 17. This pin must be enabled before use. The enabling/disabling of this pin is controlled by the Bit OPBITEN (DB5) in the control register. When OPBITEN = 1, this pin is enabled. Note that the MODE bit (DB1) in the control register should be set to 0 if OPBITEN = 1. Comparator Output The AD9834 has an on-board comparator. To connect this comparator to the SIGN BIT OUT pin, the SIGN/PIB (DB4) control bit must be set to 1. After filtering the sinusoidal output from the DAC, the waveform can be applied to the comparator to generate a square waveform. MSB from the NCO The MSB from the NCO can be output from the AD9834. By setting the SIGN/PIB (DB4) control bit to 0, the MSB of the DAC data is available at the SIGN BIT OUT pin. This is useful as a coarse clock source. This square wave can also be divided by two before being output. Bit DIV2 (DB3) in the control register controls the frequency of this output from the SIGN BIT OUT pin. Table 17. Various Outputs from SIGN BIT OUT OPBITEN Bit MODE Bit SIGN/PIB Bit DIV2 Bit SIGN BIT OUT Pin 0 X X X High impedance 1 0 0 0 DAC data MSB/2 1 0 0 1 DAC data MSB 1 0 1 0 Reserved 1 0 1 1 Comparator output 1 1 X X Reserved THE IOUT AND IOUTB PINS The analog outputs from the AD9834 are available from the IOUT and IOUTB pins. The available outputs are a sinusoidal output or a triangle output. Sinusoidal Output The SIN ROM converts the phase information from the frequency and phase registers into amplitude information, resulting in a sinusoidal signal at the output. To have a sinusoidal output from the IOUT and IOUTB pins, set Bit MODE (DB1) to 0. Triangle Output The SIN ROM can be bypassed so that the truncated digital output from the NCO is sent to the DAC. In this case, the output is no longer sinusoidal. The DAC produces 10-bit linear triangular function. To have a triangle output from the IOUT and IOUTB pins, set Bit MODE (DB1) to 1. Note that the SLEEP pin and SLEEP12 bit must be 0 (that is, the DAC is enabled) when using the IOUT and IOUTB pins. Table 18. Various Outputs from IOUT and IOUTB OPBITEN Bit MODE Bit IOUT and IOUTB Pins 0 0 Sinusoid 0 1 Triangle 1 0 Sinusoid 1 1 Reserved 3π/27π/211π/2VOUT MAXVOUT MIN02705-027 Figure 30. Triangle Output Rev. D | Page 22 of 32 Data Sheet AD9834 Rev. D | Page 23 of 32 APPLICATIONS INFORMATION Because of the various output options available from the part, the AD9834 can be configured to suit a wide variety of applications. One of the areas where the AD9834 is suitable is in modulation applications. The part can be used to perform simple modulation such as FSK. More complex modulation schemes such as GMSK and QPSK can also be implemented using the AD9834. In an FSK application, the two frequency registers of the AD9834 are loaded with different values. One frequency represents the space frequency, and the other represents the mark frequency. The digital data stream is fed to the FSELECT pin, causing the AD9834 to modulate the carrier frequency between the two values. The AD9834 has two phase registers, enabling the part to perform PSK. With phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount that is related to the bit stream that is input to the modulator. The AD9834 is also suitable for signal generator applications. With the on-board comparator, the device can be used to generate a square wave. With its low current consumption, the part is suitable for applications where it is used as a local oscillator. CHANGE PHASE? CHANGE FREQUENCY? NO NO NO NO YES NO YES NO YES YES YES YES YES YES DAC OUTPUT VOUT = VREFOUT × 18 × RLOAD/RSET × (1 + (SIN(2π(FREQREG × fMCLK × t/228 + PHASEREG/212)))) INITIALIZATION SEE FIGURE 32 SELECT DATA SOURCES SEE FIGURE 34 WAIT 8/9 MCLK CYCLES SEE TIMING DIAGRAM FIGURE 3 CHANGE PSEL/ PSELECT? CHANGE PHASE REGISTER? CHANGE DAC OUTPUT FROM SIN TO RAMP? CHANGE OUTPUT AT SIGN BIT OUT PIN? CHANGE FSEL/ FSELECT? CHANGE FREQUENCY REGISTER? CONTROL REGISTER WRITE DATA WRITE SEE FIGURE 33 02705-028 Figure 31. Flow Chart for Initialization and Operation AD9834 Data Sheet INITIALIZATIONAPPLY RESETUSING PINSET RESET PIN = 1USING PINUSING CONTROLBIT(CONTROL REGISTER WRITE)RESET = 1PIN/SW = 0(CONTROL REGISTER WRITE)PIN/SW = 1USING CONTROLBITSET RESET = 0SELECT FREQUENCY REGISTERSSELECT PHASE REGISTERS(CONTROL REGISTER WRITE)RESET BIT = 0FSEL = SELECTED FREQUENCY REGISTERPSEL = SELECTED PHASE REGISTERPIN/SW = 0(APPLY SIGNALS AT PINS)RESET PIN = 0FSELECT = SELECTED FREQUENCY REGISTERPSELECT = SELECTED PHASE REGISTERWRITE TO FREQUENCY AND PHASE REGISTERSFREQ0 REG = fOUT0/fMCLK × 228FREQ1 REG = fOUT1/fMCLK × 228PHASE0 AND PHASE1 REG = (PHASESHIFT × 212)/2π(SEE FIGURE 33)02705-029 Figure 32. Initialization NOYESDATA WRITENOYESYESNOYESNONOYESYESWRITE A FULL 28-BIT WORDTO A FREQUENCY REGISTER?(CONTROL REGISTER WRITE)B28 (D13) = 1WRITE TWO CONSECUTIVE16-BIT WORDS(SEE TABLE 11 FOR EXAMPLE)WRITE ANOTHER FULL28-BIT TO AFREQUENCY REGISTER?WRITE 14 MSBs OR LSBsTO A FREQUENCY REGISTER?(CONTROL REGISTER WRITE)B28 (D13) = 0HLB (D12) = 0/1WRITE A 16-BIT WORD(SEE TABLES 12 AND 13FOR EXAMPLES)WRITE 14 MSBs OR LSBsTO AFREQUENCY REGISTER?WRITE TO PHASEREGISTER?D15, D14 = 11D13 = 0/1 (CHOOSE THEPHASE REGISTER)D12 = XD11 ... D0 = PHASE DATA(16-BIT WRITE)WRITE TO ANOTHERPHASE REGISTER?02705-030 Figure 33. Data Write Rev. D | Page 24 of 32 Data Sheet AD9834 SELECT DATA SOURCESYESNOFSELECT AND PSELECTPINS BEING USED?(CONTROL REGISTER WRITE)PIN/SW = 0SET FSEL BITSET PSEL BITSET FSELECTAND PSELECT(CONTROL REGISTER WRITE)PIN/SW = 102705-031 Figure 34. Selecting Data Sources Rev. D | Page 25 of 32 AD9834 Data Sheet GROUNDING AND LAYOUT The printed circuit board (PCB) that houses the AD9834 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can easily be separated. A minimum etch technique is generally best for ground planes because it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD9834 is the only device requiring an AGND-to-DGND connection, the ground planes should be connected at the AGND and DGND pins of the AD9834. If the AD9834 is in a system where multiple devices require AGND-to-DGND connections, the connection should be made at one point only, establishing a star ground point as close as possible to the AD9834. Avoid running digital lines under the device because these couple noise onto the die. The analog ground plane should be allowed to run under the AD9834 to avoid noise coupling. The power supply lines to the AD9834 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other to reduce the effects of feed-through through the board. A microstrip technique is by far the best, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes and signals are placed on the other side. Good decoupling is important. The analog and digital supplies to the AD9834 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. All analog and digital supplies should be decoupled to AGND and DGND, respectively, with 0.1 μF ceramic capacitors in parallel with 10 μF tantalum capacitors. To achieve the best performance from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply is used to drive both the AVDD and DVDD of the AD9834, it is recommended that the system’s AVDD supply be used. This supply should have the recommended analog supply decoupling between the AVDD pins of the AD9834 and AGND, and the recommended digital supply decoupling capacitors between the DVDD pins and DGND. Proper operation of the comparator requires good layout strategy. The strategy must minimize the parasitic capacitance between VIN and the SIGN BIT OUT pin by adding isolation using a ground plane. For example, in a multilayered board, the VIN signal could be connected to the top layer, and the SIGN BIT OUT could be connected to the bottom layer so that isolation is provided by the power and ground planes between them. Rev. D | Page 26 of 32 Data Sheet AD9834 Rev. D | Page 27 of 32 INTERFACING TO MICROPROCESSORS The AD9834 has a standard serial interface that allows the part to interface directly with several microprocessors. The device uses an external serial clock to write the data/control information into the device. The serial clock can have a frequency of 40 MHz maximum. The serial clock can be continuous, or it can idle high or low between write operations. When data/control information is being written to the AD9834, FSYNC is taken low and is held low until the 16 bits of data are written into the AD9834. The FSYNC signal frames the 16 bits of information being loaded into the AD9834. AD9834 TO ADSP-21xx INTERFACE Figure 35 shows the serial interface between the AD9834 and the ADSP-21xx. The ADSP-21xx should be set up to operate in the SPORT transmit alternate framing mode (TFSW = 1). The ADSP-21xx is programmed through the SPORT control register and should be configured as follows:  Internal clock operation (ISCLK = 1)  Active low framing (INVTFS = 1)  16-bit word length (SLEN = 15)  Internal frame sync signal (ITFS = 1)  Generate a frame sync for each write (TFSR = 1) Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. The data is clocked out on each rising edge of the serial clock and clocked into the AD9834 on the SCLK falling edge. 1ADDITIONALPINS OMITTEDFORCLARITY. AD98341 FSYNC SDATA SCLK TFS DT SCLK ADSP-21xx1 02705-032 Figure 35. ADSP-21xx to AD9834 Interface AD9834 TO 68HC11/68L11 INTERFACE Figure 36 shows the serial interface between the AD9834 and the 68HC11/68L11 microcontroller. The microcontroller is configured as the master by setting Bit MSTR in the SPCR to 1, providing a serial clock on SCK while the MOSI output drives the serial data line SDATA. Because the microcontroller does not have a dedicated frame sync pin, the FSYNC signal is derived from a port line (PC7). The setup conditions for correct operation of the interface are as follows:  SCK idles high between write operations (CPOL = 0)  Data is valid on the SCK falling edge (CPHA = 1) When data is being transmitted to the AD9834, the FSYNC line is taken low (PC7). Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data into the AD9834, PC7 is held low after the first eight bits are transferred and a second serial write operation is performed to the AD9834. Only after the second eight bits have been transferred should FSYNC be taken high again. 1ADDITIONAL PINS OMITTED FOR CLARITY. AD98341 FSYNC SDATA SCLK 68HC11/68L111 PC7 MOSI SCK 02705-033 Figure 36. 68HC11/68L11 to AD9834 Interface AD9834 Data Sheet AD9834 TO 80C51/80L51 INTERFACE Figure 37 shows the serial interface between the AD9834 and the 80C51/80L51 microcontroller. The microcontroller is operated in Mode 0 so that TXD of the 80C51/80L51 drives SCLK of the AD9834, and RXD drives the serial data line (SDATA). The FSYNC signal is derived from a bit programmable pin on the port (P3.3 is shown in the diagram). When data is to be transmitted to the AD9834, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes, thus only eight falling SCLK edges occur in each cycle. To load the remaining eight bits to the AD9834, P3.3 is held low after the first eight bits have been transmitted, and a second write operation is initiated to transmit the second byte of data. P3.3 is taken high following the completion of the second write operation. SCLK should idle high between the two write operations. The 80C51/80L51 outputs the serial data in an LSB-first format. The AD9834 accepts the MSB first (the four MSBs being the control information, the next four bits being the address, and the eight LSBs containing the data when writing to a destination register). Therefore, the transmit routine of the 80C51/80L51 must take this into account and rearrange the bits so that the MSB is output first. 1ADDITIONAL PINS OMITTED FOR CLARITY.AD98341FSYNCSDATASCLK80C51/80L511P3.3RXDTXD02705-034 Figure 37. 80C51/80L51 to AD9834 Interface AD9834 TO DSP56002 INTERFACE Figure 38 shows the interface between the AD9834 and the DSP56002. The DSP56002 is configured for normal mode asynchronous operation with a gated internal clock (SYN = 0, GCK = 1, SCKD = 1). The frame sync pin is generated internally (SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and the frame sync signal frames the 16 bits (FSL = 0). The frame sync signal is available on Pin SC2, but needs to be inverted before being applied to the AD9834. The interface to the DSP56000/ DSP56001 is similar to that of the DSP56002. 1ADDITIONAL PINS OMITTED FOR CLARITY.AD98341FSYNCSDATASCLKDSP560021SC2STDSCK02705-035 Figure 38. DSP56002 to AD9834 Interface Rev. D | Page 28 of 32 Data Sheet AD9834 OUTLINE DIMENSIONS COMPLIANT TO JEDEC STANDARDS MO-153-AC20111106.40 BSC4.504.404.30PIN 16.606.506.40SEATINGPLANE0.150.050.300.190.65BSC1.20 MAX0.200.090.750.600.458°0°COPLANARITY0.10 Figure 39. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters ORDERING GUIDE Model1 Maximum MCLK (MHz) Temperature Range Package Description Package Option AD9834BRU 50 −40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD9834BRU-REEL 50 −40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD9834BRU-REEL7 50 −40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD9834BRUZ 50 −40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD9834BRUZ-REEL 50 −40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD9834BRUZ-REEL7 50 −40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD9834CRUZ 75 −40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD9834CRUZ-REEL7 75 −40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 1 Z = RoHS Compliant Part. Rev. D | Page 29 of 32 AD9834 Data Sheet NOTES Rev. D | Page 30 of 32 Data Sheet AD9834 NOTES Rev. D | Page 31 of 32 AD9834 Data Sheet NOTES ©2003–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02705-0-3/14(A) Rev. D | Page 32 of 32 STM32F405xx STM32F407xx ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Datasheet - production data Features • Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions • Memories – Up to 1 Mbyte of Flash memory – Up to 192+4 Kbytes of SRAM including 64- Kbyte of CCM (core coupled memory) data RAM – Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories • LCD parallel interface, 8080/6800 modes • Clock, reset and supply management – 1.8 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low power – Sleep, Stop and Standby modes – VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM • 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode • 2×12-bit D/A converters • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support • Up to 17 timers: up to twelve 16-bit and two 32- bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input • Debug mode – Serial wire debug (SWD) & JTAG interfaces – Cortex-M4 Embedded Trace Macrocell™ • Up to 140 I/O ports with interrupt capability – Up to 136 fast I/Os up to 84 MHz – Up to 138 5 V-tolerant I/Os • Up to 15 communication interfaces – Up to 3 × I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control) – Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock – 2 × CAN interfaces (2.0B Active) – SDIO interface • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII • 8- to 14-bit parallel camera interface up to 54 Mbytes/s • True random number generator • CRC calculation unit • 96-bit unique ID • RTC: subsecond accuracy, hardware calendar LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) LQFP144 (20 × 20 mm) FBGA UFBGA176 (10 × 10 mm) LQFP176 (24 × 24 mm) WLCSP90 Table 1. Device summary Reference Part number STM32F405xx STM32F405RG, STM32F405VG, STM32F405ZG, STM32F405OG, STM32F405OE STM32F407xx STM32F407VG, STM32F407IG, STM32F407ZG, STM32F407VE, STM32F407ZE, STM32F407IE www.st.com Contents STM32F405xx, STM32F407xx 2/185 DocID022152 Rev 4 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.1 ARM® Cortex™-M4F core with embedded Flash and SRAM . . . . . . . . 19 2.2.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 19 2.2.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 20 2.2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.9 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 22 2.2.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 28 2.2.18 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 28 2.2.19 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.20 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.22 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.23 Universal synchronous/asynchronous receiver transmitters (USART) . 33 2.2.24 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.25 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.26 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.27 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . 35 2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 35 2.2.29 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DocID022152 Rev 4 3/185 STM32F405xx, STM32F407xx Contents 2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 36 2.2.31 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 36 2.2.32 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.33 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.34 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.35 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.37 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.38 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.39 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.2 VCAP_1/VCAP_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 80 5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 80 5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 80 5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 102 Contents STM32F405xx, STM32F407xx 4/185 DocID022152 Rev 4 5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 108 5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 5.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.24 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.3.26 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 155 5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 156 5.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 A.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 171 A.2 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 173 A.3 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 DocID022152 Rev 4 5/185 STM32F405xx, STM32F407xx List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F405xx and STM32F407xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 13 Table 3. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 4. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 5. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 7. STM32F40x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 8. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 9. Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 10. STM32F40x register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 11. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 12. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 13. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 14. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 15. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 79 Table 16. VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 17. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 80 Table 18. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 80 Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 20. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 83 Table 21. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 22. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 23. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 24. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 88 Table 25. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 89 Table 26. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 27. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 28. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 29. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 30. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 31. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 33. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 34. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 35. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 36. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 37. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 38. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 39. Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 40. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 41. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 42. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 43. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 44. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 45. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 46. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 List of tables STM32F405xx, STM32F407xx 6/185 DocID022152 Rev 4 Table 47. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 48. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 49. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 50. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 51. Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 52. Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 53. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 54. SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 55. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 56. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 57. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 58. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 59. USB OTG FS electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 60. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 61. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 62. ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 63. Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 64. Dynamic characteristics: Ehternet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 65. Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 66. Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 67. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 68. ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 69. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 70. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 71. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 72. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 73. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 74. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 138 Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 139 Table 77. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Table 78. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Table 79. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Table 80. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Table 81. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 145 Table 82. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 85. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 86. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 87. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 88. Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 89. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 90. WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . 159 Table 91. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 160 Table 92. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 162 Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 164 Table 94. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . 167 DocID022152 Rev 4 7/185 STM32F405xx, STM32F407xx List of tables Table 96. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 97. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 98. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 List of figures STM32F405xx, STM32F407xx 8/185 DocID022152 Rev 4 List of figures Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64. . . . . . . . . . . . 15 Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 3. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. STM32F40x block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 7. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 24 Figure 8. PDR_ON and NRST control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 10. Startup in regulator OFF mode: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 11. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 28 Figure 12. STM32F40x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 13. STM32F40x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 14. STM32F40x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 15. STM32F40x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 16. STM32F40x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 17. STM32F40x WLCSP90 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 18. STM32F40x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 19. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 20. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 21. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 22. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 23. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 24. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF . . . . 85 Figure 25. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals ON . . . . . 85 Figure 26. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF . . . 86 Figure 27. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON . . . . 86 Figure 28. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . . 89 Figure 29. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . . 90 Figure 30. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 31. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 32. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 33. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 34. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 35. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 36. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 37. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 38. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 39. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 DocID022152 Rev 4 9/185 STM32F405xx, STM32F407xx List of figures Figure 40. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 41. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 42. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure 43. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 44. I2S master timing diagram (Philips protocol)(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 45. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 124 Figure 46. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Figure 47. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 48. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 49. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 50. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 51. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 133 Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 133 Figure 54. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 138 Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 139 Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 140 Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 59. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Figure 60. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 145 Figure 62. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Figure 63. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 148 Figure 64. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 148 Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 150 Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 151 Figure 69. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Figure 70. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Figure 71. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 154 Figure 72. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 154 Figure 73. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Figure 74. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Figure 75. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Figure 76. WLCSP90 - 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . . . 159 Figure 77. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 160 Figure 78. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 162 Figure 80. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 164 Figure 82. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Figure 84. LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 167 Figure 85. LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Figure 86. USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Figure 87. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 171 List of figures STM32F405xx, STM32F407xx 10/185 DocID022152 Rev 4 Figure 88. USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 172 Figure 89. USB controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Figure 90. MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 91. RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 92. RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 DocID022152 Rev 4 11/185 STM32F405xx, STM32F407xx Introduction 1 Introduction This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the STM32F4xx reference manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M4 core, please refer to the Cortex™-M4 programming manual (PM0214) available from www.st.com. Description STM32F405xx, STM32F407xx 12/185 DocID022152 Rev 4 2 Description The STM32F405xx and STM32F407xx family is based on the high-performance ARM® Cortex™-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The Cortex-M4 core with FPU will be referred to as Cortex-M4F throughout this document. The STM32F405xx and STM32F407xx family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true random number generator (RNG). They also feature standard and advanced communication interfaces. • Up to three I2Cs • Three SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. • Four USARTs plus two UARTs • An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI), • Two CANs • An SDIO/MMC interface • Ethernet and the camera interface available on STM32F407xx devices only. New advanced peripherals include an SDIO, an enhanced flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more), a camera interface for CMOS sensors. Refer to Table 2: STM32F405xx and STM32F407xx: features and peripheral counts for the list of peripherals available on each part number. The STM32F405xx and STM32F407xx family operates in the –40 to +105 °C temperature range from a 1.8 to 3.6 V power supply. The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor: refer to Section : Internal reset OFF. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F405xx and STM32F407xx family offers devices in various packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen. These features make the STM32F405xx and STM32F407xx microcontroller family suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances STM32F405xx, STM32F407xx Description DocID022152 Rev 4 13/185 Figure 5 shows the general block diagram of the device family. Table 2. STM32F405xx and STM32F407xx: features and peripheral counts Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix Flash memory in Kbytes 1024 512 512 1024 512 1024 512 1024 SRAM in Kbytes System 192(112+16+64) Backup 4 FSMC memory controller No Yes(1) Ethernet No Yes Timers Generalpurpose 10 Advanced -control 2 Basic 2 IWDG Yes WWDG Yes RTC Yes Random number generator Yes Description STM32F405xx, STM32F407xx 14/185 DocID022152 Rev 4 Communi cation interfaces SPI / I2S 3/2 (full duplex)(2) I2C 3 USART/ UART 4/2 USB OTG FS Yes USB OTG HS Yes CAN 2 SDIO Yes Camera interface No Yes GPIOs 51 72 82 114 72 82 114 140 12-bit ADC Number of channels 3 16 13 16 24 13 16 24 24 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 168 MHz Operating voltage 1.8 to 3.6 V(3) Operating temperatures Ambient temperatures: –40 to +85 °C /–40 to +105 °C Junction temperature: –40 to + 125 °C Package LQFP64 WLCSP90 LQFP100 LQFP144 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 1. For the LQFP100 and WLCSP90 packages, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). Table 2. STM32F405xx and STM32F407xx: features and peripheral counts Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix DocID022152 Rev 4 15/185 STM32F405xx, STM32F407xx Description 2.1 Full compatibility throughout the family The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pinto- pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle. The STM32F405xx and STM32F407xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The STM32F405xx and STM32F407xx, however, are not drop-in replacements for the STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F40x family remains simple as only a few pins are impacted. Figure 4, Figure 3, Figure 2, and Figure 1 give compatible board designs between the STM32F40x, STM32F2xxx, and STM32F10xxx families. Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64 31 1 16 17 32 48 33 64 49 47 VSS VSS VSS VSS 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F4xx configuration ai18489 Description STM32F405xx, STM32F407xx 16/185 DocID022152 Rev 4 Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package Figure 3. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package 20 49 1 25 26 50 75 51 100 76 73 19 VSS VSS VDD VSS VSS VSS 0 ΩΩ resistor or soldering bridge present for the STM32F10xxx configuration, not present in the STM32F4xx configuration ai18488c 99 (VSS) VDD VSS Two 0 Ω resistors connected to: - VSS for the STM32F10xx - VSS for the STM32F4xx VSS for STM32F10xx VDD for STM32F4xx - VSS, VDD or NC for the STM32F2xx ai18487d 31 71 1 36 37 72 108 73 144 109 VSS 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F4xx configuration 106 VSS 30 Two 0 Ω resistors connected to: - VSS for the STM32F10xx - VDD or signal from external power supply supervisor for the STM32F4xx VDD VSS VSS VSS 143 (PDR_ON) VDD VSS VSS for STM32F10xx VDD for STM32F4xx - VSS, VDD or NC for the STM32F2xx Signal from external power supply supervisor DocID022152 Rev 4 17/185 STM32F405xx, STM32F407xx Description Figure 4. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages MS19919V3 1 44 45 88 132 89 176 133 Two 0 Ω resistors connected to: - VSS, VDD or NC for the STM32F2xx - VDD or signal from external power supply supervisor for the STM32F4xx 171 (PDR_ON) VDDVSS Signal from external power supply supervisor Description STM32F405xx, STM32F407xx 18/185 DocID022152 Rev 4 2.2 Device overview Figure 5. STM32F40x block diagram 1. The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 84 MHz or 168 MHz, depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 2. The camera interface and ethernet are available only on STM32F407xx devices. MS19920V3 GPIO PORT A AHB/APB2 140 AF PA[15:0] TIM1 / PWM 4 compl. channels (TIM1_CH1[1:4]N, 4 channels (TIM1_CH1[1:4]ETR, BKIN as AF RX, TX, CK, CTS, RTS as AF MOSI, MISO, SCK, NSS as AF APB 1 30M Hz 8 analog inputs common to the 3 ADCs VDDREF_ADC MOSI/SD, MISO/SD_ext, SCK/CK NSS/WS, MCK as AF TX, RX DAC1_OUT as AF ITF WWDG 4 KB BKPSRAM RTC_AF1 OSC32_IN OSC32_OUT VDDA, VSSA NRST 16b SDIO / MMC D[7:0] CMD, CK as AF VBAT = 1.65 to 3.6 V DMA2 SCL, SDA, SMBA as AF JTAG & SW ARM Cortex-M4 168 MHz ETM NVIC MPU TRACECLK TRACED[3:0] Ethernet MAC 10/100 DMA/ FIFO MII or RMII as AF MDIO as AF USB OTG HS DP, DM ULPI:CK, D[7:0], DIR, STP, NXT ID, VBUS, SOF DMA2 8 Streams FIFO ART ACCEL/ CACHE SRAM 112 KB CLK, NE [3:0], A[23:0], D[31:0], OEN, WEN, NBL[3:0], NL, NREG, NWAIT/IORDY, CD INTN, NIIS16 as AF RNG Camera interface HSYNC, VSYNC PUIXCLK, D[13:0] PHY USB OTG FS DP DM ID, VBUS, SOF FIFO AHB1 168 MHz PHY FIFO @VDDA @VDDA POR/PDR BOR Supply supervision @VDDA PVD Int POR reset XTAL 32 kHz MAN AGT RTC RC HS FCLK RC LS PWR interface IWDG @VBAT AWU Reset & clock control P L L1&2 PCLKx VDD = 1.8 to 3.6 V VSS VCAP1, VCPA2 Voltage regulator 3.3 to 1.2 V VDD Power managmt Backup register RTC_AF1 AHB bus-matrix 8S7M LS 2 channels as AF DAC1 DAC2 Flash up to 1 MB SRAM, PSRAM, NOR Flash, PC Card (ATA), NAND Flash External memory controller (FSMC) TIM6 TIM7 TIM2 TIM3 TIM4 TIM5 TIM12 TIM13 TIM14 USART2 USART3 UART4 UART5 SP3/I2S3 I2C1/SMBUS I2C2/SMBUS I2C3/SMBUS bxCAN1 bxCAN2 SPI1 EXT IT. WKUP D-BUS FIFO FPU APB142 MHz (max) SRAM 16 KB CCM data RAM 64 KB AHB3 AHB2 168 MHz NJTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO I-BUS S-BUS DMA/ FIFO DMA1 8 Streams FIFO PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] PH[15:0] PI[11:0] GPIO PORT B GPIO PORT C GPIO PORT D GPIO PORT E GPIO PORT F GPIO PORT G GPIO PORT H GPIO PORT I TIM8 / PWM 16b 4 compl. channels (TIM1_CH1[1:4]N, 4 channels (TIM1_CH1[1:4]ETR, BKIN as AF 1 channel as AF 1 channel as AF RX, TX, CK, CTS, RTS as AF 8 analog inputs common to the ADC1 & 2 8 analog inputs for ADC3 DAC2_OUT as AF 16b 16b SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF MOSI/SD, MISO/SD_ext, SCK/CK NSS/WS, MCK as AF TX, RX RX, TX as AF RX, TX as AF RX, TX as AF CTS, RTS as AF RX, TX as AF CTS, RTS as AF 1 channel as AF smcard irDA smcard irDA 16b 16b 16b 1 channel as AF 2 channels as AF 32b 16b 16b 32b 4 channels 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF DMA1 AHB/APB1 LS OSC_IN OSC_OUT HCLKx XTAL OSC 4- 16MHz FIFO SP2/I2S2 NIORD, IOWR, INT[2:3] ADC3 ADC2 ADC1 Temperature sensor IF TIM9 16b TIM10 16b TIM11 16b smcard irDA USART1 irDA smcard USART6 APB2 84 MHz @VDD @VDD @VDDA DocID022152 Rev 4 19/185 STM32F405xx, STM32F407xx Description 2.2.1 ARM® Cortex™-M4F core with embedded Flash and SRAM The ARM Cortex-M4F processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM Cortex-M4F 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F405xx and STM32F407xx family is compatible with all ARM tools and software. Figure 5 shows the general block diagram of the STM32F40x family. Note: Cortex-M4F is binary compatible with Cortex-M3. 2.2.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard ARM® Cortex™-M4F processors. It balances the inherent performance advantage of the ARM Cortex-M4F over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 210 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 168 MHz. 2.2.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 2.2.4 Embedded Flash memory The STM32F40x devices embed a Flash memory of 512 Kbytes or 1 Mbytes available for storing programs and data. Description STM32F405xx, STM32F407xx 20/185 DocID022152 Rev 4 2.2.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 2.2.6 Embedded SRAM All STM32F40x products embed: • Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM RAM memory is accessed (read/write) at CPU clock speed with 0 wait states. • 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 2.2.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. DocID022152 Rev 4 21/185 STM32F405xx, STM32F407xx Description Figure 6. Multi-AHB matrix 2.2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Camera interface (DCMI) • ADC. ARM Cortex-M4 GP DMA1 GP DMA2 MAC Ethernet USB OTG HS Bus matrix-S S0 S1 S2 S3 S4 S5 S6 S7 ICODE DCODE ACCEL Flash memory SRAM1 112 Kbyte SRAM2 16 Kbyte AHB1 peripherals AHB2 FSMC Static MemCtl M0 M1 M2 M3 M4 M5 M6 I-bus D-bus S-bus DMA_PI DMA_MEM1 DMA_MEM2 DMA_P2 ETHERNET_M USB_HS_M ai18490c CCM data RAM 64-Kbyte APB1 APB2 peripherals Description STM32F405xx, STM32F407xx 22/185 DocID022152 Rev 4 2.2.9 Flexible static memory controller (FSMC) The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: • Write FIFO • Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz. LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.2.10 Nested vectored interrupt controller (NVIC) The STM32F405xx and STM32F407xx embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 82 maskable interrupt channels plus the 16 interrupt lines of the Cortex™-M4F. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 2.2.11 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines. 2.2.12 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 168 MHz. Similarly, full interrupt management of the PLL DocID022152 Rev 4 23/185 STM32F405xx, STM32F407xx Description clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz. The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 2.2.13 Boot modes At startup, boot pins are used to select one out of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade). 2.2.14 Power supply schemes • VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. • VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Refer to Figure 21: Power supply scheme for more details. Note: VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). Refer to Table 2 in order to identify the packages supporting this option. 2.2.15 Power supply supervisor Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On all other packages, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR threshold levels, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. Description STM32F405xx, STM32F407xx 24/185 DocID022152 Rev 4 The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled with the PDR_ON pin. An external power supply supervisor should monitor VDD and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to this external power supply supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset OFF. Figure 7. Power supply supervisor interconnection with internal reset OFF 1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range. The VDD specified threshold, below which the device must be maintained under reset, is 1.8 V (see Figure 7). This supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range. A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled • The brownout reset (BOR) circuitry is disabled • The embedded programmable voltage detector (PVD) is disabled • VBAT functionality is no more available and VBAT pin should be connected to VDD All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset through the PDR_ON signal. MS31383V3 NRST VDD PDR_ON External VDD power supply supervisor Ext. reset controller active when VDD < 1.7 V or 1.8 V (1) VDD Application reset signal (optional) DocID022152 Rev 4 25/185 STM32F405xx, STM32F407xx Description Figure 8. PDR_ON and NRST control with internal reset OFF 1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range. 2.2.16 Voltage regulator The regulator has four operating modes: • Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down • Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when regulator is ON: • MR is used in the nominal regulation mode (With different voltage scaling in Run) In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. Refer to Table 14: General operating conditions. • LPR is used in the Stop modes The LP regulator mode is configured by software when entering Stop mode. • Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost) MS19009V6 VDD time PDR = 1.7 V or 1.8 V (1) time NRST PDR_ON PDR_ON Reset by other source than power supply supervisor Description STM32F405xx, STM32F407xx 26/185 DocID022152 Rev 4 Two external ceramic capacitors should be connected on VCAP_1 & VCAP_2 pin. Refer to Figure 21: Power supply scheme and Figure 16: VCAP_1/VCAP_2 operating conditions. All packages have regulator ON feature. Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not manage internally, the external voltage value must be aligned with the targetted maximum frequency. Refer to Table 14: General operating conditions. The two 2.2 μF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer to Figure 21: Power supply scheme When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode the following features are no more supported: • PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. • As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. Figure 9. Regulator OFF ai18498V4 External VCAP_1/2 power supply supervisor Ext. reset controller active when VCAP_1/2 < Min V12 V12 VCAP_1 VCAP_2 BYPASS_REG VDD PA0 NRST Application reset signal (optional) VDD V12 DocID022152 Rev 4 27/185 STM32F405xx, STM32F407xx Description The following conditions must be respected: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. • If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.8 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.8 V (see Figure 10). • Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.8 V, then PA0 could be asserted low externally (see Figure 11). • If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.8 V, then a reset must be asserted on PA0 pin. Note: The minimum value of V12 depends on the maximum frequency targeted in the application (see Table 14: General operating conditions). Figure 10. Startup in regulator OFF mode: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 1. This figure is valid both whatever the internal reset mode (onON or OFFoff). 2. PDR = 1.7 V for reduced temperature range; PDR = 1.8 V for all temperature ranges. ai18491e VDD time Min V12 PDR = 1.7 V or 1.8 V (2) VCAP_1/VCAP_2 V12 NRST time Description STM32F405xx, STM32F407xx 28/185 DocID022152 Rev 4 Figure 11. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization 1. This figure is valid both whatever the internal reset mode (onON or offOFF). 2. PDR = 1.7 V for a reduced temperature range; PDR = 1.8 V for all temperature ranges. 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability 2.2.18 Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F405xx and STM32F407xx includes: • The real-time clock (RTC) • 4 Kbytes of backup SRAM • 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC VDD time Min V12 VCAP_1/VCAP_2 V12 PA0 asserted externally NRST time ai18492d PDR = 1.7 V or 1.8 V (2) Table 3. Regulator ON/OFF and internal reset ON/OFF availability Regulator ON Regulator OFF Internal reset ON Internal reset OFF LQFP64 LQFP100 Yes No Yes No LQFP144 LQFP176 Yes PDR_ON set to VDD Yes PDR_ON connected to an external power supply supervisor WLCSP90 UFBGA176 Yes BYPASS_REG set to VSS Yes BYPASS_REG set to VDD DocID022152 Rev 4 29/185 STM32F405xx, STM32F407xx Description has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 μs to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode. This memory area is disabled by default to minimize power consumption (see Section 2.2.19: Low-power modes). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 2.2.19: Low-power modes). Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 2.2.19 Low-power modes The STM32F405xx and STM32F407xx support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the V12 domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup). • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire V12 domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Description STM32F405xx, STM32F407xx 30/185 DocID022152 Rev 4 Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. The standby mode is not supported when the embedded voltage regulator is bypassed and the V12 domain is controlled by an external power. 2.2.20 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (internal reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. 2.2.21 Timers and watchdogs The STM32F405xx and STM32F407xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 4 compares the features of the advanced-control, general-purpose and basic timers. Table 4. Timer feature comparison Timer type Timer Counter resolutio n Counter type Prescaler factor DMA request generatio n Capture/ compare channels Complementar y output Max interface clock (MHz) Max timer clock (MHz) Advanced -control TIM1, TIM8 16-bit Up, Down, Up/dow n Any integer between 1 and 65536 Yes 4 Yes 84 168 DocID022152 Rev 4 31/185 STM32F405xx, STM32F407xx Description Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge- or center-aligned modes) • One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0- 100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. General purpose TIM2, TIM5 32-bit Up, Down, Up/dow n Any integer between 1 and 65536 Yes 4 No 42 84 TIM3, TIM4 16-bit Up, Down, Up/dow n Any integer between 1 and 65536 Yes 4 No 42 84 TIM9 16-bit Up Any integer between 1 and 65536 No 2 No 84 168 TIM10 , TIM11 16-bit Up Any integer between 1 and 65536 No 1 No 84 168 TIM12 16-bit Up Any integer between 1 and 65536 No 2 No 42 84 TIM13 , TIM14 16-bit Up Any integer between 1 and 65536 No 1 No 42 84 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 42 84 Table 4. Timer feature comparison (continued) Timer type Timer Counter resolutio n Counter type Prescaler factor DMA request generatio n Capture/ compare channels Complementar y output Max interface clock (MHz) Max timer clock (MHz) Description STM32F405xx, STM32F407xx 32/185 DocID022152 Rev 4 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F40x devices (see Table 4 for differences). • TIM2, TIM3, TIM4, TIM5 The STM32F40x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16- bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. • TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. DocID022152 Rev 4 33/185 STM32F405xx, STM32F407xx Description SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: • A 24-bit downcounter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source. 2.2.22 Inter-integrated circuit interface (I²C) Up to three I²C bus interfaces can operate in multimaster and slave modes. They can support the Standard-mode (up to 100 kHz) and Fast-mode (up to 400 kHz) . They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 2.2.23 Universal synchronous/asynchronous receiver transmitters (USART) The STM32F405xx and STM32F407xx embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous receiver transmitters (UART4 and UART5). These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 10.5 Mbit/s. The other available interfaces communicate at up to 5.25 Mbit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. Description STM32F405xx, STM32F407xx 34/185 DocID022152 Rev 4 2.2.24 Serial peripheral interface (SPI) The STM32F40x feature up to three SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 can communicate at up to 42 Mbits/s, SPI2 and SPI3 can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. 2.2.25 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and half-duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. 2.2.26 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S application. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. Table 5. USART feature comparison USART name Standard features Modem (RTS/ CTS) LIN SPI master irDA Smartcard (ISO 7816) Max. baud rate in Mbit/s (oversampling by 16) Max. baud rate in Mbit/s (oversampling by 8) APB mapping USART1 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) USART2 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) USART3 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) UART4 X - X - X - 2.62 5.25 APB1 (max. 42 MHz) UART5 X - X - X - 2.62 5.25 APB1 (max. 42 MHz) USART6 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) DocID022152 Rev 4 35/185 STM32F405xx, STM32F407xx Description The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S flow with an external PLL (or Codec output). 2.2.27 Secure digital input/output interface (SDIO) An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support Peripheral available only on the STM32F407xx devices. The STM32F407xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard mediumindependent interface (MII) or a reduced medium-independent interface (RMII). The STM32F407xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F407xx MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the STM32F407xx. The STM32F407xx includes the following features: • Supports 10 and 100 Mbit/s rates • Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F40x reference manual for details) • Tagged MAC frame support (VLAN support) • Half-duplex (CSMA/CD) and full-duplex operation • MAC control sublayer (control frames) support • 32-bit CRC generation and removal • Several address filtering modes for physical and multicast address (multicast and group addresses) • 32-bit status code for each transmitted or received frame • Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. • Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input • Triggers interrupt when system time becomes greater than target time Description STM32F405xx, STM32F407xx 36/185 DocID022152 Rev 4 2.2.29 Controller area network (bxCAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN. 2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) The STM32F405xx and STM32F407xx embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 4 bidirectional endpoints • 8 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected 2.2.31 Universal serial bus on-the-go high-speed (OTG_HS) The STM32F405xx and STM32F407xx devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 6 bidirectional endpoints • 12 host channels with periodic OUT support • Internal FS OTG PHY support • External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. • Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor) • for OTG/Host modes, a power switch is needed in case bus-powered devices are connected DocID022152 Rev 4 37/185 STM32F405xx, STM32F407xx Description 2.2.32 Digital camera interface (DCMI) The camera interface is not available in STM32F405xx devices. STM32F407xx products embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features: • Programmable polarity for the input pixel clock and synchronization signals • Parallel data communication can be 8-, 10-, 12- or 14-bit • Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) • Supports continuous mode or snapshot (a single frame) mode • Capability to automatically crop the image 2.2.33 Random number generator (RNG) All STM32F405xx and STM32F407xx products embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 2.2.34 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 84 MHz. 2.2.35 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: • Simultaneous sample and hold • Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer. 2.2.36 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 V and 3.6 V. The temperature sensor is internally Description STM32F405xx, STM32F407xx 38/185 DocID022152 Rev 4 connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.2.37 Digital-to-analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: • two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • left or right data alignment in 12-bit mode • synchronized update capability • noise-wave generation • triangular-wave generation • dual DAC channel independent or simultaneous conversions • DMA capability for each channel • external triggers for conversion • input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 2.2.38 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.2.39 Embedded Trace Macrocell™ The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F40x through a small number of ETM pins to an external hardware trace port analyser (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. DocID022152 Rev 4 39/185 STM32F405xx, STM32F407xx Pinouts and pin description 3 Pinouts and pin description Figure 12. STM32F40x LQFP64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VBAT PC14 PC15 NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0_WKUP PA1 PA2 VDD PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VCAP_1 VDD LQFP64 ai18493b PC13 PH0 PH1 VSS Pinouts and pin description STM32F405xx, STM32F407xx 40/185 DocID022152 Rev 4 Figure 13. STM32F40x LQFP100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE2 PE3 PE4 PE5 PE6 VBAT PC14 PC15 VSS VDD PH0 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 VDD VSS VCAP_2 PA13 PA12 PA 11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ai18495c LQFP100 PC13 PH1 DocID022152 Rev 4 41/185 STM32F405xx, STM32F407xx Pinouts and pin description Figure 14. STM32F40x LQFP144 pinout VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PE2 VDD PE3 VSS PE4 PE5 PA13 PE6 PA12 VBAT PA11 PC13 PA10 PC14 PA9 PC15 PA8 PF0 PC9 PF1 PC8 PF2 PC7 PF3 PC6 PF4 VDD PF5 VSS VSS PG8 VDD PG7 PF6 PG6 PF7 PG5 PF8 PG4 PF9 PG3 PF10 PG2 PH0 PD15 PH1 PD14 NRST VDD PC0 VSS PC1 PD13 PC2 PD12 PC3 PD11 VSSA VDD PD10 PD9 VREF+ PD8 VDDA PB15 PA0 PB14 PA1 PB13 PA2 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 109 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 72 LQFP144 120 119 118 117 116 115 114 113 112 111 110 61 62 63 64 65 66 67 68 69 70 71 26 27 28 29 30 31 32 33 34 35 36 83 82 81 80 79 78 77 76 75 74 73 ai18496b VCAP_2 VSS Pinouts and pin description STM32F405xx, STM32F407xx 42/185 DocID022152 Rev 4 Figure 15. STM32F40x LQFP176 pinout MS19916V3 PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PI7 PI6 PE2 PE3 PE4 PE5 PA13 PE6 PA12 VBAT PA11 PI8 PA10 PC14 PA9 PC15 PA8 PF0 PC9 PF1 PC8 PF2 PC7 PF3 PC6 PF4 PF5 PG8 PG7 PF6 PG6 PF7 PG5 PF8 PG4 PF9 PG3 PF10 PG2 PH0 PD15 PH1 PD14 NRST V PC0 V PC1 PD13 PC2 PD12 PC3 PD11 PD10 PD9 VREF+ PD8 PB15 PA0 PB14 PA1 PB13 PA2 PB12 PA3 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 141 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 80 LQFP176 152 151 150 149 148 147 146 145 144 143 142 69 70 71 72 73 74 75 76 77 78 79 26 27 28 29 30 31 32 33 34 35 36 107 106 105 104 103 102 101 100 99 98 89 PI4 PA15 PA14 PI3 PI2 PI5 140 139 138 137 136 135 134 133 PH4 PH5 PH6 PH7 PH8 PH9 PH10 PH11 88 81 82 83 84 85 86 87 PI1 PI0 PH15 PH14 PH13 PH12 96 95 94 93 92 91 90 97 37 38 39 40 41 42 43 44 PC13 PI9 PI10 PI11 VSS PH2 PH3 VDD VSS VDD VDDA VSSA VDDA BYPASS_REG VDD VDD VSS VDD VCAP_1 VDD VSS VDD VCAP_2 VSS VDD VSS VDD VSS VDD VSS VDD VDD VSS VDD VSS VDD DocID022152 Rev 4 43/185 STM32F405xx, STM32F407xx Pinouts and pin description Figure 16. STM32F40x UFBGA176 ballout 1. This figure shows the package top view. ai18497b 1 2 3 9 10 11 12 13 14 15 A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13 B PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12 C VBAT PI7 PI6 PI5 VDD PDR_ON VDD VDD VDD PG9 PD5 PD1 PI3 PI2 PA11 D PC13 PI8 PI9 PI4 BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10 E PC14 PF0 PI10 PI11 PH13 PH14 PI0 PA9 F PC15 VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP_2 PC9 PA8 G PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7 H PH1 PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDD PG8 PC6 J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6 K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3 L PF10 PF9 PF8 BYPASS_ REG PH11 PH10 PD15 PG2 M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS VCAP_1 PH6 PH8 PH9 PD14 PD13 N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10 P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8 R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15 VSS 4 5 6 7 8 Pinouts and pin description STM32F405xx, STM32F407xx 44/185 DocID022152 Rev 4 Figure 17. STM32F40x WLCSP90 ballout 1. This figure shows the package bump view. A VBAT PC13 PDR_ON PB4 PD7 PD4 PC12 B PC15 VDD PB7 PB3 PD6 PD2 PA15 C PA0 VSS PB6 PD5 PD1 PC11 PI0 D PC2 PB8 PA13 E PC3 VSS F PH1 PA1 G NRST H VSSA J PA2 PA 4 PA7 PB2 PE11 PB11 PB12 MS30402V1 1 PA14 PI1 PA12 PA10 PA9 PC0 PC9 PC8 PH0 PB13 PC6 PD14 PD12 PE8 PE12 BYPASS_ REG PD9 PD8 PE9 PB14 10 9 8 7 6 5 4 3 2 VDD PC14 VCAP_2 PA11 PB5 PD0 PC10 PA8 VSS VDD VSS VDD PC7 VDD PE10 PE14 VCAP_1 PD15 PE13 PE15 PD10 PD11 PA3 PA6 PB1 PB10 PB15 PB9 BOOT0 VDDA PA5 PB0 PE7 Table 6. Legend/abbreviations used in the pinout table Name Abbreviation Definition Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin type S Supply pin I Input only pin I/O Input / output pin I/O structure FT 5 V tolerant I/O TTa 3.3 V tolerant I/O directly connected to ADC B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers DocID022152 Rev 4 45/185 STM32F405xx, STM32F407xx Pinouts and pin description Table 7. STM32F40x pin and ball definitions Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 - - 1 1 A2 1 PE2 I/O FT TRACECLK/ FSMC_A23 / ETH_MII_TXD3 / EVENTOUT - - 2 2 A1 2 PE3 I/O FT TRACED0/FSMC_A19 / EVENTOUT - - 3 3 B1 3 PE4 I/O FT TRACED1/FSMC_A20 / DCMI_D4/ EVENTOUT - - 4 4 B2 4 PE5 I/O FT TRACED2 / FSMC_A21 / TIM9_CH1 / DCMI_D6 / EVENTOUT - - 5 5 B3 5 PE6 I/O FT TRACED3 / FSMC_A22 / TIM9_CH2 / DCMI_D7 / EVENTOUT 1 A10 6 6 C1 6 VBAT S - - - - D2 7 PI8 I/O FT (2)( 3) EVENTOUT RTC_TAMP1, RTC_TAMP2, RTC_TS 2 A9 7 7 D1 8 PC13 I/O FT (2) (3) EVENTOUT RTC_OUT, RTC_TAMP1, RTC_TS 3 B10 8 8 E1 9 PC14/OSC32_IN (PC14) I/O FT (2)( 3) EVENTOUT OSC32_IN(4) 4 B9 9 9 F1 10 PC15/ OSC32_OUT (PC15) I/O FT (2)( 3) EVENTOUT OSC32_OUT(4) - - - - D3 11 PI9 I/O FT CAN1_RX / EVENTOUT - - - - E3 12 PI10 I/O FT ETH_MII_RX_ER / EVENTOUT - - - - E4 13 PI11 I/O FT OTG_HS_ULPI_DIR / EVENTOUT - - - - F2 14 VSS S - - - - F3 15 VDD S - - - 10 E2 16 PF0 I/O FT FSMC_A0 / I2C2_SDA / EVENTOUT Pinouts and pin description STM32F405xx, STM32F407xx 46/185 DocID022152 Rev 4 - - - 11 H3 17 PF1 I/O FT FSMC_A1 / I2C2_SCL / EVENTOUT - - - 12 H2 18 PF2 I/O FT FSMC_A2 / I2C2_SMBA / EVENTOUT - - - 13 J2 19 PF3 I/O FT (4) FSMC_A3/EVENTOUT ADC3_IN9 - - - 14 J3 20 PF4 I/O FT (4) FSMC_A4/EVENTOUT ADC3_IN14 - - - 15 K3 21 PF5 I/O FT (4) FSMC_A5/EVENTOUT ADC3_IN15 - C9 10 16 G2 22 VSS S - B8 11 17 G3 23 VDD S - - - 18 K2 24 PF6 I/O FT (4) TIM10_CH1 / FSMC_NIORD/ EVENTOUT ADC3_IN4 - - - 19 K1 25 PF7 I/O FT (4) TIM11_CH1/FSMC_NREG / EVENTOUT ADC3_IN5 - - - 20 L3 26 PF8 I/O FT (4) TIM13_CH1 / FSMC_NIOWR/ EVENTOUT ADC3_IN6 - - - 21 L2 27 PF9 I/O FT (4) TIM14_CH1 / FSMC_CD/ EVENTOUT ADC3_IN7 - - - 22 L1 28 PF10 I/O FT (4) FSMC_INTR/ EVENTOUT ADC3_IN8 5 F10 12 23 G1 29 PH0/OSC_IN (PH0) I/O FT EVENTOUT OSC_IN(4) 6 F9 13 24 H1 30 PH1/OSC_OUT (PH1) I/O FT EVENTOUT OSC_OUT(4) 7 G10 14 25 J1 31 NRST I/O RS T 8 E10 15 26 M2 32 PC0 I/O FT (4) OTG_HS_ULPI_STP/ EVENTOUT ADC123_IN10 9 - 16 27 M3 33 PC1 I/O FT (4) ETH_MDC/ EVENTOUT ADC123_IN11 10 D10 17 28 M4 34 PC2 I/O FT (4) SPI2_MISO / OTG_HS_ULPI_DIR / ETH_MII_TXD2 /I2S2ext_SD/ EVENTOUT ADC123_IN12 Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 47/185 STM32F405xx, STM32F407xx Pinouts and pin description 11 E9 18 29 M5 35 PC3 I/O FT (4) SPI2_MOSI / I2S2_SD / OTG_HS_ULPI_NXT / ETH_MII_TX_CLK/ EVENTOUT ADC123_IN13 - - 19 30 G3 36 VDD S 12 H10 20 31 M1 37 VSSA S - - - - N1 - VREF– S - - 21 32 P1 38 VREF+ S 13 G9 22 33 R1 39 VDDA S 14 C10 23 34 N3 40 PA0/WKUP (PA0) I/O FT (5) USART2_CTS/ UART4_TX/ ETH_MII_CRS / TIM2_CH1_ETR/ TIM5_CH1 / TIM8_ETR/ EVENTOUT ADC123_IN0/WKUP(4 ) 15 F8 24 35 N2 41 PA1 I/O FT (4) USART2_RTS / UART4_RX/ ETH_RMII_REF_CLK / ETH_MII_RX_CLK / TIM5_CH2 / TIM2_CH2/ EVENTOUT ADC123_IN1 16 J10 25 36 P2 42 PA2 I/O FT (4) USART2_TX/TIM5_CH3 / TIM9_CH1 / TIM2_CH3 / ETH_MDIO/ EVENTOUT ADC123_IN2 - - - - F4 43 PH2 I/O FT ETH_MII_CRS/EVENTOU T - - - - G4 44 PH3 I/O FT ETH_MII_COL/EVENTOU T - - - - H4 45 PH4 I/O FT I2C2_SCL / OTG_HS_ULPI_NXT/ EVENTOUT - - - - J4 46 PH5 I/O FT I2C2_SDA/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 48/185 DocID022152 Rev 4 17 H9 26 37 R2 47 PA3 I/O FT (4) USART2_RX/TIM5_CH4 / TIM9_CH2 / TIM2_CH4 / OTG_HS_ULPI_D0 / ETH_MII_COL/ EVENTOUT ADC123_IN3 18 E5 27 38 - - VSS S D9 L4 48 BYPASS_REG I FT 19 E4 28 39 K4 49 VDD S 20 J9 29 40 N4 50 PA4 I/O TTa (4) SPI1_NSS / SPI3_NSS / USART2_CK / DCMI_HSYNC / OTG_HS_SOF/ I2S3_WS/ EVENTOUT ADC12_IN4 /DAC_OUT1 21 G8 30 41 P4 51 PA5 I/O TTa (4) SPI1_SCK/ OTG_HS_ULPI_CK / TIM2_CH1_ETR/ TIM8_CH1N/ EVENTOUT ADC12_IN5/DAC_OU T2 22 H8 31 42 P3 52 PA6 I/O FT (4) SPI1_MISO / TIM8_BKIN/TIM13_CH1 / DCMI_PIXCLK / TIM3_CH1 / TIM1_BKIN/ EVENTOUT ADC12_IN6 23 J8 32 43 R3 53 PA7 I/O FT (4) SPI1_MOSI/ TIM8_CH1N / TIM14_CH1/TIM3_CH2/ ETH_MII_RX_DV / TIM1_CH1N / ETH_RMII_CRS_DV/ EVENTOUT ADC12_IN7 24 - 33 44 N5 54 PC4 I/O FT (4) ETH_RMII_RX_D0 / ETH_MII_RX_D0/ EVENTOUT ADC12_IN14 25 - 34 45 P5 55 PC5 I/O FT (4) ETH_RMII_RX_D1 / ETH_MII_RX_D1/ EVENTOUT ADC12_IN15 26 G7 35 46 R5 56 PB0 I/O FT (4) TIM3_CH3 / TIM8_CH2N/ OTG_HS_ULPI_D1/ ETH_MII_RXD2 / TIM1_CH2N/ EVENTOUT ADC12_IN8 Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 49/185 STM32F405xx, STM32F407xx Pinouts and pin description 27 H7 36 47 R4 57 PB1 I/O FT (4) TIM3_CH4 / TIM8_CH3N/ OTG_HS_ULPI_D2/ ETH_MII_RXD3 / TIM1_CH3N/ EVENTOUT ADC12_IN9 28 J7 37 48 M6 58 PB2/BOOT1 (PB2) I/O FT EVENTOUT - - - 49 R6 59 PF11 I/O FT DCMI_D12/ EVENTOUT - - - 50 P6 60 PF12 I/O FT FSMC_A6/ EVENTOUT - - - 51 M8 61 VSS S - - - 52 N8 62 VDD S - - - 53 N6 63 PF13 I/O FT FSMC_A7/ EVENTOUT - - - 54 R7 64 PF14 I/O FT FSMC_A8/ EVENTOUT - - - 55 P7 65 PF15 I/O FT FSMC_A9/ EVENTOUT - - - 56 N7 66 PG0 I/O FT FSMC_A10/ EVENTOUT - - - 57 M7 67 PG1 I/O FT FSMC_A11/ EVENTOUT - G6 38 58 R8 68 PE7 I/O FT FSMC_D4/TIM1_ETR/ EVENTOUT - H6 39 59 P8 69 PE8 I/O FT FSMC_D5/ TIM1_CH1N/ EVENTOUT - J6 40 60 P9 70 PE9 I/O FT FSMC_D6/TIM1_CH1/ EVENTOUT - - - 61 M9 71 VSS S - - - 62 N9 72 VDD S - F6 41 63 R9 73 PE10 I/O FT FSMC_D7/TIM1_CH2N/ EVENTOUT - J5 42 64 P10 74 PE11 I/O FT FSMC_D8/TIM1_CH2/ EVENTOUT - H5 43 65 R10 75 PE12 I/O FT FSMC_D9/TIM1_CH3N/ EVENTOUT - G5 44 66 N11 76 PE13 I/O FT FSMC_D10/TIM1_CH3/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 50/185 DocID022152 Rev 4 - F5 45 67 P11 77 PE14 I/O FT FSMC_D11/TIM1_CH4/ EVENTOUT - G4 46 68 R11 78 PE15 I/O FT FSMC_D12/TIM1_BKIN/ EVENTOUT 29 H4 47 69 R12 79 PB10 I/O FT SPI2_SCK / I2S2_CK / I2C2_SCL/ USART3_TX / OTG_HS_ULPI_D3 / ETH_MII_RX_ER / TIM2_CH3/ EVENTOUT 30 J4 48 70 R13 80 PB11 I/O FT I2C2_SDA/USART3_RX/ OTG_HS_ULPI_D4 / ETH_RMII_TX_EN/ ETH_MII_TX_EN / TIM2_CH4/ EVENTOUT 31 F4 49 71 M10 81 VCAP_1 S 32 - 50 72 N10 82 VDD S - - - - M11 83 PH6 I/O FT I2C2_SMBA / TIM12_CH1 / ETH_MII_RXD2/ EVENTOUT - - - - N12 84 PH7 I/O FT I2C3_SCL / ETH_MII_RXD3/ EVENTOUT - - - - M12 85 PH8 I/O FT I2C3_SDA / DCMI_HSYNC/ EVENTOUT - - - - M13 86 PH9 I/O FT I2C3_SMBA / TIM12_CH2/ DCMI_D0/ EVENTOUT - - - - L13 87 PH10 I/O FT TIM5_CH1 / DCMI_D1/ EVENTOUT - - - - L12 88 PH11 I/O FT TIM5_CH2 / DCMI_D2/ EVENTOUT - - - - K12 89 PH12 I/O FT TIM5_CH3 / DCMI_D3/ EVENTOUT - - - - H12 90 VSS S - - - - J12 91 VDD S Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 51/185 STM32F405xx, STM32F407xx Pinouts and pin description 33 J3 51 73 P12 92 PB12 I/O FT SPI2_NSS / I2S2_WS / I2C2_SMBA/ USART3_CK/ TIM1_BKIN / CAN2_RX / OTG_HS_ULPI_D5/ ETH_RMII_TXD0 / ETH_MII_TXD0/ OTG_HS_ID/ EVENTOUT 34 J1 52 74 P13 93 PB13 I/O FT SPI2_SCK / I2S2_CK / USART3_CTS/ TIM1_CH1N /CAN2_TX / OTG_HS_ULPI_D6 / ETH_RMII_TXD1 / ETH_MII_TXD1/ EVENTOUT OTG_HS_VBUS 35 J2 53 75 R14 94 PB14 I/O FT SPI2_MISO/ TIM1_CH2N / TIM12_CH1 / OTG_HS_DM/ USART3_RTS / TIM8_CH2N/I2S2ext_SD/ EVENTOUT 36 H1 54 76 R15 95 PB15 I/O FT SPI2_MOSI / I2S2_SD/ TIM1_CH3N / TIM8_CH3N / TIM12_CH2 / OTG_HS_DP/ EVENTOUT RTC_REFIN - H2 55 77 P15 96 PD8 I/O FT FSMC_D13 / USART3_TX/ EVENTOUT - H3 56 78 P14 97 PD9 I/O FT FSMC_D14 / USART3_RX/ EVENTOUT - G3 57 79 N15 98 PD10 I/O FT FSMC_D15 / USART3_CK/ EVENTOUT - G1 58 80 N14 99 PD11 I/O FT FSMC_CLE / FSMC_A16/USART3_CT S/ EVENTOUT - G2 59 81 N13 100 PD12 I/O FT FSMC_ALE/ FSMC_A17/TIM4_CH1 / USART3_RTS/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 52/185 DocID022152 Rev 4 - - 60 82 M15 101 PD13 I/O FT FSMC_A18/TIM4_CH2/ EVENTOUT - - - 83 - 102 VSS S - - - 84 J13 103 VDD S - F2 61 85 M14 104 PD14 I/O FT FSMC_D0/TIM4_CH3/ EVENTOUT/ EVENTOUT - F1 62 86 L14 105 PD15 I/O FT FSMC_D1/TIM4_CH4/ EVENTOUT - - - 87 L15 106 PG2 I/O FT FSMC_A12/ EVENTOUT - - - 88 K15 107 PG3 I/O FT FSMC_A13/ EVENTOUT - - - 89 K14 108 PG4 I/O FT FSMC_A14/ EVENTOUT - - - 90 K13 109 PG5 I/O FT FSMC_A15/ EVENTOUT - - - 91 J15 110 PG6 I/O FT FSMC_INT2/ EVENTOUT - - - 92 J14 111 PG7 I/O FT FSMC_INT3 /USART6_CK/ EVENTOUT - - - 93 H14 112 PG8 I/O FT USART6_RTS / ETH_PPS_OUT/ EVENTOUT - - - 94 G12 113 VSS S - - - 95 H13 114 VDD S 37 F3 63 96 H15 115 PC6 I/O FT I2S2_MCK / TIM8_CH1/SDIO_D6 / USART6_TX / DCMI_D0/TIM3_CH1/ EVENTOUT 38 E1 64 97 G15 116 PC7 I/O FT I2S3_MCK / TIM8_CH2/SDIO_D7 / USART6_RX / DCMI_D1/TIM3_CH2/ EVENTOUT 39 E2 65 98 G14 117 PC8 I/O FT TIM8_CH3/SDIO_D0 /TIM3_CH3/ USART6_CK / DCMI_D2/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 53/185 STM32F405xx, STM32F407xx Pinouts and pin description 40 E3 66 99 F14 118 PC9 I/O FT I2S_CKIN/ MCO2 / TIM8_CH4/SDIO_D1 / /I2C3_SDA / DCMI_D3 / TIM3_CH4/ EVENTOUT 41 D1 67 100 F15 119 PA8 I/O FT MCO1 / USART1_CK/ TIM1_CH1/ I2C3_SCL/ OTG_FS_SOF/ EVENTOUT 42 D2 68 101 E15 120 PA9 I/O FT USART1_TX/ TIM1_CH2 / I2C3_SMBA / DCMI_D0/ EVENTOUT OTG_FS_VBUS 43 D3 69 102 D15 121 PA10 I/O FT USART1_RX/ TIM1_CH3/ OTG_FS_ID/DCMI_D1/ EVENTOUT 44 C1 70 103 C15 122 PA11 I/O FT USART1_CTS / CAN1_RX / TIM1_CH4 / OTG_FS_DM/ EVENTOUT 45 C2 71 104 B15 123 PA12 I/O FT USART1_RTS / CAN1_TX/ TIM1_ETR/ OTG_FS_DP/ EVENTOUT 46 D4 72 105 A15 124 PA13 (JTMS-SWDIO) I/O FT JTMS-SWDIO/ EVENTOUT 47 B1 73 106 F13 125 VCAP_2 S - E7 74 107 F12 126 VSS S 48 E6 75 108 G13 127 VDD S - - - - E12 128 PH13 I/O FT TIM8_CH1N / CAN1_TX/ EVENTOUT - - - - E13 129 PH14 I/O FT TIM8_CH2N / DCMI_D4/ EVENTOUT - - - - D13 130 PH15 I/O FT TIM8_CH3N / DCMI_D11/ EVENTOUT - C3 - - E14 131 PI0 I/O FT TIM5_CH4 / SPI2_NSS / I2S2_WS / DCMI_D13/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 54/185 DocID022152 Rev 4 - B2 - - D14 132 PI1 I/O FT SPI2_SCK / I2S2_CK / DCMI_D8/ EVENTOUT - - - - C14 133 PI2 I/O FT TIM8_CH4 /SPI2_MISO / DCMI_D9 / I2S2ext_SD/ EVENTOUT - - - - C13 134 PI3 I/O FT TIM8_ETR / SPI2_MOSI / I2S2_SD / DCMI_D10/ EVENTOUT - - - - D9 135 VSS S - - - - C9 136 VDD S 49 A2 76 109 A14 137 PA14 (JTCK/SWCLK) I/O FT JTCK-SWCLK/ EVENTOUT 50 B3 77 110 A13 138 PA15 (JTDI) I/O FT JTDI/ SPI3_NSS/ I2S3_WS/TIM2_CH1_ET R / SPI1_NSS / EVENTOUT 51 D5 78 111 B14 139 PC10 I/O FT SPI3_SCK / I2S3_CK/ UART4_TX/SDIO_D2 / DCMI_D8 / USART3_TX/ EVENTOUT 52 C4 79 112 B13 140 PC11 I/O FT UART4_RX/ SPI3_MISO / SDIO_D3 / DCMI_D4/USART3_RX / I2S3ext_SD/ EVENTOUT 53 A3 80 113 A12 141 PC12 I/O FT UART5_TX/SDIO_CK / DCMI_D9 / SPI3_MOSI /I2S3_SD / USART3_CK/ EVENTOUT - D6 81 114 B12 142 PD0 I/O FT FSMC_D2/CAN1_RX/ EVENTOUT - C5 82 115 C12 143 PD1 I/O FT FSMC_D3 / CAN1_TX/ EVENTOUT 54 B4 83 116 D12 144 PD2 I/O FT TIM3_ETR/UART5_RX/ SDIO_CMD / DCMI_D11/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 55/185 STM32F405xx, STM32F407xx Pinouts and pin description - - 84 117 D11 145 PD3 I/O FT FSMC_CLK/ USART2_CTS/ EVENTOUT - A4 85 118 D10 146 PD4 I/O FT FSMC_NOE/ USART2_RTS/ EVENTOUT - C6 86 119 C11 147 PD5 I/O FT FSMC_NWE/USART2_TX / EVENTOUT - - - 120 D8 148 VSS S - - - 121 C8 149 VDD S - B5 87 122 B11 150 PD6 I/O FT FSMC_NWAIT/ USART2_RX/ EVENTOUT - A5 88 123 A11 151 PD7 I/O FT USART2_CK/FSMC_NE1/ FSMC_NCE2/ EVENTOUT - - - 124 C10 152 PG9 I/O FT USART6_RX / FSMC_NE2/FSMC_NCE3 / EVENTOUT - - - 125 B10 153 PG10 I/O FT FSMC_NCE4_1/ FSMC_NE3/ EVENTOUT - - - 126 B9 154 PG11 I/O FT FSMC_NCE4_2 / ETH_MII_TX_EN/ ETH _RMII_TX_EN/ EVENTOUT - - - 127 B8 155 PG12 I/O FT FSMC_NE4 / USART6_RTS/ EVENTOUT - - - 128 A8 156 PG13 I/O FT FSMC_A24 / USART6_CTS /ETH_MII_TXD0/ ETH_RMII_TXD0/ EVENTOUT - - - 129 A7 157 PG14 I/O FT FSMC_A25 / USART6_TX /ETH_MII_TXD1/ ETH_RMII_TXD1/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 56/185 DocID022152 Rev 4 - E8 - 130 D7 158 VSS S - F7 - 131 C7 159 VDD S - - - 132 B7 160 PG15 I/O FT USART6_CTS / DCMI_D13/ EVENTOUT 55 B6 89 133 A10 161 PB3 (JTDO/ TRACESWO) I/O FT JTDO/ TRACESWO/ SPI3_SCK / I2S3_CK / TIM2_CH2 / SPI1_SCK/ EVENTOUT 56 A6 90 134 A9 162 PB4 (NJTRST) I/O FT NJTRST/ SPI3_MISO / TIM3_CH1 / SPI1_MISO / I2S3ext_SD/ EVENTOUT 57 D7 91 135 A6 163 PB5 I/O FT I2C1_SMBA/ CAN2_RX / OTG_HS_ULPI_D7 / ETH_PPS_OUT/TIM3_CH 2 / SPI1_MOSI/ SPI3_MOSI / DCMI_D10 / I2S3_SD/ EVENTOUT 58 C7 92 136 B6 164 PB6 I/O FT I2C1_SCL/ TIM4_CH1 / CAN2_TX / DCMI_D5/USART1_TX/ EVENTOUT 59 B7 93 137 B5 165 PB7 I/O FT I2C1_SDA / FSMC_NL / DCMI_VSYNC / USART1_RX/ TIM4_CH2/ EVENTOUT 60 A7 94 138 D6 166 BOOT0 I B VPP 61 D8 95 139 A5 167 PB8 I/O FT TIM4_CH3/SDIO_D4/ TIM10_CH1 / DCMI_D6 / ETH_MII_TXD3 / I2C1_SCL/ CAN1_RX/ EVENTOUT 62 C8 96 140 B4 168 PB9 I/O FT SPI2_NSS/ I2S2_WS / TIM4_CH4/ TIM11_CH1/ SDIO_D5 / DCMI_D7 / I2C1_SDA / CAN1_TX/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 57/185 STM32F405xx, STM32F407xx Pinouts and pin description - - 97 141 A4 169 PE0 I/O FT TIM4_ETR / FSMC_NBL0 / DCMI_D2/ EVENTOUT - - 98 142 A3 170 PE1 I/O FT FSMC_NBL1 / DCMI_D3/ EVENTOUT 63 - 99 - D5 - VSS S - A8 - 143 C6 171 PDR_ON I FT 64 A1 10 0 144 C5 172 VDD S - - - - D4 173 PI4 I/O FT TIM8_BKIN / DCMI_D5/ EVENTOUT - - - - C4 174 PI5 I/O FT TIM8_CH1 / DCMI_VSYNC/ EVENTOUT - - - - C3 175 PI6 I/O FT TIM8_CH2 / DCMI_D6/ EVENTOUT - - - - C2 176 PI7 I/O FT TIM8_CH3 / DCMI_D7/ EVENTOUT 1. Function availability depends on the chosen device. 2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com. 4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 5. If the device is delivered in an UFBGA176 or WLCSP90 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low). Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Table 8. FSMC pin definition Pins(1) FSMC LQFP100(2) WLCSP90 (2) CF NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND 16 bit PE2 A23 A23 Yes PE3 A19 A19 Yes Pinouts and pin description STM32F405xx, STM32F407xx 58/185 DocID022152 Rev 4 PE4 A20 A20 Yes PE5 A21 A21 Yes PE6 A22 A22 Yes PF0 A0 A0 - - PF1 A1 A1 - - PF2 A2 A2 - - PF3 A3 A3 - - PF4 A4 A4 - - PF5 A5 A5 - - PF6 NIORD - - PF7 NREG - - PF8 NIOWR - - PF9 CD - - PF10 INTR - - PF12 A6 A6 - - PF13 A7 A7 - - PF14 A8 A8 - - PF15 A9 A9 - - PG0 A10 A10 - - PG1 A11 - - PE7 D4 D4 DA4 D4 Yes Yes PE8 D5 D5 DA5 D5 Yes Yes PE9 D6 D6 DA6 D6 Yes Yes PE10 D7 D7 DA7 D7 Yes Yes PE11 D8 D8 DA8 D8 Yes Yes PE12 D9 D9 DA9 D9 Yes Yes PE13 D10 D10 DA10 D10 Yes Yes PE14 D11 D11 DA11 D11 Yes Yes PE15 D12 D12 DA12 D12 Yes Yes PD8 D13 D13 DA13 D13 Yes Yes PD9 D14 D14 DA14 D14 Yes Yes PD10 D15 D15 DA15 D15 Yes Yes PD11 A16 A16 CLE Yes Yes Table 8. FSMC pin definition (continued) Pins(1) FSMC LQFP100(2) WLCSP90 (2) CF NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND 16 bit DocID022152 Rev 4 59/185 STM32F405xx, STM32F407xx Pinouts and pin description PD12 A17 A17 ALE Yes Yes PD13 A18 A18 Yes PD14 D0 D0 DA0 D0 Yes Yes PD15 D1 D1 DA1 D1 Yes Yes PG2 A12 - - PG3 A13 - - PG4 A14 - - PG5 A15 - - PG6 INT2 - - PG7 INT3 - - PD0 D2 D2 DA2 D2 Yes Yes PD1 D3 D3 DA3 D3 Yes Yes PD3 CLK CLK Yes PD4 NOE NOE NOE NOE Yes Yes PD5 NWE NWE NWE NWE Yes Yes PD6 NWAIT NWAIT NWAIT NWAIT Yes Yes PD7 NE1 NE1 NCE2 Yes Yes PG9 NE2 NE2 NCE3 - - PG10 NCE4_1 NE3 NE3 - - PG11 NCE4_2 - - PG12 NE4 NE4 - - PG13 A24 A24 - - PG14 A25 A25 - - PB7 NADV NADV Yes Yes PE0 NBL0 NBL0 Yes PE1 NBL1 NBL1 Yes 1. Full FSMC features are available on LQFP144, LQFP176, and UFBGA176. The features available on smaller packages are given in the dedicated package column. 2. Ports F and G are not available in devices delivered in 100-pin packages. Table 8. FSMC pin definition (continued) Pins(1) FSMC LQFP100(2) WLCSP90 (2) CF NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND 16 bit Pinouts and pin description STM32F405xx, STM32F407xx 60/185 DocID022152 Rev 4 Table 9. Alternate function mapping Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port A PA0 TIM2_CH1_E TR TIM 5_CH1 TIM8_ETR USART2_CTS UART4_TX ETH_MII_CRS EVENTOUT PA1 TIM2_CH2 TIM5_CH2 USART2_RTS UART4_RX ETH_MII _RX_CLK ETH_RMII__REF _CLK EVENTOUT PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX ETH_MDIO EVENTOUT PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX OTG_HS_ULPI_ D0 ETH _MII_COL EVENTOUT PA4 SPI1_NSS SPI3_NSS I2S3_WS USART2_CK OTG_HS_SO F DCMI_HSYN C EVENTOUT PA5 TIM2_CH1_E TR TIM8_CH1N SPI1_SCK OTG_HS_ULPI_ CK EVENTOUT PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN SPI1_MISO TIM13_CH1 DCMI_PIXCK EVENTOUT PA7 TIM1_CH1N TIM3_CH2 TIM8_CH1N SPI1_MOSI TIM14_CH1 ETH_MII _RX_DV ETH_RMII _CRS_DV EVENTOUT PA8 MCO1 TIM1_CH1 I2C3_SCL USART1_CK OTG_FS_SOF EVENTOUT PA9 TIM1_CH2 I2C3_SMB A USART1_TX DCMI_D0 EVENTOUT PA10 TIM1_CH3 USART1_RX OTG_FS_ID DCMI_D1 EVENTOUT PA11 TIM1_CH4 USART1_CTS CAN1_RX OTG_FS_DM EVENTOUT PA12 TIM1_ETR USART1_RTS CAN1_TX OTG_FS_DP EVENTOUT PA13 JTMSSWDIO EVENTOUT PA14 JTCKSWCLK EVENTOUT PA15 JTDI TIM 2_CH1 TIM 2_ETR SPI1_NSS SPI3_NSS/ I2S3_WS EVENTOUT STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 61/185 Port B PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N OTG_HS_ULPI_ D1 ETH _MII_RXD2 EVENTOUT PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N OTG_HS_ULPI_ D2 ETH _MII_RXD3 EVENTOUT PB2 EVENTOUT PB3 JTDO/ TRACES WO TIM2_CH2 SPI1_SCK SPI3_SCK I2S3_CK EVENTOUT PB4 NJTRST TIM3_CH1 SPI1_MISO SPI3_MISO I2S3ext_SD EVENTOUT PB5 TIM3_CH2 I2C1_SMB A SPI1_MOSI SPI3_MOSI I2S3_SD CAN2_RX OTG_HS_ULPI_ D7 ETH _PPS_OUT DCMI_D10 EVENTOUT PB6 TIM4_CH1 I2C1_SCL USART1_TX CAN2_TX DCMI_D5 EVENTOUT PB7 TIM4_CH2 I2C1_SDA USART1_RX FSMC_NL DCMI_VSYN C EVENTOUT PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL CAN1_RX ETH _MII_TXD3 SDIO_D4 DCMI_D6 EVENTOUT PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS I2S2_WS CAN1_TX SDIO_D5 DCMI_D7 EVENTOUT PB10 TIM2_CH3 I2C2_SCL SPI2_SCK I2S2_CK USART3_TX OTG_HS_ULPI_ D3 ETH_ MII_RX_ER EVENTOUT PB11 TIM2_CH4 I2C2_SDA USART3_RX OTG_HS_ULPI_ D4 ETH _MII_TX_EN ETH _RMII_TX_EN EVENTOUT PB12 TIM1_BKIN I2C2_SMB A SPI2_NSS I2S2_WS USART3_CK CAN2_RX OTG_HS_ULPI_ D5 ETH _MII_TXD0 ETH _RMII_TXD0 OTG_HS_ID EVENTOUT PB13 TIM1_CH1N SPI2_SCK I2S2_CK USART3_CTS CAN2_TX OTG_HS_ULPI_ D6 ETH _MII_TXD1 ETH _RMII_TXD1 EVENTOUT PB14 TIM1_CH2N TIM8_CH2N SPI2_MISO I2S2ext_SD USART3_RTS TIM12_CH1 OTG_HS_DM EVENTOUT PB15 RTC_ REFIN TIM1_CH3N TIM8_CH3N SPI2_MOSI I2S2_SD TIM12_CH2 OTG_HS_DP EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 62/185 DocID022152 Rev 4 Port C PC0 OTG_HS_ULPI_ STP EVENTOUT PC1 ETH_MDC EVENTOUT PC2 SPI2_MISO I2S2ext_SD OTG_HS_ULPI_ DIR ETH _MII_TXD2 EVENTOUT PC3 SPI2_MOSI I2S2_SD OTG_HS_ULPI_ NXT ETH _MII_TX_CLK EVENTOUT PC4 ETH_MII_RXD0 ETH_RMII_RXD0 EVENTOUT PC5 ETH _MII_RXD1 ETH _RMII_RXD1 EVENTOUT PC6 TIM3_CH1 TIM8_CH1 I2S2_MCK USART6_TX SDIO_D6 DCMI_D0 EVENTOUT PC7 TIM3_CH2 TIM8_CH2 I2S3_MCK USART6_RX SDIO_D7 DCMI_D1 EVENTOUT PC8 TIM3_CH3 TIM8_CH3 USART6_CK SDIO_D0 DCMI_D2 EVENTOUT PC9 MCO2 TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN SDIO_D1 DCMI_D3 EVENTOUT PC10 SPI3_SCK/ I2S3_CK USART3_TX/ UART4_TX SDIO_D2 DCMI_D8 EVENTOUT PC11 I2S3ext_SD SPI3_MISO/ USART3_RX UART4_RX SDIO_D3 DCMI_D4 EVENTOUT PC12 SPI3_MOSI I2S3_SD USART3_CK UART5_TX SDIO_CK DCMI_D9 EVENTOUT PC13 EVENTOUT PC14 EVENTOUT PC15 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 63/185 Port D PD0 CAN1_RX FSMC_D2 EVENTOUT PD1 CAN1_TX FSMC_D3 EVENTOUT PD2 TIM3_ETR UART5_RX SDIO_CMD DCMI_D11 EVENTOUT PD3 USART2_CTS FSMC_CLK EVENTOUT PD4 USART2_RTS FSMC_NOE EVENTOUT PD5 USART2_TX FSMC_NWE EVENTOUT PD6 USART2_RX FSMC_NWAIT EVENTOUT PD7 USART2_CK FSMC_NE1/ FSMC_NCE2 EVENTOUT PD8 USART3_TX FSMC_D13 EVENTOUT PD9 USART3_RX FSMC_D14 EVENTOUT PD10 USART3_CK FSMC_D15 EVENTOUT PD11 USART3_CTS FSMC_A16 EVENTOUT PD12 TIM4_CH1 USART3_RTS FSMC_A17 EVENTOUT PD13 TIM4_CH2 FSMC_A18 EVENTOUT PD14 TIM4_CH3 FSMC_D0 EVENTOUT PD15 TIM4_CH4 FSMC_D1 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 64/185 DocID022152 Rev 4 Port E PE0 TIM4_ETR FSMC_NBL0 DCMI_D2 EVENTOUT PE1 FSMC_NBL1 DCMI_D3 EVENTOUT PE2 TRACECL K ETH _MII_TXD3 FSMC_A23 EVENTOUT PE3 TRACED0 FSMC_A19 EVENTOUT PE4 TRACED1 FSMC_A20 DCMI_D4 EVENTOUT PE5 TRACED2 TIM9_CH1 FSMC_A21 DCMI_D6 EVENTOUT PE6 TRACED3 TIM9_CH2 FSMC_A22 DCMI_D7 EVENTOUT PE7 TIM1_ETR FSMC_D4 EVENTOUT PE8 TIM1_CH1N FSMC_D5 EVENTOUT PE9 TIM1_CH1 FSMC_D6 EVENTOUT PE10 TIM1_CH2N FSMC_D7 EVENTOUT PE11 TIM1_CH2 FSMC_D8 EVENTOUT PE12 TIM1_CH3N FSMC_D9 EVENTOUT PE13 TIM1_CH3 FSMC_D10 EVENTOUT PE14 TIM1_CH4 FSMC_D11 EVENTOUT PE15 TIM1_BKIN FSMC_D12 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 65/185 Port F PF0 I2C2_SDA FSMC_A0 EVENTOUT PF1 I2C2_SCL FSMC_A1 EVENTOUT PF2 I2C2_ SMBA FSMC_A2 EVENTOUT PF3 FSMC_A3 EVENTOUT PF4 FSMC_A4 EVENTOUT PF5 FSMC_A5 EVENTOUT PF6 TIM10_CH1 FSMC_NIORD EVENTOUT PF7 TIM11_CH1 FSMC_NREG EVENTOUT PF8 TIM13_CH1 FSMC_ NIOWR EVENTOUT PF9 TIM14_CH1 FSMC_CD EVENTOUT PF10 FSMC_INTR EVENTOUT PF11 DCMI_D12 EVENTOUT PF12 FSMC_A6 EVENTOUT PF13 FSMC_A7 EVENTOUT PF14 FSMC_A8 EVENTOUT PF15 FSMC_A9 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 66/185 DocID022152 Rev 4 Port G PG0 FSMC_A10 EVENTOUT PG1 FSMC_A11 EVENTOUT PG2 FSMC_A12 EVENTOUT PG3 FSMC_A13 EVENTOUT PG4 FSMC_A14 EVENTOUT PG5 FSMC_A15 EVENTOUT PG6 FSMC_INT2 EVENTOUT PG7 USART6_CK FSMC_INT3 EVENTOUT PG8 USART6_ RTS ETH _PPS_OUT EVENTOUT PG9 USART6_RX FSMC_NE2/ FSMC_NCE3 EVENTOUT PG10 FSMC_ NCE4_1/ FSMC_NE3 EVENTOUT PG11 ETH _MII_TX_EN ETH _RMII_ TX_EN FSMC_NCE4_ 2 EVENTOUT PG12 USART6_ RTS FSMC_NE4 EVENTOUT PG13 UART6_CTS ETH _MII_TXD0 ETH _RMII_TXD0 FSMC_A24 EVENTOUT PG14 USART6_TX ETH _MII_TXD1 ETH _RMII_TXD1 FSMC_A25 EVENTOUT PG15 USART6_ CTS DCMI_D13 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 67/185 Port H PH0 EVENTOUT PH1 EVENTOUT PH2 ETH _MII_CRS EVENTOUT PH3 ETH _MII_COL EVENTOUT PH4 I2C2_SCL OTG_HS_ULPI_ NXT EVENTOUT PH5 I2C2_SDA EVENTOUT PH6 I2C2_SMB A TIM12_CH1 ETH _MII_RXD2 EVENTOUT PH7 I2C3_SCL ETH _MII_RXD3 EVENTOUT PH8 I2C3_SDA DCMI_HSYN C EVENTOUT PH9 I2C3_SMB A TIM12_CH2 DCMI_D0 EVENTOUT PH10 TIM5_CH1 DCMI_D1 EVENTOUT PH11 TIM5_CH2 DCMI_D2 EVENTOUT PH12 TIM5_CH3 DCMI_D3 EVENTOUT PH13 TIM8_CH1N CAN1_TX EVENTOUT PH14 TIM8_CH2N DCMI_D4 EVENTOUT PH15 TIM8_CH3N DCMI_D11 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 68/185 DocID022152 Rev 4 Port I PI0 TIM5_CH4 SPI2_NSS I2S2_WS DCMI_D13 EVENTOUT PI1 SPI2_SCK I2S2_CK DCMI_D8 EVENTOUT PI2 TIM8_CH4 SPI2_MISO I2S2ext_SD DCMI_D9 EVENTOUT PI3 TIM8_ETR SPI2_MOSI I2S2_SD DCMI_D10 EVENTOUT PI4 TIM8_BKIN DCMI_D5 EVENTOUT PI5 TIM8_CH1 DCMI_ VSYNC EVENTOUT PI6 TIM8_CH2 DCMI_D6 EVENTOUT PI7 TIM8_CH3 DCMI_D7 EVENTOUT PI8 EVENTOUT PI9 CAN1_RX EVENTOUT PI10 ETH _MII_RX_ER EVENTOUT PI11 OTG_HS_ULPI_ DIR EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI DocID022152 Rev 4 69/185 STM32F405xx, STM32F407xx Memory mapping 4 Memory mapping The memory map is shown in Figure 18. Figure 18. STM32F40x memory map 512-Mbyte block 7 Cortex-M4's internal peripherals 512-Mbyte block 6 Not used 512-Mbyte block 5 FSMC registers 512-Mbyte block 4 FSMC bank 3 & bank4 512-Mbyte block 3 FSMC bank1 & bank2 512-Mbyte block 2 Peripherals 512-Mbyte block 1 SRAM 0x0000 0000 0x1FFF FFFF 0x2000 0000 0x3FFF FFFF 0x4000 0000 0x5FFF FFFF 0x6000 0000 0x7FFF FFFF 0x8000 0000 0x9FFF FFFF 0xA000 0000 0xBFFF FFFF 0xC000 0000 0xDFFF FFFF 0xE000 0000 0xFFFF FFFF 512-Mbyte block 0 Code Flash 0x0810 0000 - 0x0FFF FFFF 0x1FFF 0000 - 0x1FFF 7A0F 0x1FFF C000 - 0x1FFF C007 0x0800 0000 - 0x080F FFFF 0x0010 0000 - 0x07FF FFFF 0x0000 0000 - 0x000F FFFF System memory + OTP Reserved Reserved Aliased to Flash, system memory or SRAM depending on the BOOT pins SRAM (16 KB aliased by bit-banding) Reserved 0x2000 0000 - 0x2001 BFFF 0x2001 C000 - 0x2001 FFFF 0x2002 0000 - 0x3FFF FFFF 0x4000 0000 Reserved 0x4000 7FFF 0x4000 7800 - 0x4000 FFFF 0x4001 0000 0x4001 57FF 0x4002 000 Reserved 0x5006 0C00 - 0x5FFF FFFF 0x6000 0000 AHB3 0xA000 0FFF 0xA000 1000 - 0xDFFF FFFF ai18513f Option Bytes Reserved 0x4001 5800 - 0x4001 FFFF 0x5006 0BFF AHB2 0x5000 0000 Reserved 0x4008 0000 - 0x4FFF FFFF AHB1 SRAM (112 KB aliased by bit-banding) Reserved 0x1FFF C008 - 0x1FFF FFFF Reserved 0x1FFF 7A10 - 0x1FFF 7FFF CCM data RAM (64 KB data SRAM) 0x1000 0000 - 0x1000 FFFF Reserved 0x1001 0000 - 0x1FFE FFFF Reserved APB2 0x4007 FFFF APB1 CORTEX-M4 internal peripherals 0xE000 0000 - 0xE00F FFFF Reserved 0xE010 0000 - 0xFFFF FFFF Memory mapping STM32F405xx, STM32F407xx 70/185 DocID022152 Rev 4 Table 10. STM32F40x register boundary addresses Bus Boundary address Peripheral 0xE00F FFFF - 0xFFFF FFFF Reserved Cortex-M4 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals 0xA000 1000 - 0xDFFF FFFF Reserved AHB3 0xA000 0000 - 0xA000 0FFF FSMC control register 0x9000 0000 - 0x9FFF FFFF FSMC bank 4 0x8000 0000 - 0x8FFF FFFF FSMC bank 3 0x7000 0000 - 0x7FFF FFFF FSMC bank 2 0x6000 0000 - 0x6FFF FFFF FSMC bank 1 0x5006 0C00- 0x5FFF FFFF Reserved AHB2 0x5006 0800 - 0x5006 0BFF RNG 0x5005 0400 - 0x5006 07FF Reserved 0x5005 0000 - 0x5005 03FF DCMI 0x5004 0000- 0x5004 FFFF Reserved 0x5000 0000 - 0x5003 FFFF USB OTG FS 0x4008 0000- 0x4FFF FFFF Reserved DocID022152 Rev 4 71/185 STM32F405xx, STM32F407xx Memory mapping AHB1 0x4004 0000 - 0x4007 FFFF USB OTG HS 0x4002 9400 - 0x4003 FFFF Reserved 0x4002 9000 - 0x4002 93FF ETHERNET MAC 0x4002 8C00 - 0x4002 8FFF 0x4002 8800 - 0x4002 8BFF 0x4002 8400 - 0x4002 87FF 0x4002 8000 - 0x4002 83FF 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF DMA2 0x4002 6000 - 0x4002 63FF DMA1 0x4002 5000 - 0x4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF BKPSRAM 0x4002 3C00 - 0x4002 3FFF Flash interface register 0x4002 3800 - 0x4002 3BFF RCC 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2400 - 0x4002 2FFF Reserved 0x4002 2000 - 0x4002 23FF GPIOI 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE 0x4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA 0x4001 5800- 0x4001 FFFF Reserved Table 10. STM32F40x register boundary addresses (continued) Bus Boundary address Peripheral Memory mapping STM32F405xx, STM32F407xx 72/185 DocID022152 Rev 4 APB2 0x4001 4C00 - 0x4001 57FF Reserved 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF TIM10 0x4001 4000 - 0x4001 43FF TIM9 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI1 0x4001 2C00 - 0x4001 2FFF SDIO 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3 0x4001 1800 - 0x4001 1FFF Reserved 0x4001 1400 - 0x4001 17FF USART6 0x4001 1000 - 0x4001 13FF USART1 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF TIM8 0x4001 0000 - 0x4001 03FF TIM1 0x4000 7800- 0x4000 FFFF Reserved Table 10. STM32F40x register boundary addresses (continued) Bus Boundary address Peripheral DocID022152 Rev 4 73/185 STM32F405xx, STM32F407xx Memory mapping APB1 0x4000 7800 - 0x4000 7FFF Reserved 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PWR 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 6800 - 0x4000 6BFF CAN2 0x4000 6400 - 0x4000 67FF CAN1 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 5000 - 0x4000 53FF UART5 0x4000 4C00 - 0x4000 4FFF UART4 0x4000 4800 - 0x4000 4BFF USART3 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 43FF I2S3ext 0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3 0x4000 3800 - 0x4000 3BFF SPI2 / I2S2 0x4000 3400 - 0x4000 37FF I2S2ext 0x4000 3000 - 0x4000 33FF IWDG 0x4000 2C00 - 0x4000 2FFF WWDG 0x4000 2800 - 0x4000 2BFF RTC & BKP Registers 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIM14 0x4000 1C00 - 0x4000 1FFF TIM13 0x4000 1800 - 0x4000 1BFF TIM12 0x4000 1400 - 0x4000 17FF TIM7 0x4000 1000 - 0x4000 13FF TIM6 0x4000 0C00 - 0x4000 0FFF TIM5 0x4000 0800 - 0x4000 0BFF TIM4 0x4000 0400 - 0x4000 07FF TIM3 0x4000 0000 - 0x4000 03FF TIM2 Table 10. STM32F40x register boundary addresses (continued) Bus Boundary address Peripheral Electrical characteristics STM32F405xx, STM32F407xx 74/185 DocID022152 Rev 4 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 1.8 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 19. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 20. Figure 19. Pin loading conditions Figure 20. Pin input voltage MS19011V1 C = 50 pF STM32F pin OSC_OUT (Hi-Z when using HSE or LSE) MS19010V1 STM32F pin VIN OSC_OUT (Hi-Z when using HSE or LSE) DocID022152 Rev 4 75/185 STM32F405xx, STM32F407xx Electrical characteristics 5.1.6 Power supply scheme Figure 21. Power supply scheme 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. 2. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.2.16: Voltage regulator and Table 2.2.15: Power supply supervisor. 3. The two 2.2 μF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 4. The 4.7 μF ceramic capacitor must be connected to one of the VDD pin. 5. VDDA=VDD and VSSA=VSS. MS19911V2 Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers, backup RAM) Kernel logic (CPU, digital & RAM) Analog: RCs, PLL,.. Power switch VBAT GPIOs OUT IN 15 × 100 nF + 1 × 4.7 μF VBAT = 1.65 to 3.6V Voltage regulator VDDA ADC Level shifter IO Logic VDD 100 nF + 1 μF Flash memory VCAP_1 2 × 2.2 μF VCAP_2 BYPASS_REG PDR_ON Reset controller VDD 1/2/...14/15 VSS 1/2/...14/15 VDD VREF+ VREFVSSA VREF 100 nF + 1 μF Electrical characteristics STM32F405xx, STM32F407xx 76/185 DocID022152 Rev 4 5.1.7 Current consumption measurement Figure 22. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ai14126 VBAT VDD VDDA IDD_VBAT IDD Table 11. Voltage characteristics Symbol Ratings Min Max Unit VDD–VSS External main supply voltage (including VDDA, VDD)(1) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. –0.3 4.0 V VIN Input voltage on five-volt tolerant pin(2) 2. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed injected current. VSS–0.3 VDD+4 Input voltage on any other pin VSS–0.3 4.0 |ΔVDDx| Variations between different VDD power pins - 50 mV |VSSX − VSS| Variations between all the different ground pins - 50 VESD(HBM) Electrostatic discharge voltage (human body model) see Section 5.3.14: Absolute maximum ratings (electrical sensitivity) DocID022152 Rev 4 77/185 STM32F405xx, STM32F407xx Electrical characteristics 5.3 Operating conditions 5.3.1 General operating conditions Table 12. Current characteristics Symbol Ratings Max. Unit IVDD Total current into VDD power lines (source)(1) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 150 mA IVSS Total current out of VSS ground lines (sink)(1) 150 IIO Output current sunk by any I/O and control pin 25 Output current source by any I/Os and control pin 25 IINJ(PIN) (2) 2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.20: 12-bit ADC characteristics. Injected current on five-volt tolerant I/O(3) 3. Positive injection is not possible on these I/Os. A negative injection is induced by VINVDD while a negative injection is induced by VIN 25 MHz. 4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. 5. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 6. In this case HCLK = system clock/2. Electrical characteristics STM32F405xx, STM32F407xx 84/185 DocID022152 Rev 4 Table 21. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) Symbol Parameter Conditions fHCLK Typ Max(1) Unit TA = 25 °C TA = 85 °C TA = 105 °C IDD Supply current in Run mode External clock(2), all peripherals enabled(3)(4) 168 MHz 93 109 117 mA 144 MHz 76 89 96 120 MHz 67 79 86 90 MHz 53 65 73 60 MHz 37 49 56 30 MHz 20 32 39 25 MHz 16 27 35 16 MHz 11 23 30 8 MHz 6 18 25 4 MHz 4 16 23 2 MHz 3 15 22 External clock(2), all peripherals disabled(3)(4) 168 MHz 46 61 69 144 MHz 40 52 60 120 MHz 37 48 56 90 MHz 30 42 50 60 MHz 22 33 41 30 MHz 12 24 31 25 MHz 10 21 29 16 MHz 7 19 26 8 MHz 4 16 23 4 MHz 3 15 22 2 MHz 2 14 21 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 3. When analog peripheral blocks such as (ADCs, DACs, HSE, LSE, HSI,LSI) are on, an additional power consumption should be considered. 4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. DocID022152 Rev 4 85/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 24. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF Figure 25. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals ON MS19974V1 0 5 10 15 20 25 30 35 40 45 50 0 20 40 60 80 100 120 140 160 180 IDD RUN( mA) CPU Frequency (MHz -45 °C 0 °C 25 °C 55 °C 85 °C 105 °C MS19975V1 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 140 160 180 IDD RUN( mA) CPU Frequency (MHz -45°C 0°C 25°C 55°C 85°C 105°C Electrical characteristics STM32F405xx, STM32F407xx 86/185 DocID022152 Rev 4 Figure 26. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF Figure 27. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON MS19976V1 0 10 20 30 40 50 60 0 20 40 60 80 100 120 140 160 180 IDD RUN( mA) CPU Frequency (MHz -45°C 0°C 25°C 55°C 85°C 105°C MS19977V1 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 160 180 IDD RUN( mA) CPU Frequency (MHz -45°C 0°C 25°C 55°C 85°C 105°C DocID022152 Rev 4 87/185 STM32F405xx, STM32F407xx Electrical characteristics Table 22. Typical and maximum current consumption in Sleep mode Symbol Parameter Conditions fHCLK Typ Max(1) T Unit A = 25 °C TA = 85 °C TA = 105 °C IDD Supply current in Sleep mode External clock(2), all peripherals enabled(3) 168 MHz 59 77 84 mA 144 MHz 46 61 67 120 MHz 38 53 60 90 MHz 30 44 51 60 MHz 20 34 41 30 MHz 11 24 31 25 MHz 8 21 28 16 MHz 6 18 25 8 MHz 3 16 23 4 MHz 2 15 22 2 MHz 2 14 21 External clock(2), all peripherals disabled 168 MHz 12 27 35 144 MHz 9 22 29 120 MHz 8 20 28 90 MHz 7 19 26 60 MHz 5 17 24 30 MHz 3 16 23 25 MHz 2 15 22 16 MHz 2 14 21 8 MHz 1 14 21 4 MHz 1 13 21 2 MHz 1 13 21 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register). Electrical characteristics STM32F405xx, STM32F407xx 88/185 DocID022152 Rev 4 Table 23. Typical and maximum current consumptions in Stop mode Symbol Parameter Conditions Typ Max T Unit A = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C IDD_STOP Supply current in Stop mode with main regulator in Run mode Flash in Stop mode, low-speed and highspeed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.45 1.5 11.00 20.00 mA Flash in Deep power down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.40 1.5 11.00 20.00 Supply current in Stop mode with main regulator in Low Power mode Flash in Stop mode, low-speed and highspeed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.31 1.1 8.00 15.00 Flash in Deep power down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.28 1.1 8.00 15.00 Table 24. Typical and maximum current consumptions in Standby mode Symbol Parameter Conditions Typ Max(1) TA = 25 °C Unit TA = 85 °C TA = 105 °C VDD = 1.8 V VDD= 2.4 V VDD = 3.3 V VDD = 3.6 V IDD_STBY Supply current in Standby mode Backup SRAM ON, lowspeed oscillator and RTC ON 3.0 3.4 4.0 20 36 μA Backup SRAM OFF, lowspeed oscillator and RTC ON 2.4 2.7 3.3 16 32 Backup SRAM ON, RTC OFF 2.4 2.6 3.0 12.5 24.8 Backup SRAM OFF, RTC OFF 1.7 1.9 2.2 9.8 19.2 1. Based on characterization, not tested in production. DocID022152 Rev 4 89/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 28. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) Table 25. Typical and maximum current consumptions in VBAT mode Symbol Parameter Conditions Typ Max(1) Unit TA = 25 °C TA = 85 °C TA = 105 °C VBAT = 1.8 V VBAT= 2.4 V VBAT = 3.3 V VBAT = 3.6 V IDD_VBA T Backup domain supply current Backup SRAM ON, low-speed oscillator and RTC ON 1.29 1.42 1.68 6 11 μA Backup SRAM OFF, low-speed oscillator and RTC ON 0.62 0.73 0.96 3 5 Backup SRAM ON, RTC OFF 0.79 0.81 0.86 5 10 Backup SRAM OFF, RTC OFF 0.10 0.10 0.10 2 4 1. Based on characterization, not tested in production. MS19990V1 0 0.5 1 1.5 2 2.5 3 3.5 0 10 20 30 40 50 60 70 80 90 100 IVBAT in (μA) Temperature in (°C) 1.65V 1.8V 2V 2.4V 2.7V 3V 3.3V 3.6V Electrical characteristics STM32F405xx, STM32F407xx 90/185 DocID022152 Rev 4 Figure 29. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 47: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 27: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU MS19991V1 0 1 2 3 4 5 6 0 10 20 30 40 50 60 70 80 90 100 IVBAT in (μA) Temperature in (°C) 1.65V 1.8V 2V 2.4V 2.7V 3V 3.3V 3.6V DocID022152 Rev 4 91/185 STM32F405xx, STM32F407xx Electrical characteristics supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. ISW = VDD × fSW × C Electrical characteristics STM32F405xx, STM32F407xx 92/185 DocID022152 Rev 4 Table 26. Switching output I/O current consumption Symbol Parameter Conditions(1) I/O toggling frequency (fSW) Typ Unit IDDIO I/O switching current VDD = 3.3 V(2) C = CINT 2 MHz 0.02 mA 8 MHz 0.14 25 MHz 0.51 50 MHz 0.86 60 MHz 1.30 VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT+ CS 2 MHz 0.10 8 MHz 0.38 25 MHz 1.18 50 MHz 2.47 60 MHz 2.86 VDD = 3.3 V CEXT = 10 pF C = CINT + CEXT+ CS 2 MHz 0.17 8 MHz 0.66 25 MHz 1.70 50 MHz 2.65 60 MHz 3.48 VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT+ CS 2 MHz 0.23 8 MHz 0.95 25 MHz 3.20 50 MHz 4.69 60 MHz 8.06 VDD = 3.3 V CEXT = 33 pF C = CINT + CEXT+ CS 2 MHz 0.30 8 MHz 1.22 25 MHz 3.90 50 MHz 8.82 60 MHz -(3) 1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value). 2. This test is performed by cutting the LQFP package pin (pad removal). 3. At 60 MHz, C maximum load is specified 30 pF. DocID022152 Rev 4 93/185 STM32F405xx, STM32F407xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 27. The MCU is placed under the following conditions: • At startup, all I/O pins are configured as analog pins by firmware. • All peripherals are disabled unless otherwise mentioned • The code is running from Flash memory and the Flash memory access time is equal to 5 wait states at 168 MHz. • The code is running from Flash memory and the Flash memory access time is equal to 4 wait states at 144 MHz, and the power scale mode is set to 2. • ART accelerator and Cache off. • The given value is calculated by measuring the difference of current consumption – with all peripherals clocked off – with one peripheral clocked on (with only the clock applied) • When the peripherals are enabled: HCLK is the system clock, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. • The typical values are obtained for VDD = 3.3 V and TA= 25 °C, unless otherwise specified. Table 27. Peripheral current consumption Peripheral(1) 168 MHz 144 MHz Unit AHB1 GPIO A 0.49 0.36 mA GPIO B 0.45 0.33 GPIO C 0.45 0.34 GPIO D 0.45 0.34 GPIO E 0.47 0.35 GPIO F 0.45 0.33 GPIO G 0.44 0.33 GPIO H 0.45 0.34 GPIO I 0.44 0.33 OTG_HS + ULPI 4.57 3.55 CRC 0.07 0.06 BKPSRAM 0.11 0.08 DMA1 6.15 4.75 DMA2 6.24 4.8 ETH_MAC + ETH_MAC_TX ETH_MAC_RX ETH_MAC_PTP 3.28 2.54 AHB2 OTG_FS 4.59 3.69 mA DCMI 1.04 0.80 Electrical characteristics STM32F405xx, STM32F407xx 94/185 DocID022152 Rev 4 AHB3 FSMC 2.18 1.67 mA APB1 TIM2 0.80 0.61 TIM3 0.58 0.44 TIM4 0.62 0.48 TIM5 0.79 0.61 TIM6 0.15 0.11 TIM7 0.16 0.12 TIM12 0.33 0.26 TIM13 0.27 0.21 TIM14 0.27 0.21 PWR 0.04 0.03 USART2 0.17 0.13 USART3 0.17 0.13 UART4 0.17 0.13 UART5 0.17 0.13 I2C1 0.17 0.13 I2C2 0.18 0.13 I2C3 0.18 0.13 SPI2/I2S2(2) 0.17/0.16 0.13/0.12 SPI3/I2S3(2) 0.16/0.14 0.12/0.12 CAN1 0.27 0.21 CAN2 0.26 0.20 DAC 0.14 0.10 DAC channel 1(3) 0.91 0.89 DAC channel 2(4) 0.91 0.89 DAC channel 1 and 2(3)(4) 1.69 1.68 WWDG 0.04 0.04 Table 27. Peripheral current consumption (continued) Peripheral(1) 168 MHz 144 MHz Unit DocID022152 Rev 4 95/185 STM32F405xx, STM32F407xx Electrical characteristics 5.3.7 Wakeup time from low-power mode The wakeup times given in Table 28 is measured on a wakeup phase with a 16 MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: • Stop or Standby mode: the clock source is the RC oscillator • Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. APB2 SDIO 0.64 0.54 mA TIM1 1.47 1.14 TIM8 1.58 1.22 TIM9 0.68 0.54 TIM10 0.45 0.36 TIM11 0.47 0.38 ADC1(5) 2.20 2.10 ADC2(5) 2.04 1.93 ADC3(5) 2.10 2.00 SPI1 0.14 0.12 USART1 0.34 0.27 USART6 0.34 0.28 1. HSE oscillator with 4 MHz crystal and PLL are ON. 2. I2SMOD bit set in SPI_I2SCFGR register, and then the I2SE bit set to enable I2S peripheral. 3. EN1 bit is set in DAC_CR register. 4. EN2 bit is set in DAC_CR register. 5. ADON bit set in ADC_CR2 register. Table 27. Peripheral current consumption (continued) Peripheral(1) 168 MHz 144 MHz Unit Table 28. Low-power mode wakeup timings Symbol Parameter Min(1) Typ(1) Max(1) Unit tWUSLEEP (2) Wakeup from Sleep mode - 1 - μs tWUSTOP (2) Wakeup from Stop mode (regulator in Run mode) - 13 - Wakeup from Stop mode (regulator in low power mode) - 17 40 μs Wakeup from Stop mode (regulator in low power mode and Flash memory in Deep power down mode) - 110 - tWUSTDBY (2)(3) Wakeup from Standby mode 260 375 480 μs 1. Based on characterization, not tested in production. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction. 3. tWUSTDBY minimum and maximum values are given at 105 °C and –45 °C, respectively. Electrical characteristics STM32F405xx, STM32F407xx 96/185 DocID022152 Rev 4 5.3.8 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 29 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Low-speed external user clock generated from an external source The characteristics given in Table 30 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Table 29. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit fHSE_ext External user clock source frequency(1) 1 - 50 MHz VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD V VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) 1. Guaranteed by design, not tested in production. 5 - - ns tr(HSE) tf(HSE) OSC_IN rise or fall time(1) - - 10 Cin(HSE) OSC_IN input capacitance(1) - 5 - pF DuCy(HSE) Duty cycle 45 - 55 % IL OSC_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 μA Table 30. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit fLSE_ext User External clock source frequency(1) - 32.768 1000 kHz VLSEH OSC32_IN input pin high level voltage 0.7VDD - VDD V VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD tw(LSE) tf(LSE) OSC32_IN high or low time(1) 450 - - ns tr(LSE) tf(LSE) OSC32_IN rise or fall time(1) - - 50 Cin(LSE) OSC32_IN input capacitance(1) - 5 - pF DuCy(LSE) Duty cycle 30 - 70 % IL OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 μA 1. Guaranteed by design, not tested in production. DocID022152 Rev 4 97/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 30. High-speed external clock source AC timing diagram Figure 31. Low-speed external clock source AC timing diagram High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 31. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). ai17528 OSC_IN External STM32F clock source VHSEH tf(HSE) tW(HSE) IL 90% 10% THSE tr(HSE) tW(HSE) t fHSE_ext VHSEL ai17529 External OSC32_IN STM32F clock source VLSEH tf(LSE) tW(LSE) IL 90% 10% TLSE tr(LSE) tW(LSE) t fLSE_ext VLSEL Electrical characteristics STM32F405xx, STM32F407xx 98/185 DocID022152 Rev 4 For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 32). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 32. Typical application with an 8 MHz crystal 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 32. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 31. HSE 4-26 MHz oscillator characteristics(1) (2) 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. Symbol Parameter Conditions Min Typ Max Unit fOSC_IN Oscillator frequency 4 - 26 MHz RF Feedback resistor - 200 - kΩ IDD HSE current consumption VDD=3.3 V, ESR= 30 Ω, CL=5 pF@25 MHz - 449 - μA VDD=3.3 V, ESR= 30 Ω, CL=10 pF@25 MHz - 532 - gm Oscillator transconductance Startup 5 - - mA/V tSU(HSE (3) 3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Startup time VDD is stabilized - 2 - ms ai17530 OSC_OUT OSC_IN fHSE CL1 RF STM32F 8 MHz resonator Resonator with integrated capacitors Bias controlled gain CL2 REXT(1) DocID022152 Rev 4 99/185 STM32F405xx, STM32F407xx Electrical characteristics Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 33. Typical application with a 32.768 kHz crystal 5.3.9 Internal clock source characteristics The parameters given in Table 33 and Table 34 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. High-speed internal (HSI) RC oscillator Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) 1. Guaranteed by design, not tested in production. Symbol Parameter Conditions Min Typ Max Unit RF Feedback resistor - 18.4 - MΩ IDD LSE current consumption - - 1 μA gm Oscillator Transconductance 2.8 - - μA/V tSU(LSE) (2) 2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer startup time VDD is stabilized - 2 - s ai17531 OSC32_OUT OSC32_IN fLSE CL1 RF STM32F 32.768 kHz resonator Resonator with integrated capacitors Bias controlled gain CL2 Table 33. HSI oscillator characteristics (1) Symbol Parameter Conditions Min Typ Max Unit fHSI Frequency - 16 - MHz ACCHSI Accuracy of the HSI oscillator User-trimmed with the RCC_CR register - - 1 % Factorycalibrated TA = –40 to 105 °C(2) –8 - 4.5 % TA = –10 to 85 °C(2) –4 - 4 % TA = 25 °C –1 - 1 % tsu(HSI) (3) HSI oscillator startup time - 2.2 4 μs IDD(HSI) HSI oscillator power consumption - 60 80 μA Electrical characteristics STM32F405xx, STM32F407xx 100/185 DocID022152 Rev 4 Low-speed internal (LSI) RC oscillator Figure 34. ACCLSI versus temperature 5.3.10 PLL characteristics The parameters given in Table 35 and Table 36 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 14. 1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Table 34. LSI oscillator characteristics (1) 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. Symbol Parameter Min Typ Max Unit fLSI (2) 2. Based on characterization, not tested in production. Frequency 17 32 47 kHz tsu(LSI) (3) 3. Guaranteed by design, not tested in production. LSI oscillator startup time - 15 40 μs IDD(LSI) (3) LSI oscillator power consumption - 0.4 0.6 μA MS19013V1 -40 -30 -20 -10 0 10 20 30 40 50 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Normalized deviati on (%) Temperature (°C) max avg min DocID022152 Rev 4 101/185 STM32F405xx, STM32F407xx Electrical characteristics Table 35. Main PLL characteristics Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock(1) 0.95(2) 1 2.10 MHz fPLL_OUT PLL multiplier output clock 24 - 168 MHz fPLL48_OUT 48 MHz PLL multiplier output clock - 48 75 MHz fVCO_OUT PLL VCO output 192 - 432 MHz tLOCK PLL lock time VCO freq = 192 MHz 75 - 200 μs VCO freq = 432 MHz 100 - 300 Jitter(3) Cycle-to-cycle jitter System clock 120 MHz RMS - 25 - ps peak to peak - ±150 - Period Jitter RMS - 15 - peak to peak - ±200 - Main clock output (MCO) for RMII Ethernet Cycle to cycle at 50 MHz on 1000 samples - 32 - Main clock output (MCO) for MII Ethernet Cycle to cycle at 25 MHz on 1000 samples - 40 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples - 330 - IDD(PLL) (4) PLL power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL) (4) PLL power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design, not tested in production. 3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%. 4. Based on characterization, not tested in production. Table 36. PLLI2S (audio PLL) characteristics Symbol Parameter Conditions Min Typ Max Unit fPLLI2S_IN PLLI2S input clock(1) 0.95(2) 1 2.10 MHz fPLLI2S_OUT PLLI2S multiplier output clock - - 216 MHz fVCO_OUT PLLI2S VCO output 192 - 432 MHz tLOCK PLLI2S lock time VCO freq = 192 MHz 75 - 200 μs VCO freq = 432 MHz 100 - 300 Electrical characteristics STM32F405xx, STM32F407xx 102/185 DocID022152 Rev 4 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 43: EMI characteristics). It is available only on the main PLL. Equation 1 The frequency modulation period (MODEPER) is given by the equation below: fPLL_IN and fMod must be expressed in Hz. As an example: If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: Jitter(3) Master I2S clock jitter Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5 RMS - 90 - peak to peak - ±280 - ps Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples - 90 - ps WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLI2S) (4) PLLI2S power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLLI2S) (4) PLLI2S power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design, not tested in production. 3. Value given with main PLL running. 4. Based on characterization, not tested in production. Table 36. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Table 37. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % MODEPER * INCSTEP - - 215−1 - 1. Guaranteed by design, not tested in production. MODEPER = round[fPLL_IN ⁄ (4 × fMod)] MODEPER round 106 4 10 3 = [ ⁄ ( × )] = 250 DocID022152 Rev 4 103/185 STM32F405xx, STM32F407xx Electrical characteristics Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): fVCO_OUT must be expressed in MHz. With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz): An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: As a result: Figure 35 and Figure 36 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 35. PLL output clock waveforms in center spread mode INCSTEP = round[((215 – 1) × md × PLLN) ⁄ (100 × 5 × MODEPER)] INCSTEP = round[((215 – 1) × 2 × 240) ⁄ (100 × 5 × 250)] = 126md(quantitazed)% mdquantized% = (MODEPER × INCSTEP × 100 × 5) ⁄ ((215 – 1) × PLLN) mdquantized% = (250 × 126 × 100 × 5) ⁄ ((215 – 1) × 240) = 2.002%(peak) Frequency (PLL_OUT) Time F0 tmode md ai17291 md 2 x tmode Electrical characteristics STM32F405xx, STM32F407xx 104/185 DocID022152 Rev 4 Figure 36. PLL output clock waveforms in down spread mode 5.3.12 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Time ai17292 Frequency (PLL_OUT) F0 2 x md tmode 2 x tmode Table 38. Flash memory characteristics Symbol Parameter Conditions Min Typ Max Unit IDD Supply current Write / Erase 8-bit mode, VDD = 1.8 V - 5 - Write / Erase 16-bit mode, VDD = 2.1 V - 8 - mA Write / Erase 32-bit mode, VDD = 3.3 V - 12 - Table 39. Flash memory programming Symbol Parameter Conditions Min(1) Typ Max(1) Unit tprog Word programming time Program/erase parallelism (PSIZE) = x 8/16/32 - 16 100(2) μs tERASE16KB Sector (16 KB) erase time Program/erase parallelism (PSIZE) = x 8 - 400 800 Program/erase parallelism ms (PSIZE) = x 16 - 300 600 Program/erase parallelism (PSIZE) = x 32 - 250 500 DocID022152 Rev 4 105/185 STM32F405xx, STM32F407xx Electrical characteristics tERASE64KB Sector (64 KB) erase time Program/erase parallelism (PSIZE) = x 8 - 1200 2400 Program/erase parallelism ms (PSIZE) = x 16 - 700 1400 Program/erase parallelism (PSIZE) = x 32 - 550 1100 tERASE128KB Sector (128 KB) erase time Program/erase parallelism (PSIZE) = x 8 - 2 4 Program/erase parallelism s (PSIZE) = x 16 - 1.3 2.6 Program/erase parallelism (PSIZE) = x 32 - 1 2 tME Mass erase time Program/erase parallelism (PSIZE) = x 8 - 16 32 Program/erase parallelism s (PSIZE) = x 16 - 11 22 Program/erase parallelism (PSIZE) = x 32 - 8 16 Vprog Programming voltage 32-bit program operation 2.7 - 3.6 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.8 - 3.6 V 1. Based on characterization, not tested in production. 2. The maximum programming time is measured after 100K erase operations. Table 39. Flash memory programming (continued) Symbol Parameter Conditions Min(1) Typ Max(1) Unit Electrical characteristics STM32F405xx, STM32F407xx 106/185 DocID022152 Rev 4 5.3.13 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. Table 40. Flash memory programming with VPP Symbol Parameter Conditions Min(1) Typ Max(1) 1. Guaranteed by design, not tested in production. Unit tprog Double word programming TA = 0 to +40 °C VDD = 3.3 V VPP = 8.5 V - 16 100(2) 2. The maximum programming time is measured after 100K erase operations. μs tERASE16KB Sector (16 KB) erase time - 230 - tERASE64KB Sector (64 KB) erase time - 490 - ms tERASE128KB Sector (128 KB) erase time - 875 - tME Mass erase time - 6.9 - s Vprog Programming voltage 2.7 - 3.6 V VPP VPP voltage range 7 - 9 V IPP Minimum current sunk on the VPP pin 10 - - mA tVPP (3) 3. VPP should only be connected during programming/erasing. Cumulative time during which VPP is applied - - 1 hour Table 41. Flash memory endurance and data retention Symbol Parameter Conditions Value Unit Min(1) 1. Based on characterization, not tested in production. NEND Endurance TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 kcycles tRET Data retention 1 kcycle(2) at TA = 85 °C 2. Cycling performed over the whole temperature range. 30 1 kcycle(2) at TA = 105 °C 10 Years 10 kcycles(2) at TA = 55 °C 20 DocID022152 Rev 4 107/185 STM32F405xx, STM32F407xx Electrical characteristics A device reset allows normal operations to be resumed. The test results are given in Table 42. They are based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC? code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 42. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, LQFP176, TA = +25 °C, fHCLK = 168 MHz, conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP176, TA = +25 °C, fHCLK = 168 MHz, conforms to IEC 61000-4-2 4A Electrical characteristics STM32F405xx, STM32F407xx 108/185 DocID022152 Rev 4 5.3.14 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. Table 43. EMI characteristics Symbol Parameter Conditions Monitored frequency band Max vs. [fHSE/fCPU] Unit 25/168 MHz SEMI Peak level VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from Flash with ART accelerator enabled 0.1 to 30 MHz 32 30 to 130 MHz 25 dBμV 130 MHz to 1GHz 29 SAE EMI Level 4 - VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from Flash with ART accelerator and PLL spread spectrum enabled 0.1 to 30 MHz 19 30 to 130 MHz 16 dBμV 130 MHz to 1GHz 18 SAE EMI level 3.5 - Table 44. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) Unit VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 °C conforming to JESD22-A114 2 2000(2) V VESD(CDM) Electrostatic discharge voltage (charge device model) TA = +25 °C conforming to JESD22-C101 II 500 1. Based on characterization results, not tested in production. 2. On VBAT pin, VESD(HBM) is limited to 1000 V. DocID022152 Rev 4 109/185 STM32F405xx, STM32F407xx Electrical characteristics 5.3.15 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of 5 uA/+0 uA range), or other functional failure (for example reset, oscillator frequency deviation). Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. The test results are given in Table 46. 5.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 45. Electrical sensitivities Symbol Parameter Conditions Class LU Static latch-up class TA = +105 °C conforming to JESD78A II level A Table 46. I/O current injection susceptibility Symbol Description Functional susceptibility Negative Unit injection Positive injection IINJ (1) 1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Injected current on all FT pins –5 +0 mA Injected current on any other pin –5 +5 Electrical characteristics STM32F405xx, STM32F407xx 110/185 DocID022152 Rev 4 All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. Table 47. I/O static characteristics Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage TTL ports 2.7 V ≤ VDD ≤ 3.6 V - - 0.8 V VIH (1) Input high level voltage 2.0 - - VIL Input low level voltage CMOS ports 1.8 V ≤ VDD ≤ 3.6 V - - 0.3VDD VIH (1) Input high level voltage 0.7VDD - - - - Vhys I/O Schmitt trigger voltage hysteresis(2) - 200 - IO FT Schmitt trigger voltage mV hysteresis(2) 5% VDD (3) - - Ilkg I/O input leakage current (4) VSS ≤ VIN ≤ VDD - - ±1 μA I/O FT input leakage current (4) VIN = 5 V - - 3 RPU Weak pull-up equivalent resistor(5) All pins except for PA10 and PB12 VIN = VSS 30 40 50 kΩ PA10 and PB12 8 11 15 RPD Weak pull-down equivalent resistor All pins except for PA10 and PB12 VIN = VDD 30 40 50 PA10 and PB12 8 11 15 CIO (6) I/O pin capacitance 5 pF 1. Tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). 6. Guaranteed by design, not tested in production. DocID022152 Rev 4 111/185 STM32F405xx, STM32F407xx Electrical characteristics In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2. In particular: • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 12). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 12). Output voltage levels Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 37 and Table 49, respectively. Table 48. Output voltage characteristics(1) 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). Symbol Parameter Conditions Min Max Unit VOL (2) 2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Output low level voltage for an I/O pin when 8 pins are sunk at same time CMOS port IIO = +8 mA 2.7 V < VDD < 3.6 V - 0.4 V VOH (3) 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–0.4 - VOL (2) Output low level voltage for an I/O pin when 8 pins are sunk at same time TTL port IIO =+ 8mA 2.7 V < VDD < 3.6 V - 0.4 V VOH (3) Output high level voltage for an I/O pin when 8 pins are sourced at same time 2.4 - VOL (2)(4) 4. Based on characterization data, not tested in production. Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +20 mA 2.7 V < VDD < 3.6 V - 1.3 V VOH (3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–1.3 - VOL (2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +6 mA 2 V < VDD < 2.7 V - 0.4 V VOH (3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–0.4 - Electrical characteristics STM32F405xx, STM32F407xx 112/185 DocID022152 Rev 4 Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 49. I/O AC characteristics(1)(2)(3) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions Min Typ Max Unit 00 fmax(IO)out Maximum frequency(4) CL = 50 pF, VDD > 2.70 V - - 2 MHz CL = 50 pF, VDD > 1.8 V - - 2 CL = 10 pF, VDD > 2.70 V - - TBD CL = 10 pF, VDD > 1.8 V - - TBD tf(IO)out Output high to low level fall time CL = 50 pF, VDD = 1.8 V to 3.6 V - - TBD ns tr(IO)out Output low to high level rise time - - TBD 01 fmax(IO)out Maximum frequency(4) CL = 50 pF, VDD > 2.70 V - - 25 MHz CL = 50 pF, VDD > 1.8 V - - 12.5(5) CL = 10 pF, VDD > 2.70 V - - 50(5) CL = 10 pF, VDD > 1.8 V - - TBD tf(IO)out Output high to low level fall time CL = 50 pF, VDD < 2.7 V - - TBD ns CL = 10 pF, VDD > 2.7 V - - TBD tr(IO)out Output low to high level rise time CL = 50 pF, VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD 10 fmax(IO)out Maximum frequency(4) CL = 40 pF, VDD > 2.70 V - - 50(5) MHz CL = 40 pF, VDD > 1.8 V - - 25 CL = 10 pF, VDD > 2.70 V - - 100(5) CL = 10 pF, VDD > 1.8 V - - TBD tf(IO)out Output high to low level fall time CL = 50 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD ns tr(IO)out Output low to high level rise time CL = 50 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD DocID022152 Rev 4 113/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 37. I/O AC characteristics definition 5.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 47). Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. 11 Fmax(IO)ou t Maximum frequency(4) CL = 30 pF, VDD > 2.70 V - - 100(5) MHz CL = 30 pF, VDD > 1.8 V - - 50(5) CL = 10 pF, VDD > 2.70 V - - 200(5) CL = 10 pF, VDD > 1.8 V - - TBD tf(IO)out Output high to low level fall time CL = 20 pF, 2.4 < VDD < 2.7 V - - TBD ns CL = 10 pF, VDD > 2.7 V - - TBD tr(IO)out Output low to high level rise time CL = 20 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD - tEXTIpw Pulse width of external signals detected by the EXTI controller 10 - - ns 1. Based on characterization data, not tested in production. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F20/21xxx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. TBD stands for “to be defined”. 4. The maximum frequency is defined in Figure 37. 5. For maximum frequencies above 50 MHz, the compensation cell should be used. Table 49. I/O AC characteristics(1)(2)(3) (continued) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions Min Typ Max Unit ai14131 10% 90% 50% tr(IO)out OUTPUT EXTERNAL ON 50pF Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) 10% 50% 90% when loaded by 50pF T tr(IO)out Electrical characteristics STM32F405xx, STM32F407xx 114/185 DocID022152 Rev 4 Figure 38. Recommended NRST pin protection 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 50. Otherwise the reset is not taken into account by the device. 5.3.18 TIM timer characteristics The parameters given in Table 51 and Table 52 are guaranteed by design. Refer to Section 5.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 50. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST) (1) 1. Guaranteed by design, not tested in production. NRST Input low level voltage TTL ports 2.7 V ≤ VDD ≤ 3.6 V - - 0.8 V VIH(NRST) (1) NRST Input high level voltage 2 - - VIL(NRST) (1) NRST Input low level voltage CMOS ports 1.8 V ≤ VDD ≤ 3.6 V - 0.3VDD VIH(NRST) (1) NRST Input high level voltage 0.7VDD - Vhys(NRST) NRST Schmitt trigger voltage hysteresis - 200 - mV RPU Weak pull-up equivalent resistor(2) 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). VIN = VSS 30 40 50 kΩ VF(NRST) (1) NRST Input filtered pulse - - 100 ns VNF(NRST) (1) NRST Input not filtered pulse VDD > 2.7 V 300 - - ns TNRST_OUT Generated reset pulse duration Internal Reset source 20 - - μs ai14132c STM32Fxxx NRST(2) RPU VDD Filter Internal Reset 0.1 μF External reset circuit(1) DocID022152 Rev 4 115/185 STM32F405xx, STM32F407xx Electrical characteristics Table 51. Characteristics of TIMx connected to the APB1 domain(1) 1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers. Symbol Parameter Conditions Min Max Unit tres(TIM) Timer resolution time AHB/APB1 prescaler distinct from 1, fTIMxCLK = 84 MHz 1 - tTIMxCLK 11.9 - ns AHB/APB1 prescaler = 1, fTIMxCLK = 42 MHz 1 - tTIMxCLK 23.8 - ns fEXT Timer external clock frequency on CH1 to CH4 fTIMxCLK = 84 MHz APB1= 42 MHz 0 fTIMxCLK/2 MHz 0 42 MHz ResTIM Timer resolution - 16/32 bit tCOUNTER 16-bit counter clock period when internal clock is selected 1 65536 tTIMxCLK 0.0119 780 μs 32-bit counter clock period when internal clock is selected 1 - tTIMxCLK 0.0119 51130563 μs tMAX_COUNT Maximum possible count - 65536 × 65536 tTIMxCLK - 51.1 s Electrical characteristics STM32F405xx, STM32F407xx 116/185 DocID022152 Rev 4 5.3.19 Communications interfaces I2C interface characteristics The STM32F405xx and STM32F407xx I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 53. Refer also to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 52. Characteristics of TIMx connected to the APB2 domain(1) 1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers. Symbol Parameter Conditions Min Max Unit tres(TIM) Timer resolution time AHB/APB2 prescaler distinct from 1, fTIMxCLK = 168 MHz 1 - tTIMxCLK 5.95 - ns AHB/APB2 prescaler = 1, fTIMxCLK = 84 MHz 1 - tTIMxCLK 11.9 - ns fEXT Timer external clock frequency on CH1 to CH4 fTIMxCLK = 168 MHz APB2 = 84 MHz 0 fTIMxCLK/2 MHz 0 84 MHz ResTIM Timer resolution - 16 bit tCOUNTER 16-bit counter clock period when internal clock is selected 1 65536 tTIMxCLK tMAX_COUNT Maximum possible count - 32768 tTIMxCLK Table 53. I2C characteristics Symbol Parameter Standard mode I2C(1) Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - μs tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - ns th(SDA) SDA data hold time 0(3) - 0 900(4) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 20 + 0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 DocID022152 Rev 4 117/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 39. I2C bus AC waveforms and measurement circuit 1. Rs= series protection resistor. 2. Rp = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. th(STA) Start condition hold time 4.0 - 0.6 - μs tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - μs tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - μs Cb Capacitive load for each bus line - 400 - 400 pF 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal. Table 53. I2C characteristics (continued) Symbol Parameter Standard mode I2C(1) Fast mode I2C(1)(2) Unit Min Max Min Max ai14979c S TAR T SD A RP I²C bus VDD_I2C STM32Fxx SDA SCL tf(SDA) tr(SDA) SCL th(STA) tw(SCLH) tw(SCLL) tsu(SDA) tr(SCL) tf(SCL) th(SDA) S TAR T REPEATED t S TAR T su(STA) tsu(STO) S TOP tw(STO:STA) VDD_I2C RP RS RS Electrical characteristics STM32F405xx, STM32F407xx 118/185 DocID022152 Rev 4 SPI interface characteristics Unless otherwise specified, the parameters given in Table 55 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14 with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 54. SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V)(1)(2) 1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. fSCL (kHz) I2C_CCR value RP = 4.7 kΩ 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE Table 55. SPI dynamic characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fSCK SPI clock frequency Master mode, SPI1, 2.7V < VDD < 3.6V - - 42 MHz Slave mode, SPI1, 2.7V < VDD < 3.6V 42 1/tc(SCK) Master mode, SPI1/2/3, 1.7V < VDD < 3.6V - - 21 Slave mode, SPI1/2/3, 1.7V < VDD < 3.6V 21 Duty(SCK) Duty cycle of SPI clock frequency Slave mode 30 50 70 % DocID022152 Rev 4 119/185 STM32F405xx, STM32F407xx Electrical characteristics tw(SCKH) SCK high and low time Master mode, SPI presc = 2, 2.7V < VDD < 3.6V TPCLK-0.5 TPCLK TPCLK+0.5 ns tw(SCKL) Master mode, SPI presc = 2, 1.7V < VDD < 3.6V TPCLK-2 TPCLK TPCLK+2 tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4 x TPCLK - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2 x TPCLK tsu(MI) Data input setup time Master mode 6.5 - - tsu(SI) Slave mode 2.5 - - th(MI) Data input hold time Master mode 2.5 - - th(SI) Slave mode 4 - - ta(SO) (2) Data output access time Slave mode, SPI presc = 2 0 - 4 x TPCLK tdis(SO) (3) Data output disable time Slave mode, SPI1, 2.7V < VDD < 3.6V 0 - 7.5 Slave mode, SPI1/2/3 1.7V < VDD < 3.6V 0 - 16.5 tv(SO) th(SO) Data output valid/hold time Slave mode (after enable edge), SPI1, 2.7V < VDD < 3.6V - 11 13 Slave mode (after enable edge), SPI2/3, 2.7V < VDD < 3.6V - 12 16.5 Slave mode (after enable edge), SPI1, 1.7V < VDD < 3.6V - 15.5 19 Slave mode (after enable edge), SPI2/3, 1.7V < VDD < 3.6V - 18 20.5 tv(MO) Data output valid time Master mode (after enable edge), SPI1 , 2.7V < VDD < 3.6V - - 2.5 Master mode (after enable edge), SPI1/2/3 , 1.7V < VDD < 3.6V - - 4.5 th(MO) Data output hold time Master mode (after enable edge) 0 - - 1. Data based on characterization results, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. Table 55. SPI dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit Electrical characteristics STM32F405xx, STM32F407xx 120/185 DocID022152 Rev 4 Figure 40. SPI timing diagram - slave mode and CPHA = 0 Figure 41. SPI timing diagram - slave mode and CPHA = 1 ai14134c SCK Input CPHA=0 MOSI INPUT MISO OUT PUT CPHA=0 MSB O UT MSB IN BIT6 OUT LSB IN LSB OUT CPOL=0 CPOL=1 BIT1 IN NSS input tSU(NSS) tc(SCK) th(NSS) ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) tsu(SI) th(SI) ai14135 SCK Input CPHA=1 MOSI INPUT MISO OUT PUT CPHA=1 MSB O UT MSB IN BIT6 OUT LSB IN LSB OUT CPOL=0 CPOL=1 BIT1 IN tSU(NSS) tc(SCK) th(NSS) ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) tsu(SI) th(SI) NSS input DocID022152 Rev 4 121/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 42. SPI timing diagram - master mode ai14136 SCK Input CPHA=0 MOSI OUTUT MISO INPUT CPHA=0 MSBIN MSB OUT BIT6 IN LSB OUT LSB IN CPOL=0 CPOL=1 BIT1 OUT NSS input tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) th(MI) High SCK Input CPHA=1 CPHA=1 CPOL=0 CPOL=1 tsu(MI) tv(MO) th(MO) Electrical characteristics STM32F405xx, STM32F407xx 122/185 DocID022152 Rev 4 I2S interface characteristics Unless otherwise specified, the parameters given in Table 56 for the i2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Note: Refer to the I2S section of RM0090 reference manual for more details on the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The value of these parameters might be slightly impacted by the source clock accuracy. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of I2SDIV / (2 x I2SDIV + ODD) and a maximum value of (I2SDIV + ODD) / (2 x I2SDIV + ODD). FS maximum value is supported for each mode/condition. Table 56. I2S dynamic characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S main clock output - 256 x 8K 256 x FS (2) MHz fCK I2S clock frequency Master data: 32 bits - 64 x FS MHz Slave data: 32 bits - 64 x FS DCK I2S clock frequency duty cycle Slave receiver 30 70 % tv(WS) WS valid time Master mode 0 6 ns th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 1 - th(WS) WS hold time Slave mode 0 - tsu(SD_MR) Data input setup time Master receiver 7.5 - tsu(SD_SR) Slave receiver 2 - th(SD_MR) Data input hold time Master receiver 0 - th(SD_SR) Slave receiver 0 - tv(SD_ST) th(SD_ST) Data output valid time Slave transmitter (after enable edge) - 27 tv(SD_MT) Master transmitter (after enable edge) - 20 th(SD_MT) Data output hold time Master transmitter (after enable edge) 2.5 - 1. Data based on characterization results, not tested in production. 2. The maximum value of 256 x FS is 42 MHz (APB1 maximum frequency). DocID022152 Rev 4 123/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 43. I2S slave timing diagram (Philips protocol) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 44. I2S master timing diagram (Philips protocol)(1) 1. Based on characterization, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. USB OTG FS characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. CK Input CPOL = 0 CPOL = 1 tc(CK) WS input SDtransmit SDreceive tw(CKH) tw(CKL) tsu(WS) tv(SD_ST) th(SD_ST) th(WS) tsu(SD_SR) th(SD_SR) MSB receive Bitn receive LSB receive MSB transmit Bitn transmit LSB transmit ai14881b LSB receive(2) LSB transmit(2) CK output CPOL = 0 CPOL = 1 tc(CK) WS output SDreceive SDtransmit tw(CKH) tw(CKL) tsu(SD_MR) tv(SD_MT) th(SD_MT) th(WS) th(SD_MR) MSB receive Bitn receive LSB receive MSB transmit Bitn transmit LSB transmit ai14884b tf(CK) tr(CK) tv(WS) LSB receive(2) LSB transmit(2) Electrical characteristics STM32F405xx, STM32F407xx 124/185 DocID022152 Rev 4 Figure 45. USB OTG FS timings: definition of data signal rise and fall time Table 57. USB OTG FS startup time Symbol Parameter Max Unit tSTARTUP (1) 1. Guaranteed by design, not tested in production. USB OTG FS transceiver startup time 1 μs Table 58. USB OTG FS DC electrical characteristics Symbol Parameter Conditions Min.(1) 1. All the voltages are measured from the local ground potential. Typ. Max.(1) Unit Input levels VDD USB OTG FS operating voltage 3.0(2) 2. The STM32F405xx and STM32F407xx USB OTG FS functionality is ensured down to 2.7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. - 3.6 V VDI (3) 3. Guaranteed by design, not tested in production. Differential input sensitivity I(USB_FS_DP/DM, USB_HS_DP/DM) 0.2 - - VCM V (3) Differential common mode range Includes VDI range 0.8 - 2.5 VSE (3) Single ended receiver threshold 1.3 - 2.0 Output levels VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) 4. RL is the load connected on the USB OTG FS drivers - - 0.3 V VOH Static output level high RL of 15 kΩ to VSS (4) 2.8 - 3.6 RPD PA11, PA12, PB14, PB15 (USB_FS_DP/DM, USB_HS_DP/DM) VIN = VDD 17 21 24 kΩ PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) 0.65 1.1 2.0 RPU PA12, PB15 (USB_FS_DP, USB_HS_DP) VIN = VSS 1.5 1.8 2.1 PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VSS 0.25 0.37 0.55 ai14137 tf Differen tial Data L ines VSS VCRS tr Crossover points DocID022152 Rev 4 125/185 STM32F405xx, STM32F407xx Electrical characteristics USB HS characteristics Unless otherwise specified, the parameters given in Table 62 for ULPI are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 61 and VDD supply voltage conditions summarized in Table 60, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD. Refer to Section Section 5.3.16: I/O port characteristics for more details on the input/outputcharacteristics. Table 59. USB OTG FS electrical characteristics(1) 1. Guaranteed by design, not tested in production. Driver characteristics Symbol Parameter Conditions Min Max Unit tr Rise time(2) 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). CL = 50 pF 4 20 ns tf Fall time(2) CL = 50 pF 4 20 ns trfm Rise/ fall time matching tr/tf 90 110 % VCRS Output signal crossover voltage 1.3 2.0 V Table 60. USB HS DC electrical characteristics Symbol Parameter Min.(1) 1. All the voltages are measured from the local ground potential. Max.(1) Unit Input level VDD USB OTG HS operating voltage 2.7 3.6 V Table 61. USB HS clock timing parameters(1) Parameter Symbol Min Nominal Max Unit fHCLK value to guarantee proper operation of USB HS interface 30 MHz Frequency (first transition) 8-bit ±10% FSTART_8BIT 54 60 66 MHz Frequency (steady state) ±500 ppm FSTEADY 59.97 60 60.03 MHz Duty cycle (first transition) 8-bit ±10% DSTART_8BIT 40 50 60 % Duty cycle (steady state) ±500 ppm DSTEADY 49.975 50 50.025 % Time to reach the steady state frequency and duty cycle after the first transition TSTEADY - - 1.4 ms Clock startup time after the de-assertion of SuspendM Peripheral TSTART_DEV - - 5.6 ms Host TSTART_HOST - - - PHY preparation time after the first transition of the input clock TPREP - - - μs Electrical characteristics STM32F405xx, STM32F407xx 126/185 DocID022152 Rev 4 Figure 46. ULPI timing diagram Ethernet characteristics Unless otherwise specified, the parameters given in Table 64, Table 65 and Table 66 for SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 14 and VDD supply voltage conditions summarized in Table 63, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 5.3.16: I/O port characteristics for more details on the input/output characteristics. 1. Guaranteed by design, not tested in production. Table 62. ULPI timing Parameter Symbol Value(1) 1. VDD = 2.7 V to 3.6 V and TA = –40 to 85 °C. Unit Min. Max. Control in (ULPI_DIR) setup time tSC - 2.0 ns Control in (ULPI_NXT) setup time - 1.5 Control in (ULPI_DIR, ULPI_NXT) hold time tHC 0 - Data in setup time tSD - 2.0 Data in hold time tHD 0 - Control out (ULPI_STP) setup time and hold time tDC - 9.2 Data out available from clock rising edge tDD - 10.7 Clock Control In (ULPI_DIR, ULPI_NXT) data In (8-bit) Control out (ULPI_STP) data out (8-bit) tDD tDC tSD tHD tSC tHC ai17361c tDC DocID022152 Rev 4 127/185 STM32F405xx, STM32F407xx Electrical characteristics Table 64 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 47 shows the corresponding timing diagram. Figure 47. Ethernet SMI timing diagram Table 65 gives the list of Ethernet MAC signals for the RMII and Figure 48 shows the corresponding timing diagram. Figure 48. Ethernet RMII timing diagram Table 63. Ethernet DC electrical characteristics Symbol Parameter Min.(1) 1. All the voltages are measured from the local ground potential. Max.(1) Unit Input level VDD Ethernet operating voltage 2.7 3.6 V Table 64. Dynamic characteristics: Ehternet MAC signals for SMI(1) 1. Data based on characterization results, not tested in production. Symbol Parameter Min Typ Max Unit tMDC MDC cycle time( 2.38 MHz) 411 420 425 ns Td(MDIO) Write data valid time 6 10 13 tsu(MDIO) Read data setup time 12 - - th(MDIO) Read data hold time 0 - - MS31384V1 ETH_MDC ETH_MDIO(O) ETH_MDIO(I) tMDC td(MDIO) tsu(MDIO) th(MDIO) RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV td(TXEN) td(TXD) tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) ai15667 Electrical characteristics STM32F405xx, STM32F407xx 128/185 DocID022152 Rev 4 Table 66 gives the list of Ethernet MAC signals for MII and Figure 48 shows the corresponding timing diagram. Figure 49. Ethernet MII timing diagram Table 65. Dynamic characteristics: Ethernet MAC signals for RMII Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 2 - - ns tih(RXD) Receive data hold time 1 - - ns tsu(CRS) Carrier sense set-up time 0.5 - - ns tih(CRS) Carrier sense hold time 2 - - ns td(TXEN) Transmit enable valid delay time 8 9.5 11 ns td(TXD) Transmit data valid delay time 8.5 10 11.5 ns Table 66. Dynamic characteristics: Ethernet MAC signals for MII(1) 1. Data based on characterization results, not tested in production. Symbol Parameter Min Typ Max Unit tsu(RXD) Receive data setup time 9 - ns tih(RXD) Receive data hold time 10 - tsu(DV) Data valid setup time 9 - tih(DV) Data valid hold time 8 - tsu(ER) Error setup time 6 - tih(ER) Error hold time 8 - td(TXEN) Transmit enable valid delay time 0 10 14 td(TXD) Transmit data valid delay time 0 10 15 MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER td(TXEN) td(TXD) tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) ai15668 MII_TX_CLK MII_TX_EN MII_TXD[3:0] DocID022152 Rev 4 129/185 STM32F405xx, STM32F407xx Electrical characteristics CAN (controller area network) interface Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 5.3.20 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 14. Table 67. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 1.8(1) - 3.6 V VREF+ Positive reference voltage 1.8(1)(2)(3) - VDDA V fADC ADC clock frequency VDDA = 1.8(1)(3) to 2.4 V 0.6 15 18 MHz VDDA = 2.4 to 3.6 V(3) 0.6 30 36 MHz fTRIG (4) External trigger frequency fADC = 30 MHz, 12-bit resolution - - 1764 kHz - - 17 1/fADC VAIN Conversion voltage range(5) 0 (VSSA or VREFtied to ground) - VREF+ V RAIN (4) External input impedance See Equation 1 for details - - 50 κΩ RADC (4)(6) Sampling switch resistance - - 6 κΩ CADC (4) Internal sample and hold capacitor - 4 - pF tlat (4) Injection trigger conversion latency fADC = 30 MHz - - 0.100 μs - - 3(7) 1/fADC tlatr (4) Regular trigger conversion latency fADC = 30 MHz - - 0.067 μs - - 2(7) 1/fADC tS (4) Sampling time fADC = 30 MHz 0.100 - 16 μs 3 - 480 1/fADC tSTAB (4) Power-up time - 2 3 μs Electrical characteristics STM32F405xx, STM32F407xx 130/185 DocID022152 Rev 4 Equation 1: RAIN max formula The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. tCONV (4) Total conversion time (including sampling time) fADC = 30 MHz 12-bit resolution 0.50 - 16.40 μs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 μs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 μs fADC = 30 MHz 6-bit resolution 0.30 - 16.20 μs 9 to 492 (tS for sampling +n-bit resolution for successive approximation) 1/fADC fS (4) Sampling rate (fADC = 30 MHz, and tS = 3 ADC cycles) 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps IVREF+ (4) ADC VREF DC current consumption in conversion mode - 300 500 μA IVDDA (4) ADC VDDA DC current consumption in conversion mode - 1.6 1.8 mA 1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). 2. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V. 3. VDDA -VREF+ < 1.2 V. 4. Based on characterization, not tested in production. 5. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 6. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V. 7. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 67. Table 67. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit RAIN (k – 0.5) fADC CADC 2N + 2 × × ln( ) = -------------------------------------------------------------- – RADC DocID022152 Rev 4 131/185 STM32F405xx, STM32F407xx Electrical characteristics a Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.16 does not affect the ADC accuracy. Figure 50. ADC accuracy characteristics 1. See also Table 68. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. Table 68. ADC accuracy at fADC = 30 MHz(1) 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. Symbol Parameter Test conditions Typ Max(2) 2. Based on characterization, not tested in production. Unit ET Total unadjusted error fPCLK2 = 60 MHz, fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 1.8(3) to 3.6 V 3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). ±2 ±5 LSB EO Offset error ±1.5 ±2.5 EG Gain error ±1.5 ±3 ED Differential linearity error ±1 ±2 EL Integral linearity error ±1.5 ±3 ai14395c EO EG 1L SBIDEAL 4095 4094 4093 5 4 3 2 1 0 7 6 1 2 3 456 7 4093 4094 4095 4096 (1) (2) ET ED EL (3) VSSA VDDA VREF+ 4096 (or depending on package)] VDDA 4096 [1LSB IDEAL = Electrical characteristics STM32F405xx, STM32F407xx 132/185 DocID022152 Rev 4 EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 51. Typical connection diagram using the ADC 1. Refer to Table 67 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. ai17534 VDD STM32F AINx IL±1 μA 0.6 V VT RAIN (1) Cparasitic VAIN 0.6 V VT RADC (1) CADC(1) 12-bit converter Sample and hold ADC converter DocID022152 Rev 4 133/185 STM32F405xx, STM32F407xx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 52 or Figure 53, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. VREF+ STM32F VDDA VSSA/V REF- 1 μF // 10 nF 1 μF // 10 nF ai17535 (See note 1) (See note 1) VREF+/VDDA STM32F 1 μF // 10 nF VREF–/VSSA ai17536 (See note 1) (See note 1) Electrical characteristics STM32F405xx, STM32F407xx 134/185 DocID022152 Rev 4 5.3.21 Temperature sensor characteristics 5.3.22 VBAT monitoring characteristics Table 69. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit TL (1) VSENSE linearity with temperature - ±1 ±2 °C Avg_Slope(1) Average slope - 2.5 mV/°C V25 (1) Voltage at 25 °C - 0.76 V tSTART (2) Startup time - 6 10 μs TS_temp (3)(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - - μs 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. Table 70. Temperature sensor calibration values Symbol Parameter Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA=3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, VDDA=3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F Table 71. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 50 - KΩ Q Ratio on VBAT measurement - 2 - Er(1) Error on Q –1 - +1 % TS_vbat (2)(2) ADC sampling time when reading the VBAT 1 mV accuracy 5 - - μs 1. Guaranteed by design, not tested in production. 2. Shortest sampling time can be determined in the application by multiple iterations. DocID022152 Rev 4 135/185 STM32F405xx, STM32F407xx Electrical characteristics 5.3.23 Embedded reference voltage The parameters given in Table 72 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. 5.3.24 DAC electrical characteristics Table 72. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.18 1.21 1.24 V TS_vrefint (1) ADC sampling time when reading the internal reference voltage 10 - - μs VRERINT_s (2) Internal reference voltage spread over the temperature range VDD = 3 V - 3 5 mV TCoeff (2) Temperature coefficient - 30 50 ppm/°C tSTART (2) Startup time - 6 10 μs 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. Table 73. Internal reference voltage calibration values Symbol Parameter Memory address VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA=3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B Table 74. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA Analog supply voltage 1.8(1) - 3.6 V VREF+ Reference supply voltage 1.8(1) - 3.6 V VREF+ ≤ VDDA VSSA Ground 0 - 0 V RLOAD (2) Resistive load with buffer ON 5 - - kΩ RO (2) Impedance output with buffer OFF - - 15 kΩ When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ CLOAD (2) Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT min(2) Lower DAC_OUT voltage with buffer ON 0.2 - - V It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.8 V DAC_OUT max(2) Higher DAC_OUT voltage with buffer ON - - VDDA – 0.2 V Electrical characteristics STM32F405xx, STM32F407xx 136/185 DocID022152 Rev 4 DAC_OUT min(2) Lower DAC_OUT voltage with buffer OFF - 0.5 - mV It gives the maximum output DAC_OUT excursion of the DAC. max(2) Higher DAC_OUT voltage with buffer OFF - - VREF+ – 1LSB V IVREF+ (4) DAC DC VREF current consumption in quiescent mode (Standby mode) - 170 240 μA With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs - 50 75 With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs IDDA (4) DAC DC VDDA current consumption in quiescent mode(3) - 280 380 μA With no load, middle code (0x800) on the inputs - 475 625 μA With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs DNL(4) Differential non linearity Difference between two consecutive code-1LSB) - - ±0.5 LSB Given for the DAC in 10-bit configuration. - - ±2 LSB Given for the DAC in 12-bit configuration. INL(4) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) - - ±1 LSB Given for the DAC in 10-bit configuration. - - ±4 LSB Given for the DAC in 12-bit configuration. Offset(4) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) - - ±10 mV Given for the DAC in 12-bit configuration - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V Gain error(4) Gain error - - ±0.5 % Given for the DAC in 12-bit configuration tSETTLING (4) Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±4LSB - 3 6 μs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ THD(4) Total Harmonic Distortion Buffer ON - - - dB CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Table 74. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments DocID022152 Rev 4 137/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 54. 12-bit buffered /non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.25 FSMC characteristics Unless otherwise specified, the parameters given in Table 75 to Table 86 for the FSMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section Section 5.3.16: I/O port characteristics for more details on the input/output characteristics. Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ tWAKEUP (4) Wakeup time from off state (Setting the ENx bit in the DAC Control register) - 6.5 10 μs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. PSRR+ (2) Power supply rejection ratio (to VDDA) (static DC measurement) - –67 –40 dB No RLOAD, CLOAD = 50 pF 1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). 2. Guaranteed by design, not tested in production. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization, not tested in production. Table 74. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments RLOAD CLOAD Buffered/Non-buffered DAC DACx_OUT Buffer(1) 12-bit digital to analog converter ai17157 Electrical characteristics STM32F405xx, STM32F407xx 138/185 DocID022152 Rev 4 Asynchronous waveforms and timings Figure 55 through Figure 58 represent asynchronous waveforms and Table 75 through Table 78 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • AddressSetupTime = 1 • AddressHoldTime = 0x1 • DataSetupTime = 0x1 • BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 2THCLK–0.5 2 THCLK+1 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 0.5 3 ns tw(NOE) FSMC_NOE low time 2THCLK–2 2THCLK+ 2 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 4.5 ns th(A_NOE) Address hold time after FSMC_NOE high 4 - ns Data FSMC_NE FSMC_NBL[1:0] FSMC_D[15:0] tv(BL_NE) t h(Data_NE) FSMC_NOE FSMC_A[25:0] Address tv(A_NE) FSMC_NWE tsu(Data_NE) tw(NE) ai14991c tv(NOE_NE) t w(NOE) t h(NE_NOE) th(Data_NOE) t h(A_NOE) t h(BL_NOE) tsu(Data_NOE) FSMC_NADV(1) t v(NADV_NE) tw(NADV) DocID022152 Rev 4 139/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.5 ns th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 - ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+4 - ns tsu(Data_NOE) Data to FSMC_NOEx high setup time THCLK+4 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns tw(NADV) FSMC_NADV low time - THCLK ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3THCLK 3THCLK+ 4 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK–0.5 THCLK+0.5 ns tw(NWE) FSMC_NWE low time THCLK–1 THCLK+2 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK–1 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 0 ns Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) NBL Data FSMC_NEx FSMC_NBL[1:0] FSMC_D[15:0] tv(BL_NE) th(Data_NWE) FSMC_NOE FSMC_A[25:0] Address tv(A_NE) tw(NWE) FSMC_NWE tv(NWE_NE) t h(NE_NWE) th(A_NWE) th(BL_NWE) tv(Data_NE) tw(NE) ai14990 FSMC_NADV(1) t v(NADV_NE) tw(NADV) Electrical characteristics STM32F405xx, STM32F407xx 140/185 DocID022152 Rev 4 Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms th(A_NWE) Address hold time after FSMC_NWE high THCLK– 2 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.5 ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK– 1 - ns tv(Data_NE) Data to FSMC_NEx low to Data valid - THCLK+3 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK–1 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns tw(NADV) FSMC_NADV low time - THCLK+0.5 ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 77. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3THCLK–1 3THCLK+1 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 2THCLK–0.5 2THCLK+0.5 ns tw(NOE) FSMC_NOE low time THCLK–1 THCLK+1 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 3 ns Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) NBL Data FSMC_NBL[1:0] FSMC_AD[15:0] tv(BL_NE) th(Data_NE) FSMC_A[25:16] Address tv(A_NE) FSMC_NWE t v(A_NE) ai14892b Address FSMC_NADV t v(NADV_NE) tw(NADV) tsu(Data_NE) th(AD_NADV) FSMC_NE FSMC_NOE tw(NE) t w(NOE) tv(NOE_NE) t h(NE_NOE) th(A_NOE) th(BL_NOE) tsu(Data_NOE) th(Data_NOE) DocID022152 Rev 4 141/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1 2 ns tw(NADV) FSMC_NADV low time THCLK– 2 THCLK+1 ns th(AD_NADV) FSMC_AD(adress) valid hold time after FSMC_NADV high) THCLK - ns th(A_NOE) Address hold time after FSMC_NOE high THCLK–1 - ns th(BL_NOE) FSMC_BL time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 2 ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+4 - ns tsu(Data_NOE) Data to FSMC_NOE high setup time THCLK+4 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 78. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 4THCLK–0.5 4THCLK+3 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK–0.5 THCLK -0.5 ns tw(NWE) FSMC_NWE low tim e 2THCLK–0.5 2THCLK+3 ns Table 77. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) (continued) NBL Data FSMC_NEx FSMC_NBL[1:0] FSMC_AD[15:0] tv(BL_NE) th(Data_NWE) FSMC_NOE FSMC_A[25:16] Address tv(A_NE) tw(NWE) FSMC_NWE tv(NWE_NE) t h(NE_NWE) th(A_NWE) th(BL_NWE) t v(A_NE) tw(NE) ai14891B Address FSMC_NADV t v(NADV_NE) tw(NADV) t v(Data_NADV) th(AD_NADV) Electrical characteristics STM32F405xx, STM32F407xx 142/185 DocID022152 Rev 4 Synchronous waveforms and timings Figure 59 through Figure 62 represent synchronous waveforms and Table 80 through Table 82 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • BurstAccessMode = FSMC_BurstAccessMode_Enable; • MemoryType = FSMC_MemoryType_CRAM; • WriteBurst = FSMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period (with maximum FSMC_CLK = 60 MHz). th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 0 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1 2 ns tw(NADV) FSMC_NADV low time THCLK– 2 THCLK+ 1 ns th(AD_NADV) FSMC_AD(address) valid hold time after FSMC_NADV high) THCLK–2 - ns th(A_NWE) Address hold time after FSMC_NWE high THCLK - ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK–2 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.5 ns tv(Data_NADV) FSMC_NADV high to Data valid - THCLK–0.5 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 78. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) DocID022152 Rev 4 143/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 59. Synchronous multiplexed NOR/PSRAM read timings Table 79. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 2 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 0 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 2 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 4.5 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 6 - ns FSMC_CLK FSMC_NEx FSMC_NADV FSMC_A[25:16] FSMC_NOE FSMC_AD[15:0] AD[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-NADVL) td(CLKL-AV) td(CLKL-NADVH) td(CLKL-AIV) td(CLKL-NOEL) td(CLKL-NOEH) td(CLKL-ADV) td(CLKL-ADIV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14893g Electrical characteristics STM32F405xx, STM32F407xx 144/185 DocID022152 Rev 4 Figure 60. Synchronous multiplexed PSRAM write timings th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 80. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 0 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns Table 79. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) FSMC_CLK FSMC_NEx FSMC_NADV FSMC_A[25:16] FSMC_NWE FSMC_AD[15:0] AD[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-NADVL) td(CLKL-AV) td(CLKL-NADVH) td(CLKL-AIV) td(CLKL-NWEL) td(CLKL-NWEH) td(CLKL-NBLH) td(CLKL-ADV) td(CLKL-ADIV) td(CLKL-Data) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14992g td(CLKL-Data) FSMC_NBL DocID022152 Rev 4 145/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 8 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 0.5 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 0 - ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low - 3 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 0 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 81. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK –0.5 - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0.5 ns Table 80. Synchronous multiplexed PSRAM write timings(1)(2) FSMC_CLK FSMC_NEx FSMC_A[25:0] FSMC_NOE FSMC_D[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-AV) td(CLKL-AIV) td(CLKL-NOEL) td(CLKL-NOEH) tsu(DV-CLKH) th(CLKH-DV) tsu(DV-CLKH) th(CLKH-DV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14894f FSMC_NADV td(CLKL-NADVL) td(CLKL-NADVH) Electrical characteristics STM32F405xx, STM32F407xx 146/185 DocID022152 Rev 4 Figure 62. Synchronous non-multiplexed PSRAM write timings td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 0 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 3 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 2 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0.5 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 6 - ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 3 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 81. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) (continued) FSMC_CLK FSMC_NEx FSMC_A[25:0] FSMC_NWE FSMC_D[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-AV) td(CLKL-AIV) td(CLKL-NWEL) td(CLKL-NWEH) td(CLKL-Data) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14993g FSMC_NADV td(CLKL-NADVL) td(CLKL-NADVH) td(CLKL-Data) FSMC_NBL td(CLKL-NBLH) DocID022152 Rev 4 147/185 STM32F405xx, STM32F407xx Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 63 through Figure 68 represent synchronous waveforms, and Table 83 and Table 84 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x04; • ATT.FSMC_WaitSetupTime = 0x07; • ATT.FSMC_HoldSetupTime = 0x04; • ATT.FSMC_HiZSetupTime = 0x00; • IO.FSMC_SetupTime = 0x04; • IO.FSMC_WaitSetupTime = 0x07; • IO.FSMC_HoldSetupTime = 0x04; • IO.FSMC_HiZSetupTime = 0x00; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. Table 82. Synchronous non-multiplexed PSRAM write timings(1)(2) 1. CL = 30 pF. 2. Based on characterization, not tested in production. Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 7 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 6 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 6 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 2 - ns td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 3 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 3 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns Electrical characteristics STM32F405xx, STM32F407xx 148/185 DocID022152 Rev 4 Figure 63. PC Card/CompactFlash controller waveforms for common memory read access 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. Figure 64. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NWE tw(NOE) FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_2(1) FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NCE4_1-NOE) tsu(D-NOE) th(NOE-D) tv(NCEx-A) td(NREG-NCEx) td(NIORD-NCEx) th(NCEx-AI) th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR) ai14895b td(NCE4_1-NWE) tw(NWE) th(NWE-D) tv(NCE4_1-A) td(NREG-NCE4_1) td(NIORD-NCE4_1) th(NCE4_1-AI) MEMxHIZ =1 tv(NWE-D) th(NCE4_1-NREG) th(NCE4_1-NIORD) th(NCE4_1-NIOWR) ai14896b FSMC_NWE FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NWE-NCE4_1) td(D-NWE) FSMC_NCE4_2 High DocID022152 Rev 4 149/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access 1. Only data bits 0...7 are read (bits 8...15 are disregarded). td(NCE4_1-NOE) tw(NOE) tsu(D-NOE) th(NOE-D) tv(NCE4_1-A) th(NCE4_1-AI) td(NREG-NCE4_1) th(NCE4_1-NREG) ai14897b FSMC_NWE FSMC_NOE FSMC_D[15:0](1) FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NOE-NCE4_1) High Electrical characteristics STM32F405xx, STM32F407xx 150/185 DocID022152 Rev 4 Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access tw(NWE) tv(NCE4_1-A) td(NREG-NCE4_1) th(NCE4_1-AI) th(NCE4_1-NREG) tv(NWE-D) ai14898b FSMC_NWE FSMC_NOE FSMC_D[7:0](1) FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NWE-NCE4_1) High td(NCE4_1-NWE) td(NIORD-NCE4_1) tw(NIORD) tsu(D-NIORD) td(NIORD-D) tv(NCEx-A) th(NCE4_1-AI) ai14899B FSMC_NWE FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD DocID022152 Rev 4 151/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access td(NCE4_1-NIOWR) tw(NIOWR) tv(NCEx-A) th(NCE4_1-AI) th(NIOWR-D) ATTxHIZ =1 tv(NIOWR-D) ai14900c FSMC_NWE FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space(1)(2) Symbol Parameter Min Max Unit tv(NCEx-A) FSMC_Ncex low to FSMC_Ay valid - 0 ns th(NCEx_AI) FSMC_NCEx high to FSMC_Ax invalid 4 - ns td(NREG-NCEx) FSMC_NCEx low to FSMC_NREG valid - 3.5 ns th(NCEx-NREG) FSMC_NCEx high to FSMC_NREG invalid THCLK+4 - ns td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5THCLK+0.5 ns td(NCEx-NOE) FSMC_NCEx low to FSMC_NOE low - 5THCLK +0.5 ns tw(NOE) FSMC_NOE low width 8THCLK–1 8THCLK+1 ns td(NOE_NCEx) FSMC_NOE high to FSMC_NCEx high 5THCLK+2.5 - ns tsu (D-NOE) FSMC_D[15:0] valid data before FSMC_NOE high 4.5 - ns th(N0E-D) FSMC_N0E high to FSMC_D[15:0] invalid 3 - ns tw(NWE) FSMC_NWE low width 8THCLK–0.5 8THCLK+ 3 ns td(NWE_NCEx) FSMC_NWE high to FSMC_NCEx high 5THCLK–1 - ns td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5THCLK+ 1 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15:0] valid - 0 ns th (NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 8THCLK –1 - ns td (D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 13THCLK –1 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Electrical characteristics STM32F405xx, STM32F407xx 152/185 DocID022152 Rev 4 NAND controller waveforms and timings Figure 69 through Figure 72 represent synchronous waveforms, and Table 85 and Table 86 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x01; • COM.FSMC_WaitSetupTime = 0x03; • COM.FSMC_HoldSetupTime = 0x02; • COM.FSMC_HiZSetupTime = 0x01; • ATT.FSMC_SetupTime = 0x01; • ATT.FSMC_WaitSetupTime = 0x03; • ATT.FSMC_HoldSetupTime = 0x02; • ATT.FSMC_HiZSetupTime = 0x01; • Bank = FSMC_Bank_NAND; • MemoryDataWidth = FSMC_MemoryDataWidth_16b; • ECC = FSMC_ECC_Enable; • ECCPageSize = FSMC_ECCPageSize_512Bytes; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter Min Max Unit tw(NIOWR) FSMC_NIOWR low width 8THCLK –1 - ns tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid - 5THCLK– 1 ns th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid 8THCLK– 2 - ns td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid - 5THCLK+ 2.5 ns th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid 5THCLK–1.5 - ns td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid - 5THCLK+ 2 ns th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD) valid 5THCLK– 1.5 - ns tw(NIORD) FSMC_NIORD low width 8THCLK–0.5 - ns tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high 9 - ns td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. DocID022152 Rev 4 153/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 69. NAND controller waveforms for read access Figure 70. NAND controller waveforms for write access FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] tsu(D-NOE) th(NOE-D) ai14901c ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NCEx td(ALE-NOE) th(NOE-ALE) tv(NWE-D) th(NWE-D) ai14902c FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NCEx td(ALE-NWE) th(NWE-ALE) Electrical characteristics STM32F405xx, STM32F407xx 154/185 DocID022152 Rev 4 Figure 71. NAND controller waveforms for common memory read access Figure 72. NAND controller waveforms for common memory write access Table 85. Switching characteristics for NAND Flash read cycles(1) 1. CL = 30 pF. Symbol Parameter Min Max Unit tw(N0E) FSMC_NOE low width 4THCLK– 0.5 4THCLK+ 3 ns tsu(D-NOE) FSMC_D[15-0] valid data before FSMC_NOE high 10 - ns th(NOE-D) FSMC_D[15-0] valid data after FSMC_NOE high 0 - ns td(ALE-NOE) FSMC_ALE valid before FSMC_NOE low - 3THCLK ns th(NOE-ALE) FSMC_NWE high to FSMC_ALE invalid 3THCLK– 2 - ns FSMC_NWE FSMC_NOE FSMC_D[15:0] tw(NOE) tsu(D-NOE) th(NOE-D) ai14912c ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NCEx td(ALE-NOE) th(NOE-ALE) tw(NWE) tv(NWE-D) th(NWE-D) ai14913c FSMC_NWE FSMC_NOE FSMC_D[15:0] td(D-NWE) ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NCEx td(ALE-NOE) th(NOE-ALE) DocID022152 Rev 4 155/185 STM32F405xx, STM32F407xx Electrical characteristics 5.3.26 Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 87 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 13, with the following configuration: • PCK polarity: falling • VSYNC and HSYNC polarity: high • Data format: 14 bits Figure 73. DCMI timing diagram Table 86. Switching characteristics for NAND Flash write cycles(1) 1. CL = 30 pF. Symbol Parameter Min Max Unit tw(NWE) FSMC_NWE low width 4THCLK–1 4THCLK+ 3 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15-0] valid - 0 ns th(NWE-D) FSMC_NWE high to FSMC_D[15-0] invalid 3THCLK –2 - ns td(D-NWE) FSMC_D[15-0] valid before FSMC_NWE high 5THCLK–3 - ns td(ALE-NWE) FSMC_ALE valid before FSMC_NWE low - 3THCLK ns th(NWE-ALE) FSMC_NWE high to FSMC_ALE invalid 3THCLK–2 - ns Table 87. DCMI characteristics(1) Symbol Parameter Min Max Unit Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 DCMI_PIXCLK Pixel clock input - 54 MHz Dpixel Pixel clock input duty cycle 30 70 % MS32414V1 Pixel clock tsu(VSYNC) tsu(HSYNC) HSYNC VSYNC DATA[0:13] 1/DCMI_PIXCLK th(HSYNC) th(HSYNC) tsu(DATA) th(DATA) Electrical characteristics STM32F405xx, STM32F407xx 156/185 DocID022152 Rev 4 5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 88 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14 with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 5.3.16: I/O port characteristics for more details on the input/output characteristics. Figure 74. SDIO high-speed mode tsu(DATA) Data input setup time 2.5 - ns th(DATA) Data hold time 1 - tsu(HSYNC), tsu(VSYNC) HSYNC/VSYNC input setup time 2 - th(HSYNC), th(VSYNC) HSYNC/VSYNC input hold time 0.5 - 1. Data based on characterization results, not tested in production. Table 87. DCMI characteristics(1) (continued) Symbol Parameter Min Max Unit tW(CKH) CK D, CMD (output) D, CMD (input) tC tW(CKL) tOV tOH tISU tIH tf tr ai14887 DocID022152 Rev 4 157/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 75. SD default mode 5.3.28 RTC characteristics CK D, CMD (output) tOVD tOHD ai14888 Table 88. Dynamic characteristics: SD / MMC characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode 0 48 MHz SDIO_CK/fPCLK2 frequency ratio - - 8/3 - tW(CKL) Clock low time fpp = 48 MHz 8.5 9 - ns tW(CKH) Clock high time fpp = 48 MHz 8.3 10 - CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU Input setup time HS fpp = 48 MHz 3 - - ns tIH Input hold time HS fpp = 48 MHz 0 - - CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time HS fpp = 48 MHz - 4.5 6 ns tOH Output hold time HS fpp = 48 MHz 1 - - CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD fpp = 24 MHz 1.5 - - ns tIHD Input hold time SD fpp = 24 MHz 0.5 - - CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fpp = 24 MHz - 4.5 7 ns tOHD Output hold default time SD fpp = 24 MHz 0.5 - - 1. Data based on characterization results, not tested in production. Table 89. RTC characteristics Symbol Parameter Conditions Min Max - fPCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register 4 - Package characteristics STM32F405xx, STM32F407xx 158/185 DocID022152 Rev 4 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID022152 Rev 4 159/185 STM32F405xx, STM32F407xx Package characteristics Figure 76. WLCSP90 - 0.400 mm pitch wafer level chip size package outline Bump side Side view Detail A Wafer back side A1 ball location A1 Detail A rotated by 90 °C eee D A0JW_ME Seating plane A2 A b E e e1 e G F e2 Table 90. WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max A 0.520 0.570 0.620 0.0205 0.0224 0.0244 A1 0.165 0.190 0.215 0.0065 0.0075 0.0085 A2 0.350 0.380 0.410 0.0138 0.015 0.0161 b 0.240 0.270 0.300 0.0094 0.0106 0.0118 D 4.178 4.218 4.258 0.1645 0.1661 0.1676 E 3.964 3.969 4.004 0.1561 0.1563 0.1576 e 0.400 0.0157 e1 3.600 0.1417 e2 3.200 0.126 F 0.312 0.0123 G 0.385 0.0152 eee 0.050 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Package characteristics STM32F405xx, STM32F407xx 160/185 DocID022152 Rev 4 Figure 77. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline 1. Drawing is not to scale. ai14398b A A2 A1 c L1 L E E1 D D1 e b Table 91. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max A 1.600 0.0630 A1 0.050 0.150 0.0020 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 D 12.000 0.4724 D1 10.000 0.3937 E 12.000 0.4724 E1 10.000 0.3937 e 0.500 0.0197 θ 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 1.000 0.0394 N Number of pins 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID022152 Rev 4 161/185 STM32F405xx, STM32F407xx Package characteristics Figure 78. LQFP64 recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. 48 49 32 64 17 1 16 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 Package characteristics STM32F405xx, STM32F407xx 162/185 DocID022152 Rev 4 Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline 1. Drawing is not to scale. IDENTIFICATION e PIN 1 GAUGE PLANE 0.25 mm SEATING PLANE D D1 D3 E3 E1 E K ccc C C 1 25 100 26 76 75 51 50 1L_ME_V4 A2 A A1 L1 L c b A1 Table 92. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data(1) Symbol millimeters inches Min Typ Max Min Typ Max A 1.600 0.0630 A1 0.050 0.150 0.0020 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 12.000 0.4724 E 15.80v 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 12.000 0.4724 e 0.500 0.0197 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 1.000 0.0394 k 0° 3.5° 7° 0° 3.5° 7° ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID022152 Rev 4 163/185 STM32F405xx, STM32F407xx Package characteristics Figure 80. LQFP100 recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. 75 51 76 50 0.5 0.3 16.7 14.3 100 26 12.3 25 1.2 16.7 1 ai14906 Package characteristics STM32F405xx, STM32F407xx 164/185 DocID022152 Rev 4 Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline 1. Drawing is not to scale. D1 D3 D E3 E1 E e Pin 1 identification 73 72 37 36 109 144 108 1 A A2A1 b c A1 L L1 k Seating plane C ccc C 0.25 mm gage plane ME_1A Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max A 1.600 0.0630 A1 0.050 0.150 0.0020 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.874 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 17.500 0.689 E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 17.500 0.6890 e 0.500 0.0197 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 1.000 0.0394 DocID022152 Rev 4 165/185 STM32F405xx, STM32F407xx Package characteristics Figure 82. LQFP144 recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. k 0° 3.5° 7° 0° 3.5° 7° ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max ai14905c 0.5 0.35 19.9 17.85 22.6 1.35 22.6 19.9 1 36 37 72 108 73 109 144 Package characteristics STM32F405xx, STM32F407xx 166/185 DocID022152 Rev 4 Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline 1. Drawing is not to scale. Table 94. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data Symbol millimeters inches(1) 1. Values in inches are converted from mm and rounded to 4 decimal digits. Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.002 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 D 9.900 10.000 10.100 0.3898 0.3937 0.3976 E 9.900 10.000 10.100 0.3898 0.3937 0.3976 e 0.650 0.0256 F 0.425 0.450 0.475 0.0167 0.0177 0.0187 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.080 0.0031 A0E7_ME_V4 Seating plane A2 ddd C A1 A e F F e R A 15 1 BOTTOM VIEW E D TOP VIEW Øb (176 + 25 balls) B A Ø eee M B Ø fff M C C A C A1 ball identifier A1 ball index area DocID022152 Rev 4 167/185 STM32F405xx, STM32F407xx Package characteristics Figure 84. LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline 1. Drawing is not to scale. ccc C C Seating plane A A2 A1 c 0.25 mm gauge plane HD D A1 L L1 k 89 88 E HE 45 44 e 1 176 Pin 1 identification b 133 132 1T_ME ZD ZE Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max A 1.600 0.0630 A1 0.050 0.150 0.0020 A2 1.350 1.450 0.0531 0.0060 b 0.170 0.270 0.0067 0.0106 C 0.090 0.200 0.0035 0.0079 D 23.900 24.100 0.9409 0.9488 E 23.900 24.100 0.9409 0.9488 e 0.500 0.0197 HD 25.900 26.100 1.0200 1.0276 HE 25.900 26.100 1.0200 1.0276 L 0.450 0.750 0.0177 0.0295 L1 1.000 0.0394 ZD 1.250 0.0492 ZE 1.250 0.0492 Package characteristics STM32F405xx, STM32F407xx 168/185 DocID022152 Rev 4 Figure 85. LQFP176 recommended footprint 1. Dimensions are expressed in millimeters. ccc 0.080 0.0031 k 0 ° 7 ° 0 ° 7 ° 1. Values in inches are converted from mm and rounded to 4 decimal digits. Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max 1T_FP_V1 133 132 1.2 0.3 0.5 89 88 1.2 44 45 21.8 26.7 1 176 26.7 21.8 DocID022152 Rev 4 169/185 STM32F405xx, STM32F407xx Package characteristics 6.2 Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. Table 96. Package thermal characteristics Symbol Parameter Value Unit ΘJA Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch 46 °C/W Thermal resistance junction-ambient LQFP100 - 14 × 14 mm / 0.5 mm pitch 43 Thermal resistance junction-ambient LQFP144 - 20 × 20 mm / 0.5 mm pitch 40 Thermal resistance junction-ambient LQFP176 - 24 × 24 mm / 0.5 mm pitch 38 Thermal resistance junction-ambient UFBGA176 - 10× 10 mm / 0.65 mm pitch 39 Thermal resistance junction-ambient WLCSP90 - 0.400 mm pitch 38.1 Part numbering STM32F405xx, STM32F407xx 170/185 DocID022152 Rev 4 7 Part numbering For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 97. Ordering information scheme Example: STM32 F 405 R E T 6 xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 405 = STM32F40x, connectivity 407= STM32F40x, connectivity, camera interface, Ethernet Pin count R = 64 pins O = 90 pins V = 100 pins Z = 144 pins I = 176 pins Flash memory size E = 512 Kbytes of Flash memory G = 1024 Kbytes of Flash memory Package T = LQFP H = UFBGA Y = WLCSP Temperature range 6 = Industrial temperature range, –40 to 85 °C. 7 = Industrial temperature range, –40 to 105 °C. Options xxx = programmed parts TR = tape and reel DocID022152 Rev 4 171/185 STM32F405xx, STM32F407xx Application block diagrams Appendix A Application block diagrams A.1 USB OTG full speed (FS) interface solutions Figure 86. USB controller configured as peripheral-only and used in Full speed mode 1. External voltage regulator only needed when building a VBUS powered device. 2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. Figure 87. USB controller configured as host-only and used in full speed mode 1. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. STM32F4xx 5V to VDD Volatge regulator (1) VDD VBUS DP VSS PA12/PB15 PA11//PB14 USB Std-B connector DM OSC_IN OSC_OUT MS19000V5 STM32F4xx VDD VBUS DP VSS USB Std-A connector DM GPIO+IRQ GPIO EN Overcurrent 5 V Pwr OSC_IN OSC_OUT MS19001V4 Current limiter power switch(1) PA12/PB15 PA11//PB14 Application block diagrams STM32F405xx, STM32F407xx 172/185 DocID022152 Rev 4 Figure 88. USB controller configured in dual mode and used in full speed mode 1. External voltage regulator only needed when building a VBUS powered device. 2. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 3. The ID pin is required in dual role only. 4. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. STM32F4xx VDD VBUS DP VSS PA9/PB13 PA12/PB15 PA11/PB14 USB micro-AB connector DM GPIO+IRQ GPIO EN Overcurrent 5 V Pwr 5 V to VDD voltage regulator (1) VDD ID(3) PA10/PB12 OSC_IN OSC_OUT MS19002V3 Current limiter power switch(2) DocID022152 Rev 4 173/185 STM32F405xx, STM32F407xx Application block diagrams A.2 USB OTG high speed (HS) interface solutions Figure 89. USB controller configured as peripheral, host, or dual-mode and used in high speed mode 1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the STM32F40x with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example of a possible connection. 2. The ID pin is required in dual role only. DP STM32F4xx DM VBUS VSS DM DP ID(2) USB USB HS OTG Ctrl FS PHY ULPI High speed OTG PHY ULPI_CLK ULPI_D[7:0] ULPI_DIR ULPI_STP ULPI_NXT not connected connector MCO1 or MCO2 24 or 26 MHz XT(1) PLL XT1 XI MS19005V2 Application block diagrams STM32F405xx, STM32F407xx 174/185 DocID022152 Rev 4 A.3 Ethernet interface solutions Figure 90. MII mode using a 25 MHz crystal 1. fHCLK must be greater than 25 MHz. 2. Pulse per second when using IEEE1588 PTP optional signal. Figure 91. RMII with a 50 MHz oscillator 1. fHCLK must be greater than 25 MHz. MCU Ethernet MAC 10/100 Ethernet PHY 10/100 PLL HCLK XT1 PHY_CLK 25 MHz MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CRS MII_COL MDIO MDC HCLK(1) PPS_OUT(2) XTAL 25 MHz STM32 OSC TIM2 Timestamp comparator Timer input trigger IEEE1588 PTP MII = 15 pins MII + MDC = 17 pins MS19968V1 MCO1/MCO2 MCU Ethernet MAC 10/100 Ethernet PHY 10/100 PLL HCLK PHY_CLK 50 MHz XT1 RMII_RXD[1:0] RMII_CRX_DV RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] MDIO MDC HCLK(1) STM32 OSC 50 MHz TIM2 Timestamp comparator Timer input trigger IEEE1588 PTP RMII = 7 pins RMII + MDC = 9 pins MS19969V1 /2 or /20 2.5 or 25 MHz synchronous 50 MHz 50 MHz DocID022152 Rev 4 175/185 STM32F405xx, STM32F407xx Application block diagrams Figure 92. RMII with a 25 MHz crystal and PHY with PLL 1. fHCLK must be greater than 25 MHz. 2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL block. MCU Ethernet MAC 10/100 Ethernet PHY 10/100 PLL HCLK PHY_CLK 25 MHz XT1 RMII_RXD[1:0] RMII_CRX_DV RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] MDIO MDC HCLK(1) STM32F TIM2 Timestamp comparator Timer input trigger IEEE1588 PTP RMII = 7 pins RMII + MDC = 9 pins MS19970V1 /2 or /20 2.5 or 25 MHz synchronous 50 MHz XTAL 25 MHz OSC PLL REF_CLK MCO1/MCO2 Revision history STM32F405xx, STM32F407xx 176/185 DocID022152 Rev 4 8 Revision history Table 98. Document revision history Date Revision Changes 15-Sep-2011 1 Initial release. 24-Jan-2012 2 Added WLCSP90 package on cover page. Renamed USART4 and USART5 into UART4 and UART5, respectively. Updated number of USB OTG HS and FS in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Updated Figure 3: Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package and Figure 4: Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages, and removed note 1 and 2. Updated Section 2.2.9: Flexible static memory controller (FSMC). Modified I/Os used to reprogram the Flash memory for CAN2 and USB OTG FS in Section 2.2.13: Boot modes. Updated note in Section 2.2.14: Power supply schemes. PDR_ON no more available on LQFP100 package. Updated Section 2.2.16: Voltage regulator. Updated condition to obtain a minimum supply voltage of 1.7 V in the whole document. Renamed USART4/5 to UART4/5 and added LIN and IrDA feature for UART4 and UART5 in Table 5: USART feature comparison. Removed support of I2C for OTG PHY in Section 2.2.30: Universal serial bus on-the-go full-speed (OTG_FS). Added Table 6: Legend/abbreviations used in the pinout table. Table 7: STM32F40x pin and ball definitions: replaced VSS_3, VSS_4, and VSS_8 by VSS; reformatted Table 7: STM32F40x pin and ball definitions to better highlight I/O structure, and alternate functions versus additional functions; signal corresponding to LQFP100 pin 99 changed from PDR_ON to VSS; EVENTOUT added in the list of alternate functions for all I/Os; ADC3_IN8 added as alternate function for PF10; FSMC_CLE and FSMC_ALE added as alternate functions for PD11 and PD12, respectively; PH10 alternate function TIM15_CH1_ETR renamed TIM5_CH1; updated PA4 and PA5 I/O structure to TTa. Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in Table 7: STM32F40x pin and ball definitions and Table 9: Alternate function mapping. Changed TCM data RAM to CCM data RAM in Figure 18: STM32F40x memory map. Added IVDD and IVSS maximum values in Table 12: Current characteristics. Added Note 1 related to fHCLK, updated Note 2 in Table 14: General operating conditions, and added maximum power dissipation values. Updated Table 15: Limitations depending on the operating power supply range. DocID022152 Rev 4 177/185 STM32F405xx, STM32F407xx Revision history 24-Jan-2012 2 (continued) Added V12 in Table 19: Embedded reset and power control block characteristics. Updated Table 21: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) and Table 20: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM. Added Figure , Figure 25, Figure 26, and Figure 27. Updated Table 22: Typical and maximum current consumption in Sleep mode and removed Note 1. Updated Table 23: Typical and maximum current consumptions in Stop mode and Table 24: Typical and maximum current consumptions in Standby mode, Table 25: Typical and maximum current consumptions in VBAT mode, and Table 26: Switching output I/O current consumption. Section : On-chip peripheral current consumption: modified conditions, and updated Table 27: Peripheral current consumption and Note 2. Changed fHSE_ext to 50 MHz and tr(HSE)/tf(HSE) maximum value in Table 29: High-speed external user clock characteristics. Added Cin(LSE) in Table 30: Low-speed external user clock characteristics. Updated maximum PLL input clock frequency, removed related note, and deleted jitter for MCO for RMII Ethernet typical value in Table 35: Main PLL characteristics. Updated maximum PLLI2S input clock frequency and removed related note in Table 36: PLLI2S (audio PLL) characteristics. Updated Section : Flash memory to specify that the devices are shipped to customers with the Flash memory erased. Updated Table 38: Flash memory characteristics, and added tME in Table 39: Flash memory programming. Updated Table 42: EMS characteristics, and Table 43: EMI characteristics. Updated Table 56: I2S dynamic characteristics Updated Figure 46: ULPI timing diagram and Table 62: ULPI timing. Added tCOUNTER and tMAX_COUNT in Table 51: Characteristics of TIMx connected to the APB1 domain and Table 52: Characteristics of TIMx connected to the APB2 domain. Updated Table 65: Dynamic characteristics: Ethernet MAC signals for RMII. Removed USB-IF certification in Section : USB OTG FS characteristics. Table 98. Document revision history (continued) Date Revision Changes Revision history STM32F405xx, STM32F407xx 178/185 DocID022152 Rev 4 24-Jan-2012 2 (continued) Updated Table 61: USB HS clock timing parameters Updated Table 67: ADC characteristics. Updated Table 68: ADC accuracy at fADC = 30 MHz. Updated Note 1 in Table 74: DAC characteristics. Section 5.3.25: FSMC characteristics: updated Table 75 toTable 86, changed CL value to 30 pF, and modified FSMC configuration for asynchronous timings and waveforms. Updated Figure 60: Synchronous multiplexed PSRAM write timings. Updated Table 96: Package thermal characteristics. Appendix A.1: USB OTG full speed (FS) interface solutions: modified Figure 86: USB controller configured as peripheral-only and used in Full speed mode added Note 2, updated Figure 87: USB controller configured as host-only and used in full speed mode and added Note 2, changed Figure 88: USB controller configured in dual mode and used in full speed mode and added Note 3. Appendix A.2: USB OTG high speed (HS) interface solutions: removed figures USB OTG HS device-only connection in FS mode and USB OTG HS host-only connection in FS mode, and updated Figure 89: USB controller configured as peripheral, host, or dual-mode and used in high speed mode and added Note 2. Added Appendix A.3: Ethernet interface solutions. Table 98. Document revision history (continued) Date Revision Changes DocID022152 Rev 4 179/185 STM32F405xx, STM32F407xx Revision history 31-May-2012 3 Updated Figure 5: STM32F40x block diagram and Figure 7: Power supply supervisor interconnection with internal reset OFF Added SDIO, added notes related to FSMC and SPI/I2S in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Starting from Silicon revision Z, USB OTG full-speed interface is now available for all STM32F405xx devices. Added full information on WLCSP90 package together with corresponding part numbers. Changed number of AHB buses to 3. Modified available Flash memory sizes in Section 2.2.4: Embedded Flash memory. Modified number of maskable interrupt channels in Section 2.2.10: Nested vectored interrupt controller (NVIC). Updated case of Regulator ON/internal reset ON, Regulator ON/internal reset OFF, and Regulator OFF/internal reset ON in Section 2.2.16: Voltage regulator. Updated standby mode description in Section 2.2.19: Low-power modes. Added Note 1 below Figure 16: STM32F40x UFBGA176 ballout. Added Note 1 below Figure 17: STM32F40x WLCSP90 ballout. Updated Table 7: STM32F40x pin and ball definitions. Added Table 8: FSMC pin definition. Removed OTG_HS_INTN alternate function in Table 7: STM32F40x pin and ball definitions and Table 9: Alternate function mapping. Removed I2S2_WS on PB6/AF5 in Table 9: Alternate function mapping. Replaced JTRST by NJTRST, removed ETH_RMII _TX_CLK, and modified I2S3ext_SD on PC11 in Table 9: Alternate function mapping. Added Table 10: STM32F40x register boundary addresses. Updated Figure 18: STM32F40x memory map. Updated VDDA and VREF+ decoupling capacitor in Figure 21: Power supply scheme. Added power dissipation maximum value for WLCSP90 in Table 14: General operating conditions. Updated VPOR/PDR in Table 19: Embedded reset and power control block characteristics. Updated notes in Table 21: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled), Table 20: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM, and Table 22: Typical and maximum current consumption in Sleep mode. Updated maximum current consumption at TA = 25 °n Table 23: Typical and maximum current consumptions in Stop mode. Table 98. Document revision history (continued) Date Revision Changes Revision history STM32F405xx, STM32F407xx 180/185 DocID022152 Rev 4 31-May-2012 3 (continued) Removed fHSE_ext typical value in Table 29: High-speed external user clock characteristics. Updated Table 31: HSE 4-26 MHz oscillator characteristics and Table 32: LSE oscillator characteristics (fLSE = 32.768 kHz). Added fPLL48_OUT maximum value in Table 35: Main PLL characteristics. Modified equation 1 and 2 in Section 5.3.11: PLL spread spectrum clock generation (SSCG) characteristics. Updated Table 38: Flash memory characteristics, Table 39: Flash memory programming, and Table 40: Flash memory programming with VPP. Updated Section : Output driving current. Table 53: I2C characteristics: Note 4 updated and applied to th(SDA) in Fast mode, and removed note 4 related to th(SDA) minimum value. Updated Table 67: ADC characteristics. Updated note concerning ADC accuracy vs. negative injection current below Table 68: ADC accuracy at fADC = 30 MHz. Added WLCSP90 thermal resistance in Table 96: Package thermal characteristics. Updated Table 90: WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data. Updated Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline and Table 94: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data. Added Figure 85: LQFP176 recommended footprint. Removed 256 and 768 Kbyte Flash memory density from Table 97: Ordering information scheme. Table 98. Document revision history (continued) Date Revision Changes DocID022152 Rev 4 181/185 STM32F405xx, STM32F407xx Revision history 04-Jun-2013 4 Modified Note 1 below Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Updated Figure 4 title. Updated Note 3 below Figure 21: Power supply scheme. Changed simplex mode into half-duplex mode in Section 2.2.25: Interintegrated sound (I2S). Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and DAC_OUT2, respectively. Updated pin 36 signal in Figure 15: STM32F40x LQFP176 pinout. Changed pin number from F8 to D4 for PA13 pin in Table 7: STM32F40x pin and ball definitions. Replaced TIM2_CH1/TIM2_ETR by TIM2_CH1_ETR for PA0 and PA5 pins in Table 9: Alternate function mapping. Changed system memory into System memory + OTP in Figure 18: STM32F40x memory map. Added Note 1 below Table 16: VCAP_1/VCAP_2 operating conditions. Updated IDDA description in Table 74: DAC characteristics. Removed PA9/PB13 connection to VBUS in Figure 86: USB controller configured as peripheral-only and used in Full speed mode and Figure 87: USB controller configured as host-only and used in full speed mode. Updated SPI throughput on front page and Section 2.2.24: Serial peripheral interface (SPI) Updated operating voltages in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts Updated note in Section 2.2.14: Power supply schemes Updated Section 2.2.15: Power supply supervisor Updated “Regulator ON” paragraph in Section 2.2.16: Voltage regulator Removed note in Section 2.2.19: Low-power modes Corrected wrong reference manual in Section 2.2.28: Ethernet MAC interface with dedicated DMA and IEEE 1588 support Updated Table 15: Limitations depending on the operating power supply range Updated Table 24: Typical and maximum current consumptions in Standby mode Updated Table 25: Typical and maximum current consumptions in VBAT mode Updated Table 36: PLLI2S (audio PLL) characteristics Updated Table 43: EMI characteristics Updated Table 48: Output voltage characteristics Updated Table 50: NRST pin characteristics Updated Table 55: SPI dynamic characteristics Updated Table 56: I2S dynamic characteristics Deleted Table 59 Updated Table 62: ULPI timing Updated Figure 47: Ethernet SMI timing diagram Table 98. Document revision history (continued) Date Revision Changes Revision history STM32F405xx, STM32F407xx 182/185 DocID022152 Rev 4 04-Jun-2013 4 (continued) Updated Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline Updated Table 94: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data Updated Figure 5: STM32F40x block diagram Updated Section 2: Description Updated footnote (3) in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts Updated Figure 3: Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package Updated Figure 4: Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages Updated Section 2.2.14: Power supply schemes Updated Section 2.2.15: Power supply supervisor Updated Section 2.2.16: Voltage regulator, including figures. Updated Table 14: General operating conditions, including footnote (2). Updated Table 15: Limitations depending on the operating power supply range, including footnote (3). Updated footnote (1) in Table 67: ADC characteristics. Updated footnote (3) in Table 68: ADC accuracy at fADC = 30 MHz. Updated footnote (1) in Table 74: DAC characteristics. Updated Figure 9: Regulator OFF. Updated Figure 7: Power supply supervisor interconnection with internal reset OFF. Added Section 2.2.17: Regulator ON/OFF and internal reset ON/OFF availability. Updated footnote (2) of Figure 21: Power supply scheme. Replaced respectively “I2S3S_WS" by "I2S3_WS”, “I2S3S_CK” by “I2S3_CK” and “FSMC_BLN1” by “FSMC_NBL1” in Table 9: Alternate function mapping. Added “EVENTOUT” as alternate function “AF15” for pin PC13, PC14, PC15, PH0, PH1, PI8 in Table 9: Alternate function mapping Replaced “DCMI_12” by “DCMI_D12” in Table 7: STM32F40x pin and ball definitions. Removed the following sentence from Section : I2C interface characteristics: ”Unless otherwise specified, the parameters given in Table 53 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 14.”. In Table 7: STM32F40x pin and ball definitions on page 45: – For pin PC13, replaced “RTC_AF1” by “RTC_OUT, RTC_TAMP1, RTC_TS” – for pin PI8, replaced “RTC_AF2” by “RTC_TAMP1, RTC_TAMP2, RTC_TS”. – for pin PB15, added RTC_REFIN in Alternate functions column. In Table 9: Alternate function mapping on page 60, for port PB15, replaced “RTC_50Hz” by “RTC_REFIN”. Table 98. Document revision history (continued) Date Revision Changes DocID022152 Rev 4 183/185 STM32F405xx, STM32F407xx Revision history 04-Jun-2013 4 (continued) Updated Figure 6: Multi-AHB matrix. Updated Figure 7: Power supply supervisor interconnection with internal reset OFF Changed 1.2 V to V12 in Section : Regulator OFF Updated LQFP176 pin 48. Updated Section 1: Introduction. Updated Section 2: Description. Updated operating voltage in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Updated Note 1. Updated Section 2.2.15: Power supply supervisor. Updated Section 2.2.16: Voltage regulator. Updated Figure 9: Regulator OFF. Updated Table 3: Regulator ON/OFF and internal reset ON/OFF availability. Updated Section 2.2.19: Low-power modes. Updated Section 2.2.20: VBAT operation. Updated Section 2.2.22: Inter-integrated circuit interface (I²C) . Updated pin 48 in Figure 15: STM32F40x LQFP176 pinout. Updated Table 6: Legend/abbreviations used in the pinout table. Updated Table 7: STM32F40x pin and ball definitions. Updated Table 14: General operating conditions. Updated Table 15: Limitations depending on the operating power supply range. Updated Section 5.3.7: Wakeup time from low-power mode. Updated Table 33: HSI oscillator characteristics. Updated Section 5.3.15: I/O current injection characteristics. Updated Table 47: I/O static characteristics. Updated Table 50: NRST pin characteristics. Updated Table 53: I2C characteristics. Updated Figure 39: I2C bus AC waveforms and measurement circuit. Updated Section 5.3.19: Communications interfaces. Updated Table 67: ADC characteristics. Added Table 70: Temperature sensor calibration values. Added Table 73: Internal reference voltage calibration values. Updated Section 5.3.25: FSMC characteristics. Updated Section 5.3.27: SD/SDIO MMC card host interface (SDIO) characteristics. Updated Table 23: Typical and maximum current consumptions in Stop mode. Updated Section : SPI interface characteristics included Table 55. Updated Section : I2S interface characteristics included Table 56. Updated Table 64: Dynamic characteristics: Ehternet MAC signals for SMI. Updated Table 66: Dynamic characteristics: Ethernet MAC signals for MII. Table 98. Document revision history (continued) Date Revision Changes Revision history STM32F405xx, STM32F407xx 184/185 DocID022152 Rev 4 04-Jun-2013 4 (continued) Updated Table 64: Dynamic characteristics: Ehternet MAC signals for SMI. Updated Table 66: Dynamic characteristics: Ethernet MAC signals for MII. Updated Table 79: Synchronous multiplexed NOR/PSRAM read timings. Updated Table 80: Synchronous multiplexed PSRAM write timings. Updated Table 81: Synchronous non-multiplexed NOR/PSRAM read timings. Updated Table 82: Synchronous non-multiplexed PSRAM write timings. Updated Section 5.3.26: Camera interface (DCMI) timing specifications including Table 87: DCMI characteristics and addition of Figure 73: DCMI timing diagram. Updated Section 5.3.27: SD/SDIO MMC card host interface (SDIO) characteristics including Table 88. Updated Chapter Figure 9. Table 98. Document revision history (continued) Date Revision Changes DocID022152 Rev 4 185/185 STM32F405xx, STM32F407xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland SIXTY User Guide LU Sixty.book Page 1 Mardi, 26. octobre 2010 2:22 14 1Couv.fm Page 1 Dimanche, 16. mai 2010 3:20 15 3 Dear customer, You have just acquired a new generation Sagemcom telephone and thank you for placing your confidence in us. This device has been manufactured with the utmost care. If you should have difficulties in operating it, we recommend that you consult this user manual. You can also find information on the following site: http://www.sagemcom.com/sixty To operate the device safely and easily, please read carefully the paragraph “Recommendations and safety instructions”, page 6. The CE label confirms that the product complies with the 1999/5/EC regulations of the European Union Parliament regarding wireless systems and telecommunications. The declaration of compliance may be looked up on the www.sagemcom.com website, or can be obtained from the following address : Sagemcom Broadband SAS 250, route de l'Empereur - 92848 Rueil-Malmaison Cedex - France Copyright © Sagemcom Broadband SAS All rights reserved Sagemcom is a registered trademark LU Sixty.book Page 3 Mercredi, 19. mai 2010 12:30 12 4 Contents Recommendations and safety instructions .....................6 Unpacking .......................................................................8 Phone description ...........................................................8 Your base................................................................... 8 Your handset.............................................................. 9 Control panel............................................................ 10 Phone installation ............................................ 12 Connecting the base .....................................................12 Setting up the handset ..................................................12 Charging batteries .........................................................12 Settings required before use .........................................13 Navigating in the menu .................................................13 Menu structure ......................................................... 14 Browsing through the menus ................................... 14 Phone use......................................................... 15 Handset location ...........................................................15 Telephoning ..................................................................15 Receiving a call ........................................................ 15 Making a call ............................................................ 16 Ending a call............................................................. 16 During a call ............................................................. 16 Call key function....................................................... 17 Secret mode............................................................. 17 Hands-free/speakerphone mode.............................. 17 Calling the last number dialled ................................. 18 Call time display ....................................................... 18 Phonebook ....................................................... 18 Creating an entry ...........................................................18 Editing an entry .............................................................19 Associating a ring tone with a phonebook entry ............19 Other number ................................................................19 Deleting an entry ...........................................................19 Calling using the phonebook .........................................20 Searching for a contact .................................................20 Call log.............................................................. 20 Viewing the received and dialled call log ...................... 20 The events log .............................................................. 21 Viewing the events log............................................. 21 Activating/deactivating the new event information screen............................ 21 Clearing notifications ............................................... 21 Information .................................................................... 21 Accessories...................................................... 22 Alarm clock ................................................................... 22 Activating / deactivating the alarm clock.................. 22 Changing the alarm clock ring tone ......................... 22 Modifying the alarm clock time ................................ 22 Timer ............................................................................ 22 Activate the timer..................................................... 22 Changing the programmed time of the timer ........... 23 Displaying or hiding the programmed time of the timer............................................................... 23 Changing the timer ring tone ................................... 23 Ring tones ........................................................ 23 Changing the ring tones ............................................... 23 Activating or deactivating the beeps ............................. 23 Activating/deactivating the silent mode ........................ 24 Settings............................................................. 24 Modifying the date and time ......................................... 24 Adjusting the contrast ................................................... 24 Modifying the language ................................................ 24 the voice box number (according to operator) .............. 25 Defining forbidden prefixes - Call barring ..................... 25 Demo ............................................................................ 26 Advanced settings ........................................................ 26 Base settings ........................................................... 26 Line settings ............................................................ 27 Modifying the base code.......................................... 29 LU Sixty.book Page 4 Mercredi, 19. mai 2010 12:30 12 5 Answering machine......................................... 29 Enabling / disabling the answering machine .................29 Modifying the OGM .......................................................30 Recording a personal outgoing message ................ 30 Deleting your personal OGM ................................... 30 Listen to a personal message .................................. 30 Playing messages .........................................................30 Remote access to answering machine .........................31 Deleting all the old messages .......................................31 TAM settings .................................................... 32 Activating and deactivating call screening ....................32 Modifying the remote access code ...............................32 Number of rings ............................................................32 Replacing the batteries................................... 33 Pairing GAP-compatible DECT handsets on the SIXTY base ........................................... 33 Appendix .......................................................... 34 Care and Maintenance ..................................................34 Problems .......................................................................34 Technical characteristics................................ 35 Initial condition .............................................................35 Environment..................................................... 36 Packaging .....................................................................36 Batteries and rechargeable batteries ............................36 The product ...................................................................36 Guarantee......................................................... 37 Terms and Conditions for United Kingdom & Ireland only ................................................................37 Terms and Conditions for other countries .....................39 LU SixtyTDM.fm Page 5 Jeudi, 20. mai 2010 9:03 09 6 RECOMMENDATIONS AND SAFETY INSTRUCTIONS Do not install your DECT telephone in a damp environment, such as a bathroom, washroom, kitchen etc, and not within 1.50 metres of a source of water or outside. This device is designed for use in temperatures of between 5 °C and 45 °C. Do not attempt to remove screws or open the appliance. It does not contain any user-replaceable parts. Only use the power unit supplied and connect it to the electricity mains in accordance with the installation instructions in this user manual and the details on the sticker regarding voltage, electrical current and frequency. As a precaution if there is a risk of danger, the power plug can be pulled out to disconnect the 230 volt power supply. Therefore the sockets should be near the device and easily accessible. This device is designed to be used for connecting to the public telephone network. If problems should arise, contact your nearest specialist dealer. Only use the telephone cable supplied. For safety reasons, never put the handset in the base station without the battery inserted or without the lid on the battery compartment as this could cause an electric shock. To avoid damaging your handset/base, only use certified rechargeable batteries NiMH 1.2 V 450 mAh, never use non rechargeable batteries. Insert the batteries in the handset/base battery compartment respecting polarity. The used battery must be disposed of in line with the recycling regulations in this user manual. Your DECT telephone has a range of approx. 50 metres indoors and up to 300 metres outdoors. The range can be affected by the proximity of metal objects, such as a television and electrical devices. Zones without reception may appear owing to elements in the building. This can cause brief interruptions in the conversation, caused by faulty transmission. LU Sixty.book Page 6 Mercredi, 19. mai 2010 12:30 12 7 Certain medical equipment and highly-sensitive machines or security systems may be affected by the transmission power of the telephone. In these cases we recommend adhering to the safety information. In regions greatly affected by electrical storms we recommend that you protect your telephone circuit with a special fixture for excess voltage. Your SIXTY has anti-skid pads that should leave no traces on your furniture and ensure stability. However, given the the wide variety of finishes used by furniture manufacturers, traces may appear on surfaces in contact with the parts of your SIXTY. Sagemcom Broadband SAS decline all responsibility in any such cases of damage. LU Sixty.book Page 7 Mercredi, 19. mai 2010 12:30 12 8 UNPACKING Place the box in front of you, open it and make sure it contains the following items: • one base SIXTY, one handset, one telephone line cord, one equipped power adapter and this user guide. PHONE DESCRIPTION Your base The SIXTY is the contemporary interpretation by SAGEMCOM of the S63, which accompanied the development of telephone communications in many countries in the 60s and 70s. It nevertheless has the latest technology, such as browser touch buttons, Hifi ringtones, dialling light and sound effects. * Keyway: indicates the position of the handset earpiece ** Press and hold the key : - If the answering machine is turned off: access to voice messaging service. - If the answering machine is turned on: access to your messages on the answering machine. Base button/Paging - Short press: find handsets (Paging) - Press and hold : handset registration Keyway * Loudspeaker/ Pick up Indicator light Access to voice messaging service/ Access to your messages on the answering machine ** LU Sixty.book Page 8 Mercredi, 19. mai 2010 12:30 12 9 Your handset SIXTY's particularity is that it has a wireless handset. The single button on the handset allows the user to hang up or answer an incoming call. It should be noted that the handset is provided with a buzzer that sounds on receiving an incoming call with the handset not on its base. The handset batteries are charged when the handset is placed on its base. When off the base, the handset's battery power provides 120 hours of standby time and 10 hours of talk time. Indicator light operation: • Fast flashing: handset registration or paging. • Slow flashing: handset on line or new events. Make sure that when the handset is on the charger, the icon is animated. Hang up/ Pick up Battery compartment Battery cover Handset charging contacts Speaker Microphone + - LU Sixty.book Page 9 Mercredi, 19. mai 2010 12:30 12 10 Control panel Your SIXTY has a touch keys for access to configuration and settings functions. The screen tells you about the state (date and time, unread message, etc..). Using the touch buttons The screen includes six touch keys around its periphery. Simply touch the tactile area for the function to be taken into account: Key Function(s) Key Function(s) Scroll up /Go to the menu list. Browse down / Go to the menu list. Context key 1: Access a menu / Validate the selection. Context key 2: Delete an entry / Return to the previous menu. Asterisk key. # key. LU Sixty.book Page 10 Mercredi, 19. mai 2010 12:30 12 11 Display screen During use or on standby, the screen of your SIXTY tells you about the state of your telephone by showing icons, and in particular: * The low emission icon (ECO mode): Your telephone is provided with an automatic power management system. As soon as the handset is near its base, the power required is reduced to the minimum. Radio transmissions are also cut off when the handset is placed on the base, and the low emission icon is then displayed. If a second handset is paired with the base, the "low emission" icon is no longer displayed. Battery indicator Microphone off Current call Speakerphone on Recording answering machine on Alarm on New voice message Low emission icon* LU Sixty.book Page 11 Mercredi, 19. mai 2010 12:30 12 12 PHONE INSTALLATION CONNECTING THE BASE Never force the plugs: they are in different shapes to avoid connection mistakes. 1. On the underside of the base, click the phone jack into its socket and connect the other end of the cord to the telephone wall outlet. 2. Connect the end of the power supply cord on the underside of the base and connect the power adapter to the mains socket. The phone display is turned on. SETTING UP THE HANDSET The batteries are already inserted in the handset. To put the handset into use, simply remove the tab by pulling on it firmly in the direction of the arrow. The handset emits a double beep to indicate that it has started and then a second beep to indicate that the handset is synchronized with the base. From then on, your handset becomes operative and you can use it to make calls. You can now use your telephone to make and receive calls. CHARGING BATTERIES Place the handset on its base and fully charge the batteries. An audio signal is emitted and a light flashes when the handset is placed correctly on the base. The battery charge icon is animated to indicate that the battery is being charged and stops to indicate that the batteries are fully charged. Before making any connections, please refer to the safety instructions presented at the beginning of this user guide. Power socket Telephone socket On leaving the factory, the handset is already registered in the base. If your handset is not recognized by the base, then launch a manual registration (See paragraph "Set the base to registration mode", page 26. LU Sixty.book Page 12 Mercredi, 19. mai 2010 12:30 12 13 SETTINGS REQUIRED BEFORE USE Setting the date and time accurately will enable you to Follow your calls and messages chronologically. According to where your base is situated in the room, You may have to adjust the contrast. To set the date and time, refer to paragraph "Modifying the date and time ", page 24. To set the contrast or the brightness of the screen, refer to paragraph "Adjusting the contrast ", page 24. NAVIGATING IN THE MENU With your SIXTY you can create your own telephone directory, display the list of calls etc. To do this, use the touch keys. With the touch keys 􀀘 and 􀀙 you can choose a menu, a sub-menu or a precise setting. The key allows you to enter the sub-menus of the chosen function and select the setting to modify. With the key you can return to the previous function or cancel the current choice. The keys and are used when you use the answerphone. See the menu structure to familiarise yourself with what your phone can do. The handset batteries charging time is 10 hours. During charging, the batteries may heat up. This is quite normal and perfectly safe. Handset charging contacts Base charging contacts LU Sixty.book Page 13 Mercredi, 19. mai 2010 12:30 12 14 Menu structure To access one of your phone's menus, use key 􀀘 or 􀀙. Browsing through the menus Use the browsing keys 􀀘 or 􀀙 to select the desired menu. Press Valid. To confirm your selection. Select the desired function by pressing the browsing keys 􀀘 or 􀀙 and then press the Valid. key. - To return to the previous menu, press Return. - To save the settings, press Valid.. Example: To access the menu SETTINGS /DATE/TIME: 1. Use 􀀘 or 􀀙 to access the menu list. 2. Select SETTINGS using 􀀘 or 􀀙. Press Valid.. 3. Select DATE/TIME using 􀀘 or 􀀙. Press Valid. You are now under the DATE/TIME menu.P Menu PHONEBOOK ACCESSORIES CALLS CALL INCOMING CALLS OUTGOING CALLS EVENTS ALARM TIMER EXTERNAL CALL SILENT MODE RING TONE SETTINGS Option VIEW RING TONE DELETE ADD NUMBER NEW ENTRY BEEPS DATE/TIME CONTRAST DEMO ANS.MACH MESSAGES ON/ OFF OUTGOING MESS. SETTINGS LANGUAGE Edit RESTRICTION ADVANCED SET. VOICE BOX No DATE/TIME LU Sixty.book Page 14 Mercredi, 19. mai 2010 12:30 12 15 PHONE USE HANDSET LOCATION Lost your handset? Press the button on the back of the base, behind the keypad. The handset will then ring. TELEPHONING Receiving a call • When a call is received, the phone rings. • The caller's phone number is displayed on the screen if you have subscribed to the "Caller ID" service. The caller's name may also be displayed if it is included in your phone book. Accepting a call in handset mode • Pick up the phone handset. You do not need to press the handset's button. • Make sure to identify the handset direction by the dot which identifies the earpiece end. The call time counter is displayed on the screen. • To end the call, hang up the handset or press the handset button. • A visual and audible signal confirms that the handset is hung up correctly. • If the handset is not on the base, you have to press the handset button to take the call. Accepting a call in speakerphone mode • Press to speak in speakerphone mode (without holding the handset). The symbol and the call time counter are displayed on the screen. • To end the call, press again. Toggle between handset mode and speakerphone mode • If you are in handset mode, press and hold the key and then hang up the handset to toggle to speakerphone mode. Press the key again to end the call. • If you are in speakerphone mode: - If the handset is hung up on the base, lift the phone handset to toggle to handset mode. - If the handset is not hung up on the base, press the dial tone button to toggle to handset mode. • To end the call, hang up the handset on the base or press . Use the 􀀘 and 􀀙 keys to vary the earphone volume or speakerphone volume. The handset earphone volume or speakerphone volume can vary from 1 to 5. LU Sixty.book Page 15 Mercredi, 19. mai 2010 12:30 12 16 Making a call The call can be made in two ways: Making a call in handset mode • Pick up the handset. • The icon is displayed on the screen. Dial your number on the keypad. The call time counter is displayed on the screen. Making a call in speakerphone mode • Press to obtain a dial tone prompt on the screen. Dial your number on the keypad. The and icons are displayed on the screen. The call time counter is displayed on the screen. Ending a call When you have finished your call, press or hang up the handset on the base. During a call Receiving a second call • During the call, a beep is transmitted to your telephone by your service provider to let you know that you have a second call waiting. • Press ACCEPT to take this new call. • Your other caller is then put on hold and you can talk with your second caller. Making a second call • During a call, you can put your contact on hold and call a second one by pressing -R- and dial the number using the keypad. • The second call is then launched, with the first call still on hold. To alternate from one call to the other • To toggle from one call to the other, press Menu then SWITCH. • The call in progress is put on hold, and you can then take the second call. To end one of the calls and continue the other one • To toggle from one call and take the other, press Menu and then HANGING UP. • The call in progress is definitely terminated, and you can then take the second call. You can also dial a number in pre-dialling mode, whether in handset or speakerphone mode: dial the number on the keypad and then lift the handset or press . If necessary, you can correct the number entered by pressing BACK. The caller on hold hears a beep emitted by the network. LU Sixty.book Page 16 Mercredi, 19. mai 2010 12:30 12 17 To set up a 3 way-call (the two parties and yourself) • During a call, press Menu and then 3-PARTY CONF. • You can then talk to both parties simultaneously, and "3-PARTY CONF" is displayed on the screen. • To end the 3 way-call, Hang up the handset. Call key function This key is a shortcut to your phone's call log. • From the idle screen, press the key : - INCOMING CALLS, - OUTGOING CALLS, - EVENTS. • Press keys 􀀘 or 􀀙 to select the calls list. • Press Valid. and then select the number using keys 􀀘 or 􀀙. Secret mode During a call, you can switch to mute mode and your phone's microphone will be muted. The person you are on line with can no longer hear you. To activate secret mode : • During a call, press Menu/ SECRET and then Activ.. • The "SECRET MODE" message will appear on the screen. To deactivate secret mode : • Press Exit, "SECRET MODE" disappears from the screen. Your correspondent will be able to hear you again. Hands-free/speakerphone mode If you want to phone in speakerphone mode, do not lift the handset, but press the base key; the icon is displayed on your phone's screen. The caller can then be heard through the loudspeaker and you speak into the base microphone. To end the call, press the key again . If you want to toggle to speakerphone mode during a call in handset mode, press the key; the icon is displayed on your phone's screen. The caller can then be heard through the base loudspeaker and the handset earphone and you speak into the handset microphone. In this mode the base microphone is inactive. You can return to speakerphone mode by holding down the key and then replacing the handset. To end the call, replace the handset or press the key . When you call hand-free/speakerphone mode, you can increase or decrease the audio volume from 1 to 5, using 􀀘 or 􀀙. LU Sixty.book Page 17 Mercredi, 19. mai 2010 12:30 12 18 Calling the last number dialled Your SIXTY stores the last 20 dialled numbers: • Go to CALLS / OUTGOING CALLS. • Select the number you want to call. • Go to Option / CALL. The number is automatically dialed in speakerphone mode. Call time display Once connected, the call time is displayed on the screen (minutes and seconds). PHONEBOOK You can save up to 150 entries in your phone book, with each sheet able to contain a 24-digit number and a name up to 12 letters long. CREATING AN ENTRY To enter a text, repeatedly press the required key to display the desired letter. • Go to PHONEBOOK / New. • Enter the name of your contact using the alphanumeric keys. • Press Valid.. • Enter the contact`s telephone number using the alphanumeric keys. • PressValid.. • Select an icon for this number to specify the type of number. • Press Valid.. The name and number are then stored in your phone book. LU Sixty.book Page 18 Mercredi, 19. mai 2010 12:30 12 19 EDITING AN ENTRY • Go to the menu PHONEBOOK. • Press keys 􀀘 or 􀀙 to select the contact you want to change. • Select Option / Edit. • Press Valid.. • You enter the name input screen. To correct the name, press Return to delete characters. Enter your changes on the keypad. After making the changes, press Valid.. • You enter the number input screen. To correct the number, press Return to delete the numbers. Enter your changes on the keypad. After making the changes, press Valid.. • Select an icon for this number. • Press Valid.. ASSOCIATING A RING TONE WITH A PHONEBOOK ENTRY You can associate a unique ring tone to each entry and thus create your own call groups As you need the active number presentation service on your handset, contact your operator to find out about the conditions for obtaining the service. • Go to the menu PHONEBOOK. • Select the entry with which you want to associate a ring tone. • Go to Option / RING TONE. • Select the ring tone of your choice. • Press Valid.. OTHER NUMBER This function allows you to assign new numbers to the same name. • Go to the menu PHONEBOOK. • Select the entry you want to assign another number to. • Go to Option / ADD NUMBER. • Enter the phone number on the alphanumeric keys. • PressValid.. • Select an icon according to the type of number entered. Press Valid.. DELETING AN ENTRY • Go to the menu PHONEBOOK. • Press keys 􀀘 or 􀀙 to select the contact you want to delete. • Select Option / DELETE. • Press Valid.. • A confirmation screen asks you if you wish to delete the entry. - To delete the entry, press Yes, the contact is deleted from your phone book. - If you do not wish to delete the entry, press No. LU Sixty.book Page 19 Mercredi, 19. mai 2010 12:30 12 20 CALLING USING THE PHONEBOOK • Go to the menu PHONEBOOK. • From the list of names, select the contact you want to call using keys 􀀘 or 􀀙. • Go to Option/CALL. The number is automatically dialled in speakerphone mode. SEARCHING FOR A CONTACT • Access your phonebook list, press successively on the keypad key which corresponds to the first letter of the name you are searching for so as to make it appear at the top of the screen. • Once the first letter of the name is displayed, wait a moment. • The phonebook selects the first name in the list that starts with the selected letter. CALL LOG Caller identification is a service that requires prior registration with your operator. VIEWING THE RECEIVED AND DIALLED CALL LOG • Go to the menu CALLS / INCOMING CALLS or OUTGOING CALLS. • Select the event to be viewed. • Press Valid.. • The screen presents the following information. (depending on the operator and the subscription): - the full name of your contact and the telephone number, - the number of consecutive calls, - time (for calls during the day) or the date (for previous calls) of the call. The calls are organised in chronological order, from the most recent call to the oldest call. To see the previous calls, use the keys 􀀘 or 􀀙. To check your call log directly, press the Log key from the idle screen. LU Sixty.book Page 20 Mercredi, 19. mai 2010 12:30 12 21 By pressing Option, a list of various executable actions appears: - CALL : To call the number. - VIEW : To view the selected call again. - STORE NUMBER : To store the name and number in the phonebook. - DELETE : To delete the call currently viewed. - DELETE ALL : To delete all calls. To return to the call viewing screen, press Return. THE EVENTS LOG Viewing the events log If one or more new events occurred during your absence, the information screen "NEW EVENTS !" appears and the light starts flashing. • If you do not wish to view the event log at this time, press Return. • To view the event log, press Valid.. • Choose the event using 􀀘 or 􀀙. • Press Valid.. Activating/deactivating the new event information screen The new event information screen can be inhibited. The events which have occurred can then be viewed in the menu CALLS / EVENTS / VIEW. The default setting is active. • Go to the menu CALLS / EVENTS. • Select ACTIVATE or DEACTIVATE to enable or disable the displaying of the new events screen. • Press Valid.. Clearing notifications The notifications received are saved in the event log and can be deleted once they have been viewed. • Go to the menu CALLS / EVENTS. • Select DELETE NOTIF. and press Valid. to remove the notifications received on your base. INFORMATION During an incoming call, following messages can be displayed: PRIVATE: Your contact does not want their number to be displayed. UNAVAILABLE: If there is a problem on the phone network. The light only stops flashing when all the events have been viewed. LU Sixty.book Page 21 Mercredi, 19. mai 2010 12:30 12 22 ACCESSORIES ALARM CLOCK This function enable you to use your SIXTY as an alarm clock. When the alarm is triggered the selected ring tone sounds for 60 seconds through the handset speaker and an alert screen is displayed. Activating / deactivating the alarm clock • Go to ACCESSORIES / ALARM. • An information screen shows the alarm clock status. • Use􀀘 or 􀀙 to select ACTIVATE or DEACTIVATE. • Press Valid.. The alarm settings information screen appears showing the new status. Changing the alarm clock ring tone • Go to ACCESSORIES / ALARM. • Use􀀘 or 􀀙 to select RING TONE in the list, press Valid.. • Select the ring tone of your choice, press Volume. • Select the desired ring tone using 􀀘 or 􀀙 to increase or decrease the volume, press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. Modifying the alarm clock time • Go to ACCESSORIES / ALARM. • Use􀀘 or 􀀙 to select SET TIME. • Enter the time at which you would like the alarm clock to sound. • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. TIMER With this menu you can use your telephone as a timer. Once the specified time has elapsed, the base rings for 60 seconds and the alarm screen is activated. Turn off the alarm by pressing Stop, the base stops ringing. Activate the timer • Go to ACCESSORIES / TIMER. • Press Start. If a timer duration is already specified, the timer is directly activated. If not please follow instructions in the next paragraph. The timer function must be inactive so that it can be set. LU Sixty.book Page 22 Mercredi, 19. mai 2010 12:30 12 23 Changing the programmed time of the timer • Go to ACCESSORIES / TIMER. • Press Valid.. • Select SET DURATION in the list. Press Valid.. • Enter the desired time. • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. Displaying or hiding the programmed time of the timer • Go to ACCESSORIES / TIMER. • Select VIEW in the list. Press Valid.. • If you want to show the timer, press Yes, else press No. • Press Return. Changing the timer ring tone • Go to ACCESSORIES / TIMER. • Select RING TONE in the list of options, press Valid.. • The list of ring tones appears, the handset plays the ring tone. • Select the ring tone. Press Volume. • Press 􀀘 or 􀀙 to increase or decrease the volume. • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. RING TONES CHANGING THE RING TONES This menu enables you to associate a unique ring tone to incoming calls. • Go to RING TONE / EXTERNAL CALL. • Press Valid.. • Select the ring tone of your choice. • then press Volume. Adjust the ringer volume using 􀀘 or 􀀙. • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. ACTIVATING OR DEACTIVATING THE BEEPS • Go to RING TONE / BEEPS. • Press Valid.. • To change the beep status, press Edit. The status is changed on the screen. • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. LU Sixty.book Page 23 Mercredi, 19. mai 2010 12:30 12 24 ACTIVATING/DEACTIVATING THE SILENT MODE When in silent mode, the telephone ringer and keypad beeps are inhibited. • Go to RING TONE / SILENT MODE. • SILENCE MODE? is displayed on the screen. • Press Yes to activate the silent mode. SETTINGS MODIFYING THE DATE AND TIME • Go to SETTINGS / DATE/TIME. • Enter the date in DD/MM/YY format. • Press Valid.. • Enter the time in HH/ MM format. • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. ADJUSTING THE CONTRAST • Go to SETTINGS / CONTRAST. • A list with five levels of contrast is displayed. • Select the level you want using the keys 􀀘 or 􀀙. The contrast is directly visible on the screen. • when you have obtained a satisfactory level. • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. MODIFYING THE LANGUAGE • Go to SETTINGS / LANGUAGE. • An information screen presents the current language used. - To keep the setting, press Valid.. - To change the setting, press 􀀘 or 􀀙. • Select the language. When you activate the silent mode, your handset is muted for all timer and alarm type functions. LU Sixty.book Page 24 Mercredi, 19. mai 2010 12:30 12 25 • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. THE VOICE BOX NUMBER (ACCORDING TO OPERATOR) This function allows you to receive calls in your absence on your operator's voice messaging service. To indicate that a new message has been received the reception indicator on the the top of the '1' key is lit in red and the new event message is displayed on the screen. To change the voice box number, proceed as follows: • Go to SETTINGS / VOICE BOX No. • The programmed number is displayed on the screen. - The number is correct, press Valid.. - To modify the number, press Edit. DEFINING FORBIDDEN PREFIXES - CALL BARRING You can prohibit the use of certain prefixes on your telephone. When a prefix is forbidden, it becomes impossible to call numbers that begin by this prefix. • Go to SETTINGS/ RESTRICTION. • Press Edit, • Select PREFIX using 􀀘 or 􀀙, press Valid.. • Enter the base code (by default 0000), press Valid.. • Select a location (dashes), press Valid.. • Enter the prefix using the keypad (for example : 06, 08, etc..). • Press Valid.. • OK is displayed on the screen. • Select ACTIVATE using 􀀘 or 􀀙. • Enter the base code (by default 0000), press Valid.. • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. The answering machine message language depends on the phone language. To check your voice messaging service, hold down key . LU Sixty.book Page 25 Mercredi, 19. mai 2010 12:30 12 26 DEMO This menu allows you to see an animation for each of your phone's key and ring tones. • Go to SETTINGS / DEMO. • Press Valid.. • Display of "DEMO Chenillard" with the animation of each key. • Press the key during this animation, "DEMO MELODY" is displayed, and the melody for external calls is initiated. • Press Exit to stop the demonstration. ADVANCED SETTINGS Base settings Set the base to registration mode Using this function you can add GAP compatible hnadsets to your base. The handset that you want to pair with your base must itself be in pair mode. Consult the user booklet of your handset to find out what to do. • Go to SETTINGS / ADVANCED SET. / SET BASE / REGISTR. MODE. • Press Valid.. • REGISTR. MODE? is displayed on the screen, press Yes. • Indicator on the the top of the '1' key starts to flash rapidly. Your base will remain in registration mode for about 1 minute. Resetting the base When you reset your base, all the base parameters are reset to their initial values (factory settings). • Go to SETTINGS / ADVANCED SET. / SET BASE / RESET BASE. • Press Valid.. • REINIT. BASE? is displayed on the screen. • Press Yes. • Enter the base code. • Press Valid.. The "RE-INIT. IN PROCESS" and the OK messages are displayed successively. Your base is now reset. You can save up to 5 GAP-compatible handsets on your SIXTY base. You can also set the base to pairing mode by holding down your base's key. LU Sixty.book Page 26 Mercredi, 19. mai 2010 12:30 12 27 De-registering a handset • Go to SETTINGS / ADVANCED SET. / SET BASE / DELETE HANDSET. • Press Valid.. • Select the handset you wish to unregister using 􀀘 or 􀀙. • Press Valid.. • A screen prompts you to confirm the unregistration. Press Yes to unregister the handset. The handset is no more registered to the base. Line settings Modifying the network type Your telephone can be installed on a public or private network (when using a PABX). This function enables you to configure your telephone according to the type of network. • Go to SETTINGS / ADVANCED SET. / SET LINE / NETWORK TYPE. • Press Valid.. • A screen presents the current status. - To keep the status, press Valid.. - To change the status, press Edit. • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. Modifying the dialling mode The type of dialling generally used is voice frequency. It is possible that the exchange to which you are connected uses pulse dialling. • Go to SETTINGS / ADVANCED SET. / SET LINE / DIAL. • Press Valid.. • A screen displays the current status. - To keep the status, press Valid.. - To modify the status, press Edit. The status is modified on the screen. • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. Before changing the settings of the telephone line, contact your operator to obtain the parameters for your line. The default dialling mode is tone. LU Sixty.book Page 27 Mercredi, 19. mai 2010 12:30 12 28 Modifying the flash duration If you connect your telephone to a private automatic branch exchange or use it in a foreign country, you may need to modify the flash duration in order to use your telephone correctly with regard to the following functionalities: outgoing 2nd call, incoming 2nd call, 3 way calling. Contact your service provider to obtain the correct flash duration and then modify it by doing the following. • Go to SETTINGS / ADVANCED SET. / SET LINE / FLASHING. • Press Valid.. • An information screen presents the current flash duration. - To keep the duration, press Valid.. - To modify the duration, press Edit. • Select the new duration. • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. Setting a PABX prefix If a private automatic branch exchange is used, you can programme the external call prefix. With this function you can set the: - PABX prefix number, - dialled number length at which point the PABX prefix will be automatically inserted (this length is called “digit before prefix”), - prefix status (on or off). • Go to SETTINGS / ADVANCED SET. / SET LINE / PABX PREFIX. • Press Valid.. • Press to modify this setting. • Select the desired option: - ACTIVATE / DEACTIVATE : to select a status. - PREFIX : to enter the number giving you access to the outside line. - EDIT LENGTH : to specify the «digits before prefix». • To modify the prefix, select PREFIX press Valid.. • Enter the prefix using the keypad, press Valid.. OK is displayed on the screen. • To modify the digits before prefix, select EDIT LENGTH, press Valid.. • Enter the digits before prefix using the keypad. • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. • Now you can activate the automatic PABX prefix functionality, select ACTIVATE and press Valid.. LU Sixty.book Page 28 Mercredi, 19. mai 2010 12:30 12 29 Modifying the base code This code securises and limits the use of your telephone. • Go to SETTINGS / ADVANCED SET. / CHANGE CODE. • Press Valid.. • Enter the old base code using the keypad (default is 0000). • Press Valid.. • Enter the new base code using the keypad. • Press Valid.. • Confirm by entering the new base code again. • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. ANSWERING MACHINE Your phone's answering machine provides the following features: • Active answering machine mode with pre-recorded messages, • Call filtering, • Remote querying. ENABLING / DISABLING THE ANSWERING MACHINE • Go to ANS. MACH / ON/OFF. • Press Valid.. • A screen displays the current status of the answering machine (On or Off). - To keep the displayed status, press Valid.. - To change the status, press 􀀘 or 􀀙: To activate the answering machine, select ACTIVATE. To turn off the answering machine, select OFF. Press Valid.. • OK is displayed on the screen. • Press Return to go back to the previous menu. If you have not recorded a personal message, the answering machine will automatically use one of the pre-recorded messages in the selected language. LU Sixty.book Page 29 Mercredi, 19. mai 2010 12:30 12 30 MODIFYING THE OGM Recording a personal outgoing message • Go to ANS. MACH / OUTGOING MESS. / CHANGE. • Press Valid.. • RECORD OGM is displayed on the screen. • Press Begin to start recording your OGM. Start talking in the base microphone. • To stop recording press End. Your outgoing message is automatically played back. • Press Return to go back to the previous menu or make a new recording. Deleting your personal OGM • Go to ANS. MACH / OUTGOING MESS. / DELETE. • Press Valid.. • DELETE ANOUNCE? is displayed on the screen, press Yes to confirm the deletion of your personal outgoing message. • OGM DELETED is displayed on the screen. • Press Return to go back to the previous menu. Listen to a personal message • Go to ANS. MACH / OUTGOING MESS. / PLAY. • Press Valid.. • PLAY OGM is displayed on the screen and the OGM is played back. At the end of the playback you will return to the menu RECORD OGM. • Press Return to go back to the previous menu. PLAYING MESSAGES If you have new messages (unread), these messages are read first. Afterwards, the messages that have already been taken are played back in chronological order (from the oldest messages to the most recent messages). • Go to ANS. MACH / MESSAGES / PLAY. • Press Valid.. • The messages are played through the loudspeaker. In order to modify an OGM, you must first turn on the answering machine. If you delete your personal outgoing message, the answering machine will automatically use the anonymous message. If you have not recorded a personal message, you will hear the anonymous, pre-recorded message. LU Sixty.book Page 30 Mercredi, 19. mai 2010 12:30 12 31 • Depending on your service provider and your subscription, the name and number of your contact will be displayed on the screen (except for a confidential call). • During playback, you can use the touch-sensitive keys to perform the following actions: - * : go back to the beginning of the message. - * x 2: return to the previous message. - # : go to the next message. - Pause/PLAY (context key 1): pause/resume playback. - DELETE (context key 2): delete the message being played. - : exit playback of messages. REMOTE ACCESS TO ANSWERING MACHINE Your answering machine can be queried remotely. This feature allows you to read your messages and query your answering from any phone when you are not at home. To remotely access your answering machine: • Dial your telephone number. • Wait for the answering machine to come on. • When your outgoing message is played, press «#». • Enter your remote access code. • A beep will indicate access to the answer machine, Any unread messages will be automatically played back. • At the end of playback, a new beep will sound to let you know that the answer machine is ready. • You can carry out the following operations : - 0 : delete the message being played. - 1 : go back to the beginning of the message. - 1 (x2): previous message. - 2 : pause / play. - 3 : next message. - 5 : messages read. - 9 : enable/disable the answering machine. DELETING ALL THE OLD MESSAGES • Go to ANS. MACH / MESSAGES / DELETE OLD. • Press Valid.. • To confirm the deletion of all the old messages, press Yes. • Press Return to go back to the previous menu. The remote access code is 0000 by default. However, it can only be used once it is customised, refer to paragraph "Modifying the remote access code ", page 32. To delete old messages one by one, refer to the previous paragraph and delete unwanted messages during playback. LU Sixty.book Page 31 Mercredi, 19. mai 2010 12:30 12 32 TAM SETTINGS This menu allows you to change the advanced settings of your answering machine. You can access the answering machine SETTINGS menu from the ANS. MACH menu. ACTIVATING AND DEACTIVATING CALL SCREENING The filtering function, when activated, allows you to listen to the message left by the caller as it is being recorded. You can unhook to answer at any time. • Go to ANS. MACH/SETTINGS/CALL SCREENING. • Press Valid.. • A screen indicating the function status appears. - To keep the current status, press Valid.. - To change the status, press 􀀘 or 􀀙. • Press Valid.. MODIFYING THE REMOTE ACCESS CODE The remote access code enables you to listen to the messages left on your answering machine via another telephone. • Go to ANS. MACH / SETTINGS / REMOTE CODE. • Press Valid.. • CODE BASE is displayed, enter your Base code (default setting is 0000). • Press Valid.. • CODE DISTANCE is displayed, enter the new remote access code (4 digits mandatory). • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. NUMBER OF RINGS This parameter determines the number of times your phone rings before your answering machine is started. The number of rings is between 3 and 7. • Go to ANS. MACH / SETTINGS / NO OF RINGS. • Press Valid.. • The programmed number of rings is displayed on the screen. Press keys 􀀘 or 􀀙 to change this number (from 3 to 7). • Press Valid.. OK is displayed on the screen. • Press Return to go back to the previous menu. LU Sixty.book Page 32 Mercredi, 19. mai 2010 12:30 12 33 REPLACING THE BATTERIES Your batteries' autonomy is no more satisfactory ? Please contact your retailer, he will propose to you new equivalent batteries. • Remove the battery compartment hatch. • Remove the old batteries, insert the new batteries one by one in compliance with the polarity of the batteries, as indicated in paragraph “Your handset”, page 9 • Refit the battery compartment hatch. • Leave your handset on its base in order to fully charge the batteries. PAIRING GAP-COMPATIBLE DECT HANDSETS ON THE SIXTY BASE Additional GAP-compatible DECT handsets can be registered on the SIXTY base. To register an additional handset on the SIXTY base: • Set your base to pairing mode by holding down the key. The light indicator on the top of the '1' key starts flashing. The base remains in pairing mode for one minute. • Set the additional handset to registration mode. (Refer to the your handset's user manual). Up to five GAP-compatible DECT handsets can be registered on the SIXTY base. LU Sixty.book Page 33 Mercredi, 19. mai 2010 12:30 12 34 APPENDIX CARE AND MAINTENANCE Turn off your phone. Use a soft damp cloth to wipe it. Do not use a dry cloth, strong liquid detergents, thinners, alcohol or any other type of solvent to clean your phone. These products may damage your phone. PROBLEMS Refer to the table presented below in case of an operational malfunction: Problems Possible causes Remedies You are having trouble reading or cannot read the display when not in standby mode. Contrast too low. Increase the contrast level (refer to paragraph "Adjusting the contrast ", page 24). No display on the base screen. Power connection unplugged. Check the power connection to the phone. No tone. The phone jack is not connected or is incorrectly connected. Check the phone cable connection (refer to paragraph "Connecting the base ", page 12). Make sure you have a dialling tone. The speaker volume is too low. Increase the speaker volume (refer to paragraph "Receiving a call ", page 15). The phone does not ring when a call is received. The mute mode is turned on. Turn off the mute mode (refer to paragraph "Activating/ deactivating the silent mode ", page 24). Your party cannot hear you. You have turned on the mute mode (microphone off). Turn off the mute mode (microphone off) in MENU then MUTE. Make sure that the "MUTE MODE" message is not displayed. You obtain a "busy" dial tone for each dialled number. Incorrect flashing time. Set the flashing time (refer to paragraph "Modifying the flash duration ", page 28). Contact your operator to get it to provide you with the right time. LU Sixty.book Page 34 Mercredi, 19. mai 2010 12:30 12 35 TECHNICAL CHARACTERISTICS INITIAL CONDITION Standard Radio frequency band Number of channels Duplex mode Spacing between channels Bit rate Modulation Vocoding Transmitting power ::::::::: DECT, GAP 1.88-1.90 GHz 120 TDMA 1.728MHz 1152 kbit/s GFSK ADPCM 250 mW Charging time Range up to Batteries Handset operating time Max answering machine capacity Ambient temperature Dimensions Weight including batteries :::::::: Handset Batteries: 10 hours 300 m outside and up to, up to 50 m inside buildings Type Ni-MH, AAA, 2 x 1.2 V 450 mAh talk time up to 10 hours standby time up to 120 hours 20 minutes +5°C to +45°C Base(WxHxL) 220 x 63 x 39 mm Handset(WxHxL) 176 x 130 x 89 mm Base 172g Handset 43 g Accessories Advanced Settings Alarm clock off Network type Public Timer off Dial mode Tone Ring Tone Flashing 100 ms Ringer Traditional PABX prefix Off Keyboard beeps On Answering Machine Silent mode Off Status On Settings Call screening Off Date/Time 01/01/10 // 00:00 Remote access code 0000 Contrast Level 2 Number of rings 7 Language English Restriction off Base code 0000 LU Sixty.book Page 35 Mercredi, 19. mai 2010 12:30 12 36 ENVIRONMENT Environmental protection and sustainable development is an important priority for SAGEMCOM. SAGEMCOM has a policy of using environmentally- friendly systems and makes environmental protection an essential part of the life-cycle of its products – from the manufacturing, to the installation, operation and disposal. PACKAGING The logo (green point) on the packaging means that a fee is paid to an authorised national organisation to improve packaging recycling and the recycling infrastructure. Follow the local sorting regulations for this type of waste product in order to improve recycling. BATTERIES AND RECHARGEABLE BATTERIES If your product contains batteries or rechargeable batteries, these must be disposed of at designated collecting centers. THE PRODUCT The crossed out dustbin displayed on the product signifies that it belongs to the electrical and electronic equipment group. The European regulations request you to carry out your own selective recycling collection at: • the sales outlet when you buy a similar new device. • the collection points available in your area (recycling centres, sorting points, etc). This means you participate in the recycling and valorisation of used electric and electronic goods which would otherwise have a negative impact on the environment and health. Annexe.fm Page 36 Jeudi, 20. mai 2010 9:03 09 37 GUARANTEE TERMS AND CONDITIONS FOR UNITED KINGDOM & IRELAND ONLY In order to apply the guarantee, you should contact the SAGEMCOM Helpdesk or the retailer where you purchased the equipment. Proof of purchase will be required in either case. Please make sure that you use your equipment only for the purpose for which it was designed and under normal usage conditions. SAGEMCOM do not accept any liability for the equipment if used outside the frame of its original designed purpose or any consequence that may arise from this usage. Should any malfunction arise, the SAGEMCOM Helpdesk or your retailer will advise you how to proceed. A) General Guarantee conditions SAGEMCOM undertakes to remedy by repair or exchange at its own convenience, free of charge for labour and replacement parts, any defects in the equipment during the guarantee period of 12 (twelve) months or 3 (three) months for accessories, from the date of original invoice of the Equipment, where those defects are a result of faulty workmanship. Unless the customer has concluded with SAGEMCOM a maintenance contract in respect of the equipment which specifically provides for repairs to be carried out at the customer`s premises, the repairs will not be carried out on the equipment at the customer premises. The customer must however return the defective equipment at his/her own expense, to the address supplied by the SAGEMCOM Helpdesk or by the retailer. In the case that a product needs to be sent in for a repair, it must always be accompanied by a proof of purchase (which is not altered, written on or in any way made illegible) showing that the product is still under guarantee. In the case that no proof of purchase is enclosed, the SAGEMCOM repair centre will use the production date as its reference for establishing the guarantee status of the product. Apart from all legal obligatory rules, SAGEMCOM, do not give any Guarantee, either implicit or explicit which is not set force in the present section, and can not be held responsible for any direct or indirect, material or immaterial damage, either in or out of the frame of the present guarantee. If any provision of this guarantee shall be held to be in whole or in part invalid or illegal due to an obligatory rule applicable to consumers pursuant to their national legislation, such invalidity or illegality shall not impair or affect the remaining provisions or parts of this guarantee. This guarantee does not affect the Customer statutory rights. LU Sixty.book Page 37 Mercredi, 19. mai 2010 12:30 12 38 B) Exclusions From Guarantee SAGEMCOM shall have no liability under the guarantee in respect of: • Damage, defects, breakdown or malfunction due to one or more of the following: - Failure to properly follow the installation process and instructions for use - An external cause to the equipment (including but not limited to: lightening, fire, shock, vandalism, inappropriate conditions of electrical network or water damage of any nature) - Modifications made without the written approval of SAGEMCOM - Unsuitable operating conditions, particularly of temperature and humidity - Repair or maintenance of the equipment by persons not authorised by SAGEMCOM • Wear and tear from normal daily use of the equipment and its accessories • Damage due to insufficient or bad packaging of equipment when returned to SAGEMCOM • Usage of new versions of software without the previous approval of SAGEMCOM • Work on any equipment or software modified or added without the prior written consent of SAGEMCOM • Malfunctions not resulting from the Equipment or from software installed in user workstations for the purpose of use of the equipment. Communication problems related to an unsuitable environment including: - Problems related to access and/or connection to the Internet such as interruptions by access networks or malfunction of the line used by the subscriber or his correspondent - Transmission faults (for example poor geographical coverage by radio and TV transmitters, interference or poor line quality) - Local network faults (wiring, servers, workstations) or the failure of the transmission network (such as but not limited to interferences, fault or poor quality of the network) - Modification of the parameters of the cellular or broadcast network carried out after the sale of the Product • Normal servicing (as defined in the user guide supplied with the equipment) as well as malfunctioning due to servicing not being carried out. Servicing costs are in any event always borne by the customer. • Malfunctions resulting from the usage of products, consumables or accessories not compatible with the equipment. C) Out of Guarantee Repairs In the cases set forth in B) as well as after expiry of the guarantee period, the customer must ask the Authorised SAGEMCOM Repair Centre for a cost estimation prior to work being carried out. In such cases, the repair and delivery costs will be invoiced to the customer. The foregoing shall apply unless otherwise agreed in writing with the customer and only for the United Kingdom and Ireland. LU Sixty.book Page 38 Mercredi, 19. mai 2010 12:30 12 39 TERMS AND CONDITIONS FOR OTHER COUNTRIES If, despite our best efforts, your product presents any defects, you should refer to your retailer and present the proof of purchase that they gave you on the day of purchase. Should any malfunctioning arise, the retailer will advise you what to do. For the warranty to apply, you should ensure that the product was used in accordance with the instructions for use and the purpose for use, and that you have at your disposal the sales invoice or receipt stating the date of purchase, the name of the retailer, the reference and the serial number of the product. No coverage shall be given under this warranty if the following conditions are applicable: • The required documents have been modified or altered in order to take advantage of the warranty. • The manufacturing numbers, product brands or labels have been altered or made illegible. • Interventions on the product have been made by an unauthorized person. • The product has been subjected to abnormal or improper use. • The product has been damaged by external factors such as lightning, over-voltage, moisture, accidental damage, improper care as well as all Acts of God. This present warranty does not affect the consumer rights that you may have under the laws in effect in your country. Important: Should you return the product to the after-sales department, please ensure that you return as well all the elements and accessories originally supplied with the product. LU Sixty.book Page 39 Mercredi, 19. mai 2010 12:30 12 SIXTY by Sagemcom Broadband SAS 250, route de l'Empereur - 92848 Rueil-Malmaison - France Tél. +33(0)1 57 61 10 00 - Fax : +33(0)1 57 61 10 01 www.sagemcom.com All rights reserved. Sagemcom Broadband SAS reserves the right to change the technical characteristics of its products and services or to stop marketing them at any time. The information and specifications included are subject to change without prior notice. Sagemcom Broadband SAS tries to ensure that all information in this document is correct, but does not accept liability for error or omission. Non contractual document. All trademarks are registered by their respective owners. Simplified joint stock company - Capital 35 703 000 € - 518 250 360 RCS Nanterre Thermomètre infrarouge 572-2 L'outil qu'il vous faut pour les environnements les plus chauds 2 Fluke Corporation Thermomètre infrarouge 572-2 Caractéristiques techniques du thermomètre infrarouge 572-2 Mesures infrarouges Gamme de température infrarouge -30 °C à 900 °C Précision IR (Géométrie d'étalonnage à une température ambiante de 23 °C ± 2 °C) ≥0 °C ± 1 °C ou ± 1 % du relevé, selon la valeur la plus élevée ≥-10 °C à <0 °C ± 2 °C <-10 °C ± 3 °C Répétabilité IR ± 0,5 % de la mesure ou ± 0,5 °C, selon la valeur la plus élevée Résolution d'affichage 0,1 °C / 0,1 °F Distance : Mesure 60:1 (calculée à 90 % de l'énergie) Dimensions minimales du point 19 mm Système de visée laser Décalage du laser double, puissance de sortie <1 mW Réponse spectrale 8 μm à 14 μm Temps de réponse (95 %) <500 ms Emissivité Réglable numériquement de 0,10 à 1,00 par pas de 0,01 ou à partir du tableau intégré des matériaux courants Options de mesure Alarmes Basse et/ou Haute Sonores ou visuelles en couleur Min/Max/Moy/Dif Oui Commutable entre degrés Celsius et Fahrenheit Oui Rétro-éclairage Deux niveaux, normal et ultra-lumineux pour les environnements sombres Entrée sonde Thermocouple de type K Affichage simultanée de la température IR et de la sonde sur le thermocouple de type-K Verrouillage du déclenchement Oui Stockage de données 99 points Ecran Matriciel de 98 x 96 pixels avec menus de fonctions Communication USB 2.0 Caractéristiques techniques du thermocouple de type K Gamme de températures en entrée du thermocouple de type K -270 °C à 1 372 °C Précision d'entrée du thermocouple de type-K (avec température ambiante de 23 °C ± 2 °C) <-40 °C ± (1 °C + 0,2 °/1 °C) ≥-40 °C ± 1 % ou 1 °C, selon le plus élevé des deux Résolution du thermocouple de type K 0,1 °C Répétabilité de thermocouple type K ± 0,5 % de la mesure ou ± 0,5 °C, selon la valeur la plus élevée Gamme de mesure (sonde à perles du thermocouple de type K) -40 °C à 260 °C Précision ± 1,1 °C de 0 °C à 260 °C. Typiquement à moins de 1,1 °C de -40 °C à 0 °C Longueur du câble Câble de thermocouple de type K de 1 m avec connecteur de thermocouple miniature standard et terminaison par perle Caractéristiques générales Température de fonctionnement 0 °C à 50 °C Température de stockage -20 °C à 60 °C Humidité relative 10 % à 90 % HR sans condensation jusqu'à 30 °C Altitude de fonctionnement 2 000 mètres au-dessus du niveau moyen de la mer Poids 0,322 kg Puissance 2 piles AA Autonomie 8 heures avec laser et rétro-éclairage allumés ; 100 heures avec laser et rétro-éclairage éteints, rapport cyclique de 100 % (thermomètre actif en continu) Sécurité et conformité IEC 60825-1 Laser FDA Classe II EMC 61326-1 Conformité CE CMC 沪制01120009 3 Fluke Corporation Thermomètre infrarouge 572-2 Pour commander Thermomètre infrarouge 572-2 Comprend Thermomètre infrarouge avec fonctions de thermomètre de contact, sonde à perle pour thermocouple de type K, cordon d’interface USB 2.0, logiciel de documentation FlukeView® Forms, mallette de transport rigide, manuel d'introduction (papier) et manuel de l'utilisateur (CD). Sondes de température recommandées Sonde Utilisation 80PK-1 Cette sonde à perle polyvalente permet de mesurer rapidement et avec précision les températures de surface et les températures de l'air dans les gaines et les bouches d'aération. 80PK-8 Les sondes de température à collier de serrage (2) sont essentielles pour le suivi des différentiels de température en constante évolution sur les boucles de tuyauterie et les tubulures d'eau chaude, et excellentes pour obtenir des températures de réfrigération rapides et précises. 80PK-9 La sonde de perforation d'isolant dispose d'un embout pointu pour perforer l'isolation des tuyaux, et d'un embout à bout plat pour obtenir des mesures de contact thermique en surface, des températures dans les gaines et les bouches d'aération. 80PK-11 La sonde pour thermocouple à gaine souple permet de fixer facilement un thermocouple au tuyau pour une utilisation en mains libres. 80PK-25 La sonde perforante est l’option la plus polyvalente. Excellente pour vérifier la température de l'air des conduits, la température de surface sous les moquettes/rembourrages, des liquides, des puits de thermomètre, des températures d'évacuation et pour pénétrer l'isolation des tuyaux. 80PK-26 La sonde conique est une excellente sonde polyvalente de mesure de surface et de gaz, disposant d'une bonne longueur et d'un revêtement d'embout à faible masse pour une réaction accélérée aux températures de l'air et des surfaces. Fluke Deutschland GmbH Parc des Nations - Allee du Ponant Bat T3 95956 ROISSY CDG CEDEX Téléphone: (01) 48 17 37 37 Télécopie: (01) 48 17 37 30 E-mail: info@fr.fluke.nl Web: www.fluke.fr N.V. Fluke Belgium S.A. Langveld Park – Unit 5 P. Basteleusstraat 2-4-6 1600 St. Pieters-Leeuw Tel: 02/40 22 100 Fax: 02/40 22 101 E-mail: info@fluke.be Web: www.fluke.be Fluke (Switzerland) GmbH Industrial Division Hardstrasse 20 CH-8303 Bassersdorf Tel: 044 580 75 00 Fax: 044 580 75 01 E-mail: info@ch.fluke.nl Web: www.fluke.ch ©2013 Fluke Corporation. Tous droits réservés. Informations modifiables sans préavis. 6/2013 Pub_ID: 12090-fre La modiflcation de ce document est interdite sans l’autorisation écrite de Fluke Corporation. User’s Guide October 2012 LMP91051EVM User’s Guide October 2012 LMP91051EVM User’s Guide CONTENTS 1 INTRODUCTION ................................................................................................... 1 2 SETUP .................................................................................................................. 2 3 OPERATION ......................................................................................................... 5 4 INSTALLING THE SENSOR AFE SOFTWARE ................................................... 10 5 BOARD LAYOUT ................................................................................................ 11 6 SCHEMATIC ....................................................................................................... 12 7 BOM .................................................................................................................... 13 LIST OF FIGURES 1 Connection Diagram ............................................................................................... 2 2 Jumper Setting (Default) for voltage reading ........................................................... 3 3 LMP91051EVM to SPIO-4 Board Connection ......................................................... 4 4 Sensor AFE Items of Interest .................................................................................. 5 5 Recommended LMP91051 Configuration for a voltage Reading ............................. 7 6 Sensor Database Window ..................................................................................... 8 7 Reults of DC Reading ............................................................................................. 9 8 LMP91051EVM’s J3 for SPI Signals ..................................................................... 10 9 LMP91051EVM Layout ......................................................................................... 11 8 LMP91051EVM Schematic ................................................................................... 12 LIST OF TABLES 1 Jumpers for Voltage Measurement ......................................................................... 3 2 LMP91051EVM Bill of Materials............................................................................ 13 1. Introduction The LMP91051 Design Kit (consisting of the LMP91051 Evaluation Module, the SPIO-4 Digital Controller Board, the Sensor AFE software, and this user’s guide) is designed to ease evaluation and design-in of Texas Instrument’s LMP91051 Configurable AFE for Nondispersive Infrared (NDIR). Data capturing and evaluations are simplified by connecting the SPIO-4 Digital Controller Board (SPIO-4 board) to a PC via USB and running the Sensor AFE software. The data capture board will generate the SPI signals to communicate to and capture data from the LMP91051. The user will also have the option to evaluate the LMP91051 without using the SPIO-4 board or the Sensor AFE software. The on board data converter will digitize the LMP91051’s analog output, and the software will display these results in time domain and histogram. The software also allows customers to write to and read from registers, to configure the device’s gain, output offset, and common mode voltage, and most importantly, to configure and learn about the LMP91051. 2 LMP91051EVM User’s Guide snou034 This document describes the connection between the boards and PC, and provides a quick start for voltage measurements. This document also describes how to evaluate the LMP91051 with and without the SPIO-4 board and provides the schematic, board layout, and BOM. 2. Setup This section describes the jumpers and connectors on the EVM as well and how to properly connect, set up and use the LMP91051EVM. 2.1. Connection Diagram Figure 1 shows the connection between the LMP91051 Evaluation Module (LMP91051EVM), SPIO-4 board, and a personal computer with the Sensor AFE software. LMP91051 can be powered using external power supplies or from the SPIO-4 board. Figure 1: Connection Diagram 2.2. Jumper Connections 1. The jumpers for this example application can be seen in Figure 2 and Table 1. 2. The SPIO-4 board is properly setup out of the box (no assembly required). 3. The schematic for the LMP91051EVM can be seen in Figure 10. 3 LMP91051EVM User’s Guide October 2012 Figure 2: Jumper Setting (Default) for voltage reading Table 1: Jumpers for Voltage Measurement Jumpers Pin Purpose JP1: VDD_DUT P1-P2 Connect LMP91051 VDD to +3.3V from SPIO4 JP2: VREF_ADC P1-P2 Connect ADC VREF to 4.1V from U5 (LM4140) JP3: VA_ADC P1-P2 Connect ADC VA to +5V from SPIO4 JP4: OUT_DUT to ADC P1-P2 Connect LMP91051 OUT to ADC input RC filter JP5: VDD to VIO Open Connect LMP91051 VDD to VIO JP6: VIO P2-P3 Connect LMP91051 VIO to +3.3V from SPIO4 J1: IN1 to CMOUT Open Connect LMP91051 IN1 to CMOUT. Note: Board is provided with this jumper open. Use provided jumper to short IN to CMOUT for easy evaluation. J2: IN2 to CMOUT Open Connect LMP91051 IN2 to CMOUT. Note: Board is provided with this jumper open. Use provided jumper to short IN to CMOUT for easy evaluation. 4 LMP91051EVM User’s Guide snou034 2.3. Installing/Opening the Software Follow Section 4 to install and open the Sensor AFE software. 2.4. Connecting and Powering the Boards These Steps have to be done in this order. 1. Connect the LMP91051EVM’s J3 to SPIO-4 Board’s J6. See Figure 3. . Figure 3: LMP91051EVM to SPIO-4 Board Connection 2. Connect SPIO-4 board to a PC via USB. 3. Use a multimeter to measure LMP91051EVM’s +5V test point; it should be approximately 5V. If it is not, check your power supplies and jumpers. Measure test point VREF_ADC; it should be approximately 4.1V. If it’s not, check your jumpers and U5. J3 5 LMP91051EVM User’s Guide October 2012 3. Operation 3.1. Sensor AFE Software Overview Once connection between the boards and PC is established, you can use the software to communicate to and capture data from the LMP91051. Drag cursor over window icons to get an icon description. Some items of interest are shown in Figure 4. Figure 4: Sensor AFE Items of Interest . 1. Menu Bar Icons (from left to right) a. Save Configuration to File: Saves the current configuration settings (register settings) to an .xml file. b. Load Configuration File: Loads the selected configuration settings (register settings) .xml file. c. Register Map: Opens Register Map window. An alternative to the Virtual Device, for writing and reading the device registers. See datasheet for details on device Register Map. d. Save All Registers to File: Saves register contents to a .cvs file. e. Read All Register from Board: After configuring the register map, use this button to read all registers. Functional only in SDIO Mode (see Item 3). f. Write All Registers To Board: After configuring the register map use this button to write all registers. Registers will not be updated until this step is done. g. Zoom In/Out Diagram Image: Zoom in and out of the virtual device image. h. Show Tutorial: Takes you to the interactive Software Overview videos. 1 2 3 4 5 6 LMP91051EVM User’s Guide snou034 i. Documentation: Accesses the LMP91051 Datasheet, SPIO4 User’s Guide, or Evaluation Board User’s Guide. 2. Device Selection and User Inputs a. LMP91050/1 : Toggle between LMP91050 and LMP91051 device. b. fc: Center frequency of external bandpass filter. c. bandwidth: Pass band bandwidth of external bandpass filter. d. R1_EXT, R2_EXT, C1_EXT, C2_EXT: External bandpass filter component values calculated based on user input for center frequency (fc) and pass band (bandwidth) described above. e. Supply: LMP91051 supply voltage (VDD). f. IC Temp: LMP91051 operating temperature g. Offset Adjust Voltage: The tool will calculate the DAC code (decimal) required to achieve this output offset adjust voltage. User must then Write to the register to update the value in the NDAC register. h. ADC Vref: ADC reference voltage. User should input value measured at VREF_ADC test point. Value used to calculate displayed Output Voltage. i. Vout Dark: This value corresponds to the user measured value at the LMP91051 output (OUT) when input is shorted (IN = CMOUT). Tool will use this value to estimate LMP91051 input voltage (IN - CMOUT) on subsequent measurements. 3. Change Mode: Change between device Read Mode OFF (default) and ON. See datasheet for details on SPI Read Mode. 4. Eval Board Setting: Document to show user how to configure jumpers and connect thermopile based on sensor selected. 5. Virtual Device: Drag cursor across color coded blocks and click to configure each block. To update registers “Write All Registers” when done. 3.2. Configuring the LMP91051 Using the Sensor AFE Software Follow the step-by-step instructions under the “HelpBar” mini-tab (left hand side of the GUI) to configure the LMP91051 for this example. These step-by-step instructions are discussed in details below, and the recommended configuration should look similar to Figure 5. 7 LMP91051EVM User’s Guide October 2012 Figure 5: Recommended LMP91051 Configuration for a voltage Reading 1. Step 1: Select a Sensor – Sensor Database window opens. See Figure 6. Step 1: Click sensor type (Thermopile) and the sensors will show in the bottom table. Step 2: Click sensor and then click “Select” button on the left to use this sensor. 8 LMP91051EVM User’s Guide snou034 Figure 6: Sensor Database Window 2. Step 2: Input Mux – click on the mux block to set “1: IN1” (default). 3. Step 3: PGA1 Enable – click on the “PGA1” block to set “1: PGA1 ON” . Remember after configuring the register map to use the Write All Registers button to update the registers. 4. Step 4: PGA2 Enable – click on the “PGA2” block to set “1: PGA2 ON” . Note: By default PGA1 and PGA2 are OFF on power up. However the software was designed to automatically power ON PGA1 and PGA2 for ease of use. 5. Step 5: External Filter – click on the switch block to choose “0: PGA1 to PGA2 direct” (default). 6. Step 6: Common Mode – click on the “CM GEN” block to set “0: 1.15V” (default). 7. Step 7: GAIN 2 – click on the “PGA2” block to set “00: 4” (default). 8. Step 8: GAIN 1 – click on the “PGA1” block to set “0: 250” (default). 9. Step 8: DAC (Output Offset) – click on the “DAC” block to set “128” (default) for 0 mV offset. Alternatively, user can also use the Offset Adjust Voltage user input field to input 0 mV. 10. Step 10: Performance - click on the “Performance” mini-tab. This tab displays the Estimated Device Performance based on device configuration and user input device Supply and IC Temp .This tab also displays the Measured System Performance if you’ve connected a board and ran the LMP91051. Step 1 Step 2 9 LMP91051EVM User’s Guide October 2012 3.3. Capturing Data 1. Click on the “Measurement” tab. 2. Under the “Output Format” field, select Display as “Output Voltage (V)” 3. Under the “Stop Condition” field, select Run as “1” Seconds. Alternatively, select “Run Continuously” radio button to run continuously up to 1 hour. 4. Click on the “Run” button to view the output voltage results. A reading should be plotted as seen in Figure . Output voltage will vary depending on input voltage across input (IN1/IN2) and CMOUT. If J1/J2 are shorted, IN1/IN2 = CMOUT, output voltage should be about 1V. Note: Board is provided with jumper J1/J2 open. Use provided jumper to short IN1/IN2 to CMOUT for easy evaluation. Figure 7: Results of DC Reading 3.4. Powering the LMP91051EVM There are two ways in which VDD can be sourced: external supply or SPIO-4 power. If using an external power supply to source VDD, do the following: 1. Connect an external power supply to banana jacks VDD-EXT and GND. 2. Jumper pins 2 and 3 of JP1 to connect the external power to VDD_DUT. If using the SPIO-4 power to source VDD, then do the following: 1. Jumper pins 1 and 2 of JP1 to connect +3.3V SPIO-4 power to VDD_DUT. The schematic for the LMP91051EVM can be seen in Figure 10. 10 LMP91051EVM User’s Guide snou034 3.5. Evaluating the LMP91051 without the SPIO-4 Board The SPIO-4 digital controller board is used to generate the SPI signals to communicate to the LMP91051. Without the SPIO-4 board, the Sensor AFE software for the LMP91051 cannot be used to capture and analyze data from the LMP91051EVM. If the SPIO-4 board is not available but LMP91051 evaluation is desirable, then connect your own SPI signals to J1 of the LMP91051EVM as seen below. Reference the LMP91051 datasheet for appropriate SPI timing diagrams. Source LMP91051 VDD with an external power supply per previous section. Figure 8: LMP91051EVM’s J3 for SPI Signals Refer to the LMP91051 datasheet for more information on the LMP91051’s SPI protocol. 4. Installing the Sensor AFE Software Each Sensor AFE product will have its own software. To access the Sensor AFE software for LMP91051, follow the steps below. 1. Getting the Zip Files a. You can find the latest downloadable Sensor AFE software at ti.com/sensorafe b. Download the zip file onto your local hard drive. Unzip this folder. 2. Installing the Driver - skip this step if you don’t have the LMP91051EVM and SPIO4 digital controller board. a. See the provided Installation Guide For SensorAFE Drivers.pdf. 11 LMP91051EVM User’s Guide October 2012 3. Installing the Software a. See the provided Installation Guide for LMP91050 SensorAFE Software.pdf i. Note: If you run the software without the boards, you’ll get an error message. Ignore that error message and click “Ok” to continue. 5. Board Layout Figure 9: LMP91051EVM Layout 6. Schematic Figure 10: LMP91051EVM Schematic 7. BOM LMP91051EVM Bill of Materials Item Designator Description Manufacturer PartNumber Quantity 1 +3P3V, +5V, A0_DUT, A1_DUT, CMOUT_DUT, CSB_ADC, CSB_DUT, DOUT_ADC, IN1_DUT, IN2_DUT, MISO, MOSI, MOSI_EN, OUT_DUT, REF_ADC, SCLK_ADC, SCLK_DUT, SDIO_DUT, TEMP, VA_ADC, VDD_DUT, VDD_EXT, VIO, VIO_ADC, VIO_EXT, VREF_ADC Test Point, TH, Compact, Red Keystone Electronics 5005 26 2 AA1 Printed Circuit Board TBD by TI 551xxxxxx-001 REV A 1 3 BNC1, BNC2, OUT DNS Amphenol Connex 112404 3 4 C1 CAP, CERM, 10uF, 6.3V, +/- 20%, X5R, 1206 TDK C3216X5R0J106M 1 5 C2 CAP CER 4700PF 250V X7R 10% 0805 TDK C2012X7R2E472K 1 6 C3, C9, C10, C12, C17, C22 CAP, TANT, 10uF, 10V, +/- 20%, 3.4 ohm, 3216-18 SMD Vishay-Sprague 293D106X0010A2TE3 6 7 C4, C7, C13, C15, C18, C19, C23 CAP, CERM, 0.1uF, 16V, +/- 5%, X7R, 0603 AVX 0603YC104JAT2A 7 8 C5, C6, C21 CAP, CERM, 10nF, 50V, +/-5%, C0G/NP0, 0805 MuRata GRM2195C1H103JA01D 3 9 C8, C14 CAP, CERM, 0.1uF, 25V, +/- 10%, X7R, 0805 AVX 08053C104KAT2A 2 10 C11 CAP, CERM, 0.1uF, 100V, +/- 5%, X7R, 1206 AVX 12061C104JAT2A 1 11 C16, C20 CAP, CERM, 1uF, 10V, +/-10%, X7R, 0805 AVX 0805ZC105KAT2A 2 12 FID1, FID2, FID3 Fiducial mark. There is nothing to buy or mount. N/A N/A 3 13 GND1, GND2, GND3, GND4, GND5, GND6, GND7, GND8, GND9, GND10, GND11 Test Point, TH, Compact, Black Keystone Electronics 5006 11 14 H1, H2, H3, H4 Bump Hemisphere B&F Fastener Supply NY PMS 440 0025 PH 4 15 J1, J2, JP3, JP4, JP5 Header, TH, 100mil, 2x1, Gold plated, 230 mil above insulator Samtec Inc. TSW-102-07-G-S 5 16 J3 SPIO-GPSI16 Header, 16-Pin, Dual row, Right Angle Sullins Connector Solutions PBC36DGAN 1 17 JP1, JP2, JP6 Header, TH, 100mil, 1x3, Gold plated, 230 mil above insulator Samtec Inc. TSW-103-07-G-S 3 18 L1, L2 Ferrite, Chip, 200mA, .080 ohm, SMD Wurth Elektronik eiSos BLM21BD272SN1L 2 19 R1, R2 RES, 160k ohm, 5%, 0.125W, 0805 Vishay-Dale CRCW0805160KJNEA 2 20 R3 DNS Vishay-Dale DNS 1 21 R4 RES, 100k ohm, 5%, 0.125W, 0805 Vishay-Dale CRCW0805100KJNEA 1 22 R5, R10 RES, 0 ohm, 5%, 0.125W, 0805 Vishay-Dale CRCW08050000Z0EA 2 23 R6 RES, 100k ohm, 1%, 0.125W, 0805 Vishay-Dale CRCW0805100KFKEA 1 24 R7 RES, 1.00k ohm, 1%, 0.125W, 0805 Vishay-Dale CRCW08051K00FKEA 1 25 R8 RES, 27.4 ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060327R4FKEA 1 26 R9 RES, 51.1 ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060351R1FKEA 1 27 R11, R12, R13, R14 DNS Vishay-Dale CRCW06031R00JNEA 4 28 U1 LMP91051 Texas Instruments LMP91051 1 29 U2 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC, 10-pin Mini SOIC, Pb- Free Texas Instruments ADC141S628QIMMX/NOP B 1 30 U3 Non-Inverting 3-State Buffer Texas Instruments SN74AHC1G125DCKR 1 31 U4 DNS Heimann HMS J21 1 32 U5 Precision Micropower Low Dropout Voltage Reference, 8- pin Narrow SOIC Texas Instruments LM4140ACM-4.1 1 33 U6 2K 5.0V I2C Serial EEPROM On Semiconductor CAT24C02WI-GT3 1 34 Y1 Osc 4.000Mhz 5.0V Full Size ECS Inc ECS-100AX-100 1 35 Y1A Oscllator Socket Aires Electronics A462-ND 1 EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. 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All rights reserved. FEN LOGIC LTD. Gertboard User Manual Gert van Loo and Myra VanInwegen Revision 1.0 The Gertboard is an add-on GPIO expansion board for the Raspberry Pi computer. It comes with a large variety of components, including buttons, LEDs, A/D and D/A converters, a motor controller, and an Atmel AVR microcontroller. There is a suite of test/example programs for the Gertboard, written in C, which is freely available at www.element14.com/raspberrypi This manual explains both how to set up the Gertboard for various control experiments and also explains at a high level how the test code works. 3 Contents Gertboard Overview ................................................................................................................................ 4 Labels on the circuit board .................................................................................................................. 5 Location of the building blocks on the Gertboard .............................................................................. 7 Jumpers and straps .............................................................................................................................. 8 GPIO pins ........................................................................................................................................... 8 Schematics .......................................................................................................................................... 9 Test programs overview ...................................................................................................................... 9 Macros........................................................................................................................................... 10 Buffered I/O, LEDs, and pushbuttons ................................................................................................... 11 Push buttons ...................................................................................................................................... 12 Locating the relevant sections of the Gertboard ............................................................................... 12 Testing the pushbuttons .................................................................................................................... 14 Testing the LEDs .............................................................................................................................. 16 Testing I/O ........................................................................................................................................ 18 Open Collector Driver ........................................................................................................................... 19 Testing the open collector drivers ..................................................................................................... 20 Motor Controller ................................................................................................................................... 22 Testing the motor controller .............................................................................................................. 23 Digital to Analogue and Analogue to Digital Converters ..................................................................... 25 Digital to analogue converter ............................................................................................................ 25 Analogue to Digital converter ........................................................................................................... 26 Testing the D/A and A/D .................................................................................................................. 26 ATmega device ..................................................................................................................................... 29 Programming the ATmega ................................................................................................................ 30 Arduino pins on the Gertboard ...................................................................................................... 30 A few sketches to get you going ................................................................................................... 31 Minicom ........................................................................................................................................ 36 Combined Tests .................................................................................................................................... 38 A/D and motor controller .................................................................................................................. 38 Decoder ............................................................................................................................................. 39 For More Information ........................................................................................................................... 40 Appendix A: Schematics ....................................................................................................................... 40 4 Gertboard Overview Raspi open collector (6x) Micro controller strapping area Motor controller D A A D SPI PWM I/O UART I/O 12x 3x SPI/dbg out in 1k 1k ULN2803a ATmega 74xx244 L6203 MCP3002 MCP4802 Fig. 1: The principle, high level diagram of the Gertboard. In this view it is possible to see how flexible Gertboard is, by being able to connect various parts of the board together. Above is a principle diagram1 of the Gertboard. Each circle in the diagram represents a header pin. These headers give you access to a wide range of control combinations. As you begin experimenting with the board, you will probably use the strapping area to connect various components on the Gertboard to the Raspberry Pi. This flexibility even allows you, for example, to connect the motor controller input pins to the Atmel ATmega device (an AVR microcontroller). The ATmega device has a separate 6-pin header, which allows it to be programmed by the Raspberry Pi using the (Serial Peripheral Interface) SPI bus. The major building blocks are: • 12x buffered I/O • 3x push buttons • 6x open collector drivers (50V, 0.5A) • 48V, 4A motor controller • 28-pin dual in line ATmega microcontroller • 2-channel 8/10/12 bit Digital to Analogue converter • 2-channel 10 bit Analogue to Digital converter Each of these building blocks has a section below. 1 A ‘principle diagram’ is a coarse overview of the most important parts of the system. It is not correct in all details. For that you must look at the board schematics. 5 Labels on the circuit board Fig. 2: A photograph of the unpopulated Gertboard viewed from above, showing the silver coloured holes and pads that eventually will be home to the components, as well as the legends printed in white epoxy ink, and green solder resist coating. Fig. 3: This image is a diagrammatic representation of the same photograph shown in Fig. 2 above. It was generated from the same files that were used to create the physical printed circuit board. The blue elements in the diagram correspond to the white text and lines on the photo and the red elements correspond to the silver pads and holes on the photo. 6 From now onwards in this guide, because it is much clearer to see, the diagram shown in Fig. x will be used in preference to show you how to wire up the Gertboard, and to run the test and example programs. It is useful to be able to look at the bare board in order to see the labels (the white text in the photo and the blue text in the diagram) on the board without the components getting in the way. These labels provide essential information that is required in order to use Gertboard to its full potential. Almost all of the components have labels, and more importantly, the pins in the headers have labels. It isn’t necessary to be too concerned about the majority of the components; such as resistors and capacitors (labelled with Cn and Rn, where n is some number). These are fairly simple devices that don’t have a ‘right way round’ when they are assembled to the board. Diodes on the other hand, do need assembling the right way round (covered later) - all the diodes are labelled Dn; of these, the ones that you will be interested in are D1 through D12, the light emitting diodes (LEDs; they are located near the top of the board on the left). Pushbutton switches are labelled S1, S2, and S3 (they are located just beneath the LEDs). Fig. 4: Two examples of ICs – an 8-pin and a 20-pin dual-inline (DIL) package. In this package style, pin 1 is always identified as the first pin anticlockwise from the package notch marking. Integrated circuits, or ICs, are marked Un, so for example the I/O buffer chips are U3, U4, and U5 (these are near the middle of the board), while the Atmel microcontroller is U8 (this is below and to the left of U3 to U5). For the ICs, it is very important to know which is pin 1. If the IC is orientated so that the end with the semi-circle notch is to the left, then pin 1 is the leftmost pin in the bottom row. On the Gertboard, the location of pin 1 is always marked with a square pad. Pin numbers increase in an anti-clockwise direction from there, as shown in the diagram. Knowing this means that the schematics in Appendix A can always be related to the pinning on the ICs on the Gertboard. Headers (the rows of pins sticking up from the board) will be a frequently used component on the Gertboard. They are labelled Jn, so for example the header to the ribbon cable from the Raspberry Pi is attached, is J1. Pin 1 on the headers is again marked with a square pad. Power pins are marked with their voltage; for example there are a few positions marked 3V3. This is a commonly used notation in electronics, and in this case it means 3.3 volts. A 5V power supply comes onto the board via the GPIO connector, but the standard Gertboard assembly instructions do not require that a header is installed to access this. If 5V is really required, and spare header pins are available, a header can be soldered in location J24 in the lower right-hand corner of the board, and then a 5V supply can be picked up from the lower pin (next to the text ‘5V’). Ground is marked with GND or a ⊥ symbol. 1 2 3 4 8 7 6 5 1 2 3 4 5 6 7 8 20 19 18 9 10 17 16 15 14 13 12 11 7 Location of the building blocks on the Gertboard Fig. 5: Photograph of an assembled Gertboard, with key functional blocks identified by coloured boundary marking. This image serves as a good reference point for a board that has been successfully assembled from bare board and components. Please note that the appearance of some components can vary. This annotated photo of a populated Gertboard shows where the building blocks (the major capabilities of the board) are located. Some of the building blocks have two areas marked. For example, the turquoise lines showing the Atmel ATmega chip not only surround the chip itself (on the lower left) but also surround two header pins near the bottom of the board, in the middle. These pins are connected to the Atmel chip and provide an easy way to interface the GPIO signals from the Raspberry Pi (which are in the black box) with the Atmel chip. The supply voltage (the voltage that acts as high or logical 1 on the board) is 3.3V. This is generated from the 5V power pin in the J1 header (the one where the ribbon cable to the Raspberry Pi is attached) by the components in the lower right corner of the board. The open collector and motor controllers can handle higher voltages and have points to attach external power supplies. 8 Jumpers and straps Fig. 6: Image showing straps on the left hand side, and jumpers on the right. Straps connect two parts of Gertboard together, whilst jumpers conveniently connect two adjacent pins on the same header, together. The Gertboard Kit contains materials to produce single straps, although the double strap also shown can also be useful. To work properly, and get the maximum flexibility from the Gertboard a number of straps and jumpers are essential. On the left of the photo are straps: they consist of wires that connect the small metal connector and plastic housing, that slip over the header pins. They are meant for connecting header pins that are further apart. It is sometimes useful to have straps that connect two or three adjacent pins to the same number of adjacent pins elsewhere on the board. This is useful for example when you want to use several LEDs. On the right of the above photo are jumpers: they are used to connect two header pins that are right next to each other. There is one jumper that should be in place at all times on the board: the one connecting pins 1 and 2 in header J7. This is the jumper that connects power from the power input pins to the rest of the board. It is near the lower right corner of the board and is the jumper connecting the two pins below the text 3V3 in the photo below. Fig. 7: Image showing header J7 with translucent jumper in place. J7 is located just above J8 (J7 legend is obscured in this image) GPIO pins The header J2, to the right of the text ‘Raspberry Pi’ on the board, provides access to all the I/O pins on the GPIO header. There are 26 pins in J1 (the GPIO header which is connected to the Raspberry Pi through the ribbon cable) but only 17 pins in J2: 3 of the pins in J1 are power and ground, and 6 are DNC (do not connect). The labels on these pins, GP0, GP1, GP4, GP7, etc, may initially seem a little arbitrary, as there are some obvious gaps, and the numbers do not correspond with the pin numbers on the GPIO header J1. These labels are important however: they correspond with the signal names used 9 by the BCM2835, the processor on the Raspberry Pi. Signal GPIOn on the BCM2835 datasheet corresponds to the pin labelled GPn on header J2 (so for example, GPIO17 on the data sheet can be found at the pin labelled GP17 on the board). The numbers in the labels allow us to specify which pins are required in the control programs to be run later. Some of the GPIO pins have an alternate function that are made use of in some of the test programs. These are shown in the table below. The rest are only used as general purpose input/output in the code. On page 27 there is a description of how to gain access to the alternate functions of GPIO pins. GPIO0 SDA0 (alt 0) I2C bus GPIO1 SLC0 (alt 0) GPIO7 SPI_CE1_N (alt 0) SPI bus GPIO8 SPI_CE0_N (alt 0) GPIO9 SPI_MISO (alt 0) GPIO10 SPI_MOSI (alt 0) GPIO11 SPI_SCLK (alt 0) GPIO14 TXD0 (alt 0) UART GPIO15 RXD0 (alt 0) GPIO18 PWM0 (alt 5) pulse width modulation Table 1: Table showing the GPIO pins on the Gertboard, and what their alternative function is. We mention the I2C bus use of GPIO0 and 1 above not because the I2C bus is used in the test programs, but because each of them has a 1800 pull-up resistor on the Raspberry Pi, and this prevents them from being used with the pushbuttons (see page 134). Schematics Whilst there are some circuit diagrams, or schematics, in the main body of the manual for some of the building blocks of the board, they are simplifications of the actual circuits on the board. To truly understand the board and the connections you need to make on it, you need to be a little familiar with the schematics. Thus we have attached the full schematics at the end of this manual as Appendix A. These pages are in landscape format. The page numbers A-1, A-2, etc, are in the lower left corner of the pages (if you hold them so that the writing is the right way up). Test programs overview When you download the Gertboard test/example code (available at www.element14.com/raspberrypi), you will have a file with a name something like gertboard_sw_10_07_12.tar.gz. This is a compressed (hence the .gz suffix, which means it was compressed using the gzip algorithm) archive (hence the .tar), where an archive is a collection of different files, all stored in a single file. To retrieve the original software, put the file where you want your Gertboard software to end up on your Raspberry Pi computer, then uncompress it by typing the following in one of the terminal windows on your Pi (substituting the name of the actual file you have downloaded for the file name we are using in this example): gunzip gertboard_sw_10_07_12.tar.gz 10 Typing a directory command, ls, should then show the newly uncompressed archive file gertboard_sw_10_07_12.tar . So now, to extract the files from the archive, type tar –xvf gertboard_sw_10_07_12.tar A new directory, gertboard_sw, will be created. In it is a set of C files and a makefile. C files are software files, but they need to be compiled to run on the processor on your system. In the case of Raspberry Pi, this is an ARM11. To compile all the code to run on Raspberry Pi, first change directory to gertboard_sw by typing: cd gertboard_sw And then in that directory, type: make all Each building block has at least one test program that goes with it. Currently the test programs are written in C; but they’ll be translated into Python in the near future. Each test program is compiled from two or more C files. The file gb_common.c (which has an associated header file gb_common.h) contains code used by all of the building blocks on the board. Each test has a C file that contains code specific to that test (thus you will find main here). Some of the tests use a special interface (for example the SPI bus), and these tests have an additional C file that provides code specific to that interface (these files are gb_spi.c for the SPI bus and gb_pwm for the pulse width modulator). In each of the sections about the individual building blocks, the code specific to the tests for that block is explained. Since all of the tests share the code in gb_common.c, an overview of that code will be given here. In order to use the Gertboard via the GPIO, the test code first needs to call setup_io. This function allocates various arrays and then calls mmap to associate the arrays with the devices that it wants to control, such as the GPIO, SPI bus, PWM (pulse width modulator) etc. The result of this is that it writes to these arrays control the devices or sends data to them, and reads from these arrays get status bits or data from the devices. At the end of a test program, restore_io should be called, which undoes the memory map and frees the allocated memory. Macros In gb_common.h, gb_spi.h, and gb_pwm.h there are a number of macros that give a more intuitive name to various parts of the arrays that have been mapped. These macros are used to do everything from setting whether a GPIO is used as input or output to controlling the clock speed of the pulse width modulator. In the chart below is a summary of the purpose of the more commonly used macros and give the page number on which its use is explained in more detail. The T column below gives the ‘type’ of the macro. This shows how the macro is used. ‘E’ means that the command is executed, as in: INP_GPIO(17); ‘W’ means that that the command is written to (assigned), as in: GPIO_PULL = 2; 11 ‘R’ means that that the command is read from, as in: data = GPIO_IN0; Macro name T Explanation Page no. INP_GPIO(n) E activates GPIO pin number n (for input) 11 OUT_GPIO(n) E used after above, sets pin n for output 11 SET_GPIO_ALT(n, a) E used after INP_GPIO, select alternate function for pin 24 GPIO_PULL W set pull code 16 GPIO_PULLCCLK0 W select which pins pull code is applied to 16 GPIO_IN0 R get input values 16 GPIO_SET0 W select which pins are set high 17 GPIO_CLR0 W select which pins are set low 17 Table 2: Commonly used macros, their purpose, type and location within this manual. The macro INP_GPIO(n) must be called for a pin number n to allow this pin to be used. By default its mode is set up as an input. If it is required that the pin is used for an output, OUT_GPIO(n)must be called after INP_GPIO(n). Buffered I/O, LEDs, and pushbuttons There are 12 pins which can be used as input or output ports. Each can be set to behave either as an input or an output, using a jumper. Note that the terms ‘input’ and ‘output’ here are always with respect to the Raspberry Pi: in input mode, the pin inputs data to the Pi; in output mode it acts as output from the Pi. It is important to keep this in mind as the Gertboard is set up: an output from the Gertboard is an input to the Raspberry Pi, and so the ‘input’ jumper must be installed to implement this. I/O 1k 1k-10k input 74xx244 output Raspi Fig. 8: The circuit diagram for I/O ports 4-12 The triangles symbols in the diagram above represent buffers. In order to make the port function as an input to the Raspberry Pi you install the ‘input’ jumper: then the data flows from the ‘I/O’ point to the ‘Raspi’ point. To make the port function as an output, the ‘output’ jumper must be installed: then the data flows from the ‘Raspi’ point to the ‘I/O’ point. If both jumpers are installed, it won’t harm the board, but the port won’t do anything sensible. 12 In both the input and output mode the LED will indicate what the logic level is on the ‘I/O’ pin. The LED will be on when the level is high and it will be off when the level is low. There is a third option for using this port: if neither the input nor output jumper is placed the I/O pin can be used as a simple ‘logic’ detector. The I/O pin can be connected to some other logic point (i.e. one that is either at 0V or 3.3V) and use the LED to check if the connect point is seen as high or low. Depending on the type of 74xx244 buffer chosen, the LED could behave randomly if the port is not driven properly. In that case it may easily switch state, switching on or off with the smallest of electronic changes, for example, when the board is simply touched. There is a series resistor between the input buffer and the GPIO port. This is to protect the BCM2835 (the processor on the Raspberry Pi) in case the user programs the GPIO as output and also leaves the ‘input’ jumper in place. The BCM2835 input is a high impedance input and thus even a 10K series resistor will not produce a noticeable change in behaviour when it is used as input. Push buttons The Gertboard has three push buttons; these are connected to ports 1, 2, and 3. Thus the first three I/O ports look like this: I/O 1k 1k-10k input 74xx244 output Raspi 1k Fig. 9: Circuit diagram showing one of the three push buttons I/Os. There is a circuit like this for ports 1 to 3. In order to use a push button, the ‘input’ jumper must not be installed, even if the intention is to use this as an input to the Raspberry Pi. If it is installed, the output of the lower buffer prevents the pushbutton from working properly. To make clear what state each button is in, the output jumper can be installed, and then the LED will now show the button state (LED on means button up, LED off means button down). To use the push buttons, a pull-up must be set on the Raspberry Pi GPIO pins used (described below, page 16) so that they are read as high (logical 1) when the buttons are not pressed. Locating the relevant sections of the Gertboard In the building blocks location diagram on page 7, the components implementing the buffered I/O are outlined in red. The ICs containing the buffers are U3, U4, and U5 near the centre of the board. The LEDs (the round translucent red plastic devices) are labelled D1 to D12; D1 is driven by port 1, D2 by port 2, etc. The pushbutton switches (the silver rectangular devices with circular depressions in the middle) are labelled S1 to S3; S1 is connected to port 1 and so on. The long thin yellow components with multiple pins, are resistor arrays. 13 The pins corresponding to ‘Raspi’ in the circuit diagrams above are B1 to B12 on the J3 header above the words ‘Raspberry Pi’ on the board (B1 to B3 correspond to the ‘Raspi’ points on the second circuit diagram with the pushbutton, and B4 to B12 correspond to the ‘Raspi’ points on the first circuit diagram). They are called ‘Raspi’ because these are the ones that should be connected to the pins in header J2, which are directly connected to the pins in J1, and which are then finally connected via the ribbon cable to the Raspberry Pi. The pins corresponding to the ‘I/O’ point on the right of the circuit diagrams above are BUF1 to BUF12 in the (unlabeled) single row header at the top of the Gertboard. On the Gertboard schematic, I/O buffers are on page A-2. The buffer chips U3, U4, and U5 are clearly labelled. It should be apparent that ports 1 to 4 are handled by chip U3, ports 5 to 8 by chip U4, and ports 9 to 12 by chip U5. The ‘Raspi’ points in the circuit diagrams above are shown as the signals BUF_1 to BUF_12 on the left side of the page, and the ‘I/O’ points are BUF1 to BUF12 to the right of the buffer chips. The input jumper locations are the blue rectangles labelled P1, P3, P5, P7, etc to the left of the buffer chips, and the output jumper locations are the blue rectangles labelled P2, P4, P6, P8, etc, to the right of the buffer chips. The pushbutton switches S1, S2, and S3 are shown separately, on the right side of the page near the bottom. The buffered I/O ports can be used with (almost) any of the GPIO pins; they just have to be connected up using the straps. So for example, if you want to use port 1 with GPIO17 a strap is placed between the B1 pin in J3 and the GP17 pin in J2. Beware that the push buttons cannot be used with GPIO0 or GPIO1 (GP0 and GP1 in header J2 on the board) as those two pins have a 1800 pull-up resistor on the Raspberry Pi. When the button is pressed the voltage on the input will be 3.3 × 1000Ω 1000Ω + 1800Ω = 1.2 This is not an I/O voltage which can be reliably seen as low. The output and input jumper locations are above and below the U3, U4, and U5 buffer chips. The ‘input’ jumpers need to be placed on the headers below the chips (shown on the board with the ‘in’ text; they are separated from the chip they go with by a yellow resistor array), and the ‘output’ jumpers need to be placed on the headers above the chips (with the ‘out’ text). If viewed closely (it is clearer on the bare board), it is possible to see that each row of 8 header pins above and below the buffer chips is divided up into 4 pairs of pins. The pairs on U3 are labelled B1 to B4, the ones on U4 are B5 to B8, and the ones on U5 are B9 to B12. The B1 pins are for port 1, B2 for port 2, etc. To use port n as an input (but not when using the pushbutton, if n is 1, 2, or 3), a jumper is installed over the pair of pins in Bn in the row marked ‘in’ (below the appropriate buffer chip). To use port n as an output, a jumper is installed over the pair of pins in Bn in the row marked ‘out’ (above the appropriate buffer chip). 14 Fig. 10: Example of port configuration where ports 1 to 3 are set to be outputs and ports 10 and 11 are set to be inputs. As a concrete example, in the picture above, ports 1, 2, and 3 are configured for output (because of the jumpers across B1, B2, and B3 on the ‘out’ side of chip U3). Ports 10 and 11 are configured for input (because of the jumpers across B10 and B11 on the ‘in’ side of U5). In the test programs, the required connections are printed out before starting the tests. The input and output jumpers are referred to in the following way: U3-out-B1 means that there is a jumper across the B1 pins on the ‘out’ side of the U3 buffer chip. So the 5 jumpers in the picture above would be referred to as U3-out-B1, U3-out-B2, U3-out-B3, U5-in-B10, and U5-in-B11. Testing the pushbuttons The test program for the pushbutton switches is called buttons. To run this test, the Gertboard must be set up as in the image below. There are straps connecting pins B1, B2, and B3 in header J3 to pins GP25, GP24, and GP23 in header J2 (respectively). Thus GPIO25 will read the leftmost pushbutton, GPIO24 will read the middle one, and GPIO23 will read the rightmost pushbutton. The jumpers on the ‘out’ area of U3 (U3-out-B1, U3-out-B2, U3-out-B3) are optional: if they are installed, the leftmost 3 LEDs will light up to indicate the state of the switches. 15 Fig. 11: Whilst the image above is clear, it isn’t very good at showing exactly how the straps are connected, and between which pins on the board. Fig. 12: This type of diagram is much more effective at showing how straps connect pins together on the board, so from now onwards, we will use these type of diagrams to show wiring arrangements. 16 In the diagram, black circles show which pins are being connected, and black lines between two pins indicate that jumpers (if they are adjacent) or straps (if they are further apart) are used to connect them. The code specific to the buttons test is buttons.c. In the main routine, the connections required for this test are firstly printed to the terminal (a text description of the wiring diagram above). When the user verifies that the connections are correct, setup_io is called (described on page 10) to get everything ready. setup_gpio is then called, which gets GPIO pins 1 to 3 ready to be used as pushbutton inputs. It does this by first using the macro INP_GPIO(n) (where n is the GPIO pin number) to select these 3 pins for input. Then pins are required to be pulled high: the buttons work by dropping the voltage down to 0V when the button is pressed, so it needs to be high when the button is not pressed. This is done by setting GPIO_PULL to 2, the code for pull-up. Should it ever be required, the code for pull-down is 1. The code for no pull is 0; this will allows this pin to be used for output after it has been used as a pushbutton input. To apply this code to the desired pins, set GPIO_PULLCCLK0 = 0X03800000. This hexadecimal number has bits 23, 24, and 25 set to 1 and all the rest set to 0. This means that the pull code is applied to GPIO pins 23, 24, and 25. A short_wait allows time for this to take effect, and then GPIO_PULL and GPIO_PULLCLK0 are set back to 0. Back in the main routine, a loop is entered in which the button states are read (using macro GPIO_IN0), grabbing bits 23, 24, and 25 using a shift and mask logical operations, and, if the button state is different from before, it is printed out in binary: up (high) is printed as ‘1’ and down (low) is printed as ‘0’. This loop executes until a sufficient number of button state changes have occurred. After the loop, unpull_pins is called, which undoes the pull-up on the pins, then call restore_io in gb_common.c to clean up. Testing the LEDs The test program for the LEDs is called leds. To set up the Gertboard to run this test, see the wiring diagram below. Every I/O port is connected up as an output, so all the ‘out’ jumpers (those above the buffer chips) are installed. Straps are used to connect the following (where all the ‘GP’ pins are in header J2 and all the ‘B’ pins are in header J3): GP25 to B1, GP24 to B2, GP23 to B3, GP22 to B4, GP21 to B5, GP18 to B6, GP17 to B7, GP11 to B8, GP10 to B9, GP9 to B10, GP8 to B11, and GP7 to B12. In other words, the leftmost 12 ‘GP’ pins are connected to the ‘B’ pins, except that GP14 and GP15 are missed out: they are already set to UART mode by Linux, so it’s best if they are not touched. If there aren’t enough jumpers or straps to wire these connections all up at once, don’t worry. Just wire up as many as possible, and run the test. Once it’s finished the straps/jumpers can be moved and the test can be run again. Nothing bad will happen if a pin is written to that has nothing connected to it. 17 Fig. 13: The wiring diagram necessary to run the Gertboard LED test program, leds The test code in leds.c first calls setup_io to get everything ready. Then setup_gpio is called, which prepares 12 GPIO pins to be used as outputs (as all 12 I/O ports will require controlling). All of the GPIO signals except GPIO 0, 1, 4, 14, and 15 are used. To set them up for output, first call INP_GPIO(n) (where n is the GPIO pin number) for each of the 12 pins to activate them. This also sets them up for input, so then call OUT_GPIO(n) afterwards for each of the 12 pins to put them in output mode. LEDs are switched on using the macro GPIO_SET0: the value assigned to GPIO_SET0 will set GPIO pin n to high if bit n is set in that value. When a GPIO pin is set high, the I/O port connected to that pin goes high, and the LED for that port turns on. Thus, the line of code “GPIO_SET0 = 0x180;” will set GPIO pins 7 and 8 high (since bits 7 and 8 are set in the hexadecimal number 0x180). Given the wiring setup above, ports 11 and 12 will go high (because these are the ports connected to GP7 and GP8), and thus the rightmost two LEDs will turn on. To turn LEDs off, use macro GPIO_CLR0. This works in a similar way to GPIO_SET0, but here the bits that are high in the value assigned to GPIO_CLR0 specify which GPIO ports will be set low (and hence which ports will be set low, and which LEDs will turn off). So for example, given the wiring above, the command “GPIO_CLR0 = 0x100;” will set GPIO8 pin low, and thus turn off the LED for port 11, which is the port connected to GP8. (In leds.c the LEDs are always all turned off together, but they don’t have to be used this way.) The test program flashes the LEDs in three patterns. The patterns are specified by a collection of global arrays given values using an initializer. The number in each of the arrays says which LEDs will 18 be turned on at that point in the pattern – so, pattern value is submitted sequentially to produce the changing pattern, switching all the LEDs off between successive pattern values. Each pattern is run through twice. The first pattern lights the LEDs one at a time in sequence, left to right. The second pattern does the same but when it reaches the rightmost LED, it then reverses direction and lights them in sequence right to left. The third pattern starts at the left end and at each step switches on one more LED until they are all lit up, then starting at the left it switches them off one by one until they are all off. Finally, the test program switches off all the LEDs and then finally calls restore_io to clean up all the LEDs to a predictable final state. Testing I/O Our two examples so far have only used the ports to access the pushbuttons and LEDs. The next example, called butled (for BUTton LED) will show one of the ports serving just as an input port. The idea is that one port (along with its button) is used to generate a signal, and software then sends that signal to another port which it is used as just an input. We read both ports in and print them on the screen. Fig. 14: The wiring diagram for test program butled which detects a button press, and then display that button state on the screen. This is to test all the I/O on the Gertboard. The wiring for this test is shown above. Pin GPIO23 controls I/O port 3, and GPIO22 controls I/O port 6, so GP23 in header J2 is connected to pin B3 in header J3, and GP22 is connected to B6. Now, for the interesting part. The pushbutton on port 3 is going to be used here, but the LED for port 3 should not be used, so therefore the output jumper for port 3 is not installed (which would be placed at U3-out-B3). 19 Looking at the schematic on page A-2, it is clear that the output buffer for port 3 goes to pin 14 of buffer chip U3. This is connected to the U3-out-B3 header pin just above pin 14 on the chip (it is pin 1 of U3-out-B3; this is clear from the schematic and from the fact that this pin has a square pad on the bare circuit board), so that pin is connected to the BUF6 pin at the top of the board. This allows the switch to generate a signal which is then sent to port 6. A jumper is installed across U4-in-B6 to allow that signal to be input from the board. The value of the switch from port 3 is also read in, and these two should be the same (most of the time). In butled.c we use INP_GPIO to set GPIO22 and GPIO23 to input and GPIO_PULL and GPIO_PULLCLK0 to set the pull-up on GPIO23. This is described in more detail on page 16, in the buttons test. Then the GPIO values are repeatedly read in, and the binary values of GPIO22 and GPIO23 are printed out, if they have changed since the last cycle. So if ‘01’ is displayed on the monitor, it can be deduced that GPIO23 is low and GPIO22 is high. (Note that the LED for port 6, labelled D6, should be off when switch 3 is pressed and on when switch 3 is up.) Now, if the values for GPIO22 and GPIO23 are always the same, ‘00’ and ‘11’ will only ever be printed out. But if the test is started with button 3 up (so ‘11’ is displayed), and then the button is pushed down, occasionally ‘01’ might be seen, followed very quickly by ‘00’. The reason for this differs between the Python and C implementations. In the C version, both values are read at the same time, and the signal from the push button (which is connected to GPIO23) takes a small amount of time to propagate through the buffers to get to GPIO22. It may even be possible to get one reading in after GPIO23 has changed, but insufficient time has passed for GPIO22 to change state and follow it! In the Python code, the read of GPIO22 occurs before the read of GPIO23 (the button). Thus if the button is pressed or released between these two reads, the new value will be read in for the button (GPIO23), but the new value of the other input (GPIO22) won’t change until the next time through the while loop. Open Collector Driver The Gertboard uses six ports of a ULN2803a to provide open collector drivers. These are used to turn off and on devices, especially those that need a different voltage or higher current than that available on the Gertboard and are powered by an external power supply. The ULN2803a can withstand up to 50V and drive 500mA on each of its ports. Each driver has an integrated protection diode (the uppermost diode in the circuit diagram below). Raspi OUT common Fig. 15: Circuit diagram of each open collector driver. 20 The ‘common’ pin is, as the name states, common for all open collector drivers. It is not connected to any other point on the Gertboard. As with all devices the control for the open collector drivers (the ‘Raspi’ point) can also be connected to the ATmega controller to, for example, drive relays or motors. The open collector drivers are in the schematics on page A-3. On the Gertboard building block diagram on page 7, the area containing the components for the open collector drivers are outlined in yellow. The pins corresponding to ‘Raspi’ in the diagram above are RLY1 to RLY6 pins in the J4 header; the pins corresponding to ‘common’ are the ones marked RPWR in the headers on the right edge of the board; and the pins corresponding to ‘OUT’ are the RLY1 to RLY6 pins in the headers J12 to J17. How these are then used is demonstrated by the test wiring and code examples. Testing the open collector drivers The program ocol (for open collector) allows the functional testing of the open collector drivers. A simple mechanism was required to switch the driver on and off, so we created a little circuit (see diagram below) consisting of two large LEDs and a resistor in series. Once connected, the forward voltage across each of these LEDs is a little above 3V, so we used a 9V battery as a power supply, and calculated a series resistance of around about 90 to set a suitable current flow through the LEDs. Since this small test circuit will not be used again, it can simply be hand soldered together off-board. Remember that LEDs are diodes, and have to be connected the right way round. The small ‘flat’ in the LED moulding denotes the ‘cathode’ or negative pin. If you think of the LED symbol in the circuit diagram below as an arrow, it is pointing in the direction of the current flow, from + to -, or from anode to cathode. To turn the circuit off and on using the open collector driver (say you want to use driver 1), first check that it works with the power supply described above. Then, leave the positive side of your circuit attached to the positive terminal of the power supply, but in addition connect it to one of the RPWR pins in the headers on the right edge of the board (they are all connected together). Disconnect the ground side of the circuit from the power supply and connect it instead to RLY1 in header J12 on the right of the board. Attach the ground terminal of the power supply to any GND or ⊥ pin on the board. Now, we need a signal to control the driver. For the ocol test we are using GPIO4 to control the open collector (you could of course use any logic signal), so connect GP4 in header J2 to RLY1 in J4. (To test a different driver, say n, with the ocol test, connect the ground side of the circuit up to RLYn in the headers on the right of the board and connect GP4 in header J2 to RLYn in J4.) Now, when RLY1 in J4 is set low, the circuit doesn’t receive any power and thus is off. When RLY1 in J4 goes high, the open collector driver uses transistors to connect the ‘ground’ side of the circuit to the ground on the board, and since this is connected to the ground terminal on the power supply, the power supply ends up powering the circuit: it is just turned off and on by the open collector driver. 21 Fig.16: Wiring diagram showing how to connect Gertboard to test the open collector drivers. It also shows the small test power supply made up of two LEDs in series, a 90  resistor and a 9V battery. You may wonder why you need to connect the positive terminal of the power supply to the open collector driver (via the RPWR pin). The reason for this is that if the circuit happens to contain an component that has electrical inductance, for example a motor or a relay, when the power is turned off this inductance causes the voltage on RLYn pin to quickly rise to a higher voltage than the positive terminal of the power supply, dropping quickly afterwards. The chip itself has an internal diode connecting the RLYn pin to the RPWR. This allows current to flow to the top (positive side) of your circuit, allowing the energy to dissipate, and preventing damage. The ocol test is very simple. First, it prints out the connections required on the board (and with your external circuit and power supply), and then it calls setup_io to get the GPIO interface ready to use and setup_gpio to set pin GPIO4 to be used as an output (using the commands INP_GPIO(4); OUT_GPIO(4); as described on page 11). Then in it uses GPIO_SET0 and GPIO_CLR0 (described on page 17) to set GPIO4 high then low 10 times. Note: the test asks which driver should be tested, but it only uses this information to print out the connections that need to be made. Otherwise it ignores your response. 22 Motor Controller The Gertboard has a position for a L6203 (Miniwatt package) motor controller. The motor controller is for brushed DC motors. The controller has two input pins, A and B (labelled MOTA and MOTB on the board). The pins can be driven high or low, and the motor responds according to the table below. The speed of the motor can be controlled by applying a pulse-width-modulated (PWM) signal to either the A or B pin. A B Motor action 0 0 no movement 0 1 rotate one way 1 0 rotate opposite way from above 1 1 no movement Table 3: Truth table showing the behaviour of the motor controller under different logic combinations. The motor controller IC has internal temperature protection. Current protection is provided by a fuse on the Gertboard. The motor controller is in the schematics on page A-4. On the Gertboard building block diagram on page 7, the area containing the components for the motor controller are outlined in purple. The motor controller and screw terminals are near the top of the board, and there are two pins for the control signals in a small header just above GP4 and GP1 in header J2. The MOTA and MOTB pins just above header J2 are the inputs to the motor controller – these are digital signals (low and high). The screw terminals at the top of the board labelled MOTA and MOTB are the outputs of the motor controller: they actually provide the power to the motor. The motor will probably need more power (a higher voltage or current) than that provided by the Gertboard. The screw terminals at the top labelled MOT+ and ⊥ allow the connection of an external power supply to provide this: the motor controller directs this power to the MOTA and MOTB screw terminals, modulating it according to the MOTA and MOTB inputs near J2. If you just want to turn the motor off and on, in either direction, this is achieved by simply choosing two of the GPIO pins and installing straps between them to the MOTA and MOTB motor controller inputs. Then, to control the motor, the pins are set high or low per the table 3 above. To control the speed of the motor however, pulse width modulation (PWM) is required. This is a device that outputs a square wave that flips back and forth from on to off very rapidly, as in the diagram below: Fig. 17: An example of a PWM output. In this example the output is neither on nor off all the time. In fact, here it is on for 50% of the time, and is therefore said to have a duty cycle of 50%. 0 1 23 With a PWM, you can control the amount of time the output is high vs. when it is low. This is called the duty cycle and is expressed as a percentage. The diagram above shows a 50% duty cycle; the one below is 25%. Fig. 18: In this PWM example, the duty cycle is 25%. There is a PWM in the BCM2835 (the Raspberry Pi processor), and it’s output can be accessed via GPIO18 (it is alternate function 5). If this is connected to one of the motor controller inputs (MOTA has been used in our motor test), and set the other motor controller input (MOTB in our test) to a steady high or low, the speed and direction of the motor can be controlled. Fig. 19: The motor direction is set by MOTB. Whilst MOTA has a duty cycle of 25%, the motor only receives power when MOTA and MOTB are different, thus it receives power for 75% of the time. For example, in the diagram above we are alternating between A low/B high and A high/B high (the second and fourth lines of the table above). When A is low, the motor will receive power making it turn one way; when A is high it will not receive power. The end result for the 25% duty cycle shown here is that the motor will turn one way at roughly ¾ speed. Fig. 20: In this example, the truth table predicts that the motor will run in the opposite direction at around 25% speed. If on the other hand you set MOTB low, as in the diagram above, then when A is high the motor will receive power making it turn in the other direction, and when A is low the motor will not receive power. The result for the 25% duty cycle is that it will turn in the other direction at about ¼ speed. Testing the motor controller The PWM is controlled by a memory map, like the GPIO and SPI bus. This memory map is part of the setup_io function in gb_common.c, so that is whether the PWM is used or not. Further setup code is found in, gb_pwm.c, with an associated header file gb_pwm.h. The function setup_pwm in gb_pwm.c sets the speed of the PWM clock, and sets the maximum value of the PWM to 1024: this is the value at which the duty cycle of the PWM will be 100%. It also makes sure that the PWM is off. The two routines set_pwm0 and force_pwm0 set the value that controls the duty cycle for the PWM. set_pwm0 sets the value (first checking that it is between 0 and 1024), but as there are only certain points in the PWM cycle where a new value is picked up, if a second value is written again quickly the first will have no effect. The force_pwm0 routine takes two arguments, a new value and a new mode. It disables the PWM, then sets the value, then re-enables it with the given mode setting, 0 1 0 1 0 1 MOTA MOTB 0 1 0 1 MOTA MOTB 24 with delays in strategic places to allow the new values to be picked up. The pwm_off routine simply disables the PWM. The test program for the motor controller is called motor. To set up Gertboard for this, connect GP17 in J2 to the MOTB pin (the MOTB pin in the 2-pin header above GP1 and GP4, not the one at the top of the board), and GP18 to MOTA in that little header. The motor leads need to be connected to the MOTA and MOTB screw terminals at the top of the board, and the power supply for the motor needs to be connected to the MOT+ and ⊥ screw terminals. This is shown below. Fig. 20: The wiring diagram for the test program motor. The code for the motor program is in motor.c. In the main routine, first the connections that must be made on the board to run this program are printed out, then call setup_io to get the GPIO interface ready for use. setup_gpio is then called to set GPIO18 up for use as the PWM output and GPIO17 up for normal output. For the latter, both INP_GPIO and OUT_GPIO are used, see page 11 for more info. To set up GPIO18, first use INP_GPIO(18) to activate the pin. One of the alternate functions for GPIO18 is to act as the output for the PWM; this is alternative 5. Thus use the macro SET_GPIO_ALT(18, 5) to select this alternate use of the pin. (See table Table 6-31 from the BCM2835 datasheet, or the online version at http://elinux.org/RPi_BCM2835_GPIOs, for more details about alternative functions for the GPIO pins. A summary of the alternate function of GPIO pins used on the Gertboard, see the table on page 9.) 25 We set the output of GPIO17 low (to make sure that the motor doesn’t turn) and then initialize the PWM by calling setup_pwm. We enable the PWM by setting the mode to PWM0_ENABLE using force_pwm0. Since GPIO17 (motor controller B input) is set low, when the duty cycle on the PWM (motor controller A input) is high enough, the motor will turn the ‘opposite way’ as described in the motor table on page 22. A loop now starts where the PWM is started, first with a very low duty cycle (because the value passed to set_pwm0 is low), then gradually increasing this to the maximum (which is set to 0x400 – 1024 – in setup_pwm). Then the value sent to the PWM is decreased to slow the motor down. Then GPIO17 is set high, so that the motor will get power on the low phase of the PWM signal. The PWM is re-enabled with the mode PWM0_ENABLE|PWM0_REVPOLAR. The reverse polarization flag flips the PWM signal, so that a low value sent to the PWM results in a signal that is high most of the time (rather than low most of the time). That way the same code can be used to slowly ramp up the speed of the motor (but in the ‘one way’ direction as in the table on page 22), then slow it down again. Finally the PWM is switched off, and the GPIO interface is closed down. Digital to Analogue and Analogue to Digital Converters In the Gertboard building blocks diagram on page 7, the components implementing the converters are outlined in orange. Both the analogue converter (D/A) and analogue to digital converter (A/D) are 8- pin chips from Microchip. The D/A is U6 (above) and the A/D is U10 (below). Each supports 2 channels. Both use the SPI bus to communicate with the Raspberry Pi. The SPI pins on the two chips are connected to the pins labelled SCLK, MOSI, MISO, CSnA, and CSnB in the header just above J2 on the board (thus in the building blocks diagram, these pins are also outlined in orange). SCLK is the clock, MOSI is the output from the RPi, and MISO is the input to the RPi. CSnA is the chip select for the A/D, and CSnB is the chip select signal for the D/A (the ‘n’ in the signal name means that the signal is ‘negative’, thus the chip is only selected when the pin is low). Both A/D and D/A chips have a 10K pull-up resistor on their chip-select pins, so the devices will not be accessed if the chips select pins are not connected. The SPI pins are conveniently located just above GP7 to GP11 in header J2, because one of the alternate functions of these pins is to drive the SPI signals. For example, the “ALT0” (alternative 0) function of GPIO9 is SPI0_MISO, which is why the pin labelled MISO is just about the pin labelled GP9. Thus to use the A/D and D/A, simply put jumpers connecting pins GP7 to GP11 to the SPI pins directly about them (although technically you only need CSnA for the A/D and CSnB for the D/A). In the schematics, the D/A and A/D converts are on page A-6. Digital to analogue converter The Gertboard uses a MCP48xx digital to analogue converter (D/A) from Microchip. The device comes in three different types: 8, 10 or 12 bits. It is likely that MCP4802, the 8 bit version, will be used, but if higher resolutions are needed, it can be replaced with the MCP4812 (10 bits) or MCP4822 (12 bits). These chips are all pin-compatible and are written to in the same way. In particular, the routine that writes to the D/A assumes that writes are in 12 bits, so it is important that the value is selected appropriately (details are below in the “Testing the D/A and A/D” section). The maximum output voltage of the D/A – the output voltage when you send an input of all 1s – is 2.04V. 26 The analogue outputs of the two channels go to pins labelled DA0 (for channel 0) and DA1 (for channel 1) in the J29 header. Just next to these pins are ground pins (GND) to provide a reference. Analogue to Digital converter The Gertboard uses a MCP3002 10-bit analogue to digital converter from Microchip. It supports 2 channels with a sampling rate of ~72k samples per second (sps). The maximum value (1023) is returned when the input voltage is 3.3V. The analogue inputs for these two channels are AD0 (for channel 0) and AD1 (for channel 1) in the J28 header. Just next to these pins are ground pins (GND) to provide a reference. Testing the D/A and A/D Since the D/A and A/D converters both use the SPI bus, the common SPI bus code has been placed into a separate file, gb_spi.c. There is also an associated header file, gb_spi.h, which contains many macros and constants needed for interacting with the SPI bus, as well as the declarations for the functions in gb_spi.c. These functions are setup_spi, read_adc, and write_dac. setup_spi sets the clock speed for the bus and clears status bits. read_adc takes an argument specifying the channel (should be 0 or 1) and returns an integer with the value read from the A/D converter. The value returned will be between 0 and 1023 (i.e. only the least significant 10 bits are set), with 0 returned when the input pin for that channel is 0V and 1023 returned for 3.3V. The write_dac routine takes two arguments, a channel number (0 or 1) and a value to write. The value written requires some explanation. The MCP48xx family of digital to analogue converters all accept a 12 bit value. The MCP4822 uses all the bits; the MCP4812 ignores the last two; and the MCP4802 (which is probably the one you are using) ignores the last four. Since you could use any of those chips on the Gertboard, write_dac is written in so that it will work with all three, so it simply sends to the D/A the value it was given. If Gertboard is fitted with the MCP4802, it can only handle values between 0 and 255, but these must be in bits 4 through 11 (assuming the least significant bit is bit 0) of the bit string it is sent. Thus if the desired number to be sent to the D/A is between 0 and 255, it must be multiplied by 16 (which effectively shifts the information 4 bits to the left) before sending this value to write_dac. The value on the output pin, Vout, is given by the following formula (assuming the 8-bit MCP4802):  =  256 × 2.048 To test the D/A, a multimeter is required. The test program for this is dtoa. To set up Gertboard for this test, jumpers are placed on the pins GP11, GP10, GP9, and GP7 connecting them to the SPI bus pins above them. Attach the multimeter as follows: the black lead needs to be connected to ground. You can use any of the pins marked with ⊥ or GND for this. The red lead needs to be connected to DA0 (to test the D/A channel 0 which is shown below) or DA1 (for channel 1). Switch the multimeter on, and set it to measure voltages from 0 to around 5V. 27 Fig. 21: The wiring diagram required to measure the output from the D to A converter fitted to the Gertboard whilst running the test program dtoa. The dtoa program first asks which channel to use and prints out the connections needed to make on Gertboard to run the program. Then it calls setup_io to get the GPIO ready to use, then calls setup_gpio to choose which pins to use and how to use them. In setup_gpio, as usual INP_GPIO(n) (where n is the pin number) is used to activate the pins. This also sets them up to be used as inputs. They should however, be used as an SPI bus, which is one of the alternative functions for these pins (it is alternate 0). Thus we use SET_GPIO_ALT(n, a) (where n is the pin number and a is the alternate number, in this case 0) to select this alternate use of the pins. Then the program sends different values to the D/A and asks for real verification, using the multimeter, that the D/A converter is generating the correct output voltage. The test program for the A/D is called atod. To run this test a voltage source on the analogue input is required. This is most easily provided by a potentiometer (a variable resistor). The two ends of the potentiometer are connected, one side to high (3.3V, which you can access from any pin labelled 3V3) and the other to low (GND or ⊥), and the middle (wiper) part to AD0 (for channel 0 as shown below) or AD1 (for channel 1). To use the SPI bus jumpers should be installed on the pins GP11, GP10, GP9, and GP8 connecting them to the SPI bus pins above them. 28 Fig. 22: Wiring diagram showing how the Gertboard is connected to verify that the A/D converter is working properly, using the test program atod. The atod program first asks which channel should be used and prints out the connections required on Gertboard to run the program. Then it calls setup_io to get the GPIO ready, then calls setup_gpio to choose which pins will be used, and how they will be used. The setup_gpio used in atod works the same way as the one in dtoa (except for activating GPIO8 instead of GPIO7). Then atod repeatedly reads the 10 bit value from the A/D converter and prints out the value on the terminal, both as an absolute number and as a bar graph (the value read is divided by 16, and the quotient is represented as a string of ‘#’ characters). One thing to be aware of is that even if the potentiometer is not moved, exactly the same result may not appear on successive reads. With 10 bits of accuracy, it is very sensitive, and even the smallest changes, such as house current running in nearby wires, can affect the value read. Even without a multimeter or a potentiometer, it is still possible to test the A/D and D/A by sending the output of the D/A to the input of the A/D. The test that does this is called dad, for digitalanalogue- digital. To set the Gertboard up for this test, hook up all the SPI bus pins (connecting GP11 though GP7 with jumpers to the pins above them) and put a jumper between pins DA1 and AD0, as in the diagram below. 29 Fig. 23: The wiring diagram for an alternative method of testing the A/D and D/A converters together, without the aid of a multimeter and potentiometer. The dad test sends 17 different digital values to the D/A (0 to 255 in even jumps, then back down to 0). The resulting values are then read in from the A/D. Both the original digital values sent and the values read back are printed out, as is a bar graph representing the value read back (divided by 16 as in atod). The bar graph printed out should be a triangle shape: the lines will start out very short, then get longer and longer as larger digital values are read back, then will get shorter again. ATmega device The Gertboard can hold an Atmel AVR microcontroller, a 28-pin ATmega device, at location U8 on the lower left of the board. This can be any of the following: ATmega48A/PA, 88A/PA, 168A/PA or 328/P in a 28-pin DIP package. The device has a 12MHz ceramic resonator attached to pins 9 and 10. All input/output pins are brought out to header J25 on the left edge of the board. There is a separate 6- pin header (J23 on the left side of the board) that can be used to program the device. The PD0/PD1 pins (ATmega UART TX and RX) are brought out to pins placed adjacent to the Raspberry Pi UART pins so you only need to place two jumpers to connect the two devices. Note that the ATmega device on the Gertboard operates at 3.3Volts. That is in contrast to the ‘Arduino’ system which runs at 5V. It is also the reason why the device does not have a 16MHz clock. In fact at 3V3 the maximum operating frequency according to the specification is just under 12MHz. Warning: many of the Arduino example sketches (programs) mention +5V as part of the circuit. Because we are running at 3.3V, you must use 3.3V instead of 5V wherever the latter is mentioned. If you use 5V you risk damaging the chip. The ATmega device is in the schematics on page A-6. 30 Programming the ATmega Programming the ATmega microcontroller is straightforward once you have all the infrastructure set up, but it requires a fair bit of software to be installed on your Raspberry Pi. We are immensely grateful to Gordon Henderson, of Drogon Systems, for working out what needed to be done and providing the customized software. Using his system, you can use the Arduino IDE (Integrated Development Environment) on the Raspberry Pi to develop and upload code for the ATmega chip on the Gertboard. The Atmel chips most commonly used on the Gertboard are the ATmega168 and ATmega328, so Gordon assumes you have one of these. To use Gordon’s system, first you need to install the Arduino IDE. Then you download a custom version of avrdude, which allows you to program the AVR microcontroller using the SPI bus. (GPIO pins GPIO7 through GPIO11 can be used as a SPI bus.) Then you have to edit various configuration files to fully integrate the Gertboard into the Arduino IDE. Finally, you have to program the ‘fuses’ on the ATmega chip. Happily, Gordon has written some scripts to do all this for you. Full instructions, scripts, and the modified avrdude are available at: https://projects.drogon.net/raspberry-pi/gertboard/ We assume now that you have downloaded and successfully installed and configured the Arduino IDE, as described above, and we proceed from there. To get going with the ATmega chip, start up the Arduino IDE. This should be easy: if the installation of the Arduino package was successful, you will have a new item “Arduino IDE” in your start menu, under “Electronics”. The exact version of the IDE you get with depends on the operating system you are using. The version number is given in the title bar. The Debian squeeze package is version 0018, while the wheezy package is 1.0.1. First you will need to configure the IDE to work with the Gertboard. Go to the Tools > Board menu and choose the Gertboard option with the chip you are using (ATmega168 or ATmega328). For IDE version 1.0.1, you will also have go to the Tools > Programmer menu and choose “Raspberry Pi GPIO”. Arduino pins on the Gertboard All the input and output pins of the ATmega chip are brought out to header J25 on the left edge of the board. They are labelled PCn, PDn, and PBn, where n is a number. These labels correspond to the pinout diagrams of the ATmega168/328 chips. However, in the Arduino world, the pins of the chips are not referred to directly. Instead there is an abstract notion of digital and analogue pin numbers, which is independent of the physical devices. This allows code written for one Arduino board to be easily used with another Arduino board, which may have a chip with a different pinout. Thus, in order to use your Gertboard with the Arduino IDE, you need to know how the Arduino pin number relates to the labels on your Gertboard. The table below shows this correspondence (“GB” means Gertboard). 31 Arduino Pin GB pin Arduino Pin GB pin Arduino Pin GB pin digital 0 PD0 digital 7 PD7 analogue 0, A0 PC0 digital 1 PD1 digital 8 PB0 analogue 1, A1 PC1 digital 2 PD2 digital 9 PB1 analogue 2, A2 PC2 digital 3 PD3 digital 10 PB2 analogue 3, A3 PC3 digital 4 PD4 digital 11 PB3 analogue 4, A4 PC4 digital 5 PD5 digital 12 PB4 analogue 5, A5 PC5 digital 6 PD6 digital 13 PB5 Table 4: The relationship between pins on Arduino and pins on the Gertboard. In both versions of the Arduino IDE, digital pins are referred to in the code with just a number. For example digitalWrite(13, HIGH); will set pin 13 (PB5 on the Gertboard) to logical 1. (In the Arduino world, LOW refers to logical 0, and HIGH refers to logical 1.) The analogue pins are handled slightly differently. In version 0018, analogue pins are referred to simply by number, so whether 0 refers to PD0 (a digital pin) or PC0 (an analogue pin) depends on the context. The command value = digitalRead(0); will cause a read from digital 0 (PD0), and value will be assigned LOW or HIGH, while the command value = analogRead(0); will cause a read from analogue 0 (PC0), and value will be assigned a number between 0 and 1023, as the A/D converters in the ATmega chip return 10 bit values. In version 1.0.1, however, although numbers 0 through 5 still work to specify analogue pins, they are referred to in the examples as A0 to A5, and this seems to be the preferred style now. So to read from analogue pin 0 you would use the command value = analogRead(A0); A few sketches to get you going A good first sketch to try is Blink, which makes an LED turn on and off. With version 0018 of the IDE it’s in the File > Examples > Digital menu; in 1.0.1 it’s in the File > Examples > Basics menu. When you select this, a new window pops up with the Blink code. There are only two functions in the code, setup and loop. These are required for all Arduino programs: setup is executed once at the very beginning, and loop is called repeatedly, as long as the chip has power. Note that you do not need to provide any code to call these functions. 32 The modified avrdude that you downloaded uses the SPI bus to upload the code to the ATmega chip, so you need to connect the GPIO pins used for the SPI bus to the 6-pin header J23, as in the diagram below. Here you are simply connecting the SPI pins in the GPIO to the corresponding SPI pins in the header. The arrangement of the pins in J23 is shown in the schematics, on page A-6. Fig. 23: The wiring diagram for downloading sketches to the ATmega microprocessor. To upload your sketch to the chip in Arduino IDE version 0018, either choose File > Upload to I/O Board option, or click the icon with the right-pointing arrow and the array of dots. With version 1.0.1 choose File > Upload Using Programmer. It will take a bit of time to compile and upload, and then your sketch is running. But nothing is happening! On most Arduino boards, pin 13 (the digital pin used by this sketch) has an LED attached to it, but not the Gertboard. You have to wire up the LED yourself. Looking at the table above, we see that digital pin 13 is labelled PB5 on the Gertboard, so you need to connect PB5 to one of the I/O ports. Looking back to the port diagram on page Error! Bookmark not defined., we need to connect it to the point labelled ‘I/O’ on that diagram. Recall that the pins corresponding to these points are BUF1 to BUF12 in the (unlabeled) single row header at the top of the Gertboard. So if you connect PB5 to BUF1, as below, the first LED will start to blink. 33 Fig. 24: Wiring diagram for the sketch Blink. Note that in this diagram we have not shown the connections to the SPI pins. Once you have uploaded the code, you no longer need them and can remove the straps. On the other hand, if you want you can leave them in place, and this is a good idea if you are planning on uploading some other sketches later. Let’s look at another fairly simple sketch called Button, located under File > Examples > Digital menu in both 0018 and 1.0.1. The comments at the beginning of the sketch read The circuit: * LED attached from pin 13 to ground * pushbutton attached to pin 2 from +5V * 10K resistor attached to pin 2 from ground Assuming that you have Blink working, your LED is already wired up, but what about the button? As mentioned above, since the ATmega chip on the Gertboard runs at 3.3V, we must replace the 5V with 3.3V. So they suggest using a circuit like the one below, where the value read at pin 2 is logical 0 if the button is not pressed (due to the 10K pull-down resistor) and logical 1 if the button is pressed. Fig. 25: Suggested switch circuit for use with Button sketch. However, the buttons on the Gertboard are used like this: 34 Fig. 26: Circuit actually in use on the Gertboard, showing an additional 1k resistor to protect the input to BCM2835. The 1K resistor between the pushbutton and the ‘Raspi’ point is to protect the BCM2835 (the processor on the Raspberry Pi) if you accidentally set the GPIO pin connected to ‘Raspi’ to output instead of input. The circuit to the right of the ‘Raspi’ point happens on the Raspberry Pi: to use the push button we set a pull-up (shown as a resistor in the circuit above) on the pin so that the value read is logical 1 when the button is not pressed (see page 16). The Gertboard buttons are connected directly to ground so they cannot be made to read logic 1 when pressed. If you are want to use a Gertboard button with an Arduino sketch that assumes that the button reads 1 when pressed, the best approach is to modify the sketch, if needed, so that it will invert the value it reads from the button. For the pull-up, we can take advantage of the pull-ups in the ATmega chip. To do this, find the lines below in the sketch // initialize the pushbutton pin as an input: pinMode(buttonPin, INPUT); and insert the following two lines after them: // set pullup on pushbutton pin digitalWrite(buttonPin, HIGH); To invert the value read from the button, find the line below: buttonSate = digitalRead(buttonPin); and insert a ! (the negation operator in C) as follows: buttonSate = !digitalRead(buttonPin); Now upload this modified sketch, as described for Blink. We still need to attach Arduino digial pin 2 (PD2 on the Gertboard, as you can see from the table) to a button, say button 3.The ‘Raspi’ pin in the circuit diagram above, which is where we want to read the value, is in the J3 header. 35 Fig. 27: Wiring diagram showing the additional strap necessary for button operation for the sketch Button. When you have done this, the first LED will be on when the third button is pressed, and off when the third button is up. Now let’s try using an analogue pin. Find the AnalogInput sketch under File > Examples > Analog (in both versions 0018 and 1.0.1). This reads in a value from analogue input 0 (which has already been converted by the internal A/D to a value between 0 and 1023), then uses that number as a delay between turning an LED on and off. Thus, the lower the voltage on the analogue pin, the faster the LED flashes. To run this example, you’ll need a potentiometer. The one used to test the A/D will work fine here. The comments for AnalogInput say to connect the potentiometer so that the wiper is on analogue pin 0 (PC0 on the Gertboard) and the outer pins are connected to +5V and ground. As above, you must use 3.3V instead of 5V as we’re running the chip at 3.3V here. The diagram below shows how to connect up the Gertboard to make this sketch work after it is uploaded. 36 Fig. 28: Wiring diagram for the AnalogInput sketch. Minicom Some of the Arduino sketches involve reading or writing data via the serial port, or UART. An example is AnalogInSerial under File > Examples > Analog for version 0018. In version 1.0.1, this same example has been renamed AnalogReadSerial and is under File > Examples > Basics. This sketch sets the baud rate to 9600, then repeatedly reads in a value from analogue pin 0 and prints this value to the serial port (also called UART). The value read in is between 0 and 1023; 0 means that the input pin is at 0V and 1023 means that it is at the supply voltage (3.3V for the Gertboard). To set up your Gertboard for this sketch, you need the potentiometer attached to analogue input 0 as described above. In addition you need to connect the ATmega chip’s UART pins to the Raspberry Pi. Digital pin 0 (PD0 on the Gertboard) is RX (receive), and digital pin 1 (PD1 on the Gertboard) is TX (transmit). These signals are also brought out to the pins labelled MCTX and MCRX just above the GP15 and GP14 pins in header J2 on the Gertboard. Thus you can use two jumpers to attach the ATmega’s TX to GP15 and RX to GP14, as shown below. 37 Fig. 29: Wiring diagram for the sketch AnalogInSerial/AnalogReadSerial. GPIO14 and GPIO15 are the pins that the Raspberry Pi uses for the UART serial port. If you refer back to the table of alternate functions on page 9, you will see that GPIO14 is listed as TX and GPIO15 as RX. This is not a mistake! This swapping is necessary: the data that is transmitted by the ATmega is received by the Raspberry Pi, and vice versa. Now, how to we get the Raspberry Pi to read and show us the data that the ATmega is sending out on the serial port? There is a button labelled Serial Monitor on the toolbar of the Arduino IDE, but it doesn’t work on the Raspberry Pi. It assumes that you are talking to an Arduino board over USB, not talking to a Gertboard over GPIO. The easiest way to retrieve this data is to use the minicom program. You can install this easily by typing into a terminal this command: sudo apt-get install minicom You can use menus to configure minicom (by typing minicom –s). Alternatively, included with the Gertboard software is a file minirc.ama0 with the settings you need to read from the GPIO UART pins at 9600 baud. Copy this file (which was provided by Gordon Henderson) to /etc/minicom/ (you’ll probably need to sudo this) and invoke minicom by typing sudo minicom ama0 Now if you upload the sketch to the ATmega chip, you should see the value from the potentiometer displayed in your minicom monitor. These examples have only just scratched the surface of the wonderful world of Arduino. Check out http://arduino.cc/en/Tutorial/HomePage for much, much more. 38 Combined Tests This section shows some examples of using more than one building block at a time. A/D and motor controller In the potmot (for potentiometer-motor) test we use a potentiometer (“pot”) connected to the analogue to digital converter (A/D) to get an input value, and this value is used to control the speed and direction of the motor. It is set up so that at one extreme, the motor is going at top speed, and as you move the wiper towards the middle it slows, at the middle the motor stops, and as you continue to move the wiper along, the motor speeds up again but in the other direction. The main routine for this is in potmot.c. Functions from gb_spi.c and gb_pwm.c are used to control the SPI bus (for reading the A/D) and the pulse width modulator (for controlling the speed of the motor). To wire up the Gertboard for this example, you combine the wiring for the A/D and motor tests. Jumpers connect GP8 to GP11 to the pins directly above them to allow us to control the SPI bus using GPIO8 to GPIO11. You must attach your potentiometer to the AD0 input. GPIO17 controls the motor B input and GPIO18 controls the motor A input using the pulse width modulator (PWM). Thus GP17 must be connected via a strap to MOTB, and GP18 must be connected to MOTA. The motor and its power source must be connected to the screw terminals in J19 at the top of the board. See the wiring diagram below. Fig. 30: Wiring diagram for the combined potmot test. + - your power source goes here M 1 2 3 39 In the main routine for potmot, first we print to the terminal the connections that need to be made on the Gertboard to run this example, then we call setup_io to set up the GPIO ready for use. Then we call setup_gpio to set the GPIO pins the way we want them. In this, we set up GPIO8 to GPIO11 to use the SPI bus using INP_GPIO and SET_GPIO_ALT as described in the section on A/D and D/A converters (page 27). GPIO17 is set up as an output (using INP_GPIO and OUT_GPIO), and GPIO18 is set up as a PWM using as INP_GPIO and SET_GPIO_ALT as described in the section on the motor controller (page 24). Back in main, we call setup_spi and setup_pwm to get the SPI bus and PWM ready for use and get the motor ready to go. Then we repeatedly read the A/D and set the direction and speed of the motor depending on the value we read. Lower A/D values (up to 511 – recall that the A/D chip used returns a 10 bit value so the maximum will be 1023) result in the motor B input being set high, and thus the motor goes in the “rotate one way” as in the motor controller table on page 22. Confusingly, this motor direction is called “backwards” in the comments of the program! Higher A/D values (512 to 1023) result in the motor B input being set low, and the motor goes in the “rotate opposite way” direction. This is called “forwards” in the comments of the program. Simple arithmetic is used to translate A/D values near 511 to slow motor speeds and A/D values near the endpoints of the range (0 and 1023) to fast motor speeds by varying the value sent to the PWM. Decoder The decoder implemented by the decoder program takes the three pushbuttons as input and turns on one of 8 LEDs to indicate the number with the binary encoding given by the state of the buttons. Switch S1 gives the most significant bit of the number, S2 the middle bit, and S3 the least significant bit. For output, the LED D5 represents the number 0, D6 represents 1, and so on, so D12 represents 7. Recall that the pushbuttons are high (1) when up and low (0) when pushed, so LED D12 is lit up when no buttons are pressed (giving binary 111 or 7), D6 is lit up when S1 and S2 are pressed (giving binary 001), etc. There is quite a bit of wiring for this one, as we are using all but one of the I/O ports.GPIO25 to GPIO23 are reading the pushbuttons, so you need to connect GP25 to B1, GP24 to B2, and GP23 to B3. The 8 lowest-numbered GPIO pins are used with I/O ports 5 to 12, so you need to connect GP11 to B5, GP10 to B6, GP9 to B7, GP8 to B8, GP7 to B9, GP4 to B10, GP1to B11, and GP0 to B12. In addition, since we are using I/O ports 5 to 12 for output, you need to install all the out jumpers for buffer chips U4 and U5 (recall that the out jumpers are those above the chips). 40 Fig. 31: Wiring diagram for the decoder test. In the main routine for decoder, as always we start out by printing out to the terminal the connections that need to be made on the Gertboard. Then we call setup_io to set up the GPIO ready for use. Then we call setup_gpio to set GPIO25 to 23 for use with the pushbuttons (by selecting them for input and enabling a pull-up, as described on page 16) and to set GPIO11 to GP7, GPIO4, GPIO1, and GPIO0 up as outputs (as described on page 11). Then we enter a loop where we read the state of the pushbuttons and light up the LED corresponding to this number (after turning off the LED previously set). We turn the LEDs on and off using GPIO_SET0 and GPIO_CLR0 as described on page 17. For More Information For further information, the datasheet for the processor can be found here: http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf Appendix A: Schematics We have included the schematics for the Gertboard in the pages that follow. They are numbered A-1, A-2, etc. The page number is located in the lower left hand of each page. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A in gnd out Front 1 2 3 TO220 Not used. Do not install! Do not use LDxxx series. They have a different pin-out! GPIO9 GPIO22 GPIO21 GPIO1 GPIO11 GPIO17 GPIO4 GPIO10 GPIO14 GPIO15 GPIO18 GPIO23 GPIO24 GPIO25 GPIO8 GPIO7 GPIO0 GPIO0 GPIO1 GPIO4 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO14 GPIO15 GPIO17 GPIO18 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 3V3_RASP 5V_RASP 3V3_RASP 3V3 5V_RASP 3V3 3V3 MOTOR_A MOTOR_B BUF_1 BUF_2 BUF_4 BUF_3 BUF_6 BUF_7 BUF_8 BUF_5 RELAY_1 RELAY_2 RELAY_3 RELAY_4 BUF_9 BUF_12 BUF_10 BUF_11 RELAY_5 RELAY_6 SCLK MOSI MISO CSnA CSnB MC_TX MC_RX Title Size Document Number Rev Date: Sheet of - 3 Gertboard A4 1 6 R1 10K-0805 J4 CON6 1 2 3 4 5 6 J2 CON17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 D20 ~1.5A MH1 HOLE_M3 J5 CON2 1 2 C6 100nF-0805 MH2 HOLE_M3 C3 100nF-0805 R2 10K-0805 U2 REG78xx In 1 Gnd 2 Out 3 J64 CON2 1 2 J11 HEADER 5 1 2 3 4 5 J3 CON12 1 2 3 4 5 6 7 8 9 10 11 12 U1 REG3v3 In 1 Gnd 2 Out 3 C2 100nF-0805 + C5 10uF-1206 J7 CON3 1 2 3 MH4 HOLE_M3 J9 CON3 1 2 3 J1 CON26A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 + C1 10uF-1206 + C4 100uF-CX02-C MH3 HOLE_M3 C7 100nF-0805 J8 CON3 1 2 3 J24 CON2 1 2 A-1 5 5 4 4 3 3 2 2 1 1 D D C C B B A A BUF1 BUF2 BUF6 BUF5 BUF10 BUF9 BUF3 BUF4 BUF8 BUF11 BUF12 BUF2 BUF12 BUF1 BUF6 BUF5 BUF11 BUF7 BUF4 BUF9 BUF3 BUF8 BUF10 BUF7 3V3 3V3 3V3 3V3 BUF_1 BUF_3 BUF_4 BUF_8 BUF_5 BUF_6 BUF_7 BUF_12 BUF_9 BUF_10 BUF_11 BUF_2 BUF_3 BUF_2 BUF_1 Title Size Document Number Rev Date: Sheet of - 3 Gertboard A4 2 6 P4 CON2 1 2 P11 CON2 1 2 U4 74xx244 20 1 19 2 4 6 8 18 14 16 12 9 7 5 3 10 11 13 15 17 RN7B 1k 4 3 P23 CON2 1 2 RN5B 1k-10k 4 3 P1 CON2 1 2 D10 LED P12 CON2 1 2 P3 CON2 1 2 D12 LED D6 LED D8 LED S3 Switch 1 2 3 4 S1 Switch 1 2 3 4 P8 CON2 1 2 RN2 1K_RESN4X1 1 2 3 4 5 D1 LED RN4C 1k-10k 6 5 P13 CON2 1 2 D9 LED RN7A 1k 2 1 C9 100n-0805 RN5A 1k-10k 2 1 D5 LED P17 CON2 1 2 P18 CON2 1 2 P15 CON2 1 2 P6 CON2 1 2 P14 CON2 1 2 P24 CON2 1 2 RN5C 1k-10k 6 5 S2 Switch 1 2 3 4 D11 LED RN7D 1k 8 7 D7 LED P2 CON2 1 2 P5 CON2 1 2 RN3 1K_RESN4x1 1 2 3 4 5 RN6D 1k-10k 8 7 RN6B 1k-10k 4 3 P20 CON2 1 2 C10 100n-0805 P9 CON2 1 2 P19 CON2 1 2 RN4A 1k-10k 2 1 D3 LED RN4D 1k-10k 8 7 J10 CON24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 P10 24 CON2 1 2 RN6A 1k-10k 2 1 U3 74xx244 20 1 19 2 4 6 8 18 14 16 12 9 7 5 3 10 11 13 15 17 D4 LED RN1 1K_RESN4X1 1 2 3 4 5 C8 100n-0805 RN5D 1k-10k 8 7 RN4B 1k-10k 4 3 P7 CON2 1 2 RN6C 1k-10k 6 5 U5 74xx244 20 1 19 2 4 6 8 18 14 16 12 9 7 5 3 10 11 13 15 17 D2 LED P21 CON2 1 2 P22 CON2 1 2 P16 CON2 1 2 RN7C 1k 6 5 A-2 5 5 4 4 3 3 2 2 1 1 D D C C B B A A RELAY_PWR RELAY_6 RELAY_4 RELAY_2 RELAY_1 RELAY_5 RELAY_3 Title Size Document Number Rev Date: Sheet of - 3 Gertboard A4 3 6 J16 CON2 1 2 J13 CON2 1 2 8x U12 ULN2803A I1 1 I2 2 I3 3 I4 4 I5 5 I6 6 I7 7 I8 8 GND 9 Q1 18 Q2 17 Q3 16 Q4 15 Q5 14 Q6 13 Q7 12 Q8 11 COM 10 J12 CON2 1 2 J15 CON2 1 2 J17 CON2 1 2 J14 CON2 1 2 J6 CON2 1 2 A-3 5 5 4 4 3 3 2 2 1 1 D D C C B B A A motor power nets named to make high current MB MP MPC MA MGND 3V3 MOTOR_A MOTOR_B Title Size Document Number Rev Date: Sheet of - 3 Gertboard A4 4 6 C13 22n-0805 J20 CON2 1 2 F1 4A C11 100n-0805 R23 0.1-2512 C12 22n-0805 J19 CON4 1 2 3 4 U7 L6203-MW VREF 9 ENB 11 IN1 5 IN2 7 BOOT1 4 BOOT2 8 OUT1 3 OUT2 1 VSS 2 GND 6 Sense 10 A-4 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Patch area 3V3 3V3 3V3 of - 3 Gertboard A4 5 6 Title Size Document Number Rev Date: Sheet J37 CON2-DNF 1 2 J68 CON3-DNF 1 2 3 J42 CON2-DNF 1 2 J51 CON2-DNF 1 2 J70 CON2-DNF 1 2 J30 CON2-DNF 1 2 J36 CON2-DNF 1 2 J48 CON2-DNF 1 2 J50 CON2-DNF 1 2 J35 CON2-DNF 1 2 J55 CON3-DNF 1 2 3 J43 CON2-DNF 1 2 J32 CON2-DNF 1 2 J60 CON2-DNF 1 2 J62 CON3-DNF 1 2 3 J53 CON2-DNF 1 2 J69 CON3-DNF 1 2 3 J40 CON2-DNF 1 2 J56 CON3-DNF 1 2 3 J57 CON3-DNF 1 2 3 J38 CON2-DNF 1 2 J54 CON2-DNF 1 2 J26 CON2-DNF 1 2 J34 CON2-DNF 1 2 J47 CON2-DNF 1 2 J66 CON3-DNF 1 2 3 J67 CON3-DNF 1 2 3 J45 CON2-DNF 1 2 J41 CON2-DNF 1 2 J59 CON3-DNF 1 2 3 J39 CON2-DNF 1 2 J44 CON2-DNF 1 2 J49 CON2-DNF 1 2 J63 CON3-DNF 1 2 3 J52 CON2-DNF 1 2 J33 CON2-DNF 1 2 J46 CON2-DNF 1 2 J58 CON3-DNF 1 2 3 J27 CON2-DNF 1 2 J65 CON3-DNF 1 2 3 J31 CON2-DNF 1 2 J61 CON2-DNF 1 2 A-5 5 5 4 4 3 3 2 2 1 1 D D C C B B A A AD0 XTAL_IN DA0 DA1 AD1 XTAL_IN PD0 PD1 PD2 PD3 PD4 PC4 PC5 PB1 PB0 PC0 PC1 PC2 RC3 PD6 PD5 PD7 PC6/DBG/RESETn PC1 PC4 PC5 PC0 PC2 RC3 PD0 PD5 PD3 PD6 PD2 PD7 PD4 PD1 PB1 PB0 PC6/DBG/RESETn PD0 PD1 MC_SCK MC_MISO MC_MOSI MC_MOSI PB2 PB2 MC_MOSI MC_MISO MC_SCK MC_SCK MC_MISO 3V3 3V3 3V3 3V3 MISO MOSI MOSI SCLK SCLK MC_RX MC_TX CSnA CSnB Title Size Document Number Rev Date: Sheet of - 3 Gertboard A4 6 6 R4 0_0805 U8 ATmega328P PC6/Reset_n 1 PD0/RXD 2 PD1/TXD 3 PD2/INT0 4 PD4/XCK/T0 6 VCC 7 PB6/XTAL1 9 GND 8 PB7/XTAL2 10 PD5/OC0B/T1 11 PD6/OC0A/AIN0 12 PD7/AIN1 13 PB0/CLK0/ICP1 14 GND 22 AVCC 20 AREF 21 OC1A/PB1 SS_n/OC1B/PB2 15 MOSI/OC2A/PB3 16 MISO/OC2A/PB4 17 SCK/PB5 18 19 ADC0/PC0 ADC1/PC1 23 ADC2/PC2 24 ADC3/PC3 25 ADC4/SDA/PC4 26 ADC5/SCL/PC5 27 28 PD3/INT1/OC2B 5 J25 CONN PCB 20x2 2 4 6 8 10 12 14 16 18 20 24 22 26 28 30 32 34 36 38 40 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 D19 1N4001 J29 CON4A 1 3 2 4 U10 MCP4802 VDD 1 CSn 2 SCK 3 SDI 4 LDACn 5 VOUTB 6 VOUTA 8 VSS 7 J71 HEADER 1 1 J28 CON4A 1 3 2 4 C15 100nF-0805 U6 MCP3002 VDD 8 VSS 4 CH0 2 CH1 3 CSn/SHDN 1 CLK 7 DOUT 6 DIN 5 R24 0_0805 C17 100nF-0805 X1 Cer resonator 1 2 3 C19 100nF-0805 C20 100nF-0805 R34 10K-0805 J23 HEADER 3X2 2 4 6 1 3 5 C16 xxF-1206 A-6 User's Guide SBOU109A–May 2011–Revised October 2011 TMP006EVM User Guide and Software Tutorial This user's guide describes the characteristics, operation, and use of the TMP006EVM evaluation board. It discusses how to set up and configure the software and hardware, and reviews various aspects of the program operation. Throughout this document, the terms evaluation board, evaluation module, and EVM are synonymous with the TMP006EVM. This document also includes an electrical schematic, printed circuit board (PCB) layout drawings, and a parts list for the EVM. Contents 1 Overview ..................................................................................................................... 2 2 TMP006EVM Hardware Setup ............................................................................................ 3 3 TMP006EVM Hardware Overview ........................................................................................ 7 4 TMP006EVM Software Overview ......................................................................................... 8 5 TMP006EVM Software Use .............................................................................................. 11 List of Figures 1 Hardware Included with TMP006EVM Kit ............................................................................... 2 2 TMP006EVM Hardware Setup ............................................................................................ 3 3 TMP006EVM Board Block Diagram ...................................................................................... 4 4 TMP006 Test Board Schematic........................................................................................... 5 5 Typical Hardware Connection ............................................................................................. 7 6 Typical PC Behavior After Connecting TMP006EVM .................................................................. 8 7 TMP006EVM Software Installation Files................................................................................. 8 8 TMP006EVM Software Installation Launch.............................................................................. 9 9 TMP006EVM GUI Software Installation Prompts....................................................................... 9 10 TMP006EVM GUI Software Default Configuration.................................................................... 10 11 Hardware Error Message................................................................................................. 11 12 Read All Registers to Update Temperature............................................................................ 12 13 Make Changes to TMP006 Registers .................................................................................. 13 14 Write Changes to TMP006 Registers................................................................................... 14 15 TMP006EVM GUI Software Registers Tab ............................................................................ 15 16 Read Registers Continuously to Update Graphs...................................................................... 16 17 Enable Transient Correction Algorithm ................................................................................. 17 18 Start Data Logging ........................................................................................................ 18 19 Example .CSV Output File (Formatted and Displayed in Microsoft Excel®) ....................................... 19 List of Tables 1 TMP006EVM Kit Contents................................................................................................. 2 2 TMP006 Test Board Parts List ........................................................................................... 6 3 Signal Definitions for H1 (10-Pin Female Socket) on TMP006EVM Board ......................................... 6 4 Signal Definition for H2 (10-Pin FFC Connector) on TMP006EVM Board .......................................... 7 Excel, Microsoft, Windows are registered trademarks of Microsoft Corporation. SPI is a trademark of Motorola Inc. I2C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners. SBOU109A–May 2011–Revised October 2011 TMP006EVM User Guide and Software Tutorial 1 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Overview www.ti.com 1 Overview The TMP006 is an infrared thermopile sensor with digital output integrated circuit. This device measures the temperature of an object without making contact, making it ideal for many types of applications. The TMP006EVM is a platform for evaluating the performance of the TMP006 under various conditions. The TMP006EVM consists of two PCBs. One board, the SM-USB-DIG, communicates with the user’s computer, provides power, and sends and receives appropriate digital signals to communicate with the TMP006. The second PCB, the TMP006_Test_Board, contains the TMP006 as well as support and configuration circuitry. This document gives a general overview of the TMP006EVM, and provides a general description of the features and functions to be considered while using this evaluation module. 1.1 TMP006EVM Kit Contents Table 1 summarizes the contents of the TMP006EVM kit. Figure 1 shows all of the included hardware. Contact the Texas Instruments Product Information Center nearest you if any component is missing. It is highly recommended that you also check the TMP006 product folder on the TI web site at www.ti.com to verify that you have the latest versions of the related software. Table 1. TMP006EVM Kit Contents Item Quantity TMP006_Test_Board 1 SM-USB-DIG Board 1 USB Cable 1 CR-ROM with TMP006EVM GUI Software (not shown) 1 Figure 1. Hardware Included with TMP006EVM Kit 2 TMP006EVM User Guide and Software Tutorial SBOU109A–May 2011–Revised October 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com TMP006EVM Hardware Setup 1.2 Related Documentation from Texas Instruments The following documents provide information regarding Texas Instruments' integrated circuits used in the assembly of the TMP006EVM. This user's guide is available from the TI web site under literature number SBOU109A. Any letter appended to the literature number corresponds to the document revision that is current at the time of the writing of this document. Newer revisions may be available from the TI web site, or call the Texas Instruments' Literature Response Center at (800) 477-8924 or the Product Information Center at (972) 644-5580. When ordering, identify the document by both title and literature number. Related Documentation Document Literature Number TMP006 Product Data Sheet SBOS518 SM-USB-DIG_Platform User Guide SBOU0958 TMP006 Layout and Assembly SBOU108 Guidelines 2 TMP006EVM Hardware Setup Figure 2 shows the system setup for the TMP006EVM. The PC runs graphical user interface (GUI) software that communicates with the SM-USB-DIG over a USB connection. The SM-USB-DIG translates the USB commands from the PC into power, I2C™, SPI™, and general-purpose input/output (GPIO) commands for the TMP006_Test_Board. The TMP006EVM does not require any additional components to operate. Figure 2. TMP006EVM Hardware Setup SBOU109A–May 2011–Revised October 2011 TMP006EVM User Guide and Software Tutorial 3 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated TMP006 V Supply (Switched +3.3-V Power) DUT I C Interface 2 Serial Interface (SPI) 10-Pin Female SM-USB-DIG Connector DRDY LED Circuitry 10-Pin FFC Cable Connector TMP006EVM Hardware Setup www.ti.com 2.1 Theory of Operation for the TMP006 Test Board A block diagram of the TMP006 test board hardware setup is shown in Figure 3. The TMP006 Test Board contains connections for the power, I2C, SPI, and GPIO signals from the SM-USB-DIG. It also has a connector that allows other boards to be connected to the TMP006 Test Board to assist with calibrating the TMP006. Figure 3. TMP006EVM Board Block Diagram 4 TMP006EVM User Guide and Software Tutorial SBOU109A–May 2011–Revised October 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com TMP006EVM Hardware Setup Figure 4 shows the complete schematic of the TMP006 Test Board. The ferrite bead and input capacitor, FB1 and C1 respectively, filter the power coming into the TMP006 test board from the SM-USB-DIG. The I2C pull-up resistors, R3 and R4, and the DRDY pull-up, R5, are required for the open-drain outputs to operate correctly. The Q1 and R6 components drive the LED (D1) so current is not provided from the TMP006 that would cause the device to self-heat. Power, I2C, and SPI signals are provided to the calibration header, H2, for use with the TMP006 calibration tools. Figure 4. TMP006 Test Board Schematic SBOU109A–May 2011–Revised October 2011 TMP006EVM User Guide and Software Tutorial 5 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated TMP006EVM Hardware Setup www.ti.com 2.2 Bill of Materials for the TMP006 Test Board Table 2 lists the bill of materials for the TMP006EVM board. Table 2. TMP006 Test Board Parts List Qty RefDes Value Description Part Number MFR 1 C1 1μF Capacitor, Ceramic 1.0μF 16V X7R 10% 0603 C1608X7R1C105K TDK 1 C2 0.01μF Capacitor, Ceramic 10000pF 25V X7R 10% 0402 C1005X7R1E103K TDK 1 D1 LED Alingap Grn Wht Diff 0603SMD SML-LX0603SUGW- Lumex TR 1 FB1 Ferrite Bead 300Ω .2A 0402 74279272 Wurth 1 H1 Connector, Socket 50-Pl .050 R/A Sngl 851-43-050-20- Mill-Max 001000 1 H2 Connector, FPC/FFC 10-Pos .5mm Horz SMD FH12-10S-0.5SH(55) Hirose 1 Q1 MOSFET P-CH 50V 130mA SC70-3 BSS84W-7-F Diodes Inc 2 R1, R2 0Ω Resistor, 0.0Ω 1/16W 0402 SMD MCR01MZPJ000 Rohm 3 R3, R4, R5 47k Resistor, 47.0kΩ 1/16W 1% 0402 SMD MCR01MZPF4702 Rohm 1 R6 160Ω Resistor, 160Ω 1/16W 1% 0402 SMD MCR01MZPF1600 Rohm 1 U1 Infrared Sensor with Digital Interface TMP006 Texas Instruments 2.3 Signal Definition of H1 (10-Pin Female Socket) Table 3 identifies the signals connected to the H1 connector on the TMP006 Test Board. This summary also identifies the signals that are used with the TMP006EVM along with the respective signal names. Table 3. Signal Definitions for H1 (10-Pin Female Socket) on TMP006EVM Board Used on the TMP006 Test Board Pin No. Signal TMP006EVM? Signal 1 I2C_SCL Yes SCL 2 CTRL/MEAS4 Yes DRDY 3 I2C_SDA1 Yes SDA 4 CTRL/MEAS5 No — 5 SPI_DOUT1 Yes SDO 6 VDUT Yes VCC 7 SPI_CLK Yes SCLK 8 GND Yes GND 9 SPI_CS1 Yes CS 10 SPI_DIN1 Yes SDI 6 TMP006EVM User Guide and Software Tutorial SBOU109A–May 2011–Revised October 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com TMP006EVM Hardware Overview 2.4 Signal Definition of H2 (10-Pin FFC Connector) Table 4 shows the signals connected to the H2 connector on the TMP006 Test Board. Table 4. Signal Definition for H2 (10-Pin FFC Connector) on TMP006EVM Board Pin No. Signal 1 SCL 2 VCC 3 SDA 4 VCC 5 SDO 6 GND 7 SCLK 8 GND 9 CS 10 SDI 3 TMP006EVM Hardware Overview If not already assembled, the basic hardware setup for the TMP006EVM involves connecting the TMP006 Test Board to the SM-USB-DIG and then connecting the USB cable. This section presents the details of this procedure. 3.1 Electrostatic Discharge Warning CAUTION Many of the components on the TMP006EVM are susceptible to damage by electrostatic discharge (ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling the EVM, including the use of a grounded wrist strap at an approved ESD workstation. 3.2 Typical TMP006EVM Hardware Setup Connect the right-angle female socket (H1) on the TMP006 Test Board to the right-angle male header (H2) on the SM-USB-DIG. Take special care to ensure that the two 10-pin sockets directly align with each other. Plug the female USB-A cable to the SM-USB-DIG and then plug the male USB-A cable into the computer. Always connect the two boards together before connecting the USB cable to avoid any issues if the connectors are misaligned. Figure 5. Typical Hardware Connection SBOU109A–May 2011–Revised October 2011 TMP006EVM User Guide and Software Tutorial 7 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated TMP006EVM Software Overview www.ti.com Figure 6 shows the typical behavior when the SM-USB-DIG is plugged into the USB port of a PC for the first time. Typically, the computer will respond with a Found New Hardware, USB Device pop-up dialog. The pop-up window then typically changes to Found New Hardware, USB Human Interface Device. This pop-up indicates that the device is ready to be used. The SM-USB-DIG uses the human interface device drivers that are part of the Microsoft® Windows® operating system. Figure 6. Typical PC Behavior After Connecting TMP006EVM In some cases, the Windows Add Hardware wizard appears. If this installation prompt occurs, allow the Device Manager to install the human interface drivers by clicking Yes at each request to install the drivers. 4 TMP006EVM Software Overview This section describes the installation and use of the TMP006EVM software. 4.1 Hardware Requirements The TMP006EVM software has been tested on the Microsoft Windows XP operating system (OS) with United States and European regional settings. The software should function correctly on other Windows-based OSs. 4.2 GUI Software Installation The TMP006EVM software is included on the CD that is shipped with the EVM kit. It is also available through the TMP006EVM product folder on the TI web site. To install the software to a computer, insert the disc into an available CD-ROM drive. Navigate to the drive contents and open the TMP006EVM software folder. Locate and launch the TMP006EVM installation file, setup.exe, as shown in Figure 7. It is in the Installer directory. Figure 7. TMP006EVM Software Installation Files 8 TMP006EVM User Guide and Software Tutorial SBOU109A–May 2011–Revised October 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com TMP006EVM Software Overview The TMP006EVM software installer file then begins the installation process as shown in Figure 8. Figure 8. TMP006EVM Software Installation Launch Follow the prompts as shown in Figure 9 to install the TMP006EVM GUI software. Figure 9. TMP006EVM GUI Software Installation Prompts The TMP006EVM GUI software is now installed. SBOU109A–May 2011–Revised October 2011 TMP006EVM User Guide and Software Tutorial 9 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated TMP006EVM Software Overview www.ti.com 4.3 Launching the TMP006EVM GUI Software With the TMP006EVM properly connected (see Figure 5), launch the EVM GUI software from the Start menu. It is located in a folder titled, TMP006EVM GUI Installer. The software should launch with a screen similar to that shown in Figure 10. Figure 10. TMP006EVM GUI Software Default Configuration 10 TMP006EVM User Guide and Software Tutorial SBOU109A–May 2011–Revised October 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com TMP006EVM Software Use If the message shown in Figure 11 appears when the TMP006EVM GUI software is launched, disconnect all components of the TMP006EVM kit, and repeat the hardware assembly instructions in Section 3.2. Figure 11. Hardware Error Message 5 TMP006EVM Software Use This section discusses how to use the TMP006EVM software. The TMP006EVM GUI software has a primary window that is used to configure and read from the TMP006, along with two other windows that are used to access different features of the TMP006. Basic GUI functionality and a description of the tabs are also presented in this section. SBOU109A–May 2011–Revised October 2011 TMP006EVM User Guide and Software Tutorial 11 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated TMP006EVM Software Use www.ti.com 5.1 Reading from the TMP006 On the primary GUI window (see Figure 10), press the Read All Reg button to read the TMP006 registers and begin collecting temperature measurement data. Figure 12 illustrates this action. Raw temperature and configuration register values can be found in the Registers tab (refer to Section 5.3). Figure 12. Read All Registers to Update Temperature 12 TMP006EVM User Guide and Software Tutorial SBOU109A–May 2011–Revised October 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com TMP006EVM Software Use 5.2 Writing to the TMP006 To modify the TMP006 configuration register, make any desired changes on the Block Diagram tab and then press the Write All Reg button, as shown in Figure 13. Figure 13. Make Changes to TMP006 Registers SBOU109A–May 2011–Revised October 2011 TMP006EVM User Guide and Software Tutorial 13 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated TMP006EVM Software Use www.ti.com The Pending changes need to be written LED illuminates when there are changes that have not been written to the TMP006, as shown in Figure 14. Figure 14. Write Changes to TMP006 Registers 14 TMP006EVM User Guide and Software Tutorial SBOU109A–May 2011–Revised October 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com TMP006EVM Software Use 5.3 Registers Tab In this tab, you can select any row in the Register table by clicking on it with your mouse. When a row is selected, it becomes highlighted in blue in the table. The individual 16 bits in the selected register are displayed below the Register table. Note that each bit has descriptive text above the bit that identifies the function of the bit. You can edit the bit value using the up (↑) or down (↓) arrow to the left of the bit. Any changes on the bit are displayed in the table and in the block diagram. Additionally, any changes in the block diagram are reflected in the table. The Help w Reg button can be pressed to see detailed help about the register that is currently selected. This feature gives detailed information regarding the meaning of each bit. The Registers tab on the TMP006EVM GUI software is illustrated in Figure 15. Figure 15. TMP006EVM GUI Software Registers Tab SBOU109A–May 2011–Revised October 2011 TMP006EVM User Guide and Software Tutorial 15 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated TMP006EVM Software Use www.ti.com 5.4 Graphing Tab The Graphing tab allows you to graph the temperature sensor results. To start the graphing process, you must press the Read Continuous button. After pressing this button, it turns green and the graph starts to update. Press the Read Continuous button again to turn off this function. Figure 16 shows this process. Figure 16. Read Registers Continuously to Update Graphs 16 TMP006EVM User Guide and Software Tutorial SBOU109A–May 2011–Revised October 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com TMP006EVM Software Use 5.5 Transient Correction Algorithm The accurate performance of the TMP006EVM is highly dependent on a stable local temperature. Degraded performance can be observed when local temperature transients are introduced into the system, because the infrared (IR) thermopile in the TMP006 is sensitive to conducted and radiated IR energy from below the sensor as well as radiated IR energy that comes from above the sensor. When the TMP006EVM experiences a local temperature transient event, the PCB temperature and the TMP006 die temperature drift apart from each other as a result of the thermal time constant of the TMP006 thermopile. This difference in temperatures causes a heat transfer between the IR sensor and the PCB to occur. Because of the small distance between the PCB and the bottom of the sensor, this heat energy is conducted (as opposed to radiated) through the thin layer of air between the IR sensor and the PCB below it. This conducted heat energy causes an offset in the IR sensor voltage reading, and ultimately leads to unwanted temperature calculation error. The additional error that results from local temperature transient events can be suppressed in the software by using a transient correction algorithm. This algorithm monitors the TMP006 die temperature over a four-second interval and uses the die temperature data to calculate a local temperature slope, as shown in Equation 1. TSLOPE = – (0.3 × TDIE1) – (0.1 × TDIE2) + (0.1 × TDIE3) + (0.3 × TDIE4) (1) The local temperature slope and the known thermal resistance and capacitance of the TMP006 thermopile are then applied to Equation 2 to correct the sensor voltage reading. VOBJ_CORRECTED = VOBJ + TSLOPE × 2.96 × 10–4 (2) The corrected sensor voltage value is then substituted for the raw sensor voltage, and the object temperature is calculated using the normal methods. To enable the transient correction algorithm, simply click the Transient Correction button in the TMP006EVM GUI as shown in Figure 17. When transient correction is first enabled, a delay of four conversions will be observed while the local temperature slope is being calculated. Figure 17. Enable Transient Correction Algorithm SBOU109A–May 2011–Revised October 2011 TMP006EVM User Guide and Software Tutorial 17 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated TMP006EVM Software Use www.ti.com 5.6 Logging Data from the TMP006EVM The TMP006EVM software has the ability to save data collected by the TMP006 into a comma-separated value (.CSV) format file. To save data in this format, select Save Temperature Data from the USB Controls drop-down menu. Figure 18 shows the steps required to begin logging temperature data with the TMP006EVM. Figure 18. Start Data Logging 18 TMP006EVM User Guide and Software Tutorial SBOU109A–May 2011–Revised October 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com TMP006EVM Software Use Figure 19 displays an example of how the output file can appear after minimal formatting by the user. Figure 19. Example .CSV Output File (Formatted and Displayed in Microsoft Excel®) SBOU109A–May 2011–Revised October 2011 TMP006EVM User Guide and Software Tutorial 19 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Revision History www.ti.com Revision History Changes from Original (May, 2011) to A Revision .......................................................................................................... Page • Updated document to reflect new software functionality ............................................................................ 1 • Revised Figure 2 for improved clarity .................................................................................................. 3 • Updated Figure 4 to reflect unpopulated connector H2 ............................................................................. 5 • Changed Figure 5 to reflect new SM-USB-DIG casing .............................................................................. 7 • Corrected typos and updated Figure 10 through Figure 16 to reflect new software functionality ............................. 8 • Added Transient Correction Algorithm section ...................................................................................... 17 • Updated Figure 18 to reflect new software functionality ........................................................................... 18 • Revised Figure 19 for improved clarity ............................................................................................... 19 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 20 Revision History SBOU109A–May 2011–Revised October 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives. Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/or safety programs, please contact the TI application engineer or visit www.ti.com/esh. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. FCC Warning This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. EVM Warnings and Restrictions It is important to operate this EVM within the input voltage range of 2.7V (min) to 5.5V (max) and the output voltage range of 2.7V (min) to 5.5V (max). Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than +25°C. The EVM is designed to operate properly with certain components above +25°C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. 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DS51589A Explorer 16 Development Board User’s Guide DS51589A-page ii © 2005 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. EXPLORER 16 DEVELOPMENT BOARD USER’S GUIDE © 2005 Microchip Technology Inc. DS51589A-page iii Table of Contents Preface ........................................................................................................................... 1 Chapter 1. Introducing the Explorer 16 Development Board 1.1 Introduction ..................................................................................................... 7 1.2 Highlights ........................................................................................................ 7 1.3 What’s in the Kit ............................................................................................. 7 1.4 Explorer 16 Development Board Functionality and Features ......................... 8 1.5 Using the Explorer 16 Out of the Box ............................................................. 9 1.6 Explorer 16 Development Board Demonstration Programs ......................... 10 1.7 Reference Documents .................................................................................. 10 Chapter 2. Explorer 16 Programming Tutorial 2.1 Introduction ................................................................................................... 11 2.2 Highlights ...................................................................................................... 11 2.3 Tutorial Overview ......................................................................................... 11 2.4 Creating the Project ...................................................................................... 12 2.5 Building The Code ........................................................................................ 16 2.6 Programming the Device .............................................................................. 19 Chapter 3. Explorer 16 Tutorial Programs 3.1 Introduction ................................................................................................... 23 3.2 PIC24 Tutorial Program Operation ............................................................... 23 3.3 dsPIC33F Tutorial Program Operation ......................................................... 25 Chapter 4. Explorer 16 Development Hardware 4.1 Introduction .................................................................................................. 27 4.2 Hardware Features ....................................................................................... 27 Appendix A. Explorer 16 Development Board Schematics A.1 Introduction .................................................................................................. 33 A.2 Development Board Block Diagram ............................................................. 33 A.3 Development Board Schematics .................................................................. 34 Appendix B. Updating the USB Connectivity Firmware B.1 Introduction .................................................................................................. 43 B.2 Updating the PICkit 2 Microcontroller Programmer ..................................... 43 B.3 Other USB Firmware Updates ..................................................................... 44 Index ............................................................................................................................. 45 Worldwide Sales and Service .................................................................................... 46 Explorer 16 Development Board User’s Guide DS51589A-page iv © 2005 Microchip Technology Inc. NOTES: EXPLORER 16 DEVELOPMENT BOARD USER’S GUIDE © 2005 Microchip Technology Inc. DS51589A-page 1 Preface INTRODUCTION This chapter contains general information that will be useful to know before using the Explorer 16 Development Board. Items discussed in this chapter include: • Document Layout • Conventions Used in this Guide • Warranty Registration • Recommended Reading • The Microchip Web Site • Development Systems Customer Change Notification Service • Customer Support • Document Revision History DOCUMENT LAYOUT This document describes how to use the Explorer 16 Development Board as a development tool to emulate and debug firmware on a target board. The manual layout is as follows: • Chapter 1. “Introducing the Explorer 16 Development Board” provides a brief overview of the Explorer 16 Development Board, its features and its uses. • Chapter 2. “Explorer 16 Programming Tutorial” provides step-by-step instructions for using MBLAB® IDE to create a project and program the Explorer 16 board. • Chapter 3. “Explorer 16 Tutorial Programs” describes the demonstration program created in Chapter 2. “Explorer 16 Programming Tutorial”. • Chapter 4. “Explorer 16 Development Hardware” provides a more detailed description of the Explorer 16 board’s hardware features. • Appendix A. “Explorer 16 Development Board Schematics” provides a block diagram and detailed schematics of the Explorer 16 board. • Appendix B. “Updating the USB Connectivity Firmware” describes how to upgrade the Explorer 16 board’s USB connectivity subsystem. NOTICE TO CUSTOMERS All documentation becomes dated, and this manual is no exception. Microchip tools and documentation are constantly evolving to meet customer needs, so some actual dialogs and/or tool descriptions may differ from those in this document. Please refer to our web site (www.microchip.com) to obtain the latest documentation available. Documents are identified with a “DS” number. This number is located on the bottom of each page, in front of the page number. The numbering convention for the DS number is “DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the document. For the most up-to-date information on development tools, see the MPLAB® IDE on-line help. Select the Help menu, and then Topics to open a list of available on-line help files. Preface © 2005 Microchip Technology Inc. DS51589A-page 2 CONVENTIONS USED IN THIS GUIDE This manual uses the following documentation conventions: WARRANTY REGISTRATION Please complete the enclosed Warranty Registration Card and mail it promptly. Sending in the Warranty Registration Card entitles users to receive new product updates. Interim software releases are available at the Microchip web site. DOCUMENTATION CONVENTIONS Description Represents Examples Arial font: Italic characters Referenced books MPLAB® IDE User’s Guide Emphasized text ...is the only compiler... Initial caps A window the Output window A dialog the Settings dialog A menu selection select Enable Programmer Quotes A field name in a window or dialog “Save project before build” Underlined, italic text with right angle bracket A menu path File>Save Bold characters A dialog button Click OK A tab Click the Power tab Text in angle brackets < > A key on the keyboard Press , Courier New font: Plain Courier New Sample source code #define START Filenames autoexec.bat File paths c:\mcc18\h Keywords _asm, _endasm, static Command-line options -Opa+, -Opa- Bit values 0, 1 Constants (in source code) 0xFF, ‘A’ Italic Courier New A variable argument file.o, where file can be any valid filename Square brackets [ ] Optional arguments mcc18 [options] file [options] Curly brackets and pipe character: { | } Choice of mutually exclusive arguments; an OR selection errorlevel {0|1} Ellipses... Replaces repeated text var_name [, var_name...] Represents code supplied by user void main (void) { ... } Explorer 16 Development Board User’s Guide DS51589A-page 3 © 2005 Microchip Technology Inc. RECOMMENDED READING This user’s guide describes how to use the Explorer 16 Development Board. Other useful documents are listed below. The following Microchip documents are available and recommended as supplemental reference resources. Readme for the Explorer 16 Development Board For the latest information on using the Explorer 16 Development Board, read the Readme for Explorer 16 Development Board.txt file (an ASCII text file) at the root level of the Explorer 16 CD-ROM. The Readme file contains update information and known issues that may not be included in this user’s guide. Readme Files For the latest information on using other tools, read the tool-specific Readme files in the Readmes subdirectory of the MPLAB IDE installation directory. The Readme files contain update information and known issues that may not be included in this user’s guide. PIC24FJ128GA010 PS Data Sheet (DS39756) and PIC24FJ128GA Family Data Sheet (DS39747) Consult this document for detailed information on the PIC24F general purpose, 16-bit devices. Reference information found in this data sheet includes: • Device memory map • Device pinout and packaging details • Device electrical specifications • List of peripherals included on the device Note that document, DS39756, is for use only with the initial prototype samples of the PIC24F family. These devices are all marked with a “PS” suffix at the end of the device number. For all other PIC24FJ128GA family devices, including those with an “ES” suffix, use DS39747. dsPIC33F Family Data Sheet (DS70165) Consult this document for detailed information on the dsPIC33F Digital Signal Controllers. Reference information found in this data sheet includes: • Device memory map • Device pinout and packaging details • Device electrical specifications • List of peripherals included on the device dsPIC30F Programmer’s Reference Manual (DS70030) This manual is a software developer’s reference for all of Microchip’s 16-bit digital signal controllers. It describes the instruction set in detail and also provides general information to assist in developing software for PIC24 MCUs, dsPIC30F and dsPIC33F DSCs. PIC24H Family Overview (DS70166) This document provides an overview of the functionality of the new PIC24H product family. It helps determine how the PIC24H high-performance, 16-bit microcontrollers fit a specific product application. Preface © 2005 Microchip Technology Inc. DS51589A-page 4 MPLAB® C30 C Compiler User’s Guide (DS51284) This document details the use of Microchip’s MPLAB C30 C Compiler for dsPIC® devices to develop an application. MPLAB C30 is a GNU-based language tool, based on source code from the Free Software Foundation (FSF). For more information about the FSF, see www.fsf.org. Other GNU language tools available from Microchip are: • MPLAB ASM30 Assembler • MPLAB LINK30 Linker • MPLAB LIB30 Librarian/Archiver MPLAB® IDE Simulator, Editor User’s Guide (DS51025) Consult this document for more information pertaining to the installation and implementation of the MPLAB Integrated Development Environment (IDE) software. THE MICROCHIP WEB SITE Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives Explorer 16 Development Board User’s Guide DS51589A-page 5 © 2005 Microchip Technology Inc. DEVELOPMENT SYSTEMS CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. The Development Systems product group categories are: • Compilers – The latest information on Microchip C compilers and other language tools. These include the MPLAB C18 and MPLAB C30 C compilers; MPASM™ and MPLAB ASM30 assemblers; MPLINK™ and MPLAB LINK30 object linkers; and MPLIB™ and MPLAB LIB30 object librarians. • Emulators – The latest information on Microchip in-circuit emulators.This includes the MPLAB ICE 2000 and MPLAB ICE 4000. • In-Circuit Debuggers – The latest information on the Microchip in-circuit debugger, MPLAB ICD 2. • MPLAB® IDE – The latest information on Microchip MPLAB IDE, the Windows® Integrated Development Environment for development systems tools. This list is focused on the MPLAB IDE, MPLAB SIM simulator, MPLAB IDE Project Manager and general editing and debugging features. • Programmers – The latest information on Microchip programmers. These include the MPLAB PM3 and PRO MATE® II device programmers and the PICSTART® Plus and PICkit™ 1 development programmers. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office • Field Application Engineer (FAE) • Technical Support • Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com DOCUMENT REVISION HISTORY Revision A (November 2005) This is the initial release of this Document. Preface © 2005 Microchip Technology Inc. DS51589A-page 6 NOTES: EXPLORER 16 DEVELOPMENT BOARD USER’S GUIDE © 2005 Microchip Technology Inc. DS51589A-page 7 Chapter 1. Introducing the Explorer 16 Development Board 1.1 INTRODUCTION Thank you for purchasing Microchip Technology’s Explorer 16 Development Board Kit. The development board provides a low-cost, modular development system for Microchip’s new line of 16-bit microcontroller families, including the PIC24, PIC24H and the 16-bit digital signal controller family, dsPIC33F. As provided, the development board works as a demo board right from the box, and also has the ability to extend its functionality through modular expansion interfaces. The Explorer 16 board supports MPLAB ICD 2 for full emulation and debug capabilities, and also allows 3V controllers to interface with 5V peripheral devices. 1.2 HIGHLIGHTS This chapter covers the following topics: • What’s in the Kit • Explorer 16 Development Board Functionality and Features • Using the Explorer 16 Out of the Box • Explorer 16 Development Board Demonstration Programs • Reference Documents 1.3 WHAT’S IN THE KIT The Explorer 16 Development Board Kit contains the following: • The Explorer 16 Development Board. • A preprogrammed PIC24FJ128GA010 Processor Installation Module (PIM), already installed to the board • A preprogrammed dsPIC33FJ256GP710 PIM • An RS-232 cable • The Explorer 16 Development CD ROM, containing: - This User’s Guide - Data Sheets for the PIC24FJ128GA family and dsPIC33FJ256GP family - Schematics and PCB drawing files for the PIM modules - Example programs for use with the PIC24 and dsPIC33F devices - Files detailing general purpose expansion boards that can be used with the Explorer 16 board (provided in Gerber format) If you are missing any part of the kit, please contact your nearest Microchip sales office, listed on the last page of this manual, for further assistance. Note: The Explorer 16 Development Board has been designed to function primarily from a permanently mounted PIC24FJ128GA010 device at position U1. Initial units will be shipped with U1 unpopulated and a PIC24FJ PIM of equal functionality mounted on the U1A headers instead. When using the PIC24FJ PIM or any other PIM, it is critical to verify that switch S2 always remains in the “PIM” position. See Section 4.2.1 “Processor Support” for more information. Introducing the Explorer 16 Development Board © 2005 Microchip Technology Inc. DS51589A-page 8 1.4 EXPLORER 16 DEVELOPMENT BOARD FUNCTIONALITY AND FEATURES A layout of the Explorer 16 Development Board is shown in Figure 1-1. The board includes these key features, as indicated in the diagram: 1. 100-pin PIM riser, compatible with the PIM versions of all Microchip PIC24F/24H/dsPIC33F devices 2. Direct 9 VDC power input that provides +3.3V and +5V (regulated) to the entire board 3. Power indicator LED 4. RS-232 serial port and associated hardware 5. On-board analog thermal sensor 6. USB connectivity for communications and device programming/debugging 7. Standard 6-wire In-Circuit Debugger (ICD) connector for connections to an MPLAB ICD 2 programmer/debugger module 8. Hardware selection of PIM or soldered on-board microcontroller (in future versions) 9. 2-line by 16-character LCD 10. Provisioning on PCB for add on graphic LCD 11. Push button switches for device Reset and user-defined inputs 12. Potentiometer for analog input 13. Eight indicator LEDs 14. 74HCT4053 multiplexers for selectable crossover configuration on serial communication lines 15. Serial EEPROM 16. Independent crystals for precision microcontroller clocking (8 MHz) and RTCC operation (32.768 kHz) 17. Prototype area for developing custom applications 18. Socket and edge connector for PICtail™ Plus card compatibility 19. Six-pin interface for PICkit 2 Programmer 20. JTAG connector pad for optional boundary scan functionality For additional details on these features, refer to Chapter 4. “Explorer 16 Development Hardware”. 1.4.1 Sample Devices Included with the Development Kit Each Explorer 16 Development Board Kit contains two preprogrammed 16-bit devices: a PIC24FJ128GA010 and a dsPIC33FJ256GP710. These are provided as 100-pin PIMs on riser sockets, which can be quickly installed on pin header U1A and exchanged as needed. Note: As Microchip’s 16-bit portfolio develops, alternate devices may be included with the Explorer 16 Development Board Kit. It is anticipated that one device each of the PIC24 and dsPIC33F families will always be included. Also in the future, the included PIC24 device will be soldered onto the board and only the dsPIC33F device will be provided as a PIM. Explorer 16 Development Board User’s Guide DS51589A-page 9 © 2005 Microchip Technology Inc. FIGURE 1-1: EXPLORER 16 DEVELOPMENT BOARD LAYOUT 1.5 USING THE EXPLORER 16 OUT OF THE BOX Although intended as a development platform, the Explorer 16 board may also be used directly from the box as a demonstration board for PIC24 and dsPIC33F devices. The programs discussed in Chapter 3. “Explorer 16 Tutorial Programs” are preprogrammed into the sample device PIMs (i.e., PIC24ExplDemo.hex for the PIC24 device and dsPIC33ExplDemo.hex for the dsPIC33F device) and are ready for immediate use. To get started with the board: 1. For Explorer 16 boards without a permanently mounted PIC24FJ device: verify that the PIC24FJ128GA010 PIM is correctly installed onto the board. If you want to use the dsPIC® device PIM, carefully remove the PIC24 PIM and install the dsPIC33F PIM in its place. For all PIMs, be certain to align the PIM so the notched corner marking is oriented in the upper left corner. 2. For Explorer 16 boards without a permanently mounted PIC24FJ device: verify that switch S2 is set in the “PIM” position. For Explorer 16 boards with a permanently mounted PIC24FJ device: verify that switch S2 is set in the “PIC” position. 3. Verify that the jumper on JP2 is installed (to enable the LEDs). 4. Apply power to the board (9 VDC) at power input J2. For information on acceptable power sources, see Appendix A. “Explorer 16 Development Board Schematics”. Refer to Chapter 3. “Explorer 16 Tutorial Programs” for details on the demonstration code operation. 1 10 7 4 5 6 3 2 8 9 11 12 13 14 15 16 17 18 19 20 Introducing the Explorer 16 Development Board © 2005 Microchip Technology Inc. DS51589A-page 10 FIGURE 1-2: EXPLORER 16 PIM MODULE, SHOWING NOTCHED CORNER MARKING 1.6 EXPLORER 16 DEVELOPMENT BOARD DEMONSTRATION PROGRAMS The preprogrammed example code on the PIMs has been included on the Explorer 16 CD-ROM for future reference. All project files have been included, so that the code may be used directly to restore a PIM to its original state (i.e., if the sample device has been reprogrammed with another program), or so the user may use the tutorial code as a platform for further experimentation. In addition, the CD-ROM contains sample demonstration programs for both PIC24 and dsPIC33F family devices. Separate demo source code (as files in C) and compiled code files (in Hex) are provided for each family. These may be used with the included PIC24 and dsPIC33F PIMs by reprogramming the devices using MPLAB ICD 2. 1.7 REFERENCE DOCUMENTS In addition to the documents listed in the “Recommended Reading” section, these documents are also available from Microchip to support the use of the Explorer 16 Development Board: • PIC18F2455/2550/4455/4550 Data Sheet (DS39632) • TC1047/TC1047A Data Sheet (DS21498) • 25AA256/25LC256 Data Sheet (DS21822) • PICkit™ 2 Microcontroller Programmer User’s Guide (DS51553) • MPLAB® ICD 2 In-Circuit Debugger Quick Start Guide (DS51268) • PRO MATE® II User’s Guide (DS30082) You can obtain these reference documents from your nearest Microchip sales office (listed in the back of this document) or by downloading them from the Microchip web site (www.microchip.com). PIC24FJ128GA010 EXPLORER 16 DEVELOPMENT BOARD USER’S GUIDE © 2005 Microchip Technology Inc. DS51589A-page 11 Chapter 2. Explorer 16 Programming Tutorial 2.1 INTRODUCTION This chapter is a self-paced tutorial to get you started using the Explorer 16 Development Board. 2.2 HIGHLIGHTS Items discussed in this chapter include: • Tutorial Overview • Creating the Project • Building the Code • Programming the Device 2.3 TUTORIAL OVERVIEW The tutorial in this chapter demonstrates the main features of the MPLAB IDE and MPLAB ICD 2 as they are used with the Explorer 16 Development Board. As presented, it is designed for use with the PIC24FJ128GA010 specifically. However, the same procedures and toolsuites can also be used with PIC24H or dsPIC33F devices. The PIC24 tutorial project demonstrated here, PIC24ExplDemo.mcp, is written in C for MPLAB C30. The program displays PIC24 features on the alphanumeric LCD, and also displays voltage, temperature and date/time as the various buttons are pressed. Described with the PIC24 project is the dsPIC device tutorial, Example1_RTC_LED_ADC.mcp. It is also written in C for MPLAB C30. The program displays voltage and current time, updating the display on command. Both programs are described in more detail in Chapter 3. “Explorer 16 Tutorial Programs”. For either project, the source file (PIC24ExplDemo.c or main_rtc.c for PIC24 or dsPIC33F, respectively) is used with a linker script file (p24fj128ga010.gld or p33fj256gp710ps.gld) and header file (p24fj128ga010.h or p33fj256gp710ps.h) to form a complete project. While these simple projects use a single source code file, more complex projects might use multiple assembler and compiler source files, as well as library files and precompiled object files. Upon completing this tutorial, you should be able to: • Create a project using the Project Wizard • Assemble and link the code and set the Configuration bits • Set up MPLAB IDE to use the MPLAB ICD 2 • Program the chip with the MPLAB ICD 2 There are three steps to this tutorial: 1. Creating a project in MPLAB IDE. 2. Assembling and linking the code. 3. Programming the chip with the MPLAB ICD 2. Explorer 16 Programming Tutorial © 2005 Microchip Technology Inc. DS51589A-page 12 2.4 CREATING THE PROJECT The first step is to create a project and a workspace in MPLAB IDE. Typically, there is one project in one workspace. A project contains the files needed to build an application (source code, linker script files, etc.) along with their associations to various build tools and build options. A workspace contains one or more projects and information on the selected device, debug tool and/or programmer, open windows and their location and other MPLAB IDE configuration settings. MPLAB IDE contains a Project Wizard to help create new projects. Before starting, create a folder named Tutorial for the project files for this tutorial (C:\Tutorial is assumed in the instructions that follow). From the Example Code\Tutorial Code directory on the Explorer 16 Development Kit Software CD-ROM, copy all of the source files into this folder. 2.4.1 Select a Device 1. Start MPLAB IDE. 2. Close any workspace that might be open (File > Close Workspace). 3. From the Project menu, select Project Wizard. 4. From the Welcome screen, click Next > to display the Project Wizard Step One dialog (Figure 2-1). FIGURE 2-1: SELECTING THE DEVICE 5. From the Device drop-down list, select “PIC24FJ128GA010” or “dsPIC33FJ256GP710PS”, depending on the PIM being used. Click Next >. The Project Wizard Step Two dialog will be displayed (see Figure 2-2). Note: These instructions presume the use of MPLAB IDE 7.22 or newer. Note: The screen shots in the following sections show the PIC24 tutorial. Except for displayed file names, the screens for the dsPIC33F tutorial will be identical. Explorer 16 Development Board User’s Guide DS51589A-page 13 © 2005 Microchip Technology Inc. FIGURE 2-2: SELECTING THE TOOLSUITE 2.4.2 Select Language Toolsuite 1. From the Active Toolsuite drop-down list, select Microchip C30 Toolsuite. This toolsuite includes the assembler and linker that will be used. 2. In the Toolsuite Contents combo box, select MPLAB C30 Compiler (pic30-gcc.exe). 3. In the Location box, click Browse... and navigate to C:\Program Files\Microchip\MPLAB C30\bin\pic30-as.exe. 4. With MPLAB LINK 30 Object Linker (pic30-ld.exe) selected in Toolsuite Contents, click Browse... and navigate to C:\Program Files\Microchip\MPLAB C30\bin\pic30-Id.exe. 5. Click Next > to continue. The Project Wizard Step Three dialog displays (Figure 2-3). Explorer 16 Programming Tutorial © 2005 Microchip Technology Inc. DS51589A-page 14 FIGURE 2-3: NAMING YOUR PROJECT 2.4.3 Name Your Project 1. In the Project Name text box, type “MyProject”. 2. In the Project Directory box, click Browse... and navigate to C:\Tutorial to place your project in the Tutorial folder. 3. Click Next > to continue. The Project Wizard Step Four dialog displays (Figure 2-4). FIGURE 2-4: ADDING FILES TO THE PROJECT Explorer 16 Development Board User’s Guide DS51589A-page 15 © 2005 Microchip Technology Inc. 2.4.4 Add Files to Project 1. From the list of folders on the PC, locate the C:\Tutorial folder. 2. Select the source (.c) and header (.h) files. Click Add >> to include the file in the project. 3. Expand the C:\Program Files\Microchip\MPLAB 30\support\gld folder and select the p24fj128ga010.gld or p33fj256gp710ps.gld file, as appropriate. 4. Click Add >> to include this file in the project. There should now be two files in the project. 5. Click Next > to continue. 6. When the summary screen displays, click Finish. After the Project Wizard completes, the MPLAB Project window shows the source files in the Source Files folder and the appropriate linker script in the Linker Scripts folder (Figure 2-5). FIGURE 2-5: PROJECT WINDOW A project and workspace has now been created in MPLAB IDE. MyProject.mcw is the workspace file and MyProject.mcp is the project file. Double-click the PIC24ExplDemo.c file (for PIC24) or main_rtc.c file (for dsPIC33F) in the Project window to open the file. MPLAB IDE should now look similar to Figure 2-6. Explorer 16 Programming Tutorial © 2005 Microchip Technology Inc. DS51589A-page 16 FIGURE 2-6: MPLAB® IDE WORKSPACE 2.5 BUILDING THE CODE In this project, building the code consists of compiling the source files to create an object file, MyProject.o, then linking the object file to create the MyProject.hex and MyProject.cof output files. (For dsPIC33F projects, the files would be Example1_RTC_LED_ADC.o, Example1_RTC_LED_ADC.hex and Example1_RTC_LED_ADC.cof.)The Hex file contains the data necessary to program the device, and the .cof file contains additional information that lets you debug the code at the source code level. Before building, there are settings required to tell MPLAB IDE where to find the include files and to reserve space for the extra debug code when the MPLAB ICD 2 is used. For PIC24 projects, the following line in the system.h file is: #include “p24fj128ga010.h” For dsPIC33 projects, the line is: #include “p33fj256gp710ps.h” This line causes a standard include file to be used. Microchip provides these files with all the Special Function Register (SFR) labels already defined for convenience. To build the code, select Build Options > Project from the Project menu. The Build Options dialog displays (Figure 2-7). Project Window Output Window Source Window Code Explorer 16 Development Board User’s Guide DS51589A-page 17 © 2005 Microchip Technology Inc. FIGURE 2-7: BUILD OPTIONS 2.5.1 Identify Assembler Include Path 1. Select the General tab. 2. Click Suite Default. This tells the environment where to find the library files. 3. Select the MPLAB LINK30 tab to view the linker settings (Figure 2-8). 4. Check Link for ICD2. 5. Click OK. The text box closes while the linker reserves space for the debug code used by the MPLAB ICD 2. 6. Click OK again to save these changes. The project is now ready to build. Explorer 16 Programming Tutorial © 2005 Microchip Technology Inc. DS51589A-page 18 FIGURE 2-8: MPLAB® LINK30 BUILD OPTIONS 2.5.2 Build the Project From the menu bar of the main MPLAB IDE window, select Project > Make. The Build Output window displays (Figure 2-9). Observe the progress of the build. When the “BUILD SUCCEEDED” message displays, you are ready to program the device. FIGURE 2-9: BUILD OUTPUT Explorer 16 Development Board User’s Guide DS51589A-page 19 © 2005 Microchip Technology Inc. 2.6 PROGRAMMING THE DEVICE The MPLAB ICD 2 In-Circuit Debugger is used to program and debug the microcontroller in-circuit on the Explorer 16 Development Board. 2.6.1 Set Up the Device Configuration The device configuration for the target microcontroller can be set by two methods: using configuration macros in the source code, or using the Configuration Bits window in MPLAB IDE. The PIC24 Explorer 16 tutorial code already includes configuration macros in the source code itself. It is only necessary to confirm that the following macros are in place near the top of the PIC24ExplDemo.c file: _CONFIG1(JTAGEN_OFF & GSS0_OFF & GWRP_OFF & BKBUG_OFF & COE_OFF & FWDTEN_OFF & FNOSC_PRI) _CONFIG2(FCKSM_CSDCMD & OSCIOFNC_ON & POSCMOD_HS) For the dsPIC33F tutorial code, confirm that the following macros are in place near the top of the main_rtc.c file: _FGS(CODE_WRITE_PROT_OFF); _FOSCSEL(FRC_PLL); _FOSC(CSW_FSCM_OFF & OSC2_IO & XT); _FWDT(WDT_OFF); If configuration macros are not used in the source code, it is also possible to set device configuration with the Configuration Bits window. For the PIC24 code, the process is as follows: 1. From the main window’s menu bar, select Configure > Configuration Bits to display the configuration settings (Figure 2-10). 2. Set the Configuration bits by clicking on a particular line item and selecting an option from the drop-down menu that appears. The Configuration bits should be set as shown in Figure 2-10. The settings that will most likely need to change are: a) Primary Oscillator Select: HS Oscillator Enabled b) Oscillator Select: Primary Oscillator (XT, HS, ES) c) Clock Switching and Monitor: SW Disabled, Mon Disabled d) Watchdog Timer Enable: Disable Note: Before proceeding, make sure that the USB driver for the MPLAB ICD 2 has been installed on the PC (see the MPLAB® ICD 2 In-Circuit Debugger User’s Guide (DS51331) for more details regarding the installation of the MPLAB ICD 2). Explorer 16 Programming Tutorial © 2005 Microchip Technology Inc. DS51589A-page 20 FIGURE 2-10: CONFIGURATION SETTINGS (PIC24) 2.6.2 Connect and Enable MPLAB ICD 2 1. Connect the MPLAB ICD 2 module to the PC with the USB cable. 2. Connect the MPLAB ICD 2 to the Explorer 16 Development Board with the short RJ-11 cable. 3. Apply power to the Explorer 16 board. 4. From the Debugger menu, click Select Tool > MPLAB ICD 2 to set the MPLAB ICD 2 as the debug tool in MPLAB IDE. 5. From the Debugger menu, select Connect to connect the debugger to the device. MPLAB IDE should report that it found the PIC24FJ128GA010 device, as shown in Figure 2-11. FIGURE 2-11: ENABLING MPLAB® ICD 2 Note: Do not use the Configuration Bits window to set device configuration if configuration macros are already used in the source code. In cases where both methods are used, configuration macros may override settings from the Configuration Bits window. Refer to the MPLAB IDE Simulator, Editor User’s Guide (DS51025) for additional information. Note: MPLAB IDE may need to download new firmware if this is the first time the MPLAB ICD 2 is being used with a PIC24FJ device. Allow it to do so. If any errors are shown, double-click the error message to get more information. Status indicates device is found Explorer 16 Development Board User’s Guide DS51589A-page 21 © 2005 Microchip Technology Inc. 2.6.3 Program the Device 1. From the Debugger menu, select Program to program the part. The Output window (Figure 2-12) displays the program steps as they occur. 2. Observe the results of the programming. When “MPLAB ICD 2 Ready” displays, the device is programmed and ready to run. FIGURE 2-12: PROGRAMMING THE DEVICE Explorer 16 Programming Tutorial © 2005 Microchip Technology Inc. DS51589A-page 22 NOTES: EXPLORER 16 DEVELOPMENT BOARD USER’S GUIDE © 2005 Microchip Technology Inc. DS51589A-page 23 Chapter 3. Explorer 16 Tutorial Programs 3.1 INTRODUCTION This chapter provides a high-level overview of the PIC24 and dsPIC33F firmware programmed during the tutorial exercise in the previous chapter. 3.2 PIC24 TUTORIAL PROGRAM OPERATION The PIC24 tutorial program is made up of three components which are individually displayed on the LCD. The program is used to demonstrate the new Parallel Master Port (PMP) module which is used to drive the LCD, as well as the new Real-Time Clock/Calendar module (RTCC). The program flow is shown in Figure 3-1. 3.2.1 PIC24 Features Features mode displays a continuous description of the PIC24FJ128GA010 device feature set. To exit the display and continue to the next mode, press S4. 3.2.2 Voltmeter/Temperature Voltmeter/Temperature mode uses the code modules, vbanner.c and ADC.c, and the A/D module to measure analog signals from the board and convert them for display on the LCD. The voltage is taken from the potentiometer (R6) and displays a voltage between 0.00V and 3.29V on line 1 of the LCD. Temperature is from a TC1074A analog thermal sensor (U5). The temperature is displayed on line 2 of the LCD and automatically alternates between Celsius and Fahrenheit values. The voltage and temperature are updated continuously. This mode also lets users store the current temperature in the on-board serial EEPROM by pressing S5. Pressing S6 switches the display between current and stored temperature values. An ‘M’ on the right side of the LCD indicates that a stored temperature value is being displayed. To exit and continue to the next mode, press S4. 3.2.3 Clock/Calendar Clock/Calendar mode uses code in the modules, rtcc.c and tbanner.c. Once this mode is entered from the main menu, a Real-Time Clock will start counting from 10:00:00, and display the date and day for Oct. 10, 2005. The new RTCC module and a 32 kHz clock crystal are used to provide the Real-Time Clock with day/date calendar. In Clock/Calendar mode, the user-defined push buttons do the following: • S3 toggles the Clock Set mode, which allows the user to set the date and time. Setup mode starts with the tens digit of the hour in the time display. • S4 accepts the value of the current item and moves cursor to the next item. • S5 decrements the currently selected item. • S6 increments the currently selected item. Pressing S3 once superimposes a flashing cursor over the tens digit of the hour in the time display. Each press of S4 moves the cursor sequentially through the digits of the time display, then the month, day and year. Pressing S3 at any time in the process returns to the regular clock/calendar display. Explorer 16 Tutorial Programs © 2005 Microchip Technology Inc. DS51589A-page 24 Pressing S4 at this point exits Clock/Calendar mode and returns the device to the PIC24 Features mode. The data that is sent to the LCD is also sent to the RS-232 serial port using the UART. A terminal emulator, such as HyperTerminal (installed by default on most Microsoft® Windows systems), will be able to display the same information. To do this, set the terminal emulator for 19200 baud, 8-bit data, 1 Stop bit and no parity check. FIGURE 3-1: PIC24 TUTORIAL PROGRAM FLOWCHART “Explorer 16 Development Board” Power-up PIC24 Features Scrolling Banner Is S4 pressed? “Mon 10:00:00” “Oct 10, 2005” No Yes Is S4 pressed? Is S5 pressed? Toggle Displayed Temperature between Current and Stored Is S4 pressed? No Is S3 pressed? Clock Setup mode: S3 – Exit Setup mode S4 – Accept Selection, Adjust Next Value S5 – Decrement Selection S6 – Increment Selection Yes Yes No Yes No Yes No Display Voltage Display Display Display Store Temperature in EEROM Is S6 pressed? No Yes and Temperature Explorer 16 Development Board User’s Guide DS51589A-page 25 © 2005 Microchip Technology Inc. 3.3 dsPIC33F TUTORIAL PROGRAM OPERATION The dsPIC33F tutorial program is made up of five simple processes which continuously execute on the dsPIC33FJ256GP710 device: • Real-Time Clock (RTC) using Timer1 • A/D conversion of Potentiometer (R6) • A/D volts to Hex conversion • Hex to Decimal conversion (for LCD display) • LCD Update The time of day and A/D conversion values are continually updated and displayed on the LCD. The program demonstrates the basic code to initialize Timer1, enable the Timer1 oscillator for RTC operation, and initialize the A/D for single channel conversion of potentiometer, RP5. The LCD is driven via the port pins. The program flow is shown in Figure 3-2. In addition to the tutorial, the Explorer 16 CD also provides code examples to demonstrate higher level processing requirements, such as DMA, digital filters and Fast Fourier Transforms (FFT). See Code Example 2 on the CD for more information. 3.3.1 Voltmeter The simple tutorial program initializes the A/D module for 12-bit mode with auto-sampling and conversion of the potentiometer connected to pin AN5 and initializes the respective interrupt. The A/D module continually samples and converts the potentiometer signal (0 to 3.3 VDC) on analog channel, AN5. When a conversion is complete, an interrupt is generated and the result in the ADCBUF0 register is copied into a temporary variable, temp1. The adc_lcd_update flag is then asserted and the A/D Interrupt Flag, AD1IF (IFS0<13>), is cleared. The program exits the Interrupt Service Routine and re-enters the main program loop. The variable, adc_lcd_update, is evaluated in the main loop to determine if there is a new A/D conversion value which can be converted and displayed on the LCD. The primary code modules associated with the operation of the ADC module and display are: • init_ADC.c • isr_ADC.c • advolts.c • hexdec.c 3.3.2 Real-Time Clock The tutorial program also supports a Real-Time Clock demo. Timer1 is initialized with interrupts enabled and the external 32.768 kHz oscillator is enabled. Within the Timer1 Interrupt Service Routine (once every second), the variables, hours, minutes and seconds, are updated, the flag variable, rtc_lcd_update, is asserted and the Timer1 Interrupt Flag, T1IF (IFS0<3>), is cleared. The program exits the Interrupt Service Routine and re-enters the main program loop. The variable, rtc_lcd_update, is evaluated in the main loop to determine if there is a new time of day value which can be converted and displayed on the LCD. The primary code modules associated with the operation of the Timer1 module and display are: • init_timer1.c • isr_timer1.c • hexdec.c Explorer 16 Tutorial Programs © 2005 Microchip Technology Inc. DS51589A-page 26 FIGURE 3-2: dsPIC33F TUTORIAL PROGRAM FLOWCHART “dsPIC33 Demo” “Press S3 to cont” Power-up Initialize Timer1 Is S3 pressed? Initialize A/D Converter to Decimal and Call Update_LCD No Update time? Update volts? Yes Yes No Yes No Convert Time of Day Display “Time 00:00:00” “R6 = 0.00 VDC” Display to Decimal and Call Update_LCD Convert A/D Result EXPLORER 16 DEVELOPMENT BOARD USER’S GUIDE © 2005 Microchip Technology Inc. DS51589A-page 27 Chapter 4. Explorer 16 Development Hardware 4.1 INTRODUCTION This chapter provides a more detailed description of the hardware features of the Explorer 16 Development Board. 4.2 HARDWARE FEATURES The key features of the Explorer 16 board are listed below. They are presented in the order given in Section 1.4 “Explorer 16 Development Board Functionality and Features”, Figure 1-1. 4.2.1 Processor Support The Explorer 16 board has been designed to accommodate both permanently mounted (i.e., soldered on) and detachable PIM processors. Slider switch, S2, allows the user to choose which processor to use. This makes it possible for the Explorer 16 board to support most 3V, 16-bit, pin compatible microcontrollers with appropriate PIMs. PIMs are visually indexed for proper installation. The PIM is always installed with the notched corner mark on the corner of the PIM board oriented to the upper left corner. Current revisions of the board do not have a permanently mounted microcontroller in U1. In order for the board to work, therefore, S2 must always be left in the “PIM” position. In future versions with a permanently mounted PIC24 device at U1, setting S2 in the “PIC” position will enable the on-board device and disable the PIM socket. 4.2.2 Power Supply There are two ways to supply power to the Explorer 16 board: • An unregulated DC supply of 9V to 15V (preferably 9V) supplied to J12. For default functionality, a power supply with a current capability of 250 mA is sufficient. Since the board can serve as a modular development platform that can connect to multiple expansion boards, voltage regulators (Q1 and Q2) with a maximum current capability of 800 mA are used. This may require a larger power supply of up to 1.6A. Because the regulators do not have heat sinks, long-term operation at such loads is not recommended. • An external, regulated DC power supply that provides both +5V and +3.3V can be connected to the terminals provided (at the bottom left side of the board, near S3). One green LED (D1) is provided to show when the Explorer 16 board is powered up. The power-on LED indicates the presence of +3.3V. Note: The Explorer 16 kit does not include a power supply. If an external supply is needed, use Microchip part number AC162039. Note: Do not attempt to power the Explorer 16 board using the MPLAB ICD 2 module. It is not designed to be a USB bus power source. Explorer 16 Development Hardware © 2005 Microchip Technology Inc. DS51589A-page 28 4.2.3 RS-232 Serial Port An RS-232 level shifter (U3) has been provided with all necessary hardware to support RS-232 connection with hardware flow control through the DB9 connector. The port is configured as a DCE device, and can be connected to a PC using a straight-through cable. The PIC24/dsPIC33F RX and TX pins are tied to the RX and TX lines of U3. The PIC24/dsPIC33F RTS and CTS pins are tied to the RX2 (DIN2) and TX2 (DOUT2) lines of the MAX3232 for hardware flow control. 4.2.4 Temperature Sensor An analog output thermal sensor (Microchip TC1074A, U4) is connected to one of the controller’s A/D channels. 4.2.5 USB Connectivity The Explorer 16 board includes a PIC18LF4550 USB microcontroller, which provides both USB connectivity and support for protocol translation. The PIC18LF4550 is hard-wired to the PIC24/dsPIC33F devices to provide three types of connectivity: • SPI™ of PIC18LF4550 to SPI1 of PIC24/dsPIC33F • I/O pins of PIC18LF4550 to ICSP™ pins of PIC24/dsPIC33F • I/O pins of PIC18LF4550 to JTAG pins of PIC24/dsPIC33F The type of connectivity depends on the firmware installed on the PIC18LF4550. At the time of initial release, the PIC18LF4550 is loaded with USB bootloader firmware, which permits easy upgrades of connectivity firmware over the USB. Installing this firmware is described in Appendix B. “Updating the USB Connectivity Firmware”. PIC24 and dsPIC33F devices both have some 5V tolerant input pins. If a 5V tolerant input is connected to the PIC18LF4550, protection diodes on the PIC18LF4550 device’s port pins will limit inputs to VDD. For more information on which pins of the 16-bit devices are 5V tolerant, refer to the appropriate device data sheet. 4.2.6 ICD Connector An MPLAB ICD 2 module can be connected by way of the modular connector (JP1) for low-cost debugging. The ICD connector utilizes port pins, RB6 and RB7 of the microcontroller, for in-circuit debugging. Jumper J7 decides the terminus of the ICD 2 connector. If the jumper is set to the “PIC24” side, JP1 communicates directly with RB6/RB7 of the PIM or on-board device (determined by S2). If the jumper is set to the “F4450” side, JP1 communicates with the on-board PIC18LF4550 USB device. 4.2.7 LCD The Explorer 16 board includes an alphanumeric LCD display with two lines of 16 characters each. The display is driven with three control lines (RD4, RD5 and RD15) and eight data lines (RE7:RE0). On PIC24 devices, the LCD is driven by the PMP module, not the I/O port. The Explorer 16 board has multiple LCD footprints and support options, although only one footprint is ever populated at one time. The Lumex LCM-SO1062 (populated at LCD4) is a 5V LCD with TTL input, and is used in the initial version of the Explorer 16 board. The Tianma TM162JCAWG1 (populated at LCD1) is a 3V LCD; it is anticipated to be used in future versions of the board. An alternate configuration option allows the use of RD3:RD0 as four of the data lines, instead of RE7:RE4. To do this, the user must cut the trace jumpers at R60/62/64/66 and create solder bridges from the pads for R61/63/65/67 (see Figure 4-1). Explorer 16 Development Board User’s Guide DS51589A-page 29 © 2005 Microchip Technology Inc. FIGURE 4-1: MODIFICATIONS TO R60-R67 FOR LCD CONFIGURATION (SCALE ENHANCED FOR VISIBILITY) 4.2.8 Graphic LCD The Explorer 16 also has a footprint and layout support for the Optrex 128 x 64 dot-matrix graphic LCD (part number F-51320GNB-LW-AB) and associated circuitry. This is the same display used in Microchip’s MPLAB PM3 programmer. 4.2.9 Switches Five push button switches provide the following functions: • S1: Active-low MCLR switch to hard reset the processor • S3: Active-low switch connected to RD6 (user-defined) • S4: Active-low switch connected to RD13 (user-defined) • S5: Active-low switch connected to RA7 (user-defined) • S6: Active-low switch connected to RD7 (user-defined) Switch S1 has a debounce capacitor, whereas S3 through S6 do not; this allows the user to investigate debounce techniques. When Idle, the switches are pulled high (+3.3V). When pressed, they are grounded. 4.2.10 Analog Input (Potentiometer) A 10 kΩ potentiometer is connected through a series resistor to AN5. It can be adjusted from VDD to GND to provide an analog input to one of the controller’s A/D channels. 4.2.11 LEDs Eight red LEDs (D2 through D9) are connected to PORTA of the PIM socket. The PORTA pins are set high to light the LEDs. These LEDs may be disabled by removing jumper JP2. 4.2.12 Oscillator Options The installed microcontroller has two separate oscillator circuits connected.The main oscillator uses an 8 MHz crystal (Y3) and functions as the controller’s primary oscillator. A second circuit, using a 32.768 kHz (watch type) crystal (Y2), functions as the Timer1 oscillator and serves as the source for the RTCC and secondary oscillator. The PIC18LF4550, at the heart of the USB subsystem, is independently clocked and has its own 20 MHz crystal (Y1). 4.2.13 Serial EEPROM A 25LC256 256K (32K x 8) serial EEPROM (U5) is included for nonvolatile firmware storage. It is also used to demonstrate SPI bus operation. R60 R61 R62 R63 R64 R65 R66 R67 Cut Traces Here Add Solder Bridges Here Explorer 16 Development Hardware © 2005 Microchip Technology Inc. DS51589A-page 30 4.2.14 PICkit 2 Connector Connector J14 provides the footprint for a 6-pin PICkit 2 programmer interface. This will provide a third low-cost programming option, besides MPLAB ICD 2 and the JTAG interface, when PICkit 2 support for larger devices become available in the future. 4.2.15 JTAG Connector Connector J13 provides a standard JTAG interface, allowing users to connect to and program the controller via JTAG. 4.2.16 PICtail™ Plus Card Edge Modular Expansion Connectors The Explorer 16 board has been designed with the PICtail™ Plus modular expansion interface, allowing the board to provide basic generic functionality and still be easily extendable to new technologies as they become available. PICtail Plus is based on a 120-pin connection divided into three sections of 30 pins, 30 pins and 56 pins. The two 30-pin connections have parallel functionality; for example, pins 1, 3, 5 and 7 have SPI1 functionality on the top 30-pin segment, with similar SPI2 functionality on the corresponding pins in the middle 30-pin segment. Each 30-pin section provides connections to all of the serial communications peripherals, as well as many I/O ports, external interrupts and A/D channels. This provides enough signals to develop many different expansion interfaces, such as Ethernet, Zigbee™, IrDA® and so on. The 30-pin PICtail Plus expansion boards can be used in either the top or middle 30-pin sections. The Explorer 16 board provides footprints for two edge connectors for daughter cards, one populated (J5, Samtec # MEC1-160-02-S-D-A) and one unpopulated (J6). The board also has a matching male edge connection (J9), allowing it to be used as an expansion card itself. 4.2.16.1 CROSSOVER CONNECTIONS FOR SPI AND UART The PICtail Plus interface allows two Explorer 16 boards to be connected directly to each other without any external connector. This provides 1-to-1 connection between the microcontrollers on the two boards, an interface that works well for many types of peripherals (I2C, PMP, etc.). However, certain serial peripheral modules, such as SPIs and UARTs, require cross-wire connections; that is, the TX (or SDO) pin of one controller must be connected to the RX (or SDI) of the other and vice versa. The Explorer 16 board uses two 74HCT4053 analog multiplexers to simplify the connections between itself and any daughter boards. U6 and U7 provide active control of the cross-wire capability on SPI1 and UART1, with a hardware flow control signal provided by three I/O pins. The multiplexers are controlled by the state of pins RB12, RB13 and RB14. When a control pin is high (the default state), the corresponding SPI1 or UART1 pin pairs are connected to their default pins on the PICtail Plus interface. When a control pin is asserted low, the corresponding pin pair functions are swapped. Table 4-1 details the relationship between the control pins and SPI1/UART1 functions on the interface. Explorer 16 Development Board User’s Guide DS51589A-page 31 © 2005 Microchip Technology Inc. TABLE 4-1: LOCATION OF SPI1 AND UART1 PINS ON PICtail™ PLUS INTERFACE Control Pin State UART1 Control Pins SPI1 Control Pin RB14 Control Pin RB13 Control Pin RB12 U1RX U1TX U1CTS U1RTS SDI1 SDO1 1 2 4 19 20 5 7 0 4 2 20 19 7 5 Note: When connecting SPI and UART peripherals on two Explorer 16 boards, use crossover connection on only one of the boards. Explorer 16 Development Hardware © 2005 Microchip Technology Inc. DS51589A-page 32 NOTES: EXPLORER 16 DEVELOPMENT BOARD USER’S GUIDE © 2005 Microchip Technology Inc. DS51589A-page 33 Appendix A. Explorer 16 Development Board Schematics A.1 INTRODUCTION This section provides detailed technical information on the Explorer 16 board. A.2 DEVELOPMENT BOARD BLOCK DIAGRAM FIGURE A-1: HIGH-LEVEL BLOCK DIAGRAM OF THE EXPLORER 16 DEVELOPMENT BOARD PIC24FJ128GA010 dsPIC33FJ256GP710 16x2 LCD Display PIC18LF4550 SPI* ICSP* JTAG* ICD/ICSP JTAG RS-232 Transceiver SPI EEPROM +3.3V and +5V Supply 9-15 VDC Switches Temperature Sensor LEDs POT Modular Expansion Connector USB PICtail™ Plus PICtail™ Plus * Hardware support only; firmware support for SPI™, JTAG and ICSP™ via USB are not available at this time. Explorer 16 Development Board Schematics © 2005 Microchip Technology Inc. DS51589A-page 34 A.3 DEVELOPMENT BOARD SCHEMATICS FIGURE A-2: EXPLORER 16 BOARD SCHEMATIC, SHEET 1 OF 8 (PIM SOCKET) VCAP/VDDCORE VDDCORE VSS VSS VDD 100-Pin PIM VSS VDD VSS VDD CVREF/AN10/RB10 AVDD AVSS VSS VDD VDD Explorer 16 Development Board User’s Guide DS51589A-page 35 © 2005 Microchip Technology Inc. FIGURE A-3: EXPLORER 16 BOARD SCHEMATIC, SHEET 2 OF 8 (BOARD MOUNTED PIC24FJ128GA010 MCU, WHEN INSTALLED) 10 μF .1 μF VCAP/VDDCORE VDD VSS PIC24FJ128GA010 VDD AVDD VDD VSS AVSS CVREF/AN10/RB10 VSS VDD VDD VSS VSS Explorer 16 Development Board Schematics © 2005 Microchip Technology Inc. DS51589A-page 36 FIGURE A-4: EXPLORER 16 BOARD SCHEMATIC, SHEET 3 OF 8 (MPLAB® ICD 2, JTAG, PICkit™ 2 AND PICtail™ Plus CONNECTORS) MPLAB® ICD 2 Connector .1 μF PICkit™ 2 Programmer Explorer 16 Development Board User’s Guide DS51589A-page 37 © 2005 Microchip Technology Inc. FIGURE A-5: EXPLORER 16 BOARD SCHEMATIC, SHEET 4 OF 8 (PICtail™ PLUS EDGE AND SOCKET CONNECTORS) Explorer 16 Development Board Schematics © 2005 Microchip Technology Inc. DS51589A-page 38 FIGURE A-6: EXPLORER 16 BOARD SCHEMATIC, SHEET 5 OF 8 (SWITCHES, MULTIPLEXERS AND POTENTIOMETER) VEE VCC .1 μF .1 μF VCC VEE .1 μF Explorer 16 Development Board User’s Guide DS51589A-page 39 © 2005 Microchip Technology Inc. FIGURE A-7: EXPLORER 16 BOARD SCHEMATIC, SHEET 6 OF 8 (EEPROM, TEMPERATURE SENSOR, LEDs, OSCILLATOR CIRCUITS AND POWER SUPPLY) .1 μF 25LC256 .1 μF TC1047A 22 pF 22 pF 32 kHz .1 μF 47 μF .1 μF 47 μF 47 μF .1 μF .1 μF .1 μF .1 μF .1 μF .1 μF .1 μF VCC VSS VDD VOUT VSS 8 MHz 22 pF 22 pF Explorer 16 Development Board Schematics © 2005 Microchip Technology Inc. DS51589A-page 40 FIGURE A-8: EXPLORER 16 BOARD SCHEMATIC, SHEET 7 OF 8 (USB AND UART SUBSYSTEMS) VUSB VSS VDD VDD VSS VSS VDD PIC18F4550_QFN44 VDD .1 μF .1 μF .1 μF .1 μF .1 μF .1 μF .1 μF .1 μF .1 μF .1 μF 22 pF 22 pF 20 MHz VBUS VCC Explorer 16 Development Board User’s Guide DS51589A-page 41 © 2005 Microchip Technology Inc. FIGURE A-9: EXPLORER 16 BOARD SCHEMATIC, SHEET 8 OF 8 (LCDs AND OPTIONAL LCD CONNECTIONS) Alternative LCD Configurations: 4.7 μF 4.7 μF 4.7 μF 4.7 μF 1 μF 1 μF 1 μF 1 μF 1 μF .1 μF VEE VO VCC VEE VCC VEE VEE VSS VDD VO Explorer 16 Development Board Schematics © 2005 Microchip Technology Inc. DS51589A-page 42 NOTES: EXPLORER 16 DEVELOPMENT BOARD USER’S GUIDE © 2005 Microchip Technology Inc. DS51589A-page 43 Appendix B. Updating the USB Connectivity Firmware B.1 INTRODUCTION The USB subsystem of the Explorer 16 Development Board is preprogrammed with USB bootloader firmware. This provides an easy method for upgrading the PIC18LF4550 firmware to support ICSP, JTAG and SPI connectivity to PIC24 and dsPIC33F devices. This chapter describes how to upgrade the PIC18LF4550 device’s firmware with the PICkit 2 software. The same process can be used to upgrade the PIC18LF4550 device’s firmware when updates and new firmware packages become available. B.2 UPDATING THE PICkit 2 MICROCONTROLLER PROGRAMMER Before beginning, it will be necessary to obtain and install the PICkit 2 programmer software. Complete instructions for installing and using the programmer software application is provided in the PICkit™ 2 Microcontroller Programmer User’s Guide (DS51553). The programmer and user’s guide, as well as the latest version of the PICkit 2 operating system firmware, are available from the Microchip corporate web site, www.microchip.com. To update the USB firmware: 1. If not done already, download the latest PICkit 2 operating system software from the Microchip web site. 2. On the Explorer 16 board, install a jumper between pins 9 and 10 of the JTAG connector (J13). 3. Press and release MCLR (S1). This places the USB subsystem in Bootloader mode and makes it ready to accept new code. 4. Connect the Explorer 16 board to the PC via a standard USB cable. 5. Launch the PICkit 2 programmer software. From the menu bar, select Tools > Download PICKit 2 Operating System (Figure B-1). FIGURE B-1: DOWNLOAD PICkit™ 2 OPERATING SYSTEM Updating the USB Connectivity Firmware © 2005 Microchip Technology Inc. DS51589A-page 44 6. Browse to the directory where the latest operating system firmware was saved (Figure B-2). FIGURE B-2: SELECT PICkit™ 2 OPERATING SYSTEM 7. Select the PK2_Explorer16_*.hex file and click the Open button. The progress of the update is displayed in the status bar of the programming software. When the update completes successfully, the status bar displays “Operating System Verified”. The update is now complete. B.3 OTHER USB FIRMWARE UPDATES It is anticipated that various USB connectivity firmwares will be made available in the future. Users are encouraged to periodically check the Microchip web site (www.microchip.com) for new and revised code. EXPLORER 16 DEVELOPMENT BOARD USER’S GUIDE © 2005 Microchip Technology Inc. DS51589A-page 45 Index B Build Options............................................................ 16 C Configuration Bits..................................................... 19 Crossover Connections (Serial Communications) ...................................8, 30 Customer Change Notification Service ...................... 5 Customer Support ...................................................... 5 D Documentation Conventions........................................................ 2 Layout ................................................................. 1 dsPIC33 Tutorial Program........................................ 25 dsPIC33F Tutorial Program Flowchart .......................................................... 26 E Explorer 16 Development Board Block Diagram .................................................. 33 Layout ................................................................. 9 Schematics ..................................................34–41 Explorer 16 Programming Tutorial ........................... 11 Building the Code ............................................. 16 Creating the Project .......................................... 12 Programming the Device .................................. 19 F Free Software Foundation ......................................... 4 G GNU Language Tools ................................................ 4 H Hardware Features Analog Potentiometer ....................................8, 29 ICD Connector ...............................................8, 28 JTAG Connector ............................................8, 30 LCD, Alphanumeric........................................8, 28 LCD, Graphic .................................................8, 29 LEDs ..............................................................8, 29 Multiplexers....................................................8, 30 Oscillator Options ..........................................8, 29 PICkit 2 Connector.........................................8, 30 PICtail Plus Card Edge Connectors...............8, 30 Power Indicator LED........................................... 8 Power Supply.................................................8, 27 Processor Support ........................................ 8, 27 Prototype Area .................................................... 8 RS-232 Serial Port ........................................ 8, 28 Serial EEPROM............................................ 8, 29 Switches........................................................ 8, 29 Temperature Sensor ..................................... 8, 28 USB Connectivity .......................................... 8, 28 I Internet Address......................................................... 4 L Language Toolsuite.................................................. 13 M Microchip Internet Web Site ....................................... 4 MPLAB ICD 2........................................................... 10 MPLAB IDE Simulator, Editor User’s Guide............... 4 P PIC24 Tutorial Program ........................................... 23 Flowchart .......................................................... 24 PICtail Plus Edge Connectors Use with Crossover Serial Connections........................................ 30 Project ...................................................................... 12 Project Wizard.......................................................... 12 R Reading, Recommended ........................................... 3 Readme...................................................................... 3 Reference Documents ............................................. 10 S Schematics......................................................... 34–41 U USB Connectivity ...................................................... 28 Updating the USB Connectivity Firmware............................................. 43 W Warranty Registration ................................................ 2 Workspace ............................................................... 12 WWW Address........................................................... 4 DS51589A-page 46 © 2005 Microchip Technology Inc. AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256 ASIA/PACIFIC India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 WORLDWIDE SALES AND SERVICE 10/31/05 MSP-EXP430F5529 Experimenter Board User's Guide Literature Number: SLAU330A May 2011–Revised June 2011 2 SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Contents Preface ....................................................................................................................................... 5 1 Getting Started ................................................................................................................... 7 1.1 MSP-EXP430F5529 Experimenter Board Introduction ............................................................. 7 1.2 Kit Contents .............................................................................................................. 8 2 User Experience Software .................................................................................................... 9 2.1 Introduction ............................................................................................................... 9 2.2 Main Menu ............................................................................................................... 9 2.3 Clock ..................................................................................................................... 10 2.4 Games ................................................................................................................... 10 2.5 Power Tests ............................................................................................................ 10 2.6 Demo Apps ............................................................................................................. 11 2.7 SD Card Access ....................................................................................................... 12 2.8 Settings Menu .......................................................................................................... 12 3 Software Installation and Debugging ................................................................................... 13 3.1 Software ................................................................................................................. 13 3.2 Download the Required Software .................................................................................... 13 3.3 Working With the Example Software ................................................................................ 13 4 MSP-EXP430F5529 Hardware .............................................................................................. 17 4.1 Hardware Overview .................................................................................................... 17 4.2 Jumper Settings and Power .......................................................................................... 18 4.3 eZ-FET Emulator ....................................................................................................... 21 4.4 MSP-EXP430F5529 Hardware Components ...................................................................... 21 5 Frequently Asked Questions, References, and Schematics .................................................... 24 5.1 Frequently Asked Questions ......................................................................................... 24 5.2 References .............................................................................................................. 24 5.3 Schematics and BOM ................................................................................................. 25 SLAU330A–May 2011–Revised June 2011 Table of Contents 3 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com List of Figures 1 MSP-EXP430F5529 Experimenter Board ............................................................................... 7 2 User Experience Navigation ............................................................................................... 9 3 Selecting a CCS Workspace............................................................................................. 14 4 Opening Existing Project ................................................................................................. 14 5 Simple Hardware Overview .............................................................................................. 17 6 Hardware Block Details ................................................................................................... 18 7 Common Power Jumper Settings ....................................................................................... 18 8 Visual Power Schematic.................................................................................................. 20 9 MSP430 Current Measurement Connection ........................................................................... 21 10 Schematics (1 of 7)........................................................................................................ 25 11 Schematics (2 of 7)........................................................................................................ 26 12 Schematics (3 of 7)........................................................................................................ 27 13 Schematics (4 of 7)........................................................................................................ 28 14 Schematics (5 of 7)........................................................................................................ 29 15 Schematics (6 of 7)........................................................................................................ 30 16 Schematics (7 of 7)........................................................................................................ 31 List of Tables 1 MSP-EXP430F5529 Jumper Settings and Functionality ............................................................. 19 2 Push Buttons, Potentiometer, and LED Connections................................................................. 22 3 Pinning Mapping for Header J4.......................................................................................... 23 4 Pin Mapping for Header J5............................................................................................... 23 5 Pin Mapping for Header J12 ............................................................................................. 23 6 Bill of Materials............................................................................................................. 32 4 List of Figures SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Preface SLAU330A–May 2011–Revised June 2011 Read This First If You Need Assistance The primary sources of information for MSP430 devices are the data sheets and the family user's guides. The most up-to-date versions of these documents can be found at www.ti.com/msp430. Information specific to the MSP-EXP430F5529 Experimenter Board can be found at www.ti.com/usbexp. Customer support for MSP430 devices and the MSP-EXP430F5529 Experimenter Board is provided by the Texas Instruments Product Information Center (PIC), as well as on the TI E2E (Engineer-2-Engineer) Forum at the link below. Contact information for the PIC can be found on the TI web site at: support.ti.com. The MSP430 Specific E2E forum is located at: community.ti.com/forums/12.aspx. Related Documentation from Texas Instruments MSP-EXP430F5529 Experimenter Board User's Guide (SLAU330) MSP-EXP430F5529 Experimenter Board User Experience Software MSP-EXP430F5529 Experimenter Board Quick Start Guide (SLAU339) MSP-EXP430F5529 Experimenter Board PCB Design Files (SLAR055) MSP430F552x Code Examples (SLAC300) FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user, at his own expense, will be required to take whatever measures may be required to correct this interference. SLAU330A–May 2011–Revised June 2011 Preface 5 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated 6 Read This First SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated User's Guide SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 1 Getting Started 1.1 MSP-EXP430F5529 Experimenter Board Introduction The MSP-EXP430F5529 Experimenter Board is a development platform based on the MSP430F5529 with integrated USB. The Experimenter Board showcases the abilities of the latest family of MSP430s and is perfect for learning and developing USB-based applications using the MSP430. The features include a 102x64 dot-matrix LCD, microSD memory card interface, 3-axis accelerometer, five capacitive-touch pads, RF EVM expansion headers, nine LEDs, an analog thumb-wheel, easy access to spare F5529 pins, integrated Spy-Bi-Wire flash emulation module, and standard full JTAG pin access. The kit is pre-programmed with an out-of-box demo to immediately demonstrate the capabilities of the MSP430 and Experimenter Board. This document details the hardware, its use, and the example software. Figure 1. MSP-EXP430F5529 Experimenter Board The MSP-EXP430F5529 Experimenter Board is available for purchase from the TI eStore: https://estore.ti.com/MSP-EXP430F5529-MSP430F5529-Experimenter-Board-P2413C43.aspx SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 7 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Getting Started www.ti.com 1.2 Kit Contents • MSP-EXP430F5529 Experimenter Board • Two mini-USB cables • Battery holder • 1GB microSD card • Quick start guide 8 MSP-EXP430F5529 Experimenter Board SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com User Experience Software 2 User Experience Software 2.1 Introduction The MSP-EXP430F5529 Experimenter Board arrives with a User Experience application installed to demonstrate a few of the capabilities of the MSP430F5529. Set the power switch to "LDO", and connect your PC to the "5529 USB" connection as shown in Figure 2. A splash screen displaying the TI logo should appear on the LCD. Wait approximately three seconds, or press either the S1 or S2 button, to display the Main Menu. Use the thumb wheel to navigate up and down the menu items on the LCD screen. Press the S1 pushbutton to enter a selection, or press the S2 pushbutton to cancel. Figure 2. User Experience Navigation 2.2 Main Menu The main menu displays a list of applications and settings that demonstrate key features of the MSP430F5529. Use the thumb wheel on the bottom right of the PCB to scroll up and down through the menu options. Use the push-buttons to enter and exit menu items. Press S1 to enter a menu item. Press S2 to return to a previous menu or to cancel an operation. Each application in the main menu is described in the following sections. SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 9 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated User Experience Software www.ti.com 2.3 Clock Select this option from the main menu to bring up the Clock sub-menu. Press S2 to return to the previous menu. NOTE: The User Experience software initializes the real-time clock to 04:30:00 - 01/01/2011 when powered is applied to the MSP430. Digital Clock: Displays an image of a digital watch with the current time and date. Analog Clock: Displays an image of an analog clock with the current time. Set Time: Allows the user to set the current time. Use the scroll wheel to change the value of the current selection. Press push-button S1 is used to advance to the next field. The clock changes take affect after the last field is updated. 2.4 Games Select this option from the main menu to bring up the Games sub-menu. Press S2 to return to the previous menu. Defender: The player controls a small spaceship. The object of the game is to fly through a tunnel without hitting the walls and to successfully navigate around mines scattered throughout the tunnel. Press S1 or S2 to begin the game. Use the wheel to move the ship up and down and press S1 or S2 to shoot a missile. As the game progresses, the tunnel gets narrower and the game speeds up. After the player's ship crashes, the score is displayed. Simon: A version of the famous memory game. The objective of the game is to match a randomly generated sequence of LEDs displayed on the touch pads. After the sequence is displayed, the user must touch the correct pads in the same sequence. The game begins with a single-symbol sequence and adds an additional symbol to the sequence after each successful response by the user. The game ends when the user incorrectly enters a sequence. The number of turns obtained in the sequence is then displayed. Tilt Puzzle: A version of the famous "8-puzzle" game. The game consists of a 3 by 3 grid with eight numbers and one empty space. The game utilizes the on-board accelerometer to shift numbers up-down and left-right. The objective of the game is to have the sum of the numbers in each row and column equal to twelve. Press S1 to begin a new game if the current game is unsolvable. The nature of the game is that there is a 50% probability the game is not solvable. 2.5 Power Tests Select this option from the main menu to bring up the Power Test sub-menu. Press S2 to return to the previous menu. The Power Test menu contains two demonstrations that allow the user to externally measure the current consumption of the MSP430 in both active mode and low-power mode. Current consumption can be measured using a multi-meter with current measuring capabilities (ammeter). Remove the jumper on "430 PWR" (JP6) and connect a multi-meter in series with the MSP430 VCC supply. This connection can be made using the two large vias near the "430 PWR" text on the PCB. See Section 4 for more details on this connection. Active Mode: Demo for measuring active mode current of the MSP430. Instructions are presented on screen. Press S1 to continue to the application. Press S2 to return to the Power Tests sub-menu. The Active Mode menu consists of two columns. The left column controls the core voltage (VCORE) of the MSP430F5529, and the right column controls MCLK. The right column displays only those MCLK frequencies that are valid for the current VCORE setting. The capacitive touch pads at the bottom of the board control which column is currently active. The wheel scrolls through the options in the active column. 10 MSP-EXP430F5529 Experimenter Board SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com User Experience Software Press S1 to enter Measurement Mode. While in measurement mode, measure the current by attaching a multi-meter across the 430 PWR holes and removing the 430 PWR jumper J6. Replace the 430 PWR jumper after making the measurement, then press S1 or S2 to return to the Active Mode menu. Press S2 to return to the Power Tests sub-menu Low Power Mode: Selecting Low Power Mode takes the user to an information screen with directions on how to navigate the Low Power Mode menu. Press S1 to continue on to the application. Press S2 to return to the Power Tests sub-menu. In the Low Power Mode menu, use the wheel to select a low-power mode option, then press S1 to enter low-power mode. While in low-power mode, measure the current by attaching a multi-meter across the 430 PWR holes and removing the 430 PWR jumper. Press S1 or S2 to return to the Low Power Mode menu. 2.6 Demo Apps Select this option from the main menu to bring up the Demo Apps sub-menu, which allows access to various demo applications. Many of them require a USB connection. Use the wheel to select one of the options and then press S1 to enter the application. Press S2 to return to the main menu. Terminal Echo uses the CDC stack to communicate with a hyperterminal on the PC. USB Mouse uses the HID stack to interface with the PC. Terminal Echo: Select Terminal Echo to display an informational screen and connects to the PC. Make sure to connect a USB cable from the USB port labeled "5529 USB" to the host PC. Open a hyperterminal window and connect to the MSP430. Text that is typed in the hyperterminal window is echoed back to the terminal and is displayed on the LCD screen of the Experimenter Board. Press S2 to exit and return Demo Apps sub-menu. USB Mouse: Select USB Mouse to display an informational screen and connects to the PC. Make sure to connect a USB cable from the USB port labeled "5529 USB" to the host PC. The MSP430 now acts as the mouse for the PC. Tilt the board to move the mouse around the screen, and press S1 to click. Press S2 to exit and return Demo Apps sub-menu. USB microSD: Select USB microSD to connect to the PC as a mass storage device. Make sure to connect a USB cable from the USB port labeled "5529 USB" to the host PC. The MSP430 shows as an external drive (or removable drive) for the PC. Press S2 to return to the Demo Apps sub-menu. Touch Graph: Select Touch Graph to display an instruction screen for a very short time and then launch the application. Touch the capacitor key pads with varying pressures to see the varying capacitance being displayed as bars with varying heights. Slide a finger over multiple capacitor key pads to observe the change in heights of bars with respect to the current position of the finger and also the effect of capacitance from neighboring pads. Press S2 to exit and return Demo Apps sub-menu. Touch Slide: Select Touch Slide to display an instruction screen for a very short time and then launch the application. Touch the capacitor key pads with varying pressures to see the varying capacitance being displayed as bars with varying heights. Slide a finger over multiple capacitor key pads to observe the change in heights of bars with respect to the current position of the finger and also the effect of capacitance from neighboring pads. Press S2 to exit and return Demo Apps sub-menu. Demo Cube: Select Demo Cube to launch the demo cube application. Read the instructions and press S1 to start the application. There are two modes. Use S1 to toggle between them. In the first mode, the cube randomly rotates by itself. In the second mode, the cube can be rotated by tilting the board. This mode uses the accelerometer. Press S2 to exit and return Demo Apps sub-menu. SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 11 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated User Experience Software www.ti.com 2.7 SD Card Access Select SD Card Access to access a microSD card placed in the SD card reader at the top of the board. If no SD card is present, a warning screen is displayed. When an SD card is present, the screen displays a list of the contents of the card. Directories are denoted by "". Use the wheel to scroll through the list and select files or directories to open by pressing S1. When a file is open, use the wheel to scroll further through the file. Press S2 to close the current file or directory. Press S2 while in the root directory to return to the main menu. 2.8 Settings Menu Select Settings to modify the display settings for the Experimenter Board. Use the wheel to select the setting to modify and press S1 to enter. Press S2 to return to the main menu. Contrast: Modify the contrast of the LCD by turning the wheel. When first entering the menu, the contrast remains unchanged for a few seconds to allow the user to read the instructions and then changes to the setting for the current position of the wheel. After the contrast is set at the desired level, press S2 to return to the Settings sub-menu. Backlight: Modify the brightness of the backlight by turning the wheel. There are 12 brightness settings, from having the backlight turned off up to full brightness. After the backlight is set at the desired level, press S2 to return to the Settings sub-menu. Calibrate Accel: Sets the "default" position for the accelerometer. An instruction screen is shown first. For best results, set the board on a flat surface. Press S1 to start calibrations. The accelerometer readings at that point in time are stored to flash and are subtracted from the subsequent accelerometer readings of other applications like USB Mouse and USB Tilt Puzzle. SW Version: Displays the current version of the firmware loaded on the Experimenter Board. LEDs & Logo: Lights all the LEDs on the board. There are one red, one yellow, one green, and five blue LEDs on the capacitive touch pads. This provides a method to determine whether or not all the LEDs are in working condition. The screen also displays the TI Bug and a USB Flash Drive logo on the screen. 12 MSP-EXP430F5529 Experimenter Board SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com Software Installation and Debugging 3 Software Installation and Debugging 3.1 Software Texas Instruments' Code Composer Studio (CCS) is an MSP430 integrated development environment (IDE) designed specifically to develop applications and program MSP430 devices. CCS, CCS Core Edition, and IAR Embedded Workbench can all be used to evaluate the example software for the Experimenter Board. The compiler limitation of 8KB prevents IAR KickStart from being used for the evaluation of the example software. The example software, titled "User Experience," is available online as MSP-EXP430F5529 Experimenter Board User Experience Software. 3.2 Download the Required Software Different development software tools are available for the MSP-EXP430F5529 Experimenter Board development board. IAR Embedded Workbench KickStart and Code Composer Studio (CCS) are both available in a free limited version. IAR Embedded Workbench KickStart allows 8KB of C-code compilation. CCS is limited to a code size of 16KB. The software is available at www.ti.com/msp430. The firmware is larger than IAR KickStart's 8KB limit, so a full license of IAR Workbench is required to compile the application using IAR. A 30-day evaluation version of IAR is also available from http://supp.iar.com/Download/SW/?item=EW430-EVAL. This document describes working with Code Composer Studio (CCS). There are many other compilers and integrated development environments (IDEs) for MSP430 that can be used with the MSP-EXP430F5529 Experimenter Board, including Rowley Crossworks and MSPGCC. However, the example project has been created using Code Composer Studio (CCS) and IAR. For more information on the supported software and the latest code examples visit the online product folder (http://focus.ti.com/docs/toolsw/folders/print/msp-exp430f5529.html). 3.3 Working With the Example Software The MSP-EXP430F5529 example software is written in C and offers APIs to control the MSP430F5529 chip and external components on the MSP-EXP430F5529 Experimenter Board. New application development can use this library for guidance. The example software can be downloaded from the MSP-EXP430F5529 tools page, MSP-EXP430F5529 Experimenter Board User Experience Software. The zip package includes the MSP-EXP430F5529 example software. The code is ready for compilation and execution. To modify, compile, and debug the example code the following steps should be followed: 1. If you have not already done so, download the sample code from the MSP-EXP430F5529 tools page. 2. Install 5529UE-x.xx-Setup.exe installation package to the PC. 3. Connect the MSP-FET430UIF programmer to the PC. If you have not already done so, install the drivers for the programmer. 4. Connect one end of the 14-pin cable to JTAG programmer and another end to the JTAG header on the board. 5. Open CCS and select a workspace directory (see Figure 3). SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 13 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Software Installation and Debugging www.ti.com Figure 3. Selecting a CCS Workspace • Select Project > Import Existing CCS/CCE Eclipse Project. • Browse to the extracted project directory. The project should now show up in the Projects list (see Figure 4). • Make sure the project is selected, and click Finish. Figure 4. Opening Existing Project The project is now open. To build, download, and debug the code on the device on the MSP-EXP430F5529 Experimenter Board, select Target > Debug Active Project or click the green 'bug' button. 14 MSP-EXP430F5529 Experimenter Board SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com Software Installation and Debugging You may be prompted to update the firmware on the MSP-FET430UIF programmer. Do not be concerned; click the button that says Update, and the program download should continue as expected. NOTE: To begin developing your own application, follow these steps: 1. Download and install a supported IDE: Code Composer Studio – Free 16KB IDE: www.ti.com/ccs IAR Embedded Workbench KickStart – Free 8KB IDE: www.ti.com/iar-kickstart 2. Connect the MSP-EXP430F5529 Experimenter Board "eZ-FET" USB to the PC. 3. Download and debug your application. SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 15 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Software Installation and Debugging www.ti.com 3.3.1 Basic Code Structure CTS "Capacitive Touch Sensing" library with functions related to the capacitive touch pads. CCS CCS-specific project files CCS_Code_Size_Limited CCS-specific project files for 16kb code size limited version F5xx_F6xx_Core_Lib Core Libraries FatFs Stack for the FAT file system used by SD Card IAR IAR-specific project files MSP-EXP430F5529_HAL Provides an abstraction layer for events like button presses, etc. HAL_AppUart Functions for controlling application UART HAL_Board Experimenter Board port initialization and control HAL_Buttons Driver for the buttons on the Experimenter Board HAL_Cma3000 Functions required to use on-board accelerometer HAL_Dogs102x6 Driver for the DOGS 102x64 display HAL_Menu Used to create the menus for the example software and applications HAL_SDCard Driver for the SD Card module HAL_Wheel Driver for the scroll (thumb) wheel USB USB stack for the Experimenter Board UserExperienceDemo Files related to the example software provided with the board 5xx_ACTIVE_test Runs a RAM test Clock Displays analog and digital clocks. Also provides a function to set time and date. Demo_Cube Displays a auto/manual rotating cube (uses accelerometer) DemoApps Contains the demos for capacitive touch EchoUsb HyperTerminal application LPM Provides options for various low-power modes MassStorage Use microSD as external storage on computer menuGames Play LaunchPad Defender or Simon Puzzle Play Tilt-puzzle Mouse Use the Experimenter Board as a mouse PMM Active low-power modes. Choose VCORE and MCLK settings. PowerTest Test the current consumption of various low-power modes Random Random number generator SDCard Access microSD card contents on the Experimenter's Board Settings Options to set various parameters like contrast, brightness, etc. UserExperience.c Main MSP-EXP430F5529 Experimenter Board file MSP-EXP430F5529 User Experience Manifest.pdf readme.txt 16 MSP-EXP430F5529 Experimenter Board SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com MSP-EXP430F5529 Hardware 4 MSP-EXP430F5529 Hardware 4.1 Hardware Overview Figure 5 and Figure 6 show the functional blocks and connections of the MSP-EXP430F5529 Experimenter Board. The area of the PCB labeled as "eZ430-FET Emulator" and bordered by a thick broken line on the PCB silk screen is an integrated TI Flash Emulation Tool (FET) which is connected to the Experimenter Board by the jumpers on JP16. This module is similar to any eZ430 emulator, and provides real-time in-system Spy-Bi-Wire programming and debugging via a USB connection to a PC. Using the eZ430-FET Emulator module eliminates the need for using an external MSP430 Flash Emulation Tool (MSP-FET430UIF). However, full speed 4-wire JTAG communication is only possible with a MSP-FET430UIF connected to the "5529 JTAG" header. For additional details on the installation and usage of the Flash Emulation Tool, Spy-Bi-Wire and JTAG, see the MSP430 Hardware Tools User's Guide (SLAU278). Figure 5. Simple Hardware Overview SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 17 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated MSP-EXP430F5529 Hardware www.ti.com Figure 6. Hardware Block Details 4.2 Jumper Settings and Power Figure 7 shows the common jumper settings, depending on the power source for the MSP-EXP430F5529 Experimenter Board. Figure 7. Common Power Jumper Settings 18 MSP-EXP430F5529 Experimenter Board SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com MSP-EXP430F5529 Hardware There are also other jumpers available for current measurement, disconnection of certain peripherals, and other advanced options (see Table 1). The black line on the board below the jumpers JP8 (LDO) and JP11 (JTAG) indicates the default jumper position. Table 1. MSP-EXP430F5529 Jumper Settings and Functionality Header Functionality When Jumper Present Functionality When Jumper Absent JP2 – POT Connects pin P8.0 to potentiometer Disconnects pin P8.0 to potentiometer JP3 – LED1 Connects pin P1.0 to LED1 Disconnects pin P1.0 to LED1 JP6 – 430 PWR Provides power to MSP430F5529. Also used to measure current MSP430F5529 is not powered. consumption of the MSP430F5529. NOTE: The two large vias near the "430 PWR" label on the PCB are connected to JP6 as well. These vias can be used to easily connect a test lead onto the PCB for current consumption measurement. JP7 – SYS PWR Provides power to the entire MSP-EXP430F5529 board. Also MSP-EXP430F5529 Experimenter used to measure current consumption of the entire board. Board system devices are not powered. JP8 – LDO Only applicable when powering via "5529 USB" connection. No connection to MSP430 VCC when powered via "5529 USB". ALT (Default): Connects the alternate LDO (TPS73533) to the MSP430 VCC. INT: Connects the internal 'F5529 LDO to the MSP430 VCC. JP11 – JTAG Only applicable when powering via JTAG connection. JTAG tool does NOT provide power to system. EXT (Default): JTAG tool does NOT provide power to system. INT: JTAG tool will provide power to system. JP14 – RF PWR Connects system VCC to the RF headers: J12, J13, and RF2. RF headers: J12, J13, and RF2 do not have power. JP15 – USB PWR Connects USB 5-V power to MSP430F5529 and Alternate LDO USB 5-V power not connected to (TPS73533). system. JP16 – eZ-FET DVCC: Connects MSP430 V No connection between CC to eZ-FET Connection MSP430F5529 and the eZ-FET. TXD / RXD: Connects UART between F5529 and eZ-FET. RST / TEST: Connects Spy-Bi-Wire JTAG between F5529 and eZ-FET. SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 19 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated MSP-EXP430F5529 Hardware www.ti.com Figure 8 shows a visual diagram of the power connections for the MSP-EXP430F5529 Experimenter Board. Care should be observed when using multiple power sources such as USB and a battery at the same time. This could lead to the battery being charged if the power settings are not correct. Figure 8. Visual Power Schematic 20 MSP-EXP430F5529 Experimenter Board SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com MSP-EXP430F5529 Hardware Figure 9 shows a method of connecting a multi-meter to the MSP-EXP430F5529 to measure the current of the MSP430F5529. Figure 9. MSP430 Current Measurement Connection 4.3 eZ-FET Emulator The connection between the eZ-FET emulator and the MSP-EXP430F5529 can be opened by removing the jumpers on JP16. This is necessary only to ensure there is no interaction between the two sub-systems. The eZ-FET Emulator can program other eZ430 tools such as the eZ430-F2013 target board as well. A six-pin header on J17 would need be installed on the PCB for this feature. The USB interface on the eZ-FET emulator also allows for UART communication with a PC host, in addition to providing power to Experimenter Board when the power switch is set to 'eZ'. The USCI module in the MSP430F5529 supports the UART protocol that is used to communicate with the TI TUSB3410 device on the eZ-FET emulator for data transfer to the PC. 4.4 MSP-EXP430F5529 Hardware Components 4.4.1 Dot-Matrix LCD The EA DOGS102W-6 is a dot-matrix LCD with a resolution of 102x64 pixels. The LCD has a built-in back-light driver that can be controlled by a PWM signal from the MSP430F5529, pin P7.6. The MSP430F5529 communicates with the EA DOGS102W-6 via an SPI-like communication protocol. To supplement the limited set of instructions and functionalities provided by the on-chip LCD driver, an LCD driver has been developed for the MSP430F5529 to support additional functionalities such as font set and graphical utilities. More information on the LCD can be obtained from the manufacturer's data sheet. SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 21 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated MSP-EXP430F5529 Hardware www.ti.com 4.4.2 Push Buttons, Potentiometer, and LEDs Table 2 describes the pin connections for the potentiometer, push-button switches, and the on-board LEDs. Table 2. Push Buttons, Potentiometer, and LED Connections Peripheral Pin Connection Potentiometer Wheel P8.0 Switch 1 (S1) P1.7 Switch 2 (S2) P2.2 RESET Switch (S3) RST / NMI LED1 P1.0 LED2 P8.1 LED3 P8.3 Capacitive Touch Pad 1 (Cross) P1.1 Capacitive Touch Pad 2 (Square) P1.2 Capacitive Touch Pad 3 (Octagon) P1.3 Capacitive Touch Pad 4 (Triangle) P1.4 Capacitive Touch Pad 5 (Circle) P1.5 4.4.3 Wireless Evaluation Module Interface Included in the communication peripherals are the headers that support the CC-EM boards from TI. The transceiver modules connect to the USCI of the MSP430F5529 configured in SPI mode using the UCB0 peripheral. Libraries that interface the MSP430 to these transceivers are available at www.ti.com/msp430 under the Code Examples tab. The RF PWR jumper must be populated to provide power to the EM daughterboard. The following radio daughter cards are compatible with the MSP-EXP430F5529 Experimenter Board: • CC1100EMK/CC1101EMK – Sub-1-GHz radio • CC2500EMK – 2.4-GHz radio • CC2420EMK/CC2430EMK – 2.4-GHz 802.15.4 [SoC] radio • CC2520EMK/CC2530EMK – 2.4-GHz 802.15.4 [SoC] radio • CC2520 + CC2591 EM (if R4 and R8 0-Ω resistors are connected) NOTE: Future evaluation boards may also be compatible with the header connections. 4.4.4 eZ430-RF2500T Interface The eZ430-RF2500T module can be attached to the MSP-EXP430F5529 Experimenter Board in one of two ways – through an 18-pin connector (J12 – eZ RF) or a 6-pin connector (J13 – eZ RF Target). The pins on the eZ430-RF2500T headers are multiplexed with the pins on the CC-EM headers, which allows the EZ430-RF2500T module to behave identically to a CC-EM daughterboard. Power must be provided to the EZ430-RF2500T module by setting the jumper RF PWR (JP14). The eZ430-RF2500T connection should always be made with the antenna facing off of the board. For more information on the connections to the required eZ430-RF2500T, see the eZ430-RF2500 Development Tool User's Guide (SLAU227), available through www.ti.com/ez430. 22 MSP-EXP430F5529 Experimenter Board SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com MSP-EXP430F5529 Hardware 4.4.5 Three-Axis Accelerometer The MSP-EXP430F5529 Experimenter Board includes a VTI digital three-axis accelerometer (part number CMA3000-D01). The accelerometer supports SPI communication and outputs data for each X, Y and Z axis. The accelerometer is powered through pin P3.6. This interface, especially in conjunction with other on-board interfaces such as the LCD, enables several potential applications such as USB mouse movement emulation and tilt sensing. The example software used the accelerometer for the Tilt Puzzle, Demo Cube, and USB Mouse. For more information on the accelerometer chip, see the manufacturer's data sheet (http://www.vti.fi). 4.4.6 Pin Access Headers The MSP-EXP430F5529 Experimenter Boards includes three headers (J4, J5, and J12) that can be used as additional connections to external hardware or for signal analysis during firmware development. All pins except the GND pin are internally selectable as either general purpose input/output pins or as described in the device datasheet. Table 3. Pinning Mapping for Header J4 Pin Description Port Pin Port Pin Pin Description Vcc VCC P6.6 CB6 / A6 UCA1RXD / UCA1SOMI P4.5 P8.1 GPIO – LED2 UCA1TXD / UCA1SIMO P4.4 P8.2 GPIO – LED3 GPIO P4.6 P8.0 GPIO – POT GPIO P4.7 P4.5 UCA1RXD / UCA1SOMI A9 / VREF- / VeREF- P5.1 P4.4 UCA1TXD / UCA1SIMO GND GND P6.7 CB7 / A7 Table 4. Pin Mapping for Header J5 Pin Description Port Pin Port Pin Pin Description VCC VCC P7.0 CB8 / A12 UCB1SOMI / UCB1SCL - SD P4.2 P7.1 CB9 / A13 UCB1SIMO / UCB1SDA - LCD/SD P4.1 P7.2 CB10 / A14 UCB1CLK / UCA1STE - LCD/SD P4.3 P7.3 CB11 / A15 UCB1STE / UCA1CLK - RF P4.0 P4.1 UCB1SIMO / UCB1SDA - LCD/SD TB0OUTH / SVMOUT - SD P3.7 P4.2 UCB1SOMI / UCB1SCL - SD GND GND P7.7 TB0CLK / MCLK Table 5. Pin Mapping for Header J12 Pin Description Port Pin Port Pin Pin Description (RF_STE) P2.6 P3.0 (RF_SIMO) (RF_SOMI) P3.1 P3.2 (RF_SPI_CLK) TA2.0 P2.3 P2.1 TA1.2 TB0.3 P7.5 GND GND GPIO P4.7 P2.4 TA2.1 (RXD) P4.5 P4.6 GPIO (TXD) P4.4 P4.0 UCx1xx (LED1) P1.0 P2.0 TA1.1 GND GND RF_PWR RF_PWR SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 23 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Frequently Asked Questions, References, and Schematics www.ti.com 5 Frequently Asked Questions, References, and Schematics 5.1 Frequently Asked Questions 1. Which devices can be programmed with the Experimenter Board? The MSP-EXP430F5529 board is designed specifically to demonstrate the MSP430F5529. 2. The MSP430F5529 is no longer accessible via JTAG. Is something wrong with the device? Verify that the jumpers are configured correctly. See Section 4 for jumper configuration. Verify that the target device is powered properly. If the target is powered locally, verify that the supplied VCC is sufficient to power the board. Check the device data sheet for the specification. 3. I did every step in the previous question but still could not use or communicate with the device. Improper programming of the device could lead to a JTAG total lockup condition. The cause of this problem might be an incorrect device selection when creating a new project in CCS (select MSP430F5529) or programming the device without a stable power source (low battery, switching the Power Selector while programming, or absence of the MSP430 power jumper JP6 during programming). To solve this, completely reset the device. First unplug all power sources and connections (JTAG and USB cables). Set the Power Selector Switch to FET mode. Use a jumper cable to briefly short one of the GND test points with the 430 PWR test point. The device should now be released from the lockup state. 4. Does the Experimenter board protect against blowing the JTAG fuse of the target device? No. Fuse blow capability is inherent to all flash-based MSP430 devices to protect user's intellectual property. Care must be taken to avoid the enabling of the fuse blow option during programming, because blowing the fuse would prevent further access to the MSP430 device via JTAG. 5. I am measuring system current in the range of 30 mA, is this normal? The LCD and the LCD backlight require a large amount of current (approximately 20 mA to 25 mA) to operate. This results in a total system current consumption in the range of 30 mA. If the LCD backlight is on, 30 mA is considered normal. To ensure the board is OK, disable the LCD and the LCD backlight and measure the current again. The entire board current consumption should not exceed 10 mA at this state. Note that the current consumption of the board could vary greatly depending on the optimization of the board configurations and the applications. The expected current consumption for the MSP430F5529 in standby mode (LPM3), for example, is ~2 μA. Operating at 1 MHz, the total current consumption should not exceed ~280 μA. 6. I have trouble reading the LCD clearly. Why is the LCD contrast setting so low? The LCD contrast is highly dependent on the voltage of the system. Changing power source from USB (3.3 V) to batteries (~3 V) could drastically reduce the contrast. Fortunately, the LCD driver supports adjustable contrast. The specific instruction can be found in the LCD user's guide. The MSP-EXP430F5529 software also provides the function to adjust the contrast using the wheel (see Section 2.8). 7. When I run the example code, nothing happens on the LCD. Verify that all jumpers are installed correctly and the 14-pin JTAG cable are properly connected. 5.2 References • MSP430x5xx/MSP430x6xx Family User's Guide (SLAU208) • Code Composer Studio (CCStudio) Integrated Development Environment (IDE) (http://focus.ti.com/docs/toolsw/folders/print/msp-ccstudio.html) • MSP430 Interface to CC1100/2500 Code Library (PDF: SLAA325) (Associated Files: SLAA325.ZIP) 24 MSP-EXP430F5529 Experimenter Board SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com Frequently Asked Questions, References, and Schematics 5.3 Schematics and BOM The following pages show the schematics and BOM. In addition, the original Eagle CAD schematics and Gerber files are available for download (SLAR055). Figure 10. Schematics (1 of 7) SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 25 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Frequently Asked Questions, References, and Schematics www.ti.com Figure 11. Schematics (2 of 7) 26 MSP-EXP430F5529 Experimenter Board SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com Frequently Asked Questions, References, and Schematics Figure 12. Schematics (3 of 7) SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 27 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Frequently Asked Questions, References, and Schematics www.ti.com Figure 13. Schematics (4 of 7) 28 MSP-EXP430F5529 Experimenter Board SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com Frequently Asked Questions, References, and Schematics Figure 14. Schematics (5 of 7) SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 29 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Frequently Asked Questions, References, and Schematics www.ti.com Figure 15. Schematics (6 of 7) 30 MSP-EXP430F5529 Experimenter Board SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com Frequently Asked Questions, References, and Schematics Figure 16. Schematics (7 of 7) SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 31 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Frequently Asked Questions, References, and Schematics www.ti.com Table 6. Bill of Materials Part Value Package Type Device C1 47pF 0805 C2 12pF 0805 C3 DNP 0603 C4 12pF 0805 C5 10μF 0805 C6 47pF 0805 C7 100nF 0805 C8 220n 0603 C9 220n 0603 C10 10uF/6,3V 1210 C11 100n 0603 C12 100n 0805 C13 100n 0805 C14 DNP 0603 C15 10uF/6,3V 1210 C16 100n 0805 C17 470n 0805 C18 10μF 0805 C19 100nF 0805 C20 .1u 0603 C21 .1u 0603 C22 1μF 0805 C23 1μF 0805 C24 1μF 0805 C25 1μF 0805 C26 1μF 0805 C27 1μF 0805 C28 4.7uF 0805 C29 10nF 0805 C30 1μF 0805 C31 .1u 0603 C32 4.7u 0805 C33 0.1u 0603 C34 4u7 0603 C35 10p 0603 C36 10p 0603 C37 10n 0402 C38 33p 0402 C39 33p 0402 C40 1u/6.3V 0603 C41 100n 0402 C42 1u/6.3V 0603 C43 100n 0402 C44 1u/6.3V 0603 C45 22p 0402 C46 22p 0402 C47 100n 0402 C48 100n 0402 C49 100n 0402 C50 10uF/6,3V 1210 CON1 8PIN_SM_MA_HEADER HEADER 2x4 MALE .1" SMD CON2 8PIN_SM_MA_HEADER HEADER 2x4 MALE .1" SMD 32 MSP-EXP430F5529 Experimenter Board SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com Frequently Asked Questions, References, and Schematics Table 6. Bill of Materials (continued) Part Value Package Type Device CON3 8PIN_SM_MA_HEADER HEADER 2x4 MALE .1" SMD D1 LLSD103A-7 Mini MELF D2 1N4148 Micro MELF SOD110-R J1 103308-2 14-Pin Male JTAG Connector JP2 POT_JMP HEADER 1x2 MALE .1" TH JP1E\SMALL_PIN JP3 LED_JMP HEADER 1x2 MALE .1" TH JP1E\SMALL_PIN J4 HEADER - F5529 PIN ACCESS HEADER 2x7 MALE .1" TH J5 HEADER - F5529 PIN ACCESS HEADER 2x7 MALE .1" TH JP6 430_PWR HEADER 1x2 MALE .1" TH JP1E JP7 SYS_PWR HEADER 1x2 MALE .1" TH JP1E JP8 LDO_PWR_SEL HEADER 1x3 MALE .1" TH PINHD-1X3/SMALL_PIN J9 22-03-5035 MOLEX 3-PIN MALE HEADER 22-03-5035 J10 HEADER - PWR HEADER 1x3 MALE .1" TH PINHD-1X3 JP11 JTAG_PWR_SEN HEADER 1x3 MALE .1" TH PINHD-1X3/SMALL_PIN J12 eZ-RF1 HEADER - RF2500 HEADER 2x9 MALE .1" TH J13 6-Pin Male eZ430 Connector 6-Pin Male eZ430 Connector SL127L6TH JP14 RF_PWR HEADER 1x2 MALE .1" TH JP1E JP15 USB_PWR HEADER 1x2 MALE .1" TH JP1E JP16 eZ430-FET_JMP HEADER 2x5 MALE .1" TH JP5Q J17 6-Pin Male eZ430 Connector 6-Pin Male eZ430 Connector SL127L6TH LED1 LEDCHIPLED_0603 0603 LEDCHIPLED_0603 LED2 LEDCHIPLED_0603 0603 LEDCHIPLED_0603 LED3 LEDCHIPLED_0603 0603 LEDCHIPLED_0603 LED4 OSRAM TOPLED Santana Blue LED 0805 (Surface Mount Bottom) OSRAM TOPLED Santana Blue LED LED5 OSRAM TOPLED Santana Blue LED 0805 (Surface Mount Bottom) OSRAM TOPLED Santana Blue LED LED6 OSRAM TOPLED Santana Blue LED 0805 (Surface Mount Bottom) OSRAM TOPLED Santana Blue LED LED7 OSRAM TOPLED Santana Blue LED 0805 (Surface Mount Bottom) OSRAM TOPLED Santana Blue LED LED8 OSRAM TOPLED Santana Blue LED 0805 (Surface Mount Bottom) OSRAM TOPLED Santana Blue LED LED9 LEDCHIPLED_0603 0603 LED_0603D0603 PAD1 CAP_TOUCH_PAD CAP_TOUCH_PAD PROJECT7264_CC430_PAD PAD2 CAP_TOUCH_PAD CAP_TOUCH_PAD PROJECT7264_CC430_PAD PAD3 CAP_TOUCH_PAD CAP_TOUCH_PAD PROJECT7264_CC430_PAD PAD4 CAP_TOUCH_PAD CAP_TOUCH_PAD PROJECT7264_CC430_PAD PAD5 CAP_TOUCH_PAD CAP_TOUCH_PAD PROJECT7264_CC430_PAD POT1 EVL-HFKA05B54 POT EVL-HFKA05B54 Q1 MS3V-T1R 32.768kHz CL Clock Crystal 32kHz F20XX_PIR_DEMO_&_EVAL_CM200T Q2 SMD Oscillator 4MHz SMD Oscillator 4MHz QUARZ_HC49_4P-1 Q3 SMD Oscillator 12MHz SMD Oscillator 12MHz XTL_FT7AFT10A R1 47k 0603 R-US_R0603 R2 0R 0603 R-US_R0603 R3 470R 0603 R-US_R0603 R4 470R 0603 R-US_R0603 R5 470R 0603 R-US_R0603 R6 47k 0603 R-US_R0603 R7 680 0805 RES0805 R8 680 0805 RES0805 R9 680 0805 RES0805 R10 680 0805 RES0805 R11 680 0805 RES0805 R12 100K 0603 R-US_R0603 R13 100k 0603 R-US_R0603 SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 33 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Frequently Asked Questions, References, and Schematics www.ti.com Table 6. Bill of Materials (continued) Part Value Package Type Device R14 100k 0603 R-US_R0603 R15 100K 0603 R-US_R0603 R16 100k 0603 R-US_R0603 R17 47k 0603 R-US_R0603 R18 47k 0603 R-US_R0603 R19 0 0603 R-US_R0603 R20 100k 0603 R-US_R0603 R21 36k 1% 0603 R-US_R0603 R22 27R 0603 R-US_R0603 R23 27R 0603 R-US_R0603 R24 1M 0603 R-US_R0603 R25 1k4 0603 R-US_R0603 R26 100R 0603 R-US_R0603 R27 33k 0603 R-US_R0603 R28 47k 0402 R_SMDR0402 R29 47k 0402 R_SMDR0402 R30 47k 0402 R_SMDR0402 R31 100R 0402 R_SMDR0402 R32 100R 0402 R_SMDR0402 R33 270 0402 R_SMDR0402 R34 DNP 0402 R_SMDR0402 R35 100R 0402 R_SMDR0402 R36 100R 0402 R_SMDR0402 R37 6k8 0402 R_SMDR0402 R38 3k3 0402 R_SMDR0402 R39 10k 0402 R_SMDR0402 R40 15k 0402 R_SMDR0402 R41 33k 0402 R_SMDR0402 R42 1k5 0402 R_SMDR0402 R43 33R 0402 R_SMDR0402 R44 DNP (47k) 0402 R_SMDR0402 R45 DNP (47k) 0402 R_SMDR0402 R46 33R 0402 R_SMDR0402 R47 100k/1% 0402 R_SMDR0402 R48 33k 0402 R_SMDR0402 R49 3k3 0402 R_SMDR0402 R50 100k/1% 0402 R_SMDR0402 R51 3k3 0402 R_SMDR0402 R52 100R 0402 R_SMDR0402 R53 1k5 0402 R_SMDR0402 R54 1k5 0402 R_SMDR0402 RF1 CCxxxx RF EVM HEADER CCXXXX_20PIN TFM-110-02-SM-D-A-K RF2 CCxxxx RF EVM HEADER CCXXXX_20PIN TFM-110-02-SM-D-A-K S1 USER1 PUSHBUTTON BUTTON EVQ-11L05R S2 USER2 PUSHBUTTON BUTTON EVQ-11L05R S3 F5529 RESET PUSHBUTTON BUTTON EVQ-11L05R S4 F5529 USB BSL PUSHBUTTON BUTTON EVQ-11L05R SW1 POWER SELECT SWITCH DP3T_SWITCH JS203011CQN TP1 F5529 VREF+ TEST POINT TEST_POINT - TP2 F5529 VCORE TEST POINT TEST_POINT - TP3 CC430 EM TEST POINT TEST_POINT - 34 MSP-EXP430F5529 Experimenter Board SLAU330A–May 2011–Revised June 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated www.ti.com Frequently Asked Questions, References, and Schematics Table 6. Bill of Materials (continued) Part Value Package Type Device TP4 CC430 EM TEST POINT TEST_POINT - TP5 CC430 EM TEST POINT TEST_POINT - TP6 CC430 EM TEST POINT TEST_POINT - TP7 CC430 EM TEST POINT TEST_POINT - TP8 CC430 EM TEST POINT TEST_POINT - TP9 eZ430 F16x TEST POINT (EZ_VBUS) TEST_POINT - TP10 eZ430 F16x TEST POINT (RESET) TEST_POINT - TP11 eZ430 F16x TEST POINT (GND) TEST_POINT - TP12 eZ430 F16x TEST POINT (HTCK) TEST_POINT - TP13 eZ430 F16x TEST POINT (HTMS) TEST_POINT - TP14 eZ430 F16x TEST POINT (HTDI) TEST_POINT - TP15 eZ430 F16x TEST POINT (HTDO) TEST_POINT - U1 F5529 - MSP430F5529 80-LQFP MSP430F5529IPNR U2 3-AXIS SPI/I2C ACCELEROMETER SMD CMA3000 CMA3000-D01 U3 102x64 LCD DISPLAY EA DOGS102-6 EA DOGS102-6 U3 LED BACKLIGHT EA DOGS102-6 EA LED39x41-W U4 Alternate LDO - TPS73533 SC70-5 TPS73533DRBT U5 LED Backlight Current Source - TPS75105 SON-10 TPS75105DSKR U6 F5529 USB ESD Protection - TPD2E001 SOT-5 TPD2E001DRLR U7 eZ430 - MSP430F16x 64-LQFP MSP430F1612IPMR U8 eZ430 Level Translator - TXS0104E 14-TSSOP TXS0104EPWR U9 eZ430 LDO - TPS77301 8-MSOP TPS77301DGK U10 eZ430 - TUSB3410 32-LQFP TUSB3410VF U11 eZ430 USB ESD Protection - TPD2E001 SOT-5 TPD2E001DRLR U12 eZ430 EEPROM - CAT24C128YI 8-TSSOP CAT24C128YI USB1 F5529 USB Mini-USB Through Hole 54819-0519 USB2 eZ430 USB Mini-USB Through Hole 54819-0519 X1 microSD Card Holder microSD Card Holder 502702-0891 SLAU330A–May 2011–Revised June 2011 MSP-EXP430F5529 Experimenter Board 35 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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