AD8310 Analog Devices - Farnell Element 14 - Revenir à l'accueil

 

 

Branding Farnell element14 (France)

 

Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Recherche intégrée

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

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Voltage Level Translation

Puce électronique / Microchip :

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Raspberry Pi board B product overview

Logiciels :

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Introduction to Cadsoft EAGLE PCB Design Software in Chinese

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Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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Ben's Autodesk 123D Tutorial Trailer

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Ben's CadSoft EAGLE Tutorial Trailer

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Ben Heck's Soldering Tutorial Trailer

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Ben Heck's AVR Dev Board tutorial

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Ben Heck's Pinball Tutorial Trailer

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Ben Heck's Interface Tutorial Trailer

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First Stage with Python and PiFace Digital

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Cypress - Getting Started with PSoC® 3 - Part 2

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

Autres documentations :
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Fast, Voltage-Out, DC to 440 MHz, 95 dB Logarithmic Amplifier AD8310 Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved. FEATURES Multistage demodulating logarithmic amplifier Voltage output, rise time <15 ns High current capacity: 25 mA into grounded RL 95 dB dynamic range: −91 dBV to +4 dBV Single supply of 2.7 V min at 8 mA typ DC to 440 MHz operation, ±0.4 dB linearity Slope of +24 mV/dB, intercept of −108 dBV Highly stable scaling over temperature Fully differential dc-coupled signal path 100 ns power-up time, 1 mA sleep current APPLICATIONS Conversion of signal level to decibel form Transmitter antenna power measurement Receiver signal strength indication (RSSI) Low cost radar and sonar signal processing Network and spectrum analyzers Signal-level determination down to 20 Hz True-decibel ac mode for multimeters FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The AD8310 is a complete, dc to 440 MHz demodulating logarithmic amplifier (log amp) with a very fast voltage mode output, capable of driving up to 25 mA into a grounded load in under 15 ns. It uses the progressive compression (successive detection) technique to provide a dynamic range of up to 95 dB to ±3 dB law conformance or 90 dB to a ±1 dB error bound up to 100 MHz. It is extremely stable and easy to use, requiring no significant external components. A single-supply voltage of 2.7 V to 5.5 V at 8 mA is needed, corresponding to a power consumption of only 24 mW at 3 V. A fast-acting CMOS-compatible enable pin is provided. Each of the six cascaded amplifier/limiter cells has a small-signal gain of 14.3 dB, with a −3 dB bandwidth of 900 MHz. A total of nine detector cells are used to provide a dynamic range that extends from −91 dBV (where 0 dBV is defined as the amplitude of a 1 V rms sine wave), an amplitude of about ±40 μV, up to +4 dBV (or ±2.2 V). The demodulated output is accurately scaled, with a log slope of 24 mV/dB and an intercept of −108 dBV. The scaling parameters are supply- and temperature-independent. The fully differential input offers a moderately high impedance (1 kΩ in parallel with about 1 pF). A simple network can match the input to 50 Ω and provide a power sensitivity of −78 dBm to +17 dBm. The logarithmic linearity is typically within ±0.4 dB up to 100 MHz over the central portion of the range, but it is somewhat greater at 440 MHz. There is no minimum frequency limit; the AD8310 can be used down to low audio frequencies. Special filtering features are provided to support this wide range. The output voltage runs from a noise-limited lower boundary of 400 mV to an upper limit within 200 mV of the supply voltage for light loads. The slope and intercept can be readily altered using external resistors. The output is tolerant of a wide variety of load conditions and is stable with capacitive loads of 100 pF. The AD8310 provides a unique combination of low cost, small size, low power consumption, high accuracy and stability, high dynamic range, a frequency range encompassing audio to UHF, fast response time, and good load-driving capabilities, making this product useful in numerous applications that require the reduction of a signal to its decibel equivalent. The AD8310 is available in the industrial temperature range of −40°C to +85°C in an 8-lead MSOP package. AD8310 Rev. F | Page 2 of 24 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 4 ESD Caution .................................................................................. 4 Pin Configuration and Function Descriptions ............................. 5 Typical Performance Characteristics ............................................. 6 Theory of Operation ........................................................................ 9 Progressive Compression ............................................................ 9 Slope and Intercept Calibration ................................................ 10 Offset Control ............................................................................. 10 Product Overview ........................................................................... 11 Enable Interface .......................................................................... 11 Input Interface ............................................................................ 11 Offset Interface ........................................................................... 12 Output Interface ......................................................................... 12 Using the AD8310 .......................................................................... 14 Basic Connections ...................................................................... 14 Transfer Function in Terms of Slope and Intercept ............... 15 dBV vs. dBm ............................................................................... 15 Input Matching ........................................................................... 15 Narrow-Band Matching ............................................................ 16 General Matching Procedure .................................................... 16 Slope and Intercept Adjustments ............................................. 17 Increasing the Slope to a Fixed Value ...................................... 17 Output Filtering .......................................................................... 18 Lowering the High-Pass Corner Frequency of the Offset Compensation Loop .................................................................. 18 Applications Information .............................................................. 19 Cable-Driving ............................................................................. 19 DC-Coupled Input ..................................................................... 19 Evaluation Board ............................................................................ 20 Die Information .............................................................................. 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23 REVISION HISTORY 6/10—Rev. E to Rev. F Added Die Information Section ................................................... 22 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23 6/05—Rev. D to Rev. E Changes to Figure 6 .......................................................................... 6 Change to Basic Connections Section ......................................... 14 Changes to Equation 10 ................................................................. 17 Changes to Ordering Guide .......................................................... 22 10/04—Rev. C to Rev. D Format Updated .................................................................. Universal Typical Performance Characteristics Reordered .......................... 6 Changes to Figure 41 and Figure 42 ............................................. 20 7/03—Rev. B to Rev. C Replaced TPC 12 ............................................................................... 5 Change to DC-Coupled Input Section ........................................ 14 Replaced Figure 20 ......................................................................... 15 Updated Outline Dimensions ....................................................... 16 2/03—Rev. A to Rev. B Change to Evaluation Board Section ........................................... 15 Change to Table III ......................................................................... 16 Updated Outline Dimensions ....................................................... 16 1/00—Rev. 0 to Rev. A 10/99—Revision 0: Initial Version AD8310 Rev. F | Page 3 of 24 SPECIFICATIONS TA = 25°C, VS = 5 V, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit INPUT STAGE Inputs INHI, INLO Maximum Input1 Single-ended, p-p ±2.0 ±2.2 V 4 dBV Equivalent Power in 50 Ω Termination resistor of 52.3 Ω 17 dBm Differential drive, p-p 20 dBm Noise Floor Terminated 50 Ω source 1.28 nV/√Hz Equivalent Power in 50 Ω 440 MHz bandwidth −78 dBm Input Resistance From INHI to INLO 800 1000 1200 Ω Input Capacitance From INHI to INLO 1.4 pF DC Bias Voltage Either input 3.2 V LOGARITHMIC AMPLIFIER Output VOUT ±3 dB Error Dynamic Range From noise floor to maximum input 95 dB Transfer Slope 10 MHz ≤ f ≤ 200 MHz 22 24 26 mV/dB Overtemperature, −40°C < TA < +85°C 20 26 mV/dB Intercept (Log Offset)2 10 MHz ≤ f ≤ 200 MHz −115 −108 −99 dBV Equivalent dBm (re 50 Ω) −102 −95 −86 dBm Overtemperature, −40°C ≤ TA ≤ +85°C −120 −96 dBV Equivalent dBm (re 50 Ω) −107 −83 dBm Temperature sensitivity −0.04 dB/°C Linearity Error (Ripple) Input from −88 dBV (−75 dBm) to +2 dBV (+15 dBm) ±0.4 dB Output Voltage Input = −91 dBV (−78 dBm) 0.4 V Input = 9 dBV (22 dBm) 2.6 V Minimum Load Resistance, RL 100 Ω Maximum Sink Current 0.5 mA Output Resistance 0.05 Ω Video Bandwidth 25 MHz Rise Time (10% to 90%) Input level = −43 dBV (−30 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 15 ns Input level = −3 dBV (+10 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 20 ns Fall Time (90% to 10%) Input level = −43 dBV (−30 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 30 ns Input level = −3 dBV (+10 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 40 ns Output Settling Time to 1% Input level = −13 dBV (0 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 40 ns POWER INTERFACES Supply Voltage, VPOS 2.7 5.5 V Quiescent Current Zero signal 6.5 8.0 9.5 mA Overtemperature −40°C < TA < +85°C 5.5 8.5 10 mA Disable Current 0.05 μA Logic Level to Enable Power High condition, −40°C < TA < +85°C 2.3 V Input Current When High 3 V at ENBL 35 μA Logic Level to Disable Power Low condition, −40°C < TA < +85°C 0.8 V 1 The input level is specified in dBV, because logarithmic amplifiers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of 1 V rms. A power level of 0 dBm (1 mW) in a 50 Ω termination corresponds to an input of 0.2236 V rms. Therefore, the relationship between dBV and dBm is a fixed offset of 13 dBm in the special case of a 50 Ω termination. 2 Guaranteed but not tested; limits are specified at six sigma levels. AD8310 Rev. F | Page 4 of 24 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage, VS 7.5 V Input Power (re 50 Ω), Single-Ended 18 dBm Differential Drive 22 dBm Internal Power Dissipation 200 mW θJA 200°C/W Maximum Junction Temperature 125°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION AD8310 Rev. F | Page 5 of 24 01084-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INLO1INHI8 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 INLO One of Two Balanced Inputs. Biased roughly to VPOS/2. 2 COMM Common Pin. Usually grounded. 3 OFLT Offset Filter Access. Nominally at about 1.75 V. 4 VOUT Low Impedance Output Voltage. Carries a 25 mA maximum load. 5 VPOS Positive Supply. 2.7 V to 5.5 V at 8 mA quiescent current. 6 BFIN Buffer Input. Used to lower postdetection bandwidth. 7 ENBL CMOS Compatible Chip Enable. Active when high. 8 INHI Second of Two Balanced Inputs. Biased roughly to VPOS/2. AD8310 Rev. F | Page 6 of 24 TYPICAL PERFORMANCE CHARACTERISTICS 3.00RSSI OUTPUT ( V)2.52.01.51.00.5TA = +85°CTA = +25°CTA =–40°C01084-011 Figure 3. RSSI Output vs. Input Level, 100 MHz Sine Input at TA = −40°C, +25°C, and +85°C, Single-Ended Input 3.0RSSI OUTPUT ( V)2.52.01.51.00.5010MHz50MHz100MHz Figure 4. RSSI Output vs. Input Level at TA = 25°C for Frequencies of 10 MHz, 50 MHz, and 100 MHz 3.00RSSI OUTPUT ( V)2.52.01.51.00.5200MHz300MHz440MHz Figure 5. RSSI Output vs. Input Level at TA = 25°C for Frequencies of 200 MHz, 300 MHz, and 440 MHz Figure 6. Log Linearity of RSSI Output vs. Input Level, 100 MHz Sine Input at TA = −40°C, +25°C, and +85°C Figure 7. Log Linearity of RSSI Output vs. Input Level at TA = 25°C for Frequencies of 10 MHz, 50 MHz, and 100 MHz Figure 8. Log Linearity of RSSI Output vs. Input Level at TA = 25°C for Frequencies of 200 MHz, 300 MHz, and 440 MHz AD8310 Rev. F | Page 7 of 24 500mV PERVERTICALDIVISIONVOUT100pF3300pFGROUND REFERENCE0.01μF Figure 9. Small-Signal AC Response of RSSI Output with External BFIN Capacitance of 100 pF, 3300 pF, and 0.01 μF GND REFERENCEINPUT 500mV PERVERTICALDIVISIONVOUT154Ω100Ω200Ω Figure 10. Large-Signal RSSI Pulse Response with CL = 100 pF and RL = 100 Ω, 154 Ω, and 200 Ω 100ns PERHORIZONTALDIVISIONGND REFERENCEINPUT500mV PERVERTICALDIVISIONVOUT Figure 12. Small-Signal RSSI Pulse Response with RL = 402 Ω and CL = 68 pF Figure 13. Large-Signal RSSI Pulse Response with RL = 100 Ω and CL = 33 pF, 68 pF, and 100 pF Figure 11. RSSI Pulse Response with RL = 402 Ω and CL = 68 pF, for Inputs Stepped from 0 dBV to −33 dBV, −23 dBV, −13 dBV, and −3 dBV 01084-008 Figure 14. Small-Signal RSSI Pulse Response with RL = 50 Ω and Back Termination of 50 Ω (Total Load = 100 Ω) AD8310 100SUPPLY CURRENT ( mA)1010.10.010.0010.0001TA = +85°CTA = +25°C Figure 18. Power-On/Off Response Time with RF Input of −83 dBV to −3 dBV Figure 15. Supply Current vs. Enable Voltage at TA = −40°C, +25°C, and +85°C 3029RSSI SLOPE ( mV/dB)24232226252827 Figure 16. RSSI Slope vs. Frequency Figure 19. RSSI Intercept vs. Frequency INTERCEPT (dBV)0–115–113 3010COUNT252015 3540NORMAL(23.6584,0.308728) Figure 17. Transfer Slope Distribution, VS = 5 V, Frequency = 100 MHz, 25°C –111–109–107–105–103–101–99–97 Figure 20. Intercept Distribution, VS = 5 V, Frequency = 100 MHz, 25°C AD8310 Rev. F | Page 9 of 24 THEORY OF OPERATION Logarithmic amplifiers perform a more complex operation than classical linear amplifiers, and their circuitry is significantly different. A good grasp of what log amps do and how they do it can help users avoid many pitfalls in their applications. For a complete discussion of the theory, see the AD8307 data sheet. The essential purpose of a log amp is not to amplify (though amplification is needed internally), but to compress a signal of wide dynamic range to its decibel equivalent. It is, therefore, a measurement device. An even better term might be logarithmic converter, because the function is to convert a signal from one domain of representation to another via a precise nonlinear transformation: ⎞⎛INV (1) where: VOUT is the output voltage. VY is the slope voltage. The logarithm is usually taken to base ten, in which case VY is also the volts-per-decade. VIN is the input voltage. VX is the intercept voltage. Log amps implicitly require two references (here VX and VY) that determine the scaling of the circuit. The accuracy of a log amp cannot be any better than the accuracy of its scaling references. In the AD8310, these are provided by a band gap reference. VOUT5VY4VY3VY2VYVY VOUT =0LOGVINVSHIFTLOWER INTERCEPTVIN=10–2VX–40dBcVIN=102VX+40dBcVIN=104VX+80dBcVIN =VX0dBc Figure 21. General Form of the Logarithmic Function While Equation 1, plotted in Figure 21, is fundamentally correct, a different formula is appropriate for specifying the calibration attributes or demodulating log amps like the AD8310, operating in RF applications with a sine wave input. (2) where: VOUT is the demodulated and filtered baseband (video or RSSI) output. VSLOPE is the logarithmic slope, now expressed in V/dB (25 mV/dB for the AD8310). PIN is the input power, expressed in dB relative to some reference power level. PO is the logarithmic intercept, expressed in dB relative to the same reference level. A widely used reference in RF systems is dB above 1 mW in 50 Ω, a level of 0 dBm. Note that the quantity (PIN − PO) is dB. The logarithmic function disappears from the formula, because the conversion has already been implicitly performed in stating the input in decibels. This is strictly a concession to popular convention. Log amps manifestly do not respond to power (tacitly, power absorbed at the input), but rather to input voltage. The input is specified in dBV (decibels with respect to 1 V rms) throughout this data sheet. This is more precise, although still incomplete, because the signal waveform is also involved. Many users specify RF signals in terms of power (usually in dBm/50 Ω), and this convention is used in this data sheet when specifying the performance of the AD8310. PROGRESSIVE COMPRESSION High speed, high dynamic-range log amps use a cascade of nonlinear amplifier cells to generate the logarithmic function as a series of contiguous segments, a type of piecewise linear technique. The AD8310 employs six cells in its main signal path, each having a small-signal gain of 14.3 dB (×5.2) and a −3 dB bandwidth of about 900 MHz. The overall gain is about 20,000 (86 dB), and the overall bandwidth of the chain is approximately 500 MHz, resulting in a gain-bandwidth product (GBW) of 10,000 GHz, about a million times that of a typical op amp. This very high GBW is essential to accurate operation under small-signal conditions and at high frequencies. The AD8310 exhibits a logarithmic response down to inputs as small as 40 μV at 440 MHz. Progressive compression log amps either provide a baseband video response or accept an RF input and demodulate this signal to develop an output that is essentially the envelope of the input represented on a logarithmic or decibel scale. The AD8310 is the latter kind. Demodulation is performed in a total of nine detector cells. Six are associated with the amplifier stages, and three are passive detectors that receive a progres-sively attenuated fraction of the full input. The maximum signal frequency can be 440 MHz, but, because all the gain stages are dc-coupled, operation at very low frequencies is possible. AD8310 Rev. F | Page 10 of 24 SLOPE AND INTERCEPT CALIBRATION All monolithic log amps from Analog Devices use precision design techniques to control the logarithmic slope and intercept. The primary source of this calibration is a pair of accurate voltage references that provide supply- and temperature-independent scaling. The slope is set to 24 mV/dB by the bias chosen for the detector cells and the subsequent gain of the postdetector output interface. With this slope, the full 95 dB dynamic range can be easily accommodated within the output swing capacity, when operating from a 2.7 V supply. Intercept positioning at −108 dBV (−95 dBm re 50 Ω) has likewise been chosen to provide an output centered in the available voltage range. Precise control of the slope and intercept results in a log amp with stable scaling parameters, making it a true measurement device as, for example, a calibrated received signal strength indicator (RSSI). In this application, the input waveform is invariably sinusoidal. The input level is correctly specified in dBV. It can alternatively be stated as an equivalent power, in dBm, but in this case, it is necessary to specify the impedance in which this power is presumed to be measured. In RF practice, it is common to assume a reference impedance of 50 Ω, in which 0 dBm (1 mW) corresponds to a sinusoidal amplitude of 316.2 mV (223.6 mV rms). However, the power metric is correct only when the input impedance is lowered to 50 Ω, either by a termination resistor added across INHI and INLO, or by the use of a narrow-band matching network. Note that log amps do not inherently respond to power, but to the voltage applied to their input. The AD8310 presents a nominal input impedance much higher than 50 Ω (typically 1 kΩ at low frequencies). A simple input matching network can considerably improve the power sensitivity of this type of log amp. This increases the voltage applied to the input and, therefore, alters the intercept. For a 50 Ω reactive match, the voltage gain is about 4.8, and the whole dynamic range moves down by 13.6 dB. The effective intercept is a function of wave-form. For example, a square-wave input reads 6 dB higher than a sine wave of the same amplitude, and a Gaussian noise input reads 0.5 dB higher than a sine wave of the same rms value. OFFSET CONTROL In a monolithic log amp, direct coupling is used between the stages for several reasons. First, it avoids the need for coupling capacitors, which typically have a chip area at least as large as that of a basic gain cell, considerably increasing die size. Second, the capacitor values predetermine the lowest frequency at which the log amp can operate. For moderate values, this can be as high as 30 MHz, limiting the application range. Third, the parasitic back-plate capacitance lowers the bandwidth of the cell, further limiting the scope of applications. However, the very high dc gain of a direct-coupled amplifier raises a practical issue. An offset voltage in the early stages of the chain is indistinguishable from a real signal. If it were as high as 400 μV, it would be 18 dB larger than the smallest ac signal (50 μV), potentially reducing the dynamic range by this amount. This problem can be averted by using a global feedback path from the last stage to the first, which corrects this offset in a similar fashion to the dc negative feedback applied around an op amp. The high frequency components of the feedback signal must, of course, be removed to prevent a reduction of the HF gain in the forward path. An on-chip filter capacitor of 33 pF provides sufficient suppres-sion of HF feedback to allow operation above 1 MHz. The −3 dB point in the high-pass response is at 2 MHz, but the usable range extends well below this frequency. To further lower the frequency range, an external capacitor can be added at OFLT (Pin 3). For example, 300 pF lowers it by a factor of 10. Operation at low audio frequencies requires a capacitor of about 1 μF. Note that this filter has no effect for input levels well above the offset voltage, where the frequency range would extend down to dc (for a signal applied directly to the input pins). The dc offset can optionally be nulled by adjusting the voltage on the OFLT pin (see the Applications Information section). AD8310 Rev. F | Page 11 of 24 PRODUCT OVERVIEW The AD8310 has six main amplifier/limiter stages. These six cells and their and associated gm styled full-wave detectors handle the lower two-thirds of the dynamic range. Three top-end detectors, placed at 14.3 dB taps on a passive attenuator, handle the upper third of the 95 dB range. The first amplifier stage provides a low noise spectral density (1.28 nV/√Hz). Biasing for these cells is provided by two references: one determines their gain, and the other is a band gap circuit that determines the logarithmic slope and stabilizes it against supply and temperature variations. The AD8310 can be enabled or disabled by a CMOS-compatible level at ENBL (Pin 7). The differential current-mode outputs of the nine detectors are summed and then converted to single-sided form, nominally scaled 2 μA/dB. The output voltage is developed by applying this current to a 3 kΩ load resistor followed by a high speed gain-of-four buffer amplifier, resulting in a logarithmic slope of 24 mV/dB (480 mV/decade) at VOUT (Pin 4). The unbuffered voltage can be accessed at BFIN (Pin 6), allowing certain functional modifications such as the addition of an external postdemodulation filter capacitor and the alteration or adjustment of slope and intercept. +–VPOSINHIINLOCOMM38mA1.0kΩBAND GAP REFERENCEAND BIASINGSIX 14.3dB 900MHzAMPLIFIER STAGESNINE DETECTOR CELLSSPACED 14.3dBINPUT-OFFSETCOMPENSATION LOOP22μA/dBMIRROR3kΩ3kΩ1kΩCOMMCOMMENBLBFINVOUTOFLTENABLEBUFFERINPUTOUTPUTOFFSETFILTERAD8310SUPPLY+INPUT–INPUTCOMMON Figure 22. Main Features of the AD8310 The last gain stage also includes an offset-sensing cell. This generates a bipolarity output current, if the main signal path exhibits an imbalance due to accumulated dc offsets. This current is integrated by an on-chip capacitor that can be increased in value by an off-chip component at OFLT (Pin 3). The resulting voltage is used to null the offset at the output of the first stage. Because it does not involve the signal input connections, whose ac-coupling capacitors otherwise introduce a second pole into the feedback path, the stability of the offset correction loop is assured. The AD8310 is built on an advanced, dielectrically isolated, complementary bipolar process. In the following interface diagrams shown in Figure 23 to Figure 26, resistors labeled as R are thin-film resistors that have a low temperature coefficient of resistance (TCR) and high linearity under large-signal conditions. Their absolute tolerance is typically within ±20%. Similarly, capacitors labeled as C have a typical tolerance of ±15% and essentially zero temperature or voltage sensitivity. Most interfaces have additional small junction capacitances associated with them, due to active devices or ESD protection, which might not be accurate or stable. Component numbering in these interface diagrams is local. ENABLE INTERFACE The chip-enable interface is shown in Figure 23. The currents in the diode-connected transistors control the turn-on and turn-off states of the band gap reference and the bias generator. They are a maximum of 100 μA when ENBL is taken to 5 V under worst-case conditions. For voltages below 1 V, the AD8310 is disabled and consumes a sleep current of less than 1 μA. When tied to the supply or a voltage above 2 V, it is fully enabled. The internal bias circuitry is very fast (typically <100 ns for either off or on). In practice, however, the latency period before the log amp exhibits its full dynamic range is more likely to be limited by factors relating to the use of ac coupling at the input or the settling of the offset-control loop (see the following sections). Figure 23. Enable Interface INPUT INTERFACE Figure 24 shows the essentials of the input interface. CP and CM are parasitic capacitances, and CD is the differential input capacitance, largely due to Q1 and Q2. In most applications, both input pins are ac-coupled. The S switches close when enable is asserted. When disabled, bias current IE is shut off and the inputs float; therefore, the coupling capacitors remain charged. If the log amp is disabled for long periods, small leakage currents discharge these capacitors. Then, if they are poorly matched, charging currents at power-up can generate a transient input voltage that can block the lower reaches of the dynamic range until it becomes much less than the signal. A single-sided signal can be applied via a blocking capacitor to either Pin 1 or Pin 8, with the other pin ac-coupled to ground. Under these conditions, the largest input signal that can be handled is 0 dBV (a sine amplitude of 1.4 V) when using a 3 V supply; a 5 dBV input (2.5 V amplitude) can be handled with a 5 V supply. When using a fully balanced drive, this maximum input level is permissible for supply voltages as low as 2.7 V. Above 10 MHz, this is easily achieved using an LC matching network. Such a network, having an inductor at the input, usefully eliminates the input transient noted above. AD8310 TOP-ENDDETECTORSCOMINHIINLOCPCDCMCOM4kΩ~3kΩ125Ω6kΩ6kΩ2kΩTYP 2.2V FOR3V SUPPLY,3.2V AT 5VSVPOSIE2.4mAQ1Q2 581 Figure 24. Signal Input Interface Occasionally, it might be desirable to use the dc-coupled potential of the AD8310 in baseband applications. The main challenge here is to present the signal at the elevated common-mode input level, which might require the use of low noise, low offset buffer amplifiers. In some cases, it might be possible to use dual supplies of ±3 V, which allow the input pins to operate at ground potential. The output, which is internally referenced to the COMM pin (now at −3 V), can be positioned back to ground level, with essentially no sensitivity to the particular value of the negative supply. OFFSET INTERFACE The input-referred dc offsets in the signal path are nulled via the interface associated with Pin 3, shown in Figure 25. Q1 and Q2 are the first-stage input transistors, having slightly unbalanced load resistors, resulting in a deliberate offset voltage of about 1.5 mV referred to the input pins. Q3 generates a small current to null this error, dependent on the voltage at the OFLT pin. When Q1 and Q2 are perfectly matched, this voltage is about 1.75 V. In practice, it can range from approximately 1 V to 2.5 V for an input-referred offset of ±1.5 mV. Figure 25. Offset Interface and Offset-Nulling Path In normal operation using an ac-coupled input signal, the OFLT pin should be left unconnected. The gm cell, which is gated off when the chip is disabled, converts a residual offset (sensed at a point near the end of the cascade of amplifiers) to a current. This is integrated by the on-chip capacitor, CHP, plus any added external capacitance, COFLT, to generate the voltage that is applied back to the input stage in the polarity needed to null the output offset. From a small-signal perspective, this feedback alters the response of the amplifier, which exhibits a zero in its ac transfer function, resulting in a closed-loop, high-pass −3 dB corner at about 2 MHz. An external capacitor lowers the high-pass corner to arbitrarily low frequencies; using 1 μF, the 3 dB corner is at 60 Hz. OUTPUT INTERFACE The nine detectors generate differential currents, having an average value that is dependent on the signal input level, plus a fluctuation at twice the input frequency. These are summed at nodes LGP and LGN in Figure 26. Further currents are added at these nodes to position the intercept by slightly raising the output for zero input and to provide temperature compensation. 0.2pF3kΩ VOUT4 Figure 26. Simplified Output Interface AD8310 Rev. F | Page 13 of 24 For zero-signal conditions, all the detector output currents are equal. For a finite input of either polarity, their difference is converted by the output interface to a single-sided unipolar current, nominally scaled 2 μA/dB (40 μA/decade), at the output pin BFIN. An on-chip resistor of ~3 kΩ, R1, converts this current to a voltage of 6 mV/dB. This is then amplified by a factor of 4 in the output buffer, which can drive a current of up to 25 mA in a grounded load resistor. The overall rise time of the AD8310 is less than 15 ns. There is also a delay time of about 6 ns when the log amp is driven by an RF burst, starting at zero amplitude. When driving capacitive loads, it is desirable to add a low value of load resistor to speed up the return to the baseline; the buffer is stable for loads of a least 100 pF. The output bandwidth can be lowered by adding a grounded capacitor at BFIN. The time-constant of the resulting single-pole filter is formed with the 3 kΩ internal load resistor (with a tolerance of 20%). Therefore, to set the −3 dB frequency to 20 kHz, use a capacitor of 2.7 nF. Using 2.7 μF, the filter corner is at 20 Hz. AD8310 Rev. F | Page 14 of 24 USING THE AD8310 The AD8310 has very high gain and bandwidth. Consequently, it is susceptible to all signals that appear at the input terminals within a very broad frequency range. Without the benefit of filtering, these are indistinguishable from the desired signal and have the effect of raising the apparent noise floor (that is, lowering the useful dynamic range). For example, while the signal of interest has an IF of 50 MHz, any of the following can easily be larger than the IF signal at the lower extremities of its dynamic range: a few hundred mV of 60 Hz hum picked up due to poor grounding techniques, spurious coupling from a digital clock source on the same PC board, local radio stations, and so on. Careful shielding and supply decoupling is, therefore, essential. A ground plane should be used to provide a low impedance connection to the common pin COMM, for the decoupling capacitor(s) used at VPOS, and for the output ground. BASIC CONNECTIONS Figure 27 shows the connections needed for most applications. A supply voltage between 2.7 V and 5.5 V is applied to VPOS and is decoupled using a 0.01 μF capacitor close to the pin. Optionally, a small series resistor can be placed in the power line to give additional filtering of power-supply noise. The ENBL input, which has a threshold of approximately 1.3 V (see Figure 15), should be tied to VPOS when this feature is not needed. VS(2.7V–5.5V)C20.01μF52.3Ω C10.01μFC40.01μFNCNCINHIENBLBFINVPOSINLOCOMMOFLTVOUTAD83104.7ΩOPTIONALVOUT (RSSI)SIGNALINPUT87651234 Figure 27. Basic Connections While the AD8310’s input can be driven differentially, the input signal is, in general, single-ended. C1 is tied to ground, and the input signal is coupled in through C2. Capacitor C1 and Capacitor C2 should have the same value to minimize start-up transients when the enable feature is used; otherwise, their values need not be equal. The 52.3 Ω resistor combines with the 1.1 kΩ input impedance of the AD8310 to yield a simple broadband 50 Ω input match. An input matching network can also be used (see the Input Matching section). The coupling time constant, 50 × CC/2, forms a high-pass corner with a 3 dB attenuation at fHP = 1/(π × 50 × CC), where C1 = C2 = CC. In high frequency applications, fHP should be as large as possible to minimize the coupling of unwanted low frequency signals. In low frequency applications, a simple RC network forming a low-pass filter should be added at the input for similar reasons. This should generally be placed at the generator side of the coupling capacitors, thereby lowering the required capacitance value for a given high-pass corner frequency. For applications in which the ground plane might not be an equi-potential (possibly due to noise in the ground plane), the low input of an unbalanced source should generally be ac-coupled through a separate connection of the low associated with the source. Furthermore, it is good practice in such situations to break the ground loop by inserting a small resistance to ground in the low side of the input connector (see Figure 28). Figure 28. Connections for Isolation of Source Ground from Device Ground Figure 29 shows the output vs. the input level for sine inputs at 10 MHz, 50 MHz, and 100 MHz. Figure 30 shows the logarith-mic conformance under the same conditions. Figure 29. Output vs. Input Level at 10 MHz, 50 MHz, and 100 MHz AD8310 Rev. F | Page 15 of 24 5ERROR ( dB)4–1–2–3–4203110MHz50MHz ±3dB DYNAMIC RANGE±1dB DYNAMIC RANGE Figure 30. Log Conformance Error vs. Input Level at 10 MHz, 50 MHz, and 100 MHz TRANSFER FUNCTION IN TERMS OF SLOPE AND INTERCEPT The transfer function of the AD8310 is characterized in terms of its slope and intercept. The logarithmic slope is defined as the change in the RSSI output voltage for a 1 dB change at the input. For the AD8310, slope is nominally 24 mV/dB. Therefore, a 10 dB change at the input results in a change at the output of approximately 240 mV. The plot of log conformance shows the range over which the device maintains its constant slope. The dynamic range of the log amp is defined as the range over which the slope remains within a certain error band, usually ±1 dB or ±3 dB. In Figure 30, for example, the ±1 dB dynamic range is approximately 95 dB (from +4 dBV to −91 dBV). The intercept is the point at which the extrapolated linear response would intersect the horizontal axis (see Figure 29). For the AD8310, the intercept is calibrated to be −108 dBV (−95 dBm). Using the slope and intercept, the output voltage can be calculated for any input level within the specified input range using the following equation: VOUT = VSLOPE × (PIN − PO) (3) where: VOUT is the demodulated and filtered RSSI output. VSLOPE is the logarithmic slope expressed in V/dB. PIN is the input signal expressed in dB relative to some reference level (either dBm or dBV in this case). PO is the logarithmic intercept expressed in dB relative to the same reference level. For example, for an input level of −33 dBV (−20 dBm), the output voltage is VOUT = 0.024 V/dB × (−33 dBV − (−108 dBV)) = 1.8 V (4) dBV vs. dBm The most widely used convention in RF systems is to specify power in dBm, decibels above 1 mW in 50 Ω. Specification of the log amp input level in terms of power is strictly a concession to popular convention. As mentioned previously, log amps do not respond to power (power absorbed at the input), but to the input voltage. The use of dBV, defined as decibels with respect to a 1 V rms sine wave, is more precise. However, this is still ambiguous, because waveform is also involved in the response of a log amp, which, for a complex input such as a CDMA signal, does not follow the rms value exactly. Because most users specify RF signals in terms of power (more specifically, in dBm/50 Ω) both dBV and dBm are used to specify the perform-ance of the AD8310, showing equivalent dBm levels for the special case of a 50 Ω environment. Values in dBV are converted to dBm re 50 Ω by adding 13 dB. Table 4. Correction for Signals with Differing Crest Factors Signal Type Correction Factor1 (dB) Sine wave 0 Square wave or dc −3.01 Triangular wave 0.9 GSM channel (all time slots on) 0.55 CDMA channel (forward link, nine channels on) 3.55 CDMA channel (reverse link) 0.5 PDC channel (all time slots on) 0.58 1 Add to the measured input level. INPUT MATCHING Where higher sensitivity is required, an input matching network is useful. Using a transformer to achieve the impedance trans-formation also eliminates the need for coupling capacitors, lowers the offset voltage generated directly at the input, and balances the drive amplitude to INLO and INHI. The choice of turns ratio depends somewhat on the frequency. At frequencies below 50 MHz, the reactance of the input capacitance is much higher than the real part of the input impedance. In this frequency range, a turns ratio of about 1:4.8 lowers the input impedance to 50 Ω, while raising the input voltage lowers the effect of the short-circuit noise voltage by the same factor. The intercept is also lowered by the turns ratio; for a 50 Ω match, it is reduced by 20 log10 (4.8) or 13.6 dB. The total noise is reduced by a somewhat smaller factor, because there is a small contribution from the input noise current. AD8310 Rev. F | Page 16 of 24 NARROW-BAND MATCHING Transformer coupling is useful in broadband applications. However, a magnetically coupled transformer might not be convenient in some situations. Table 5 lists narrow-band matching values. Table 5. Narrow-Band Matching Values fC (MHz) ZIN (Ω) C1 (pF) C2 (pF) LM (nH) Voltage Gain (dB) 10 45 160 150 3300 13.3 20 44 82 75 1600 13.4 50 46 30 27 680 13.4 100 50 15 13 270 13.4 150 57 10 8.2 220 13.2 200 57 7.5 6.8 150 12.8 250 50 6.2 5.6 100 12.3 500 54 3.9 3.3 39 10.9 10 103 100 91 5600 10.4 20 102 51 43 2700 10.4 50 99 22 18 1000 10.6 100 98 11 9.1 430 10.5 150 101 7.5 6.2 260 10.3 200 95 5.6 4.7 180 10.3 250 92 4.3 3.9 130 9.9 500 114 2.2 2.0 47 6.8 At high frequencies, it is often preferable to use a narrow-band matching network, as shown in Figure 31. This has several advan-tages. The same voltage gain is achieved, providing increased sensitivity, but a measure of selectivity is also introduced. The component count is low: two capacitors and an inexpensive chip inductor. Additionally, by making these capacitors unequal, the amplitudes at INP and INM can be equalized when driving from a single-sided source; that is, the network also serves as a balun. Figure 32 shows the response for a center frequency of 100 MHz; note the very high attenuation at low frequencies. The high fre-quency attenuation is due to the input capacitance of the log amp. C1 INHIAD8310SIGNALINPUTLM8 Figure 31. Reactive Matching Network Figure 32. Response of 100 MHz Matching Network GENERAL MATCHING PROCEDURE For other center frequencies and source impedances, the following steps can be used to calculate the basic matching parameters. Step 1: Tune Out CIN At a center frequency, fC, the shunt impedance of the input capacitance, CIN, can be made to disappear by resonating with a temporary inductor, LIN, whose value is given by (5) where CIN = 1.4 pF. For example, at fC = 100 MHz, LIN = 1.8 μH. Step 2: Calculate CO and LO Now, having a purely resistive input impedance, calculate the nominal coupling elements, CO and LO, using (6) For the AD8310, RIN is 1 kΩ. Therefore, if a match to 50 Ω is needed, at fC = 100 MHz, CO must be 7.12 pF and LO must be 356 nH. Step 3: Split CO into Two Parts To provide the desired fully balanced form of the network shown in Figure 31, two capacitors C1 and C2, each of nominally twice CO, can be used. This requires a value of 14.24 pF in this example. Under these conditions, the voltage amplitudes at INHI and INLO are similar. A somewhat better balance in the two drives can be achieved when C1 is made slightly larger than C2, which also allows a wider range of choices in selecting from standard values. For example, capacitors of C1 = 15 pF and C2 = 13 pF can be used, making CO = 6.96 pF. AD8310 Rev. F | Page 17 of 24 ( ) Step 4: Calculate LM The matching inductor required to provide both LIN and LO is the parallel combination of these. (7) With LIN = 1.8 μH and LO = 356 nH, the value of LM to complete this example of a match of 50 Ω at 100 MHz is 297.2 nH. The nearest standard value of 270 nH can be used with only a slight loss of matching accuracy. The voltage gain at resonance depends only on the ratio of impedances, as given by (8) SLOPE AND INTERCEPT ADJUSTMENTS Where system (that is, software) calibration is not available, the adjustments shown in Figure 33 can be used, either singly or in combination, to trim the absolute accuracy of the AD8310. The log slope can be raised or lowered by VR1; the values shown provide a calibration range of ±10% (22.6 mV/dB to 27.4 mV/dB), which includes full allowance for the variability in the value of the internal resistances. The adjustment can be made by alternately applying two fixed input levels, provided by an accurate signal generator, spaced over the central portion of the dynamic range, for example, −60 dBV and −20 dBV. Alternatively, an AM-modulated signal at about the center of the dynamic range can be used. For a modulation depth M, expressed as a fraction, the decibel range between the peaks and troughs over one cycle of the modulation period is given by (9) For example, using a generator output of −40 dBm with a 70% modulation depth (M = 0.7), the decibel range is 15 dB, because the signal varies from −47.5 dBm to −32.5 dBm. The log intercept is adjustable by VR2 over a −3 dB range with the component values shown. VR2 is adjusted while applying an accurately known CW signal, preferably near the lower end of the dynamic range, to minimize the effect of any residual uncertainty in the slope. For example, to position the intercept to −80 dBm, a test level of −65 dBm can be applied, and VR2 can be adjusted to produce a dc output of 15 dB above 0 at 24 mV/dB, which is 360 mV. 52.3 AD8310 Figure 33. Slope and Intercept Adjustments INCREASING THE SLOPE TO A FIXED VALUE It is also possible to increase the slope to a new fixed value and, therefore, to increase the change in output for each decibel of input change. A common example of this is the need to map the output swing of the AD8310 into the input range of an analog-to-digital converter (ADC) with a rail-to-rail input swing. Alternatively, a situation might arise when only a part of the total dynamic range is required (for example, just 20 dB) in an application where the nominal input level is more tightly constrained, and a higher sensitivity to a change in this level is required. Of course, the maximum output is limited by either the load resistance and the maximum output current rating of 25 mA or by the supply voltage (see the Specifications section). The slope can easily be raised by adding a resistor from VOUT to BFIN, as shown in Figure 34. This alters the gain of the output buffer, by means of stable positive feedback, from its normal value of 4 to an effective value that can be as high as 16, corresponding to a slope of 100 mV/dB. INHI 8765 Figure 34. Raising the Slope to 100 mV/dB The resistor, RSLOPE, is set according to the equation SlopeRSLOPEmV/dB241− = (10) AD8310 Rev. F | Page 18 of 24 OUTPUT FILTERING LOWERING THE HIGH-PASS CORNER FREQUENCY OF THE OFFSET COMPENSATION LOOP For applications in which maximum video bandwidth and, consequently, fast rise time are desired, it is essential that the BFIN pin be left unconnected and free of any stray capacitance. In normal operation using an ac-coupled input signal, the OFLT pin should be left unconnected. Input-referred dc offsets of about 1.5 mV in the signal path are nulled via an internal offset control loop. This loop has a high-pass −3 dB corner at about 2 MHz. In low frequency ac-coupled applications, it is necessary to lower this corner frequency to prevent input signals from being misinterpreted as offsets. An external capacitor on OFLT lowers the high-pass corner to arbitrarily low frequencies (Figure 36). For example, by using a 1 μF capacitor, the 3 dB corner is reduced to 60 Hz. The nominal output video bandwidth of 25 MHz can be reduced by connecting a ground-referenced capacitor (CFILT) to the BFIN pin, as shown in Figure 35. This is generally done to reduce out-put ripple (at twice the input frequency for a symmetric input waveform such as sinusoidal signals). +42μA/dB3kΩVOUTBFIN AD8310 Figure 35. Lowering the Postdemodulation Video Bandwidth CFILT is selected using the following equation: Figure 36. Lowering the High-Pass Corner Frequency of the Offset Control Loop (11) The corner frequency is set by the following equation: The video bandwidth should typically be set at a frequency equal to about one-tenth the minimum input frequency. This ensures that the output ripple of the demodulated log output, which is at twice the input frequency, is well filtered. In many log amp applications, it might be necessary to lower the corner frequency of the postdemodulation filtering to achieve low output ripple while maintaining a rapid response time to changes in signal level. An example of a 4-pole active filter is shown in the AD8307 data sheet. (12) where COFLT is the capacitor connected to OFLT. AD8310 Rev. F | Page 19 of 24 APPLICATIONS INFORMATION The AD8310 is highly versatile and easy to use. It needs only a few external components, most of which can be immediately accommodated using the simple connections shown in the Using the AD8310 section. A few examples of more specialized applications are provided in the following sections. See the AD8307 data sheet for more applications (note the slightly different pin configuration). CABLE-DRIVING For a supply voltage of 3 V or greater, the AD8310 can drive a grounded 100 Ω load to 2.5 V. If reverse-termination is required when driving a 50 Ω cable, it should be included in series with the output, as shown in Figure 37. The slope at the load is then 12 mV/dB. In some cases, it might be permissible to operate the cable without a termination at the far end, in which case the slope is not lowered. Where a further increase in slope is desirable, the scheme shown in Figure 34 can be used. AD8310VOUT50Ω50Ω Figure 37. Output Response of Cable-Driver Application DC-COUPLED INPUT It might occasionally be necessary to provide response to dc inputs. Because the AD8310 is internally dc-coupled, there is no reason why this cannot be done. However, its differential inputs must be positioned at least 2 V above the COM potential for proper biasing of the first stage. Usually, the source is a single-sided ground-referenced signal, so level-shifting and a single-ended-to-differential conversion must be provided to correctly drive the AD8310’s inputs. Figure 38 shows how a level-shift to midsupply (2.5 V in this example) and a single-ended-to-differential conversion can be accomplished using the AD8138 differential amplifier. The four 499 Ω resistors set up a gain of unity. An output common-mode (or bias) voltage of 2.5 is achieved by applying 2.5 V from a supply-referenced resistive divider to the VOCM pin of the AD8138. The differential outputs of the AD8138 directly drive the 1.1 kΩ input impedance of the AD8310. Figure 38. DC-Coupled Log Amp In this application the offset voltage of the AD8138 must be trimmed. The internal offset compensation circuitry of the AD8310 is disabled by applying a nominal voltage of ~1.9 V to the OFLT pin, so the trim on the AD8138 is effectively trimming the offsets of both devices. The trim is done by grounding the circuit’s input and slightly varying the gain resistors on the inverting input of the AD8138 (a 50 Ω potentiometer is used in this example) until the voltage on the AD8310’s output reaches a minimum. After trimming, the lower end of the dynamic range is limited by the broadband noise at the output of the AD8138, which is approximately 425 μV p-p. A differential low-pass filter can be added between the AD8138 and the AD8310 when the very fast pulse response of the circuit is not required. Figure 39. Transfer Function of DC-Coupled Log Amp Application AD8310 Rev. F | Page 20 of 24 EVALUATION BOARD An evaluation board is available that has been carefully laid out and tested to demonstrate the specified high speed performance of the AD8310. Figure 40 shows the schematic of the evaluation board, which follows the basic connections schematic shown in Figure 27. Connectors INHI, INLO, and VOUT are of the SMA type. Supply and ground are connected to the TP1 and TP2 vector pins. The layout and silkscreen for the component side of the board are shown in Figure 41 and Figure 42. Switches and component settings for different setups are described in Table 6. For ordering information, see the Ordering Guide. C20.01μFINHIENBLBFINVPOSINLOCOMMOFLTVOUTAD831012348765C40.01μFC10.01μFR352.3ΩSW1ABR40ΩR1INHIINLOTP2C7OPENW1W2R60Ω VOUTC5OPENC3OPENR50ΩTP1VPOSR2 Figure 40. Evaluation Board Schematic Figure 41. Layout of the Component Side of the Evaluation Board 01084-042 Figure 42. Component Side Silkscreen of the Evaluation Board AD8310 Rev. F | Page 21 of 24 Table 6. Evaluation Board Setup Options Component Function Default Condition TP1, TP2 Supply and Ground Vector Pins. Not applicable SW1 Device Enable. When in Position A, the ENBL pin is connected to +VS, and the AD8310 is in normal operating mode. When in Position B, the ENBL pin is connected to ground, putting the device into sleep mode. SW1 = A R1/R4 SMA Connector Grounds. Connects common of INHI and INLO SMA connectors to ground. They can be used to isolate the generator ground from the evaluation board ground. See Figure 28. R1 = R4 = 0 Ω C1, C2, R3 Input Interface. R3 (52.3 Ω) combines with the AD8310’s 1 kΩ input impedance to give an overall broadband input impedance of 50 Ω. C1, C2, and the AD8310’s input impedance combine to set a high-pass input corner of 32 kHz. Alternatively, R3, C1, and C2 can be replaced by an inductor and matching capacitors to form an input matching network. See the Input Matching section for details. R3 = 52.3 Ω, C1 = C2 = 0.01 μF C3 RSSI (Video) Bandwidth Adjust. The addition of C3 (farads) lowers the RSSI bandwidth of the AD8310’s output according to the following equation: CFILT = 1/(2π × 3 kΩ Video Bandwidth) − 2.1 pF C3 = open C4, C5, R5 Supply Decoupling. The normal supply decoupling of 0.01 μF (C4) can be augmented by a larger capacitor in C5. An inductor or small resistor can be placed in R5 for additional decoupling. C4 = 0.01 μF, C5 = open, R5 = 0 Ω R6 Output Source Impedance. In cable-driving applications, a resistor (typically 50 Ω or 75 Ω) can be placed in R6 to give the circuit a back-terminated output impedance. R6 = 0 Ω W1, W2, C6, R7 Output Loading. Resistors and capacitors can be placed in C6 and R7 to load-test VOUT. Jumper W1 and Jumper W2 are used to connect or disconnect the loads. C6 = R7 = open, W1 = W2 = installed C7 Offset Compensation Loop. A capacitor in C7 reduces the corner frequency of the offset control loop in low frequency applications. C7 = open AD8310 DIE INFORMATION Figure 43. Die Outline Dimensions Table 7. Die Pad Function Descriptions Pin No. Mnemonic Description 1 INLO One of Two Balanced Inputs. Biased roughly to VPOS/2. 2 COMM Common Pin. Usually grounded. 3 OFLT Offset Filter Access. Nominally at about 1.75 V. 4 VOUT Low Impedance Output Voltage. Carries a 25 mA maximum load. 5A, 5B VPOS Positive Supply. 2.7 V to 5.5 V at 8 mA quiescent current. 6 BFIN Buffer Input. Used to lower postdetection bandwidth. 7 ENBL CMOS Compatible Chip Enable. Active when high. 8 INHI Second of Two Balanced Inputs. Biased roughly to VPOS/2. AD8310 OUTLINE DIMENSIONS Figure 44. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding AD8310ARM −40°C to +85°C 8-Lead MSOP, Tube RM-8 J6A AD8310ARM-REEL7 −40°C to +85°C 8-Lead MSOP, 7” Tape and Reel RM-8 J6A AD8310ARMZ −40°C to +85°C 8-Lead MSOP, Tube RM-8 J6A AD8310ARMZ-REEL7 −40°C to +85°C 8-Lead MSOP, 7” Tape and Reel RM-8 J6A AD8310ACHIPS −40°C to +85°C Die AD8310-EVAL Evaluation Board 1 Z = RoHS Compliant Part. AD8310 Rev. F | Page 24 of 24 NOTES © 2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01084–0–6/10(F) 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 Q NC G Q NC F Q Q NC E A Q NC B QC B A NC CLK CLR V Q D GND NC CC H Q NC − No internal connection 1 2 3 4 5 6 7 14 13 12 11 10 9 8 A B Q Q Q Q GND A B C D VCC Q Q Q Q CLR H G F E CLK SN54HC164, SN74HC164 www.ti.com SCLS115F –DECEMBER 1982–REVISED OCTOBER 2013 8-Bit Parallel-Out Serial Shift Registers Check for Samples: SN54HC164, SN74HC164 1FEATURES DESCRIPTION • Wide Operating Voltage Range of 2 V to 6 V These 8-bit shift registers feature AND-gated serial • Outputs Can Drive Up To 10 LSTTL Loads inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control • Low Power Consumption, 80-μA Max ICC over incoming data; a low at either input inhibits entry • Typical tpd= 20 ns of the new data and resets the first flip-flop to the low • ±4-mA Output Drive at 5 V level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the • Low Input Current of 1-μA Max state of the first flip-flop. Data at the serial inputs can • AND-Gated (Enable/Disable) Serial Inputs be changed while CLK is high or low, provided the • Fully Buffered Clock and Serial Inputs minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. • Direct Clear SN54HC164...J OR W PACKAGE SN74HC164...D, N, NS, OR PW PACKAGE (TOP VIEW) SN54HC164...FK PACKAGE (TOP VIEW) FUNCTION TABLE(1)(2) INPUTS OUTPUTS CLR CLK A B QA QB . . . QH L X X X L L L H L X X QA0 QB0 QH0 H ↑ H H H QAn QGn H ↑ L X L QAn QGn H ↑ X L L QAn QGn (1) QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. (2) QAn, QGn = the level of QA or QG before the most recent ↑ transition of CLK: indicates a 1-bit shift. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1982–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. CLK A B CLR QA QB QC QD QE QF QG QH Clear Clear Serial Inputs Outputs 9 A B CLR CLK Pin numbers shown are for the D, J, N, NS, PW, and W packages. C1 1D R 3 QA C1 1D R 4 QB C1 1D R 5 QC C1 1D R 6 QD C1 1D R 10 QE C1 1D R 11 QF C1 1D R 12 QG C1 1D R 13 QH 2 1 8 SN54HC164, SN74HC164 SCLS115F –DECEMBER 1982–REVISED OCTOBER 2013 www.ti.com LOGIC DIAGRAM (POSITIVE LOGIC) TYPICAL CLEAR, SHIFT, AND CLEAR SEQUENCE 2 Submit Documentation Feedback Copyright © 1982–2013, Texas Instruments Incorporated Product Folder Links: SN54HC164 SN74HC164 SN54HC164, SN74HC164 www.ti.com SCLS115F –DECEMBER 1982–REVISED OCTOBER 2013 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNITS VCC Supply voltage range −0.5 7 V IIK Input clamp current VI < 0 or VI > VCC (2) ±20 mA IOK Output clamp current VO < 0 or VO > VCC (2) ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA Continuous current through VCC or GND ±50 mA D package 86 N package 80 θJA (3) Package thermal impedance °C/W NS package 76 PW package 113 Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS(1) SN54HC164 SN74HC164 UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V VCC = 6 V 4.2 4.2 VCC = 2 V 0.5 0.5 VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V VCC = 6 V 1.8 1.8 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 1000 1000 Δt/Δv(2) Input transition rise/fall time VCC = 4.5 V 500 500 ns VCC = 6 V 400 400 TA Operating free-air temperature −55 125 −40 125 °C (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. (2) If this device is used in the threshold region (from VIL max = 0.5 V to VIH min = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. Copyright © 1982–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: SN54HC164 SN74HC164 SN54HC164, SN74HC164 SCLS115F –DECEMBER 1982–REVISED OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) SN54HC164 SN74HC164 Recommended TA = 25°C –55°C to 125°C –55°C to 85°C SN74HC164 PARAMETER TEST CONDITIONS VCC –55°C to 125°C UNIT MIN TYP MAX MIN MAX MIN MAX MIN MAX 2 V 1.9 1.998 1.9 1.9 1.9 IOH = −20 μA 4.5 V 4.4 4.499 4.4 4.4 4.4 VOH VI = VIH or VIL 6 V 5.9 5.999 5.9 5.9 5.9 V IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84 3.7 IOH = −5.2 mA 6 V 5.48 5.8 5.2 5.34 5.2 2 V 0.002 0.1 0.1 0.1 0.1 IOL = 20 μA 4.5 V 0.001 0.1 0.1 0.1 0.1 VOL VI = VIH or VIL 6 V 0.001 0.1 0.1 0.1 0.1 V IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 0.4 IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33 0.4 II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 ±1000 nA ICC VI = VCC or 0 IO = 0 6 V 8 160 80 160 μA Ci 2 V to 6 V 3 10 10 10 10 pF TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) SN54HC164 SN74HC164 Recommended TA = 25°C –55°C to 125°C –55°C to 85°C SN74HC164 PARAMETER VCC –55°C to 125°C UNIT MIN MAX MIN MAX MIN MAX MIN MAX 2 V 6 4.2 5 4.2 fclock Clock frequency 4.5 V 31 21 25 21 MHz 6 V 36 25 28 25 2 V 100 150 125 125 CLR low 4.5 V 20 30 25 25 Pulse 6 V 17 25 21 21 tw duration ns 2 V 80 120 100 120 CLK high or low 4.5 V 16 24 20 24 6 V 14 20 18 20 2 V 100 150 125 125 Data 4.5 V 20 30 25 25 Setup time 6 V 17 25 21 25 tsu before CLK↑ ns 2 V 100 150 125 125 CLR inactive 4.5 V 20 30 25 25 6 V 17 25 21 25 2 V 5 5 5 5 th Hold time, data after CLK↑ 4.5 V 5 5 5 5 ns 6 V 5 5 5 5 4 Submit Documentation Feedback Copyright © 1982–2013, Texas Instruments Incorporated Product Folder Links: SN54HC164 SN74HC164 SN54HC164, SN74HC164 www.ti.com SCLS115F –DECEMBER 1982–REVISED OCTOBER 2013 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54HC164 SN74HC164 Recommended PARAMETE FROM TO TA = 25°C SN74HC164 (OUTPUT VCC –55°C to 125°C –55°C to 85°C –55°C to 125°C UNIT R (INPUT) ) MIN TYP MAX MIN MAX MIN MAX MIN MAX 2 V 6 10 4.2 5 4..2 fmax 4.5 V 31 54 21 25 21 MHz 6 V 36 62 25 28 25 2 V 140 205 295 255 255 tPHL CLR Any Q 4.5 V 28 41 59 51 51 6 V 24 35 51 46 46 ns 2 V 115 175 265 220 220 tpd CLK Any Q 4.5 V 23 35 53 44 44 6 V 20 30 45 38 38 2 V 38 75 110 95 110 tt 4.5 V 8 15 22 19 22 ns 6 V 6 13 19 16 19 OPERATING CHARACTERISTICS TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load 135 pF Copyright © 1982–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: SN54HC164 SN74HC164 VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PULSE DURATIONS tsu th 50% 50% 50% 10% 10% 90% 90% VCC VCC 0 V 0 V tr t Reference f Input Data Input 50% High-Level Pulse 50% VCC 0 V 50% 50% VCC 0 V t Low-Level w Pulse VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% 50% 50% 10% 10% 90% 90% VCC VOH VOL 0 V tr t Input f In-Phase Output 50% tPLH tPHL 50% 50% 10% 10% 90% 90% VOH VOL tf tr tPHL tPLH Out-of-Phase Output NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ! 1 MHz, ZO = 50 !, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Test Point From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT SN54HC164, SN74HC164 SCLS115F –DECEMBER 1982–REVISED OCTOBER 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 1982–2013, Texas Instruments Incorporated Product Folder Links: SN54HC164 SN74HC164 SN54HC164, SN74HC164 www.ti.com SCLS115F –DECEMBER 1982–REVISED OCTOBER 2013 REVISION HISTORY Changes from Revision E (November 2010) to Revision F Page • Updated document to new TI data sheet format - no specification changes. ...................................................................... 1 • Removed ordering information. ............................................................................................................................................ 1 • Updated operating temperature range. ................................................................................................................................. 3 Copyright © 1982–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: SN54HC164 SN74HC164 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 5962-8416201VCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8416201VC A SNV54HC164J 5962-8416201VDA ACTIVE CFP W 14 25 TBD A42 N / A for Pkg Type -55 to 125 5962-8416201VD A SNV54HC164W 84162012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84162012A SNJ54HC 164FK 8416201CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8416201CA SNJ54HC164J SN54HC164J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC164J SN74HC164D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164DRG3 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164DT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU | CU SN N / A for Pkg Type -40 to 125 SN74HC164N SN74HC164N3 OBSOLETE PDIP N 14 TBD Call TI Call TI -40 to 125 SN74HC164NE3 PREVIEW PDIP N 14 25 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SN74HC164N SN74HC164NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 SN74HC164N PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74HC164NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164PWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SN74HC164PWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 SNJ54HC164FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84162012A SNJ54HC 164FK SNJ54HC164J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8416201CA SNJ54HC164J SNJ54HC164W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 8416201DA SNJ54HC164W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 3 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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OTHER QUALIFIED VERSIONS OF SN54HC164, SN54HC164-SP, SN74HC164 : • Catalog: SN74HC164, SN54HC164 • Military: SN54HC164 • Space: SN54HC164-SP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74HC164DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC164DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC164DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 SN74HC164DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 SN74HC164DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC164DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC164DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC164NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HC164PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC164PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Apr-2014 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC164DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC164DR SOIC D 14 2500 333.2 345.9 28.6 SN74HC164DR SOIC D 14 2500 364.0 364.0 27.0 SN74HC164DRG3 SOIC D 14 2500 364.0 364.0 27.0 SN74HC164DRG4 SOIC D 14 2500 333.2 345.9 28.6 SN74HC164DRG4 SOIC D 14 2500 367.0 367.0 38.0 SN74HC164DT SOIC D 14 250 367.0 367.0 38.0 SN74HC164NSR SO NS 14 2000 367.0 367.0 38.0 SN74HC164PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74HC164PWT TSSOP PW 14 250 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 7-Apr-2014 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. FEATURES Wide bandwidth: 0.1 GHz to 2.5 GHz min High dynamic range: 70 dB to ±3.0 dB High accuracy: ±1.0 dB over 65 dB range (@ 1.9 GHz) Fast response: 40 ns full-scale typical Controller mode with error output Scaling stable over supply and temperature Wide supply range: 2.7 V to 5.5 V Low power: 40 mW at 3 V Power-down feature: 60 mW at 3 V Complete and easy to use APPLICATIONS RF transmitter power amplifier setpoint control and level monitoring Logarithmic amplifier for RSSI measurement cellular base stations, radio link, radar FUNCTIONAL BLOCK DIAGRAM +++++AD8313VOUTVSETCOMMPWDNGAINBIASBAND GAPREFERENCESLOPECONTROLINTERCEPTCONTROLEIGHT 8dB 3.5GHz AMPLIFIER STAGES8dB8dBVPOSINHIINLOVPOS8dB8dBNINE DETECTOR CELLSCINTLPI→VV→I1876523401085-C-001 Figure 1. GENERAL DESCRIPTION The AD8313 is a complete multistage demodulating logarithmic amplifier that can accurately convert an RF signal at its differ-ential input to an equivalent decibel-scaled value at its dc output. The AD8313 maintains a high degree of log conformance for signal frequencies from 0.1 GHz to 2.5 GHz and is useful over the range of 10 MHz to 3.5 GHz. The nominal input dynamic range is –65 dBm to 0 dBm (re: 50 Ω), and the sensitivity can be increased by 6 dB or more with a narrow-band input impedance matching network or a balun. Application is straightforward, requiring only a single supply of 2.7 V to 5.5 V and the addition of a suitable input and supply decoupling. Operating on a 3 V supply, its 13.7 mA consumption (for TA = 25°C) is only 41 mW. A power-down feature is provided; the input is taken high to initiate a low current (20 μA) sleep mode, with a threshold at half the supply voltage. The AD8313 uses a cascade of eight amplifier/limiter cells, each having a nominal gain of 8 dB and a −3 dB bandwidth of 3.5 GHz. This produces a total midband gain of 64 dB. At each amplifier output, a detector (rectifier) cell is used to convert the RF signal to baseband form; a ninth detector cell is placed directly at the input of the AD8313. The current-mode outputs of these cells are summed to generate a piecewise linear approxi-mation to the logarithmic function. They are converted to a low impedance voltage-mode output by a transresistance stage, which also acts as a low-pass filter. When used as a log amplifier, scaling is determined by a separate feedback interface (a transconductance stage) that sets the slope to approximately 18 mV/dB; used as a controller, this stage accepts the setpoint input. The logarithmic intercept is positioned to nearly −100 dBm, and the output runs from about 0.45 V dc at −73 dBm input to 1.75 V dc at 0 dBm input. The scale and intercept are supply- and temperature-stable. The AD8313 is fabricated on Analog Devices’ advanced 25 GHz silicon bipolar IC process and is available in an 8-lead MSOP package. The operating temperature range is −40°C to +85°C. An evaluation board is available. INPUT AMPLITUDE (dBm)2.0–80OUTPUT VOLTAGE ( V DC)1.81.61.41.21.00.80.60.40.20–70–60–50–40–30–20–100FREQUENCY = 1.9GHz543210–1–2–3–4–5OUTPUT ERROR ( dB)01085-C-002 Figure 2. Typical Logarithmic Response and Error vs. Input Amplitude AD8313 Rev. D | Page 2 of 24 TABLE OF CONTENTS Specifications.....................................................................................3 Absolute Maximum Ratings............................................................6 ESD Caution..................................................................................6 Pin Configurations and Function Description.............................7 Typical Performance Characteristics.............................................8 Circuit Description.........................................................................11 Interfaces..........................................................................................13 Power-Down Interface, PWDN................................................13 Signal Inputs, INHI, INLO........................................................13 Logarithmic/Error Output, VOUT..........................................13 Setpoint Interface, VSET............................................................14 Applications.....................................................................................15 Basic Connections for Log (RSSI) Mode.................................15 Operating in Controller Mode.................................................15 Input Coupling...........................................................................16 Narrow-Band LC Matching Example at 100 MHz................16 Adjusting the Log Slope.............................................................18 Increasing Output Current........................................................19 Effect of Waveform Type on Intercept.....................................19 Evaluation Board............................................................................20 Schematic and Layout................................................................20 General Operation.....................................................................20 Using the AD8009 Operational Amplifier..............................20 Varying the Logarithmic Slope.................................................20 Operating in Controller Mode.................................................20 RF Burst Response.....................................................................20 Outline Dimensions.......................................................................24 Ordering Guide..........................................................................24 REVISION HISTORY 6/04—Data Sheet Changed from Rev. C to Rev. D Updated Evaluation Board Section..............................................21 2/03—Data Sheet changed from Rev. B to Rev. C TPCs and Figures Renumbered........................................Universal Edits to SPECIFICATIONS.............................................................2 Updated ESD CAUTION................................................................4 Updated OUTLINE DIMENSIONS..............................................7 8/99—Data Sheet changed from Rev. A to Rev. B 5/99—Data Sheet changed from Rev. 0 to Rev. A 8/98—Revision 0: Initial Version AD8313 Rev. D | Page 3 of 24 SPECIFICATIONS TA = 25°C, VS = 5 V1, RL 10 kΩ, unless otherwise noted. Table 1. Parameter Conditions Min2 Typ Max2 Unit SIGNAL INPUT INTERFACE Specified Frequency Range 0.1 2.5 GHz DC Common-Mode Voltage VPOS – 0.75 V Input Bias Currents 10 μA Input Impedance fRF < 100 MHz3 900||1.1 Ω||pF4 LOG (RSSI) MODE Sinusoidal, input termination configuration shown in Figure 29 100 MHz5 Nominal conditions ±3 dB Dynamic Range6 53.5 65 dB Range Center −31.5 dBm ±1 dB Dynamic Range 56 dB Slope 17 19 21 mV/dB Intercept −96 −88 −80 dBm 2.7 V ≤ VS ≤ 5.5 V, −40°C ≤ T ≤ +85°C ±3 dB Dynamic Range 51 64 dB Range Center −31 dBm ±1 dB Dynamic Range 55 dB Slope 16 19 22 mV/dB Intercept −99 −89 −75 dBm Temperature Sensitivity PIN = −10 dBm −0.022 dB/°C 900 MHz5 Nominal conditions ±3 dB Dynamic Range 60 69 dB Range Center −32.5 dBm ±1 dB Dynamic Range 62 dB Slope 15.5 18 20.5 mV/dB Intercept −105 −93 −81 dBm 2.7 V ≤ VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C ±3 dB Dynamic Range 55.5 68.5 dB Range Center –32.75 dBm ±1 dB Dynamic Range 61 dB Slope 15 18 21 mV/dB Intercept –110 –95 –80 dBm Temperature Sensitivity PIN = –10 dBm –0.019 dB/°C 1.9 GHz7 Nominal conditions ±3 dB Dynamic Range 52 73 dB Range Center –36.5 dBm ±1 dB Dynamic Range 62 dB Slope 15 17.5 20.5 mV/dB Intercept –115 –100 –85 dBm 2.7 V ≤ VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C ±3 dB Dynamic Range 50 73 dB Range Center –36.5 dBm ±1 dB Dynamic Range 60 dB Slope 14 17.5 21.5 mV/dB Intercept –125 –101 –78 dBm Temperature Sensitivity PIN = –10 dBm –0.019 dB/°C AD8313 Rev. D | Page 4 of 24 Parameter Conditions Min2 Typ Max2 Unit 2.5 GHz7 Nominal conditions ±3 dB Dynamic Range 48 66 dB Range Center –34 dBm ±1 dB Dynamic Range 46 dB Slope 16 20 25 mV/dB Intercept –111 –92 –72 dBm 2.7 V ≤ VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C ±3 dB Dynamic Range 47 68 dB Range Center –34.5 dBm ±1 dB Dynamic Range 46 dB Slope 14.5 20 25 mV/dB Intercept –128 –92 –56 dBm Temperature Sensitivity PIN =–10 dBm –0.040 dB/°C 3.5 GHz5 Nominal conditions ±3 dB Dynamic Range 43 dB ±1 dB Dynamic Range 35 dB Slope 24 mV/dB Intercept –65 dBm CONTROL MODE Controller Sensitivity f = 900 MHz 23 V/dB Low Frequency Gain VSET to VOUT8 84 dB Open-Loop Corner Frequency VSET to VOUT8 700 Hz Open-Loop Slew Rate f = 900 MHz 2.5 V/μs VSET Delay Time 150 ns VOUT INTERFACE Current Drive Capability Source Current 400 μA Sink Current 10 mA Minimum Output Voltage Open-loop 50 mV Maximum Output Voltage Open-loop VPOS – 0.1 V Output Noise Spectral Density PIN = –60 dBm, fSPOT = 100 Hz 2.0 μV/√Hz PIN = –60 dBm, fSPOT = 10 MHz 1.3 μV/√Hz Small Signal Response Time PIN = –60 dBm to –57 dBm, 10% to 90% 40 60 ns Large Signal Response Time PIN = No signal to 0 dBm; settled to 0.5 dB 110 160 ns VSET INTERFACE Input Voltage Range 0 VPOS V Input Impedance 18||1 kΩ||pF4 POWER-DOWN INTERFACE PWDN Threshold VPOS/2 V Power-Up Response Time Time delay following high to low transition until device meets full specifications. 1.8 μs PWDN Input Bias Current PWDN = 0 V 5 μA PWDN = VS <1 μA POWER SUPPLY Operating Range 2.7 5.5 V Powered-Up Current 13.7 15.5 mA 4.5 V ≤VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C 18.5 mA 2.7 V ≤VS ≤ 3.3 V, –40°C ≤ T ≤ +85°C 18.5 mA Powered-Down Current 4.5 V ≤VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C 50 150 μA 2.7 V ≤VS ≤ 3.3 V, –40°C ≤ T ≤ +85°C 20 50 μA AD8313 Rev. D | Page 5 of 24 1 Except where otherwise noted; performance at VS = 3 V is equivalent to 5 V operation. 2 Minimum and maximum specified limits on parameters that are guaranteed but not tested are 6 sigma values. 3 Input impedance shown over frequency range in Figure 26. 4 Double vertical bars (||) denote “in parallel with.” 5 Linear regression calculation for error curve taken from –40 dBm to –10 dBm for all parameters. 6 Dynamic range refers to range over which the linearity error remains within the stated bound. 7 Linear regression calculation for error curve taken from –60 dBm to –5 dBm for 3 dB dynamic range. All other regressions taken from –40 dBm to –10 dBm. 8 AC response shown in Figure 12. AD8313 Rev. D | Page 6 of 24 ABSOLUTE MAXIMUM RATINGS Table 2. Supply Voltage VS 5.5 V VOUT, VSET, PWDN 0 V, VPOS Input Power Differential (re: 50 Ω, 5.5 V) 25 dBm Input Power Single-Ended (re: 50 Ω, 5.5 V) 19 dBm Internal Power Dissipation 200 mW θJA 200°C/W Maximum Junction Temperature 125°C Operating Temperature Range –40°C to +85°C Storage Temperature Range –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. AD8313 Rev. D | Page 7 of 24 PIN CONFIGURATIONS AND FUNCTION DESCRIPTION VPOS1INHI2INLO3VPOS4VOUT8VSET7COMM6PWDN5AD8313TOP VIEW(Not to Scale)01085-C-003 Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1, 4 VPOS Positive Supply Voltage (VPOS), 2.7 V to 5.5 V. 2 INHI Noninverting Input. This input should be ac-coupled. 3 INLO Inverting Input. This input should be ac-coupled. 5 PWDN Connect Pin to Ground for Normal Operating Mode. Connect this pin to the supply for power-down mode. 6 COMM Device Common. 7 VSET Setpoint Input for Operation in Controller Mode. To operate in RSSI mode, short VSET and VOUT. 8 VOUT Logarithmic/Error Output. AD8313 Rev. D | Page 8 of 24 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = 5 V, RL input match shown in Figure 29, unless otherwise noted. INPUT AMPLITUDE (dBm)2.0–70VOUT ( V)1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–100101.9GHz2.5GHz900MHz100MHz01085-C-004 Figure 4. VOUT vs. Input Amplitude INPUT AMPLITUDE (dBm)6–6–7010–60ERROR ( dB)–50–40–30–20–100420–2–4900MHz100MHz100MHz900MHz1.9GHz2.5GHz2.5GHz1.9GHz01085-C-005 Figure 5. Log Conformance vs. Input Amplitude INPUT AMPLITUDE (dBm)2.0–70VOUT ( V)1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–10010543210–1–2–3–4–5ERROR ( dB)–40°C+25°C+85°CSLOPE AND INTERCEPT NORMALIZED AT +25°CAND APPLIED TO–40°C AND +85°C01085-C-006 Figure 6. VOUT and Log Conformance vs. Input Amplitude at 100 MHz for Multiple Temperatures INPUT AMPLITUDE (dBm)2.0–70VOUT ( V)1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–10010543210–1–2–3–4–5ERROR ( dB)+25°C+85°C–40°CSLOPE AND INTERCEPT NORMALIZED AT +25°CAND APPLIED TO–40°C AND +85°C01-85-C-007 Figure 7. VOUT and Log Conformance vs. Input Amplitude at 900 MHz for Multiple Temperatures INPUT AMPLITUDE (dBm)2.0–70VOUT ( V)1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–10010543210–1–2–3–4–5ERROR ( dB)–40°C+25°C+85°CSLOPE AND INTERCEPT NORMALIZED AT +25°CAND APPLIED TO–40°C AND +85°C01085-C-008 Figure 8. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz for Multiple Temperatures INPUT AMPLITUDE (dBm)2.0–70VOUT ( V)1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–10010543210–1–2–3–4–5ERROR ( dB)–40°C+25°C+85°CSLOPE AND INTERCEPTNORMALIZED AT +25°C ANDAPPLIED TO–40°C AND +85°C01085-C-009 Figure 9. VOUT and Log Conformance vs. Input Amplitude at 2.5 GHz for Multiple Temperatures AD8313 Rev. D | Page 9 of 24 FREQUENCY (MHz)22211602500500SLOPE ( mV/dB)10001500200020191817–40°C+25°C+85°C01085-C-010 Figure 10. VOUT Slope vs. Frequency for Multiple Temperatures SUPPLY VOLTAGE (V)242.5SLOPE ( mV/dB)232221201918171615143.03.54.04.55.05.56.01.9GHz2.5GHz900MHz100MHzSPECIFIED OPERATING RANGE01085-C-011 Figure 11. VOUT Slope vs. Supply Voltage FREQUENCY (Hz)VSET TO VOUT GAIN (dB)1001k10k100k1M REF LEVEL = 92dBSCALE: 10dB/DIV01085-C-012 Figure 12. AC Response from VSET to VOUTFREQUENCY (MHz)–11002500500INTERCEPT ( dBm)100015002000–70–80–90–100+85°C–40°C+25°C01085-C-013 Figure 13. VOUT Intercept vs. Frequency for Multiple Temperatures SUPPLY VOLTAGE (V)–702.5INTERCEPT ( dBm)–75–80–85–90–95–100–105–1103.03.54.04.55.05.56.01.9GHz2.5GHz900MHz100MHzSPECIFIED OPERATING RANGE01085-C-014 Figure 14. VOUT Intercept vs. Supply Voltage FREQUENCY (Hz)100100.1μV/ Hz11k10k100k1M10M2GHz RF INPUTRF INPUT–70dBm–60dBm–55dBm–50dBm–45dBm–40dBm–35dBm–30dBm01085-C-015 Figure 15. VOUT Noise Spectral Density AD8313 Rev. D | Page 10 of 24 PWDN VOLTAGE (V)0100.00SUPPLY CURRENT ( mA)10.001.000.100.012134 5 40μAVPOS = +3VVPOS = +5V20μA13.7mA01085-C-016 Figure 16. Typical Supply Current vs. PWDN Voltage CH. 1 AND CH. 2: 1V/DIVCH. 3: 5V/DIVHORIZONTAL: 1μs/DIVVOUT @VS = +5.5VPWDNCH. 1 GNDCH. 2 GNDCH. 3 GNDVOUT @VS = +2.7V01085-C-017 Figure 17. PWDN Response Time CH. 1CH. 1 GNDCH. 2 GNDCH. 2CH. 1 AND CH. 2: 200mV/DIVAVERAGE: 50 SAMPLESVS = +5.5VVS = +2.7VHORIZONTAL: 50ns/DIVPULSED RF100MHz,–45dBm01085-C-019 Figure 18. Response Time, No Signal to –45 dBm CH.1&CH.2:500mV/DIVAVERAGE:50SAMPLESHORIZONTAL:50ns/DIVCH. 1 GNDCH. 2 GNDPULSED RF100MHz,0dBmCH.1CH.2VS = +5.5VVS = +2.7V01085-C-020 Figure 19. Response Time, No Signal to 0 dBm ________________________________________________________________________________________________________________________________ HP8648BSIGNALGENERATORHP8112APULSEGENERATOR0.1μF54.9Ω0.01μF0.01μF10Ω10Ω0.1μF+VS+VSTEKTDS784CSCOPE87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD8313TEK P6205FET PROBETRIG0603 SIZE SURFACEMOUNT COMPONENTS ONA LOW LEAKAGE PC BOARDEXT TRIGOUTPIN = 0dBmRF OUT10MHz REF OUTPUT01085-C-018 Figure 20. Test Setup for PWDN Response Time 0.1μF54.9Ω0.01μF0.01μF10Ω10Ω0.1μF+VS+VSTEKTDS784CSCOPE87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD8313TEK P6205FET PROBETRIG0603 SIZE SURFACEMOUNT COMPONENTS ONA LOW LEAKAGE PC BOARD01085-C-021TRIGOUTEXT TRIGRF OUT10MHz REF OUTPUT–6dBRFSPLITTER–6dBHP8648BSIGNALGENERATORPULSEMODULATIONMODEPULSE MODE INOUTHP8112APULSEGENERATOR Figure 21. Test Setup for RSSI Mode Pulse Response AD8313 Rev. D | Page 11 of 24 CIRCUIT DESCRIPTION The AD8313 is an 8-stage logarithmic amplifier, specifically designed for use in RF measurement and power amplifier control applications at frequencies up to 2.5 GHz. A block diagram is shown in Figure 22. For a detailed description of log amp theory and design principles, refer to the AD8307 data sheet. +++++AD8313VOUTVSETCOMMPWDNGAINBIASBAND GAPREFERENCESLOPECONTROLINTERCEPTCONTROLEIGHT 8dB 3.5GHz AMPLIFIER STAGES8dB8dBVPOSINHIINLOVPOS8dB8dBNINE DETECTOR CELLSCINTLPI→VV→I1876523401085-C-001 Figure 22. Block Diagram A fully differential design is used. Inputs INHI and INLO (Pins 2 and 3) are internally biased to approximately 0.75 V below the supply voltage, and present a low frequency impedance of nominally 900 Ω in parallel with 1.1 pF. The noise spectral density referred to the input is 0.6 nV/√Hz, equivalent to a voltage of 35 V rms in a 3.5 GHz bandwidth, or a noise power of −76 dBm re: 50 Ω. This sets the lower limit to the dynamic range; the Applications section shows how to increase the sensitivity by using a matching network or input transformer. However, the low end accuracy of the AD8313 is enhanced by specially shaping the demodulation transfer characteristic to partially compensate for errors due to internal noise. Each of the eight cascaded stages has a nominal voltage gain of 8 dB and a bandwidth of 3.5 GHz. Each stage is supported by precision biasing cells that determine this gain and stabilize it against supply and temperature variations. Since these stages are direct-coupled and the dc gain is high, an offset compensation loop is included. The first four stages and the biasing system are powered from Pin 4, while the later stages and the output inter-faces are powered from Pin 1. The biasing is controlled by a logic interface PWDN (Pin 5); this is grounded for normal operation, but may be taken high (to VS) to disable the chip. The threshold is at VPOS/2 and the biasing functions are enabled and disabled within 1.8 μs. Each amplifier stage has a detector cell associated with its output. These nonlinear cells perform an absolute value (full-wave rectification) function on the differential voltages along this backbone in a transconductance fashion; their outputs are in current-mode form and are thus easily summed. A ninth detector cell is added at the input of the AD8313. Since the midrange response of each of these nine detector stages is separated by 8 dB, the overall dynamic range is about 72 dB (Figure 23). The upper end of this range is determined by the capacity of the first detector cell, and occurs at approximately 0 dBm. The practical dynamic range is over 70 dB to the ±3 dB error points. However, some erosion of this range can occur at temperature and frequency extremes. Useful operation to over 3 GHz is possible, and the AD8313 remains serviceable at 10 MHz, needing only a small amount of additional ripple filtering. INPUT AMPLITUDE (dBm)2.0–80VOUT ( V)1.81.61.41.21.00.80.60.40.20–70–60–50–40–30–20–100543210–1–2–3–4–5ERROR ( dB)–90INTERCEPT =–100dBmSLOPE = 18mV/dB01085-c-023 Figure 23. Typical RSSI Response and Error vs. Input Power at 1.9 GHz The fluctuating current output generated by the detector cells, with a fundamental component at twice the signal frequency, is filtered first by a low-pass section inside each cell, and then by the output stage. The output stage converts these currents to a voltage, VOUT, at VOUT (Pin 8), which can swing rail-to-rail. The filter exhibits a 2-pole response with a corner at approximately 12 MHz and full-scale rise time (10% to 90%) of 40 ns. The residual output ripple at an input frequency of 100 MHz has an amplitude of under 1 mV. The output can drive a small resistive load; it can source currents of up to 400 μA, and sink up to 10 mA. The output is stable with any capacitive load, though settling time could be impaired. The low frequency incremental output impedance is approximately 0.2 Ω. In addition to its use as an RF power measurement device (that is, as a logarithmic amplifier), the AD8313 may also be used in controller applications by breaking the feedback path from VOUT to VSET (Pin 7), which determines the slope of the output (nominally 18 mV/dB). This pin becomes the setpoint input in controller modes. In this mode, the voltage VOUT remains close to ground (typically under 50 mV) until the decibel equivalent of the voltage VSET is reached at the input, when VOUT makes a rapid transition to a voltage close to VPOS (see the Operating in Controller Mode section). The logarithmic intercept is nominally positioned at −100 dBm (re: 50 Ω); this is effective in both the log amp mode and the controller mode. AD8313 Rev. D | Page 12 of 24 With Pins 7 and 8 connected (log amp mode), the output can be stated as )dBm100(+=INSLOPEOUTPVV where PIN is the input power stated in dBm when the source is directly terminated in 50 Ω. However, the input impedance of the AD8313 is much higher than 50 Ω, and the sensitivity of this device may be increased by about 12 dB by using some type of matching network (see below), which adds a voltage gain and lowers the intercept by the same amount. Dependence on the ref-erence impedance can be avoided by restating the expression as )V2.2/(log20μ×××=INSLOPEOUTVVV where VIN is the rms value of a sinusoidal input appearing across Pins 2 and 3; here, 2.2 μV corresponds to the intercept, expressed in voltage terms. For detailed information on the effect of signal waveform and metrics on the intercept positioning for a log amp, refer to the AD8307 data sheet. With Pins 7 and 8 disconnected (controller mode), the output can be stated as SETINSLOPESOUTVPVVV>→)100/(logwhen SETINSLOPEOUTVPVV<→)100/(logwhen0 when the input is stated in terms of the power of a sinusoidal signal across a net termination impedance of 50 Ω. The transition zone between high and low states is very narrow since the output stage behaves essentially as a fast integrator. The above equations can be restated as SETINSLOPESOUTVVVVV>μ→)V2.2/(logwhen SETINSLOPEOUTVVVV<μ→)V2.2/(logwhen0 Another use of the separate VOUT and VSET pins is in raising the load-driving current capability by including an external NPN emitter follower. More complete information about usage in these modes is provided in the Applications section. AD8313 Rev. D | Page 13 of 24 INTERFACES This section describes the signal and control interfaces and their behavior. On-chip resistances and capacitances exhibit variations of up to ±20%. These resistances are sometimes temperature-dependent, and the capacitances may be voltage-dependent. POWER-DOWN INTERFACE, PWDN The power-down threshold is accurately centered at the midpoint of the supply as shown in Figure 24. If Pin 5 is left unconnected or tied to the supply voltage (recommended), the bias enable current is shut off, and the current drawn from the supply is predominately through a nominal 300 kΩ chain (20 μA at 3 V). When grounded, the bias system is turned on. The threshold level is accurately at VPOS/2. When operating in the device ON state, the input bias current at the PWDN pin is approximately 5 μA for VPOS = 3 V. 5PWDNVPOS75kΩ6COMM150kΩ50kΩ150kΩTO BIASENABLE401085-C-024 Figure 24. Power-Down Threshold Circuitry SIGNAL INPUTS, INHI, INLO The simplest low frequency ac model for this interface consists of just a 900 Ω resistance, RIN, in shunt with a 1.1 pF input cap-acitance, CIN, connected across INHI and INLO. Figure 25 shows these distributed in the context of a more complete schematic. The input bias voltage shown is for the enabled chip; when disabled, it rises by a few hundred millivolts. If the input is coupled via capacitors, this change may cause a low level signal transient to be introduced, having a time constant formed by these capacitors and RIN. For this reason, large coupling capacitors should be well matched. This is not necessary when using the small capacitors found in many impedance transforming networks used at high frequencies. 1.25kΩCOMMVPOSINHIINLOVPOS0.5pF0.5pF0.7pF2.5kΩ2.5kΩ~0.75V(1ST DETECTOR)250Ω~1.4mA125Ω125Ω1.25kΩ1.24VGAIN BIASTO 2NDSTAGETO STAGES1 TO 4123401085-C-025 Figure 25. Input Interface Simplified Schematic For high frequency use, Figure 26 shows the input impedance plotted on a Smith chart. This measured result of a typical device includes a 191 mil 50 Ω trace and a 680 pF capacitor to ground from the INLO pin. 1.1pF900Ω1.9GHzFrequency100MHz900MHz1.9GHz2.5GHzR650552223+jX–j400–j135–j65–j432.5GHz900MHz100MHzAD8313 MEASURED01085-C-026 Figure 26. Typical Input Impedance LOGARITHMIC/ERROR OUTPUT, VOUT The rail-to-rail output interface is shown in Figure 27. VOUT can run from within about 50 mV of ground, to within about 100 mV of the supply voltage, and is short-circuit safe to either supply. However, the sourcing load current, ISOURCE, is limited to that which is provided by the PNP transistor, typically 400 μA. Larger load currents can be provided by adding an external NPN transistor (see the Applications section). The dc open-loop gain of this amplifier is high, and it may be regarded as an integrator having a capacitance of 2 pF (CINT) driven by the current-mode signal generated by the summed outputs of the nine detector stages, which is scaled approximately 4.0 μA/dB. COMMgmSTAGECINTLPLM10mAMAXVOUTCLBIASISOURCE400μAVPOSFROMSETPOINTSUMMEDDETECTOROUTPUTS68101085-C-027 Figure 27. Output Interface Circuitry Thus, for midscale RF input of about 3 mV, which is some 40 dB above the minimum detector output, this current is 160 μA, and the output changes by 8 V/μs. When VOUT is connected to VSET, the rise and fall times are approximately 40 ns (for RL ≥ 10 kΩ ). The nominal slew rate is 2.5 V/μs. The HF compensation tech-nique results in stable operation with a large capacitive load, CL, though the positive-going slew rate is then limited by ISOURCE/CL to 1 V/μs for CL = 400 pF. AD8313 Rev. D | Page 14 of 24 SETPOINT INTERFACE, VSET The setpoint interface is shown in Figure 28. The voltage, VSET, is divided by a factor of 3 in a resistive attenuator of 18 kΩ total resistance. The signal is converted to a current by the action of the op amp and the resistor R3 (1.5 kΩ), which balances the current generated by the summed output of the nine detector cells at the input to the previous cell. The logarithmic slope is nominally 3 μs × 4.0 μA/dB × 1.5 kΩ = 18 mV/dB. 8VSETVPOSR112kΩR26kΩ6COMM25μA25μAFDBKTO O/PSTAGE1R31.5kΩLP01085-C-028 Figure 28. Setpoint Interface Circuitry AD8313 Rev. D | Page 15 of 24 APPLICATIONS BASIC CONNECTIONS FOR LOG (RSSI) MODE Figure 29 shows the AD8313 connected in its basic measurement mode. A power supply between 2.7 V and 5.5 V is required. The power supply to each of the VPOS pins should be decoupled with a 0.1 μF surface-mount ceramic capacitor and a 10 Ω series resistor. The PWDN pin is shown as grounded. The AD8313 may be disabled by a logic high at this pin. When disabled, the chip current is reduced to about 20 μA from its normal value of 13.7 mA. The logic threshold is at VPOS/2, and the enable function occurs in about 1.8 μs. However, that additional settling time is generally needed at low input levels. While the input in this case is terminated with a simple 50 Ω broadband resistive match, there are many ways in which the input termi-nation can be accomplished. These are discussed in the Input Coupling section. VSET is connected to VOUT to establish a feedback path that controls the overall scaling of the logarithmic amplifier. The load resistance, RL, should not be lower than 5 kΩ so that the full-scale output of 1.75 V can be generated with the limited available current of 400 μA max. As stated in the Absolute Maximum Ratings table, an externally applied overvoltage on the VOUT pin, which is outside the range 0 V to VPOS, is sufficient to cause permanent damage to the device. If overvoltages are expected on the VOUT pin, a series resistor, RPROT, should be included as shown. A 500 Ω resistor is sufficient to protect against overvoltage up to ±5 V; 1000 Ω should be used if an overvoltage of up to ±15 V is expected. Since the output stage is meant to drive loads of no more than 400 μA, this resistor does not impact device perform-ance for higher impedance drive applications (higher output current applications are discussed in the Increasing Output Current section). 0.1μF53.6Ω680pF680pFR110ΩR210Ω0.1μF+VS+VS87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD8313RPROTRL= 1MΩ01085-C-029 Figure 29. Basic Connections for Log (RSSI) Mode OPERATING IN CONTROLLER MODE Figure 30 shows the basic connections for operation in controller mode. The link between VOUT and VSET is broken and a set-point is applied to VSET. Any difference between VSET and the equivalent input power to the AD8313 drives VOUT either to the supply rail or close to ground. If VSET is greater than the equivalent input power, VOUT is driven toward ground, and vice versa. 0.1μFR110ΩR310Ω0.1μF+VS+VS87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD8313RPROT01085-C-030 Figure 30. Basic Connections for Operation in the Controller Mode This mode of operation is useful in applications where the output power of an RF power amplifier (PA) is to be controlled by an analog AGC loop (Figure 31). In this mode, a setpoint voltage, proportional in dB to the desired output power, is applied to the VSET pin. A sample of the output power from the PA, via a directional coupler or other means, is fed to the input of the AD8313. SETPOINTCONTROL DACRFINVOUTVSETAD8313DIRECTIONALCOUPLERPOWERAMPLIFIERRF INENVELOPE OFTRANSMITTEDSIGNAL01085-C-031 Figure 31. Setpoint Controller Operation VOUT is applied to the gain control terminal of the power amplifier. The gain control transfer function of the power amplifier should be an inverse relationship, that is, increasing voltage decreases gain. A positive input step on VSET (indicating a demand for increased power from the PA) drives VOUT toward ground. This should be arranged to increase the gain of the PA. The loop settles when VOUT settles to a voltage that sets the input power to the AD8313 to the dB equivalent of VSET. AD8313 Rev. D | Page 16 of 24 INPUT COUPLING The signal can be coupled to the AD8313 in a variety of ways. In all cases, there must not be a dc path from the input pins to ground. Some of the possibilities include dual-input coupling capacitors, a flux-linked transformer, a printed circuit balun, direct drive from a directional coupler, or a narrow-band impedance matching network. Figure 32 shows a simple broadband resistive match. A termination resistor of 53.6 Ω combines with the internal input impedance of the AD8313 to give an overall resistive input impedance of approximately 50 Ω. It is preferable to place the termination resistor directly across the input pins, INHI to INLO, where it lowers the possible deleterious effects of dc offset voltages on the low end of the dynamic range. At low frequencies, this may not be quite as beneficial, since it requires larger coupling capacitors. The two 680 pF input coupling capacitors set the high-pass corner frequency of the network at 9.4 MHz. RMATCH53.6ΩC2680pFC1680pFCINRINAD831350Ω50ΩSOURCE01085-C-032 Figure 32. A Simple Broadband Resistive Input Termination The high-pass corner frequency can be set higher according to the equation 50213××π×=CfdB where: C2C1C2C1C××= In high frequency applications, the use of a transformer, balun, or matching network is advantageous. The impedance matching characteristics of these networks provide what is essentially a gain stage before the AD8313 that increases the device sensitivity. This gain effect is explored in the following matching example. Figure 33 and Figure 34 show device performance under these three input conditions at 900 MHz and 1.9 GHz. While the 900 MHz case clearly shows the effect of input matching by realigning the intercept as expected, little improvement is seen at 1.9 GHz. Clearly, if no improvement in sensitivity is required, a simple 50 Ω termination may be the best choice for a given design based on ease of use and cost of components. INPUT AMPLITUDE (dBm)–80–70–60–50–40–30–20–103210–1–2–3ERROR ( dB)TERMINATEDDR = 66dB–90100BALANCEDMATCHEDBALANCEDDR = 71dBMATCHEDDR = 69dB01085-C-033 Figure 33. Comparison of Terminated, Matched, and Balanced Input Drive at 900 MHz INPUT AMPLITUDE (dBm)–80–70–60–50–40–30–20–1003210–1–2–3ERROR ( dB)–9010TERMINATEDDR = 75dBBALANCEDBALANCEDDR = 75dBMATCHEDDR = 73dBMATCHEDTERMINATED01085-C-034 Figure 34. Comparison of Terminated, Matched, and Balanced Input Drive at 1.9 GHz NARROW-BAND LC MATCHING EXAMPLE AT 100 MHz While numerous software programs provide an easy way to calculate the values of matching components, a clear under-standing of the calculations involved is valuable. A low frequency (100 MHz) value has been used for this example because of the deleterious board effects at higher frequencies. RF layout simulation software is useful when board design at higher frequencies is required. A narrow-band LC match can be implemented either as a series-inductance/shunt-capacitance or as a series-capacitance/ shunt-inductance. However, the concurrent requirement that the AD8313 inputs, INHI and INLO, be ac-coupled, makes a series-capacitance/shunt-inductance type match more appropriate (Figure 35). AD8313 Rev. D | Page 17 of 24 LMATCHC2C1CINRINAD831350Ω50ΩSOURCE01085-C-035 Figure 35. Narrow-Band Reactive Match Typically, the AD8313 needs to be matched to 50 Ω. The input impedance of the AD8313 at 100 MHz can be read from the Smith chart (Figure 26) and corresponds to a resistive input impedance of 900 Ω in parallel with a capacitance of 1.1 pF. To make the matching process simpler, the AD8313 input cap-acitance, CIN, can be temporarily removed from the calculation by adding a virtual shunt inductor (L2), which resonates away CIN (Figure 36). This inductor is factored back into the calculation later. This allows the main calculation to be based on a simple resistive-to-resistive match, that is, 50 Ω to 900 Ω. The resonant frequency is defined by the equation INCL2×=ω1 therefore, H3.212μ=ω=INCL2 L1C2C1CINCMATCH=(C1× C2)(C1 + C2)RINAD831350Ω50ΩSOURCE01085-C-036L2TEMPORARYINDUCTANCELMATCH=(C1× C2)(C1 + C2) Figure 36. Input Matching Example With CIN and L2 temporarily out of the picture, the focus is now on matching a 50 Ω source resistance to a (purely resistive) load of 900 Ω and calculating values for CMATCH and L1. When MATCHINSCL1RR= the input looks purely resistive at a frequency given by MHz10021=×π=MATCH0CL1f Solving for CMATCH gives pF5.72110=π×=fRRCINSMATCH Solving for L1 gives nH6.33720=π=fRRL1INS Because L1 and L2 are parallel, they can be combined to give the final value for LMATCH, that is, nH294=+×=L2L1L2L1LMATCH C1 and C2 can be chosen in a number of ways. First, C2 can be set to a large value, for example, 1000 pF, so that it appears as an RF short. C1 would then be set equal to the calculated value of CMATCH. Alternatively, C1 and C2 can each be set to twice CMATCH so that the total series capacitance is equal to CMATCH. By making C1 and C2 slightly unequal (that is, select C2 to be about 10% less than C1) but keeping their series value the same, the ampli-tude of the signals on INHI and INLO can be equalized so that the AD8313 is driven in a more balanced manner. Any of the options detailed above can be used provided that the combined series value of C1 and C2, that is, C1 × C2/(C1 + C2) is equal to CMATCH. In all cases, the values of CMATCH and LMATCH must be chosen from standard values. At this point, these values need now be installed on the board and measured for performance at 100 MHz. Because of board and layout parasitics, the component values from the preceding example had to be tuned to the final values of CMATCH = 8.9 pF and LMATCH = 270 nH as shown in Table 4. Assuming a lossless matching network and noting conservation of power, the impedance transformation from RS to RIN (50 Ω to 900 Ω) has an associated voltage gain given by dB6.12log20dB=×=SINRRGain Because the AD8313 input responds to voltage and not to true power, the voltage gain of the matching network increases the effective input low-end power sensitivity by this amount. Thus, in this case, the dynamic range is shifted downward, that is, the 12.6 dB voltage gain shifts the 0 dBm to −65 dBm input range downward to −12.6 dBm to −77.6 dBm. However, because of network losses, this gain is not be fully realized in practice. Refer to Figure 33 and Figure 34 for an example of practical attainable voltage gains. Table 4 shows recommended values for the inductor and cap-acitors in Figure 35 for some selected RF frequencies in addition to the associated theoretical voltage gain. These values for a reactive match are optimal for the board layout detailed as Figure 45. AD8313 Rev. D | Page 18 of 24 As previously discussed, a modification of the board layout produces networks that may not perform as specified. At 2.5 GHz, a shunt inductor is sufficient to achieve proper matching. Con-sequently, C1 and C2 are set sufficiently high that they appear as RF shorts. Table 4. Recommended Values for C1, C2, and LMATCH in Figure 35 Freq. (MHz) CMATCH (pF) C1 (pF) C2 (pF) LMATCH (nH) Voltage Gain(dB) 100 8.9 22 15 270 12.6 1000 270 900 1.5 3 3 8.2 9.0 1.5 1000 8.2 1900 1.5 3 3 2.2 6.2 1.5 1000 2.2 2500 Large 390 390 2.2 3.2 Figure 37 shows the voltage response of the 100 MHz matching network. Note the high attenuation at lower frequencies typical of a high-pass network. FREQUENCY (MHz)1550VOLTAGE GAIN ( dB)1050–510020001085-C-037 Figure 37. Voltage Response of 100 MHz Narrow-Band Matching Network ADJUSTING THE LOG SLOPE Figure 38 shows how the log slope can be adjusted to an exact value. The idea is simple: the output at the VOUT pin is attenu-ated by the variable resistor R2 working against the internal 18 kΩ of input resistance at the VSET pin. When R2 is 0, the attenu-ation it introduces is 0, and thus the slope is the basic 18 mV/dB. Note that this value varies with frequency, (Figure 10). When R2 is set to its maximum value of 10 kΩ, the attenuation from VOUT to VSET is the ratio 18/(18 + 10), and the slope is raised to (28/18) × 18 mV, or 28 mV/dB. At about the midpoint, the nominal scale is 23 mV/dB. Thus, a 70 dB input range changes the output by 70 × 23 mV, or 1.6 V. 0.1μFR110ΩR310ΩR210kΩ0.1μF+VS+VS87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD831301085-C-03818–30mV/dB Figure 38. Adjusting the Log Slope As stated, the unadjusted log slope varies with frequency from 17 mV/dB to 20 mV/dB, as shown in Figure 10. By placing a resistor between VOUT and VSET, the slope can be adjusted to a convenient 20 mV/dB as shown in Figure 39. Table 5 shows the recommended values for this resistor, REXT. Also shown are values for REXT, which increase the slope to approximately 50 mV/dB. The corresponding voltage swings for a −65 dBm to 0 dBm input range are also shown in Table 6. 0.1μFR110ΩR310ΩREXT0.1μF+VS+VS87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD831301085-C-03920mV/dB Figure 39. Adjusting the Log Slope to a Fixed Value Table 5. Values for R in Figure 39EXT Frequency MHz REXT kV Slope mV/dB VOUT Swing for Pin −65 dBm to 0 dBm – V 100 0.953 20 0.44 to 1.74 900 2.00 20 0.58 to 1.88 1900 2.55 20 0.70 to 2.00 2500 0 20 0.54 to 1.84 100 29.4 50 1.10 to 4.35 900 32.4 50.4 1.46 to 4.74 1900 33.2 49.8 1.74 to 4.98 2500 26.7 49.7 1.34 to 4.57 The value for REXT is calculated by ()Ω×−=k18SlopeOriginalSlopeOriginalSlopeNewREXT The value for the Original Slope, at a particular frequency, can be read from Figure 10. The resulting output swing is calculated by simply inserting the New Slope value and the intercept at that frequency (Figure 10 and Figure 13) into the general equation for the AD8313’s output voltage: VOUT = Slope(PIN − Intercept) AD8313 Rev. D | Page 19 of 24 INCREASING OUTPUT CURRENT To drive a more substantial load, either a pull-up resistor or an emitter-follower can be used. In Figure 40, a 1 kΩ pull-up resistor is added at the output, which provides the load current necessary to drive a 1 kΩ load to 1.7 V for VS = 2.7 V. The pull-up resistor slightly lowers the intercept and the slope. As a result, the transfer function of the AD8313 is shifted upward (intercept shifts downward). 0.1μFR110ΩR310Ω0.1μF+VS+VS87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD831301085-C-0401kΩRL= 1kΩ+VS20mV/dB Figure 40. Increasing AD8313 Output Current Capability In Figure 41, an emitter-follower provides the current gain, when a 100 Ω load can readily be driven to full-scale output. While a high ß transistor such as the BC848BLT1 (min ß = 200) is recommended, a 2 kΩ pull-up resistor between VOUT and +VS can provide additional base current to the transistor. βMIN = 2000.1μFR110ΩR310Ω0.1μF+VS+VS+VS87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD831301085-C-041RL100ΩOUTPUT13kΩ10kΩBC848BLT1 Figure 41. Output Current Drive Boost Connection In addition to providing current gain, the resistor/potentiometer combination between VSET and the emitter of the transistor increases the log slope to as much as 45 mV/dB, at maximum resistance. This gives an output voltage of 4 V for a 0 dBm input. If no increase in the log slope is required, VSET can be connected directly to the emitter of the transistor. EFFECT OF WAVEFORM TYPE ON INTERCEPT Although specified for input levels in dBm (dB relative to 1 mW), the AD8313 responds to voltage and not to power. A direct consequence of this characteristic is that input signals of equal rms power but differing crest factors produce different results at the log amp’s output. Different signal waveforms vary the effective value of the log amp’s intercept upward or downward. Graphically, this looks like a vertical shift in the log amp’s transfer function. The device’s logarithmic slope, however, is in principle not affected. For example, if the AD8313 is being fed alternately from a continuous wave and from a single CDMA channel of the same rms power, the AD8313 output voltage differs by the equivalent of 3.55 dB (64 mV) over the complete dynamic range of the device (the output for a CDMA input being lower). Table 6 shows the correction factors that should be applied to measure the rms signal strength of a various signal types. A continuous wave input is used as a reference. To measure the rms power of a square wave, for example, the mV equivalent of the dB value given in the table (18 mV/dB × 3.01 dB) should be subtracted from the output voltage of the AD8313. Table 6. Shift in AD8313 Output for Signals with Differing Crest Factors Signal Type Correction Factor (Add to Output Reading) CW Sine Wave 0 dB Square Wave or DC −3.01 dB Triangular Wave +0.9 dB GSM Channel (All Time Slots On) +0.55 dB CDMA Channel +3.55 dB PDC Channel (All Time Slots On) +0.58 dB Gaussian Noise +2.51 dB AD8313 Rev. D | Page 20 of 24 EVALUATION BOARD SCHEMATIC AND LAYOUT Figure 44 shows the schematic of the AD8313 evaluation board. Note that uninstalled components are indicated as open. This board contains the AD8313 as well as the AD8009 current-feedback operational amplifier. This is a 4-layer board (top and bottom signal layers, ground, and power). The top layer silkscreen and layout are shown in Figure 42 and Figure 43. A detailed drawing of the recommended PCB footprint for the MSOP package and the pads for the matching components are shown in Figure 45. The vacant portions of the signal and power layers are filled out with ground plane for general noise suppression. To ensure a low impedance connection between the planes, there are multiple through-hole connections to the RF ground plane. While the ground planes on the power and signal planes are used as general-purpose ground returns, any RF grounds related to the input matching network (for example, C2) are returned directly to the RF internal ground plane. GENERAL OPERATION The AD8313 should be powered by a single supply in the range of 2.7 V to 5.5 V. The power supply to each AD8313 VPOS pin is decoupled by a 10 Ω resistor and a 0.1 μF capacitor. The AD8009 can run on either single or dual supplies, +5 V to ±6 V. Both the positive and negative supply traces are decoupled using a 0.1 μF capacitor. Pads are provided for a series resistor or inductor to provide additional supply filtering. The two signal inputs are ac-coupled using 680 pF high quality RF capacitors (C1, C2). A 53.6 Ω resistor across the differential signal inputs (INHI, INLO) combines with the internal 900 Ω input impedance to give a broadband input impedance of 50.6 Ω. This termination is not optimal from a noise perspective due to the Johnson noise of the 53.6 Ω resistor. Neither does it account for the AD8313’s reactive input impedance nor for the decrease over frequency of the resistive component of the input imped-ance. However, it does allow evaluation of the AD8313 over its complete frequency range without having to design multiple matching networks. For optimum performance, a narrow-band match can be implemented by replacing the 53.6 Ω resistor (labeled L/R) with an RF inductor and replacing the 680 pF capacitors with appropriate values. The Narrow-Band LC Matching Example at 100 MHz section includes a table of recommended values for selected frequencies and explains the method of calculation. Switch 1 is used to select between power-up and power-down modes. Connecting the PWDN pin to ground enables normal operation of the AD8313. In the opposite position, the PWDN pin can be driven externally (SMA connector labeled ENBL) to either device state, or it can be allowed to float to a disabled device state. The evaluation board comes with the AD8313 configured to operate in RSSI/measurement mode. This mode is set by the 0 Ω resistor (R11), which shorts the VOUT and VSET pins to each other. When using the AD8009, the AD8313 logarithmic output appears on the SMA connector labeled VOUT. Using only the AD8313, the log output can be measured at TP1 or the SMA connector labeled VSET. USING THE AD8009 OPERATIONAL AMPLIFIER The AD8313 can supply only 400 μA at VOUT. It is also sensitive to capacitive loading, which can cause inaccurate measurements, especially in applications where the AD8313 is used to measure the envelope of RF bursts. The AD8009 alleviates both of these issues. It is an ultrahigh speed current feedback amplifier capable of delivering over 175 mA of load current, with a slew rate of 5,500 V/μs, which results in a rise time of 545 ps, making it ideal as a pulse amplifier. The AD8009 is configured as a buffer amplifier with a gain of 1. Other gain options can be implemented by installing the appro-priate resistors at R10 and R12. Various output filtering and loading options are available using R5, R6, and C6. Note that some capacitive loads may cause the AD8009 to become unstable. It is recommended that a 42.2 Ω resistor be installed at R5 when driving a capacitive load. More details can be found in the AD8009 data sheet. VARYING THE LOGARITHMIC SLOPE The slope of the AD8313 can be increased from its nominal value of 18 mV/dB to a maximum of 40 mV/dB by removing R11, the 0 Ω resistor, which shorts VSET to VOUT. VSET and VOUT are now connected through the 20 kΩ potentiometer. The AD8009 must be configured for a gain of 1 to accurately vary the slope of the AD8313. OPERATING IN CONTROLLER MODE To put the AD8313 into controller mode, R7 and R11 should be removed, breaking the link between VOUT and VSET. The VSET pin can then be driven externally via the SMA connector labeled VSET. RF BURST RESPONSE The VOUT pin of the AD8313 is very sensitive to capacitive loading, as a result care must be taken when measuring the device’s response to RF bursts. For best possible response time measurements it is recommended that the AD8009 be used to buffer the output from the AD8313. No connection should be made to TP1, the added load will effect the response time. AD8313 Rev. D | Page 21 of 24 001085-C-048 Figure 42. Layout of Signal Layer 01085-C-049 Figure 43. Signal Layer Silkscreen AD8313 Rev. D | Page 22 of 24 VPS1VPS101085-C-046R210ΩEXT ENABLESW1R110Ω1234INHIINLOVPOSPWDNCOMMVSETAD83138765INHIVOUTEXT VSETAD8009VPOSVOUTC70.1μFC1680pFC2680pFC30.1μFC50.1μFR40ΩR12301ΩR50ΩR70ΩR30ΩR110ΩR90ΩR210ΩL/R53.6ΩVNEGVPS2INLOTP1Z1Z2R10OPENR6OPENR820kΩC6OPENABC40.1μF Figure 44. Evaluation Board Schematic Table 7. Evaluation Board Configuration Options Component Function Default VPS1, VPS2, GND, VNEG Supply Pins. VPS1 is the positive supply pin for the AD8313. VPS2 and VNEG are the positive and negative supply pins for the AD8009. If the AD8009 is being operated from a single supply, VNEG should be connected to GND. VPS1 and VPS2 are independent. GND is shared by both devices. Not Applicable Z1 AD8313 Logarithmic Amplifier. If the AD8313 is used in measurement mode, it is not necessary to power up the AD8009 op amp. The log output can be measured at TP1 or at the SMA connector labeled VSET. Installed Z1 AD8009 Operational Amplifier. Installed SW1 Device Enable. When in Position A, the PWDN pin is connected to ground and the AD8313 is in normal operating mode. In Position B, the PWDN pin is connected to an SMA connector labeled ENBL. A signal can be applied to this connector. SW1 = A R7, R8 Slope Adjust. The slope of the AD8313 can be increased from its nominal value of 18 mV/dB to a maximum of 40 mV/dB by removing R11, the 0 Ω resistor, which shorts VSET to VOUT, and installing a 0 Ω resistor at R7. The 20 kΩ potentiometer at R8 can then be used to change the slope. R7 = 0 Ω (Size 0603) R8 = installed Operating in Controller Mode. To put the AD8313 into controller mode, R7 and R11 should be removed, breaking the link between VOUT and VSET. The VSET pin can then be driven externally via the SMA connector labeled VSET. L/R, C1, C2, R9 Input Interface. The 52.3 Ω resistor in position L/R, along with C1 and C2, create a wideband 50 Ω input. Alternatively, the 52.3 Ω resistor can be replaced by an inductor to form an input matching network. See Input Coupling section for more details. Remove the 0 Ω resistor at R9 for differential drive applications. L/R = 53.6 Ω (Size 0603) C1 = C2 = 680 pF (Size 0603) R9 = 0 Ω (Size 0603) R10, R12 Op Amp Gain Adjust. The AD8009 is initially configured as a buffer; gain = 1. To increase the gain of the op amp, modify the resistor values R10 and R12. R10 = open (Size 0603) R12 = 301 Ω (Size 0603) R5, R6, C6 Op Amp Output Loading/Filtering. A variety of loading and filtering options are available for the AD8009. The robust output of the op amp is capable of driving low impedances such as 50 Ω or 75 Ω, configure R5 and R6 accordingly. See the AD8009 data sheet for more details. R5 = 0 Ω (Size 0603) R6 = open (Size 0603) C6 = open (Size 0603) R1, R2, R3, R4, C3, C4, C5, C7 Supply Decoupling. R1 = R2 = 10 Ω (Size 0603) R3 = R4 = 0 Ω (Size 0603) C3 = C4 = 0.1 μF (Size 0603) C5 = C7 = 0.1 μF (Size 0603) AD8313 Rev. D | Page 23 of 24 4854.490.6282027.57550201950354122464851.791.3511016126TRACE WIDTH15.4NOT CRITICAL DIMENSIONSUNIT = MILS01085-C-047 Figure 45. Detail of PCB Footprint for Package and Pads for Matching Network AD8313 Rev. D | Page 24 of 24 OUTLINE DIMENSIONS 0.800.600.408°0°4854.90BSCPIN 10.65 BSC3.00BSCSEATINGPLANE0.150.000.380.221.10 MAX3.00BSCCOPLANARITY0.100.230.08COMPLIANT TO JEDEC STANDARDS MO-187AA Figure 46 . 8-Lead MicroSOIC Package [MSOP] (RM-08) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Temperature Range Package Descriptions Package Option Branding AD8313ARM −40°C to +85°C 8-Lead MSOP RM-08 J1A AD8313ARM-REEL −40°C to +85°C 13" Tape and Reel RM-08 J1A AD8313ARM-REEL7 −40°C to +85°C 7" Tape and Reel RM-08 J1A AD8313ARMZ1 −40°C to +85°C 8-Lead MSOP AD8313ARMZ-REEL71 −40°C to +85°C 7" Tape and Reel AD8313-EVAL Evaluation Board 1 Z = Pb-free part. TUSB3410, TUSB3410I USB to Serial Port Controller January 2010 Connectivity Interface Solutions Data Manual SLLS519H Contents May 2008 SLLS519G iii Contents Section Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Controller Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 USB Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 Enhanced UART Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 Terminal Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Detailed Controller Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 USB Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.1 External Memory Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.2 Host Download Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 USB Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 Serial Port Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 Serial Port Data Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5.1 RS-232 Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5.2 RS-485 Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5.3 IrDA Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 MCU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1.1 ROMS: ROM Shadow Configuration Register (Addr:FF90h) . . . . . . . . . . . . . . . . . . . 14 4.1.2 Boot Operation (MCU Firmware Loading) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1.3 WDCSR: Watchdog Timer, Control, and Status Register (Addr:FF93h) . . . . . . . . . 15 4.2 Buffers + I/O RAM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 Endpoint Descriptor Block (EDB−1 to EDB−3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.1 OEPCNF_n: Output Endpoint Configuration (n = 1 to 3) (Base Addr: FF08h, FF10h, FF18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.2 OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1) . . . . 19 4.3.3 OEPBCTX_n: Output Endpoint X Byte Count (n = 1 to 3) (Offset 2) . . . . . . . . . . . . 20 4.3.4 OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5) . . . . 20 4.3.5 OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3) (Offset 6) . . . . . . . . . . . . 20 4.3.6 OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7) . . . . . . . . . 21 4.3.7 IEPCNF_n: Input Endpoint Configuration (n = 1 to 3) (Base Addr: FF48h, FF50h, FF58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3.8 IEPBBAX_n: Input Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1) . . . . . . 21 4.3.9 IEPBCTX_n: Input Endpoint X-Byte Count (n = 1 to 3) (Offset 2) . . . . . . . . . . . . . . 22 4.3.10 IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5) . . . . . . 22 4.3.11 IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3) (Offset 6) . . . . . . . . . . . . . . . 22 4.3.12 IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7) . . . . . . . . . . . . 23 4.4 Endpoint-0 Descriptor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4.1 IEPCNFG_0: Input Endpoint-0 Configuration Register (Addr:FF80h) . . . . . . . . . . . 23 4.4.2 IEPBCNT_0: Input Endpoint-0 Byte Count Register (Addr:FF81h) . . . . . . . . . . . . . 24 4.4.3 OEPCNFG_0: Output Endpoint-0 Configuration Register (Addr:FF82h) . . . . . . . . . 24 4.4.4 OEPBCNT_0: Output Endpoint-0 Byte Count Register (Addr:FF83h) . . . . . . . . . . . 24 Contents iv SLLS519G May 2008 Section Page 5 USB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 FUNADR: Function Address Register (Addr:FFFFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 USBSTA: USB Status Register (Addr:FFFEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 USBMSK: USB Interrupt Mask Register (Addr:FFFDh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4 USBCTL: USB Control Register (Addr:FFFCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.5 MODECNFG: Mode Configuration Register (Addr:FFFBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.6 Vendor ID/Product ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.7 SERNUM7: Device Serial Number Register (Byte 7) (Addr:FFEFh) . . . . . . . . . . . . . . . . . . . . . . 28 5.8 SERNUM6: Device Serial Number Register (Byte 6) (Addr:FFEEh) . . . . . . . . . . . . . . . . . . . . . . 29 5.9 SERNUM5: Device Serial Number Register (Byte 5) (Addr:FFEDh) . . . . . . . . . . . . . . . . . . . . . . 29 5.10 SERNUM4: Device Serial Number Register (Byte 4) (Addr:FFECh) . . . . . . . . . . . . . . . . . . . . . . 29 5.11 SERNUM3: Device Serial Number Register (Byte 3) (Addr:FFEBh) . . . . . . . . . . . . . . . . . . . . . . 29 5.12 SERNUM2: Device Serial Number Register (Byte 2) (Addr:FFEAh) . . . . . . . . . . . . . . . . . . . . . . 30 5.13 SERNUM1: Device Serial Number Register (Byte 1) (Addr:FFE9h) . . . . . . . . . . . . . . . . . . . . . . 30 5.14 SERNUM0: Device Serial Number Register (Byte 0) (Addr:FFE8h) . . . . . . . . . . . . . . . . . . . . . . 30 5.15 Function Reset And Power-Up Reset Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.16 Pullup Resistor Connect/Disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1.1 DMACDR1: DMA Channel Definition Register (UART Transmit Channel) (Addr:FFE0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.2 DMACSR1: DMA Control And Status Register (UART Transmit Channel) (Addr:FFE1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.3 DMACDR3: DMA Channel Definition Register (UART Receive Channel) (Addr:FFE4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1.4 DMACSR3: DMA Control And Status Register (UART Receive Channel) (Addr:FFE5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 Bulk Data I/O Using the EDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2.1 IN Transaction (TUSB3410 to Host) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.2 OUT Transaction (Host to TUSB3410) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1 UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.1 RDR: Receiver Data Register (Addr:FFA0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.2 TDR: Transmitter Data Register (Addr:FFA1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.3 LCR: Line Control Register (Addr:FFA2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.1.4 FCRL: UART Flow Control Register (Addr:FFA3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1.5 Transmitter Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1.6 MCR: Modem-Control Register (Addr:FFA4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.1.7 LSR: Line-Status Register (Addr:FFA5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.1.8 MSR: Modem-Status Register (Addr:FFA6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.1.9 DLL: Divisor Register Low Byte (Addr:FFA7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.1.10 DLH: Divisor Register High Byte (Addr:FFA8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.1.11 Baud-Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.1.12 XON: Xon Register (Addr:FFA9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.1.13 XOFF: Xoff Register (Addr:FFAAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.1.14 MASK: UART Interrupt-Mask Register (Addr:FFABh) . . . . . . . . . . . . . . . . . . . . . . . . 48 Contents May 2008 SLLS519G v Section Page 7.2 UART Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2.1 Receiver Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2.2 Hardware Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.2.3 Auto RTS (Receiver Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.2.4 Auto CTS (Transmitter Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.2.5 Xon/Xoff Receiver Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.2.6 Xon/Xoff Transmit Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8 Expanded GPIO Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.1 Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.1.1 PUR_3: GPIO Pullup Register For Port 3 (Addr:FF9Eh) . . . . . . . . . . . . . . . . . . . . . . 51 9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1 8052 Interrupt and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1.1 8052 Standard Interrupt Enable (SIE) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1.2 Additional Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1.3 VECINT: Vector Interrupt Register (Addr:FF92h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1.4 Logical Interrupt Connection Diagram (Internal/External) . . . . . . . . . . . . . . . . . . . . . . 55 10 I2C Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.1 I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.1.1 I2CSTA: I2C Status and Control Register (Addr:FFF0h) . . . . . . . . . . . . . . . . . . . . . . 57 10.1.2 I2CADR: I2C Address Register (Addr:FFF3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.1.3 I2CDAI: I2C Data-Input Register (Addr:FFF2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.1.4 I2CDAO: I2C Data-Output Register (Addr:FFF1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.2 Random-Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.3 Current-Address Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.4 Sequential-Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.5 Byte-Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.6 Page-Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11 TUSB3410 Bootcode Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.2 Bootcode Programming Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.3 Default Bootcode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.3.1 Device Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.3.2 Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.3.3 Interface Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.3.4 Endpoint Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.3.5 String Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.4 External I2C Device Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.4.1 Product Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.4.2 Descriptor Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.5 Checksum in Descriptor Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.6 Header Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.6.1 TUSB3410 Bootcode Supported Descriptor Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.6.2 USB Descriptor Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.6.3 Autoexec Binary Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.7 USB Host Driver Downloading Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Contents vi SLLS519G May 2008 Section Page 11.8 Built-In Vendor Specific USB Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.8.1 Reboot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.8.2 Force Execute Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.8.3 External Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.8.4 External Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.8.5 I2C Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.8.6 I2C Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.8.7 Internal ROM Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.9 Bootcode Programming Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.9.1 USB Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.9.2 Hardware Reset Introduced by the Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.10 File Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.2 Commercial Operating Condition (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 13 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.1 Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.2 External Circuit Required for Reliable Bus Powered Suspend Operation . . . . . . . . . . . . . . . . . . 81 13.3 Wakeup Timing (WAKEUP or RI/CP Transitions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.4 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 List of Illustrations May 2008 SLLS519G vii List of Illustrations Figure Title Page 1−1 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1−2 USB-to-Serial (Single Channel) Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3−1 RS-232 and IR Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3−2 USB-to-Serial Implementation (RS-232) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3−3 RS-485 Bus Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4−1 MCU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5−1 Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5−2 Pullup Resistor Connect/Disconnect Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7−1 MSR and MCR Registers in Loop-Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7−2 Receiver/Transmitter Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7−3 Auto Flow Control Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9−1 Internal Vector Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11−1 Control Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11−2 Control Write Transfer Without Data Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 13−1 Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13−2 External Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13−3 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 List of Tables viii SLLS519G May 2008 List of Tables Table Title Page 2−1 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4−1 ROM/RAM Size Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4−2 XDATA Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4−3 Memory-Mapped Registers Summary (XDATA Range = FF80h ” FFFFh) . . . . . . . . . . . . . . . . . . . . 16 4−4 EDB Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4−5 Endpoint Registers and Offsets in RAM (n = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4−6 Endpoint Registers Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4−7 Input/Output EDB-0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6−1 DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6−2 DMA IN-Termination Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7−1 UART Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7−2 Transmitter Flow-Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7−3 Receiver Flow-Control Possibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7−4 DLL/DLH Values and Resulted Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9−1 8052 Interrupt Location Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9−2 Vector Interrupt Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11−1 Device Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11−2 Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11−3 Interface Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11−4 Output Endpoint1 Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11−5 String Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11−6 USB Descriptors Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11−7 Autoexec Binary Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11−8 Host Driver Downloading Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11−9 Bootcode Response to Control Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11−10 Bootcode Response to Control Write Without Data Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11−11 Vector Interrupt Values and Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Introduction SLLS519H—January 2010 TUSB3410, TUSB3410I 1 1 Introduction 1.1 Controller Description The TUSB3410 provides bridging between a USB port and an enhanced UART serial port. The TUSB3410 contains all the necessary logic to communicate with the host computer using the USB bus. It contains an 8052 microcontroller unit (MCU) with 16K bytes of RAM that can be loaded from the host or from the external on-board memory via an I2C bus. It also contains 10K bytes of ROM that allow the MCU to configure the USB port at boot time. The ROM code also contains an I2C boot loader. All device functions, such as the USB command decoding, UART setup, and error reporting, are managed by the internal MCU firmware under the auspices of the PC host. The TUSB3410 can be used to build an interface between a legacy serial peripheral device and a PC with USB ports, such as a legacy-free PC. Once configured, data flows from the host to the TUSB3410 via USB OUT commands and then out from the TUSB3410 on the SOUT line. Conversely, data flows into the TUSB3410 on the SIN line and then into the host via USB IN commands. Host (PC or On-The-Go Dual-Role Device) USB Out In TUSB3410 SOUT SIN Legacy Serial Peripheral Figure 1−1. Data Flow Introduction 2 TUSB3410, TUSB3410I SLLS519H—January 2010 8052 Core Clock Oscillator 12 MHz PLL and Dividers 10K × 8 ROM 8 8 2 × 16-Bit Timers 16K × 8 RAM 8 8 4 Port 3 2K × 8 SRAM 8 8 I2C Controller 8 UART−1 CPU-I/F Suspend/ Resume 8 UBM USB Buffer Manager 8 8 USB Serial Interface Engine USB TxR TDM Control Logic P3.4 P3.3 P3.1 P3.0 I2C Bus DP, DM 8 DMA-1 DMA-3 RTS CTS DTR DSR MUX IR Encoder SOUT/IR_SOUT MUX IR Decoder SIN/IR_SIN 24 MHz SIN SOUT Figure 1−2. USB-to-Serial (Single Channel) Controller Block Diagram Introduction SLLS519H—January 2010 TUSB3410, TUSB3410I 3 1.2 Ordering Information T PACKAGED DEVICES TA COMMENT 32-TERMINAL LQFP PACKAGE 32-TERMINAL QFN PACKAGE 40°C to 85°C TUSB3410 I VF TUSB3410 I RHB Industrial temperature range Shipped in trays −TUSB3410 I RHBR Industrial temperature range Tape and Reel Option 0°C to 70°C TUSB3410 VF TUSB3410 RHB Shipped in trays TUSB3410 RHBR Tape and Reel Option 1.3 Revision History Version Date Changes Mar−2002 Initial Release A Apr−2002 1. General grammatical corrections 2. Added Design−in warning on cover sheet 3. Removed references to Optional preprogrammed VID/PID Registers from Section 5.1.6 through 5.1.11. Renumber the remainder of Section 5.1 accordingly – option no longer supported. 4. Clarified GPIO pin availability B Jun−2002 1. Removed Design−in warning from cover sheet 2. Added Note 8 to Terminal Functions Table for GPIO Pins. 3. Removed Section 3.2.3 – Production Programming Mode – Mode no longer supported. 4. Added Clock Output Control description to section 5.1.5. 5. Removed Section 11.6.4 USB Descriptor with Binary Firmware 6. Added Icc Spec to Table 12.3 C Nov−2003 1. Added Industrial Temperature Option and Information 2. Added USB Logo to Cover D July 2005 1. General grammatical corrections 2. Numerous technical corrections F July 2007 1. Added ordering information for TUSB3410IRHBR and TUSB3410RHBR G May 2008 1. Added terminal assignments for RHB package H Jan 2010 1. Removed reference to 48-MHz in 13.4 Introduction 4 TUSB3410, TUSB3410I SLLS519H—January 2010 Main Features SLLS519H—January 2010 TUSB3410, TUSB3410I 5 2 Main Features 2.1 USB Features • Fully compliant with USB 2.0 full speed specifications: TID #40340262 • Supports 12-Mbps USB data rate (full speed) • Supports USB suspend, resume, and remote wakeup operations • Supports two power source modes: − Bus-powered mode − Self-powered mode • Can support a total of three input and three output (interrupt, bulk) endpoints 2.2 General Features • Integrated 8052 microcontroller with − 256 × 8 RAM for internal data − 10K × 8 ROM (with USB and I2C boot loader) − 16K × 8 RAM for code space loadable from host or I2C port − 2K × 8 shared RAM used for data buffers and endpoint descriptor blocks (EDB) − Four GPIO terminals from 8052 port 3 − Master I2C controller for EEPROM device access − MCU operates at 24 MHz providing 2 MIPS operation − 128-ms watchdog timer • Built-in two-channel DMA controller for USB/UART bulk I/O • Operates from a 12-MHz crystal • Supports USB suspend and resume • Supports remote wake-up • Available in 32-terminal LQFP • 3.3-V operation with 1.8-V core operating voltage provided by on-chip 1.8-V voltage regulator 2.3 Enhanced UART Features • Software/hardware flow control: − Programmable Xon/Xoff characters − Programmable Auto-RTS/DTR and Auto-CTS/DSR • Automatic RS-485 bus transceiver control, with and without echo • Selectable IrDA mode for up to 115.2 kbps transfer • Software selectable baud rate from 50 to 921.6 k baud • Programmable serial-interface characteristics − 5-, 6-, 7-, or 8-bit characters − Even, odd, or no parity-bit generation and detection − 1-, 1.5-, or 2-stop bit generation Main Features 6 TUSB3410, TUSB3410I SLLS519H—January 2010 • Line break generation and detection • Internal test and loop-back capabilities • Modem-control functions (CTS, RTS, DSR, DTR, RI, and DCD) • Internal diagnostics capability − Loopback control for communications link-fault isolation − Break, parity, overrun, framing-error simulation 2.4 Terminal Assignment VF PACKAGE (TOP VIEW) 23 22 21 20 19 1 2 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 RI/CP DCD DSR CTS WAKEUP SCL SDA RESET VCC X2 X1/CLKI GND P3.4 P3.3 P3.1 P3.0 24 18 3 4 5 6 7 8 17 TEST1 TEST0 CLKOUT DTR RTS SOUT/IR_SOUT GND SIN/IR_SIN VREGEN SUSPEND VCC VDD18 PUR DP DM GND RHB PACKAGE (BOTTOM VIEW) 1 2 3 4 6 7 8 24 23 22 21 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 VREGEN SUSPEND VCC VDD18 PUR DP DM GND TEST1 TEST0 CLKOUT SOUT/IR_SOUT GND SIN/IR_SIN DTR RTS RESET WAKEUP CTS DSR DCD RI SDA SCL /CP P3.0 P3.1 P3.3 P3.4 GND X1/CLKI X2 VCC 20 Main Features SLLS519H—January 2010 TUSB3410, TUSB3410I 7 Table 2−1. Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. CLKOUT 22 O Clock output (controlled by bits 2 (CLKOUTEN) and 3(CLKSLCT) in the MODECNFG register (see Section 5.5 and Note 1) CTS 13 I UART: Clear to send (see Note 4) DCD 15 I UART: Data carrier detect (see Note 4) DM 7 I/O Upstream USB port differential data minus DP 6 I/O Upstream USB port differential data plus DSR 14 I UART: Data set ready (see Note 4) DTR 21 O UART: Data terminal ready (see Note 1) GND 8, 18, 28 GND Digital ground P3.0 32 I/O General-purpose I/O 0 (port 3, terminal 0) (see Notes 3, 5, and 8) P3.1 31 I/O General-purpose I/O 1 (port 3, terminal 1) (see Notes 3, 5, and 8) P3.3 30 I/O General-purpose I/O 3 (port 3, terminal 3) (see Notes 3, 5, and 8) P3.4 29 I/O General-purpose I/O 4 (port 3, terminal 4) (see Notes 3, 5, and 8) PUR 5 O Pull-up resistor connection (see Note 2) RESET 9 I Device master reset input (see Note 4) RI/CP 16 I UART: Ring indicator (see Note 4) RTS 20 O UART: Request to send (see Note 1) SCL 11 O Master I2C controller: clock signal (see Note 1) SDA 10 I/O Master I2C controller: data signal (see Notes 1 and 5) SIN/IR_SIN 17 I UART: Serial input data / IR Serial data input (see Note 6) SOUT/IR_SOUT 19 O UART: Serial output data / IR Serial data output (see Note 7) SUSPEND 2 O Suspend indicator terminal (see Note 3). When this terminal is asserted high, the device is in suspend mode. TEST0 23 I Test input (for factory test only) (see Note 5). This terminal must be tied to VCC through a 10-kΩ resistor. TEST1 24 I Test input (for factory test only) (see Note 5). This terminal must be tied to VCC through a 10-kΩ resistor. VCC 3, 25 PWR 3.3 V VDD18 4 PWR 1.8-V supply. An internal voltage regulator generates this supply voltage when terminal VREGEN is low. When VREGEN is high, 1.8 V must be supplied externally. VREGEN 1 I This active-low terminal is used to enable the 3.3-V to 1.8-V voltage regulator. WAKEUP 12 I Remote wake-up request terminal. When low, wakes up system (see Note 5) X1/CLKI 27 I 12-MHz crystal input or clock input X2 26 O 12-MHz crystal output NOTES: 1. 3-state CMOS output (±4-mA drive/sink) 2. 3-state CMOS output (±8-mA drive/sink) 3. 3-state CMOS output (±12-mA drive/sink) 4. TTL-compatible, hysteresis input 5. TTL-compatible, hysteresis input, with internal 100-μA active pullup resistor 6. TTL-compatible input without hysteresis, with internal 100-μA active pullup resistor 7. Normal or IR mode: 3-state CMOS output (±4-mA drive/sink) 8. The MCU treats the outputs as open drain types in that the output can be driven low continuously, but a high output is driven for two clock cycles and then the output is high impedance. Main Features 8 TUSB3410, TUSB3410I SLLS519H—January 2010 Detailed Controller Description SLLS519H—January 2010 TUSB3410, TUSB3410I 9 3 Detailed Controller Description 3.1 Operating Modes The TUSB3410 controls its USB interface in response to USB commands, and this action is independent of the serial port mode selected. On the other hand, the serial port can be configured in three different modes. As with any interface device, data movement is the main function of the TUSB3410, but typically the initial configuration and error handling consume most of the support code. The following sections describe the various modes the device can be used in and the means of configuring the device. 3.2 USB Interface Configuration The TUSB3410 contains onboard ROM microcode, which enables the MCU to enumerate the device as a USB peripheral. The ROM microcode can also load application code into internal RAM from either external memory via the I2C bus or from the host via the USB. 3.2.1 External Memory Case After reset, the TUSB3410 is disconnected from the USB. Bit 7 (CONT) in the USBCTL register (see Section 5.4) is cleared. The TUSB3410 checks the I2C port for the existence of valid code; if it finds valid code, then it uploads the code from the external memory device into the RAM program space. Once loaded, the TUSB3410 connects to the USB by setting the CONT bit and enumeration and configuration are performed. This is the most likely use of the device. 3.2.2 Host Download Case If the valid code is not found at the I2C port, then the TUSB3410 connects to the USB by setting bit 7 (CONT) in the USBCTL register (see Section 5.4), and then an enumeration and default configuration are performed. The host can download additional microcode into RAM to tailor the application. Then, the MCU causes a disconnect and reconnect by clearing and setting the CONT bit, which causes the TUSB3410 to be re-enumerated with a new configuration. 3.3 USB Data Movement From the USB perspective, the TUSB3410 looks like a USB peripheral device. It uses endpoint 0 as its control endpoint, as do all USB peripherals. It also configures up to three input and three output endpoints, although most applications use one bulk input endpoint for data in, one bulk output endpoint for data out, and one interrupt endpoint for status updates. The USB configuration likely remains the same regardless of the serial port configuration. Most data is moved from the USB side to the UART side and from the UART side to the USB side using on-chip DMA transfers. Some special cases may use programmed I/O under control of the MCU. 3.4 Serial Port Setup The serial port requires a few control registers to be written to configure its operation. This configuration likely remains the same regardless of the data mode used. These registers include the line control register that controls the serial word format and the divisor registers that control the baud rate. These registers are usually controlled by the host application. 3.5 Serial Port Data Modes The serial port can be configured in three different, although similar, data modes: the RS-232 data mode, the RS-485 data mode, and the IrDA data mode. Similar to the USB mode, once configured for a specific application, it is unlikely that the mode would be changed. The different modes affect the timing of the serial input and output or the use of the control signals. However, the basic serial-to-parallel conversion of the receiver and parallel-to-serial conversion of the transmitter remain the same in all modes. Some features are available in all modes, but are only applicable in certain modes. For instance, software flow control via Xoff/Xon characters can be used in all modes, but would usually only be used in RS-232 or IrDA mode because the RS-485 mode is half-duplex communication. Similarly, hardware flow control via RTS/CTS (or DTR/DSR) handshaking is available in RS-232 or IrDA mode. However, this would probably be used only in RS-232 mode, since in IrDA mode only the SIN and SOUT paths are optically coupled. Detailed Controller Description 10 TUSB3410, TUSB3410I SLLS519H—January 2010 3.5.1 RS-232 Data Mode The default mode is called the RS-232 mode and is typically used for full duplex communication on SOUT and SIN. In this mode, the modem control outputs (RTS and DTR) communicate to a modem or are general outputs. The modem control inputs (CTS, DSR, DCD, and RI/CP) communicate to a modem or are general inputs. Alternatively, RTS and CTS (or DTR and DSR) can throttle the data flow on SOUT and SIN to prevent receive FIFO overruns. Finally, software flow control via Xoff/Xon characters can be used for the same purpose. This mode represents the most general-purpose applications, and the other modes are subsets of this mode. 3.5.2 RS-485 Data Mode The RS-485 mode is very similar to the RS-232 mode in that the SOUT and SIN formats remain the same. Since RS-485 is a bus architecture, it is inherently a single duplex communication system. The TUSB3410 in RS-485 mode controls the RTS and DTR signals such that either can enable an RS-485 driver or RS-485 receiver. When in RS-485 mode, the enable signals for transmitting are automatically asserted whenever the DMA is set up for outbound data. The receiver can be left enabled while the driver is enabled to allow an echo if desired, but when receive data is expected, the driver must be disabled. Note that this precludes use of hardware flow control, since this is a half-duplex operation, it would not be effective. Software flow control is supported, but may be of limited value. The RS-485 mode is enabled by setting bit 7 (485E) in the FCRL register (see Section 7.1.4), and bit 1 (RCVE) in the MCR register (see Section 7.1.6) allows the receiver to eavesdrop while in the RS-485 mode. 3.5.3 IrDA Data Mode The IrDA mode encodes SOUT and decodes SIN in the manner prescribed by the IrDA standard, up to 115.2 kbps. Connection to an external IrDA transceiver is required. Communications is usually full duplex. Generally, in an IrDA system, only the SOUT and SIN paths are connected so hardware flow control is usually not an option. Software flow control is supported. The IrDA mode is enabled by setting bit 6 (IREN) in the USBCTL register (see Section 5.4). The IR encoder and decoder circuitry work with the UART to change the serial bit stream into a series of pulses and back again. For every zero bit in the outbound serial stream, the encoder sends a low-to-high-to-low pulse with the duration of 3/16 of a bit frame at the middle of the bit time. For every one bit in the serial stream, the output remains low for the entire bit time. The decoding process consists of receiving the signal from the IrDA receiver and converting it into a series of zeroes and ones. As the converse to the encoder, the decoder converts a pulse to a zero bit and the lack of a pulse to a one bit. Detailed Controller Description SLLS519H—January 2010 TUSB3410, TUSB3410I 11 From UART MUX IR Encoder SOUT/IR_SOUT Terminal 1 0 IR_TX SOUT UART BaudOut Clock IREN (in USBCTL Register) MUX 1 0 SOFTSW (in MODECNFG Register) TXCNTL (in MODECNFG Register) MUX 1 0 CLKOUT CLKOUTEN Terminal (in MODECNFG Register) 3.556 MHz MUX 1 0 CLKSLCT (in MODECNFG Register) To UART Receiver IR Decoder IR_RX SIN/IR_SIN Terminal 3.3 V SOUT SIN Figure 3−1. RS-232 and IR Mode Select Detailed Controller Description 12 TUSB3410, TUSB3410I SLLS519H—January 2010 4 7 1 6 8 3 2 Transceivers DTR RTS DCD DSR CTS SOUT SIN P3.0 P3.1 P3.3 Serial Port GPIO Terminals for Other Onboard Control Function TUSB3410 12 MHz USB-0 DB9 Connector RI/CP P3.4 X1/CLKI X2 DP DM Figure 3−2. USB-to-Serial Implementation (RS-232) 12 MHz USB-0 RS-485 Transceiver RTS DTR SOUT SIN TUSB3410 RS-485 Bus 2-Bit Time 1-Bit Max Receiver is Disabled if RCVE = 0 SOUT DTR RTS X1/CLKI X2 DP DM Figure 3−3. RS-485 Bus Implementation MCU Memory Map SLLS519H—January 2010 TUSB3410, TUSB3410I 13 4 MCU Memory Map Figure 4−1 illustrates the MCU memory map under boot and normal operation. NOTE: The internal 256 bytes of RAM are not shown, since they are assumed to be in the standard 8052 location (0000h to 00FFh). The shaded areas represent the internal ROM/RAM. • When bit 0 (SDW) of the ROMS register is 0 (boot mode) The 10K ROM is mapped to address (0x0000−0x27FF) and is duplicated in location (0x8000−0xA7FF) in code space. The internal 16K RAM is mapped to address range (0x0000−0x3FFF) in data space. Buffers, MMR, and I/O are mapped to address range (0xF800−0xFFFF) in data space. • When bit 0 (SDW) is 1 (normal mode) The 10K ROM is mapped to (0x8000−0xA7FF) in code space. The internal 16K RAM is mapped to address range (0x0000−0x3FFF) in code space. Buffers, MMR, and I/O are mapped to address range (0xF800−0xFFFF) in data space. Normal Mode (SDW = 1) 0000h CODE XDATA 16K Code RAM Read Only 2K Data MMR 10K Boot ROM Boot Mode (SDW = 0) CODE XDATA 10K Boot ROM 2K Data MMR 10K Boot ROM (16K) Read/Write 27FFh 3FFFh 8000h A7FFh F800h FF7Fh FF80h FFFFh Figure 4−1. MCU Memory Map MCU Memory Map 14 TUSB3410, TUSB3410I SLLS519H—January 2010 4.1 Miscellaneous Registers 4.1.1 ROMS: ROM Shadow Configuration Register (Addr:FF90h) This register is used by the MCU to switch from boot mode to normal operation mode (boot mode is set on power-on reset only). In addition, this register provides the device revision number and the ROM/RAM configuration. 7 6 5 4 3 2 1 0 ROA S1 S0 RSVD RSVD RSVD RSVD SDW R/O R/O R/O R/O R/O R/O R/O R/W BIT NAME RESET FUNCTION 0 SDW 0 This bit enables/disables boot ROM. (Shadow the ROM). SDW = 0 When clear, the MCU executes from the 10K boot ROM space. The boot ROM appears in two locations: 0000h and 8000h. The 16K RAM is mapped to XDATA space; therefore, a read/write operation is possible. This bit is set by the MCU after the RAM load is completed. The MCU cannot clear this bit; it is cleared on power-up reset or watchdog time-out reset. SDW = 1 When set by the MCU, the 10K boot ROM maps to location 8000h, and the 16K RAM is mapped to code space, starting at location 0000h. At this point, the MCU executes from RAM, and the write operation is disabled (no write operation is possible in code space). 4−1 RSVD No effect These bits are always read as 0000b. 6−5 S[1:0] No effect Code space size. These bits define the ROM or RAM code-space size (bit 7 (ROA) defines ROM or RAM). These bits are permanently set to 10b, indicating 16K bytes of code space, and are not affected by reset (see Table 4−1). 00 = 4K bytes code space size 01 = 8K bytes code space size 10 = 16K bytes code space size 11 = 32K bytes code space size 7 ROA No effect ROM or RAM version. This bit indicates whether the code space is RAM or ROM based. This bit is permanently set to 1, indicating the code space is RAM, and is not affected by reset (see Table 4−1). ROA = 0 Code space is ROM ROA = 1 Code space is RAM Table 4−1. ROM/RAM Size Definition Table ROMS REGISTER BOOT ROM RAM CODE ROM CODE ROA S1 S0 0 0 0 None None 4K 0 0 1 None None 8K 0 1 0 None None 16K (reserved) 1 1 1 None None 32K (reserved) 1 0 0 10K 4K None 1 0 1 10K 8K None 1† 1† 0† 10K† 16K† None† 1 1 1 10K 32K (reserved) None † This is the hardwired setting. 4.1.2 Boot Operation (MCU Firmware Loading) Since the code space is in RAM (with the exception of the boot ROM), the TUSB3410 firmware must be loaded from an external source. Two sources are available for booting: one from an external serial EEPROM connected to the I2C bus and the other from the host via the USB. On device reset, bit 0 (SDW) in the ROMS register (see Section 4.1.1) and bit 7 (CONT) in the USBCTL register (see Section 5.4) are cleared. This configures the memory space to boot mode (see Table 4−3) and keeps the device disconnected from the host. The first instruction is fetched from location 0000h (which is in the 10K ROM). The 16K RAM is mapped to XDATA space (location 0000h). The MCU executes a read from an external EEPROM and tests whether it contains the code (by testing for boot signature). If it contains the code, then the MCU reads from EEPROM MCU Memory Map SLLS519H—January 2010 TUSB3410, TUSB3410I 15 and writes to the 16K RAM in XDATA space. If it does not contain the code, then the MCU proceeds to boot from the USB. Once the code is loaded, the MCU sets the SDW bit to 1 in the ROMS register. This switches the memory map to normal mode; that is, the 16K RAM is mapped to code space, and the MCU starts executing from location 0000h. Once the switch is done, the MCU sets the CONT bit to 1 in the USBCTL register. This connects the device to the USB and results in normal USB device enumeration. 4.1.3 WDCSR: Watchdog Timer, Control, and Status Register (Addr:FF93h) A watchdog timer (WDT) with 1-ms clock is provided. If this register is not accessed for a period of 128 ms, then the WDT counter resets the MCU (see Figure 5−1). The watchdog timer is enabled by default and can be disabled by writing a pattern of 101010b into the WDD[5:0] bits. The 1-ms clock for the watchdog timer is generated from the SOF pulses. Therefore, in order for the watchdog timer to count, bit 7 (CONT) in the USBCTL register (see Section 5.4) must be set. 7 6 5 4 3 2 1 0 WDD0 WDR WDD5 WDD4 WDD3 WDD2 WDD1 WDT R/W R/C R/W R/W R/W R/W R/W W/O BIT NAME RESET FUNCTION 0 WDT 0 MCU must write a 1 to this bit to prevent the watchdog timer from resetting the MCU. If the MCU does not write a 1 in a period of 128 ms, the watchdog timer resets the device. Writing a 0 has no effect on the watchdog timer. (The watchdog timer is a 7-bit counter using a 1-ms CLK.) This bit is read as 0. 5−1 WDD[5:1] 00000 These bits disable the watchdog timer. For the timer to be disabled these bits must be set to 10101b and bit 7 (WDD0) must also be set to 0. If any other pattern is present, then the watchdog timer is in operation. 6 WDR 0 Watchdog reset indication bit. This bit indicates if the reset occurred due to power-on reset or watchdog timer reset. WDR = 0 A power-up reset occurred WDR = 1 A watchdog time-out reset occurred. To clear this bit, the MCU must write a 1. Writing a 0 has no effect. 7 WDD0 1 This bit is one of the six disable bits for the watchdog timer. This bit must be cleared in order for the watchdog timer to be disabled. 4.2 Buffers + I/O RAM Map The address range from F800h to FFFFh (2K bytes) is reserved for data buffers, setup packet, endpoint descriptors block (EDB), and all I/O. There are 128 locations reserved for memory-mapped registers (MMR). Table 4−2 represents the XDATA space allocation and access restriction for the DMA, USB buffer manager (UBM), and MCU. Table 4−2. XDATA Space DESCRIPTION ADDRESS RANGE UBM ACCESS DMA ACCESS MCU ACCESS Internal MMRs (Memory-Mapped Registers) FFFFh−FF80h No (Only EDB-0) No (only data register and EDB-0) Yes EDB (Endpoint Descriptors Block) FF7Fh−FF08h Only for EDB update Only for EDB update Yes Setup Packet FF07h−FF00h Yes No Yes Input Endpoint-0 Buffer FEFFh−FEF8h Yes Yes Yes Output Endpoint-0 Buffer FEF7h−FEF0h Yes Yes Yes Data Buffers FEEFh−F800h Yes Yes Yes MCU Memory Map 16 TUSB3410, TUSB3410I SLLS519H—January 2010 Table 4−3. Memory-Mapped Registers Summary (XDATA Range = FF80h → FFFFh) ADDRESS REGISTER DESCRIPTION FFFFh FUNADR Function address register FFFEh USBSTA USB status register FFFDh USBMSK USB interrupt mask register FFFCh USBCTL USB control register FFFBh MODECNFG Mode configuration register FFFAh−FFF4h Reserved FFF3h I2CADR I2C-port address register FFF2h I2CDATI I2C-port data input register FFF1h I2CDATO I2C-port data output register FFF0h I2CSTA I2C-port status register FFEFh SERNUM7 Serial number byte 7 register FFEEh SERNUM6 Serial number byte 6 register FFEDh SERNUM5 Serial number byte 5 register FFECh SERNUM4 Serial number byte 4 register FFEBh SERNUM3 Serial number byte 3 register FFEAh SERNUM2 Serial number byte 2 register FFE9h SERNUM1 Serial number byte 1 register FFE8h SERNUM0 Serial number byte 0 register FFE7h−FFE6h Reserved FFE5h DMACSR3 DMA-3: Control and status register FFE4h DMACDR3 DMA-3: Channel definition register FFE3h−FFE2h Reserved FFE1h DMACSR1 DMA-1: Control and status register FFE0h DMACDR1 DMA-1: Channel definition register FFDFh−FFACh Reserved FFABh MASK UART: Interrupt mask register FFAAh XOFF UART: Xoff register FFA9h XON UART: Xon register FFA8h DLH UART: Divisor high-byte register FFA7h DLL UART: Divisor low-byte register FFA6h MSR UART: Modem status register FFA5h LSR UART: Line status register FFA4h MCR UART: Modem control register FFA3h FCRL UART: Flow control register FFA2h LCR UART: Line control registers FFA1h TDR UART: Transmitter data registers FFA0h RDR UART: Receiver data registers FF9Eh PUR_3 GPIO: Pullup register for port 3 MCU Memory Map SLLS519H—January 2010 TUSB3410, TUSB3410I 17 Table 4−3. Memory-Mapped Registers Summary (XDATA Range = FF80h → FFFFh) (Continued) ADDRESS REGISTER DESCRIPTION FF9Dh−FF94h FF93h Reserved WDCSR Watchdog timer control and status register FF92h VECINT Vector interrupt register FF91h Reserved FF90h ROMS ROM shadow configuration register FF8Fh−FF84h Reserved FF83h OEPBCNT_0 Output endpoint_0: Byte count register FF82h OEPCNFG_0 Output endpoint_0: Configuration register FF81h IEPBCNT_0 Input endpoint_0: Byte count register FF80h IEPCNFG_0 Input endpoint_0: Configuration register Table 4−4. EDB Memory Locations ADDRESS REGISTER DESCRIPTION FF7Fh−FF60h Reserved FF5Fh IEPSIZXY_3 Input endpoint_3: X-Y buffer size FF5Eh IEPBCTY_3 Input endpoint_3: Y-byte count FF5Dh IEPBBAY_3 Input endpoint_3: Y-buffer base address FF5Ch − Reserved FF5Bh − Reserved FF5Ah IEPBCTX_3 Input endpoint_3: X-byte count FF59h IEPBBAX Input endpoint_3: X-buffer base address FF58h IEPCNF_3 Input endpoint_3: Configuration FF57h IEPSIZXY_2 Input endpoint_2: X-Y buffer size FF56h IEPBCTY_2 Input endpoint_2: Y-byte count FF55h IEPBBAY_2 Input endpoint_2: Y-buffer base address FF54h − Reserved FF53h − Reserved FF52h IEPBCTX_2 Input endpoint_2: X-byte count FF51h IEPBBAX_2 Input endpoint_2: X-buffer base address FF50h IEPCNF_2 Input endpoint_2: Configuration FF4Fh IEPSIZXY_1 Input endpoint_1: X-Y buffer size FF4Eh IEPBCTY_1 Input endpoint_1: Y-byte count FF4Dh IEPBBAY_1 Input endpoint_1: Y-buffer base address FF4Ch − Reserved FF4Bh − Reserved FF4Ah IEPBCTX_1 Input endpoint_1: X-byte count FF49h IEPBBAX_1 Input endpoint_1: X-buffer base address FF48h IEPCNF_1 Input endpoint_1: Configuration FF47h ↑ Reserved FF20h FF1Fh OEPSIZXY_3 Output endpoint_3: X-Y buffer size FF1Eh OEPBCTY_3 Output endpoint_3: Y-byte count FF1Dh OEPBBAY_3 Output endpoint_3: Y-buffer base address FF1Bh−FF1Ch − Reserved MCU Memory Map 18 TUSB3410, TUSB3410I SLLS519H—January 2010 Table 4−4. EDB Memory Locations (Continued) ADDRESS REGISTER DESCRIPTION FF1Ah OEPBCTX_3 Output endpoint_3: X-byte count FF19h OEPBBAX_3 Output endpoint_3: X-buffer base address FF18h OEPCNF_3 Output endpoint_3: Configuration FF17h OEPSIZXY_2 Output endpoint_2: X-Y buffer size FF16h OEPBCTY_2 Output endpoint_2: Y-byte count FF15h OEPBBAY_2 Output endpoint_2: Y-buffer base address FF14h−FF13h − Reserved FF12h OEPBCTX_2 Output endpoint_2: X-byte count FF11h OEPBBAX_2 Output endpoint_2: X-buffer base address FF10h OEPCNF_2 Output endpoint_2: Configuration FF0Fh OEPSIZXY_1 Output endpoint_1: X-Y buffer size FF0Eh OEPBCTY_1 Output endpoint_1: Y-byte count FF0Dh OEPBBAY_1 Output endpoint_1: Y-buffer base address FF0Ch−FF0Bh − Reserved FF0Ah OEPBCTX_1 Output endpoint_1: X-byte count FF09h OEPBBAX_1 Output endpoint_1: X-buffer base address FF08h OEPCNF_1 Output endpoint_1: Configuration FF07h ↑ (8 bytes) Setup packet block FF00h FEFFh ↑ (8 bytes) Input endpoint_0 buffer FEF8h FEF7h ↑ (8 bytes) Output endpoint_0 buffer FEF0h FEEFh TOPBUFF Top of buffer space ↑ Buffer space F800h STABUFF Start of buffer space 4.3 Endpoint Descriptor Block (EDB−1 to EDB−3) Data transfers between the USB, the MCU, and external devices that are defined by an endpoint descriptor block (EDB). Three input and three output EDBs are provided. With the exception of EDB-0 (I/O endpoint-0), all EDBs are located in SRAM as per Table 4−3. Each EDB contains information describing the X- and Y-buffers. In addition, each EDB provides general status information. Table 4−5 describes the EDB entries for EDB−1 to EDB−3. EDB−0 registers are described in Table 4−6. MCU Memory Map SLLS519H—January 2010 TUSB3410, TUSB3410I 19 Table 4−5. Endpoint Registers and Offsets in RAM (n = 1 to 3) OFFSET ENTRY NAME DESCRIPTION 07 EPSIZXY_n I/O endpoint_n: X/Y-buffer size 06 EPBCTY_n I/O endpoint_n: Y-byte count 05 EPBBAY_n I/O endpoint_n: Y-buffer base address 04 SPARE Not used 03 SPARE Not used 02 EPBCTX_n I/O endpoint_n: X-byte count 01 EPBBAX_n I/O endpoint_n: X-buffer base address 00 EPCNF_n I/O endpoint_n: Configuration Table 4−6. Endpoint Registers Base Addresses BASE ADDRESS DESCRIPTION FF08h Output endpoint 1 FF10h Output endpoint 2 FF18h Output endpoint 3 FF48h Input endpoint 1 FF50h Input endpoint 2 FF58h Input endpoint 3 4.3.1 OEPCNF_n: Output Endpoint Configuration (n = 1 to 3) (Base Addr: FF08h, FF10h, FF18h) 7 6 5 4 3 2 1 0 UBME ISO=0 TOGLE DBUF STALL USBIE RSV RSV R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 1−0 RSV x Reserved = 0 2 USBIE x USB interrupt enable on transaction completion. Set/cleared by the MCU. USBIE = 0 No interrupt on transaction completion USBIE = 1 Interrupt on transaction completion 3 STALL 0 USB stall condition indication. Set/cleared by the MCU. STALL = 0 STALL = 1 No stall USB stall condition. If set by the MCU, then a STALL handshake is initiated and the bit is cleared by the MCU. 4 DBUF x Double-buffer enable. Set/cleared by the MCU. DBUF = 0 Primary buffer only (X-buffer only) DBUF = 1 Toggle bit selects buffer 5 TOGLE x USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1. 6 ISO x ISO = 0 Nonisochronous transfer. This bit must be cleared by the MCU since only nonisochronous transfer is supported. 7 UBME x USB buffer manager (UBM) enable/disable bit. Set/cleared by the MCU. UBME = 0 UBM cannot use this endpoint UBME = 1 UBM can use this endpoint 4.3.2 OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1) 7 6 5 4 3 2 1 0 A10 A9 A8 A7 A6 A5 A4 A3 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 7−0 A[10:3] x A[10:3] of X-buffer base address (padded with 3 LSBs of zeros for a total of 11 bits). This value is set by the MCU. The UBM or DMA uses this value as the start-address of a given transaction. Note that the UBM or DMA does not change this value at the end of a transaction. MCU Memory Map 20 TUSB3410, TUSB3410I SLLS519H—January 2010 4.3.3 OEPBCTX_n: Output Endpoint X Byte Count (n = 1 to 3) (Offset 2) 7 6 5 4 3 2 1 0 NAK C6 C5 C4 C3 C2 C1 C0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 6−0 C[6:0] x X-buffer byte count: X000.0000b Count = 0 X000.0001b Count = 1 byte : : X011.1111b Count = 63 bytes X100.0000b Count = 64 bytes Any value ≥ 100.0001b may result in unpredictable results. 7 NAK x NAK = 0 NAK = 1 No valid data in buffer. Ready for host OUT Buffer contains a valid packet from host (gives NAK response to Host OUT request) 4.3.4 OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5) 7 6 5 4 3 2 1 0 A10 A9 A8 A7 A6 A5 A4 A3 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 7−0 A[10:3] x A[10:3] of Y-buffer base address (padded with 3 LSBs of zeros for a total of 11 bits). This value is set by the MCU. The UBM or DMA uses this value as the start-address of a given transaction. Furthermore, UBM or DMA does not change this value at the end of a transaction. 4.3.5 OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3) (Offset 6) 7 6 5 4 3 2 1 0 NAK C6 C5 C4 C3 C2 C1 C0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 6−0 C[6:0] x Y-byte count: X000.0000b Count = 0 X000.0001b Count = 1 byte : : X011.1111b Count = 63 bytes X100.0000b Count = 64 bytes Any value ≥ 100.0001b may result in unpredictable results. 7 NAK x NAK = 0 NAK = 1 No valid data in buffer. Ready for host OUT Buffer contains a valid packet from host (gives NAK response to Host OUT request) MCU Memory Map SLLS519H—January 2010 TUSB3410, TUSB3410I 21 4.3.6 OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7) 7 6 5 4 3 2 1 0 RSV S6 S5 S4 S3 S2 S1 S0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 6−0 S[6:0] x X- and Y-buffer size: 0000.0000b Size = 0 0000.0001b Size = 1 byte : : 0011.1111b Size = 63 bytes 0100.0000b Size = 64 bytes Any value ≥ 100.0001b may result in unpredictable results. 7 RSV x Reserved = 0 4.3.7 IEPCNF_n: Input Endpoint Configuration (n = 1 to 3) (Base Addr: FF48h, FF50h, FF58h) 7 6 5 4 3 2 1 0 UBME ISO=0 TOGLE DBUF STALL USBIE RSV RSV R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 1−0 RSV x Reserved = 0 2 USBIE x USB interrupt enable on transaction completion USBIE = 0 No interrupt on transaction completion USBIE = 1 Interrupt on transaction completion 3 STALL 0 USB stall condition indication. Set by the UBM but can be set/cleared by the MCU STALL = 0 No stall STALL = 1 USB stall condition. If set by the MCU, then a STALL handshake is initiated and the bit is cleared automatically. 4 DBUF x Double buffer enable DBUF = 0 Primary buffer only (X-buffer only) DBUF = 1 Toggle bit selects buffer 5 TOGLE x USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1 6 ISO x ISO = 0 Nonisochronous transfer. This bit must be cleared by the MCU since only nonisochronous transfer is supported 7 UBME x UBM enable/disable bit. Set/cleared by the MCU UBME = 0 UBM cannot use this endpoint UBME = 1 UBM can use this endpoint 4.3.8 IEPBBAX_n: Input Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1) 7 6 5 4 3 2 1 0 A10 A9 A8 A7 A6 A5 A4 A3 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 7−0 A[10:3] x A[10:3] of X-buffer base address (padded with 3 LSBs of zeros for a total of 11 bits). This value is set by the MCU. The UBM or DMA uses this value as the start-address of a given transaction, but note that the UBM or DMA does not change this value at the end of a transaction. MCU Memory Map 22 TUSB3410, TUSB3410I SLLS519H—January 2010 4.3.9 IEPBCTX_n: Input Endpoint X-Byte Count (n = 1 to 3) (Offset 2) 7 6 5 4 3 2 1 0 NAK C6 C5 C4 C3 C2 C1 C0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 6−0 C[6:0] x X-Buffer byte count: X000.0000b Count = 0 X000.0001b Count = 1 byte : : X011.1111b Count = 63 bytes X100.0000b Count = 64 bytes Any value ≥ 100.0001b may result in unpredictable results. 7 NAK x NAK = 0 NAK = 1 Buffer contains a valid packet for host-IN transaction Buffer is empty (gives NAK response to host-IN request) 4.3.10 IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5) 7 6 5 4 3 2 1 0 A10 A9 A8 A7 A6 A5 A4 A3 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 7−0 A[10:3] x A[10:3] of Y-buffer base address (padded with 3 LSBs of zeros for a total of 11 bits). This value is set by the MCU. The UBM or DMA uses this value as the start-address of a given transaction, but note that the UBM or DMA does not change this value at the end of a transaction. 4.3.11 IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3) (Offset 6) 7 6 5 4 3 2 1 0 NAK C6 C5 C4 C3 C2 C1 C0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 6−0 C[6:0] x Y-Byte count: X000.0000b Count = 0 X000.0001b Count = 1 byte : : X011.1111b Count = 63 bytes X100.0000b Count = 64 bytes Any value ≥ 100.0001b may result in unpredictable results. 7 NAK x NAK = 0 NAK = 1 Buffer contains a valid packet for host-IN transaction Buffer is empty (gives NAK response to host-IN request) MCU Memory Map SLLS519H—January 2010 TUSB3410, TUSB3410I 23 4.3.12 IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7) 7 6 5 4 3 2 1 0 RSV S6 S5 S4 S3 S2 S1 S0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 6−0 S[6:0] x X- and Y-buffer size: 0000.0000b Size = 0 0000.0001b Size = 1 byte : : 0011.1111b Size = 63 bytes 0100.0000b Size = 64 bytes Any value ≥ 100.0001b may result in unpredictable results. 7 RSV x Reserved = 0 4.4 Endpoint-0 Descriptor Registers Unlike registers EDB-1 to EDB-3, which are defined as memory entries in SRAM, endpoint-0 is described by a set of four registers (two for output and two for input). The registers and their respective addresses, used for EDB-0 description, are defined in Table 4−7. EDB-0 has no buffer base-address register, since these addresses are hardwired to FEF8h and FEF0h. Note that the bit positions have been preserved to provide consistency with EDB-n (n = 1 to 3). Table 4−7. Input/Output EDB-0 Registers ADDRESS REGISTER NAME DESCRIPTION BUFFER BASE ADDRESS FF83h FF82h OEPBCNT_0 OEPCNFG_0 Output endpoint_0: Byte count register Output endpoint_0: Configuration register FEF0h FF81h FF80h IEPBCNT_0 IEPCNFG_0 Input endpoint_0: Byte count register Input endpoint_0: Configuration register FEF8h 4.4.1 IEPCNFG_0: Input Endpoint-0 Configuration Register (Addr:FF80h) 7 6 5 4 3 2 1 0 UBME RSV TOGLE RSV STALL USBIE RSV RSV R/W R/O R/O R/O R/W R/W R/O R/O BIT NAME RESET FUNCTION 1−0 RSV 0 Reserved = 0 2 USBIE 0 USB interrupt enable on transaction completion. Set/cleared by the MCU. USBIE = 0 No interrupt USBIE = 1 Interrupt on transaction completion 3 STALL 0 USB stall condition indication. Set/cleared by the MCU STALL = 0 No stall STALL = 1 USB stall condition. If set by the MCU, then a STALL handshake is initiated and the bit is cleared automatically by the next setup transaction. 4 RSV 0 Reserved = 0 5 TOGLE 0 USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1. 6 RSV 0 Reserved = 0 7 UBME 0 UBM enable/disable bit. Set/cleared by the MCU UBME = 0 UBM cannot use this endpoint UBME = 1 UBM can use this endpoint MCU Memory Map 24 TUSB3410, TUSB3410I SLLS519H—January 2010 4.4.2 IEPBCNT_0: Input Endpoint-0 Byte Count Register (Addr:FF81h) 7 6 5 4 3 2 1 0 NAK RSV RSV RSV C3 C2 C1 C0 R/W R/O R/O R/O R/W R/W R/W R/W BIT NAME RESET FUNCTION 3−0 C[3:0] 0h Byte count: 0000b Count = 0 : : 0111b Count = 7 1000b Count = 8 1001b to 1111b are reserved. (If used, they default to 8) 6−4 RSV 0 Reserved = 0 7 NAK 1 NAK = 0 NAK = 1 Buffer contains a valid packet for host-IN transaction Buffer is empty (gives NAK response to host-IN request) 4.4.3 OEPCNFG_0: Output Endpoint-0 Configuration Register (Addr:FF82h) 7 6 5 4 3 2 1 0 UBME RSV TOGLE RSV STALL USBIE RSV RSV R/W R/O R/O R/O R/W R/W R/O R/O BIT NAME RESET FUNCTION 1−0 RSV 0 Reserved = 0 2 USBIE 0 USB interrupt enable on transaction completion. Set/cleared by the MCU. USBIE = 0 No interrupt on transaction completion USBIE = 1 Interrupt on transaction completion 3 STALL 0 USB stall condition indication. Set/cleared by the MCU STALL = 0 No stall STALL = 1 USB stall condition. If set by the MCU, a STALL handshake is initiated and the bit is cleared automatically. 4 RSV 0 Reserved = 0 5 TOGLE 0 USB \toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1. 6 RSV 0 Reserved = 0 7 UBME 0 UBM enable/disable bit. Set/cleared by the MCU UBME = 0 UBM cannot use this endpoint UBME = 1 UBM can use this endpoint 4.4.4 OEPBCNT_0: Output Endpoint-0 Byte Count Register (Addr:FF83h) 7 6 5 4 3 2 1 0 NAK RSV RSV RSV C3 C2 C1 C0 R/W R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET FUNCTION 3−0 C[3:0] 0h Byte count: 0000b Count = 0 : : 0111b Count = 7 1000b Count = 8 1001b to 1111b are reserved 6−4 RSV 0 Reserved = 0 7 NAK 1 NAK =0 NAK = 1 No valid data in buffer. Ready for host OUT Buffer contains a valid packet from host (gives NAK response to host-OUT request). USB Registers SLLS519H—January 2010 TUSB3410, TUSB3410I 25 5 USB Registers 5.1 FUNADR: Function Address Register (Addr:FFFFh) This register contains the device function address. 7 6 5 4 3 2 1 0 RSV FA6 FA5 FA4 FA3 FA2 FA1 FA0 R/O R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 6−0 FA[6:0] 0 These bits define the current device address assigned to the function. The MCU writes a value to this register because of the SET-ADDRESS host command. 7 RSV 0 Reserved = 0 5.2 USBSTA: USB Status Register (Addr:FFFEh) All bits in this register are set by the hardware and are cleared by the MCU when writing a 1 to the proper bit location (writing a 0 has no effect). In addition, each bit can generate an interrupt if its corresponding mask bit is set (R/C notation indicates read and clear only by the MCU). 7 6 5 4 3 2 1 0 RSTR SUSR RESR RSV URRI SETUP WAKEUP STPOW R/C R/C R/C R/O R/C R/C R/C R/C BIT NAME RESET FUNCTION 0 STPOW 0 SETUP overwrite bit. Set by hardware when a setup packet is received while there is already a packet in the setup buffer. STPOW = 0 STPOW = 1 MCU can clear this bit by writing a 1 (writing 0 has no effect). SETUP overwrite 1 WAKEUP 0 Remote wakeup bit WAKEUP = 0 WAKEUP = 1 The MCU can clear this bit by writing a 1 (writing 0 has no effect). Remote wakeup request from WAKEUP terminal 2 SETUP 0 SETUP transaction received bit. As long as SETUP is 1, IN and OUT on endpoint-0 are NAKed, regardless of their real NAK bits value. SETUP = 0 SETUP = 1 MCU can clear this bit by writing a 1 (writing 0 has no effect). SETUP transaction received 3 URRI 0 UART RI (ring indicate) status bit – a rising edge causes this bit to be set. URRI = 0 URRI = 1 The MCU can clear this bit by writing a 1 (writing 0 has no effect). Ring detected, which is used to wake the chip up (bring it out of suspend). 4 RSV 0 Reserved 5 RESR 0 Function resume request bit RESR = 0 RESR = 1 The MCU can clear this bit by writing a 1 (writing 0 has no effect). Function resume is detected 6 SUSR 0 Function suspended request bit. This bit is set in response to a global or selective suspend condition. SUSR = 0 SUSR = 1 The MCU can clear this bit by writing a 1 (writing 0 has no effect). Function suspend is detected 7 RSTR 0 Function reset request bit. This bit is set in response to the USB host initiating a port reset. This bit is not affected by the USB function reset. RSTR = 0 RSTR = 1 The MCU can clear this bit by writing a 1 (writing 0 has no effect). Function reset is detected USB Registers 26 TUSB3410, TUSB3410I SLLS519H—January 2010 5.3 USBMSK: USB Interrupt Mask Register (Addr:FFFDh) 7 6 5 4 3 2 1 0 RSTR SUSR RESR RSV URRI SETUP WAKEUP STPOW R/W R/W R/W R/O R/W R/W R/W R/W BIT NAME RESET FUNCTION 0 STPOW 0 SETUP overwrite interrupt-enable bit STPOW = 0 STPOW = 1 STPOW interrupt disabled STPOW interrupt enabled 1 WAKEUP 0 Remote wakeup interrupt enable bit WAKEUP = 0 WAKEUP = 1 WAKEUP interrupt disable WAKEUP interrupt enable 2 SETUP 0 SETUP interrupt enable bit SETUP = 0 SETUP = 1 SETUP interrupt disabled SETUP interrupt enabled 3 URRI 0 UART RI interrupt enable bit URRI = 0 URRI = 1 UART RI interrupt disable UART RI interrupt enable 4 RSV 0 Reserved 5 RESR 0 Function resume interrupt enable bit RESR = 0 RESR = 1 Function resume interrupt disabled Function resume interrupt enabled 6 SUSR 0 Function suspend interrupt enable SUSR = 0 SUSR = 1 Function suspend interrupt disabled Function suspend interrupt enabled 7 RSTR 0 Function reset interrupt bit. This bit is not affected by USB function reset. RSTR = 0 RSTR = 1 Function reset interrupt disabled Function reset interrupt enabled USB Registers SLLS519H—January 2010 TUSB3410, TUSB3410I 27 5.4 USBCTL: USB Control Register (Addr:FFFCh) Unlike the rest of the registers, this register is cleared by the power-up reset signal only. The USB reset cannot reset this register (see Figure 5−1). 7 6 5 4 3 2 1 0 CONT IREN RWUP FRSTE RSV RSV SIR DIR R/W R/W R/C R/W R/W R/W R/W R/W BIT NAME RESET 0 DIR 0 As a response to a setup packet, the MCU decodes the request and sets/clears this bit to reflect the data transfer direction. DIR = 0 DIR = 1 USB data-OUT transaction (from host to TUSB3410) USB data-IN transaction (from TUSB3410 to host) 1 SIR 0 SETUP interrupt-status bit. This bit is controlled by the MCU to indicate to the hardware when the SETUP interrupt is being serviced. SIR = 0 SIR = 1 SETUP interrupt is not served. The MCU clears this bit before exiting the SETUP interrupt routine. SETUP interrupt is in progress. The MCU sets this bit when servicing the SETUP interrupt. 2 RSV 0 Reserved = 0 3 RSV 0 This bit must always be written as 0. 4 FRSTE 1 Function reset-connection bit. This bit connects/disconnects the USB function reset to/from the MCU reset. FRSTE = 0 FRSTE = 1 Function reset is not connected to MCU reset Function reset is connected to MCU reset 5 RWUP 0 Device remote wakeup request. This bit is set by the MCU and is cleared automatically. RWUP = 0 RWUP = 1 Writing a 0 to this bit has no effect When MCU writes a 1, a remote-wakeup pulse is generated. 6 IREN 0 IR mode enable. This bit is set and cleared by firmware. IREN = 0 IREN = 1 IR encoder/decoder is disabled, UART mode is selected IR encoder/decoder is enabled, UART mode is deselected 7 CONT 0 Connect/disconnect bit CONT = 0 CONT = 1 Upstream port is disconnected. Pullup disabled. Upstream port is connected. Pullup enabled. 5.5 MODECNFG: Mode Configuration Register (Addr:FFFBh) This register is cleared by the power-up reset signal only. The USB reset cannot reset this register. 7 6 5 4 3 2 1 0 RSV RSV RSV RSV CLKSLCT CLKOUTEN SOFTSW TXCNTL R/O R/O R/O R/O R/W R/W R/W R/W BIT NAME RESET FUNCTION 0 TXCNTL 0 Transmit output control: Hardware or firmware switching select for 3-state serial output buffer. TXCNTL = 0 TXCNTL = 1 Hardware automatic switching is selected Firmware toggle switching is selected 1 SOFTSW 0 Soft switch: Firmware controllable 3-state output buffer enable for serial output terminal. SOFTSW = 0 SOFTSW = 1 Serial output buffer is enabled Serial output buffer is disabled 2 CLKOUTEN 0 Clock output enable: Enables/disables the clock output at CLKOUT terminal. CLKOUTEN = 0 CLKOUTEN = 1 Clock output is disabled. Device drives low at CLKOUT terminal. Clock output is enabled 3 CLKSLCT 0 Clock output source select: Selects between 3.556-MHz fixed clock or UART baud out clock as output clock source. CLKSLCT = 0 CLKSLCT = 1 UART baud out clock is selected as clock output Fixed 3.556-MHz free running clock is selected as clock output 4−7 RSV 0 Reserved USB Registers 28 TUSB3410, TUSB3410I SLLS519H—January 2010 Clock Output Control Bit 2 (CLKOUTEN) in the MODECNFG register enables or disables the clock output at the CLKOUT terminal of the TUSB3410. The power up default of CLKOUT is disabled. Firmware can write a 1 to enable the clock output if needed. Bit 3 (CLKSLCT) in the MODECNFG register selects the output clock source from either a fixed 3.556-MHz free-running clock or the UART BaudOut clock. 5.6 Vendor ID/Product ID USB−IF and Microsoft WHQL certification requires that end equipment makers use their own unique vendor ID and product ID for each product (model). OEMs cannot use silicon vendor’s (for instance, TI’s default) VID/PID in their end products. A unique VID/PID combination will avoid potential driver conflicts and enable logo certification. See www.usb.org for more information. 5.7 SERNUM7: Device Serial Number Register (Byte 7) (Addr:FFEFh) Each TUSB3410 device has a unique 64-bit serial die id number, which is generated during manufacturing. The die id is incremented sequentially, however there is no assurance that numbers will not be skipped. The device serial number registers mirror this unique 64-bit serial die id value. After power-up reset, this read-only register (SERNUM7) contains the most significant byte (byte 7) of the complete 64-bit device serial number. This register cannot be reset. 7 6 5 4 3 2 1 0 D63 D62 D61 D60 D59 D58 D57 D56 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET FUNCTION 7−0 D[63:56] Device serial number byte 7 value Device serial number byte 7 value Procedure to load device serial number value in shared RAM: • After power-up reset, the boot code copies the predefined USB descriptors to shared RAM. As a result, the default serial number hard-coded in the boot code (0x00 hex) is copied to the shared RAM data space. • The boot code checks to see if an EEPROM is present on the I2C port. If an EEPROM is present and contains a valid device serial number as part of the USB device descriptor information stored in EEPROM, then the boot code overwrites the serial number value stored in shared RAM with the one found in EEPROM. Otherwise, the device serial number value stored in shared RAM remains unchanged. If firmware is stored in the EEPROM, then it is executed. This firmware can read the SERNUM7 through SERNUM0 registers and overwrite the serial number stored in RAM or store a custom number in RAM. • In summary, the serial number value in external EEPROM has the highest priority to be loaded into shared RAM data space. The serial number value stored in shared RAM is used as part of the valid device descriptor information during normal operation. USB Registers SLLS519H—January 2010 TUSB3410, TUSB3410I 29 5.8 SERNUM6: Device Serial Number Register (Byte 6) (Addr:FFEEh) The device serial number registers mirror the unique 64-bit die id value. After power-up reset, this read-only register (SERNUM6) contains byte 6 of the complete 64-bit device serial number. This register cannot be reset. 7 6 5 4 3 2 1 0 D55 D54 D53 D52 D51 D50 D49 D48 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET FUNCTION 7−0 D[55:48] Device serial number byte 6 value Device serial number byte 6 value NOTE: See the procedure described in the SERNUM7 register (see Section 5.7) to load the device serial number into shared RAM. 5.9 SERNUM5: Device Serial Number Register (Byte 5) (Addr:FFEDh) The device serial number registers mirror the unique 64-bit die id value. After power-up reset, this read-only register (SERNUM5) contains byte 5 of the complete 64-bit device serial number. This register cannot be reset. 7 6 5 4 3 2 1 0 D47 D46 D45 D44 D43 D42 D41 D40 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET FUNCTION 7−0 D[47:40] Device serial number byte 5 value Device serial number byte 5 value NOTE: See the procedure described in the SERNUM7 register (see Section 5.7) to load the device serial number into shared RAM. 5.10 SERNUM4: Device Serial Number Register (Byte 4) (Addr:FFECh) The device serial number registers mirror the unique 64-bit die id value. After power-up reset, this read-only register (SERNUM4) contains byte 4 of the complete 64-bit device serial number. This register cannot be reset. 7 6 5 4 3 2 1 0 D39 D38 D37 D36 D35 D34 D33 D32 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET FUNCTION 7−0 D[39:32] Device serial number byte 4 value Device serial number byte 4 value NOTE: See the procedure described in the SERNUM7 register (see Section 5.7) to load the device serial number into shared RAM. 5.11 SERNUM3: Device Serial Number Register (Byte 3) (Addr:FFEBh) The device serial number registers mirror the unique 64-bit die id value. After power-up reset, this read-only register (SERNUM3) contains byte 3 of the complete 64-bit device serial number. This register cannot be reset. 7 6 5 4 3 2 1 0 D31 D30 D29 D28 D27 D26 D25 D24 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET FUNCTION 7−0 D[31:24] Device serial number byte 3 value Device serial number byte 3 value NOTE: See the procedure described in the SERNUM7 register (see Section 5.7) to load the device serial number into shared RAM. USB Registers 30 TUSB3410, TUSB3410I SLLS519H—January 2010 5.12 SERNUM2: Device Serial Number Register (Byte 2) (Addr:FFEAh) The device serial number registers mirror the unique 64-bit die id value. After power-up reset, this read-only register (SERNUM2) contains byte 2 of the complete 64-bit device serial number. This register cannot be reset. 7 6 5 4 3 2 1 0 D23 D22 D21 D20 D19 D18 D17 D16 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET FUNCTION 7−0 D[23:16] 0 Device serial number byte 2 value NOTE: See the procedure described in the SERNUM7 register (see Section 5.7) to load the device serial number into shared RAM. 5.13 SERNUM1: Device Serial Number Register (Byte 1) (Addr:FFE9h) The device serial number registers mirror the unique 64-bit die id value. After power-up reset, this read-only register (SERNUM1) contains byte 1 of the complete 64-bit device serial number. This register cannot be reset. 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET FUNCTION 7−0 D[15:8] Device serial number byte 1 value Device serial number byte 1 value NOTE: See the procedure described in the SERNUM7 register (see Section 5.7) to load the device serial number into shared RAM. 5.14 SERNUM0: Device Serial Number Register (Byte 0) (Addr:FFE8h) The device serial number registers mirror the unique 64-bit die id value. After power-up reset, this read-only register (SERNUM0) contains byte 0 of the complete 64-bit device serial number. This register cannot be reset. 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET FUNCTION 7−0 D[7:0] Device serial number byte 0 value Device serial number byte 0 value NOTE: See the procedure described in the SERNUM7 register (see Section 5.7) to load the device serial number into shared RAM. USB Registers SLLS519H—January 2010 TUSB3410, TUSB3410I 31 5.15 Function Reset And Power-Up Reset Interconnect Figure 5−1 represents the logical connection of the USB-function reset (USBR) signal and the power-up reset (RESET) terminal. The internal RESET signal is generated from the RESET terminal (PURS signal) or from the USB reset (USBR signal). The USBR can be enabled or disabled by bit 4 (FRSTE) in the USBCTL register (see Section 5.4) (on power up, FRSTE = 0). The internal RESET is used to reset all registers and logic, with the exception of the USBCTL and MODECNFG registers which are cleared by the PURS signal only. USBCTL Register MODECNFG Register PURS USBR RESET MCU FRSTE USB Function Reset To Internal MMRs RESET G2 WDD[5:0] WDT Reset Figure 5−1. Reset Diagram 5.16 Pullup Resistor Connect/Disconnect The TUSB3410 enumeration can be activated by the MCU (there is no need to disconnect the cable physically). Figure 5−2 represents the implementation of the TUSB3410 connect and disconnect from a USB up-stream port. When bit 7 (CONT) is 1 in the USBCTL register (see Section 5.4), the CMOS driver sources VDD to the pullup resistor (PUR terminal) presenting a normal connect condition to the USB host. When CONT is 0, the PUR terminal is driven low. In this state, the 1.5-kΩ resistor is connected to GND, resulting in the device disconnection state. The PUR driver is a CMOS driver that can provide (VDD − 0.1 V) minimum at 8-mA source current. HOST D+ D− 15 kΩ TUSB3410 1.5 kΩ CMOS PUR CONT Bit DP0 DM0 Figure 5−2. Pullup Resistor Connect/Disconnect Circuit USB Registers 32 TUSB3410, TUSB3410I SLLS519H—January 2010 DMA Controller SLLS519H—January 2010 TUSB3410, TUSB3410I 33 6 DMA Controller Table 6−1 outlines the DMA channels and their associated transfer directions. Two channels are provided for data transfer between the host and the UART. Table 6−1. DMA Controller Registers DMA CHANNEL TRANSFER DIRECTION COMMENTS DMA−1 Host to UART DMA writes to UART TDR register DMA−3 UART to host DMA reads from UART RDR register 6.1 DMA Controller Registers Each DMA channel can point to one of three EDBs (EDB-1 to EDB-3) and transfer data to/from the UART channel. The DMA can move data from a given out-point buffer (defined by the EDB) to the destination port. Similarly, the DMA can move data from a port to a given input-endpoint buffer. At the end of a block transfer, the DMA updates the byte count and bit 7 (NAK) in the EDB (see Section 4.3) when receiving. In addition, it uses bit 4 (XY) in the DMACDR register to switch automatically, without interrupting the MCU (the XY bit toggle is performed by the UBM). The DMA stops only when a time-out or error condition occurs. When the DMA is transmitting (from the X/Y buffer) it continues alternating between X/Y buffers until it detects a byte count smaller than the buffer size (buffer size is typically 64 bytes). At that point it completes the transfer and stops. DMA Controller 34 TUSB3410, TUSB3410I SLLS519H—January 2010 6.1.1 DMACDR1: DMA Channel Definition Register (UART Transmit Channel) (Addr:FFE0h) These registers define the EDB number that the DMA uses for data transfer to the UARTS. In addition, these registers define the data transfer direction and selects X or Y as the transaction buffer. 7 6 5 4 3 2 1 0 EN INE CNT XY T/R E2 E1 E0 R/W R/W R/W R/W R/O R/W R/W R/W BIT NAME RESET FUNCTION 2−0 E[2:0] 0 Endpoint descriptor pointer. This field points to a set of EDB registers that is to be used for a given transfer. 3 T/R 0 This bit is always 1, indicating that the DMA data transfer is from SRAM to the UART TDR register (see Section 7.1.2). (The MCU cannot change this bit.) 4 XY 0 X/Y buffer select bit. XY = 0 XY = 1 Next buffer to transmit/receive is the X buffer Next buffer to transmit/receive is the Y buffer 5 CNT 0 DMA continuous transfer control bit. This bit defines the mode of the DMA transfer. This bit must always be written as 1. In this mode, the DMA and UBM alternate between the X- and Y-buffers. The DMA sets bit 4 (XY) and the UBM uses it for the transfer. The DMA alternates between the X-/Y-buffers and continues transmitting (from X-/Y-buffer) without MCU intervention. The DMA terminates, and interrupts the MCU, under the following conditions: 1. When the UBM byte count < buffer size (in EDB), the DMA transfers the partial packet and interrupt the MCU on completion. 2. Transaction timer expires. The DMA interrupts the MCU. 6 INE 0 DMA Interrupt enable/disable bit. This bit enables/disables the interrupt on transfer completion. INE = 0 Interrupt is disabled. In addition, bit 0 (PPKT) in the DMACSR1 register (see Section 6.1.2) does not clear bit 7 (EN) and the DMAC is not disabled. INE = 1 Enables the EN interrupt. When this bit is set, the DMA interrupts the MCU on a 1 to 0 transition of the bit 7 (EN). (When transfer is completed, EN = 0.) 7 EN 0 DMA channel enable bit. The MCU sets this bit to start the DMA transfer. When the transfer completes, or when it is terminated due to error, this bit is cleared. The 1 to 0 transition of this bit generates an interrupt (if the interrupt is enabled). EN = 0 DMA is halted. The DMA is halted when the byte count reaches zero or transaction time-out occurs. When halted, the DMA updates the byte count, sets NAK = 0 in the output endpoint byte count register, and interrupts the MCU (if bit 6 (INE) = 1). EN = 1 Setting this bit starts the DMA transfer. 6.1.2 DMACSR1: DMA Control And Status Register (UART Transmit Channel) (Addr:FFE1h) This register defines the transaction time-out value. In addition, it contains a completion code that reports any errors or a time-out condition. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PPKT R R R R R R R R/C BIT NAME RESET FUNCTION 0 PPKT 0 Partial packet condition bit. This bit is set by the DMA and cleared by the MCU. PPKT = 0 No partial-packet condition PPKT = 1 Partial-packet condition detected. When INE = 0, this bit does not clear bit 7 (EN) in the DMACDR1 register; therefore, the DMAC stays enabled, ready for the next transaction. Clears when MCU writes a 1. Writing a 0 has no effect. 7−1 − 0 These bits are read-only and return 0s when read. DMA Controller SLLS519H—January 2010 TUSB3410, TUSB3410I 35 6.1.3 DMACDR3: DMA Channel Definition Register (UART Receive Channel) (Addr:FFE4h) These registers define the EDB number that the DMA uses for data transfer from the UARTS. In addition, these registers define the data transfer direction and selects X or Y as the transaction buffer. 7 6 5 4 3 2 1 0 EN INE CNT XY T/R E2 E1 E0 R/W R/W R/W R/W R/O R/W R/W R/W BIT NAME RESET FUNCTION 2−0 E[2:0] 0 Endpoint descriptor pointer. This field points to a set of EDB registers that are used for a given transfer. 3 T/R 1 This bit is always read as 1. This bit must be written as 0 to update the X/Y buffer bit (bit 4 in this register) which must only be performed in burst mode. 4 XY 0 X/Y buffer select bit. XY = 0 XY = 1 Next buffer to transmit/receive is X Next buffer to transmit/receive is Y 5 CNT 0 DMA continuous transfer control bit. This bit defines the mode of the DMA transfer. This bit must always be written as 1. In this mode, the DMA and UBM alternate between the X- and Y-buffers. The UBM sets bit 4 (XY) and the DMA uses it for the transfer. The DMA alternates between the X-/Y-buffers and continues receiving (to X-/Y-buffer) without MCU intervention. The DMA terminates the transfer and interrupts the MCU, under the following conditions: 1. Transaction time-out expired: DMA updates EDB and interrupts the MCU. UBM transfers the partial packet to the host. 2. UART receiver error condition: DMA updates EDB and does not interrupt the MCU. UBM transfers the partial packet to the host. 6 INE 0 DMA interrupt enable/disable bit. This bit enables/disables the interrupt on transfer completion. INE = 0 Interrupt is disabled. In addition, bit 0 (OVRUN) and bit 1 (TXFT) in the DMACSR3 register (see Section 6.1.4) do not clear bit 7 (EN) and the DMAC is not disabled. INE = 1 Enables the EN interrupt. When this bit is set, the DMA interrupts the MCU on a 1-to-0 transition of bit 7 (EN). (When transfer is completed, EN = 0). 7 EN 0 DMA channel enable bit. The MCU sets this bit to start the DMA transfer. When transfer completes, or when terminated due to error, this bit is cleared. The 1-to-0 transition of this bit generates an interrupt (if the interrupt is enabled). EN = 0 DMA is halted. The DMA is halted when transaction time-out occurs, or under a UART receiver-error condition. When halted, the DMA updates the byte count and sets NAK = 0 in the input endpoint byte count register. If the termination is due to transaction time-out, then the DMA generates an interrupt. However, if the termination is due to a UART error condition, then the DMA does not generate an interrupt. (The UART generates the interrupt.) EN = 1 Setting this bit starts the DMA transfer. DMA Controller 36 TUSB3410, TUSB3410I SLLS519H—January 2010 6.1.4 DMACSR3: DMA Control And Status Register (UART Receive Channel) (Addr:FFE5h) This register defines the transaction time-out value. In addition, it contains a completion code that reports any errors or a time-out condition. 7 6 5 4 3 2 1 0 TEN C4 C3 C2 C1 C0 TXFT OVRUN R/W R/W R/W R/W R/W R/W R/C R/C BIT NAME RESET FUNCTION 0 OVRUN 0 Overrun condition bit. This bit is set by DMA and cleared by the MCU (see Table 6−2) OVRUN = 0 No overrun condition OVRUN = 1 Overrun condition detected. When IEN = 0, this bit does not clear bit 7 (EN) in the DMACDR register; therefore, the DMAC stays enabled, ready for the next transaction. Clears when the MCU writes a 1. Writing a 0 has no effect. 1 TXFT 0 Transfer time-out condition bit (see Table 6−2) TXFT = 0 DMA stopped transfer without time-out TXFT =1 DMA stopped due to transaction time-out. When IEN = 0, this bit does not clear bit 7 (EN) in the DMACDR3 register (see Section 6.1.3); therefore, the DMAC stays enabled, ready for the next transaction. Clears when the MCU writes a 1. Writing a 0 has no effect. 6−2 C[4:0] 00000b This field defines the transaction time-out value in 1-ms increments. This value is loaded to a down counter every time a byte transfer occurs. The down counter is decremented every SOF pulse (1 ms). If the counter decrements to zero, then it sets bit 1 (TXFT) = 1 and halts the DMA transfer. The counter starts counting only when bit 7 (TEN) = 1 and bit 7 (EN) = 1 in the DMACDR3 register and the first byte has been received. 00000 = 0-ms time-out : : 11111 = 31-ms time-out 7 TEN 0 Transaction time-out counter enable/disable bit TEN = 0 TEN = 1 Counter is disabled (does not time-out) Counter is enabled Table 6−2. DMA IN-Termination Condition IN TERMINATION TXFT OVRUN COMMENTS UART error 0 0 UART error condition detected UART partial packet 1 0 This condition occurs when UART receiver has no more data for the host (data starvation). UART overrun 1 1 This condition occurs when X- and Y-input buffers are full and the UART FIFO is full (host is busy). 6.2 Bulk Data I/O Using the EDB The UBM (USB buffer manager) and the DMAC (DMA controller) access the EDB to fetch buffer parameters for IN and OUT transactions (IN and OUT are with respect to host). In this discussion, it is assumed that: • The MCU initialized the EDBs • DMA-continuous mode is being used • Double buffering is being used • The X/Y toggle is controlled by the UBM DMA Controller SLLS519H—January 2010 TUSB3410, TUSB3410I 37 6.2.1 IN Transaction (TUSB3410 to Host) 1. The MCU initializes the IEDB (64-byte packet, and double buffering is used) and the following DMA registers: • DMACSR3: Defines the transaction time-out value. • DMACDR3: Defines the IEDB being used and the DMA mode of operation (continuous mode). Once this register is set with EN = 1, the transfer starts. 2. The DMA transfers data from the UART to the X buffer. When a block of 64 bytes is transferred, the DMA updates the byte count and sets NAK to 0 in the input endpoint byte count register (indicating to the UBM that the X buffer is ready to be transferred to host). The UBM starts X-buffer transfer to host using the byte-count value in the input endpoint byte count register and toggles the X/Y bit. The DMA continues transferring data from a device to Y-buffer. At the end of the block transfer, the DMA updates the byte count and sets NAK to 0 in the input endpoint byte count register (indicating to the UBM that the Y-buffer is ready to be transferred to host). The DMA continues the transfer from the device to host, alternating between X-and Y-buffers without MCU intervention. 3. Transfer termination: As mentioned, the DMA/UBM continues the data transfer, alternating between the X- and Y-buffers. Termination of the transfer can happen under the following conditions: • Stop Transfer: The host notifies the MCU (via control-end-point) to stop the transfer. Under this condition, the MCU sets bit 7 (EN) to 0 in the DMACDR register. • Partial Packet: The device receiver has no data to be transferred to host. Under this condition, the byte-count value is less than 64 when the transaction timer time-out occurs. When the DMA detects this condition, it sets bit 1 (TXFT) to 1 and bit 0 (OVRUN) to 0 in the DMACSR3 register, updates the byte count and NAK bit in the the input endpoint byte count register, and interrupts the MCU. The UBM transfers the partial packet to host. • Buffer Overrun: The host is busy, X- and Y-buffers are full (X-NAK = 0 and Y-NAK = 0), and the DMA cannot write to these buffers. The transaction time-out stops the DMA transfer, the DMA sets bit 1 (TXFT) to 1 and bit 0 (OVRUN) to 1 in the DMACSR3 register, and interrupts the MCU. • UART Error Condition: When receiving from a UART, a receiver-error condition stops the DMA and sets bit 1 (TXFT) to 1 and bit 0 (OVRUN) to 0 in the DMACSR3 register, but the EN bit remains set at 1. Therefore, the DMA does not interrupt the MCU. However, the UART generates a status interrupt, notifying the MCU that an error condition has occurred. DMA Controller 38 TUSB3410, TUSB3410I SLLS519H—January 2010 6.2.2 OUT Transaction (Host to TUSB3410) 1. The MCU initializes the OEDB (64-byte packet, and double buffering is used) and the following DMA registers: • DMACSR1: Provides an indication of a partial packet. • DMACDR1: Defines the output endpoint being used, and the DMA mode of operation (continuous mode). Once the EN bit is set to 1 in this register, the transfer starts. 2. The UBM transfers data from host to X-buffer. When a block of 64 bytes is transferred, the UBM updates the byte count and sets NAK to 1 in the output endpoint byte count register (indicating to DMA that the X-buffer is ready to be transferred to the UART). The DMA starts X-buffer transfer using the byte-count value in the output endpoint byte count register. The UBM continues transferring data from host to Y-buffer. At the end of the block transfer, the UBM updates the byte count and sets NAK to 1 in the output endpoint byte count register (indicating to DMA that the Y-buffer is ready to be transferred to device). The DMA continues the transfer from the X-/Y-buffers to the device, alternating between X- and Y-buffers without MCU intervention. 3. Transfer termination: The DMA/UBM continues the data transfer alternating between X- and Y-buffers. The termination of the transfer can happen under the following conditions: • Stop Transfer: The host notifies the MCU (via control-end point) to stop the transfer. Under this condition, the MCU sets EN to 0 in the DMACDR1 register. • Partial-Packet: UBM receives a partial packet from host. Under this condition, the byte-count value is less than 64. When the DMA detects this condition, it transfers the partial packet to the device, sets PPKT to 1, updates NAK to 0 in the output endpoint byte count register, and interrupts the MCU. UART SLLS519H—January 2010 TUSB3410, TUSB3410I 39 7 UART 7.1 UART Registers Table 7−1 summarizes the UART registers. These registers are used for data I/O, control, and status information. UART setup is done by the MCU. Data transfer is typically performed by the DMAC. However, the MCU can perform data transfer without a DMA; this is useful when debugging the firmware. Table 7−1. UART Registers Summary REGISTER ADDRESS REGISTER NAME ACCESS FUNCTION COMMENTS FFA0h RDR R/O UART receiver data register Can be accessed by MCU or DMA FFA1h TDR W/O UART transmitter data register Can be accessed by MCU or DMA FFA2h LCR R/W UART line control register FFA3h FCRL R/W UART flow control register FFA4h MCR R/W UART modem control register FFA5h LSR R/O UART line status register Can generate an interrupt FFA6h MSR R/O UART modem status register Can generate an interrupt FFA7h DLL R/W UART divisor register (low byte) FFA8h DLH R/W UART divisor register (high byte) FFA9h XON R/W UART Xon register FFAAh XOFF R/W UART Xoff register FFABh MASK R/W UART interrupt mask register Can control three interrupt sources 7.1.1 RDR: Receiver Data Register (Addr:FFA0h) The receiver data register consists of a 32-byte FIFO. Data received via the SIN terminal is converted from serial-to-parallel format and stored in this FIFO. Data transfer from this register to the RAM buffer is the responsibility of the DMA controller. 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET FUNCTION 7−0 D[7:0] 0 Receiver byte 7.1.2 TDR: Transmitter Data Register (Addr:FFA1h) The transmitter data register is double buffered. Data written to this register is loaded into the shift register, and shifted out on SOUT. Data transfer from the RAM buffer to this register is the responsibility of the DMA controller. 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 W/O W/O W/O W/O W/O W/O W/O W/O BIT NAME RESET FUNCTION 7−0 D[7:0] 0 Transmit byte UART 40 TUSB3410, TUSB3410I SLLS519H—January 2010 7.1.3 LCR: Line Control Register (Addr:FFA2h) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. 7 6 5 4 3 2 1 0 FEN BRK FPTY EPRTY PRTY STP WL1 WL0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 1:0 WL[1:0] 0 Specifies the word length for transmit and receive 00b = 5 bits 01b = 6 bits 10b = 7 bits 11b = 8 bits 2 STP 0 Specifies the number of stop bits for transmit and receive STP = 0 STP = 1 STP = 1 1 stop bit (word length = 5, 6, 7, 8) 1.5 stop bits (word length = 5) 2 stop bits (word length = 6, 7, 8) 3 PRTY 0 Specifies whether parity is used PRTY = 0 PRTY = 1 No parity Parity is generated 4 EPRTY 0 Specifies whether even or odd parity is generated EPRTY = 0 EPRTY = 1 Odd parity is generated (if bit 3 (PRTY) = 1) Even parity is generated (if PRTY = 1) 5 FPTY 0 Selects the forced parity bit FPTY = 0 FPTY = 1 Parity is not forced Parity bit is forced. If bit 4 (EPRTY) = 0, the parity bit is forced to 1 6 BRK 0 This bit is the break-control bit BRK = 0 BRK = 1 Normal operation Forces SOUT into break condition (logic 0) 7 FEN 0 FIFO enable. This bit disables/enables the FIFO. To reset the FIFO, the MCU clears and then sets this bit. FEN = 0 FEN = 1 The FIFO is cleared and disabled. When disabled, the selected receiver flow control is activated. The FIFO is enabled and it can receive data. UART SLLS519H—January 2010 TUSB3410, TUSB3410I 41 7.1.4 FCRL: UART Flow Control Register (Addr:FFA3h) This register provides the flow-control modes of operation (see Table 7−3 for more details). 7 6 5 4 3 2 1 0 485E DTR RTS RXOF DSR CTS TXOA TXOF R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 0 TXOF 0 This bit controls the transmitter Xon/Xoff flow control. TXOF = 0 TXOF = 1 Disable transmitter Xon/Xoff flow control Enable transmitter Xon/Xoff flow control 1 TXOA 0 This bit controls the transmitter Xon-on-any/Xoff flow control TXOA = 0 TXOA = 1 Disable the transmitter Xon-on-any/Xoff flow control Enable the transmitter Xon-on-any/Xoff flow control 2 CTS 0 Transmitter CTS flow-control enable bit CTS = 0 CTS = 1 Disables transmitter CTS flow control CTS flow control is enabled, that is, when CTS input terminal is high, transmission is halted; when the CTS terminal is low, transmission resumes. When loopback mode is enabled, this bit must be set if flow control is also required. 3 DSR 0 Transmitter DSR flow-control enable bit DSR = 0 DSR = 1 Disables transmitter DSR flow control DSR flow control is enabled, that is, when DSR input terminal is high, transmission is halted; when the DSR terminal is low, transmission resumes. When loopback mode is enabled, this bit must be set if flow control is also required. 4 RXOF 0 This bit controls the receiver Xon/Xoff flow control. RXOF = 0 RXOF = 1 Receiver does not attempt to match Xon/Xoff characters Receiver searches for Xon/Xoff characters 5 RTS 0 Receiver RTS flow control enable bit RTS = 0 RTS = 1 Disables receiver RTS flow control Receiver RTS flow control is enabled. RTS output terminal goes high when the receiver FIFO HALT trigger level is reached; it goes low, when the receiver FIFO RESUME receiving trigger level is reached. 6 DTR 0 Receiver DTR flow-control enable bit DTR = 0 DTR = 1 Disables receiver DTR flow control Receiver DTR flow control is enabled. DTR output terminal goes high when the receiver FIFO HALT trigger level is reached; it goes low, when the receiver FIFO RESUME receiving trigger level is reached. 7 485E 0 RS-485 enable bit. This bit configures the UART to control external RS-485 transceivers. When configured in half-duplex mode (485E = 1), RTS or DTR can be used to enable the RS-485 driver or receiver. See Figure 3−3. 485E = 0 485E = 1 UART is in normal operation mode (full duplex) The UART is in half duplex RS-485 mode. In this mode, RTS and DTR are active with opposite polarity (when RTS = 0, DTR = 1). When the DMA is ready to transmit, it drives RTS = 1 (and DTR = 0) 2-bit times before the transmission starts. When the DMA terminates the transmission, it drives RTS = 0 (and DTR = 1) after the transmission stops. When 485E is set to 1, bit 4 (DTR) and bit 5 (RTS) in the MCR register (see Section 7.1.6) have no effect. Also, see bit 1 (RCVE) in the MCR register. UART 42 TUSB3410, TUSB3410I SLLS519H—January 2010 7.1.5 Transmitter Flow Control On reset (power up, USB, or soft reset) the transmitter defaults to the Xon state and the flow control is set to mode-0 (flow control is disabled). Table 7−2. Transmitter Flow-Control Modes BIT 3 BIT 2 BIT 1 BIT 0 DSR CTS TXOA TXOF All flow control is disabled 0 0 0 0 Xon/Xoff flow control is enabled 0 0 0 1 Xon on any/ Xoff flow control 0 0 1 0 Not permissible (see Note 9) X X 1 1 CTS flow control 0 1 0 0 Combination flow control (see Note 10) 0 1 0 1 Combination flow control 0 1 1 0 DSR flow control 1 0 0 0 1 0 0 1 1 0 1 0 Combination flow control 1 1 0 0 1 1 0 1 1 1 1 0 NOTES: 9. This is a nonpermissible combination. If used, TXOA and TXOF are cleared. 10. Combination example: Transmitter stops when either CTS or Xoff is detected. Transmitter resumes when both CTS is negated and Xon is detected. Table 7−3. Receiver Flow-Control Possibilities MODE BIT 6 BIT 5 BIT 4 DTR RTS RXOF 0 All flow control is disabled 0 0 0 1 Xon/Xoff flow control is enabled 0 0 1 2 RTS flow control 0 1 0 3 Combination flow control (see Note 11) 0 1 1 4 DTR flow control 1 0 0 5 Combination flow control 1 0 1 6 Combination flow control (see Note 12) 1 1 0 7 Combination flow control 1 1 1 NOTES: 11. Combination example: Both RTS is asserted and Xoff transmitted when the FIFO is full. Both RTS is deasserted and Xon is transmitted when the FIFO is empty. 12. Combination example: Both DTR and RTS are asserted when the FIFO is full. Both DTR and RTS are deasserted when the FIFO is empty. UART SLLS519H—January 2010 TUSB3410, TUSB3410I 43 7.1.6 MCR: Modem-Control Register (Addr:FFA4h) This register provides control for modem interface I/O and definition of the flow control mode. 7 6 5 4 3 2 1 0 LCD LRI RTS DTR RSV LOOP RCVE URST R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 0 URST 0 UART soft reset. This bit can be used by the MCU to reset the UART. URST = 0 Normal operation. Writing a 0 by MCU has no effect. URST = 1 When the MCU writes a 1 to this bit, a UART reset is generated (ORed with hard reset). When the UART exits the reset state, URST is cleared. The MCU can monitor this bit to determine if the UART completed the reset cycle. 1 RCVE 0 Receiver enable bit. This bit is valid only when bit 7 (485E) in the FCRL register (see Section 7.1.4) is 1 (RS-485 mode). When 485E = 0, this bit has no effect on the receiver. RCVE = 0 When 485E = 1, the UART receiver is disabled when RTS = 1, i.e., when data is being transmitted, the UART receiver is disabled. RCVE = 1 When 485E = 1, the UART receiver is enabled regardless of the RTS state, i.e., UART receiver is enabled all the time. This mode can detect collisions on the RS-485 bus when received data does not match transmitted data. 2 LOOP 0 This bit controls the normal-/loop-back mode of operation (see Figure 7−1). LOOP = 0 Normal operation LOOP = 1 Enable loop-back mode of operation. In this mode the following occur:  SOUT is set high  SIN is disconnected from the receiver input.  The transmitter serial output is looped back into the receiver serial input.  The four modem-control inputs: CTS, DSR, DCD, and RI/CP are disconnected.  DTR, RTS, LRI and LCD are internally connected to the four modem-control inputs, and read in the MSR register (see Section 7.1.8) as described below. Note: the FCRL register (see Section 7.1.4) must be configured to enable bits 2 (CTS) and 3 (DSR) to maintain proper operation with flow control and loop back.  DTR is reflected in MSR register bit 4 (LCTS)  RTS is reflected in MSR register bit 5 (LDSR)  LRI is reflected in MSR register bit 6 (LRI)  LCD is reflected in MSR register bit 7 (LCD) 3 RSV 0 Reserved 4 DTR 0 This bit controls the state of the DTR output terminal (see Figure 7−1). This bit has no effect when auto-flow control is used or when bit 7 (485E) = 1 (in the FCRL register, see Section 7.1.4). DTR = 0 Forces the DTR output terminal to inactive (high) DTR = 1 Forces the DTR output terminal to active (low) 5 RTS 0 This bit controls the state of the RTS output terminal (see Figure 7−1). This bit has no effect when auto-flow control is used or when bit 7 (485E) = 1 (in the FCRL register, see Section 7.1.4). RTS = 0 Forces the RTS output terminal to inactive (high) RTS = 1 Forces the RTS output terminal to active (low) 6 LRI 0 This bit is used for loop-back mode only. When in loop-back mode, this bit is reflected in bit 6 (LRI) in the MSR register, see Section 7.1.8 (see Figure 7−1). LRI = 0 Clears the MSR register bit 6 to 0 LRI = 1 Sets the MSR register bit 6 to 1 7 LCD 0 This bit is used for loop-back mode only. When in loop-back mode, this bit is reflected in bit 7 (LCD) in the MSR register, see Section 7.1.8 (see Figure 7−1). LCD = 0 Clears the MSR register bit 7 to 0 LCD = 1 Sets the MSR register bit 7 to 1 UART 44 TUSB3410, TUSB3410I SLLS519H—January 2010 7.1.7 LSR: Line-Status Register (Addr:FFA5h) This register provides the status of the data transfer. DMA transfer is halted when any of bit 0 (OVR), bit 1 (PTE), bit 2 (FRE), or bit 3 (BRK) is 1. 7 6 5 4 3 2 1 0 RSV TEMT TxE RxF BRK FRE PTE OVR R/O R/O R/O R/O R/C R/C R/C R/C BIT NAME RESET FUNCTION 0 OVR 0 This bit indicates the overrun condition of the receiver. If set, it halts the DMA transfer and generates a status interrupt (if enabled). OVR = 0 OVR = 1 No overrun error Overrun error has occurred. Clears when the MCU writes a 1. Writing a 0 has no effect. 1 PTE 0 This bit indicates the parity condition of the received byte. If set, it halts the DMA transfer and generates a status interrupt (if enabled). PTE = 0 PTE = 1 No parity error in data received Parity error in data received. Clears when the MCU writes a 1. Writing a 0 has no effect. 2 FRE 0 This bit indicates the framing condition of the received byte. If set, it halts the DMA transfer and generates a status interrupt (if enabled). FRE = 0 FRE = 1 No framing error in data received Framing error in data received. Clears when MCU writes a 1. Writing a 0 has no effect. 3 BRK 0 This bit indicates the break condition of the received byte. If set, it halts the DMA transfer and generates a status interrupt (if enabled). BRK = 0 BRK = 1 No break condition A break condition in data received was detected. Clears when the MCU writes a 1. Writing a 0 has no effect. 4 RxF 0 This bit indicates the condition of the receiver data register. Typically, the MCU does not monitor this bit since data transfer is done by the DMA controller. RxF = 0 RxF = 1 No data in the RDR RDR contains data. Generates Rx interrupt (if enabled). 5 TxE 1 This bit indicates the condition of the transmitter data register. Typically, the MCU does not monitor this bit since data transfer is done by the DMA controller. TxE = 0 TxE = 1 TDR is not empty TDR is empty. Generates Tx interrupt (if enabled). 6 TEMT 1 This bit indicates the condition of both transmitter data register and shift register is empty. TEMT = 0 TEMT = 1 Either TDR or TSR is not empty Both TDR and TSR are empty 7 RSV 0 Reserved = 0 UART SLLS519H—January 2010 TUSB3410, TUSB3410I 45 CTS Modem Status Register Modem Control Register Bit 4 LCTS Bit 5 LDSR Bit 6 LRI Bit 7 LCD Bit 5 RTS Bit 4 DTR Bit 6 LRI Bit 7 LCD Bit 2 LOOP DSR RI/CP DCD RTS DTR FCRL Register Setting FCRL Register Setting Device Terminals Figure 7−1. MSR and MCR Registers in Loop-Back Mode UART 46 TUSB3410, TUSB3410I SLLS519H—January 2010 7.1.8 MSR: Modem-Status Register (Addr:FFA6h) This register provides information about the current state of the control lines from the modem. 7 6 5 4 3 2 1 0 LCD LRI LDSR LCTS ΔCD TRI ΔDSR ΔCTS R/O R/O R/O R/O R/C R/C R/C R/C BIT NAME RESET FUNCTION 0 ΔCTS 0 This bit indicates that the CTS input has changed state. Cleared when the MCU writes a 1 to this bit. Writing a 0 has no effect. 1 ΔDSR 0 This bit indicates that the DSR input has changed state. Cleared when the MCU writes a 1 to this bit. Writing a 0 has no effect. ΔDSR = 0 ΔDSR = 1 Indicates no change in the DSR input Indicates that the DSR input has changed state since the last time it was read. Clears when the MCU writes a 1. Writing a 0 has no effect. 2 TRI 0 Trailing edge of the ring indicator. This bit indicates that the RI/CP input has changed from low to high. This bit is cleared when the MCU writes a 1 to this bit. Writing a 0 has no effect. TRI = 0 TRI = 1 Indicates no applicable transition on the RI/CP input Indicates that an applicable transition has occurred on the RI/CP input. 3 ΔCD 0 This bit indicates that the CD input has changed state. Cleared when the MCU writes a 1 to this bit. Writing a 0 has no effect. ΔCD = 0 ΔCD = 1 Indicates no change in the CD input Indicates that the CD input has changed state since the last time it was read. 4 LCTS 0 During loopback, this bit reflects the status of bit 4 (DTR) in the MCR register, see Section 7.1.6 (see Figure 7−1) LCTS = 0 LCTS = 1 CTS input is high CTS input is low 5 LDSR 0 During loop back, this bit reflects the status of bit 5 (RTS) in the MCR register, see Section 7.1.6 (see Figure 7−1) LDSR = 0 LDSR= 1 DSR input is high DSR input is low 6 LRI 0 During loop back, this bit reflects the status of bit 6 (LRI) in the MCR register, see Section 7.1.6 (see Figure 7−1) LRI = 0 LRI = 1 RI/CP input is high RI/CP input is low 7 LCD 0 During loopback, this bit reflects the status of bit 7 (LCD) in the MCR register, see Section 7.1.6 (see Figure 7−1) LCD = 0 LCD = 0 CD input is high CD input is low 7.1.9 DLL: Divisor Register Low Byte (Addr:FFA7h) This register contains the low byte of the baud-rate divisor. 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 7−0 D[7:0] 08h Low-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate generator. UART SLLS519H—January 2010 TUSB3410, TUSB3410I 47 7.1.10 DLH: Divisor Register High Byte (Addr:FFA8h) This register contains the high byte of the baud-rate divisor. 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 7−0 D[15:8] 00h High-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate generator. 7.1.11 Baud-Rate Calculation The following formulas calculate the baud-rate clock and the divisors. The baud-rate clock is derived from the 96-MHz master clock (dividing by 6.5). The table below presents the divisors used to achieve the desired baud rates, together with the associate rounding errors. Baud CLK  96 MHz 6.5  14.76923077 MHz Divisor  14.76923077106 Desired Baud Rate 16 Table 7−4. DLL/DLH Values and Resulted Baud Rates DESIRED BAUD DLL/DLH VALUE ACTUAL BAUD ERROR % RATE DECIMAL HEXADECIMAL RATE 1 200 769 0301 1 200.36 0.03 2 400 385 0181 2 397.60 0.01 4 800 192 00C0 4 807.69 0.16 7 200 128 0080 7 211.54 0.16 9 600 96 0060 9 615.38 0.16 14 400 64 0040 14 423.08 0.16 19 200 48 0030 19 230.77 0.16 38 400 24 0018 38 461.54 0.16 57 600 16 0010 57 692.31 0.16 115 200 8 0008 115 384.62 0.16 230 400 4 0004 230 769.23 0.16 460 800 2 0002 461 538.46 0.16 921 600 1 0001 923 076.92 0.16 NOTE: The TUSB3410 does support baud rates lower than 1200 bps, which are not listed due to less interest. 7.1.12 XON: Xon Register (Addr:FFA9h) This register contains a value that is compared to the received data stream. Detection of a match interrupts the MCU (only if the interrupt enable bit is set). This value is also used for Xon transmission. 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 7−0 D[7:0] 0000 Xon value to be compared to the incoming data stream UART 48 TUSB3410, TUSB3410I SLLS519H—January 2010 7.1.13 XOFF: Xoff Register (Addr:FFAAh) This register contains a value that is compared to the received data stream. Detection of a match halts the DMA transfer, and interrupts the MCU (only if the interrupt enable bit is set). This value is also used for Xoff transmission. 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 7−0 D[7:0] 0000 Xoff value to be compared to the incoming data stream 7.1.14 MASK: UART Interrupt-Mask Register (Addr:FFABh) This register controls the UARTs interrupt sources. 7 6 5 4 3 2 1 0 RSV RSV RSV RSV RSV TRI SIE MIE R/O R/O R/O R/O R/O R/W R/W R/W BIT NAME RESET FUNCTION 0 MIE 0 This bit controls the UART-modem interrupt. MIE = 0 MIE = 1 Modem interrupt is disabled Modem interrupt is enabled 1 SIE 0 This bit controls the UART-status interrupt. SIE = 0 SIE = 1 Status interrupt is disabled Status interrupt is enabled 2 TRI 0 This bit controls the UART-TxE/RxF interrupts TRI = 0 TRI = 1 TxE/RxF interrupts are disabled TxE/RxF interrupts are enabled 7−3 RSV 0 Reserved = 0 7.2 UART Data Transfer Figure 7−2 illustrates the data transfer between the UART and the host using the DMA controller and the USB buffer manager (UBM). A buffer of 512 bytes is reserved for buffering the UART channel (transmit and receive buffers). The UART channel has 64 bytes of double-buffer space (X- and Y-buffer). When the DMA writes to the X-buffer, the UBM reads from the Y-buffer. Similarly, when the DMA reads from the X-buffer, the UBM writes to the Y-buffer. The DMA channel is configured to operate in the continuous mode (by setting bit 5 (CNT) in the DMACDR registers = 1). Once the MCU enables the DMA, data transfer toggles between the UMB and the DMA without MCU intervention. See Section 6.2.1, IN Transaction (TUSB3410 to Host), for DMA transfer-termination condition. 7.2.1 Receiver Data Flow The UART receiver has a 32-byte FIFO. The receiver FIFO has two trigger levels. One is the high-level mark (HALT), which is set to 12 bytes, and the other is the low-level mark (RESUME), which is set to 4 bytes. When the HALT mark is reached, either the RTS terminal goes high or Xoff is transmitted (depending on the auto setting). When the FIFO reaches the RESUME mark, then either the RTS terminal goes low or Xon is transmitted. UART SLLS519H—January 2010 TUSB3410, TUSB3410I 49 64-Byte Y-Buffer 64-Byte X-Buffer DMA DMACDR3 USB Buffer Manager X/Y 4 8 Receiver Halt on Error or Time-Out RDR: 32-Byte FIFO RTS/DTR = 1 or Xoff Transmitted RTS/DTR = 0 or Xon Transmitted Xoff/Xon CTS/DTR = 1/0 64-Byte Y-Buffer 64-Byte X-Buffer DMA DMACDR1 SIN SOUT TDR Pause/Run Host Figure 7−2. Receiver/Transmitter Data Flow 7.2.2 Hardware Flow Control Figure 7−3 illustrates the connection necessary to achieve hardware flow control. The CTS and RTS signals are provided for this purpose. Auto CTS and auto RTS (and Xon/Xoff) can be enabled/disabled independently by programming the UART flow control register (FCRL). TUSB3410 SIN RTS SOUT CTS External Device SOUT CTS SIN RTS Figure 7−3. Auto Flow Control Interconnect 7.2.3 Auto RTS (Receiver Control) In this mode, the RTS output terminal signals the receiver-FIFO status to an external device. The RTS output signal is controlled by the high- and low-level marks of the FIFO. When the high-level mark is reached, RTS goes high, signaling to an external sending device to halt its transfer. Conversely, when the low-level mark is reached, RTS goes low, signaling to an external sending device to resume its transfer. Data transfer from the FIFO to the X-/Y-buffer is performed by the DMA controller. See Section 6.2.1, IN Transaction (TUSB3410 to Host), for DMA transfer-termination condition. 7.2.4 Auto CTS (Transmitter Control) In this mode, the CTS input terminal controls the transfer from internal buffer (X or Y) to the TDR. When the DMA controller transfers data from the Y-buffer to the TDR and the CTS input terminal goes high, the DMA controller is suspended until CTS goes low. Meanwhile, the UBM is transferring data from the host to the X-buffer. When CTS goes low, the DMA resumes the transfer. Data transfer continues alternating between the X- and Y-buffers, without MCU intervention. See Section 6.2.2, OUT Transaction (Host to TUSB3410), for DMA transfer-termination condition. UART 50 TUSB3410, TUSB3410I SLLS519H—January 2010 7.2.5 Xon/Xoff Receiver Flow Control To enable Xon/Xoff flow control, certain bits within the modem control register must be set as follows: MCR bit 5 = 1 and MCR bits 6 and 7 = 00. In this mode, the Xon/Xoff bytes are transmitted to an external sending device to control the device’s transmission. When the high-level mark (of the FIFO) is reached, the Xoff byte is transmitted, signaling to an external sending device to halt its transfer. Conversely, when the low-level mark is reached, the Xon byte is transmitted, signaling to an external sending device to resume its transfer. The data transfer from the FIFO to X-/Y-buffer is performed by the DMA controller. 7.2.6 Xon/Xoff Transmit Flow Control To enable Xon/Xoff flow control, certain bits within the modem control register must be set as follows: MCR bit 5 = 1 and MCR bits 6 and 7 = 00. In this mode, the incoming data are compared to the XON and XOFF registers. If a match to XOFF is detected, the DMA is paused. If a match to XON is detected, the DMA resumes. Meanwhile, the UBM is transferring data from the host to the X-buffer. The MCU does not switch the buffers unless the Y-buffer is empty and the X-buffer is full. When Xon is detected, the DMA resumes the transfer. Expanded GPIO Port SLLS519H—January 2010 TUSB3410, TUSB3410I 51 8 Expanded GPIO Port 8.1 Input/Output and Control Registers The TUSB3410 has four general-purpose I/O terminals (P3.0, P3.1, P3.3, and P3.4) that are controlled by firmware running on the MCU. Each terminal can be controlled individually and each is implemented with a 12-mA push/pull CMOS output with 3-state control plus input. The MCU treats the outputs as open drain types in that the output can be driven low continuously, but a high output is driven for two clock cycles and then the output is high impedance. An input terminal can be read using the MOV instruction. For example, MOV C,P3.3 reads the input on P3.3. As a precaution, be certain the associated output is high impedance before reading the input. An output can be set high (and then high impedance) using the SETB instruction. For example, SETB P3.1 sets P3.1 high. An output can be set low using the CLR instruction, as in CLR P3.4, which sets P3.4 low (driven continuously until changed). Each GPIO terminal has an associated internal pullup resistor. It is strongly recommended that the pullup resistor remain connected to the terminal to prevent oscillations in the input buffer. The only exception is if an external source always drives the input. 8.1.1 PUR_3: GPIO Pullup Register For Port 3 (Addr:FF9Eh) 7 6 5 4 3 2 1 0 RSV RSV RSV Pin4 Pin3 RSV Pin1 Pin0 R/O R/O R/O R/W R/W R/O R/W R/W BIT NAME RESET FUNCTION 0 1 3 4 Pin0 Pin1 Pin3 Pin4 0 The MCU may write to this register. If the MCU sets any of these bits to 1, then the pullup resistor is disconnected from the associated terminal. If the MCU clears any of these bits to 0, then the pullup resistor is connected from the terminal. The pullup resistor is connected to the VCC power supply. 2, 5, 6, 7 RSV 0 Reserved Expanded GPIO Port 52 TUSB3410, TUSB3410I SLLS519H—January 2010 Interrupts SLLS519H—January 2010 TUSB3410, TUSB3410I 53 9 Interrupts 9.1 8052 Interrupt and Status Registers All 8052 standard, five interrupt sources are preserved. SIE is the standard interrupt-enable register that controls the five interrupt sources. This is also known as IE0 located at S:A8h in the special function register area. All the additional interrupt sources are ORed together to generate EX0. Table 9−1. 8052 Interrupt Location Map INTERRUPT SOURCE DESCRIPTION START ADDRESS COMMENTS ES UART interrupt 0023h ET1 Timer-1 interrupt 001Bh EX1 External interrupt-1 0013h ET0 Timer-0 interrupt 000Bh EX0 External interrupt-0 0003h Used for all internal peripherals Reset 0000h 9.1.1 8052 Standard Interrupt Enable (SIE) Register 7 6 5 4 3 2 1 0 EA RSV RSV ES ET1 EX1 ET0 EX0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 0 EX0 0 Enable or disable external interrupt-0 EX0 = 0 EX0 = 1 External interrupt-0 is disabled External interrupt-0 is enabled 1 ET0 0 Enable or disable timer-0 interrupt ET0 = 0 ET0 = 1 Timer-0 interrupt is disabled Timer-0 interrupt is enabled 2 EX1 0 Enable or disable external interrupt-1 EX1 = 0 EX1 = 1 External interrupt-1 is disabled External interrupt-1 is enabled 3 ET1 0 Enable or disable timer-1 interrupt ET1 = 0 EX1 = 1 Timer-1 interrupt is disabled Timer-1 interrupt is enabled 4 ES 0 Enable or disable serial port interrupts ES = 0 ES = 1 Serial-port interrupt is disabled Serial-port interrupt is enabled 5, 6 RSV 0 Reserved 7 EA 0 Enable or disable all interrupts (global disable) EA = 0 EA = 1 Disable all interrupts Each interrupt source is individually controlled 9.1.2 Additional Interrupt Sources All nonstandard 8052 interrupts (DMA, I2C, etc.) are ORed to generate an internal INT0. Furthermore, the INT0 must be programmed as an active low-level interrupt (not edge-triggered). After reset, if INT0 is not changed, then it is an edge-triggered interrupt. A vector interrupt register is provided to identify all interrupt sources (see Section 9.1.3, VECINT: Vector Interrupt Register). Up to 64 interrupt vectors are provided. It is the responsibility of the MCU to read the vector and dispatch to the proper interrupt routine. Interrupts 54 TUSB3410, TUSB3410I SLLS519H—January 2010 9.1.3 VECINT: Vector Interrupt Register (Addr:FF92h) This register contains a vector value, which identifies the internal interrupt source that is trapped to location 0003h. Writing (any value) to this register removes the vector and updates the next vector value (if another interrupt is pending). Note: the vector value is offset; therefore, its value is in increments of two (bit 0 is set to 0). When no interrupt is pending, the vector is set to 00h (see Table 9−2). As shown, the interrupt vector is divided to two fields: I[2:0] and G[3:0]. The I field defines the interrupt source within a group (on a first-come-first-served basis). In the G field, which defines the group number, group G0 is the lowest and G15 is the highest priority. 7 6 5 4 3 2 1 0 G3 G2 G1 G0 I2 I1 I0 0 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET FUNCTION 3−1 I[2:0] 0H This field defines the interrupt source in a given group. See Table 9−2. Bit 0 = 0 always; therefore, vector values are offset by two. 7−4 G[3:0] 0H This field defines the interrupt group. I[2:0] and G[3:0] combine to produce the actual interrupt vector. Table 9−2. Vector Interrupt Values G[3:0] (Hex) I[2:0] (Hex) VECTOR (Hex) INTERRUPT SOURCE 0 0 00 No interrupt 1 1 1 1 1 0 1 2 3 4−7 10 12 14 16 18−1E Not used Output endpoint-1 Output endpoint-2 Output endpoint-3 Reserved 2 2 2 2 2 0 1 2 3 4−7 20 22 24 26 28−2E Reserved Input endpoint-1 Input endpoint-2 Input endpoint-3 Reserved 3 3 3 3 3 3 3 3 0 1 2 3 4 5 6 7 30 32 34 36 38 3A 3C 3E STPOW packet received SETUP packet received Reserved Reserved RESR interrupt SUSR interrupt RSTR interrupt Wakeup 4 4 4 4 4 0 1 2 3 4−7 40 42 44 46 48 → 4E I2C TXE interrupt I2C RXF interrupt Input endpoint-0 Output endpoint-0 Reserved 5 5 5 0 1 2−7 50 52 54 → 5E UART status interrupt UART modem interrupt Reserved 6 6 6 0 1 2−7 60 62 64 → 6E UART RXF interrupt UART TXE interrupt Reserved 7 0−7 70 → 7E Reserved 8 8 8 0 2 3−7 80 84 86−8E DMA1 interrupt DMA3 interrupt Reserved 9−15 X 90 → FE Not used Interrupts SLLS519H—January 2010 TUSB3410, TUSB3410I 55 9.1.4 Logical Interrupt Connection Diagram (Internal/External) Figure 9−1 shows the logical connection of the interrupt sources and its relationship to INT0. The priority encoder generates an 8-bit vector, corresponding to 64 interrupt sources (not all are used). The interrupt priorities are hardwired. Vector 0x88 is the highest and 0x12 is the lowest. Priority Encoder Interrupts IEO (INT0) IEO Vector Figure 9−1. Internal Vector Interrupt Interrupts 56 TUSB3410, TUSB3410I SLLS519H—January 2010 I2C Port SLLS519H—January 2010 TUSB3410, TUSB3410I 57 10 I2C Port 10.1 I2C Registers 10.1.1 I2CSTA: I2C Status and Control Register (Addr:FFF0h) This register controls the stop condition for read and write operations. In addition, it provides transmitter and receiver handshake signals with their respective interrupt enable bits. 7 6 5 4 3 2 1 0 RXF RIE ERR 1/4 TXE TIE SRD SWR R/O R/W R/C R/W R/O R/W R/W R/W BIT NAME RESET FUNCTION 0 SWR 0 Stop write condition. This bit determines if the I2C controller generates a stop condition when data from the I2CDAO register is transmitted to an external device. SWR = 0 Stop condition is not generated when data from the I2CDAO register is shifted out to an external device. SWR = 1 Stop condition is generated when data from the I2CDAO register is shifted out to an external device. 1 SRD 0 Stop read condition. This bit determines if the I2C controller generates a stop condition when data is received and loaded into the I2CDAI register. SRD = 0 Stop condition is not generated when data from the SDA line is shifted into the I2CDAI register. SRD = 1 Stop condition is generated when data from the SDA line are shifted into the I2CDAI register. 2 TIE 0 I2C transmitter empty interrupt enable TIE = 0 TIE = 1 Interrupt disable Interrupt enable 3 TXE 1 I2C transmitter empty. This bit indicates that data can be written to the transmitter. It can be used for polling or it can generate an interrupt. TXE = 0 Transmitter is full. This bit is cleared when the MCU writes a byte to the I2CDAO register. TXE = 1 Transmitter is empty. The I2C controller sets this bit when the contents of the I2CDAO register are copied to the SDA shift register. 4 1/4 0 Bus speed selection (see Note 13) 1/4 = 0 1/4 = 1 100-kHz bus speed 400-kHz bus speed 5 ERR 0 Bus error condition. This bit is set by the hardware when the device does not respond. It is cleared by the MCU. ERR = 0 No bus error ERR = 1 Bus error condition has been detected. Clears when the MCU writes a 1. Writing a 0 has no effect. 6 RIE 0 I2C receiver ready interrupt enable RIE = 0 RIE = 1 Interrupt disable Interrupt enable 7 RXF 0 I2C receiver full. This bit indicates that the receiver contains new data. It can be used for polling or it can generate an interrupt. RXF = 0 Receiver is empty. This bit is cleared when the MCU reads the I2CDAI register. RXF = 1 Receiver contains new data. This bit is set by the I2C controller when the received serial data has been loaded into the I2CDAI register. NOTE 13: The bootcode automatically sets the I2C bus speed to 400 kHz. Only 400-kHz I2C EEPROMs can be used. I2C Port 58 TUSB3410, TUSB3410I SLLS519H—January 2010 10.1.2 I2CADR: I2C Address Register (Addr:FFF3h) This register holds the device address and the read/write command bit. 7 6 5 4 3 2 1 0 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 0 R/W 0 Read/write command bit R/W = 0 R/W = 1 Write operation Read operation 7−1 A[6:0] 0h Seven address bits for device addressing 10.1.3 I2CDAI: I2C Data-Input Register (Addr:FFF2h) This register holds the received data from an external device. 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET FUNCTION 7−0 D[7:0] 0 8-bit input data from an I2C device 10.1.4 I2CDAO: I2C Data-Output Register (Addr:FFF1h) This register holds the data to be transmitted to an external device. Writing to this register starts the transfer on the SDA line. 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 W/O W/O W/O W/O W/O W/O W/O W/O BIT NAME RESET FUNCTION 7−0 D[7:0] 0 8-bit output data to an I2C device 10.2 Random-Read Operation A random read requires a dummy byte-write sequence to load in the data word address. Once the device-address word and the data-word address are clocked out and acknowledged by the device, the MCU starts a current-address sequence. The following describes the sequence of events to accomplish this transaction. Device Address + EPROM [High Byte] • The MCU clears bit 1 (SRD) within the I2CSTA register. This forces the I2C controller not to generate a stop condition after the contents of the I2CDAI register are received. • The MCU clears bit 0 (SWR) within the I2CSTA register. This forces the I2C controller not to generate a stop condition after the contents of the I2CDAO register are transmitted. • The MCU writes the device address (bit 0 (R/W) = 0) to the I2CADR register (write operation) • The MCU writes the high byte of the EEPROM address into the I2CDAO register (this starts the transfer on the SDA line). • Bit 3 (TXE) in the I2CSTA register is automatically cleared (indicates busy) by writing data to the I2CDAO register. • The contents of the I2CADR register are transmitted to EEPROM (preceded by start condition on SDA). I2C Port SLLS519H—January 2010 TUSB3410, TUSB3410I 59 • The contents of the I2CDAO register are transmitted to EEPROM (EPROM address). • Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register has been transmitted. • A stop condition is not generated. EPROM [Low Byte] • The MCU writes the low byte of the EEPROM address into the I2CDAO register. • Bit 3 (TXE) in the I2CSTA register is automatically cleared (indicates busy) by writing to the I2CDAO register. • The contents of the I2CDAO register are transmitted to the device (EEPROM address). • Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register has been transmitted. • This completes the dummy write operation. At this point, the EEPROM address is set and the MCU can do either a single- or a sequential-read operation. 10.3 Current-Address Read Operation Once the EEPROM address is set, the MCU can read a single byte by executing the following steps: • The MCU sets bit 1 (SRD) in the I2CSTA register to 1. This forces the I2C controller to generate a stop condition after the I2CDAI-register contents are received. • The MCU writes the device address (bit 0 (R/W) = 1) to the I2CADR register (read operation). • The MCU writes a dummy byte to the I2CDAO register (this starts the transfer on SDA line). • Bit 7 (RXF) in the I2CSTA register is cleared (RX is empty). • The contents of the I2CADR register are transmitted to the device (preceded by start condition on SDA). • The data from EEPROM are latched into the I2CDAI register (stop condition is transmitted). • Bit 7 (RXF) in the I2CSTA register is set and interrupts the MCU, indicating that the data are available. • The MCU reads the I2CDAI register. This clears bit 7 (RXF) in the I2CSTA register. 10.4 Sequential-Read Operation Once the EEPROM address is set, the MCU can execute a sequential read operation by executing the following (this example illustrates a 32-byte sequential read): Device Address • The MCU clears bit 1 (SRD) in the I2CSTA register. This forces the I2C controller to not generate a stop condition after the I2CDAI register contents are received. • The MCU writes the device address (bit 0 (R/W) = 1) to the I2CADR register (read operation). • The MCU writes a dummy byte to the I2CDAO register (this starts the transfer on the SDA line). • Bit 7 (RXF) in the I2CSTA register is cleared (RX is empty). • The contents of the I2CADR register are transmitted to the device (preceded by start condition on SDA). I2C Port 60 TUSB3410, TUSB3410I SLLS519H—January 2010 N-Byte Read (31 Bytes) • The data from the device is latched into the I2CDAI register (stop condition is not transmitted). • Bit 7 (RXF) in the I2CSTA register is set and interrupts the MCU, indicating that data is available. • The MCU reads the I2CDAI register. This clears bit 7 (RXF) in the I2CSTA register. • This operation repeats 31 times. Last-Byte Read (Byte 32) • MCU sets bit 1 (SRD) in the I2STA register to 1. This forces the I2C controller to generate a stop condition after the I2CDAI register contents are received. • The data from the device is latched into the I2CDAI register (stop condition is transmitted). • Bit 7 (RXF) in the I2CSTA register is set and interrupts the MCU, indicating that data is available. • The MCU reads the I2CDAI register. This clears bit 7 (RXF) in the I2CSTA register. 10.5 Byte-Write Operation The byte-write operation involves three phases: device address + EPROM [high byte] phase, EPROM [low byte] phase, and EPROM [DATA] phase. The following describes the sequence of events to accomplish the byte-write transaction. Device Address + EPROM [High Byte] • The MCU sets clears the SWR bit in the I2CSTA register. This forces the I2C controller to not generate a stop condition after the contents of the I2CDAO register are transmitted. • The MCU writes the device address (bit 0 (R/W) = 0) to the I2CADR register (write operation). • The MCU writes the high byte of the EEPROM address into the I2CDAO register (this starts the transfer on the SDA line). • Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy). • The contents of the I2CADR register are transmitted to the device (preceded by start condition on SDA). • The contents of the I2CDAO register are transmitted to the device (EEPROM high address). • Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register contents have been transmitted. EPROM [Low Byte] • The MCU writes the low byte of the EEPROM address into the I2CDAO register. • Bit 3 (TXE) in the I2CSTA register is cleared (indicating busy). • The contents of the I2CDAO register are transmitted to the device (EEPROM address). • Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register contents have been transmitted. EPROM [DATA] • The MCU sets bit 0 (SWR) in the I2CSTA register. This forces the I2C controller to generate a stop condition after the contents of the I2CDAO register are transmitted. • The data to be written to the EPROM is written by the MCU into the I2CDAO register. • Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy). • The contents of the I2CDAO register are transmitted to the device (EEPROM data). • Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register contents have been transmitted. • The I2C controller generates a stop condition after the contents of the I2CDAO register are transmitted. I2C Port SLLS519H—January 2010 TUSB3410, TUSB3410I 61 10.6 Page-Write Operation The page-write operation is initiated in the same way as byte write, with the exception that a stop condition is not generated after the first EPROM [DATA] is transmitted. The following describes the sequence of writing 32 bytes in page mode. Device Address + EPROM [High Byte] • The MCU clears bit 0 (SWR) in the I2CSTA register. This forces the I2C controller to not generate a stop condition after the contents of the I2CDAO register are transmitted. • The MCU writes the device address (bit 0 (R/W) = 0) to the I2CADR register (write operation). • The MCU writes the high byte of the EEPROM address into the I2CDAO register • Bit 3 (TXE) in the I2CSTA register is cleared (indicating busy). • The contents of the I2CADR register are transmitted to the device (preceded by start condition on SDA). • The contents of the I2CDAO register are transmitted to the device (EEPROM address). • Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register contents have been transmitted. EPROM [Low Byte] • The MCU writes the low byte of the EEPROM address into the I2CDAO register. • Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy). • The contents of the I2CDAO register are transmitted to the device (EEPROM address). • Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register contents have been transmitted. EPROM [DATA]—31 Bytes • The data to be written to the EEPROM are written by the MCU into the I2CDAO register. • Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy). • The contents of the I2CDAO register are transmitted to the device (EEPROM data). • Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register contents have been transmitted. • This operation repeats 31 times. EPROM [DATA]—Last Byte • The MCU sets bit 0 (SWR) in the I2CSTA register. This forces the I2C controller to generate a stop condition after the contents of the I2CDAO register are transmitted. • The MCU writes the last date byte to be written to the EEPROM, into the I2CDAO register. • Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy). • The contents of the I2CDAO register are transmitted to EEPROM (EEPROM data). • Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register contents have been transmitted. • The I2C controller generates a stop condition after the contents of the I2CDAO register are transmitted. I2C Port 62 TUSB3410, TUSB3410I SLLS519H—January 2010 TUSB3410 Bootcode Flow SLLS519H—January 2010 TUSB3410, TUSB3410I 63 11 TUSB3410 Bootcode Flow 11.1 Introduction TUSB3410 bootcode is a program embedded in the 10k-byte boot ROM within the TUSB3410. This program is designed to load application firmware from either an external I2C memory device or USB host bootloader device driver. After the TUSB3410 finishes downloading, the bootcode releases its control to the application firmware. This section describes how the bootcode initializes the TUSB3410 device in detail. In addition, the default USB descriptor, I2C device header format, USB host driver firmware downloading format, and supported built-in USB vendor specific requests are listed for reference. Users should carefully follow the appropriate format to interface with the bootcode. Unsupported formats may cause unexpected results. The bootcode source code is also provided for programming reference. 11.2 Bootcode Programming Flow After power-on reset, the bootcode initializes the I2C and USB registers along with internal variables. The bootcode then checks to see if an I2C device is present and contains a valid signature. If an I2C device is present and contains a valid signature, the bootcode continues searching for descriptor blocks and then processes them if the checksum is correct. If application firmware was found, then the bootcode downloads it and releases the control to the application firmware. Otherwise, the bootcode connects to the USB and waits for host driver to download application firmware. Once firmware downloading is complete, the bootcode releases the control to the firmware. The following is the bootcode step-by-step operation. • Check if bootcode is in the application mode. This is the mode that is entered after application code is downloaded via either an I2C device or the USB. If the bootcode is in the application mode, then the bootcode releases the control to the application firmware. Otherwise, the bootcode continues. • Initialize all the default settings. − Call CopyDefaultSettings() routine. Set I2C to 400-kHz speed. − Call UsbDataInitialization() routine. Set bFUNADR = 0 Disconnect from USB (bUSBCTL = 0x00) Bootcode handles USB reset Copy predefined device, configuration, and string descriptors to RAM Disable all endpoints and enable USB interrupts (SETUP, RSTR, SUSR, and RESR) • Search for product signature − Check if valid signature is in I2C. If not, skip the I2C process. Read 2 bytes from address 0x0000 with type III and device address 0. Stop searching if valid signature is found. Read 2 bytes from address 0x0000 with type II and device address 4. Stop searching if valid signature is found. • If a valid I2C signature is found, then load the customized device, configuration and string descriptors from I2C EEPROM. − Process each descriptor block from I2C until end of header is found If the descriptor block contains device, configuration, or string descriptors, then the bootcode overwrites the default descriptors. TUSB3410 Bootcode Flow 64 TUSB3410, TUSB3410I SLLS519H—January 2010 If the descriptor block contains binary firmware, then the bootcode sets the header pointer to the beginning of the binary firmware in the I2C EEPROM. If the descriptor block is end of header, then the bootcode stops searching. • Enable global and USB interrupts and set the connection bit to 1. − Enable global interrupts by setting bit 7 (EA) within the SIE register (see Section 9.1.1) to 1. − Enable all internal peripheral interrupts by setting the EX0 bit within the SIE register to 1. − Connect to the USB by setting bit 7 (CONT) within the USBCNTL register (see Section 5.4) to 1. • Wait for any interrupt events until Get DEVICE DESCIPTOR setup packet arrives. − Suspend interrupt The idle bit in the MCU PCON register is set and suspend mode is entered. USB reset wakes up the microcontroller. − Resume interrupt Bootcode wakes up and waits for new USB requests. − Reset interrupt Call UsbReset() routine. − Setup interrupt Bootcode processes the request. − USB reboot request Disconnect from the USB by clearing bit 7 (CONT) in the USBCTL register and restart at address 0x0000. • Download firmware from I2C EEPROM − Disable global interrupts by clearing bit 7 (EA) within the SIE register − Load firmware to XDATA space if available. • Download firmware from the USB. − If no firmware is found in an I2C EEPROM, the USB host downloads firmware via output endpoint 1. − In the first data packet to output endpoint 1, the USB host driver adds 3 bytes before the application firmware in binary format. These three bytes are the LSB and MSB indicating the firmware size and followed by the arithmetic checksum of the binary firmware. • Release control to the application firmware. − Update the USB configuration and interface number. − Release control to application firmware. • Application firmware − Either disconnect from the USB or continue responding to USB requests. 11.3 Default Bootcode Settings The bootcode has its own predefined device, configuration, and string descriptors. These default descriptors should be used in evaluation only. They must not be used in the end-user product. 11.3.1 Device Descriptor The device descriptor provides the USB version that the device supports, device class, protocol, vendor and product identifications, strings, and number of possible configurations. The operation system (Windows, MAC, or Linux) reads this descriptor to decide which device driver should be used to communicate with this device. TUSB3410 Bootcode Flow SLLS519H—January 2010 TUSB3410, TUSB3410I 65 The bootcode uses 0x0451 (Texas Instruments) as the vendor ID and 0x3410 (TUSB3410) as the product ID. It also supports three different strings and one configuration. Table 11−1 lists the device descriptor. Table 11−1. Device Descriptor OFFSET (decimal) FIELD SIZE VALUE DESCRIPTION 0 bLength 1 0x12 Size of this descriptor in bytes 1 bDescriptorType 1 1 Device descriptor type 2 bcdUSB 2 0x0110 USB spec 1.1 4 bDeviceClass 1 0xFF Device class is vendor−specific 5 bDeviceSubClass 1 0 We have no subclasses. 6 bDeviceProtocol 1 0 We use no protocols. 7 bMaxPacketSize0 1 8 Max. packet size for endpoint zero 8 idVendor 2 0x0451 USB−assigned vendor ID = TI 10 idProduct 2 0x3410 TI part number = TUSB3410 12 bcdDevice 2 0x100 Device release number = 1.0 14 iManufacturer 1 1 Index of string descriptor describing manufacturer 15 iProducct 1 2 Index of string descriptor describing product 16 iSerialNumber 1 3 Index of string descriptor describing device’s serial number 17 bNumConfigurations 1 1 Number of possible configurations: 11.3.2 Configuration Descriptor The configuration descriptor provides the number of interfaces supported by this configuration, power configuration, and current consumption. The bootcode declares only one interface running in bus-powered mode. It consumes up to 100 mA at boot time. Table 11−2 lists the configuration descriptor. Table 11−2. Configuration Descriptor OFFSET (decimal) FIELD SIZE VALUE DESCRIPTION 0 bLength 1 9 Size of this descriptor in bytes. 1 bDescriptor Type 1 2 Configuration descriptor type 2 wTotalLength 2 25 = 9 + 9 + 7 Total length of data returned for this configuration. Includes the combined length of all descriptors (configuration, interface, endpoint, and class- or vendor-specific) returned for this configuration. 4 bNumInterfaces 1 1 Number of interfaces supported by this configuration 5 bConfigurationValue 1 1 Value to use as an argument to the SetConfiguration() request to select this configuration. 6 iConfiguration 1 0 Index of string descriptor describing this configuration. 7 bmAttributes 1 0x80 Configuration characteristics D7: Reserved (set to one) D6: Self-powered D5: Remote wakeup is supported D4−0: Reserved (reset to zero) 8 bMaxPower 1 0x32 This device consumes 100 mA. TUSB3410 Bootcode Flow 66 TUSB3410, TUSB3410I SLLS519H—January 2010 11.3.3 Interface Descriptor The interface descriptor provides the number of endpoints supported by this interface as well as interface class, subclass, and protocol. The bootcode supports only one endpoint and use its own class. Table 11−3 lists the interface descriptor. Table 11−3. Interface Descriptor OFFSET (decimal) FIELD SIZE VALUE DESCRIPTION 0 bLength 1 9 Size of this descriptor in bytes 1 bDescriptorType 1 4 Interface descriptor type 2 bInterfaceNumber 1 0 Number of interface. Zero-based value identifying the index in the array of concurrent interfaces supported by this configuration. 3 bAlternateSetting 1 0 Value used to select alternate setting for the interface identified in the prior field 4 bNumEndpoints 1 1 Number of endpoints used by this interface (excluding endpoint zero). If this value is zero, this interface only uses the default control pipe. 5 bInterfaceClass 1 0xFF The interface class is vendor specific. 6 bInterfaceSubClass 1 0 7 bInterfaceProtocol 1 0 8 iInterface 1 0 Index of string descriptor describing this interface 11.3.4 Endpoint Descriptor The endpoint descriptor provides the type and size of communication pipe supported by this endpoint. The bootcode supports only one output endpoint with the size of 64 bytes in addition to control endpoint 0 (required by all USB devices). Table 11−4 lists the endpoint descriptor. Table 11−4. Output Endpoint1 Descriptor OFFSET (decimal) FIELD SIZE VALUE DESCRIPTION 0 bLength 1 7 Size of this descriptor in bytes 1 bDescriptorType 1 5 Endpoint descriptor type 2 bEndpointAddress 1 0x01 Bit 3…0: The endpoint number Bit 7: Direction 0 = OUT endpoint 1 = IN endpoint 3 bmAttributes 1 2 Bit 1…0: Transfer type 10 = Bulk 11 = Interrupt 4 wMaxPacketSize 2 64 Maximum packet size this endpoint is capable of sending or receiving when this configuration is selected. 6 bInterval 1 0 Interval for polling endpoint for data transfers. Expressed in milliseconds. 11.3.5 String Descriptor The string descriptor contains data in the unicode format. It is used to show the manufacturers name, product model, and serial number in human readable format. The bootcode supports three strings. The first string is the manufacturers name. The second string is the product name. The third string is the serial number. Table 11−5 lists the string descriptor. TUSB3410 Bootcode Flow SLLS519H—January 2010 TUSB3410, TUSB3410I 67 Table 11−5. String Descriptor OFFSET (decimal) FIELD SIZE VALUE DESCRIPTION 0 bLength 1 4 Size of string 0 descriptor in bytes 1 bDescriptorType 1 0x03 String descriptor type 2 wLANGID[0] 2 0x0409 English 4 bLength 1 36 (decimal) Size of string 1 descriptor in bytes 5 bDescriptorType 1 0x03 String descriptor type 6 bString 2 ‘T’,0x00 Unicode, T is the first byte 8 2 ‘e’,0x00 Texas Instruments 10 2 ‘x’,0x00 12 2 ‘a’,0x00 14 2 ‘s’,0x00 16 2 ‘ ’,0x00 18 2 ‘I’,0x00 20 2 ‘n’,0x00 22 2 ‘s’,0x00 24 2 ‘t’,0x00 26 2 ‘r’,0x00 28 2 ‘u’,0x00 30 2 ‘m’,0x00 32 2 ‘e’,0x00 34 2 ‘n’,0x00 36 2 ‘t’,0x00 38 2 ‘s’,0x00 40 bLength 1 42 (decimal) Size of string 2 descriptor in bytes 41 bDescriptorType 1 0x03 STRING descriptor type 42 bString 2 ‘T’,0x00 UNICODE, T is first byte 44 2 ‘U’,0x00 TUSB3410 boot device 46 2 ‘S’,0x00 48 2 ‘B’,0x00 50 2 ‘3’,0x00 52 2 ‘4’,0x00 54 2 ‘1’,0x00 56 2 ‘0’,0x00 58 2 ‘ ‘,0x00 60 2 ‘B‘,0x00 62 2 ‘o’,0x00 64 2 ‘o’,0x00 66 2 ‘t’,0x00 TUSB3410 Bootcode Flow 68 TUSB3410, TUSB3410I SLLS519H—January 2010 Table 11−5. String Descriptor (Continued) OFFSET FIELD SIZE VALUE DESCRIPTION 68 2 ‘ ’,0x00 70 2 ‘D’,0x00 72 2 ‘e‘,0x00 74 2 ‘v’,0x00 76 2 ‘I,0x00 78 2 ‘c’,0x00 80 2 ‘e’,0x00 82 bLength 1 34 (decimal) Size of string 3 descriptor in bytes 84 bDescriptorType 1 0x03 STRING descriptor type 86 bString 2 r0,0x00 UNICODE 88 2 r1,0x00 R0 to rF are BCD of SERNUM0 to 90 2 r2,0x00 SERNUM7 registers. 16 digit hex 92 2 r3,0x00 16 digit hex numbers are created from 94 2 r4,0x00 SERNUM0 to SERNUM7 registers 96 2 r5,0x00 98 2 r6,0x00 100 2 r7,0x00 102 2 r8,0x00 104 2 r9,0x00 106 2 rA,0x00 108 2 rB,0x00 110 2 rC,0x00 112 2 rD,0x00 114 2 rE,0x00 116 2 rF,0x00 11.4 External I2C Device Header Format A valid header should contain a product signature and one or more descriptor blocks. The descriptor block contains the descriptor prefix and content. In the descriptor prefix, the data type, size, and checksum are specified to describe the content. The descriptor content contains the necessary information for the bootcode to process. The header processing routine always counts from the first descriptor block until the desired block number is reached. The header reads in the descriptor prefix with a size of 4 bytes. This prefix contains the type of block, size, and checksum. For example, if the bootcode would like to find the position of the third descriptor block, then it reads in the first descriptor prefix, calculates the position on the second descriptor prefix based on the size specified in the prefix. bootcode, then repeats the same calculation to find out the position of the third descriptor block. 11.4.1 Product Signature The product signature must be stored at the first 2 bytes within the I2C storage device. These 2 bytes must match the product number. The order of these 2 bytes must be the LSB first followed by the MSB. For example, the TUSB3410 is 0x3410. Therefore, the first byte must be 0x10 and the second byte must be 0x34. The TUSB3410 bootcode searches the first 2 bytes of the I2C device. If the first 2 bytes are not 0x10 and 0x34, then the bootcode skips the header processing. TUSB3410 Bootcode Flow SLLS519H—January 2010 TUSB3410, TUSB3410I 69 11.4.2 Descriptor Block Each descriptor block contains a prefix and content. The size of the prefix is always 4 bytes. It contains the data type, size, and checksum for data integrity. The descriptor content contains the corresponding information specified in the prefix. It could be as small as 1 byte or as large as 65535 bytes. The next descriptor immediately follows the previous descriptor. If there are no more descriptors, then an extra byte with a value of zero should be added to indicate the end of header. 11.4.2.1 Descriptor Prefix The first byte of the descriptor prefix is the data type. This tells the bootcode how to process the data in the descriptor content. The second and third bytes are the size of descriptor content. The second byte is the low byte of the size and the third byte is the high byte. The last byte is the 8-bit arithmetic checksum of descriptor content. 11.4.2.2 Descriptor Content Information stored in the descriptor content can be the USB information, firmware, or other type of data. The size of the content should be from 1 byte to 65535 bytes. 11.5 Checksum in Descriptor Block Each descriptor prefix contains one checksum of the descriptor content. If the checksum is wrong, the bootcode simply ignores the descriptor block. 11.6 Header Examples The header can be specified in different ways. The following descriptors show examples of the header format and the supported descriptor block. 11.6.1 TUSB3410 Bootcode Supported Descriptor Block The TUSB3410 bootcode supports the following descriptor blocks. • USB Device Descriptor • USB Configuration Descriptor • USB String Descriptor • Binary Firmware1 • Autoexec Binary Firmware2 11.6.2 USB Descriptor Header Table 11−6 contains the USB device, configuration, and string descriptors for the bootcode. The last byte is zero to indicate the end of header. 1 Binary firmware is loaded when the bootcode receives the first get device descriptor request from host. Downloading the firmware should either continue that request in the data stage or disconnect from the USB and then reconnect to the USB as a new device. 2 The bootcode loads this autoexec binary firmware before it connects to the USB. The firmware should connect to the USB once it is loaded. TUSB3410 Bootcode Flow 70 TUSB3410, TUSB3410I SLLS519H—January 2010 Table 11−6. USB Descriptors Header OFFSET TYPE SIZE VALUE DESCRIPTION 0 Signature0 1 0x10 FUNCTION_PID_L 1 Signature1 1 0x34 FUNCTION_PID_H 2 Data Type 1 0x03 USB device descriptor 3 Data Size (low byte) 1 0x12 The device descriptor is 18 (decimal) bytes. 4 Data Size (high byte) 1 0x00 5 Check Sum 1 0xCC Checksum of data below 6 bLength 1 0x12 Size of device descriptor in bytes 7 bDescriptorType 1 0x01 Device descriptor type 8 bcdUSB 2 0x0110 USB spec 1.1 10 bDeviceClass 1 0xFF Device class is vendor-specific 11 bDeviceSubClass 1 0x00 We have no subclasses. 12 bDeviceProtocol 1 0x00 We use no protocols 13 bMaxPacketSize0 1 0x08 Maximum packet size for endpoint zero 14 idVendor 2 0x0451 USB−assigned vendor ID = TI 16 idProduct 2 0x3410 TI part number = TUSB3410 18 bcdDevice 2 0x0100 Device release number = 1.0 20 iManufacturer 1 0x01 Index of string descriptor describing manufacturer 21 iProducct 1 0x02 Index of string descriptor describing product 22 iSerialNumber 1 0x03 Index of string descriptor describing device’s serial number 23 bNumConfigurations 1 0x01 Number of possible configurations: 24 Data Type 1 0x04 USB configuration descriptor 25 Data Size (low byte) 1 0x19 25 bytes 26 Data Size (high byte) 1 0x00 27 Check Sum 1 0xC6 Checksum of data below 28 bLength 1 0x09 Size of this descriptor in bytes 29 bDescriptorType 1 0x02 CONFIGURATION descriptor type 30 wTotalLength 2 25(0x19) = 9 + 9 + 7 Total length of data returned for this configuration. Includes the combined length of all descriptors (configuration, interface, endpoint, and class- or vendor-specific) returned for this configuration. 32 bNumInterfaces 1 0x01 Number of interfaces supported by this configuration 33 bConfigurationValue 1 0x01 Value to use as an argument to the SetConfiguration() request to select this configuration 34 iConfiguration 1 0x00 Index of string descriptor describing this configuration. 35 bmAttributes 1 0xE0 Configuration characteristics D7: Reserved (set to one) D6: Self-powered D5: Remote wakeup is supported D4−0: Reserved (reset to zero) 36 bMaxPower 1 0x64 This device consumes 100 mA. 37 bLength 1 0x09 Size of this descriptor in bytes 38 bDescriptorType 1 0x04 INTERFACE descriptor type 39 bInterfaceNumber 1 0x00 Number of interface. Zero-based value identifying the index in the array of concurrent interfaces supported by this configuration. TUSB3410 Bootcode Flow SLLS519H—January 2010 TUSB3410, TUSB3410I 71 Table 11−6. USB Descriptors Header (Continued) OFFSET TYPE SIZE VALUE DESCRIPTION 40 bAlternateSetting 1 0x00 Value used to select alternate setting for the interface identified in the prior field 41 bNumEndpoints 1 0x01 Number of endpoints used by this interface (excluding endpoint zero). If this value is zero, this interface only uses the default control pipe. 42 bInterfaceClass 1 0xFF The interface class is vendor specific. 43 bInterfaceSubClass 1 0x00 44 bInterfaceProtocol 1 0x00 45 iInterface 1 0x00 Index of string descriptor describing this interface 46 bLength 1 0x07 Size of this descriptor in bytes 47 bDescriptorType 1 0x05 ENDPOINT descriptor type 48 bEndpointAddress 1 0x01 Bit 3…0: The endpoint number Bit 7: Direction 0 = OUT endpoint 1 = IN endpoint 49 bmAttributes 1 0x02 Bit 1…0: Transfer Type 10 = Bulk 11 = Interrupt 50 wMaxPacketSize 2 0x0040 Maximum packet size this endpoint is capable of sending or receiving when this configuration is selected. 52 bInterval 1 0x00 Interval for polling endpoint for data transfers. Expressed in milliseconds. 53 Data Type 1 0x05 USB String descriptor 54 Data Size (low byte) 1 0x1A 26(0x1A) = 4 + 6 + 6 + 10 55 Data Size (high byte) 1 0x00 56 Check Sum 1 0x50 Checksum of data below 57 bLength 1 0x04 Size of string 0 descriptor in bytes 58 bDescriptorType 1 0x03 STRING descriptor type 59 wLANGID[0] 2 0x0409 English 61 bLength 1 0x06 Size of string 1 descriptor in bytes 62 bDescriptorType 1 0x03 STRING descriptor type 63 bString 2 ‘T’,0x00 UNICODE, ‘T’ is the first byte. 65 2 ‘I’,0x00 TI = 0x54, 0x49 67 bLength 1 0x06 Size of string 2 descriptor in bytes 68 bDescriptorType 1 0x03 STRING descriptor type 69 bString 2 ‘u’,0x00 UNICODE, ‘u’ is the first byte. 71 2 ‘C’,0x00 ‘uC’ = 0x75, 0x43 73 bLength 1 0x0A Size of string 3 descriptor in bytes 74 bDescriptorType 1 0x03 STRING descriptor type 75 bString 2 ‘3’,0x00 UNICODE, ‘T’ is the first byte. 77 2 ‘4’,0x00 ‘3410’ = 0x33, 0x34, 0x31, 0x30 79 2 ‘1’,0x00 81 2 ‘0’,0x00 83 Data Type 1 0x00 End of header 11.6.3 Autoexec Binary Firmware If the application requires firmware loaded prior to establishing a USB connection, then the following header can be used. The bootcode loads the firmware and releases control to the firmware directly without connecting to the USB. However, per the USB specification requirement, any USB device should connect to the bus and respond to the host within the first 100 ms. Therefore, if downloading time is more than 100 ms, the USB and header speed descriptor blocks should be added before the autoexec binary firmware. Table 11−7 shows an example of autoexec binary firmware header. TUSB3410 Bootcode Flow 72 TUSB3410, TUSB3410I SLLS519H—January 2010 Table 11−7. Autoexec Binary Firmware OFFSET TYPE SIZE VALUE DESCRIPTION 0x0000 Signature0 1 0x10 FUNCTION_PID_L 0x0001 Signature1 1 0x34 FUNCTION_PID_H 0x0002 Data Type 1 0x07 Autoexec binary firmware 0x0003 Data Size (low byte) 1 0x67 0x4567 bytes of application code 0x0004 Data Size (high byte) 1 0x45 0x0005 Check Sum 1 0xNN Checksum of the following firmware 0x0006 Program 0x4567 Binary application code 0x456d Data Type 1 0x00 End of header 11.7 USB Host Driver Downloading Header Format If firmware downloading from the USB host driver is desired, then the USB host driver must follow the format in Table 11−8. The Texas Instruments bootloader driver generates the proper format. Therefore, users only need to provide the binary image of the application firmware for the Bootloader. If the checksum is wrong, then the bootcode disconnects from the USB and waits before it reconnects to the USB. Table 11−8. Host Driver Downloading Format OFFSET TYPE SIZE VALUE DESCRIPTION 0x0000 Firmware size (low byte) 1 0xXX Application firmware size 0x0001 Firmware size (low byte) 1 0xYY 0x0002 Checksum 1 0xZZ Checksum of binary application code 0x0003 Program 0xYYXX Binary application code 11.8 Built-In Vendor Specific USB Requests The bootcode supports several vendor specific USB requests. These requests are primarily for internal testing only. These functions should not be used in normal operation. 11.8.1 Reboot The reboot command forces the bootcode to execute. bmRequestType USB_REQ_TYPE_DEVICE | USB_REQ_TYPE_VENDOR | USB_REQ_TYPE_OUT 01000000b bRequest BTC_REBOOT 0x85 wValue None 0x0000 wIndex None 0x0000 wLength None 0x0000 Data None 11.8.2 Force Execute Firmware The force execute firmware command requests the bootcode to execute the downloaded firmware unconditionally. bmRequestType USB_REQ_TYPE_DEVICE | USB_REQ_TYPE_VENDOR | USB_REQ_TYPE_OUT 01000000b bRequest BTC_FORCE_EXECUTE_FIRMWARE 0x8F wValue None 0x0000 wIndex None 0x0000 wLength None 0x0000 Data None TUSB3410 Bootcode Flow SLLS519H—January 2010 TUSB3410, TUSB3410I 73 11.8.3 External Memory Read The bootcode returns the content of the specified address. bmRequestType USB_REQ_TYPE_DEVICE | USB_REQ_TYPE_VENDOR | USB_REQ_TYPE_IN 11000000b bRequest BTC_EXETERNAL_MEMORY_READ 0x90 wValue None 0x0000 wIndex Data address 0xNNNN (From 0x0000 to 0xFFFF) wLength 1 byte 0x0001 Data Byte in the specified address 0xNN 11.8.4 External Memory Write The external memory write command tells the bootcode to write data to the specified address. bmRequestType USB_REQ_TYPE_DEVICE | USB_REQ_TYPE_VENDOR | USB_REQ_TYPE_OUT 01000000b bRequest BTC_EXETERNAL_MEMORY_WRITE 0x91 wValue HI: 0x00 LO: Data 0x00NN wIndex Data address 0xNNNN (From 0x0000 to 0xFFFF) wLength None 0x0000 Data None 11.8.5 I2C Memory Read The bootcode returns the content of the specified address in I2C EEPROM. In the wValue field, the I2C device number is from 0x00 to 0x07 in the high byte. The memory type is from 0x01 to 0x03 for CAT I to CAT III devices. If bit 7 of bValueL is set, then the bus speed is 400 kHz. This request is also used to set the device number and speed before the I2C write request. bmRequestType USB_REQ_TYPE_DEVICE | USB_REQ_TYPE_VENDOR | USB_REQ_TYPE_IN 11000000b bRequest BTC_I2C_MEMORY_READ 0x92 wValue HI: I2C device number LO: Memory type bit[1:0] Speed bit[7] 0xXXYY wIndex Data address 0xNNNN (From 0x0000 to 0xFFFF) wLength 1 byte 0x0001 Data Byte in the specified address 0xNN 11.8.6 I2C Memory Write The I2C memory write command tells the bootcode to write data to the specified address. bmRequestType USB_REQ_TYPE_DEVICE | USB_REQ_TYPE_VENDOR | USB_REQ_TYPE_OUT 01000000b bRequest BTC_I2C_MEMORY_WRITE 0x93 wValue HI: should be zero LO: Data 0x00NN wIndex Data address 0xNNNN (From 0x0000 to 0xFFFF) wLength None 0x0000 Data None TUSB3410 Bootcode Flow 74 TUSB3410, TUSB3410I SLLS519H—January 2010 11.8.7 Internal ROM Memory Read The bootcode returns the byte of the specified address within the boot ROM. That is, the binary code of the bootcode. bmRequestType USB_REQ_TYPE_DEVICE | USB_REQ_TYPE_VENDOR | USB_REQ_TYPE_OUT 01000000b bRequest BTC_INTERNAL_ROM_MEMORY_READ 0x94 wValue None 0x0000 wIndex Data address 0xNNNN (From 0x0000 to 0xFFFF) wLength 1 byte 0x0001 Data Byte in the specified address 0xNN 11.9 Bootcode Programming Consideration 11.9.1 USB Requests For each USB request, the bootcode follows the steps below to ensure proper operation of the hardware. 1. Determine the direction of the request by checking the MSB of the bmRequestType field and set the DIR bit within the USBCTL register accordingly. 2. Decode the command 3. If another setup is pending, then return. Otherwise, serve the request. 4. Check again, if another setup is pending then go to step 2. 5. Clear the interrupt source and then the VECINT register. 6. Exit the interrupt routine. 11.9.1.1 USB Request Transfers The USB request consist of three types of transfers. They are control-read-with-data-stage, control-writewithout- data-stage, and control-write-with-data-stage transfer. In each transfer, arrows indicate interrupts generated after receiving the setup packet, in or out token. Figure 11−1 and Figure 11−2 show the USB data flow and how the hardware and firmware respond to the USB requests. Table 11−9 and Table 11−10 lists the bootcode reposes to the standard USB requests. TUSB3410 Bootcode Flow SLLS519H—January 2010 TUSB3410, TUSB3410I 75 Setup (0) IN(1) IN(0) IN(0/1) OUT(1) INT INT INT INT More Packets Setup Stage Data Stage StatusStage 1.Hardware generates interrupt to MCU. 2.Hardware sets NAK on both the IN and the OUT endpoints. 3.Set DIR bit in USBCTL to indicate the data direction. 4.Decode the setup packet. 5.If another setup packet arrives, abandon this one. 6.Execute appropriate routine per a) Clear NAK bit in OUT endpoint. b) Copy data to IN endpoint buffer and set byte count. 1.Hardware generates interrupt to MCU. 2.Copy data to IN buffer. 3.Clear the NAK bit. 4.If all data has been sent, stall input endpoint. 1.Hardware does NOT generate interrupt to MCU. Table 11-9. Figure 11−1. Control Read Transfer Table 11−9. Bootcode Response to Control Read Transfer CONTROL READ ACTION IN BOOTCODE Get status of device Return power and remote wakeup settings Get status of interface Return 2 bytes of zeros Get status of endpoint Return endpoint status Get descriptor of device Return device descriptor Get descriptor of configuration Return configuration descriptor Get descriptor of string Return string descriptor Get descriptor of interface Stall Get descriptor of endpoint Stall Get configuration Return bConfiguredNumber value Get interface Return bInterfaceNumber value TUSB3410 Bootcode Flow 76 TUSB3410, TUSB3410I SLLS519H—January 2010 Setup (0) IN(1) INT Setup Stage Status Stage 1.Hardware generates interrupt to MCU. 2.Hardware sets NAK on both the IN and the OUT endpoints. 3.Set DIR bit in USBCTL to indicate the data direction. 4.Decode the setup packet. 5.If another setup packet arrives, abandon this one. 6.Execute appropriate routine per 1.Hardware does NOT generates interrupt to MCU. Table 11−10. Figure 11−2. Control Write Transfer Without Data Stage Table 11−10. Bootcode Response to Control Write Without Data Stage CONTROL WRITE WITHOUT DATA STAGE ACTION IN BOOTCODE Clear feature of device Stall Clear feature of interface Stall Clear feature of endpoint Clear endpoint stall Set feature of device Stall Set feature of interface Stall Set feature of endpoint Stall endpoint Set address Set device address Set descriptor Stall Set configuration Set bConfiguredNumber Set interface SetbInterfaceNumber Sync. frame Stall 11.9.1.2 Interrupt Handling Routine The higher-vector number has a higher priority than the lower-vector number. Table 11−11 lists all the interrupts and source of interrupts. TUSB3410 Bootcode Flow SLLS519H—January 2010 TUSB3410, TUSB3410I 77 Table 11−11. Vector Interrupt Values and Sources G[3:0] (Hex) I[2:0] (Hex) VECTOR (Hex) INTERRUPT SOURCE INTERRUPT SOURCE SHOULD BE CLEARED 0 0 00 No Interrupt No Source 1 1 12 Output−endpoint−1 VECINT register 1 2 14 Output−endpoint−2 VECINT register 1 3 16 Output−endpoint−3 VECINT register 1 4−7 18→1E Reserved 2 1 22 Input−endpoint−1 VECINT register 2 2 24 Input−endpoint−2 VECINT register 2 3 26 Input−endpoint−3 VECINT register 2 4−7 28→2E Reserved 3 0 30 STPOW packet received USBSTA/ VECINT registers 3 1 32 SETUP packet received USBSTA/ VECINT registers 3 2 34 Reserved 3 3 36 Reserved 3 4 38 RESR interrupt USBSTA/ VECINT registers 3 5 3A SUSR interrupt USBSTA/ VECINT registers 3 6 3C RSTR interrupt USBSTA/ VECINT registers 3 7 3E Wakeup interrupt USBSTA/ VECINT registers 4 0 40 I2C TXE interrupt VECINT register 4 1 42 I2C TXE interrupt VECINT register 4 2 44 Input−endpoint−0 VECINT register 4 3 46 Output−endpoint−0 VECINT register 4 4−7 48→4E Reserved 5 0 50 UART1 status interrupt LSR/VECNT register 5 1 52 UART1 modern interrupt LSR/VECINT register 5 2−7 54→5E Reserved 6 0 60 UART1 RXF interrupt LSR/VECNT register 6 1 62 UART1 TXE interrupt LSR/VECINT register 6 2−7 64→6E Reserved 7 0−7 70→7E Reserved 8 0 80 DMA1 interrupt DMACSR/VECINT register 8 1 82 Reserved 8 2 84 DMA3 interrupt DMACSR/VECINT register 8 3−7 86→7E Reserved 9−15 0−7 90→FE Reserved 11.9.2 Hardware Reset Introduced by the Firmware This feature can be used during a firmware upgrade. Once the upgrade is complete, the application firmware disconnects from the USB for at least 200 ms to ensure the operating system has unloaded the device driver. The firmware then enables the watchdog timer (enabled by default after power-on reset) and enters an endless loop without resetting the watchdog timer. Once the watchdog timer times out, it resets the TUSB3410 similar to a power on reset. The bootcode takes control and executes the power-on boot sequence. TUSB3410 Bootcode Flow 78 TUSB3410, TUSB3410I SLLS519H—January 2010 11.10 File Listings The TUSB3410 Bootcode Source Listing (SLLC139.zip) is available under the TUSB3410 product page on the TI website. Look under the Related Software link. The files listed below are included in the zip file. • Types.h • USB.h • TUSB3410.h • Bootcode.h • Watchdog.h • Bootcode.c • Bootlsr.c • BootUSB.c • Header.h • Header.c • I2c.h • I2c.c Electrical Specifications SLLS519H—January 2010 TUSB3410, TUSB3410I 79 12 Electrical Specifications 12.1 Absolute Maximum Ratings† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 12.2 Commercial Operating Condition (3.3 V) PARAMETER MIN TYP MAX UNIT VCC Supply voltage 3 3.3 3.6 V VI Input voltage 0 VCC V V High level input voltage TTL 2 VCC VIH High-V CMOS 0.7 × VCC VCC V Low level input voltage TTL 0 0.8 VIL Low-V CMOS 0 0.2 × VCC T Operating temperature Commercial range 0 70 °C TA Industrial range −40 85 °C 12.3 Electrical Characteristics TA = 25°C, VCC = 3.3 V ±5%, VSS = 0 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V High level output voltage TTL I 4 mA VCC – 0.5 VOH High-V CMOS IOH = −VCC – 0.5 V Low level output voltage TTL I 4 mA 0.5 VOL Low-V CMOS IOL = 0.5 V Positive threshold voltage TTL V V 1.8 VIT+ V CMOS VI = VIH 0.7 × VCC V Negative threshold voltage TTL V V 0.8 1.8 VIT− V CMOS VI = VIH 0.2 × VCC V Hysteresis (V V ) TTL V V 0.3 0.7 Vhys VIT+ − VIT−) V CMOS VI = VIH 0.17 × VCC 0.3 × VCC I High level input current TTL V V ±20 IIH High-A CMOS VI = VIH ±1 μA I Low level input current TTL V V ±20 IIL Low-A CMOS VI = VIL ±1 μA IOZ Output leakage current (Hi-Z) VI = VCC or VSS ±20 μA IOL Output low drive current 0.1 mA IOH Output high drive current 0.1 mA I Supply current (operating) Serial data at 921.6 k 15 mA ICC Supply current (suspended) 200 μA Electrical Specifications 80 TUSB3410, TUSB3410I SLLS519H—January 2010 Electrical Characteristics (continued) TA = 25°C, VCC = 3.3 V ±5%, VSS = 0 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Clock duty cycle‡ 50% Jitter specification‡ ±100 ppm CI Input capacitance 18 pF CO Output capacitance 10 pF ‡ Applies to all clock outputs Application Notes SLLS519H—January 2010 TUSB3410, TUSB3410I 81 13 Application Notes 13.1 Crystal Selection The TUSB3410 requires a 12-MHz clock source to work properly. This clock source can be a crystal placed across the X1 and X2 terminals. A parallel resonant crystal is recommended. Most parallel resonant crystals are specified at a frequency with a load capacitance of 18 pF. This load can be realized by placing 33-pF capacitors from each end of the crystal to ground. Together with the input capacitance of the TUSB3410 and stray board capacitance, this provides close to two 36-pF capacitors in series to emulate the 18-pF load requirement. Note, that when using a crystal, it takes about 2 ms after power up for a stable clock to be produced. When using a clock oscillator, the signal applied to the X1/CLKI terminal must not exceed 1.8 V. In this configuration, the X2 terminal is unconnected. TUSB3410 X1/CLKI 33 pF 12 MHz X2 33 pF Figure 13−1. Crystal Selection 13.2 External Circuit Required for Reliable Bus Powered Suspend Operation TI has found a potential problem with the action of the SUSPEND output terminal immediately after power on. In some cases the SUSPEND terminal can power up asserted high. When used in a bus powered application this can cause a problem because the VREGEN input is usually connected to the SUSPEND output. This in turn causes the internal 1.8-V voltage regulator to shut down, which means an external crystal may not have time to begin oscillating, thus the device will not initialize itself correctly. TI has determined that using components R2 and D1 (rated to 25 mA) in the circuit shown below can be used as a workaround. Note that R1 and C1 are required components for proper reset operation, unless the reset signal is provided by another means. Note that use of an external oscillator (1.8-V output) versus a crystal would avoid this situation. Self-powered applications would probably not see this problem because the VREGEN input would likely be tied low, enabling the internal 1.8-V regulator at all times. TUSB3410 SUSPEND D1 VREGEN RESET R2 32 kΩ C1 1 μF 3.3 V R1 15 kΩ Figure 13−2. External Circuit Application Notes 82 TUSB3410, TUSB3410I SLLS519H—January 2010 13.3 Wakeup Timing (WAKEUP or RI/CP Transitions) The TUSB3410 can be brought out of the suspended state, or woken up, by a command from the host. The TUSB3410 also supports remote wakeup and can be awakened by either of two input signals. A low pulse on the WAKEUP terminal or a low-to-high transition on the RI/CP terminal wakes the device up. Note that for reliable operation, either condition must persist for approximately 3 ms minimum. This allows time for the crystal to power up since in the suspend mode the crystal interface is powered down. The state of the WAKEUP or RI/CP terminal is then sampled by the clock to verify there was a valid wakeup event. 13.4 Reset Timing There are three requirements for the reset signal timing. First, the minimum reset pulse duration is 100 μs. At power up, this time is measured from the time the power ramps up to 90% of the nominal VCC until the reset signal exceeds 1.2 V. The second requirement is that the clock must be valid during the last 60 μs of the reset window. The third requirement is that, according to the USB specification, the device must be ready to respond to the host within 100 ms. This means that within the 100-ms window, the device must come out of reset, load any pertinent data from the I2C EEPROM device, and transfer execution to the application firmware if any is present. Because the latter two events can require significant time, the amount of which can change from system to system, TI recommends having the device come out of reset within 30 ms, leaving 70 ms for the other events to complete. This means the reset signal must rise to 1.8 V within 30 ms. These requirements are depicted in Figure 13−3. Notice that when using a 12-MHz crystal, the clock signal may take several milliseconds to ramp up and become valid after power up. Therefore, the reset window may need to be elongated up to 10 ms or more to ensure that there is a 60-μs overlap with a valid clock. CLK RESET t VCC 90% 3.3 V 1.2 V 0 V >60 μs 100 μs < RESET TIME 1.8 V RESET TIME < 30 ms Figure 13−3. Reset Timing PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TUSB3410IRHB ACTIVE VQFN RHB 32 73 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 3410I TUSB3410IRHBG4 ACTIVE VQFN RHB 32 73 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 3410I TUSB3410IRHBR ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 3410I TUSB3410IRHBRG4 ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 3410I TUSB3410IRHBT ACTIVE VQFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 3410I TUSB3410IVF ACTIVE LQFP VF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TUSB3410I TUSB3410IVFG4 ACTIVE LQFP VF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TUSB3410I TUSB3410RHB ACTIVE VQFN RHB 32 73 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 3410 TUSB3410RHBG4 ACTIVE VQFN RHB 32 73 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 3410 TUSB3410RHBR ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 3410 TUSB3410RHBRG4 ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 3410 TUSB3410RHBT ACTIVE VQFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 3410 TUSB3410VF ACTIVE LQFP VF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TUSB3410 TUSB3410VFG4 ACTIVE LQFP VF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TUSB3410 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2014 Addendum-Page 2 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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OTHER QUALIFIED VERSIONS OF TUSB3410 : • Automotive: TUSB3410-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TUSB3410IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TUSB3410IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TUSB3410RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TUSB3410RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TUSB3410IRHBR VQFN RHB 32 3000 338.1 338.1 20.6 TUSB3410IRHBT VQFN RHB 32 250 210.0 185.0 35.0 TUSB3410RHBR VQFN RHB 32 3000 338.1 338.1 20.6 TUSB3410RHBT VQFN RHB 32 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 Pack Materials-Page 2 MECHANICAL DATA MTQF002B – JANUARY 1995 – REVISED MAY 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 VF (S-PQFP-G32) PLASTIC QUAD FLATPACK 4040172/D 04/00 Gage Plane Seating Plane 1,60 MAX 1,45 1,35 8,80 9,20 SQ 0,05 MIN 0,45 0,75 0,25 0,13 NOM 5,60 TYP 1 32 7,20 6,80 24 25 SQ 8 9 17 16 0,25 0,45 0,10 0°–7° 0,80 0,20 M NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated DB OR PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 EN C1+ V+ C1− C2+ C2− V− RIN FORCEOFF VCC GND DOUT FORCEON DIN INVALID ROUT MAX3221 www.ti.com SLLS348N –JUNE 1999–REVISED JANUARY 2014 MAX3221 3-V to 5.5-V Multichannel RS-232 Line Driver/Receiver With ±15-kV ESD Protection Check for Samples: MAX3221 1FEATURES DESCRIPTION • RS-232 Bus-Pin ESD Protection Exceeds The MAX3221 device consists of one line driver, one ±15 kV Using Human-Body Model (HBM) line receiver, and a dual charge-pump circuit with ±15-kV ESD protection pin to pin (serial-port • Meets or Exceeds the Requirements of connection pins, including GND). The device meets TIA/EIA-232-F and ITU V.28 Standards the requirements of TIA/EIA-232-F and provides the • Operates With 3-V to 5.5-V VCC Supply electrical interface between an asynchronous • Operates Up To 250 kbit/s communication controller and the serial-port connector. The charge pump and four small external • One Driver and One Receiver capacitors allow operation from a single 3-V to 5.5-V • Low Standby Current: 1 μA Typical supply. These devices operate at data signaling rates • External Capacitors: 4 × 0.1 μF up to 250 kbit/s and a maximum of 30-V/μs driver output slew rate. • Accepts 5-V Logic Input With 3.3-V Supply • Alternative High-Speed Pin-Compatible Flexible control options for power management are Device (1 Mbit/s) available when the serial port is inactive. The auto- powerdown feature functions when FORCEON is low – SNx5C3221 and FORCEOFF is high. During this mode of • Auto-Powerdown Feature Automatically operation, if the device does not sense a valid RS- Disables Drivers for Power Savings 232 signal on the receiver input, the driver output is disabled. If FORCEOFF is set low and EN is high, APPLICATIONS both the driver and receiver are shut off, and the supply current is reduced to 1 μA. Disconnecting the • Battery-Powered, Hand-Held, and Portable serial port or turning off the peripheral drivers causes Equipment the auto-powerdown condition to occur. Auto• PDAs and Palmtop PCs powerdown can be disabled when FORCEON and • Notebooks, Subnotebooks, and Laptops FORCEOFF are high. With auto-powerdown enabled, the device is activated automatically when a valid • Digital Cameras signal is applied to the receiver input. The INVALID • Mobile Phones and Wireless Devices output notifies the user if an RS-232 signal is present at the receiver input. INVALID is high (valid data) if the receiver input voltage is greater than 2.7 V or less than −2.7 V, or has been between −0.3 V and 0.3 V for less than 30 μs. INVALID is low (invalid data) if the receiver input voltage is between −0.3 V and 0.3 V for more than 30 μs. Refer to Figure 5 for receiver input levels. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1999–2014, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. DIN DOUT Auto-powerdown INVALID RIN FORCEOFF FORCEON ROUT EN 11 16 9 13 10 8 1 12 MAX3221 SLLS348N –JUNE 1999–REVISED JANUARY 2014 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Function Tables xxx Each Driver(1) INPUTS DIN FORCEON FORCEOFF VALID RIN RS-232 OUPUT DOUT DRIVER STATUS LEVEL X X L X Z Powered off L H H X H Normal operation H H H X L with auto-powerdown disabled L L H Yes H Normal operation H L H Yes L with auto-powerdown enabled L L H No Z Powered off by autoH L H No Z powerdown feature (1) H = high level, L = low level, X = irrelevant, Z = high impedance Each Receiver(1) INPUTS OUTPUT ROUT RIN EN VALID RIN RS-232 LEVEL L L X H H L X L X H X Z Open L No H (1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), Open = disconnected input or connected driver off Logic Diagram (Positive Logic) 2 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links :MAX3221 MAX3221 www.ti.com SLLS348N –JUNE 1999–REVISED JANUARY 2014 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage range(2) –0.3 6 V V+ Positive output supply voltage range(2) –0.3 7 V V– Negative output supply voltage range(2) 0.3 –7 V V+ – V– Supply voltage difference(2) 13 V Driver (FORCEOFF, FORCEON, EN) –0.3 6 VI Input voltage range V Receiver –25 25 Driver –13.2 13.2 VO Output voltage range V Receiver (INVALID) –0.3 VCC + 0.3 DB package 82 θJA Package thermal impedance(3) (4) °C/W PW package 108 TJ Operating virtual junction temperature 150 °C Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to network GND. (3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. (4) The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (see Figure 6)(1) MIN NOM MAX UNIT VCC = 3.3 V 3 3.3 3.6 Supply voltage V VCC = 5 V 4.5 5 5.5 DIN, FORCEOFF, VCC = 3.3 V 2 VIH Driver high-level input voltage FORCEON, EN V VCC = 5 V 2.4 V DIN, FORCEOFF, IL Driver low-level input voltage FORCEON, EN 0.8 V Driver input voltage DIN, FORCEOFF, 0 5.5 VI FORCEON, EN V Receiver input voltage –25 25 MAX3221C 0 70 TA Operating free-air temperature °C MAX3221I –40 85 (1) Test conditions are C1−C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2−C4 = 0.33 μF at VCC = 5 V ± 0.5 V. Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links :MAX3221 MAX3221 SLLS348N –JUNE 1999–REVISED JANUARY 2014 www.ti.com Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (see Figure 6) PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT I FORCEOFF, FORCEON, I Input leakage current EN ±0.01 ±1 μA Auto-powerdown No load, FORCEOFF and 0.3 1 mA disabled FORCEON at VCC I Powered off No load, FORCEOFF at GND 1 10 CC Supply current No load, VCC = 3.3 V to 5 V No load, FORCEOFF at VCC, μA Auto-powerdown enabled FORCEON at GND, 1 10 All RIN are open or grounded (1) Test conditions are C1−C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2−C4 = 0.33 μF at VCC = 5 V ± 0.5 V. (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. Driver Section Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (see Figure 6) PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT VOH High-level output voltage DOUT at RL = 3 kΩ to GND, DIN = GND 5 5.4 V VOL Low-level output voltage DOUT at RL = 3 kΩ to GND, DIN = VCC –5 –5.4 V IIH High-level input current VI = VCC ±0.01 ±1 μA IIL Low-level input current VI at GND ±0.01 ±1 μA VCC = 3.6 V VO = 0 V ±35 ±60 IOS Short-circuit output current(3) mA VCC = 5.5 V VO = 0 V ±35 ±60 rO Output resistance VCC, V+, and V– = 0 V VO = ±2 V 300 10M Ω VO = ±12 V, ±25 VCC = 3 V to 3.6 V Ioff Output leakage current FORCEOFF = GND μA VO = ±12 V, ±25 VCC = 4.5 V to 5.5V (1) Test conditions are C1−C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2−C4 = 0.33 μF at VCC = 5 V ± 0.5 (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. (3) Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one output should be shorted at a time. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (see Figure 6) PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT Maximum data rate CL = 1000 pF, RL = 3 kΩ, 150 250 kbit/s See Figure 1 t CL = 150 to 2500 pF, RL = 3 kΩ to 7 kΩ, sk(p) Pulse skew(3) See Figure 2 100 ns Slew rate, transition region VCC = 3.3 V, CL = 150 to 1000 pF 6 30 SR(tr) (see Figure 1) R V/μs L = 3 kΩ to 7 kΩ CL = 150 to 2500 pF 4 30 (1) Test conditions are C1−C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2−C4 = 0.33 μF at VCC = 5 V ± 0.5 V. (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. (3) Pulse skew is defined as |tPLH − tPHL| of each channel of the same device. ESD Protection TERMINAL TEST CONDITIONS TYP UNIT NAME NO DOUT 13 HBM ±15 kV 4 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links :MAX3221 MAX3221 www.ti.com SLLS348N –JUNE 1999–REVISED JANUARY 2014 Receiver Section Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (see Figure 6) PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT VOH High-level output voltage IOH = –1 mA VCC – 0.6 VCC – 0.1 V VOL Low-level output voltage IOL = 1.6 mA 0.4 V VCC = 3.3 V 1.5 2.4 VIT+ Positive-going input threshold voltage V VCC = 5 V 1.8 2.4 VCC = 3.3 V 0.6 1.1 VIT– Negative-going input threshold voltage V VCC = 5 V 0.8 1.4 Vhys Input hysteresis (VIT+ – VIT–) 0.5 V Ioff Output leakage current FORCEOFF = 0 V ±0.05 ±10 μA ri Input resistance VI = ±3 V to ±25 V 3 5 7 kΩ (1) Test conditions are C1−C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2−C4 = 0.33 μF at VCC = 5 V ± 0.5 V. (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (see Figure 3) PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT t CL = 150 pF, PLH Propagation delay time, low- to high-level output See Figure 3 150 ns t CL = 150 pF, PHL Propagation delay time, high- to low-level output See Figure 3 150 ns t CL = 150 pF, RL = 3kΩ, en Output enable time See Figure 4 200 ns t CL = 150 pF, RL = 3kΩ, dis Output disable time See Figure 4 200 ns tsk(p) Pulse skew(3) See Figure 3 50 ns (1) Test conditions are C1−C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2−C4 = 0.33 μF at VCC = 5 V ± 0.5 V. (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. (3) Pulse skew is defined as |tPLH − tPHL| of each channel of the same device. ESD Protection TERMINAL TEST CONDITIONS TYP UNIT NAME NO RIN 13 HBM ±15 kV Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links :MAX3221 MAX3221 SLLS348N –JUNE 1999–REVISED JANUARY 2014 www.ti.com Auto-Powerdown Section Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (see Figure 5) PARAMETER TEST CONDITIONS MIN MAX UNIT V Receiver input threshold for INVALID high-level FORCEON = GND, T+(valid) output voltage FORCEOFF = V 2.7 V CC V Receiver input threshold for INVALID high-level FORCEON = GND, T–(valid) output voltage FORCEOFF = V –2.7 V CC V Receiver input threshold for INVALID low-level FORCEON = GND, T(invalid) output voltage FORCEOFF = V –0.3 0.3 V CC IOH = –1 mA, VOH INVALID high-level output voltage FORCEON = GND, VCC – 0.6 V FORCEOFF = VCC IOH = –1 mA, VOL INVALID low-level output voltage FORCEON = GND, 0.4 V FORCEOFF = VCC (1) Test conditions are C1−C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2−C4 = 0.33 μF at VCC = 5 V ± 0.5 V. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (see Figure 5) PARAMETER MIN TYP(2) MAX UNIT tvalid Propagation delay time, low- to high-level output 1 μs tinvalid Propagation delay time, high- to low-level output 30 μs ten Supply enable time 100 μs (1) Test conditions are C1−C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2−C4 = 0.33 μF at VCC = 5 V ± 0.5 V. (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. 6 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links :MAX3221 TEST CIRCUIT VOLTAGE WAVEFORMS 50 ! −3 V 3 V Output Input VOL VOH Generator tPHL (see Note B) tPLH Output CL (see Note A) 3 V or 0 V FORCEON 3 V FORCEOFF 1.5 V 1.5 V 50% 50% 50 ! TEST CIRCUIT VOLTAGE WAVEFORMS 0 V 3 V Output Input VOL VOH tPLH Generator (see Note B) RL 3 V FORCEOFF RS-232 Output CL tPHL (see Note A) 50% 50% 1.5 V 1.5 V 50 ! TEST CIRCUIT VOLTAGE WAVEFORMS −3 V −3 V 3 V 3 V 0 V 3 V Output Input VOL VOH tTLH Generator (see Note B) RL 3 V FORCEOFF RS-232 Output C tTHL L (see Note A) SR(tr) = 6 V tTHL or tTLH MAX3221 www.ti.com SLLS348N –JUNE 1999–REVISED JANUARY 2014 Parameter Measurement Information A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 1. Driver Slew Rate A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 2. Driver Pulse Skew A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 3. Receiver Propagation Delay Times Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links :MAX3221 TEST CIRCUIT VOLTAGE WAVEFORMS 50 ! Generator (see Note B) 3 V or 0 V Output VOL VOH tPZH (S1 at GND) 3 V 0 V 0.3 V Output Input 0.3 V 3 V or 0 V FORCEON EN 1.5 V 1.5 V 50% tPHZ (S1 at GND) tPLZ (S1 at VCC) 50% tPZL (S1 at VCC) RL S1 VCC GND CL (see Note A) Output MAX3221 SLLS348N –JUNE 1999–REVISED JANUARY 2014 www.ti.com Parameter Measurement Information (continued) A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. C. tPLZ and tPHZ are the same as tdis. D. tPZL and tPZH are the same as ten. Figure 4. Receiver Enable and Disable Times 8 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links :MAX3221 TEST CIRCUIT 50 ! Generator (see Note B) FORCEOFF ROUT FORCEON Autopowerdown INVALID DIN DOUT CL = 30 pF (see Note A) 2.7 V −2.7 V 0.3 V −0.3 V 0 V Valid RS-232 Level, INVALID High Indeterminate Indeterminate If Signal Remains Within This Region For More Than 30 μs, INVALID Is Low† Valid RS-232 Level, INVALID High † Auto-powerdown disables drivers and reduces supply current to 1 μA. VOLTAGE WAVEFORMS 3 V 2.7 V −2.7 V INVALID Output Receiver Input tvalid 0 V 0 V −3 V VCC 0 V !V+ 0 V !V− V+ VCC ten V− 50% VCC 50% VCC 2.7 V −2.7 V 0.3 V 0.3 V tinvalid Supply Voltages MAX3221 www.ti.com SLLS348N –JUNE 1999–REVISED JANUARY 2014 Parameter Measurement Information (continued) Figure 5. INVALID Propagation Delay Times and Driver Enabling Time Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links :MAX3221 CBYPASS = 0.1 μF Autopowerdown VCC C1 C2, C3, and C4 3.3 V ± 0.3 V 5 V ± 0.5 V 3 V to 5.5 V 0.1 μF 0.047 μF 0.1 μF 0.1 μF 0.33 μF 0.47 μF VCC vs CAPACITOR VALUES FORCEOFF + − + − + − + − + − 1 8 2 3 5 6 7 4 16 13 12 11 10 9 15 14 VCC GND C1+ V+ C2+ C1− C2− V− DOUT FORCEON DIN INVALID ROUT EN RIN C1 C2 C4 5 k! C3† † C3 can be connected to VCC or GND. NOTES: A. Resistor values shown are nominal. B. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be connected as shown. MAX3221 SLLS348N –JUNE 1999–REVISED JANUARY 2014 www.ti.com APPLICATION INFORMATION Figure 6. Typical Operating Circuit and Capacitor Values 10 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links :MAX3221 MAX3221 www.ti.com SLLS348N –JUNE 1999–REVISED JANUARY 2014 REVISION HISTORY Changes from Revision M (March 2004) to Revision N Page • Updated document to new TI data sheet format - no specification changes. ...................................................................... 1 • Deleted Ordering Information table. ...................................................................................................................................... 1 • Added ESD warning. ............................................................................................................................................................ 2 Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links :MAX3221 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples MAX3221CDB ACTIVE SSOP DB 16 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 MA3221C MAX3221CDBE4 ACTIVE SSOP DB 16 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 MA3221C MAX3221CDBG4 ACTIVE SSOP DB 16 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 MA3221C MAX3221CDBR ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 MA3221C MAX3221CDBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 MA3221C MAX3221CPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 MA3221C MAX3221CPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 MA3221C MAX3221CPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 MA3221C MAX3221CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 MA3221C MAX3221CPWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 MA3221C MAX3221CPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 MA3221C MAX3221IDB ACTIVE SSOP DB 16 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 MB3221I MAX3221IDBE4 ACTIVE SSOP DB 16 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 MB3221I MAX3221IDBG4 ACTIVE SSOP DB 16 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 MB3221I MAX3221IDBR ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 MB3221I MAX3221IDBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 MB3221I MAX3221IDBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 MB3221I PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples MAX3221IPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 MB3221I MAX3221IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 MB3221I MAX3221IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 MB3221I MAX3221IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 MB3221I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 3 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF MAX3221 : • Enhanced Product: MAX3221-EP NOTE: Qualified Version Definitions: • Enhanced Product - Supports Defense, Aerospace and Medical Applications TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant MAX3221CDBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 MAX3221CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MAX3221IDBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 MAX3221IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MAX3221IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MAX3221IPWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2014 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MAX3221CDBR SSOP DB 16 2000 367.0 367.0 38.0 MAX3221CPWR TSSOP PW 16 2000 367.0 367.0 35.0 MAX3221IDBR SSOP DB 16 2000 367.0 367.0 38.0 MAX3221IPWR TSSOP PW 16 2000 364.0 364.0 27.0 MAX3221IPWR TSSOP PW 16 2000 367.0 367.0 35.0 MAX3221IPWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2014 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01 28 PINS SHOWN Gage Plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 Seating Plane 7,90 9,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 A 28 1 16 20 6,50 6,50 14 0,05 MIN 5,90 5,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 0,15 M 0°–8° 0,10 0,09 0,25 NOTES: A. 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E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved. FEATURES Highly accurate; supports IEC 60687, IEC 61036, IEC 61268, IEC 62053-21, IEC 62053-22, and IEC 62053-23 Compatible with 3-phase/3-wire, 3-phase/4-wire, and other 3-phase services Less than 0.1% active energy error over a dynamic range of 1000 to 1 at 25°C Supplies active/reactive/apparent energy, voltage rms, current rms, and sampled waveform data Two pulse outputs, one for active power and the other selectable between reactive and apparent power with programmable frequency Digital power, phase, and rms offset calibration On-chip, user-programmable thresholds for line voltage SAG and overvoltage detections An on-chip, digital integrator enables direct interface-to-current sensors with di/dt output A PGA in the current channel allows direct interface to current transformers An SPI®-compatible serial interface with IRQ Proprietary ADCs and DSP provide high accuracy over large variations in environmental conditions and time Reference 2.4 V (drift 30 ppm/°C typical) with external overdrive capability Single 5 V supply, low power (70 mW typical) GENERAL DESCRIPTION The ADE7758 is a high accuracy, 3-phase electrical energy measurement IC with a serial interface and two pulse outputs. The ADE7758 incorporates second-order Σ-Δ ADCs, a digital integrator, reference circuitry, a temperature sensor, and all the signal processing required to perform active, reactive, and apparent energy measurement and rms calculations. The ADE7758 is suitable to measure active, reactive, and apparent energy in various 3-phase configurations, such as WYE or DELTA services, with both three and four wires. The ADE7758 provides system calibration features for each phase, that is, rms offset correction, phase calibration, and power calibration. The APCF logic output gives active power information, and the VARCF logic output provides instantaneous reactive or apparent power information. FUNCTIONAL BLOCK DIAGRAM PHASE BANDPHASE CDATA4AVDDPOWERSUPPLYMONITOR12REFIN/OUT11AGNDADC–+9ICP10ICNPGA1ADC–+14VCP13VNPGA2ACTIVE/REACTIVE/APPARENT ENERGIESAND VOLTAGE/CURRENT RMS CALCULATIONFOR PHASE C(SEE PHASE A FOR DETAILED SIGNALPATH)ADC–+7IBP8IBNPGA1ADC–+15VBPPGA2ACTIVE/REACTIVE/APPARENT ENERGIESAND VOLTAGE/CURRENT RMS CALCULATIONFOR PHASE B(SEE PHASE A FOR DETAILED SIGNALPATH)ADC–+5IAP6IANPGA1ADC–+16VAPPGA2AVRMSGAIN[11:0]AVAG[11:0]|X|APHCAL[6:0]ΦHPFINTEGRATORdtAVAROS[11:0]AVARG[11:0]LPF290° PHASESHIFTING FILTERπ2AWATTOS[11:0]AWG[11:0]LPF222DIN24DOUT23SCLK21CS18IRQADE7758 REGISTERSANDSERIAL INTERFACEWDIV[7:0]%VARDIV[7:0]%VADIV[7:0]%AIRMSOS[11:0]X2LPF2.4VREF4kΩDFC÷APCFNUM[11:0]APCFDEN[11:0]ACTIVE POWER1APCF3DVDD2DGND19CLKIN20CLKOUTDFCVARCFNUM[11:0]VARCFDEN[11:0]REACTIVE ORAPPARENT POWER17VARCFADE7758AVRMSOS[11:0]04443-001÷ Figure 1. ADE7758 Data Sheet Rev. E | Page 2 of 72 TABLE OF CONTENTS Features..............................................................................................1 General Description.........................................................................1 Functional Block Diagram..............................................................1 General Description.........................................................................4 Specifications.....................................................................................5 Timing Characteristics................................................................6 Timing Diagrams..............................................................................7 Absolute Maximum Ratings............................................................8 ESD Caution..................................................................................8 Pin Configuration and Function Descriptions.............................9 Terminology....................................................................................11 Typical Performance Characteristics...........................................12 Test Circuits.....................................................................................17 Theory of Operation......................................................................18 Antialiasing Filter.......................................................................18 Analog Inputs..............................................................................18 Current Channel ADC...............................................................19 di/dt Current Sensor and Digital Integrator...............................20 Peak Current Detection.............................................................21 Overcurrent Detection Interrupt.............................................21 Voltage Channel ADC...............................................................22 Zero-Crossing Detection...........................................................23 Phase Compensation..................................................................23 Period Measurement..................................................................25 Line Voltage SAG Detection.....................................................25 SAG Level Set..............................................................................26 Peak Voltage Detection..............................................................26 Phase Sequence Detection.........................................................26 Power-Supply Monitor...............................................................27 Reference Circuit........................................................................27 Temperature Measurement.......................................................27 Root Mean Square Measurement.............................................28 Active Power Calculation..........................................................30 Reactive Power Calculation......................................................35 Apparent Power Calculation.....................................................39 Energy Registers Scaling...........................................................41 Waveform Sampling Mode.......................................................41 Calibration...................................................................................42 Checksum Register.....................................................................55 Interrupts.....................................................................................55 Using the Interrupts with an MCU..........................................56 Interrupt Timing........................................................................56 Serial Interface............................................................................56 Serial Write Operation...............................................................57 Serial Read Operation................................................................59 Accessing the On-Chip Registers.............................................59 Registers...........................................................................................60 Communications Register.........................................................60 Operational Mode Register (0x13)..........................................64 Measurement Mode Register (0x14).......................................64 Waveform Mode Register (0x15).............................................65 Computational Mode Register (0x16).....................................66 Line Cycle Accumulation Mode Register (0x17)...................67 Interrupt Mask Register (0x18)................................................68 Interrupt Status Register (0x19)/Reset Interrupt Status Register (0x1A)...........................................................................69 Outline Dimensions.......................................................................70 Ordering Guide..........................................................................70 Revision History 10/11—Rev. D to Rev. E Changes to Figure 1..........................................................................1 Changes to Figure 41......................................................................19 Changes to Figure 60......................................................................27 Added Figure 61; Renumbered Sequentially..............................27 Changes to Phase Sequence Detection Section..........................27 Changes to Power-Supply Monitor Section................................27 Changes to Figure 62......................................................................28 Changes to Figure 67......................................................................32 Changes to Figure 68......................................................................32 Changes to Equation 25.................................................................34 Changes to Figure 69......................................................................34 Changes to Table 17.......................................................................62 Change to Table 18.........................................................................64 Changes to Table 24.......................................................................69 Changes to Ordering Guide..........................................................70 10/08—Rev. C to Rev. D Changes to Figure 1...........................................................................1 Changes to Phase Sequence Detection Section and Figure 60.27 Data Sheet ADE7758 Rev. E | Page 3 of 72 Changes to Current RMS Calculation Section............................28 Changes to Voltage Channel RMS Calculation Section and Figure 63...........................................................................................29 Changes to Table 17........................................................................60 Changes to Ordering Guide...........................................................70 7/06—Rev. B to Rev. C Updated Format..................................................................Universal Changes to Figure 1...........................................................................1 Changes to Table 2............................................................................6 Changes to Table 4............................................................................9 Changes to Figure 34 and Figure 35.............................................17 Changes to Current Waveform Gain Registers Section and Current Channel Sampling Section..............................................19 Changes to Voltage Channel Sampling Section..........................22 Changes to Zero-Crossing Timeout Section...............................23 Changes to Figure 60......................................................................27 Changes to Current RMS Calculation Section............................28 Changes to Current RMS Offset Compensation Section and Voltage Channel RMS Calculation Section.................................29 Added Table 7 and Table 9; Renumbered Sequentially..............29 Changes to Figure 65......................................................................30 Changes to Active Power Offset Calibration Section.................31 Changes to Reactive Power Frequency Output Section.............38 Changes to Apparent Power Frequency Output Section and Waveform Sampling Mode Section..............................................41 Changes to Gain Calibration Using Line Accumulation Section....................................................................49 Changes to Example: Power Offset Calibration Using Line Accumulation Section....................................................................53 Changes to Calibration of IRMS and VRMS Offset Section.....54 Changes to Table 18........................................................................64 Changes to Table 20........................................................................65 11/05—Rev. A to Rev. B Changes to Table 1............................................................................5 Changes to Figure 23 Caption.......................................................14 Changes to Current Waveform Gain Registers Section.............19 Changes to di/dt Current Sensor and Digital Integrator Section............................................................................20 Changes to Phase Compensation Section....................................23 Changes to Figure 57......................................................................25 Changes to Figure 60......................................................................27 Changes to Temperature Measurement Section and Root Mean Square Measurement Section............................28 Inserted Table 6................................................................................28 Changes to Current RMS Offset Compensation Section..........29 Inserted Table 7................................................................................29 Added Equation 17.........................................................................31 Changes to Energy Accumulation Mode Section.......................33 Changes to the Reactive Power Calculation Section..................35 Added Equation 32...........................................................................36 Changes to Energy Accumulation Mode Section.......................38 Changes to the Reactive Power Frequency Output Section......38 Changes to the Apparent Energy Calculation Section...............40 Changes to the Calibration Section..............................................42 Changes to Figure 76 through Figure 84...............................43–54 Changes to Table 15........................................................................59 Changes to Table 16........................................................................63 Changes to Ordering Guide...........................................................69 9/04—Rev. 0 to Rev. A Changed Hexadecimal Notation......................................Universal Changes to Features List...................................................................1 Changes to Specifications Table......................................................5 Change to Figure 25........................................................................16 Additions to the Analog Inputs Section.......................................19 Added Figures 36 and 37; Renumbered Subsequent Figures....19 Changes to Period Measurement Section....................................26 Change to Peak Voltage Detection Section.................................26 Added Figure 60..............................................................................27 Change to the Current RMS Offset Compensation Section.....29 Edits to Active Power Frequency Output Section......................33 Added Figure 68; Renumbered Subsequent Figures..................33 Changes to Reactive Power Frequency Output Section.............37 Added Figure 73; Renumbered Subsequent Figures..................38 Change to Gain Calibration Using Pulse Output Example.......44 Changes to Equation 37.................................................................45 Changes to Example—Phase Calibration of Phase A Using Pulse Output.........................................................................45 Changes to Equations 56 and 57...................................................53 Addition to the ADE7758 Interrupts Section.............................54 Changes to Example-Calibration of RMS Offsets......................54 Addition to Table 20.......................................................................66 1/04—Revision 0: Initial Version ADE7758 Data Sheet Rev. E | Page 4 of 72 GENERAL DESCRIPTION The ADE7758 has a waveform sample register that allows access to the ADC outputs. The part also incorporates a detection circuit for short duration low or high voltage variations. The voltage threshold levels and the duration (number of half-line cycles) of the variation are user programmable. A zero-crossing detection is synchronized with the zero-crossing point of the line voltage of any of the three phases. This information can be used to measure the period of any one of the three voltage inputs. The zero-crossing detection is used inside the chip for the line cycle energy accumulation mode. This mode permits faster and more accurate calibration by synchronizing the energy accumulation with an integer number of line cycles. Data is read from the ADE7758 via the SPI serial interface. The interrupt request output (IRQ) is an open-drain, active low logic output. The IRQ output goes active low when one or more interrupt events have occurred in the . A status register indicates the nature of the interrupt. The is available in a 24-lead SOIC package. ADE7758ADE7758 Data Sheet ADE7758 Rev. E | Page 5 of 72 SPECIFICATIONS AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, TMIN to TMAX = −40°C to +85°C. Table 1. Parameter1, 2 Specification Unit Test Conditions/Comments ACCURACY Active Energy Measurement Error (per Phase) 0.1 % typ Over a dynamic range of 1000 to 1 Phase Error Between Channels Line frequency = 45 Hz to 65 Hz, HPF on PF = 0.8 Capacitive ±0.05 °max Phase lead 37° PF = 0.5 Inductive ±0.05 °max Phase lag 60° AC Power Supply Rejection AVDD = DVDD = 5 V + 175 mV rms/120 Hz Output Frequency Variation 0.01 % typ V1P = V2P = V3P = 100 mV rms DC Power Supply Rejection AVDD = DVDD = 5 V ± 250 mV dc Output Frequency Variation 0.01 % typ V1P = V2P = V3P = 100 mV rms Active Energy Measurement Bandwidth 14 kHz IRMS Measurement Error 0.5 % typ Over a dynamic range of 500:1 IRMS Measurement Bandwidth 14 kHz VRMS Measurement Error 0.5 % typ Over a dynamic range of 20:1 VRMS Measurement Bandwidth 260 Hz ANALOG INPUTS See the Analog Inputs section Maximum Signal Levels ±500 mV max Differential input Input Impedance (DC) 380 kΩ min ADC Offset Error3 ±30 mV max Uncalibrated error, see the Terminology section Gain Error3 ±6 % typ External 2.5 V reference WAVEFORM SAMPLING Sampling CLKIN/128, 10 MHz/128 = 78.1 kSPS Current Channels See the Current Channel ADC section Signal-to-Noise Plus Distortion 62 dB typ Bandwidth (−3 dB) 14 kHz Voltage Channels See the Voltage Channel ADC section Signal-to-Noise Plus Distortion 62 dB typ Bandwidth (−3 dB) 260 Hz REFERENCE INPUT REFIN/OUT Input Voltage Range 2.6 V max 2.4 V + 8% 2.2 V min 2.4 V − 8% Input Capacitance 10 pF max ON-CHIP REFERENCE Nominal 2.4 V at REFIN/OUT pin Reference Error ±200 mV max Current Source 6 μA max Output Impedance 4 kΩ min Temperature Coefficient 30 ppm/°C typ CLKIN All specifications CLKIN of 10 MHz Input Clock Frequency 15 MHz max 5 MHz min LOGIC INPUTS DIN, SCLK, CLKIN, and CS Input High Voltage, VINH 2.4 V min DVDD = 5 V ± 5% Input Low Voltage, VINL 0.8 V max DVDD = 5 V ± 5% Input Current, IIN ±3 μA max Typical 10 nA, VIN = 0 V to DVDD Input Capacitance, CIN 10 pF max ADE7758 Data Sheet Rev. E | Page 6 of 72 Parameter1, 2 Specification Unit Test Conditions/Comments LOGIC OUTPUTS DVDD = 5 V ± 5% IRQ, DOUT, and CLKOUT IRQ is open-drain, 10 kΩ pull-up resistor Output High Voltage, VOH 4 V min ISOURCE = 5 mA Output Low Voltage, VOL 0.4 V max ISINK = 1 mA APCF and VARCF Output High Voltage, VOH 4 V min ISOURCE = 8 mA Output Low Voltage, VOL 1 V max ISINK = 5 mA POWER SUPPLY For specified performance AVDD 4.75 V min 5 V − 5% 5.25 V max 5 V + 5% DVDD 4.75 V min 5 V − 5% 5.25 V max 5 V + 5% AIDD 8 mA max Typically 5 mA DIDD 13 mA max Typically 9 mA 1 See the Typical Performance Characteristics. 2 See the Terminology section for a definition of the parameters. 3 See the Analog Inputs section. TIMING CHARACTERISTICS AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, TMIN to TMAX = −40°C to +85°C. Table 2. Parameter1, 2 Specification Unit Test Conditions/Comments WRITE TIMING t1 50 ns (min) CS falling edge to first SCLK falling edge t2 50 ns (min) SCLK logic high pulse width t3 50 ns (min) SCLK logic low pulse width t4 10 ns (min) Valid data setup time before falling edge of SCLK t5 5 ns (min) Data hold time after SCLK falling edge t6 1200 ns (min) Minimum time between the end of data byte transfers t7 400 ns (min) Minimum time between byte transfers during a serial write t8 100 ns (min) CS hold time after SCLK falling edge READ TIMING t93 4 μs (min) Minimum time between read command (that is, a write to communication register) and data read t10 50 ns (min) Minimum time between data byte transfers during a multibyte read t114 30 ns (min) Data access time after SCLK rising edge following a write to the communications register t125 100 ns (max) Bus relinquish time after falling edge of SCLK 10 ns (min) t135 100 ns (max) Bus relinquish time after rising edge of CS 10 ns (min) 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. 2 See the timing diagrams in Figure 3 and Figure 4 and the Serial Interface section. 3 Minimum time between read command and data read for all registers except waveform register, which is t9 = 500 ns min. 4 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V. 5 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted here is the true bus relinquish time of the part and is independent of the bus loading. Data Sheet ADE7758 Rev. E | Page 7 of 72 TIMING DIAGRAMS 200μAIOL1.6mAIOH2.1VTO OUTPUTPINCL50pF04443-002 Figure 2. Load Circuit for Timing Specifications DINSCLKCSt2t3t1t4t5t7t6t8COMMAND BYTEMOST SIGNIFICANT BYTELEAST SIGNIFICANT BYTE1A6A4A5A3A2A1A0DB7DB0DB7DB0t704443-003 Figure 3. Serial Write Timing SCLKCSt1t10t130A6A4A5A3A2A1A0DB0DB7DB0DB7DINDOUTt11t12COMMAND BYTEMOST SIGNIFICANT BYTELEAST SIGNIFICANT BYTEt904443-004 Figure 4. Serial Read Timing ADE7758 Data Sheet Rev. E | Page 8 of 72 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating AVDD to AGND –0.3 V to +7 V DVDD to DGND –0.3 V to +7 V DVDD to AVDD –0.3 V to +0.3 V Analog Input Voltage to AGND, IAP, IAN, IBP, IBN, ICP, ICN, VAP, VBP, VCP, VN –6 V to +6 V Reference Input Voltage to AGND –0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND –0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND –0.3 V to DVDD + 0.3 V Operating Temperature Industrial Range –40°C to +85°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C 24-Lead SOIC, Power Dissipation 88 mW θJA Thermal Impedance 53°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Data Sheet ADE7758 Rev. E | Page 9 of 72 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS APCF1DGND2DVDD3AVDD4DOUT24SCLK23DIN22CS21IAP5CLKOUT20IAN6CLKIN19IBP7IRQ18IBN8VARCF17ICP9VAP16ICN10VBP15AGND11VCP14REFIN/OUT12VN13ADE7758TOP VIEW(Not to Scale)04443-005 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 APCF Active Power Calibration Frequency (APCF) Logic Output. It provides active power information. This output is used for operational and calibration purposes. The full-scale output frequency can be scaled by writing to the APCFNUM and APCFDEN registers (see the Active Power Frequency Output section). 2 DGND This provides the ground reference for the digital circuitry in the ADE7758, that is, the multiplier, filters, and digital-to-frequency converter. Because the digital return currents in the ADE7758 are small, it is acceptable to connect this pin to the analog ground plane of the whole system. However, high bus capacitance on the DOUT pin can result in noisy digital current that could affect performance. 3 DVDD Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7758. The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to DGND with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 4 AVDD Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7758. The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. The Typical Performance Characteristics show the power supply rejection performance. This pin should be decoupled to AGND with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 5, 6, 7, 8, 9, 10 IAP, IAN, IBP, IBN, ICP, ICN Analog Inputs for Current Channel. This channel is used with the current transducer and is referenced in this document as the current channel. These inputs are fully differential voltage inputs with maximum differential input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V, depending on the gain selections of the internal PGA (see the Analog Inputs section). All inputs have internal ESD protection circuitry. In addition, an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage. 11 AGND This pin provides the ground reference for the analog circuitry in the ADE7758, that is, ADCs, temperature sensor, and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, for example, antialiasing filters, current, and voltage transducers. To keep ground noise around the ADE7758 to a minimum, the quiet ground plane should be connected to the digital ground plane at only one point. It is acceptable to place the entire device on the analog ground plane. 12 REFIN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.4 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source can also be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 μF ceramic capacitor. 13, 14, 15, 16 VN, VCP, VBP, VAP Analog Inputs for the Voltage Channel. This channel is used with the voltage transducer and is referenced as the voltage channels in this document. These inputs are single-ended voltage inputs with the maximum signal level of ±0.5 V with respect to VN for specified operation. These inputs are voltage inputs with maximum input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V, depending on the gain selections of the internal PGA (see the Analog Inputs section). All inputs have internal ESD protection circuitry, and in addition, an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage. ADE7758 Data Sheet Rev. E | Page 10 of 72 Pin No. Mnemonic Description 17 VARCF Reactive Power Calibration Frequency Logic Output. It gives reactive power or apparent power information depending on the setting of the VACF bit of the WAVMODE register. This output is used for operational and calibration purposes. The full-scale output frequency can be scaled by writing to the VARCFNUM and VARCFDEN registers (see the Reactive Power Frequency Output section). 18 IRQ Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts include: an active energy register at half level, an apparent energy register at half level, and waveform sampling up to 26 kSPS (see the Interrupts section). 19 CLKIN Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7758. The clock frequency for specified operation is 10 MHz. Ceramic load capacitors of a few tens of picofarad should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for the load capacitance requirements 20 CLKOUT A crystal can be connected across this pin and CLKIN as previously described to provide a clock source for the ADE7758. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used. 21 CS Chip Select. Part of the 4-wire serial interface. This active low logic input allows the ADE7758 to share the serial bus with several other devices (see the Serial Interface section). 22 DIN Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK (see the Serial Interface section). 23 SCLK Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this clock (see the Serial Interface section). The SCLK has a Schmidt-trigger input for use with a clock source that has a slow edge transition time, for example, opto-isolator outputs. 24 DOUT Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic output is normally in a high impedance state, unless it is driving data onto the serial data bus (see the Serial Interface section). Data Sheet ADE7758 Rev. E | Page 11 of 72 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7758 is defined by %100–×=EnergyTrueEnergyTrueADE7758byRegisteredEnergyErrortMeasuremen (1) Phase Error Between Channels The high-pass filter (HPF) and digital integrator introduce a slight phase mismatch between the current and the voltage channel. The all-digital design ensures that the phase matching between the current channels and voltage channels in all three phases is within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2° over a range of 40 Hz to 1 kHz. This internal phase mismatch can be combined with the external phase error (from current sensor or component tolerance) and calibrated with the phase calibration registers. Power Supply Rejection (PSR) This quantifies the ADE7758 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when an ac signal (175 mV rms/100 Hz) is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading—see the Measurement Error definition. For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when the power supplies are varied ±5%. Any error introduced is again expressed as a percentage of the reading. ADC Offset Error This refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND that the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection (see the Typical Performance Characteristics section). However, when HPFs are switched on, the offset is removed from the current channels and the power calculation is not affected by this offset. Gain Error The gain error in the ADCs of the ADE7758 is defined as the difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADC section and the Voltage Channel ADC section). The difference is expressed as a percentage of the ideal code. Gain Error Match The gain error match is defined as the gain error (minus the offset) obtained when switching between a gain of 1, 2, or 4. It is expressed as a percentage of the output ADC code obtained under a gain of 1. ADE7758 Data Sheet Rev. E | Page 12 of 72 TYPICAL PERFORMANCE CHARACTERISTICS 0.5–0.5–0.4–0.3–0.2–0.100.10.20.30.40.010.1110100PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)+25°CPF = 1+85°C–40°C04443-006 Figure 6. Active Energy Error as a Percentage of Reading (Gain = +1) over Temperature with Internal Reference and Integrator Off 0.3–0.3–0.2–0.100.10.20.010.1110100PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)PF = +1, +25°CPF = +0.5, +25°CPF =–0.5, +25°CPF = +0.5, +85°CPF = +0.5,–40°C04443-007 Figure 7. Active Energy Error as a Percentage of Reading (Gain = +1) over Power Factor with Internal Reference and Integrator Off 0.3–0.3–0.2–0.100.10.20.010.1110100PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)GAIN = +2GAIN = +4PF = 1GAIN = +104443-008 Figure 8. Active Energy Error as a Percentage of Reading over Gain with Internal Reference and Integrator Off 0.20–0.20–0.15–0.10–0.0500.050.100.150.010.1110100PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)PF =–0.5, +25°CPF = +0.5, +25°CPF = +0.5,–40°CPF = +0.5, +85°C04443-009 Figure 9. Active Energy Error as a Percentage of Reading (Gain = +1) over Temperature with External Reference and Integrator Off 0.50.6–0.2–0.3–0.4–0.100.10.20.30.44547495153555759616365LINE FREQUENCY (Hz)PERCENT ERROR (%)WITH RESPECT TO 55HzPF = 1PF = 0.504443-010 Figure 10. Active Energy Error as a Percentage of Reading (Gain = +1) over Frequency with Internal Reference and Integrator Off 0.080.10–0.06–0.08–0.10–0.04–0.0200.020.040.060.010.1110100PERCENTFULL-SCALECURRENT(%)PERCENT ERROR (%)WITH RESPECTTO 5V; 3AVDD=5VVDD=5.25VVDD=4.75VPF=104443-011 Figure 11. Active Energy Error as a Percentage of Reading (Gain = +1) over Power Supply with Internal Reference and Integrator Off Data Sheet ADE7758 Rev. E | Page 13 of 72 0.200.25–0.15–0.20–0.25–0.10–0.0500.050.100.150.010.1110100PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)PHASE APHASE BPHASE CALL PHASESPF = 104443-012 Figure 12. APCF Error as a Percentage of Reading (Gain = +1) with Internal Reference and Integrator Off 0.4–0.4–0.3–0.2–0.100.10.20.30.010.1110100PF = 0, +25°CPF = 0, +85°CPF = 0,–40°CPERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)04443-013 Figure 13. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Temperature with Internal Reference and Integrator Off 0.8–0.8–0.6–0.4–0.200.20.40.60.010.1110100PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)PF = 0, +25°CPF =–0.866, +25°CPF = +0.866, +25°CPF = +0.866, +85°CPF = +0.866,–40°C04443-014 Figure 14. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Power Factor with Internal Reference and Integrator Off 0.3–0.3–0.2–0.100.10.20.010.1110100PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)PF = 0, +25°CPF = 0, +85°CPF = 0,–40°C04443-015 Figure 15. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Temperature with External Reference and Integrator Off 0.3–0.3–0.2–0.100.10.20.010.1110100PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)PF = 0, +25°CPF =–0.866, +25°CPF = +0.866, +25°CPF = +0.866, +85°CPF = +0.866,–40°C04443-016 Figure 16. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Power Factor with External Reference and Integrator Off 0.8–0.8–0.6–0.4–0.200.20.40.64547495153555759616365LINE FREQUENCY (Hz)PERCENT ERROR (%)WITH RESPECT TO 55HzPF = 0PF = 0.86604443-017 Figure 17. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Frequency with Internal Reference and Integrator Off ADE7758 Data Sheet Rev. E | Page 14 of 72 0.10–0.10–0.08–0.06–0.04–0.0200.020.040.060.080.010.1110100PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)WITH RESPECT TO 5V; 3A5V5.25V4.75V04443-018 Figure 18. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Supply with Internal Reference and Integrator Off 0.3–0.3–0.2–0.100.10.20.010.1110100PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)GAIN = +1GAIN = +2GAIN = +4PF = 004443-019 Figure 19. Reactive Energy Error as a Percentage of Reading over Gain with Internal Reference and Integrator Off 0.4–0.4–0.2–0.3–0.100.10.20.30.010.1110100PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)PHASE AALL PHASESPHASE CPHASE BPF = 104443-020 Figure 20. VARCF Error as a Percentage of Reading (Gain = +1) with Internal Reference and Integrator Off 0.3–0.3–0.2–0.100.10.20.010.1110100PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)+25°C+85°C–40°C04443-021 Figure 21. Active Energy Error as a Percentage of Reading (Gain = +4) over Temperature with Internal Reference and Integrator On 0.50.4–0.5–0.4–0.2–0.3–0.100.10.20.30.010.1110100PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)PF = +1, +25°CPF =–0.5, +25°CPF = +0.5, +25°CPF = +0.5, +85°CPF = +0.5,–40°C04443-022 Figure 22. Active Energy Error as a Percentage of Reading (Gain = +4) over Power Factor with Internal Reference and Integrator On 0.8–0.8–0.4–0.6–0.200.20.40.60.010.1110100PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)PF = 0, +25°CPF = +0.866, +25°CPF =–0.866, +25°CPF =–0.866, +85°CPF =–0.866,–40°C04443-023 Figure 23. Reactive Energy Error as a Percentage of Reading (Gain = +4) over Power Factor with Internal Reference and Integrator On Data Sheet ADE7758 Rev. E | Page 15 of 72 0.4–0.5–0.4–0.2–0.3–0.100.10.20.30.010.1110100PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)+25°C+85°C–40°CPF = 004443-024 Figure 24. Reactive Energy Error as a Percentage of Reading (Gain = +4) over Temperature with Internal Reference and Integrator On 0.50.4–0.5–0.4–0.2–0.3–0.100.10.20.34547495153555759616365LINE FREQUENCY (Hz)PERCENT ERROR (%)PF = 1PF = 0.504443-025 Figure 25. Active Energy Error as a Percentage of Reading (Gain = +4) over Frequency with Internal Reference and Integrator On 1.21.0–0.8–0.6–0.2–0.400.20.40.60.84547495153555759616365LINE FREQUENCY (Hz)PERCENT ERROR (%)PF = 0.866PF = 004443-026 Figure 26. Reactive Energy Error as a Percentage of Reading (Gain = +4) over Frequency with Internal Reference and Integrator On 0.80.6–1.2–1.0–0.6–0.8–0.4–0.200.20.40.010.1110100PF = 0.5PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)PF = 104443-027 Figure 27. IRMS Error as a Percentage of Reading (Gain = +1) with Internal Reference and Integrator Off 0.80.6–1.0–0.6–0.8–0.4–0.200.20.40.1110100PF = +1PF =–0.5PERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)04443-028 Figure 28. IRMS Error as a Percentage of Reading (Gain = +4) with Internal Reference and Integrator On 0.4–0.4–0.3–0.2–0.100.10.20.3110100VOLTAGE (V)PERCENT ERROR (%)04443-029 Figure 29. VRMS Error as a Percentage of Reading (Gain = +1) with Internal Reference ADE7758 Data Sheet Rev. E | Page 16 of 72 1.5–1.5–1.0–0.500.51.00.011100.1100+25°C+85°C–40°CPERCENT FULL-SCALE CURRENT (%)PERCENT ERROR (%)04443-030 –2024681012182115129630CH 1 PhB OFFSET (mV)HITSMEAN: 6.5149SD: 2.81604443-032 Figure 30. Apparent Energy Error as a Percentage of Reading (Gain = +1) over Temperature with Internal Reference and Integrator Off Figure 32. Phase B Channel 1 Offset Distribution 2468101412121086420CH 1 PhC OFFSET (mV)HITSMEAN: 6.69333SD: 2.7044304443-033 –4–20246810121815129630CH 1 PhA OFFSET (mV)HITSMEAN: 5.55393SD: 3.298504443-031 Figure 33. Phase C Channel 1 Offset Distribution Figure 31. Phase A Channel 1 Offset Distribution Data Sheet ADE7758 Rev. E | Page 17 of 72 TEST CIRCUITS REFIN/OUT33nF1kΩ100nF33nF1kΩ10μFVDDVNIANIBPIBNICPICNVAPAVDDDVDDVBPVCPAGNDDGNDDOUTSCLKAPCFCLKOUTCLKINCSDINIRQ10MHz22pF22pFPS2501-1131121TO FREQ.COUNTER142320IAPRBSAMEASIAP, IAN98710161514100nF10μF33nF1kΩ1MΩ220V33nF1kΩ825ΩITO SPI BUS341956242321221812SAMEASIAP, IANSAMEAS VAPSAMEAS VAPADE7758CURRENTTRANSFORMER17VARCFCT TURN RATIO 1800:1CHANNEL 2 GAIN = +1CHANNEL 1 GAINRB110Ω25Ω42.5Ω81.25Ω04443-034 Figure 34. Test Circuit for Integrator Off REFIN/OUT33nF1kΩ33nF1kΩ33nF1kΩ33nF1kΩ100nF10μFVDDVNIANIBPIBNICPICNVAPAVDDDVDDVBPVCPAGNDDGNDDOUTSCLKAPCFCLKOUTCLKINCSDINIRQ10MHz22pF22pFPS2501-1131121TO FREQ.COUNTER142320IAPSAMEASIAP, IAN98710161514100nF10μF33nF1kΩ1MΩ220V33nF1kΩ825ΩTO SPI BUS341956242321221812SAMEASIAP, IANSAMEAS VAPSAMEAS VAPADE7758Idi/dt SENSOR17VARCFCHANNEL 1 GAIN = +8CHANNEL 2 GAIN = +104443-035 Figure 35. Test Circuit for Integrator On ADE7758 Data Sheet Rev. E | Page 18 of 72 THEORY OF OPERATION ANTIALIASING FILTER This filter prevents aliasing, which is an artifact of all sampled systems. Input signals with frequency components higher than half the ADC sampling rate distort the sampled signal at a fre-quency below half the sampling rate. This happens with all ADCs, regardless of the architecture. The combination of the high sampling rate Σ-Δ ADC used in the ADE7758 with the relatively low bandwidth of the energy meter allows a very simple low-pass filter (LPF) to be used as an antialiasing filter. A simple RC filter (single pole) with a corner frequency of 10 kHz produces an attenuation of approximately 40 dB at 833 kHz. This is usually sufficient to eliminate the effects of aliasing. ANALOG INPUTS The ADE7758 has six analog inputs divided into two channels: current and voltage. The current channel consists of three pairs of fully differential voltage inputs: IAP and IAN, IBP and IBN, and ICP and ICN. These fully differential voltage input pairs have a maximum differential signal of ±0.5 V. The current channel has a programmable gain amplifier (PGA) with possible gain selection of 1, 2, or 4. In addition to the PGA, the current channels also have a full-scale input range selection for the ADC. The ADC analog input range selection is also made using the gain register (see Figure 38). As mentioned previously, the maximum differential input voltage is ±0.5 V. However, by using Bit 3 and Bit 4 in the gain register, the maximum ADC input voltage can be set to ±0.5 V, ±0.25 V, or ±0.125 V on the current channels. This is achieved by adjusting the ADC reference (see the Reference Circuit section). Figure 36 shows the maximum signal levels on the current channel inputs. The maximum common-mode signal is ±25 mV, as shown in Figure 37. DIFFERENTIAL INPUTV1 + V2 = 500mV MAX PEAK+500mVVCMV1IAP, IBP,OR ICPVCM–500mVCOMMON-MODE±25mV MAXV1 + V2V2IAN, IBN,OR ICN04443-036 Figure 36. Maximum Signal Levels, Current Channels, Gain = 1 The voltage channel has three single-ended voltage inputs: VAP, VBP, and VCP. These single-ended voltage inputs have a maximum input voltage of ±0.5 V with respect to VN. Both the current and voltage channel have a PGA with possible gain selections of 1, 2, or 4. The same gain is applied to all the inputs of each channel. Figure 37 shows the maximum signal levels on the voltage channel inputs. The maximum common-mode signal is ±25 mV, as shown in Figure 36. SINGLE-ENDED INPUT±500mV MAX PEAK+500mVAGNDVCMV2VAP, VBP,OR VCPVCM–500mVCOMMON-MODE±25mV MAXVNV204443-037 Figure 37. Maximum Signal Levels, Voltage Channels, Gain = 1 The gain selections are made by writing to the gain register. Bit 0 to Bit 1 select the gain for the PGA in the fully differential current channel. The gain selection for the PGA in the single-ended voltage channel is made via Bit 5 to Bit 6. Figure 38 shows how a gain selection for the current channel is made using the gain register. IAP, IBP, ICPIAN, IBN, ICNVINK ×VINGAIN[7:0]GAIN (K)SELECTION04443-038 Figure 38. PGA in Current Channel Figure 39 shows how the gain settings in PGA 1 (current channel) and PGA 2 (voltage channel) are selected by various bits in the gain register. GAIN REGISTER1CURRENT AND VOLTAGE CHANNEL PGA CONTROL7 6 5 4 3 2 1 00 0 0 0 0 0 0 0ADDRESS: 0x23RESERVED1REGISTER CONTENTS SHOW POWER-ON DEFAULTSPGA 2 GAIN SELECT00 = ×101 = ×210 = ×4INTEGRATOR ENABLE0 = DISABLE1 = ENABLEPGA 1 GAIN SELECT00 = ×101 = ×210 = ×4CURRENT INPUT FULL-SCALE SELECT00 = 0.5V01 = 0.25V10 = 0.125V04443-039 Figure 39. Analog Gain Register Bit 7 of the gain register is used to enable the digital integrator in the current signal path. Setting this bit activates the digital integrator (see the DI/DT Current Sensor and Digital Integrator section). Data Sheet ADE7758 Rev. E | Page 19 of 72 CURRENT CHANNEL ADC Figure 41 shows the ADC and signal processing path for the input IA of the current channels (same for IB and IC). In waveform sampling mode, the ADC outputs are signed twos complement 24-bit data-words at a maximum of 26.0 kSPS (thousand samples per second). With the specified full-scale analog input signal of ±0.5 V, the ADC produces its maximum output code value (see Figure 41). This diagram shows a full-scale voltage signal being applied to the differential inputs IAP and IAN. The ADC output swings between 0xD7AE14 (−2,642,412) and 0x2851EC (+2,642,412). Current Channel Sampling The waveform samples of the current channel can be routed to the WFORM register at fixed sampling rates by setting the WAVSEL[2:0] bit in the WAVMODE register to 000 (binary) (see Table 20). The phase in which the samples are routed is set by setting the PHSEL[1:0] bits in the WAVMODE register. Energy calculation remains uninterrupted during waveform sampling. When in waveform sample mode, one of four output sample rates can be chosen by using Bit 5 and Bit 6 of the WAVMODE register (DTRT[1:0]). The output sample rate can be 26.04 kSPS, 13.02 kSPS, 6.51 kSPS, or 3.25 kSPS. By setting the WFSM bit in the interrupt mask register to Logic 1, the interrupt request output IRQ goes active low when a sample is available. The timing is shown in . The 24-bit waveform samples are transferred from the one byte (8-bits) at a time, with the most significant byte shifted out first. Figure 40ADE7758READ FROMWAVEFORM0SGNCURRENT CHANNEL DATA–24 BITS0x12SCLKDINDOUTIRQ04443-040 Figure 40. Current Channel Waveform Sampling The interrupt request output IRQ stays low until the interrupt routine reads the reset status register (see the section). InterruptsDIGITALINTEGRATOR1GAIN[7]ADCREFERENCEACTIVEAND REACTIVEPOWER CALCULATIONWAVEFORM SAMPLEREGISTERCURRENT RMS (IRMS)CALCULATIONIAPIANPGA1VINGAIN[4:3]2.42V, 1.21V, 0.6VGAIN[1:0]×1, ×2, ×4ANALOGINPUTRANGEVIN0V0.5V/GAIN0.25V/GAIN0.125V/GAINADC OUTPUTWORD RANGECHANNEL 1(CURRENTWAVEFORM)DATA RANGE0xD7AE140x0000000x2851EC50HzCHANNEL 1 (CURRENTWAVEFORM)DATA RANGEAFTER INTEGRATOR(50HzANDAIGAIN[11:0] = 0x000)0xCB2E480x0000000x34D1B860HzCHANNEL 1 (CURRENTWAVEFORM)DATA RANGEAFTER INTEGRATOR(60HzANDAIGAIN[11:0] = 0x000)0xD4176D0x0000000x2BE893HPF04443-0411WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA ISATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A –20dB/DECADE FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT WILL NOT BE FURTHERATTENUATED. Figure 41. Current Channel Signal Path ADE7758 Data Sheet Rev. E | Page 20 of 72 DI/DT CURRENT SENSOR AND DIGITAL INTEGRATOR The di/dt sensor detects changes in the magnetic field caused by the ac current. Figure 42 shows the principle of a di/dt current sensor. MAGNETIC FIELD CREATED BY CURRENT (DIRECTLY PROPORTIONAL TO CURRENT) + EMF (ELECTROMOTIVE FORCE) – INDUCED BY CHANGES IN MAGNETIC FLUX DENSITY (di/dt) 04443-042 Figure 42. Principle of a di/dt Current Sensor The flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. The changes in the magnetic flux density passing through a conductor loop generate an electromotive force (EMF) between the two ends of the loop. The EMF is a voltage signal that is propor- tional to the di/dt of the current. The voltage output from the di/dt current sensor is determined by the mutual inductance between the current carrying conductor and the di/dt sensor. The current signal needs to be recovered from the di/dt signal before it can be used. An integrator is therefore necessary to restore the signal to its original form. The ADE7758 has a built- in digital integrator to recover the current signal from the di/dt sensor. The digital integrator on Channel 1 is disabled by default when the ADE7758 is powered up. Setting the MSB of the GAIN[7:0] register turns on the integrator. Figure 43 to Figure 46 show the magnitude and phase response of the digital integrator. 10 100 1k 10k 20 –50 –40 –30 –20 –10 0 10 FREQUENCY (Hz) GAIN (dB) 04443-043 Figure 43. Combined Gain Response of the Digital Integrator and Phase Compensator 10 100 1k 10k 80 91 90 89 88 87 86 85 84 83 82 81 FREQUENCY (Hz) PHASE (Degrees) 04443-044 Figure 44. Combined Phase Response of the Digital Integrator and Phase Compensator 40 45 50 55 60 65 70 5 –1 0 1 2 3 4 FREQUENCY (Hz) MAGNITUDE (dB) 04443-045 Figure 45. Combined Gain Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz) 40 45 50 55 60 65 70 89.80 90.10 90.05 90.00 89.95 89.90 89.85 FREQUENCY (Hz) PHASE (Degrees) 04443-046 Figure 46. Combined Phase Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz) Data Sheet ADE7758 Rev. E | Page 21 of 72 Note that the integrator has a −20 dB/dec attenuation and approximately −90° phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. However, the di/dt sensor has a 20 dB/dec gain associated with it and generates significant high frequency noise. A more effective antialiasing filter is needed to avoid noise due to aliasing (see the Theory of Operation section). When the digital integrator is switched off, the ADE7758 can be used directly with a conventional current sensor, such as a current transformer (CT) or a low resistance current shunt. PEAK CURRENT DETECTION The ADE7758 can be programmed to record the peak of the current waveform and produce an interrupt if the current exceeds a preset limit. Peak Current Detection Using the PEAK Register The peak absolute value of the current waveform within a fixed number of half-line cycles is stored in the IPEAK register. Figure 47 illustrates the timing behavior of the peak current detection. L2 L1 CONTENT OF IPEAK[7:0] 00 L1L2L1 NO. OF HALF LINE CYCLES SPECIFIED BY LINECYC[15:0] REGISTER CURRENT WAVEFORM (PHASE SELECTED BY PEAKSEL[2:0] IN MMODE REGISTER) 04443-047 Figure 47. Peak Current Detection Using the IPEAK Register Note that the content of the IPEAK register is equivalent to Bit 14 to Bit 21 of the current waveform sample. At full-scale analog input, the current waveform sample is 0x2851EC. The IPEAK at full-scale input is therefore expected to be 0xA1. In addition, multiple phases can be activated for the peak detection simultaneously by setting more than one of the PEAKSEL[2:4] bits in the MMODE register to logic high. These bits select the phase for both voltage and current peak measurements. Note that if more than one bit is set, the VPEAK and IPEAK registers can hold values from two different phases, that is, the voltage and current peak are independently processed (see the Peak Current Detection section). Note that the number of half-line cycles is based on counting the zero crossing of the voltage channel. The ZXSEL[2:0] bits in the LCYCMODE register determine which voltage channels are used for the zero-crossing detection. The same signal is also used for line cycle energy accumulation mode if activated (see the Line Cycle Accumulation Mode Register (0X17) section). OVERCURRENT DETECTION INTERRUPT Figure 48 illustrates the behavior of the overcurrent detection. IPINTLVL[7:0] READ RSTATUS REGISTER PKI INTERRUPT FLAG (BIT 15 OF STATUS REGISTER) PKI RESET LOW WHEN RSTATUS REGISTER IS READ CURRENT PEAK WAVEFORM BEING MONITORED (SELECTED BY PKIRQSEL[2:0] IN MMODE REGISTER) 04443-048 Figure 48. ADE7758 Overcurrent Detection Note that the content of the IPINTLVL[7:0] register is equivalent to Bit 14 to Bit 21 of the current waveform sample. Therefore, setting this register to 0xA1 represents putting peak detection at full-scale analog input. Figure 48 shows a current exceeding a threshold. The overcurrent event is recorded by setting the PKI flag (Bit 15) in the interrupt status register. If the PKI enable bit is set to Logic 1 in the interrupt mask register, the IRQ logic output goes active low (see the Interrupts section). Similar to peak level detection, multiple phases can be activated for peak detection. If any of the active phases produce waveform samples above the threshold, the PKI flag in the interrupt status register is set. The phase of which overcurrent is monitored is set by the PKIRQSEL[2:0] bits in the MMODE register (see Table 19). ADE7758 Data Sheet Rev. E | Page 22 of 72 ADCTO VOLTAGE RMSCALCULATION ANDWAVEFORM SAMPLINGTO ACTIVE ANDREACTIVE ENERGYCALCULATIONVAP+–VNPGAVAGAIN[6:5]×1, ×2, ×4LPF OUTPUTWORD RANGE0xD8690x00x279750HzLPF OUTPUTWORD RANGE0xD8B80x00x274860Hz0xD7AE0x00x2852PHASECALIBRATIONPHCAL[6:0]ΦANALOG INPUTRANGEVA0V0.5VGAINLPF1f3dB = 260Hz04443-049 Figure 49. ADC and Signal Processing in Voltage Channel VOLTAGE CHANNEL ADC Figure 49 shows the ADC and signal processing chain for the input VA in the voltage channel. The VB and VC channels have similar processing chains. For active and reactive energy measurements, the output of the ADC passes to the multipliers directly and is not filtered. This solution avoids the much larger multibit multiplier and does not affect the accuracy of the measurement. An HPF is not implemented on the voltage channel to remove the dc offset because the HPF on the current channel alone should be sufficient to eliminate error due to ADC offsets in the power calculation. However, ADC offset in the voltage channels produces large errors in the voltage rms calculation and affects the accuracy of the apparent energy calculation. Voltage Channel Sampling The waveform samples on the voltage channels can also be routed to the WFORM register. However, before passing to the WFORM register, the ADC outputs pass through a single-pole, low-pass filter (LPF1) with a cutoff frequency at 260 Hz. Figure 50 shows the magnitude and phase response of LPF1. This filter attenuates the signal slightly. For example, if the line frequency is 60 Hz, the signal at the output of LPF1 is attenuated by 3.575%. The waveform samples are 16-bit, twos complement data ranging between 0x2748 (+10,056d) and 0xD8B8 (−10,056d). The data is sign extended to 24-bit in the WFORM register. ()dB225.0974.0Hz260Hz60112−==⎟⎟⎠⎞⎜⎜⎝⎛+=fH (3) 0–20–40–60–800–10–20–30–40101001kFREQUENCY (Hz)PHASE (Degrees)GAIN (dB)(60Hz;–0.2dB)(60Hz;–13°)04443-050 Figure 50. Magnitude and Phase Response of LPF1 Note that LPF1 does not affect the active and reactive energy calculation because it is only used in the waveform sampling signal path. However, waveform samples are used for the voltage rms calculation and the subsequent apparent energy accumulation. The WAVSEL[2:0] bits in the WAVMODE register should be set to 001 (binary) to start the voltage waveform sampling. The PHSEL[1:0] bits control the phase from which the samples are routed. In waveform sampling mode, one of four output sample rates can be chosen by changing Bit 5 and Bit 6 of the WAVMODE register (see Table 20). The available output sample rates are 26.0 kSPS, 13.5 kSPS, 6.5 kSPS, or 3.3 kSPS. By setting the WFSM bit in the interrupt mask register to Logic 1, the interrupt request output IRQ goes active low when a sample is available. The 24-bit waveform samples are transferred from the one byte (8 bits) at a time, with the most significant byte shifted out first. ADE7758 The sign of the register is extended in the upper 8 bits. The timing is the same as for the current channels, as seen in Figure 40. Data Sheet ADE7758 Rev. E | Page 23 of 72 ZERO-CROSSING DETECTION The ADE7758 has zero-crossing detection circuits for each of the voltage channels (VAN, VBN, and VCN). Figure 51 shows how the zero-cross signal is generated from the output of the ADC of the voltage channel. REFERENCEADCZERO-CROSSINGDETECTORPGAVAN,VBN,VCNGAIN[6:5]×1,×2,×4LPF1f–3dB=260Hz24.8°@60HzANALOGVOLTAGEWAVEFORM(VAN,VBN, ORVCN)LPF1OUTPUTREADRSTATUSIRQ1.00.90804443-051 Figure 51. Zero-Crossing Detection on Voltage Channels The zero-crossing interrupt is generated from the output of LPF1. LPF1 has a single pole at 260 Hz (CLKIN = 10 MHz). As a result, there is a phase lag between the analog input signal of the voltage channel and the output of LPF1. The phase response of this filter is shown in the Voltage Channel Sampling section. The phase lag response of LPF1 results in a time delay of approximately 1.1 ms (at 60 Hz) between the zero crossing on the voltage inputs and the resulting zero-crossing signal. Note that the zero-crossing signal is used for the line cycle accumulation mode, zero-crossing interrupt, and line period/frequency measurement. When one phase crosses from negative to positive, the corresponding flag in the interrupt status register (Bit 9 to Bit 11) is set to Logic 1. An active low in the IRQ output also appears if the corresponding ZX bit in the interrupt mask register is set to Logic 1. Note that only zero crossing from negative to positive generates an interrupt. The flag in the interrupt status register is reset to 0 when the interrupt status register with reset (RSTATUS) is read. Each phase has its own interrupt flag and mask bit in the interrupt register. Zero-Crossing Timeout Each zero-crossing detection has an associated internal timeout register (not accessible to the user). This unsigned, 16-bit register is decreased by 1 every 384/CLKIN seconds. The registers are reset to a common user-programmed value, that is, the zero-crossing timeout register (ZXTOUT[15:0], Address 0x1B), every time a zero crossing is detected on its associated input. The default value of ZXTOUT is 0xFFFF. If the internal register decrements to 0 before a zero crossing at the corresponding input is detected, it indicates an absence of a zero crossing in the time determined by the ZXTOUT[15:0]. The ZXTOx detection bit of the corresponding phase in the interrupt status register is then switched on (Bit 6 to Bit 8). An active low on the IRQ output also appears if the ZXTOx mask bit for the corresponding phase in the interrupt mask register is set to Logic 1. shows the mechanism of the zero-crossing timeout detection when the Line Voltage A stays at a fixed dc level for more than 384/CLKIN × ZXTOUT[15:0] seconds. Figure 52ZXTOADETECTION BITREADRSTATUSVOLTAGECHANNEL AZXTOUT[15:0]16-BIT INTERNALREGISTER VALUE04443-052 Figure 52. Zero-Crossing Timeout Detection PHASE COMPENSATION When the HPF in the current channel is disabled, the phase error between the current channel (IA, IB, or IC) and the corresponding voltage channel (VA, VB, or VC) is negligible. When the HPF is enabled, the current channels have phase response (see Figure 53 through Figure 55). The phase response is almost 0 from 45 Hz to 1 kHz. The frequency band is sufficient for the requirements of typical energy measurement applications. However, despite being internally phase compensated, the ADE7758 must work with transducers that may have inherent phase errors. For example, a current transformer (CT) with a phase error of 0.1° to 0.3° is not uncommon. These phase errors can vary from part to part, and they must be corrected to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7758 provides a means of digitally calibrating these small phase errors. The ADE7758 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for the small phase errors. The phase calibration registers (APHCAL, BPHCAL, and CPHCAL) are twos complement, 7-bit sign-extended registers that can vary the time advance in the voltage channel signal path from +153.6 μs to −75.6 μs (CLKIN = 10 MHz), ADE7758 Data Sheet Rev. E | Page 24 of 72 407065605550450.200.150.100.050–0.05–0.10FREQUENCY (Hz)PHASE (Degrees)04443-054 respectively. Negative values written to the PHCAL registers represent a time advance, and positive values represent a time delay. One LSB is equivalent to 1.2 μs of time delay or 2.4 μs of time advance with a CLKIN of 10 MHz. With a line frequency of 60 Hz, this gives a phase resolution of 0.026° (360° × 1.2 μs × 60 Hz) at the fundamental in the positive direction (delay) and 0.052° in the negative direction (advance). This corresponds to a total correction range of −3.32° to +1.63° at 60 Hz. Figure 56 illustrates how the phase compensation is used to remove a 0.1° phase lead in IA of the current channel from the external current transducer. To cancel the lead (0.1°) in the current channel of Phase A, a phase lead must be introduced into the corresponding voltage channel. The resolution of the phase adjustment allows the introduction of a phase lead of 0.104°. The phase lead is achieved by introducing a time advance into VA. A time advance of 4.8 μs is made by writing −2 (0x7E) to the time delay block (APHCAL[6:0]), thus reducing the amount of time delay by 4.8 μs or equivalently, 360° × 4.8 μs × 60 Hz = 0.104° at 60 Hz. Figure 54. Phase Response of the HPF and Phase Compensation (40 Hz to 70 Hz) 445654525048460.100.080.060.040.020–0.02FREQUENCY (Hz)PHASE (Degrees)04443-055 01002003004005006007008001k9009001020304050607080FREQUENCY (Hz)PHASE (Degrees)04443-053 Figure 55. Phase Response of HPF and Phase Compensation (44 Hz to 56 Hz) Figure 53. Phase Response of the HPF and Phase Compensation (10 Hz to 1 kHz) Data Sheet ADE7758 Rev. E | Page 25 of 72 PGA1IAPIANIAADCHPFPGA2VAPVNVAADC60Hz0.1°IAVARANGE OF PHASECALIBRATION111110060APHCAL[6:0]–153.6μsTO +75.6μsVAVAADVANCED BY 4.8μs(+0.104° @ 60Hz)0x7EIA60HzDIGITALINTEGRATORACTIVE ANDREACTIVEENERGYCALCULATION+1.36°, –2.76° @ 50Hz; 0.022°, 0.043°+1.63°, –3.31° @ 60Hz; 0.026°, 0.052°04443-056 Figure 56. Phase Calibration on Voltage Channels PERIOD MEASUREMENT The ADE7758 provides the period or frequency measurement of the line voltage. The period is measured on the phase specified by Bit 0 to Bit 1 of the MMODE register. The period register is an unsigned 12-bit FREQ register and is updated every four periods of the selected phase. Bit 7 of the LCYCMODE selects whether the period register displays the frequency or the period. Setting this bit causes the register to display the period. The default setting is logic low, which causes the register to display the frequency. When set to measure the period, the resolution of this register is 96/CLKIN per LSB (9.6 μs/LSB when CLKIN is 10 MHz), which represents 0.06% when the line frequency is 60 Hz. At 60 Hz, the value of the period register is 1737d. At 50 Hz, the value of the period register is 2084d. When set to measure frequency, the value of the period register is approximately 960d at 60 Hz and 800d at 50 Hz. This is equivalent to 0.0625 Hz/LSB. LINE VOLTAGE SAG DETECTION The ADE7758 can be programmed to detect when the absolute value of the line voltage of any phase drops below a certain peak value for a number of half cycles. Each phase of the voltage channel is controlled simultaneously. This condition is illustrated in Figure 57. Figure 57 shows a line voltage fall below a threshold, which is set in the SAG level register (SAGLVL[7:0]), for nine half cycles. Because the SAG cycle register indicates a six half-cycle threshold (SAGCYC[7:0] = 0x06), the SAG event is recorded at the end of the sixth half cycle by setting the SAG flag of the corresponding phase in the interrupt status register (Bit 1 to Bit 3 in the interrupt status register). If the SAG enable bit is set to Logic 1 for this phase (Bit 1 to Bit 3 in the interrupt mask register), the IRQ logic output goes active low (see the section). The phases are compared to the same parameters defined in the SAGLVL and SAGCYC registers. InterruptsSAGLVL[7:0]FULL-SCALEREAD RSTATUSREGISTERSAGCYC[7:0]=0x066HALFCYCLESSAG INTERRUPT FLAG(BIT 3 TO BIT 5 OFSTATUS REGISTER)VAP, VBP, OR VCPSAG EVENT RESET LOWWHEN VOLTAGE CHANNELEXCEEDS SAGLVL[7:0]04443-057 Figure 57. ADE7758 SAG Detection Figure 57 shows a line voltage fall below a threshold, which is set in the SAG level register (SAGLVL[7:0]), for nine half cycles. Because the SAG cycle register indicates a six half-cycle threshold (SAGCYC[7:0] = 0x06), the SAG event is recorded at the end of the sixth half cycle by setting the SAG flag of the corresponding phase in the interrupt status register (Bit 1 to Bit 3 in the interrupt status register). If the SAG enable bit is set to Logic 1 for this phase (Bit 1 to Bit 3 in the interrupt mask register), the IRQ logic output goes active low (see the section). The phases are compared to the same parameters defined in the SAGLVL and SAGCYC registers. Interrupts ADE7758 Data Sheet Rev. E | Page 26 of 72 SAG LEVEL SET The contents of the single-byte SAG level register, SAGLVL[0:7], are compared to the absolute value of Bit 6 to Bit 13 from the voltage waveform samples. For example, the nominal maximum code of the voltage channel waveform samples with a full-scale signal input at 60 Hz is 0x2748 (see the Voltage Channel Sampling section). Bit 13 to Bit 6 are 0x9D. Therefore, writing 0x9D to the SAG level register puts the SAG detection level at full scale and sets the SAG detection to its most sensitive value. The detection is made when the content of the SAGLVL[7:0] register is greater than the incoming sample. Writing 0x00 puts the SAG detection level at 0. The detection of a decrease of an input voltage is disabled in this case. PEAK VOLTAGE DETECTION The ADE7758 can record the peak of the voltage waveform and produce an interrupt if the current exceeds a preset limit. Peak Voltage Detection Using the VPEAK Register The peak absolute value of the voltage waveform within a fixed number of half-line cycles is stored in the VPEAK register. Figure 58 illustrates the timing behavior of the peak voltage detection. L2L1CONTENT OFVPEAK[7:0]00L1L2L1NO. OF HALFLINE CYCLESSPECIFIED BYLINECYC[15:0]REGISTERVOLTAGE WAVEFORM(PHASE SELECTED BYPEAKSEL[2:4]IN MMODE REGISTER)04443-058 Figure 58. Peak Voltage Detection Using the VPEAK Register Note that the content of the VPEAK register is equivalent to Bit 6 to Bit 13 of the 16-bit voltage waveform sample. At full-scale analog input, the voltage waveform sample at 60 Hz is 0x2748. The VPEAK at full-scale input is, therefore, expected to be 0x9D. In addition, multiple phases can be activated for the peak detection simultaneously by setting multiple bits among the PEAKSEL[2:4] bits in the MMODE register. These bits select the phase for both voltage and current peak measurements. Note that if more than one bit is set, the VPEAK and IPEAK registers can hold values from two different phases, that is, the voltage and current peak are independently processed (see the Peak Current Detection section). Note that the number of half-line cycles is based on counting the zero crossing of the voltage channel. The ZXSEL[2:0] bits in the LCYCMODE register determine which voltage channels are used for the zero-crossing detection (see Table 22). The same signal is also used for line cycle energy accumulation mode if activated. Overvoltage Detection Interrupt Figure 59 illustrates the behavior of the overvoltage detection. VPINTLVL[7:0]READ RSTATUSREGISTERPKV INTERRUPT FLAG(BIT 14 OF STATUSREGISTER)PKV RESET LOWWHEN RSTATUSREGISTER IS READVOLTAGE PEAK WAVEFORM BEING MONITORED(SELECTED BY PKIRQSEL[5:7] IN MMODE REGISTER)04443-059 Figure 59. ADE7758 Overvoltage Detection Note that the content of the VPINTLVL[7:0] register is equivalent to Bit 6 to Bit 13 of the 16-bit voltage waveform samples; therefore, setting this register to 0x9D represents putting the peak detection at full-scale analog input. Figure 59 shows a voltage exceeding a threshold. By setting the PKV flag (Bit 14) in the interrupt status register, the overvoltage event is recorded. If the PKV enable bit is set to Logic 1 in the interrupt mask register, the IRQ logic output goes active low (see the section). Interrupts Multiple phases can be activated for peak detection. If any of the active phases produce waveform samples above the threshold, the PKV flag in the interrupt status register is set. The phase in which overvoltage is monitored is set by the PKIRQSEL[5:7] bits in the MMODE register (see Table 19). PHASE SEQUENCE DETECTION The ADE7758 has an on-chip phase sequence error detection interrupt. This detection works on phase voltages and considers all associated zero crossings. The regular succession of these zero crossings events is a negative to positive transition on Phase A, followed by a positive to negative transition on Phase C, followed by a negative to positive transition on Phase B, and so on. Data Sheet ADE7758 Rev. E | Page 27 of 72 On the ADE7758, if the regular succession of the zero crossings presented above happens, the SEQERR bit (Bit 19) in the STATUS register is set (Figure 60). If SEQERR is set in the mask register, the IRQ logic output goes active low (see the section). Interrupts If the regular zero crossing succession does not occur, that is when a negative to positive transition on Phase A followed by a positive to negative transition on Phase B, followed by a negative to positive transition on Phase C, and so on, the SEQERR bit (Bit 19) in the STATUS register is cleared to 0. To have the ADE7758 trigger SEQERR status bit when the zero crossing regular succession does not occur, the analog inputs for Phase C and Phase B should be swapped. In this case, the Phase B voltage input should be wired to the VCP pin, and the Phase C voltage input should be wired to the VBP pin. 04443-060ABSEQERR BIT OF STATUS REGISTER IS SETA = 0°B = –120°C = +120°CVOLTAGEWAVEFORMSZEROCROSSINGSCABCACAB Figure 60. Regular Phase Sequence Sets SEQERR Bit to 1 04443-160ACSEQERR BIT OF STATUS REGISTER IS NOT SETA = 0°C = –120°B = +120°BZEROCROSSINGSVOLTAGEWAVEFORMSBACBABAC Figure 61. Erroneous Phase Sequence Clears SEQERR Bit to 0 POWER-SUPPLY MONITOR The ADE7758 also contains an on-chip power-supply monitor. The analog supply (AVDD) is monitored continuously by the ADE7758. If the supply is less than 4 V ± 5%, the ADE7758 goes into an inactive state, that is, no energy is accumulated when the supply voltage is below 4 V. This is useful to ensure correct device operation at power-up and during power-down. The power-supply monitor has built-in hysteresis and filtering. This gives a high degree of immunity to false triggering due to noisy supplies. When AVDD returns above 4 V ± 5%, the ADE7758 waits 18 μs for the voltage to achieve the recommended voltage range, 5 V ± 5% and then becomes ready to function. Figure 62 shows the behavior of the ADE7758 when the voltage of AVDD falls below the power-supply monitor threshold. The power supply and decoupling for the part should be designed such that the ripple at AVDD does not exceed 5 V ± 5% as specified for normal operation. AVDD5V4V0VADE7758INTERNALCALCULATIONSACTIVEINACTIVEINACTIVETIME04443-061 Figure 62. On-Chip, Power-Supply Monitoring REFERENCE CIRCUIT The nominal reference voltage at the REFIN/OUT pin is 2.42 V. This is the reference voltage used for the ADCs in the ADE7758. However, the current channels have three input range selections (full scale is selectable among 0.5 V, 0.25 V, and 0.125 V). This is achieved by dividing the reference internally by 1, ½, and ¼. The reference value is used for the ADC in the current channels. Note that the full-scale selection is only available for the current inputs. The REFIN/OUT pin can be overdriven by an external source, for example, an external 2.5 V reference. Note that the nominal reference value supplied to the ADC is now 2.5 V and not 2.42 V. This has the effect of increasing the nominal analog input signal range by 2.5/2.42 × 100% = 3% or from 0.5 V to 0.5165 V. The voltage of the ADE7758 reference drifts slightly with temperature; see the Specifications section for the temperature coefficient specification (in ppm/°C). The value of the temperature drift varies from part to part. Because the reference is used for all ADCs, any ×% drift in the reference results in a 2×% deviation of the meter accuracy. The reference drift resulting from temperature changes is usually very small and typically much smaller than the drift of other components on a meter. Alternatively, the meter can be calibrated at multiple temperatures. TEMPERATURE MEASUREMENT The ADE7758 also includes an on-chip temperature sensor. A temperature measurement is made every 4/CLKIN seconds. The output from the temperature sensing circuit is connected to an ADC for digitizing. The resultant code is processed and placed in the temperature register (TEMP[7:0]). This register can be read by the user and has an address of 0x11 (see the Serial Interface section). The contents of the temperature register are signed (twos complement) with a resolution of 3°C/LSB. The offset of this register may vary significantly from part to part. To calibrate this register, the nominal value should be measured, and the equation should be adjusted accordingly. ADE7758 Data Sheet Rev. E | Page 28 of 72 Temp (°C) = [(TEMP[7:0] − Offset) × 3°C/LSB] + Ambient(°C) (4) For example, if the temperature register produces a code of 0x46 at ambient temperature (25°C), and the temperature register currently reads 0x50, then the temperature is 55°C : Temp (°C) = [(0x50 – 0x46) × 3°C/LSB] + 25°C = 55°C Depending on the nominal value of the register, some finite temperature can cause the register to roll over. This should be compensated for in the system master (MCU). The ADE7758 temperature register varies with power supply. It is recommended to use the temperature register only in applications with a fixed, stable power supply. Typical error with respect to power supply variation is show in Table 5. Table 5. Temperature Register Error with Power Supply Variation 4.5 V 4.75 V 5 V 5.25 V 5.5 V Register Value 219 216 214 211 208 % Error +2.34 +0.93 0 −1.40 −2.80 ROOT MEAN SQUARE MEASUREMENT Root mean square (rms) is a fundamental measurement of the magnitude of an ac signal. Its definition can be both practical and mathematical. Defined practically, the rms value assigned to an ac signal is the amount of dc required to produce an equivalent amount of power in the load. Mathematically, the rms value of a continuous signal f(t) is defined as ()dtT120TtfFRMS∫= (5) For time sampling signals, rms calculation involves squaring the signal, taking the average, and obtaining the square root. ][112nfNFRMSNnΣ== (6) The method used to calculate the rms value in the ADE7758 is to low-pass filter the square of the input signal (LPF3) and take the square root of the result (see Figure 63). i(t) = √2 × IRMS × sin(ωt) (7) then i2(t) = IRMS2 − IRMS2 × cos(ωt) (8) The rms calculation is simultaneously processed on the six analog input channels. Each result is available in separate registers. While the ADE7758 measures nonsinusoidal signals, it should be noted that the voltage rms measurement, and therefore the apparent energy, are bandlimited to 260 Hz. The current rms as well as the active power have a bandwidth of 14 kHz. Current RMS Calculation Figure 63 shows the detail of the signal processing chain for the rms calculation on one of the phases of the current channel. The current channel rms value is processed from the samples used in the current channel waveform sampling mode. The current rms values are stored in 24-bit registers (AIRMS, BIRMS, and CIRMS). One LSB of the current rms register is equivalent to one LSB of the current waveform sample. The update rate of the current rms measurement is CLKIN/12. SGN224223222216215214CURRENT SIGNALFROM HPF ORINTEGRATOR(IF ENABLED)0x1D37810x00++0x2851EC0x00xD7AE14X2LPF3AIRMS[23:0]AIRMSOS[11:0]04443-062 Figure 63. Current RMS Signal Processing With the specified full-scale analog input signal of 0.5 V, the ADC produces an output code that is approximately ±2,642,412d (see the Current Channel ADC section). The equivalent rms value of a full-scale sinusoidal signal at 60 Hz is 1,914,753 (0x1D3781). The accuracy of the current rms is typically 0.5% error from the full-scale input down to 1/500 of the full-scale input. Additionally, this measurement has a bandwidth of 14 kHz. It is recommended to read the rms registers synchronous to the voltage zero crossings to ensure stability. The IRQ can be used to indicate when a zero crossing has occurred (see the Interrupts section). Table 6 shows the settling time for the IRMS measurement, which is the time it takes for the rms register to reflect the value at the input to the current channel. Table 6. Settling Time for IRMS Measurement 63% 100% Integrator Off 80 ms 960 ms Integrator On 40 ms 1.68 sec Data Sheet ADE7758 Rev. E | Page 29 of 72 Current RMS Offset Compensation The ADE7758 incorporates a current rms offset compensation register for each phase (AIRMSOS, BIRMSOS, and CIRMSOS). These are 12-bit signed registers that can be used to remove offsets in the current rms calculations. An offset can exist in the rms calculation due to input noises that are integrated in the dc component of I2(t). Assuming that the maximum value from the current rms calculation is 1,914,753d with full-scale ac inputs (60 Hz), one LSB of the current rms offset represents 0.94% of the measurement error at 60 dB down from full scale. The IRMS measurement is undefined at zero input. Calibration of the offset should be done at low current and values at zero input should be ignored. For details on how to calibrate the current rms measurement, see the Calibration section. IRMS IRMS 2 IRMSOS 0    16384 (9) where IRMS0 is the rms measurement without offset correction. Table 7. Approximate IRMS Register Values Frequency (Hz) Integrator Off (d) Integrator On (d) 50 1,921,472 2,489,581 60 1,914,752 2,067,210 Voltage Channel RMS Calculation Figure 64 shows the details of the signal path for the rms estimation on Phase A of the voltage channel. This voltage rms estimation is done in the ADE7758 using the mean absolute value calculation, as shown in Figure 64.The voltage channel rms value is processed from the waveform samples after the low-pass filter LPF1. The output of the voltage channel ADC can be scaled by ±50% by changing VRMSGAIN[11:0] registers to perform an overall rms voltage calibration. The VRMSGAIN registers scale the rms calculations as well as the apparent energy calculation because apparent power is the product of the voltage and current rms values. The voltage rms values are stored in 24-bit registers (AVRMS, BVRMS, and CVRMS). One LSB of a voltage waveform sample is approximately equivalent to 256 LSBs of the voltage rms register. The update rate of the voltage rms measurement is CLKIN/12. With the specified full-scale ac analog input signal of 0.5 V, the LPF1 produces an output code that is approximately 63% of its full-scale value, that is, ±9,372d, at 60 Hz (see the Voltage Channel ADC section). The equivalent rms value of a full-scale ac signal is approximately 1,639,101 (0x1902BD) in the VRMS register. The accuracy of the VRMS measurement is typically 0.5% error from the full-scale input down to 1/20 of the full-scale input. Additionally, this measurement has a bandwidth of 260 Hz. It is recommended to read the rms registers synchronous to the voltage zero crossings to ensure stability. The IRQ can be used to indicate when a zero crossing has occurred (see the Interrupts section). VAN AVRMSGAIN[11:0] 0x2748 LPF OUTPUT WORD RANGE 0x0 60Hz 0xD8B8 0x2797 LPF OUTPUT WORD RANGE 0x0 50Hz 0xD869 LPF1 VOLTAGE SIGNAL–V(t) 0.5 GAIN 0x193504 50Hz 0x0 0x1902BD 60Hz 0x0 |X| AVRMS[23:0] LPF3 SGN216 215 214 28 27 26 VRMSOS[11:0] + + 04443-063 Figure 64. Voltage RMS Signal Processing Table 8 shows the settling time for the VRMS measurement, which is the time it takes for the rms register to reflect the value at the input to the voltage channel. Table 8. Settling Time for VRMS Measurement 63% 100% 100 ms 960 ms Voltage RMS Offset Compensation The ADE7758 incorporates a voltage rms offset compensation for each phase (AVRMSOS, BVRMSOS, and CVRMSOS). These are 12-bit signed registers that can be used to remove offsets in the voltage rms calculations. An offset can exist in the rms calculation due to input noises and offsets in the input samples. It should be noted that the offset calibration does not allow the contents of the VRMS registers to be maintained at 0 when no voltage is applied. This is caused by noise in the voltage rms calculation, which limits the usable range between full scale and 1/50th of full scale. One LSB of the voltage rms offset is equivalent to 64 LSBs of the voltage rms register. Assuming that the maximum value from the voltage rms calculation is 1,639,101d with full-scale ac inputs, then 1 LSB of the voltage rms offset represents 0.042% of the measurement error at 1/10 of full scale. VRMS = VRMS0 + VRMSOS × 64 (10) where VRMS0 is the rms measurement without the offset correction. Table 9. Approximate VRMS Register Values Frequency (Hz) Value (d) 50 1,678,210 60 1,665,118 ADE7758 Data Sheet Rev. E | Page 30 of 72 Voltage RMS Gain Adjust The ADC gain in each phase of the voltage channel can be adjusted for the rms calculation by using the voltage rms gain registers (AVRMSGAIN, BVRMSGAIN, and CVRMSGAIN). The gain of the voltage waveforms before LPF1 is adjusted by writing twos complement, 12-bit words to the voltage rms gain registers. Equation 11 shows how the gain adjustment is related to the contents of the voltage gain register.        212 ValuesWithout Gain 1 VRMSGAIN RMS Nominal VRMSRegister ofContent (11) For example, when 0x7FF is written to the voltage gain register, the RMS value is scaled up by 50%. 0x7FF = 2047d 2047/212 = 0.5 Similarly, when 0x800, which equals –2047d (signed twos complement), is written the ADC output is scaled by –50%. ACTIVE POWER CALCULATION Electrical power is defined as the rate of energy flow from source to load. It is given by the product of the voltage and current waveforms. The resulting waveform is called the instantaneous power signal and it is equal to the rate of energy flow at every instant of time. The unit of power is the watt or joules/sec. Equation 14 gives an expression for the instantaneous power signal in an ac system. v(t) = √2 × VRMS × sin(ωt) (12) i(t) = √2 × IRMS × sin(ωt) (13) where VRMS = rms voltage and IRMS = rms current. p(t) = v(t) × i(t) p(t) = IRMS × VRMS − IRMS × VRMS × cos(2ωt) (14) The average power over an integral number of line cycles (n) is given by the expression in Equation 15.   VRMS IRMS dttp nT p nT     0 1 (15) where: t is the line cycle period. P is referred to as the active or real power. Note that the active power is equal to the dc component of the instantaneous power signal p(t) in Equation 14, that is, VRMS × IRMS. This is the relationship used to calculate the active power in the ADE7758 for each phase. The instantaneous power signal p(t) is generated by multiplying the current and voltage signals in each phase. The dc component of the instantaneous power signal in each phase (A, B, and C) is then extracted by LPF2 (the low-pass filter) to obtain the average active power information on each phase. Figure 65 shows this process. The active power of each phase accumulates in the corresponding 16-bit watt-hour register (AWATTHR, BWATTHR, or CWATTHR). The input to each active energy register can be changed depending on the accumulation mode setting (see Table 22). INSTANTANEOUS POWER SIGNAL p(t) = VRMS×IRMS – VRMS×IRMS×cos(2ωt) ACTIVE REAL POWER SIGNAL = VRMS × IRMS 0x19999A VRMS ×IRMS 0xCCCCD 0x00000 CURRENT i(t) = 2 ×IRMS ×sin(ωt) VOLTAGE v(t) = 2 ×VRMS ×sin(ωt) 04443-064 Figure 65. Active Power Calculation Because LPF2 does not have an ideal brick wall frequency response (see Figure 66), the active power signal has some ripple due to the instantaneous power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Because the ripple is sinusoidal in nature, it is removed when the active power signal is integrated over time to calculate the energy. 0 –4 –8 –12 GAIN (dB) –16 –20 –24 1 3 18 0 FREQUENCY(Hz) 30 100 04443-065 Figure 66. Frequency Response of the LPF Used to Filter Instantaneous Power in Each Phase Data Sheet ADE7758 Rev. E | Page 31 of 72 Active Power Gain Calibration Note that the average active power result from the LPF output in each phase can be scaled by ±50% by writing to the phase’s watt gain register (AWG, BWG, or CWG). The watt gain registers are twos complement, signed registers and have a resolution of 0.024%/LSB. Equation 16 describes mathematically the function of the watt gain registers. ⎟⎠⎞⎜⎝⎛+×=12212gisterReGainWattOutputLPFDataPowerAverage (16) The REVPAP bit (Bit 17) in the interrupt status register is set if the average power from any one of the phases changes sign. The phases monitored are selected by TERMSEL bits in the COMPMODE register (see Table 21). The TERMSEL bits are also used to select which phases are included in the APCF and VARCF pulse outputs. If the REVPAP bit is set in the mask register, the IRQ logic output goes active low (see the section). Note that this bit is set whenever there are sign changes, that is, the REVPAP bit is set for both a positive-to-negative change and a negative-to-positive change of the sign bit. The response time of this bit is approximately 176 ms for a full-scale signal, which has an average value of 0xCCCCD at the low pass filter output. For smaller inputs, the time is longer. Interrupts The output is scaled by −50% by writing 0x800 to the watt gain registers and increased by +50% by writing 0x7FF to them. These registers can be used to calibrate the active power (or energy) calculation in the ADE7758 for each phase. CLKINValueAveragemsTimesponseRe4252601×⎥⎥⎦⎤⎢⎢⎣⎡+≅(17) Active Power Offset Calibration The APCFNUM [15:13] indicate reverse power on each of the individual phases. Bit 15 is set if the sign of the power on Phase A is negative, Bit 14 for Phase B, and Bit 13 for Phase C. The ADE7758 also incorporates a watt offset register on each phase (AWATTOS, BWATTOS, and CWATTOS). These are signed twos complement, 12-bit registers that are used to remove offsets in the active power calculations. An offset can exist in the power calculation due to crosstalk between channels on the PCB or in the chip itself. The offset calibration allows the contents of the active power register to be maintained at 0 when no power is being consumed. One LSB in the active power offset register is equivalent to 1/16 LSB in the active power multiplier output. At full-scale input, if the output from the multiplier is 0xCCCCD (838,861d), then 1 LSB in the LPF2 output is equivalent to 0.0075% of measurement error at 60 dB down from full scale on the current channel. At −60 dB down on full scale (the input signal level is 1/1000 of full-scale signal inputs), the average word value from LPF2 is 838.861 (838,861/1000). One LSB is equivalent to 1/838.861/16 × 100% = 0.0075% of the measured value. The active power offset register has a correction resolution equal to 0.0075% at −60 dB. No-Load Threshold The ADE7758 has an internal no-load threshold on each phase. The no-load threshold can be activated by setting the NOLOAD bit (Bit 7) of the COMPMODE register. If the active power falls below 0.005% of full-scale input, the energy is not accumulated in that phase. As stated, the average multiplier output with full-scale input is 0xCCCCD. Therefore, if the average multiplier output falls below 0x2A, the power is not accumulated to avoid creep in the meter. The no-load threshold is implemented only on the active energy accumulation. The reactive and apparent energies do not have the no-load threshold option. Active Energy Calculation As previously stated, power is defined as the rate of energy flow. This relationship can be expressed mathematically as dtdEnergyPower= (18) Sign of Active Power Calculation Note that the average active power is a signed calculation. If the phase difference between the current and voltage waveform is more than 90°, the average power becomes negative. Negative power indicates that energy is being placed back on the grid. The ADE7758 has a sign detection circuitry for active power calculation. Conversely, Energy is given as the integral of power. ()dtp∫=tEnergy (19) ADE7758 Data Sheet Rev. E | Page 32 of 72 AWG[11:0]WDIV[7:0]DIGITALINTEGRATORMULTIPLIERIVHPFCURRENT SIGNAL–i(t)0x2851EC0x000xD7AE14VOLTAGE SIGNAL–v(t)0x2852000x0xD7AE++++LPF2%SIGN26202–12–22–32–4AWATTOS[11:0]AWATTHR[15:0]150400TOTAL ACTIVE POWER ISACCUMULATED (INTEGRATED) INTHE ACTIVE ENERGY REGISTERTIME (nT)TAVERAGE POWERSIGNAL–P0xCCCCD0x00000PHCAL[6:0]Φ04443-066 Figure 67. ADE7758 Active Energy Accumulation The ADE7758 achieves the integration of the active power signal by continuously accumulating the active power signal in the internal 41-bit energy registers. The watt-hr registers (AWATTHR, BWATTHR, and CWATTHR) represent the upper 16 bits of these internal registers. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 20 expresses the relationship. ()()⎭⎬⎫⎩⎨⎧×==Σ∫∞=→00TLimnTnTpdttpEnergy (20) where: n is the discrete time sample number. T is the sample period. Figure 67 shows a signal path of this energy accumulation. The average active power signal is continuously added to the internal active energy register. This addition is a signed operation. Negative energy is subtracted from the active energy register. Note the values shown in Figure 67 are the nominal full-scale values, that is, the voltage and current inputs at the corresponding phase are at their full-scale input level. The average active power is divided by the content of the watt divider register before it is added to the corresponding watt-hr accumulation registers. When the value in the WDIV[7:0] register is 0 or 1, active power is accumulated without division. WDIV is an 8-bit unsigned register that is useful to lengthen the time it takes before the watt-hr accumulation registers overflow. Figure 68 shows the energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three displayed curves show the minimum time it takes for the watt-hr accumulation register to overflow when the watt gain register of the corre-sponding phase equals to 0x7FF, 0x000, and 0x800. The watt gain registers are used to carry out a power calibration in the ADE7758. As shown, the fastest integration time occurs when the watt gain registers are set to maximum full scale, that is, 0x7FF. This is the time it takes before overflow can be scaled by writing to the WDIV register and therefore can be increased by a maximum factor of 255. Note that the active energy register content can roll over to full-scale negative (0x8000) and continue increasing in value when the active power is positive (see Figure 67). Conversely, if the active power is negative, the energy register would under flow to full-scale positive (0x7FFF) and continue decreasing in value. By setting the AEHF bit (Bit 0) of the interrupt mask register, the ADE7758 can be configured to issue an interrupt (IRQ) when Bit 14 of any one of the three watt-hr accumulation registers has changed, indicating that the accumulation register is half full (positive or negative). Setting the RSTREAD bit (Bit 6) of the LCYMODE register enables a read-with-reset for the watt-hr accumulation registers, that is, the registers are reset to 0 after a read operation. CONTENTS OFWATT-HRACCUMULATION REGISTER0x7FFF0x3FFF0x00000xC0000x8000TIME (Sec)0.340.681.021.361.702.04WATT GAIN = 0x7FFWATT GAIN = 0x000WATT GAIN = 0x80004443-067 Figure 68. Energy Register Roll-Over Time for Full-Scale Power (Minimum and Maximum Power Gain) Data Sheet ADE7758 Rev. E | Page 33 of 72 Integration Time Under Steady Load The discrete time sample period (T) for the accumulation register is 0.4 μs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs and the watt gain registers set to 0x000, the average word value from each LPF2 is 0xCCCCD (see Figure 65 and Figure 67). The maximum value that can be stored in the watt-hr accumulation register before it overflows is 215 − 1 or 0x7FFF. Because the average word value is added to the internal register, which can store 240 − 1 or 0xFF, FFFF, FFFF before it overflows, the integration time under these conditions with WDIV = 0 is calculated as sec0.524μs0.40xCCCCDFFFFFFFF,0xFF,=×=Time (21) When WDIV is set to a value different from 0, the time before overflow is scaled accordingly as shown in Equation 22. Time = Time (WDIV = 0) × WDIV[7:0] (22) Energy Accumulation Mode The active power accumulated in each watt-hr accumulation register (AWATTHR, BWATTHR, or CWATTHR) depends on the configuration of the CONSEL bits in the COMPMODE register (Bit 0 and Bit 1). The different configurations are described in Table 10. Table 10. Inputs to Watt-Hr Accumulation Registers CONSEL[1, 0] AWATTHR BWATTHR CWATTHR 00 VA × IA VB × IB VC × IC 01 VA × (IA – IB) 0 VC × (IC – IB) 10 VA × (IA – IB) 0 VC × IC 11 Reserved Reserved Reserved Depending on the poly phase meter service, the appropriate formula should be chosen to calculate the active energy. The American ANSI C12.10 Standard defines the different configurations of the meter. Table 11 describes which mode should be chosen in these different configurations. Table 11. Meter Form Configuration ANSI Meter Form CONSEL (d) TERMSEL (d) 5S/13S 3-Wire Delta 0 3, 5, or 6 6S/14S 4-Wire Wye 1 7 8S/15S 4-Wire Delta 2 7 9S/16S 4-Wire Wye 0 7 Active Power Frequency Output Pin 1 (APCF) of the ADE7758 provides frequency output for the total active power. After initial calibration during manufac-turing, the manufacturer or end customer often verifies the energy meter calibration. One convenient way to verify the meter calibration is for the manufacturer to provide an output frequency that is proportional to the energy or active power under steady load conditions. This output frequency can provide a simple, single-wire, optically isolated interface to external calibration equipment. Figure 69 illustrates the energy-to-frequency conversion in the ADE7758. INPUTTOBWATTHRREGISTERINPUTTOAWATTHRREGISTERINPUTTOCWATTHRREGISTERDFCAPCFAPCFNUM[11:0]APCFDEN[11:0]÷+++÷404443-068 Figure 69. Active Power Frequency Output A digital-to-frequency converter (DFC) is used to generate the APCF pulse output from the total active power. The TERMSEL bits (Bit 2 to Bit 4) of the COMPMODE register can be used to select which phases to include in the total power calculation. Setting Bit 2, Bit 3, and Bit 4 includes the input to the AWATTHR, BWATTHR, and CWATTHR registers in the total active power calculation. The total active power is signed addition. However, setting the ABS bit (Bit 5) in the COMPMODE register enables the absolute-only mode; that is, only the absolute value of the active power is considered. The output from the DFC is divided down by a pair of frequency division registers before being sent to the APCF pulse output. Namely, APCFDEN/APCFNUM pulses are needed at the DFC output before the APCF pin outputs a pulse. Under steady load conditions, the output frequency is directly proportional to the total active power. The pulse width of APCF is 64/CLKIN if APCFNUM and APCFDEN are both equal. If APCFDEN is greater than APCFNUM, the pulse width depends on APCFDEN. The pulse width in this case is T × (APCFDEN/2), where T is the period of the APCF pulse and APCFDEN/2 is rounded to the nearest whole number. An exception to this is when the period is greater than 180 ms. In this case, the pulse width is fixed at 90 ms. The maximum output frequency (APCFNUM = 0x00 and APCFDEN = 0x00) with full-scale ac signals on one phase is approximately 16 kHz. The ADE7758 incorporates two registers to set the frequency of APCF (APCFNUM[11:0] and APCFDEN[11:0]). These are unsigned 12-bit registers that can be used to adjust the frequency of APCF by 1/212 to 1 with a step of 1/212. For example, if the output frequency is 1.562 kHz while the contents of APCFDEN are 0 (0x000), then the output frequency can be set to 6.103 Hz by writing 0xFF to the APCFDEN register. If 0 were written to any of the frequency division registers, the divider would use 1 in the frequency division. In addition, the ratio APCFNUM/APCFDEN should be set not greater than 1 to ensure proper operation. In other words, the APCF output frequency cannot be higher than the frequency on the DFC output. The output frequency has a slight ripple at a frequency equal to 2× the line frequency. This is due to imperfect filtering of the instantaneous power signal to generate the active power signal ADE7758 Data Sheet Rev. E | Page 34 of 72 (see the Active Power Calculation section). Equation 14 gives an expression for the instantaneous power signal. This is filtered by LPF2, which has a magnitude response given by Equation 23. ()22811Hff+= (23) –E(t)tVltVI×cos(4π×f1 ×t)4π×f11 +22f1804443-069 The active power signal (output of the LPF2) can be rewritten as ()()(tffIRMSVRMSIRMSVRMStp12214cos821π×⎥⎥⎥⎥⎦⎤⎢⎢⎢⎢⎣⎡+×−×= (24) Figure 70. Output Frequency Ripple where f1 is the line frequency, for example, 60 Hz. Line Cycle Active Energy Accumulation Mode From Equation 24, E(t) equals The ADE7758 is designed with a special energy accumulation mode that simplifies the calibration process. By using the on-chip, zero-crossing detection, the ADE7758 updates the watt-hr accumulation registers after an integer number of zero crossings (see Figure 71). The line-active energy accumulation mode for watt-hr accumulation is activated by setting the LWATT bit (Bit 0) of the LCYCMODE register. The total energy accumu-lated over an integer number of half-line cycles is written to the watt-hr accumulation registers after the LINECYC number of zero crossings is detected. When using the line cycle accumulation mode, the RSTREAD bit (Bit 6) of the LCYCMODE register should be set to Logic 0. ())4cos(8214–12211tfffIRMSVRMStIRMSVRMSππ×⎥⎥⎥⎥⎥⎦⎤⎢⎢⎢⎢⎢⎣⎡+××× (25) From Equation 25, it can be seen that there is a small ripple in the energy calculation due to the sin(2ωt) component (see Figure 70). The ripple gets larger with larger loads. Choosing a lower output frequency for APCF during calibration by using a large APCFDEN value and keeping APCFNUM relatively small can significantly reduce the ripple. Averaging the output frequency over a longer period achieves the same results. ZXSEL01ZERO-CROSSINGDETECTION(PHASEA)ZXSEL11ZERO-CROSSINGDETECTION(PHASEB)ZXSEL21ZERO-CROSSINGDETECTION(PHASEC)1ZXSEL[0:2]AREBITS3TO5 INTHELCYCMODEREGISTERCALIBRATIONCONTROLLINECYC[15:0]WATTOS[11:0]WG[11:0]WDIV[7:0]++%++WATTHR[15:0]ACCUMULATEACTIVEPOWERFORLINECYCNUMBER OFZERO-CROSSINGS;WATT-HRACCUMULATIONREGISTERSAREUPDATED ONCEEVERYLINECYCNUMBER OFZERO-CROSSINGSACTIVEPOWER15040004443-070 Figure 71. ADE7758 Line Cycle Active Energy Accumulation Mode Data Sheet ADE7758 Rev. E | Page 35 of 72 Phase A, Phase B, and Phase C zero crossings are, respectively, included when counting the number of half-line cycles by setting ZXSEL[0:2] bits (Bit 3 to Bit 5) in the LCYCMODE register. Any combination of the zero crossings from all three phases can be used for counting the zero crossing. Only one phase should be selected at a time for inclusion in the zero crossings count during calibration (see the Calibration section). The number of zero crossings is specified by the LINECYC register. LINECYC is an unsigned 16-bit register. The ADE7758 can accumulate active power for up to 65535 combined zero crossings. Note that the internal zero-crossing counter is always active. By setting the LWATT bit, the first energy accumulation result is, therefore, incorrect. Writing to the LINECYC register when the LWATT bit is set resets the zero-crossing counter, thus ensuring that the first energy accumulation result is accurate. At the end of an energy calibration cycle, the LENERGY bit (Bit 12) in the STATUS register is set. If the corresponding mask bit in the interrupt mask register is enabled, the IRQ output also goes active low; thus, the IRQ can also be used to signal the end of a calibration. Because active power is integrated on an integer number of half-line cycles in this mode, the sinusoidal component is reduced to 0, eliminating any ripple in the energy calculation. Therefore, total energy accumulated using the line-cycle accumulation mode is E(t) = VRMS × IRMS × t (26) where t is the accumulation time. Note that line cycle active energy accumulation uses the same signal path as the active energy accumulation. The LSB size of these two methods is equivalent. Using the line cycle accumula-tion to calculate the kWh/LSB constant results in a value that can be applied to the WATTHR registers when the line accumulation mode is not selected (see the Calibration section). REACTIVE POWER CALCULATION A load that contains a reactive element (inductor or capacitor) produces a phase difference between the applied ac voltage and the resulting current. The power associated with reactive elements is called reactive power, and its unit is VAR. Reactive power is defined as the product of the voltage and current waveforms when one of these signals is phase shifted by 90°. Equation 30 gives an expression for the instantaneous reactive power signal in an ac system when the phase of the current channel is shifted by +90°. ()(θ=–sin2ωtVtv (27) ()()()⎟⎠⎞⎜⎝⎛π+=′=2sin2isin2ωtItωtIti (28) where: v = rms voltage. i = rms current. θ = total phase shift caused by the reactive elements in the load. Then the instantaneous reactive power q(t) can be expressed as ()()()()⎟⎠⎞⎜⎝⎛πθ⎟⎠⎞⎜⎝⎛πθ=′×=2––2cos–2––cosωtVIVItqtitvtq (29) where ()ti′ is the current waveform phase shifted by 90°. Note that q(t) can be rewritten as ()()(θ +θ=–2sinsinωtVIVItq (30) The average reactive power over an integral number of line cycles (n) is given by the expression in Equation 31. ()()∫××==nT0θsindtnT1IVtqQ (31) where: T is the period of the line cycle. Q is referred to as the average reactive power. The instantaneous reactive power signal q(t) is generated by multiplying the voltage signals and the 90° phase-shifted current in each phase. The dc component of the instantaneous reactive power signal in each phase (A, B, and C) is then extracted by a low-pass filter to obtain the average reactive power information on each phase. This process is illustrated in Figure 72. The reactive power of each phase is accumulated in the corresponding 16-bit VAR-hour register (AVARHR, BVARHR, or CVARHR). The input to each reactive energy register can be changed depending on the accumulation mode setting (see Table 21). The frequency response of the LPF in the reactive power signal path is identical to that of the LPF2 used in the average active power calculation (see Figure 66). VRMS × IRMS × sin(φ)θ0x00000CURRENTi(t) = 2×IRMS×sin(ωt)VOLTAGEv(t) = 2×VRMS×sin(ωt –θ)INSTANTANEOUSREACTIVE POWER SIGNALq(t) = VRMS × IRMS × sin(φ) + VRMS × IRMS × sin(2ωt + θ)AVERAGE REACTIVE POWER SIGNAL =VRMS × IRMS × sin(θ)04443-071 Figure 72. Reactive Power Calculation The low-pass filter is nonideal, so the reactive power signal has some ripple. This ripple is sinusoidal and has a frequency equal to 2× the line frequency. Because the ripple is sinusoidal in nature, it is removed when the reactive power signal is integrated over time to calculate the reactive energy. ADE7758 Data Sheet Rev. E | Page 36 of 72 The phase-shift filter has –90° phase shift when the integrator is enabled and +90° phase shift when the integrator is disabled. In addition, the filter has a nonunity magnitude response. Because the phase-shift filter has a large attenuation at high frequency, the reactive power is primarily for the calculation at line frequency. The effect of harmonics is largely ignored in the reactive power calculation. Note that because of the magnitude characteristic of the phase shifting filter, the LSB weight of the reactive power calculation is slightly different from that of the active power calculation (see the Energy Registers Scaling section). The ADE7758 uses the line frequency of the phase selected in the FREQSEL[1:0] bits of the MMODE[1:0] to compensate for attenuation of the reactive energy phase shift filter over frequency (see the Period Measurement section). Reactive Power Gain Calibration The average reactive power from the LPF output in each phase can be scaled by ±50% by writing to the phase’s VAR gain register (AVARG, BVARG, or CVARG). The VAR gain registers are twos complement, signed registers and have a resolution of 0.024%/LSB. The function of the VAR gain registers is expressed by ⎟⎠⎞⎜⎝⎛+×=12212gisterReGainVAROutputLPFPowerReactiveAverage (32) The output is scaled by –50% by writing 0x800 to the VAR gain registers and increased by +50% by writing 0x7FF to them. These registers can be used to calibrate the reactive power (or energy) calculation in the ADE7758 for each phase. Reactive Power Offset Calibration The ADE7758 incorporates a VAR offset register on each phase (AVAROS, BVAROS, and CVAROS). These are signed twos complement, 12-bit registers that are used to remove offsets in the reactive power calculations. An offset can exist in the power calculation due to crosstalk between channels on the PCB or in the chip itself. The offset calibration allows the contents of the reactive power register to be maintained at 0 when no reactive power is being consumed. The offset registers’ resolution is the same as the active power offset registers (see the Apparent Power Offset Calibration section). Sign of Reactive Power Calculation Note that the average reactive power is a signed calculation. As stated previously, the phase shift filter has –90° phase shift when the integrator is enabled and +90° phase shift when the integrator is disabled. Table 12 summarizes the relationship between the phase difference between the voltage and the current and the sign of the resulting VAR calculation. The ADE7758 has a sign detection circuit for the reactive power calculation. The REVPRP bit (Bit 18) in the interrupt status register is set if the average reactive power from any one of the phases changes. The phases monitored are selected by TERMSEL bits in the COMPMODE register (see Table 21). If the REVPRP bit is set in the mask register, the IRQ logic output goes active low (see the section). Note that this bit is set whenever there is a sign change; that is, the bit is set for either a positive-to-negative change or a negative-to-positive change of the sign bit. The response time of this bit is approximately 176 ms for a full-scale signal, which has an average value of 0xCCCCD at the low-pass filter output. For smaller inputs, the time is longer. InterruptsCLKINueAverageValmssponseTimeRe4260125×⎥⎦⎤⎢⎣⎡+≅ (33) Table 12. Sign of Reactive Power Calculation Φ1 Integrator Sign of Reactive Power Between 0 to +90 Off Positive Between −90 to 0 Off Negative Between 0 to +90 On Positive Between −90 to 0 On Negative 1 Φ is defined as the phase angle of the voltage signal minus the current signal; that is, Φ is positive if the load is inductive and negative if the load is capacitive. Reactive Energy Calculation Reactive energy is defined as the integral of reactive power. ()dttqEnergyReactive∫= (34) Similar to active power, the ADE7758 achieves the integration of the reactive power signal by continuously accumulating the reactive power signal in the internal 41-bit accumulation registers. The VAR-hr registers (AVARHR, BVARHR, and CVARHR) represent the upper 16 bits of these internal registers. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 35 expresses the relationship ()()⎭⎬⎫⎩⎨⎧×==Σ∫∞=→0n0LimdtTnTqtqEnergyReactiveT (35) where: n is the discrete time sample number. T is the sample period. Figure 73 shows the signal path of the reactive energy accumula-tion. The average reactive power signal is continuously added to the internal reactive energy register. This addition is a signed operation. Negative energy is subtracted from the reactive energy register. The average reactive power is divided by the content of the VAR divider register before it is added to the corresponding VAR-hr accumulation registers. When the value in the VARDIV[7:0] register is 0 or 1, the reactive power is accumulated without any division. VARDIV is an 8-bit unsigned register that is useful to lengthen the time it takes before the VAR-hr accumulation registers overflow. Data Sheet ADE7758 Rev. E | Page 37 of 72 Similar to reactive power, the fastest integration time occurs when the VAR gain registers are set to maximum full scale, that is, 0x7FF. The time it takes before overflow can be scaled by writing to the VARDIV register; and, therefore, it can be increased by a maximum factor of 255. By setting the REHF bit (Bit 1) of the interrupt mask register, the ADE7758 can be configured to issue an interrupt (IRQ) when Bit 14 of any one of the three VAR-hr accumulation registers has changed, indicating that the accumulation register is half full (positive or negative). When overflow occurs, the VAR-hr accumulation registers content can rollover to full-scale negative (0x8000) and continue increasing in value when the reactive power is positive. Con-versely, if the reactive power is negative, the VAR-hr accumulation registers content can roll over to full-scale positive (0x7FFF) and continue decreasing in value. Setting the RSTREAD bit (Bit 6) of the LCYMODE register enables a read-with-reset for the VAR-hr accumulation registers; that is, the registers are reset to 0 after a read operation. VARG[11:0]VARDIV[7:0]90°PHASESHIFTINGFILTERMULTIPLIERIVHPFCURRENTSIGNAL–i(t)0x2851EC0x000xD7AE14VOLTAGESIGNAL–v(t)0x28520x000xD7AE++++LPF2%SIGN26202–12–22–32–4VAROS[11:0]VARHR[15:0]150400TOTALREACTIVEPOWER ISACCUMULATED(INTEGRATED) INTHEVAR-HRACCUMULATIONREGISTERSπ2PHCAL[6:0]Φ04443-072 Figure 73. ADE7758 Reactive Energy Accumulation ADE7758 Data Sheet Rev. E | Page 38 of 72 Integration Time Under Steady Load The discrete time sample period (T) for the accumulation register is 0.4 μs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs, a 90° phase difference between the voltage and the current signal (the largest possible reactive power), and the VAR gain registers set to 0x000, the average word value from each LPF2 is 0xCCCCD. The maximum value that can be stored in the reactive energy register before it overflows is 215 − 1 or 0x7FFF. Because the average word value is added to the internal register, which can store 240 − 1 or 0xFF, FFFF, FFFF before it overflows, the integration time under these conditions with VARDIV = 0 is calculated as sec0.5243μs0.40xCCCCDFFFFFFFF,0xFF,=×=Time (36) When VARDIV is set to a value different from 0, the time before overflow are scaled accordingly as shown in Equation 37. Time = Time(VARDIV = 0) × VARDIV (37) Energy Accumulation Mode The reactive power accumulated in each VAR-hr accumulation register (AVARHR, BVARHR, or CVARHR) depends on the configuration of the CONSEL bits in the COMPMODE register (Bit 0 and Bit 1). The different configurations are described in Table 13. Note that IA’/IB’/IC’ are the current phase-shifted current waveform. Table 13. Inputs to VAR-Hr Accumulation Registers CONSEL[1, 0] AVARHR BVARHR CVARHR 00 VA × IA’ VB × IB VC × IC’ 01 VA (IA’ – IB’) 0 VC (IC’ – IB’) 10 VA (IA’ – IB’) 0 VC × IC’ 11 Reserved Reserved Reserved Reactive Power Frequency Output Pin 17 (VARCF) of the ADE7758 provides frequency output for the total reactive power. Similar to APCF, this pin provides an output frequency that is directly proportional to the total reactive power. The pulse width of VARPCF is 64/CLKIN if VARCFNUM and VARCFDEN are both equal. If VARCFDEN is greater than VARCFNUM, the pulse width depends on VARCFDEN. The pulse width in this case is T × (VARCFDEN/2), where T is the period of the VARCF pulse and VARCFDEN/2 is rounded to the nearest whole number. An exception to this is when the period is greater than 180 ms. In this case, the pulse width is fixed at 90 ms. A digital-to-frequency converter (DFC) is used to generate the VARCF pulse output from the total reactive power. The TERMSEL bits (Bit 2 to Bit 4) of the COMPMODE register can be used to select which phases to include in the total reactive power calcu-lation. Setting Bit 2, Bit 3, and Bit 4 includes the input to the AVARHR, BVARHR, and CVARHR registers in the total reactive power calculation. The total reactive power is signed addition. However, setting the SAVAR bit (Bit 6) in the COMPMODE register enables absolute value calculation. If the active power of that phase is positive, no change is made to the sign of the reactive power. However, if the sign of the active power is negative in that phase, the sign of its reactive power is inverted before summing and creating VARCF pulses. This mode should be used in conjunction with the absolute value mode for active power (Bit 5 in the COMPMODE register) for APCF pulses. The effects of setting the ABS and SAVAR bits of the COMPMODE register are as follows when ABS = 1 and SAVAR = 1: If watt > 0, APCF = Watts, VARCF = +VAR. If watt < 0, APCF = |Watts|, VARCF = −VAR. INPUTTO BVARHRREGISTERINPUTTOAVARHRREGISTERINPUTTO CVARHRREGISTER+++INPUTTO BVAHRREGISTERINPUTTOAVAHRREGISTERINPUTTO CVAHRREGISTER+++01VARCFVARCFNUM[11:0]VARCFDEN[11:0]÷DFCVACF BIT (BIT 7) OFWAVMODE REGISTER÷404443-073 Figure 74. Reactive Power Frequency Output The output from the DFC is divided down by a pair of frequency division registers before sending to the VARCF pulse output. Namely, VARCFDEN/VARCFNUM pulses are needed at the DFC output before the VARCF pin outputs a pulse. Under steady load conditions, the output frequency is directly proportional to the total reactive power. Figure 74 illustrates the energy-to-frequency conversion in the ADE7758. Note that the input to the DFC can be selected between the total reactive power and total apparent power. Therefore, the VARCF pin can output frequency that is proportional to the total reactive power or total apparent power. The selection is made by setting the VACF bit (Bit 7) in the WAVMODE register. Setting this bit switches the input to the total apparent power. The default value of this bit is logic low. Therefore, the default output from the VARCF pin is the total reactive power. All other operations of this frequency output are similar to that of the active power frequency output (see the Active Power Frequency Output section). Line Cycle Reactive Energy Accumulation Mode The line cycle reactive energy accumulation mode is activated by setting the LVAR bit (Bit 1) in the LCYCMODE register. The total reactive energy accumulated over an integer number of zero crossings is written to the VAR-hr accumulation registers after the LINECYC number of zero crossings is detected. The operation of this mode is similar to watt-hr accumulation (see the Line Cycle Active Energy Accumulation Mode section). Data Sheet ADE7758 Rev. E | Page 39 of 72 When using the line cycle accumulation mode, the RSTREAD bit (Bit 6) of the LCYCMODE register should be set to Logic 0. APPARENT POWER CALCULATION Apparent power is defined as the amplitude of the vector sum of the active and reactive powers. Figure 75 shows what is typically referred to as the power triangle. REACTIVE POWERACTIVE POWERAPPARENTPOWERθ04443-074 Figure 75. Power Triangle There are two ways to calculate apparent power: the arithmetical approach or the vectorial method. The arithmetical approach uses the product of the voltage rms value and current rms value to calculate apparent power. Equation 38 describes the arithmetical approach mathematically. S = VRMS × IRMS (38) where S is the apparent power, and VRMS and IRMS are the rms voltage and current, respectively. The vectorial method uses the square root of the sum of the active and reactive power, after the two are individually squared. Equation 39 shows the calculation used in the vectorial approach. 22QPS+= (39) where: S is the apparent power. P is the active power. Q is the reactive power. For a pure sinusoidal system, the two approaches should yield the same result. The apparent energy calculation in the ADE7758 uses the arithmetical approach. However, the line cycle energy accumulation mode in the ADE7758 enables energy accumula-tion between active and reactive energies over a synchronous period, thus the vectorial method can be easily implemented in the external MCU (see the Line Cycle Active Energy Accumulation Mode section). Note that apparent power is always positive regardless of the direction of the active or reactive energy flows. The rms value of the current and voltage in each phase is multiplied to produce the apparent power of the corresponding phase. The output from the multiplier is then low-pass filtered to obtain the average apparent power. The frequency response of the LPF in the apparent power signal path is identical to that of the LPF2 used in the average active power calculation (see Figure 66). Apparent Power Gain Calibration Note that the average active power result from the LPF output in each phase can be scaled by ±50% by writing to the phase’s VAGAIN register (AVAG, BVAG, or CVAG). The VAGAIN registers are twos complement, signed registers and have a resolution of 0.024%/LSB. The function of the VAGAIN registers is expressed mathematically as ⎟⎠⎞⎜⎝⎛+×=12212RegisterVAGAINOutputLPFPowerApparentAverage (40) The output is scaled by –50% by writing 0x800 to the VAR gain registers and increased by +50% by writing 0x7FF to them. These registers can be used to calibrate the apparent power (or energy) calculation in the ADE7758 for each phase. Apparent Power Offset Calibration Each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value (see the Current RMS Calculation section and the Voltage Channel RMS Calculation section). The voltage and current rms values are then multiplied together in the apparent power signal processing. As no additional offsets are created in the multiplication of the rms values, there is no specific offset compensation in the apparent power signal processing. The offset compensation of the apparent power measurement in each phase should be done by calibrating each individual rms measurement (see the Calibration section). ADE7758 Data Sheet Rev. E | Page 40 of 72 Apparent Energy Calculation Apparent energy is defined as the integral of apparent power. Apparent Energy = ∫ S(t)dt (41) Similar to active or reactive power accumulation, the fastest integration time occurs when the VAGAIN registers are set to maximum full scale, that is, 0x7FF. When overflow occurs, the content of the VA-hr accumulation registers can roll over to 0 and continue increasing in value. Similar to active and reactive energy, the ADE7758 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in the internal 41-bit, unsigned accumulation registers. The VA-hr registers (AVAHR, BVAHR, and CVAHR) represent the upper 16 bits of these internal registers. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 42 expresses the relationship By setting the VAEHF bit (Bit 2) of the mask register, the ADE7758 can be configured to issue an interrupt (IRQ) when the MSB of any one of the three VA-hr accumulation registers has changed, indicating that the accumulation register is half full. Setting the RSTREAD bit (Bit 6) of the LCYMODE register enables a read-with-reset for the VA-hr accumulation registers; that is, the registers are reset to 0 after a read operation. ()()⎭⎬⎫⎩⎨⎧×==Σ∫∞=→0n0TLimdtTnTStSEnergyApparent (42) Integration Time Under Steady Load The discrete time sample period (T) for the accumulation register is 0.4 μs (4/CLKIN). With full-scale, 60 Hz sinusoidal signals on the analog inputs and the VAGAIN registers set to 0x000, the average word value from each LPF2 is 0xB9954. The maximum value that can be stored in the apparent energy register before it overflows is 216 − 1 or 0xFFFF. As the average word value is first added to the internal register, which can store 241 − 1 or 0x1FF, FFFF, FFFF before it overflows, the integration time under these conditions with VADIV = 0 is calculated as where: n is the discrete time sample number. T is the sample period. Figure 76 shows the signal path of the apparent energy accumu-lation. The apparent power signal is continuously added to the internal apparent energy register. The average apparent power is divided by the content of the VA divider register before it is added to the corresponding VA-hr accumulation register. When the value in the VADIV[7:0] register is 0 or 1, apparent power is accumulated without any division. VADIV is an 8-bit unsigned register that is useful to lengthen the time it takes before the VA-hr accumulation registers overflow. sec1.157μs0.40xB9954FFFFFFFF,0x1FF,=×=Time (43) When VADIV is set to a value different from 0, the time before overflow is scaled accordingly, as shown in Equation 44. Time = Time(VADIV = 0) × VADIV (44) VOLTAGE RMS SIGNAL0x174BAC60Hz0x00x17F26350Hz0x0CURRENT RMS SIGNAL0x1C82B0x00MULTIPLIERIRMSVRMSVAG[11:0]VADIV[7:0]++LPF2%VARHR[15:0]150400APPARENT POWER ISACCUMULATED (INTEGRATED) INTHE VA-HR ACCUMULATION REGISTERS04443-075 Figure 76. ADE7758 Apparent Energy Accumulation Data Sheet ADE7758 Rev. E | Page 41 of 72 Table 14. Inputs to VA-Hr Accumulation Registers CONSEL[1, 0] AVAHR1 BVAHR CVAHR 00 AVRMS × AIRMS BVRMS × BIRMS CVRMS × CIRMS 01 AVRMS × AIRMS AVRMS + CVRMS/2 × BIRMS CVRMS × CIRMS 10 AVRMS × AIRMS BVRMS × BIRMS CVRMS × CIRMS 11 Reserved Reserved Reserved 1 AVRMS/BVRMS/CVRMS are the rms voltage waveform, and AIRMS/BIRMS/CIRMS are the rms values of the current waveform. Energy Accumulation Mode The apparent power accumulated in each VA-hr accumulation register (AVAHR, BVAHR, or CVAHR) depends on the con- figuration of the CONSEL bits in the COMPMODE register (Bit 0 and Bit 1). The different configurations are described in Table 14. The contents of the VA-hr accumulation registers are affected by both the registers for rms voltage gain (VRMSGAIN), as well as the VAGAIN register of the corresponding phase. Apparent Power Frequency Output Pin 17 (VARCF) of the ADE7758 provides frequency output for the total apparent power. By setting the VACF bit (Bit 7) of the WAVMODE register, this pin provides an output frequency that is directly proportional to the total apparent power. A digital-to-frequency converter (DFC) is used to generate the pulse output from the total apparent power. The TERMSEL bits (Bit 2 to Bit 4) of the COMPMODE register can be used to select which phases to include in the total power calculation. Setting Bit 2, Bit 3, and Bit 4 includes the input to the AVAHR, BVAHR, and CVAHR registers in the total apparent power calculation. A pair of frequency divider registers, namely VARCFDEN and VARCFNUM, can be used to scale the output frequency of this pin. Note that either VAR or apparent power can be selected at one time for this frequency output (see the Reactive Power Frequency Output section). Line Cycle Apparent Energy Accumulation Mode The line cycle apparent energy accumulation mode is activated by setting the LVA bit (Bit 2) in the LCYCMODE register. The total apparent energy accumulated over an integer number of zero crossings is written to the VA-hr accumulation registers after the LINECYC number of zero crossings is detected. The operation of this mode is similar to watt-hr accumulation (see the Line Cycle Active Energy Accumulation Mode section). When using the line cycle accumulation mode, the RSTREAD bit (Bit 6) of the LCYCMODE register should be set to Logic 0. Note that this mode is especially useful when the user chooses to perform the apparent energy calculation using the vectorial method. By setting LWATT and LVAR bits (Bit 0 and Bit 1) of the LCYCMODE register, the active and reactive energies are accumulated over the same period. Therefore, the MCU can perform the squaring of the two terms and then take the square root of their sum to determine the apparent energy over the same period. ENERGY REGISTERS SCALING The ADE7758 provides measurements of active, reactive, and apparent energies that use separate signal paths and filtering for calculation. The differences in the datapaths can result in small differences in LSB weight between the active, reactive, and apparent energy registers. These measurements are internally compensated so that the scaling is nearly one to one. The relationship between the registers is shown in Table 15. Table 15. Energy Registers Scaling Frequency 60 Hz 50 Hz Integrator Off VAR 1.004 × WATT 1.0054 × WATT VA 1.00058 × WATT 1.0085 × WATT Integrator On VAR 1.0059 × WATT 1.0064 × WATT VA 1.00058 × WATT 1.00845 × WATT WAVEFORM SAMPLING MODE The waveform samples of the current and voltage waveform, as well as the active, reactive, and apparent power multiplier out- puts, can all be routed to the WAVEFORM register by setting the WAVSEL[2:0] bits (Bit 2 to Bit 4) in the WAVMODE register. The phase in which the samples are routed is set by setting the PHSEL[1:0] bits (Bit 0 and Bit 1) in the WAVMODE register. All energy calculation remains uninterrupted during waveform sampling. Four output sample rates can be chosen by using Bit 5 and Bit 6 of the WAVMODE register (DTRT[1:0]). The output sample rate can be 26.04 kSPS, 13.02 kSPS, 6.51 kSPS, or 3.25 kSPS (see Table 20). By setting the WFSM bit in the interrupt mask register to Logic 1, the interrupt request output IRQ goes active low when a sample is available. The 24-bit waveform samples are transferred from the ADE7758 one byte (8 bits) at a time, with the most significant byte shifted out first. The interrupt request output IRQ stays low until the interrupt routine reads the reset status register (see the Interrupts section). ADE7758 Data Sheet Rev. E | Page 42 of 72 CALIBRATION A reference meter or an accurate source is required to calibrate the ADE7758 energy meter. When using a reference meter, the ADE7758 calibration output frequencies APCF and VARCF are adjusted to match the frequency output of the reference meter under the same load conditions. Each phase must be calibrated separately in this case. When using an accurate source for calibration, one can take advantage of the line cycle accumulation mode and calibrate the three phases simultaneously. There are two objectives in calibrating the meter: to establish the correct impulses/kW-hr constant on the pulse output and to obtain a constant that relates the LSBs in the energy and rms registers to Watt/VA/VAR hours, amps, or volts. Additionally, calibration compensates for part-to-part variation in the meter design as well as phase shifts and offsets due to the current sensor and/or input networks. Calibration Using Pulse Output The ADE7758 provides a pulsed output proportional to the active power accumulated by all three phases, called APCF. Additionally, the VARCF output is proportional to either the reactive energy or apparent energy accumulated by all three phases. The following section describes how to calibrate the gain, offset, and phase angle using the pulsed output information. The equations are based on the pulse output from the ADE7758 (APCF or VARCF) and the pulse output of the reference meter or CFEXPECTED. Figure 77 shows a flowchart of how to calibrate the ADE7758 using the pulse output. Because the pulse outputs are proportional to the total energy in all three phases, each phase must be calibrated individually. Writing to the registers is fast to reconfigure the part for calibrating a different phase; therefore, Figure 77 shows a method that calibrates all phases at a given test condition before changing the test condition. Data Sheet ADE7758 Rev. E | Page 43 of 72 STARTCALIBRATE IRMSOFFSETCALIBRATE VRMSOFFSETMUST BE DONEBEFORE VA GAINCALIBRATIONWATT AND VACAN BE CALIBRATEDSIMULTANEOUSLY @PF = 1 BECAUSE THEYHAVE SEPARATE PULSE OUTPUTSALLPHASESVA AND WATTGAIN CAL?YESNOSET UP PULSEOUTPUT FORA, B, OR CCALIBRATEWATT AND VAGAIN @ ITEST,PF = 1ALLPHASESGAIN CALVAR?YESNOSET UP FORPHASEA, B, OR CCALIBRATEVAR GAIN@ ITEST, PF = 0,INDUCTIVEALLPHASESPHASE ERROR CAL?YESNOSET UP PULSEOUTPUT FORA, B, OR CCALIBRATEPHASE @ ITEST,PF = 0.5,INDUCTIVEALL PHASESVAR OFFSETCAL?YESNOSET UP PULSEOUTPUT FORA, B, OR CCALIBRATEVAR OFFSET@ IMIN, PF = 0,INDUCTIVEALL PHASESWATT OFFSETCAL?YESNOSET UP PULSEOUTPUT FORA, B, OR CCALIBRATEWATT OFFSET@ IMIN, PF = 1END04443-076 Figure 77. Calibration Using Pulse Output Gain Calibration Using Pulse Output Gain calibration is used for meter-to-meter gain adjustment, APCF or VARCF output rate calibration, and determining the Wh/LSB, VARh/LSB, and VAh/LSB constant. The registers used for watt gain calibration are APCFNUM (0x45), APCFDEN (0x46), and xWG (0x2A to 0x2C). Equation 50 through Equation 52 show how these registers affect the Wh/LSB constant and the APCF pulses. For calibrating VAR gain, the registers in Equation 50 through Equation 52 should be replaced by VARCFNUM (0x47), VARCFDEN (0x48), and xVARG (0x2D to 0x2F). For VAGAIN, they should be replaced by VARCFNUM (0x47), VARCFDEN (0x48), and xVAG (0x30 to 0x32). Figure 78 shows the steps for gain calibration of watts, VA, or VAR using the pulse outputs. ADE7758 Data Sheet Rev. E | Page 44 of 72 STARTSTEP1STEP1AENABLEAPCFANDVARCFPULSEOUTPUTSSTEP2CLEAR GAINREGISTERS:xWG,xVAG,xVARGSELECTVAFORVARCF OUTPUTCFNUM/VARCFNUMSETTOCALCULATEVALUES?NOYESALLPHASESVAANDWATTGAINCAL?YESNOSTEP3SETUPPULSEOUTPUTFORPHASEA,B, ORCSTEP5SETUPSYSTEMFORITEST,VNOMPF=1STEP6MEASURE%ERRORFORAPCFANDVARCFSTEP7CALCULATEANDWRITETOxWG,xVAGCALCULATEWh/LSBANDVAh/LSBCONSTANTSSETCFNUM/VARCFNUMANDCFDEN/VARCFDENTOCALCULATEDVALUESSTEP4ENDALLPHASESVAR GAINCALIBRATED?YESNOSELECTVARFORVARCFOUTPUTSTEP3SETUPPULSEOUTPUTFORPHASEA,B, ORCVARCFNUM/VARCFDENSETTOCALCULATEDVALUES?NOYESSTEP5SETUPSYSTEMFORITEST,VNOMPF=0, INDUCTIVESTEP6MEASURE%ERRORFORVARCFSTEP7CALCULATEANDWRITETOxVARGCALCULATEVARh/LSBCONSTANTSETVARCFNUM/VARCFDENTOCALCULATEDVALUESSTEP404443-077SELECTPHASEA,B, ORCFORLINEPERIODMEASUREMENT Figure 78. Gain Calibration Using Pulse Output Step 1: Enable the pulse output by setting Bit 2 of the OPMODE register (0x13) to Logic 0. This bit enables both the APCF and VARCF pulses. Step 1a: VAR and VA share the VARCF pulse output. WAVMODE[7], Address (0x15), should be set to choose between VAR or VA pulses on the output. Setting the bit to Logic 1 selects VA. The default is Logic 0 or VARCF pulse output. Step 2: Ensure the xWG/xVARG/xVAG are zero. Step 3: Disable the Phase B and Phase C contribution to the APCF and VARCF pulses. This is done by the TERMSEL[2:4] bits of the COMPMODE register (0x16). Setting Bit 2 to Logic 1 and Bit 3 and Bit 4 to Logic 0 allows only Phase A to be included in the pulse outputs. Select Phase A, Phase B, or Phase C for a line period measurement with the FREQSEL[1:0] bits in the MMODE register (0x14). For example, clearing Bit 1 and Bit 0 selects Phase A for line period measurement. Data Sheet ADE7758 Rev. E | Page 45 of 72 Step 4: Set APCFNUM (0x45) and APCFDEN (0x46) to the calculated value to perform a coarse adjustment on the imp/kWh ratio. For VAR/VA calibration, set VARCFNUM (0x47) and VARCFDEN (0x48) to the calculated value. The pulse output frequency with one phase at full-scale inputs is approximately 16 kHz. A sample set of meters could be tested to find a more exact value of the pulse output at full scale in the user application. To calculate the values for APCFNUM/APCFDEN and VARCFNUM/VARCFDEN, use the following formulas: FULLSCALETESTFULLSCALENOMNOMINALIIVVAPCF××=kHz16 (45) ()θ××××=cos36001000NOMTESTEXPECTEDVIMCAPCF (46) ⎟⎠⎞⎜⎝⎛=EXPECTEDNOMINALAPCFAPCFINTAPCFDEN (47) where: MC is the meter constant. ITEST is the test current. VNOM is the nominal voltage at which the meter is tested. VFULLSCALE and IFULLSCALE are the values of current and voltage, which correspond to the full-scale ADC inputs of the ADE7758. θ is the angle between the current and the voltage channel. APCFEXPECTED is equivalent to the reference meter output under the test conditions. APCFNUM is written to 0 or 1. The equations for calculating the VARCFNUM and VARCFDEN during VAR calibration are similar: ()θ××××=sin36001000NOMTESTEXPECTEDVIMCVARCF (48) Because the APCFDEN and VARCFDEN values can be calculated from the meter design, these values can be written to the part automatically during production calibration. Step 5: Set the test system for ITEST, VNOM, and the unity power factor. For VAR calibration, the power factor should be set to 0 inductive in this step. For watt and VA, the unity power factor should be used. VAGAIN can be calibrated at the same time as WGAIN because VAGAIN can be calibrated at the unity power factor, and both pulse outputs can be measured simultaneously. However, when calibrating VAGAIN at the same time as WGAIN, the rms offsets should be calibrated first (see the Calibration of IRMS and VRMS Offset section). Step 6: Measure the percent error in the pulse output, APCF and/or VARCF, from the reference meter: %100–%×=REFREFCFCFAPCFError (49) where CFREF = APCFEXPECTED = the pulse output of the reference meter. Step 7: Calculate xWG adjustment. One LSB change in xWG (12 bits) changes the WATTHR register by 0.0244% and therefore APCF by 0.0244%. The same relationship holds true for VARCF. [][][]⎟⎠⎞⎜⎝⎛+××=1220:1110:110:11xWGAPCFDENAPCFNUMAPCFAPCFNOMINALEXPECTED (50) %0244.0%–ErrorxWG= (51) When APCF is calibrated, the xWATTHR registers have the same Wh/LSB from meter to meter if the meter constant and the APCFNUM/APCFDEN ratio remain the same. The Wh/LSB constant is WDIVAPCFNUMAPCFDENMCLSBWh1100041×××= (52) Return to Step 2 to calibrate Phase B and Phase C gain. Example: Watt Gain Calibration of Phase A Using Pulse Output For this example, ITEST = 10 A, VNOM = 220 V, VFULLSCALE = 500 V, IFULLSCALE = 130 A, MC = 3200 impulses/kWh, Power Factor = 1, and Frequency = 50 Hz. Clear APCFNUM (0x45) and write the calculated value to APCFDEN (0x46) to perform a coarse adjustment on the imp/kWh ratio, using Equation 45 through Equation 47. kHz542.013010500220kHz16=××=NOMINALAPCF ()Hz9556.10cos36001000220103200=××××=EXPECTEDAPCF 277Hz9556.1Hz542=⎟⎟⎠⎞⎜⎜⎝⎛=INTAPCFDEN With Phase A contributing to CF, at ITEST, VNOM, and the unity power factor, the example ADE7758 meter shows 2.058 Hz on the pulse output. This is equivalent to a 5.26% error from the reference meter value using Equation 49. %26.5%100Hz9556.1Hz9556.1–Hz058.2=×=%Error The AWG value is calculated to be −216 d using Equation 51, which means the value 0xF28 should be written to AWG. 2802165.215%0244.0%26.5–xFAWG=−=−== ADE7758 Data Sheet Rev. E | Page 46 of 72 PHASE CALIBRATION USING PULSE OUTPUT The ADE7758 includes a phase calibration register on each phase to compensate for small phase errors. Large phase errors should be compensated by adjusting the antialiasing filters. The ADE7758 phase calibration is a time delay with different weights in the positive and negative direction (see the Phase Compensation section). Because a current transformer is a source of phase error, a fixed nominal value can be decided on to load into the xPHCAL registers at power-up. During calibration, this value can be adjusted for CT-to-CT error. Figure 79 shows the steps involved in calibrating the phase using the pulse output. START ALL PHASES PHASEERROR CALIBRATED? END YES NO STEP1 SET UPPULSE OUTPUTFOR PHASEA,B, ORC ANDENABLECF OUTPUTS STEP2 SET UPSYSTEM FOR ITEST, VNOM, PF=0.5, INDUCTIVE STEP3 MEASURE% ERROR INAPCF STEP4 CALCULATEPHASE ERROR(DEGREES) STEP5 PERIOD OF SYSTEM KNOWN? MEASURE PERIODUSING FREQ[11:0] REGISTER NO YES CALCULATEAND WRITETO xPHCAL 04443-078 SELECTPHASE FORLINEPERIOD MEASUREMENT CONFIGURE FREQ[11:0]FORA LINEPERIOD MEASUREMENT Figure 79. Phase Calibration Using Pulse Output Step 1: Step 1 and Step 3 from the gain calibration should be repeated to configure the ADE7758 pulse output. Ensure the xPHCAL registers are zero. Step 2: Set the test system for ITEST, VNOM, and 0.5 power factor inductive. Step 3: Measure the percent error in the pulse output, APCF, from the reference meter using Equation 49. Step 4: Calculate the Phase Error in degrees by           100%3 – %Error Error Arcsin Phase (53) Step 5: Calculate xPHCAL.      360 1 ) ( 1 _ _ 1 s PeriodLine PHCAL LSB Weight Error Phase xPHCAL (54) where PHCAL_LSB_Weight is 1.2 μs if the %Error is negative or 2.4 μs if the %Error is positive (see the Phase Compensation section). If it is not known, the line period is available in the ADE7758 frequency register, FREQ (0x10). To configure line period measurement, select the phase for period measurement in the MMODE[1:0] and set LCYCMODE[7]. Equation 55 shows how to determine the value that needs to be written to xPHCAL using the period register measurement.      360 ] 0:11[ _ _ 6 .9 FREQ PHCAL LSB Weight s Error Phase xPHCAL (55) Example: Phase Calibration of Phase A Using Pulse Output For this example, ITEST = 10 A, VNOM = 220 V, VFULLSCALE = 500 V, IFULLSCALE = 130 A, MC = 3200 impulses/kWh, power factor = 0.5 inductive, and frequency = 50 Hz. With Phase A contributing to CF, at ITEST, VNOM, and 0.5 inductive power factor, the example ADE7758 meter shows 0.9668 Hz on the pulse output. This is equivalent to −1.122% error from the reference meter value using Equation 49. The Phase Error in degrees using Equation 53 is 0.3713°.             3713 .0 3 %100 1.122% – Error – Arcsin Phase If at 50 Hz the FREQ register = 2083d, the value that should be written to APHCAL is 17d, or 0x11 using Equation 55. Note that a PHCAL_LSB_Weight of 1.2 μs is used because the %Error is negative. 11 01719.17 360 2083 μs 2.1 μs 6.9 3713 .0 APHCAL  x     Power Offset Calibration Using Pulse Output Power offset calibration should be used for outstanding performance over a wide dynamic range (1000:1). Calibration of the power offset is done at or close to the minimum current where the desired accuracy is required. The ADE7758 has power offset registers for watts and VAR (xWATTOS and xVAROS). Offsets in the VA measurement are compensated by adjusting the rms offset registers (see the Calibration of IRMS and VRMS Offset section). Figure 80 shows the steps to calibrate the power offsets using the pulse outputs. Data Sheet ADE7758 Rev. E | Page 47 of 72 STARTSTEP1ENABLECFOUTPUTSSTEP2CLEAR OFFSETREGISTERSxWATTOS,xVAROSALLPHASESWATT OFFSETCALIBRATED?YESNOALLPHASESVAR OFFSETCALIBRATED?YESNOSETUPAPCFPULSE OUTPUTFORPHASEA,B,ORCSTEP4STEP3SETUPSYSTEMFORIMIN,VNOM,PF=1STEP5MEASURE%ERRORFORAPCFSTEP6CALCULATEANDWRITETOxWATTOSENDSETUPVARCFPULSE OUTPUTFORPHASEA,B,ORCSTEP4STEP3SETUPSYSTEMFORIMIN,VNOM,PF=0, INDUCTIVESTEP5MEASURE%ERRORFORVARCFMEASUREPERIODUSINGFREQ[11:0]REGISTERSTEP6CALCULATEANDWRITETOxVAROSSTEP7.REPEATSTEP3TOSTEP6FORxVAROSSELECTPHASEFORLINEPERIODMEASUREMENTCONFIGUREFREQ[11:0]FORALINEPERIODMEASUREMENT04443-079 Figure 80. Offset Calibration Using Pulse Output Step 1: Repeat Step 1 and Step 3 from the gain calibration to configure the ADE7758 pulse output. Step 2: Clear the xWATTOS and xVAROS registers. Step3: Disable the Phase B and Phase C contribution to the APCF and VARCF pulses. This is done by the TERMSEL[2:4] bits of the COMPMODE register (0x16). Setting Bit 2 to Logic 1 and Bit 3 and Bit 4 to Logic 0 allows only Phase A to be included in the pulse outputs. Select Phase A, Phase B, or Phase C for a line period measurement with the FREQSEL[1:0] bits in the MMODE register (0x14). For example, clearing Bit 1 and Bit 0 selects Phase A for line period measurement. Step 4: Set the test system for IMIN, VNOM, and unity power factor. For Step 6, set the test system for IMIN, VNOM, and zero-power factor inductive. Step 5: Measure the percent error in the pulse output, APCF or VARCF, from the reference meter using Equation 49. Step 6: Calculate xWATTOS using Equation 56 (for xVAROS use Equation 57). APCFNUMAPCFDENQAPCF%APCFxWATTOSEXPECTEDERROR××⎟⎠⎞⎜⎝⎛×=42%100– (56) ADE7758 Data Sheet Rev. E | Page 48 of 72 VARCFNUMVARCFDENQVARCF%VARCFxVAROSEXPECTEDERROR××⎟⎠⎞⎜⎝⎛×=42%100– (57) where Q is defined in Equation 58 and Equation 59. For xWATTOS, 4121425××=CLKINQ (58) For xVAROS, 4140]:[1120221424×⎟⎠⎞⎜⎝⎛××=FREQCLKINQ (59) where the FREQ (0x10) register is configured for line period measurements. Step 7: Repeat Step 3 to Step 6 for xVAROS calibration. Example: Offset Calibration of Phase A Using Pulse Output For this example, IMIN = 50 mA, VNOM = 220 V, VFULLSCALE = 500 V, IFULLSCALE = 130 A, MC = 3200 impulses/kWh, Power Factor = 1, Frequency = 50 Hz, and CLKIN = 10 MHz. With IMIN, VNOM, and unity power factor, the example ADE7758 meter shows 0.009789 Hz on the APCF pulse output. When the power factor is changed to 0.5 inductive, the VARCF output is 0.009769 Hz. This is equivalent to 0.1198% for the watt measurement and −0.0860% for the VAR measurement. Using Equation 56 through Equation 59, the values 0xFFD and 0x3 should be written to AWATTOS (0x39) and AVAROS (0x3C), respectively. 0xFFD3– –2.812770.0186320.009778%1000.1198%–4===××⎟⎠⎞⎜⎝⎛×=AWATTOS 32.612770.0144420.009778%1000.0860%––4==××⎟⎠⎞⎜⎝⎛×=AVAROS For AWATTOS, 01863.04121461025=××=EQ For AVAROS, 0.01444414208320221461024=×××=EQ Calibration Using Line Accumulation Line cycle accumulation mode configures the nine energy registers such that the amount of energy accumulated over an integer number of half line cycles appears in the registers after the LENERGY interrupt. The benefit of using this mode is that the sinusoidal component of the active energy is eliminated. Figure 81 shows a flowchart of how to calibrate the ADE7758 using the line accumulation mode. Calibration of all phases and energies can be done simultaneously using this mode to save time during calibration. STARTCAL IRMS OFFSETCAL VRMS OFFSETCAL WATT AND VAGAIN ALL PHASES@ PF = 1CAL VAR GAIN ALLPHASES @ PF = 0,INDUCTIVECALIBRATE PHASEALL PHASES@ PF = 0.5,INDUCTIVECALIBRATE ALLPHASES WATTOFFSET @ IMIN ANDPF = 1CALIBRATE ALLPHASES VAROFFSETS @ IMINAND PF = 0,INDUCTIVEEND04443-080 Figure 81. Calibration Using Line Accumulation Data Sheet ADE7758 Rev. E | Page 49 of 72 Gain Calibration Using Line Accumulation Step 2: Select Phase A, Phase B, or Phase C for a line period measurement with the FREQSEL[1:0] bits in the MMODE register (0x14). For example, clearing Bit 1 and Bit 0 selects Phase A for line period measurement. Gain calibration is used for meter-to-meter gain adjustment, APCF or VARCF output rate calibration, and determining the Wh/LSB, VARh/LSB, and VAh/LSB constant. Step 3: Set up ADE7758 for line accumulation by writing 0xBF to LCYCMODE. This enables the line accumulation mode on the xWATTHR, xVARHR, and xVAHR (0x01 to 0x09) registers by setting the LWATT, LVAR, and LVA bits, LCYCMODE[0:2] (0x17), to Logic 1. It also sets the ZXSEL bits, LCYCMODE[3:5], to Logic 1 to enable the zero-crossing detection on all phases for line accumulation. Additionally, the FREQSEL bit, LCYCMODE[7], is set so that FREQ (0x10) stores the line period. When using the line accumulation mode, the RSTREAD bit of LCYCMODE should be set to 0 to disable the read with reset mode. Select the phase for line period measurement in MMODE[1:0]. Step 0: Before performing the gain calibration, the APCFNUM/ APCFDEN (0x45/0x46) and VARCFNUM/ VARCFDEN (0x47/0x48) values can be set to achieve the correct impulses/kWh, impulses/kVAh, or impulses/kVARh using the same method outlined in Step 4 in the Gain Calibration Using Pulse Output section. The calibration of xWG/xVARG/xVAG (0x2A through 0x32) is done with the line accumulation mode. Figure 82 shows the steps involved in calibrating the gain registers using the line accumulation mode. Step 1: Clear xWG, xVARG, and xVAG. Step 4: Set the number of half-line cycles for line accumulation by writing to LINECYC (0x1C). FREQUENCYKNOWN?NOYESSTEP0SETAPCFNUM/APCFDENANDVARCFNUM/VARCFDENSTEP1STEP2CLEARxWG/xVAR/xVAGSTEP3SETLYCMODEREGISTERSTEP4SETACCUMULATIONTIME(LINECYC)STEP5SETMASKFORLENERGY INTERRUPTSTEP6SETUPSYSTEMFORITEST,VNOM,PF=1STEP7READFREQ[11:0]REGISTERSTEP8RESETSTATUSREGISTERSTEP9READALLxWATTHRANDxVAHRAFTERLENERGYINTERRUPTSTEP9ACALCULATExWGSTEP9BCALCULATExVAGSTEP10WRITETOxWGANDxVAGCALIBRATEWATTANDVA@PF=1STEP11SETUPTESTSYSTEMFORITEST,VNOM,PF=0, INDUCTIVESTEP12RESETSTATUSREGISTERSTEP13READALLxVARHRAFTERLENERGYINTERRUPTSTEP14CALCULATExVARGSTEP15WRITETOxVARGSTEP16CALCULATEWh/LSB,VAh/LSB,VARh/LSBEND04443-081SELECTPHASEFORLINEPERIODMEASUREMENTCONFIGUREFREQ[11:0]FORALINEPERIODMEASUREMENT Figure 82. Gain Calibration Using Line Accumulation ADE7758 Data Sheet Rev. E | Page 50 of 72 Step 5: Set the LENERGY bit, MASK[12] (0x18), to Logic 1 to enable the interrupt signaling the end of the line cycle accumulation. Step 6: Set the test system for ITEST, VNOM, and unity power factor (calibrate watt and VA simultaneously and first). Step 7: Read the FREQ (0x10) register if the line frequency is unknown. Step 8: Reset the interrupt status register by reading RSTATUS (0x1A). Step 9: Read all six xWATTHR (0x01 to 0x03) and xVAHR (0x07 to 0x09) energy registers after the LENERGY interrupt and store the values. Step 9a: Calculate the values to be written to xWG registers according to the following equations: ()WDIVAPCFNUMAPCFDENAccumTimeθcosVIMCWATTHRNOMTESTEXPECTED1360010004××××××××= (60) where AccumTime is []SelectedPhasesofNo.FrequencyLine :LINECYC××2015 (61) where: MC is the meter constant. θ is the angle between the current and voltage. Line Frequency is known or calculated from the FREQ[11:0] register. With the FREQ[11:0] register configured for line period measurements, the line frequency is calculated with Equation 62. 6-109.60]:[111××=FREQFrequencyLine (62) No. of Phases Selected is the number of ZXSEL bits set to Logic 1 in LCYCMODE (0x17). Then, xWG is calculated as 1221×⎟⎟⎠⎞⎜⎜⎝⎛−=MEASUREDEXPECTEDWATTHRWATTHRxWG (63) Step 9b: Calculate the values to be written to the xVAG registers according to the following equation: VADIVVARCFNUMVARCFDENAccumTimeVIMCVAHRNOMTESTEXPECTED1360010004×××××××= (64) 1221×⎟⎟⎠⎞⎜⎜⎝⎛−=MEASUREDEXPECTEDVAHRVAHRxVAG Step 10: Write to xWG and xVAG. Step 11: Set the test system for ITEST, VNOM, and zero power factor inductive to calibrate VAR gain. Step 12: Repeat Step 7. Step 13: Read the xVARHR (0x04 to 0x06) after the LENERGY interrupt and store the values. Step 14: Calculate the values to be written to the xVARG registers (to adjust VARCF to the expected value). ()VARDIVVARCFNUMVARCFDENAccumTimeθsinVIMCVARHRNOMTESTEXPECTED1360010004××××××××= (65) 1221×⎟⎟⎠⎞⎜⎜⎝⎛−=MEASUREDEXPECTEDVARHRVARHRxVARG Step 15: Write to xVARG. Step 16: Calculate the Wh/LSB, VARh/LSB, and VAh/LSB constants. ()xWATTHRAccumTimeθcosVILSBWhNOMTEST××××=3600 (66) xVAHRAccumTimeVILSBVAhNOMTEST×××=3600 (67) ()xVARHRAccumTimeθsinVILSBVARhNOMTEST××××=3600 (68) Example: Watt Gain Calibration Using Line Accumulation This example shows only Phase A watt calibration. The steps outlined in the Gain Calibration Using Line Accumulation section show how to calibrate watt, VA, and VAR. All three phases can be calibrated simultaneously because there are nine energy registers. For this example, ITEST = 10 A, VNOM = 220 V, Power Factor = 1, Frequency = 50 Hz, LINECYC (0x1C) is set to 0x800, and MC = 3200 imp/kWhr. Data Sheet ADE7758 Rev. E | Page 51 of 72 To set APCFNUM (0x45) and APCFDEN (0x46) to the calculated value to perform a coarse adjustment on the imp/kW-hr ratio, use Equation 45 to Equation 47. kHz5415.013010500220kH16=××=zAPCFNOMINAL ()Hz1.956cos36001000220103200=θ××××=EXPECTEDAPCF 277Hz956.1Hz5.541INT=⎟⎟⎠⎞⎜⎜⎝⎛=APCFDEN Under the test conditions above, the AWATTHR register value is 15559d after the LENERGY interrupt. Using Equation 60 and Equation 61, the value to be written to AWG is −199d, 0xF39. []SelectedPhasesofNo.FREQ:LINECYCAccumTime××××=−6106.9]0:11[12015 6.832128s3106.920851280006=××××=−xAccumTime 148041127736001000832.612201032004=××××××××=EXPECTEDWATTHR 0xF39–199–198.8764021155591480412===×⎟⎠⎞⎜⎝⎛−=xWG Using Equation 66, the Wh/LSB constant is 00.000282148043600832.622010=×××=LSBWh Phase Calibration Using Line Accumulation The ADE7758 includes a phase calibration register on each phase to compensate for small phase errors. Large phase errors should be compensated by adjusting the antialiasing filters. The ADE7758 phase calibration is a time delay with different weights in the positive and negative direction (see the Phase Compensation section). Because a current transformer is a source of phase error, a fixed nominal value can be decided on to load into the xPHCAL (0x3F to 0x41) registers at power-up. During calibration, this value can be adjusted for CT-to-CT error. Figure 83 shows the steps involved in calibrating the phase using the line accumulation mode. STEP1SETLCYCMODE,LINECYCANDMASKREGISTERSSTEP2SETUPSYSTEMFORITEST,VNOM,PF=0.5,INDUCTIVESTEP3RESETSTATUSREGISTERSTEP4READALLxWATTHRREGISTERSAFTERLENERGYINTERRUPTSTEP5CALCULATEPHASEERROR INDEGREESFORALLPHASESSTEP6CALCULATEANDWRITETOALLxPHCALREGISTERS04443-082 Figure 83. Phase Calibration Using Line Accumulation Step 1: If the values were changed after gain calibration, Step 1, Step 3, and Step 4 from the gain calibration should be repeated to configure the LCYCMODE and LINECYC registers. Step 2: Set the test system for ITEST, VNOM, and 0.5 power factor inductive. Step 3: Reset the interrupt status register by reading RSTATUS (0x1A). Step 4: The xWATTHR registers should be read after the LENERGY interrupt. Measure the percent error in the energy register readings (AWATTHR, BWATTHR, and CWATTHR) compared to the energy register readings at unity power factor (after gain calibration) using Equation 69. The readings at unity power factor should have been repeated after the gain calibration and stored for use in the phase calibration routine. 22–1PF1PF5PF====xWATTHRxWATTHRxWATTHRError (69) Step 5: Calculate the Phase Error in degrees using the equation ()⎟⎠⎞⎜⎝⎛=°3–ErrorArcsinErrorPhase (70) Step 6: Calculate xPHCAL and write to the xPHCAL registers (0x3F to 0x41). °×××=3601)(1__1sPeriodLineWeightLSBPHCALErrorPhasexPHCAL(71) where PHCAL_LSB_Weight is 1.2 μs if the %Error is negative or 2.4 μs if the %Error is positive (see the Phase Compensation section). ADE7758 Data Sheet Rev. E | Page 52 of 72 If it is not known, the line period is available in the ADE7758 frequency register, FREQ (0x10). To configure line period measurement, select the phase for period measurement in the MMODE[1:0] and set LCYCMODE[7]. Equation 72 shows how to determine the value that needs to be written to xPHCAL using the period register measurement. °××=360]0:11[__μs6.9FREQWeightLSBPHCALErrorPhasexPHCAL (72) Example: Phase Calibration Using Line Accumulation This example shows only Phase A phase calibration. All three PHCAL registers can be calibrated simultaneously using the same method. For this example, ITEST = 10 A, VNOM = 220 V, power factor = 0.5 inductive, and frequency = 50 Hz. Also, LINECYC = 0x800. With ITEST, VNOM, and 0.5 inductive power factor, the example ADE7758 meter shows 7318d in the AWATTHR (0x01) register. 14804d in the AWATTHR register. This is equivalent to −1.132% error. %132.101132.0214804214804–7318−=−==Error ()°=⎟⎠ ⎞⎛−01132.0 50 Hz, the FREQ (0x10) register = 2085d, is 17d. Note that a PHCAL_LSB_Weight of 1.2 μs is used because the %Error is negative. 11x01736020852.16.9374.0==××°=APHCAL F STEP1SETMMODE,LCYCMODE,LINECYCANDMASKREGISTERSSTEP2SETUPSYSTEMFORIMIN,VNOM@PF=1STEP3RESETSTATUSREGISTERSTEP4READALLxWATTHRREGISTERSAFTERLENERGYINTERRUPTENDFORSTEP8READALLxVARHRAFTERLENERGYINTERRUPTFORSTEP8,CALCULATExVAROSFORALLPHASESSTEP5CALCULATExWATTOSFORALLPHASESFORSTEP8,WRITETOALLxVAROSREGISTERSSTEP6WRITETOALLxWATTOSREGISTERSSTEP7SETUPSYSTEMFORITEST,VNOM@PF=0, INDUCTIVESTEP8REPEATSTEP3TOSTEP8FORxVARHR,xVAROS CALIBRATION Data Sheet ADE7758 Rev. E | Page 53 of 72 Power Offset Calibration Using Line Accumulation Power offset calibration should be used for outstanding performance over a wide dynamic range (1000:1). Calibration of the power offset is done at or close to the minimum current. The ADE7758 has power offset registers for watts and VAR, xWATTOS (0x39 to 0x3B) and xVAROS (0x3C to 0x3E). Offsets in the VA measurement are compensated by adjusting the rms offset registers (see the Calibration of IRMS and VRMS Offset section). More line cycles could be required at the minimum current to minimize the effect of quantization error on the offset calibration. For example, if a current of 40 mA results in an active energy accumulation of 113 after 2000 half line cycles, one LSB variation in this reading represents an 0.8% error. This measurement does not provide enough resolution to calibrate out a <1% offset error. However, if the active energy is accumulated over 37,500 half line cycles, one LSB variation results in 0.05% error, reducing the quantization error. Figure 84 shows the steps to calibrate the power offsets using the line accumulation mode. Step 1: If the values change after gain calibration, Step 1, Step 3, and Step 4 from the gain calibration should be repeated to configure the LCYCMODE, LINECYC, and MASK registers. Select Phase A, Phase B, or Phase C for a line period measure-ment with the FREQSEL[1:0] bits in the MMODE register (0x14). For example, clearing Bit 1 and Bit 0 selects Phase A for line period measurement. Step 2: Set the test system for IMIN, VNOM, and unity power factor. Step 3: Reset the interrupt status register by reading RSTATUS (0x1A). Step 4: Read all xWATTHR energy registers (0x01 to 0x03) after the LENERGY interrupt and store the values. Step 4a: If it is not known, the line period is available in the ADE7758 frequency register, FREQ (0x10). To configure line period measurement, select the phase for period measurement in the MMODE[1:0] and set LCYCMODE[7]. Step 5: Calculate the value to be written to the xWATTOS registers according to the following equations: TESTMINMINITESTIMINITESTIIIILINECYCLINECYCxWATTHRIxWATTHROffsetTESTMIN––×⎟⎟⎠⎞⎜⎜⎝⎛××= (73) []29240:11×××=CLKINAccumTimeOffsetxWATTOS (74) where: AccumTime is defined in Equation 61. is the value in the energy register at ITEST. is the value in the energy register at IMIN. LINECYCIMIN is the number of line cycles accumulated at IMIN. LINECYCIMAX is the number of line cycles accumulated at IMAX. TESTIxWATTHRMINIxWATTHR Step 6: Write to all xWATTOS registers (0x39 to 0x3B). Step 7: Set the test system for IMIN, VNOM, and zero power factor inductive to calibrate VAR gain. Step 8: Repeat Steps 3, 4, and 5. Step 9: Calculate the value written to the xVAROS registers according to the following equations: TESTMINMINITESTIMINITESTIIIILINECYCLINECYCxVARHRIxVARHROffsetTESTMIN––×⎟⎟⎠⎞⎜⎜⎝⎛××= (75) 262202]0:11[40]:[11××××=FREQCLKINAccumTimeOffsetxVAROS(76) where the FREQ[11:0] register is configured for line period readings. Example: Power Offset Calibration Using Line Accumulation This example only shows Phase A of the phase active power offset calibration. Both active and reactive power offset for all phases can be calibrated simultaneously using the method explained in the Power Offset Calibration Using Line Accumulation section. For this example, IMIN = 50 mA, ITEST = 10 A, VNOM = 220 V, VFULLSCALE = 500 V, IFULLSCALE = 130 A, MC = 3200 impulses/kWh, Power Factor = 1, Frequency = 50 Hz, and CLKIN = 10 MHz. Also, LINECYCITEST = 0x800 and LINECYCIMIN = 0x4000. After accumulating over 0x800 line cycles for gain calibration at ITEST, the example ADE7758 meter shows 14804d in the AWATTHR (0x01) register. At IMIN, the meter shows 592d in the AWATTHR register. By using Equation 73, this is equivalent to 0.161 LSBs of offset; therefore, using Equation 61 and Equation 74, the value written to AWATTOS is 0d. 0.1610–0.050.050x8000x400014804–10592=×⎟⎠⎞⎜⎝⎛××=Offset s64.453106.9208512400006=×××××=−AccumTime ADE7758 Data Sheet Rev. E | Page 54 of 72 00.0882MHz1054.6440.16129=−=×××=AWATTOS The low-pass filter used to obtain the rms measurements is not ideal; therefore, it is recommended to synchronize the readings with the zero crossings of the voltage waveform and to average a few measurements when reading the rms registers. Calibration of IRMS and VRMS Offset IRMSOS and VRMSOS are used to cancel noise and offset contributions from the inputs. The calibration method is the same whether calibrating using the pulse outputs or line accumulation. Reading the registers is required for this calibration because there is no rms pulse output. The rms offset calibration should be performed before VAGAIN calibration. The rms offset calibration also removes offset from the VA calculation. For this reason, no VA offset register exists in the ADE7758. The ADE7758 IRMS measurement is linear over a 500:1 range, and the VRMS measurement is linear over a 20:1 range. To measure the voltage VRMS offset (xVRMSOS), measure rms values at two different nonzero current levels, for example, VNOM and VFULLSCALE/20. To measure the current rms offset (IRMSOS), measure rms values at two different nonzero current levels, for example, ITEST and IFULLSCALE/500. This translates to two test conditions: ITEST and VNOM, and IFULLSCALE/500 and VFULLSCALE/20. Figure 85 shows a flowchart for calibrating the rms measurements. STEP1SETCONFIGURATIONREGISTERSFORZEROCROSSINGONALLPHASESSTEP2SET INTERRUPTMASKFORZEROCROSSINGONALLPHASESSTEP3STEP4READRMSREGISTERSSTEP5WRITETOxVRMSOSxIRMSOSSETUPSYSTEMFORITEST,VNOMSETUPSYSTEMFORIFULLSCALE/500,VFULLSCALE/20STARTTESTEDALLPHASES?YESNOTESTEDALLCONDITIONS?12STEP4ACHOOSENn=0STEP4DREADxIRMSxVRMSSTEP4ECALCULATETHEAVERAGE OFNSAMPLESSTEP4BRESET INTERRUPTSTATUSREGISTERENDn=n+1n=N?NOYESYESNOSTEP4CINTERRUPT?04443-084 Figure 85. RMS Calibration Routine Data Sheet ADE7758 Rev. E | Page 55 of 72 Step 1: Set configuration registers for zero crossings on all phases by writing the value 0x38 to the LCYCMODE register (0x17). This sets all of the ZXSEL bits to Logic 1. Step 2: Set the interrupt mask register for zero-crossing detection on all phases by writing 0xE00 to the MASK[0:24] register (0x18). This sets all of the ZX bits to Logic 1. Step 3: Set up the calibration system for one of the two test conditions: ITEST and VNOM, and IFULLSCALE/500 and VFULLSCALE/20. Step 4: Read the rms registers after the zero-crossing interrupt and take an average of N samples. This is recommended to get the most stable rms readings. This procedure is detailed in Figure 85: Steps 4a through 4e. Step 4a. Choose the number of samples, N, to be averaged. Step 4b. Reset the interrupt status register by reading RSTATUS (0x1A). Step 4c. Wait for the zero-crossing interrupt. When the zero-crossing interrupt occurs, move to Step 4d. Step 4d. Read the xIRMS and xVRMS registers. These values will be averaged in Step 4e. Step 4e: Average the N samples of xIRMS and xVRMS. The averaged values will be used in Step 5. Step 5: Write to the xVRMSOS (0x33 to 0x35) and xIRMSOS (0x36 to 0x38) registers according to the following equations: ()( 222222163841TESTMINITESTMINIMINTESTI–IIRMSI–IRMSIxIRMSOS×××= (77) where: IMIN is the full scale current/500. ITEST is the test current. IRMSIMIN and IRMSITEST are the current rms register values without offset correction for the inputs IMIN and ITEST, respectively. NOMMINVNOMMINVMINNOMV–VVRMSV–VRMSVxVRMSOS×××=641 (78) where: VMIN is the full scale voltage/20 VNOM is the nominal line voltage. VRMSVMIN and VRMSVNOM are the voltage rms register values without offset correction for the input VMIN and VNOM, respectively. Example: Calibration of RMS Offsets For this example, ITEST = 10 A, IMAX = 100 A, VNOM = 220 V, VFULLSCALE = 500 V, Power Factor = 1, and Frequency = 50 Hz. Twenty readings are taken synchronous to the zero crossings of all three phases at each current and voltage to determine the average xIRMS and xVRMS readings. At ITEST and VNOM, the example ADE7758 meter gets an average AIRMS (0x0A) reading of 148242.2 and 744570.8 in the AVRMS (0x0D) register. Then the current is set to IMIN = IFULLSCALE/500 or 260 mA. At IMIN, the average AIRMS reading is 3885.68. At VMIN = VFULLSCALE/20 or 25 V, the example meter gets an average AVRMS of 86362.36. Using this data, −15d is written to AIRMSOS (0x36) and −31d is written to AVRMSOS (0x33) registers according to the Equation 77 and Equation 78. ()(() 0xFF2158.1410–260.0148242.2260.0–3885.681016384122222=−=−=×××=AIRMSOS ()()()0xFE1319.30220–25744570.825–86362.36220641=−=−=×××=AVRMSOS This example shows the calculations and measurements for Phase A only. However, all three xIRMS and xVRMS registers can be read simultaneously to compute the values for each xIRMSOS and xVRMSOS register. CHECKSUM REGISTER The ADE7758 has a checksum register CHKSUM[7:0] (0x7E) to ensure the data bits received in the last serial read operation are not corrupted. The 8-bit checksum register is reset before the first bit (MSB of the register to be read) is put on the DOUT pin. During a serial read operation, when each data bit becomes available on the rising edge of SCLK, the bit is added to the checksum register. In the end of the serial read operation, the contents of the checksum register are equal to the sum of all the 1s in the register previously read. Using the checksum register, the user can determine if an error has occurred during the last read operation. Note that a read to the checksum register also generates a checksum of the checksum register itself. DOUTADDR: 0x7ECHECKSUMREGISTERCONTENT OF REGISTERS(N-BYTES)04443-085 Figure 86. Checksum Register for Serial Interface Read INTERRUPTS The ADE7758 interrupts are managed through the interrupt status register (STATUS[23:0], Address 0x19) and the interrupt mask register (MASK[23:0], Address 0x18). When an interrupt event occurs in the ADE7758, the corresponding flag in the interrupt status register is set to a Logic 1 (see Table 24). If the mask bit for this interrupt in the interrupt mask register is Logic 1, then the IRQ logic output goes active low. The flag bits ADE7758 Data Sheet Rev. E | Page 56 of 72 in the interrupt status register are set irrespective of the state of the mask bits. To determine the source of the interrupt, the MCU should perform a read from the reset interrupt status register with reset. This is achieved by carrying out a read from RSTATUS, Address 0x1A. The IRQ output goes logic high on completion of the interrupt status register read command (see the section). When carrying out a read with reset, the is designed to ensure that no interrupt events are missed. If an interrupt event occurs just as the interrupt status register is being read, the event is not lost, and the Interrupt TimingADE7758IRQ logic output is guaranteed to go logic high for the duration of the interrupt status register data transfer before going logic low again to indicate the pending interrupt. Note that the reset interrupt bit in the status register is high for only one clock cycle, and it then goes back to 0. USING THE INTERRUPTS WITH AN MCU Figure 87 shows a timing diagram that illustrates a suggested implementation of ADE7758 interrupt management using an MCU. At time t1, the IRQ line goes active low indicating that one or more interrupt events have occurred in the . The ADE7758IRQ logic output should be tied to a negative-edge-triggered external interrupt on the MCU. On detection of the negative edge, the MCU should be configured to start executing its interrupt service routine (ISR). On entering the ISR, all interrupts should be disabled using the global interrupt mask bit. At this point, the MCU external interrupt flag can be cleared to capture interrupt events that occur during the current ISR. When the MCU interrupt flag is cleared, a read from the reset interrupt status register with reset is carried out. (This causes the IRQ line to be reset logic high (t2); see the section.) The reset interrupt status register contents are used to determine the source of the interrupt(s) and hence the appropriate action to be taken. If a subsequent interrupt event occurs during the ISR (t3) that event is recorded by the MCU external interrupt flag being set again. Interrupt Timing On returning from the ISR, the global interrupt mask bit is cleared (same instruction cycle) and the external interrupt flag uses the MCU to jump to its ISR once again. This ensures that the MCU does not miss any external interrupts. The reset bit in the status register is an exception to this and is only high for one clock cycle after a reset event. INTERRUPT TIMING The Serial Interface section should be reviewed before reviewing this section. As previously described, when the IRQ output goes low, the MCU ISR must read the interrupt status register to determine the source of the interrupt. When reading the interrupt status register contents, the IRQ output is set high on the last falling edge of SCLK of the first byte transfer (read interrupt status register command). The IRQ output is held high until the last bit of the next 8-bit transfer is shifted out (interrupt status register contents), as shown in . If an interrupt is pending at this time, the Figure 88IRQ output goes low again. If no interrupt is pending, the IRQ output remains high. SERIAL INTERFACE The ADE7758 has a built-in SPI interface. The serial interface of the ADE7758 is made of four signals: SCLK, DIN, DOUT, and CS. The serial clock for a data transfer is applied at the SCLK logic input. This logic input has a Schmitt trigger input structure that allows slow rising (and falling) clock edges to be used. All data transfer operations are synchronized to the serial clock. Data is shifted into the at the DIN logic input on the falling edge of SCLK. Data is shifted out of the at the DOUT logic output on a rising edge of SCLK. ADE7758ADE7758 The CS logic input is the chip select input. This input is used when multiple devices share the serial bus. A falling edge on CS also resets the serial interface and places the in communications mode. ADE7758 The CS input should be driven low for the entire data transfer operation. Bringing CS high during a data transfer operation aborts the transfer and places the serial bus in a high impedance state. The CS logic input can be tied low if the is the only device on the serial bus. ADE7758 However, with CS tied low, all initiated data transfer operations must be fully completed. The LSB of each register must be transferred because there is no other way of bringing the back into communications mode without resetting the entire device, that is, performing a software reset using Bit 6 of the OPMODE[7:0] register, Address 0x13. ADE7758 The functionality of the ADE7758 is accessible via several on-chip registers (see Figure 89). The contents of these registers can be updated or read using the on-chip serial interface. After a falling edge on CS, the is placed in communications mode. In communications mode, the expects the first communication to be a write to the internal communications register. The data written to the communications register contains the address and specifies the next data transfer to be a read or a write command. Therefore, all data transfer operations with the , whether a read or a write, must begin with a write to the communications register. ADE7758ADE7758ADE7758 Data Sheet ADE7758 Rev. E | Page 57 of 72 GLOBALINTERRUPTMASKISR RETURNGLOBAL INTERRUPTMASK RESETCLEAR MCUINTERRUPTFLAGREADSTATUS WITHRESET (0x1A)ISR ACTION(BASED ON STATUS CONTENTS)MCUINTERRUPTFLAG SETPROGRAMSEQUENCEt1t2t3JUMPTOISRJUMPTOISRIRQ04443-086 Figure 87. ADE7758 Interrupt Management STATUS REGISTER CONTENTSSCLKDINDOUTREAD STATUS REGISTER COMMANDt1CS0001000DB15DB8DB7DB01t9t11t12IRQ04443-087 Figure 88. ADE7758 Interrupt Timing COMMUNICATIONSREGISTERINOUTINOUTINOUTINOUTINOUTREGISTER NO. 1REGISTER NO. 2REGISTER NO. 3REGISTER NO. n–1REGISTER NO. nREGISTERADDRESSDECODEDINDOUT04443-088 Figure 89. Addressing ADE7758 Registers via the Communications Register The communications register is an 8-bit, write-only register. The MSB determines whether the next data transfer operation is a read or a write. The seven LSBs contain the address of the register to be accessed (see Table 16). Figure 90 and Figure 91 show the data transfer sequences for a read and write operation, respectively. MULTIBYTECOMMUNICATIONS REGISTER WRITEDINSCLKDOUTREAD DATAADDRESS0CS04443-089 Figure 90. Reading Data from the ADE7758 via the Serial Interface COMMUNICATIONS REGISTER WRITEDINSCLKADDRESS1CSMULTIBYTEREAD DATA04443-090 Figure 91. Writing Data to the ADE7758 via the Serial Interface On completion of a data transfer (read or write), the ADE7758 once again enters into communications mode, that is, the next instruction followed must be a write to the communications register. A data transfer is completed when the LSB of the ADE7758 register being addressed (for a write or a read) is transferred to or from the ADE7758. SERIAL WRITE OPERATION The serial write sequence takes place as follows. With the ADE7758 in communications mode and the CS input logic low, a write to the communications register takes place first. The MSB of this byte transfer must be set to 1, indicating that the next data transfer operation is a write to the register. The seven LSBs of this byte contain the address of the register to be written to. The starts shifting in the register data on the next falling edge of SCLK. All remaining bits of register data are shifted in on the falling edge of the subsequent SCLK pulses (see ). ADE7758Figure 92 ADE7758 Data Sheet Rev. E | Page 58 of 72 As explained earlier, the data write is initiated by a write to the communications register followed by the data. During a data write operation to the ADE7758, data is transferred to all on-chip registers one byte at a time. After a byte is transferred into the serial port, there is a finite time duration before the content in the serial port buffer is transferred to one of the ADE7758 on-chip registers. Although another byte transfer to the serial port can start while the previous byte is being transferred to the destination register, this second-byte transfer should not finish until at least 900 ns after the end of the previous byte transfer. This functionality is expressed in the timing specification t6 (see Figure 92). If a write operation is aborted during a byte transfer (CS brought high), then that byte is not written to the destination register. Destination registers can be up to 3 bytes wide (see the Accessing the On-Chip Registers section). Therefore, the first byte shifted into the serial port at DIN is transferred to the most significant byte (MSB) of the destination register. If the destination register is 12 bits wide, for example, a two-byte data transfer must take place. The data is always assumed to be right justified; therefore, in this case, the four MSBs of the first byte would be ignored, and the four LSBs of the first byte written to the ADE7758 would be the four MSBs of the 12-bit word. Figure 93 illustrates this example. DINSCLKCSt2t3t1t4t5t7t6t8COMMAND BYTEMOST SIGNIFICANT BYTELEAST SIGNIFICANT BYTE1A6A4A5A3A2A1A0DB7DB0DB7DB0t704443-091 Figure 92. Serial Interface Write Timing Diagram SCLKDINXXXXDB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0MOST SIGNIFICANT BYTELEAST SIGNIFICANT BYTE04443-092 Figure 93. 12-Bit Serial Write Operation SCLKCSt1t10t130A6A4A5A3A2A1A0DB0DB7DB0DB7DINDOUTt11t12COMMAND BYTEMOST SIGNIFICANT BYTELEAST SIGNIFICANT BYTEt904443-093 Figure 94. Serial Interface Read Timing Diagram Data Sheet ADE7758 Rev. E | Page 59 of 72 SERIAL READ OPERATION During a data read operation from the ADE7758, data is shifted out at the DOUT logic output on the rising edge of SCLK. As was the case with the data write operation, a data read must be preceded with a write to the communications register. With the ADE7758 in communications mode and CS logic low, an 8-bit write to the communications register takes place first. The MSB of this byte transfer must be a 0, indicating that the next data transfer operation is a read. The seven LSBs of this byte contain the address of the register that is to be read. The starts shifting out of the register data on the next rising edge of SCLK (see ). At this point, the DOUT logic output switches from a high impedance state and starts driving the data bus. All remaining bits of register data are shifted out on subsequent SCLK rising edges. The serial interface enters communications mode again as soon as the read is completed. The DOUT logic output enters a high impedance state on the falling edge of the last SCLK pulse. ADE7758Figure 94 The read operation can be aborted by bringing the CS logic input high before the data transfer is completed. The DOUT output enters a high impedance state on the rising edge of CS. When an ADE7758 register is addressed for a read operation, the entire contents of that register are transferred to the serial port. This allows the ADE7758 to modify its on-chip registers without the risk of corrupting data during a multibyte transfer. Note that when a read operation follows a write operation, the read command (that is, write to communications register) should not happen for at least 1.1 μs after the end of the write operation. If the read command is sent within 1.1 μs of the write operation, the last byte of the write operation can be lost. ACCESSING THE ON-CHIP REGISTERS All ADE7758 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications register and then transferring the register data. For a full description of the serial interface protocol, see the Serial Interface section. ADE7758 Data Sheet Rev. E | Page 60 of 72 REGISTERS COMMUNICATIONS REGISTER The communications register is an 8-bit, write-only register that controls the serial data transfer between the ADE7758 and the host processor. All data transfer operations must begin with a write to the communications register. The data written to the communications register determines whether the next operation is a read or a write and which register is being accessed. Table 16 outlines the bit designations for the communications register. Table 16. Communications Register Bit Location Bit Mnemonic Description 0 to 6 A0 to A6 The seven LSBs of the communications register specify the register for the data transfer operation. Table 17 lists the address of each ADE7758 on-chip register. 7 W/R When this bit is a Logic 1, the data transfer operation immediately following the write to the communications register is interpreted as a write to the ADE7758. When this bit is a Logic 0, the data transfer operation immediately following the write to the communications register is interpreted as a read operation. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W/R A6 A5 A4 A3 A2 A1 A0 Table 17. ADE7758 Register List Address [A6:A0] Name R/W1 Length Type2 Default Value Description 0x00 Reserved – Reserved. 0x01 AWATTHR R 16 S 0 Watt-Hour Accumulation Register for Phase A. Active power is accumulated over time in this read-only register. The AWATTHR register can hold a maximum of 0.52 seconds of active energy information with full-scale analog inputs before it overflows (see the Active Energy Calculation section). Bit 0 and Bit 1 of the COMPMODE register determine how the active energy is processed from the six analog inputs. 0x02 BWATTHR R 16 S 0 Watt-Hour Accumulation Register for Phase B. 0x03 CWATTHR R 16 S 0 Watt-Hour Accumulation Register for Phase C. 0x04 AVARHR R 16 S 0 VAR-Hour Accumulation Register for Phase A. Reactive power is accumulated over time in this read-only register. The AVARHR register can hold a maximum of 0.52 seconds of reactive energy information with full-scale analog inputs before it overflows (see the Reactive Energy Calculation section). Bit 0 and Bit 1 of the COMPMODE register determine how the reactive energy is processed from the six analog inputs. 0x05 BVARHR R 16 S 0 VAR-Hour Accumulation Register for Phase B. 0x06 CVARHR R 16 S 0 VAR-Hour Accumulation Register for Phase C. 0x07 AVAHR R 16 S 0 VA-Hour Accumulation Register for Phase A. Apparent power is accumulated over time in this read-only register. The AVAHR register can hold a maximum of 1.15 seconds of apparent energy information with full-scale analog inputs before it overflows (see the Apparent Energy Calculation section). Bit 0 and Bit 1 of the COMPMODE register determine how the apparent energy is processed from the six analog inputs. 0x08 BVAHR R 16 S 0 VA-Hour Accumulation Register for Phase B. 0x09 CVAHR R 16 S 0 VA-Hour Accumulation Register for Phase C. 0x0A AIRMS R 24 S 0 Phase A Current Channel RMS Register. The register contains the rms component of the Phase A input of the current channel. The source is selected by data bits in the mode register. 0x0B BIRMS R 24 S 0 Phase B Current Channel RMS Register. 0x0C CIRMS R 24 S 0 Phase C Current Channel RMS Register. 0x0D AVRMS R 24 S 0 Phase A Voltage Channel RMS Register. Data Sheet ADE7758 Rev. E | Page 61 of 72 Address [A6:A0] Name R/W1 Length Type2 Default Value Description 0x0E BVRMS R 24 S 0 Phase B Voltage Channel RMS Register. 0x0F CVRMS R 24 S 0 Phase C Voltage Channel RMS Register. 0x10 FREQ R 12 U 0 Frequency of the Line Input Estimated by the Zero-Crossing Processing. It can also display the period of the line input. Bit 7 of the LCYCMODE register determines if the reading is frequency or period. Default is frequency. Data Bit 0 and Bit 1 of the MMODE register determine the voltage channel used for the frequency or period calculation. 0x11 TEMP R 8 S 0 Temperature Register. This register contains the result of the latest temperature conversion. Refer to the Temperature Measurement section for details on how to interpret the content of this register. 0x12 WFORM R 24 S 0 Waveform Register. This register contains the digitized waveform of one of the six analog inputs or the digitized power waveform. The source is selected by Data Bit 0 to Bit 4 in the WAVMODE register. 0x13 OPMODE R/W 8 U 4 Operational Mode Register. This register defines the general configuration of the ADE7758 (see Table 18). 0x14 MMODE R/W 8 U 0xFC Measurement Mode Register. This register defines the channel used for period and peak detection measurements (see Table 19). 0x15 WAVMODE R/W 8 U 0 Waveform Mode Register. This register defines the channel and sampling frequency used in the waveform sampling mode (see Table 20). 0x16 COMPMODE R/W 8 U 0x1C Computation Mode Register. This register configures the formula applied for the energy and line active energy measurements (see Table 22). 0x17 LCYCMODE R/W 8 U 0x78 Line Cycle Mode Register. This register configures the line cycle accumulation mode for WATT-HR, VAR-HR, and VA-Hr (see Table 23). 0x18 Mask R/W 24 U 0 IRQ Mask Register. It determines if an interrupt event generates an active-low output at the IRQ pin (see the section). Interrupts 0x19 Status R 24 U 0 IRQ Status Register. This register contains information regarding the source of the interrupts (see the section). ADE7758Interrupts 0x1A RSTATUS R 24 U 0 IRQ Reset Status Register. Same as the STATUS register, except that its contents are reset to 0 (all flags cleared) after a read operation. 0x1B ZXTOUT R/W 16 U 0xFFFF Zero-Cross Timeout Register. If no zero crossing is detected within the time period specified by this register, the interrupt request line (IRQ) goes active low for the corresponding line voltage. The maximum timeout period is 2.3 seconds (see the section). Zero-Crossing Detection 0x1C LINECYC R/W 16 U 0xFFFF Line Cycle Register. The content of this register sets the number of half-line cycles that the active, reactive, and apparent energies are accumulated for in the line accumulation mode. 0x1D SAGCYC R/W 8 U 0xFF SAG Line Cycle Register. This register specifies the number of consecutive half-line cycles where voltage channel input may fall below a threshold level. This register is common to the three line voltage SAG detection. The detection threshold is specified by the SAGLVL register (see the Line Voltage SAG Detection section). 0x1E SAGLVL R/W 8 U 0 SAG Voltage Level. This register specifies the detection threshold for the SAG event. This register is common to all three phases’ line voltage SAG detections. See the description of the SAGCYC register for details. 0x1F VPINTLVL R/W 8 U 0xFF Voltage Peak Level Interrupt Threshold Register. This register sets the level of the voltage peak detection. Bit 5 to Bit 7 of the MMODE register determine which phases are to be monitored. If the selected voltage phase exceeds this level, the PKV flag in the IRQ status register is set. 0x20 IPINTLVL R/W 8 U 0xFF Current Peak Level Interrupt Threshold Register. This register sets the level of the current peak detection. Bit 5 to Bit 7 of the MMODE register determine which phases are to be monitored. If the selected current phase exceeds this level, the PKI flag in the IRQ status register is set. 0x21 VPEAK R 8 U 0 Voltage Peak Register. This register contains the value of the peak voltage waveform that has occurred within a fixed number of half-line cycles. The number of half-line cycles is set by the LINECYC register. ADE7758 Data Sheet Rev. E | Page 62 of 72 Address [A6:A0] Name R/W1 Length Type2 Default Value Description 0x22 IPEAK R 8 U 0 Current Peak Register. This register holds the value of the peak current waveform that has occurred within a fixed number of half-line cycles. The number of half-line cycles is set by the LINECYC register. 0x23 Gain R/W 8 U 0 PGA Gain Register. This register is used to adjust the gain selection for the PGA in the current and voltage channels (see the Analog Inputs section). 0x24 AVRMSGAIN R/W 12 S 0 Phase A VRMS Gain Register. The range of the voltage rms calculation can be adjusted by writing to this register. It has an adjustment range of ±50% with a resolution of 0.0244%/LSB. 0x25 BVRMSGAIN R/W 12 S 0 Phase B VRMS Gain Register. 0x26 CVRMSGAIN R/W 12 S 0 Phase C VRMS Gain Register. 0x27 AIGAIN R/W 12 S 0 Phase A Current Gain Register. This register is not recommended to be used and it should be kept at 0, its default value. 0x28 BIGAIN R/W 12 S 0 Phase B Current Gain Register. This register is not recommended to be used and it should be kept at 0, its default value. 0x29 CIGAIN R/W 12 S 0 Phase C Current Gain Register. This register is not recommended to be used and it should be kept at 0, its default value. 0x2A AWG R/W 12 S 0 Phase A Watt Gain Register. The range of the watt calculation can be adjusted by writing to this register. It has an adjustment range of ±50% with a resolution of 0.0244%/LSB. 0x2B BWG R/W 12 S 0 Phase B Watt Gain Register. 0x2C CWG R/W 12 S 0 Phase C Watt Gain Register. 0x2D AVARG R/W 12 S 0 Phase A VAR Gain Register. The range of the VAR calculation can be adjusted by writing to this register. It has an adjustment range of ±50% with a resolution of 0.0244%/LSB. 0x2E BVARG R/W 12 S 0 Phase B VAR Gain Register. 0x2F CVARG R/W 12 S 0 Phase C VAR Gain Register. 0x30 AVAG R/W 12 S 0 Phase A VA Gain Register. The range of the VA calculation can be adjusted by writing to this register. It has an adjustment range of ±50% with a resolution of 0.0244%/LSB. 0x31 BVAG R/W 12 S 0 Phase B VA Gain Register. 0x32 CVAG R/W 12 S 0 Phase C VA Gain Register. 0x33 AVRMSOS R/W 12 S 0 Phase A Voltage RMS Offset Correction Register. 0x34 BVRMSOS R/W 12 S 0 Phase B Voltage RMS Offset Correction Register. 0x35 CVRMSOS R/W 12 S 0 Phase C Voltage RMS Offset Correction Register. 0x36 AIRMSOS R/W 12 S 0 Phase A Current RMS Offset Correction Register. 0x37 BIRMSOS R/W 12 S 0 Phase B Current RMS Offset Correction Register. 0x38 CIRMSOS R/W 12 S 0 Phase C Current RMS Offset Correction Register. 0x39 AWATTOS R/W 12 S 0 Phase A Watt Offset Calibration Register. 0x3A BWATTOS R/W 12 S 0 Phase B Watt Offset Calibration Register. 0x3B CWATTOS R/W 12 S 0 Phase C Watt Offset Calibration Register. 0x3C AVAROS R/W 12 S 0 Phase A VAR Offset Calibration Register. 0x3D BVAROS R/W 12 S 0 Phase B VAR Offset Calibration Register. 0x3E CVAROS R/W 12 S 0 Phase C VAR Offset Calibration Register. 0x3F APHCAL R/W 7 S 0 Phase A Phase Calibration Register. The phase relationship between the current and voltage channel can be adjusted by writing to this signed 7-bit register (see the Phase Compensation section). 0x40 BPHCAL R/W 7 S 0 Phase B Phase Calibration Register. 0x41 CPHCAL R/W 7 S 0 Phase C Phase Calibration Register. 0x42 WDIV R/W 8 U 0 Active Energy Register Divider. 0x43 VARDIV R/W 8 U 0 Reactive Energy Register Divider. 0x44 VADIV R/W 8 U 0 Apparent Energy Register Divider. Data Sheet ADE7758 Rev. E | Page 63 of 72 Address [A6:A0] Name R/W1 Length Type2 Default Value Description 0x45 APCFNUM R/W 16 U 0 Active Power CF Scaling Numerator Register. The content of thisregister is used in the numerator of the APCF output scaling calculation. Bits [15:13] indicate reverse polarity active power measurement for Phase A, Phase B, and Phase C in order; that is, Bit 15 is Phase A, Bit 14 is Phase B, and so on. 0x46 APCFDEN R/W 12 U 0x3F Active Power CF Scaling Denominator Register. The content of this register is used in the denominator of the APCF output scaling. 0x47 VARCFNUM R/W 16 U 0 Reactive Power CF Scaling Numerator Register. The content of this register is used in the numerator of the VARCF output scaling. Bits [15:13] indicate reverse polarity reactive power measurement for Phase A, Phase B, and Phase C in order; that is, Bit 15 is Phase A, Bit 14 is Phase B, and so on. 0x48 VARCFDEN R/W 12 U 0x3F Reactive Power CF Scaling Denominator Register. The content of this register is used in the denominator of the VARCF output scaling. 0x49 to 0x7D Reserved − − – − Reserved. 0x7E CHKSUM R 8 U − Checksum Register. The content of this register represents the sum of all the ones in the last register read from the SPI port. 0x7F Version R 8 U − Version of the Die. 1 This column specifies the read/write capability of the register. R = Read only register. R/W = Register that can be both read and written. 2 Type decoder: U = unsigned; S = signed. ADE7758 Data Sheet Rev. E | Page 64 of 72 OPERATIONAL MODE REGISTER (0x13) The general configuration of the ADE7758 is defined by writing to the OPMODE register. Table 18 summarizes the functionality of each bit in the OPMODE register. Table 18. OPMODE Register Bit Location Bit Mnemonic Default Value Description 0 DISHPF 0 The HPFs in all current channel inputs are disabled when this bit is set. 1 DISLPF 0 The LPFs after the watt and VAR multipliers are disabled when this bit is set. 2 DISCF 1 The frequency outputs APCF and VARCF are disabled when this bit is set. 3 to 5 DISMOD 0 By setting these bits, the ADE7758 ADCs can be turned off. In normal operation, these bits should be left at Logic 0. DISMOD[2:0] Description 0 0 0 Normal operation. 1 0 0 Redirect the voltage inputs to the signal paths for the current channels and the current inputs to the signal paths for the voltage channels. 0 0 1 Switch off only the current channel ADCs. 1 0 1 Switch off current channel ADCs and redirect the current input signals to the voltage channel signal paths. 0 1 0 Switch off only the voltage channel ADCs. 1 1 0 Switch off voltage channel ADCs and redirect the voltage input signals to the current channel signal paths. 0 1 1 Put the ADE7758 in sleep mode. 1 1 1 Put the ADE7758 in power-down mode (reduces AIDD to 1 mA typ). 6 SWRST 0 Software Chip Reset. A data transfer to the ADE7758 should not take place for at least 166 μs after a software reset. 7 Reserved 0 This should be left at 0. MEASUREMENT MODE REGISTER (0x14) The configuration of the PERIOD and peak measurements made by the ADE7758 is defined by writing to the MMODE register. Table 19 summarizes the functionality of each bit in the MMODE register. Table 19. MMODE Register Bit Location Bit Mnemonic Default Value Description 0 to 1 FREQSEL 0 These bits are used to select the source of the measurement of the voltage line frequency. FREQSEL1 FREQSEL0 Source 0 0 Phase A 0 1 Phase B 1 0 Phase C 1 1 Reserved 2 to 4 PEAKSEL 7 These bits select the phases used for the voltage and current peak registers. Setting Bit 2 switches the IPEAK and VPEAK registers to hold the absolute values of the largest current and voltage waveform (over a fixed number of half-line cycles) from Phase A. The number of half-line cycles is determined by the content of the LINECYC register. At the end of the LINECYC number of half-line cycles, the content of the registers is replaced with the new peak values. Similarly, setting Bit 3 turns on the peak detection for Phase B, and Bit 4 for Phase C. Note that if more than one bit is set, the VPEAK and IPEAK registers can hold values from two different phases, that is, the voltage and current peak are independently processed (see the Peak Current Detection section). 5 to 7 PKIRQSEL 7 These bits select the phases used for the peak interrupt detection. Setting Bit 5 switches on the monitoring of the absolute current and voltage waveform to Phase A. Similarly, setting Bit 6 turns on the waveform detection for Phase B, and Bit 7 for Phase C. Note that more than one bit can be set for detection on multiple phases. If the absolute values of the voltage or current waveform samples in the selected phases exceeds the preset level specified in the VPINTLVL or IPINTLVL registers the corresponding bit(s) in the STATUS registers are set (see the Peak Current Detection section). Data Sheet ADE7758 Rev. E | Page 65 of 72 WAVEFORM MODE REGISTER (0x15) The waveform sampling mode of the ADE7758 is defined by writing to the WAVMODE register. Table 20 summarizes the functionality of each bit in the WAVMODE register. Table 20. WAVMODE Register Bit Location Bit Mnemonic Default Value Description 0 to 1 PHSEL 0 These bits are used to select the phase of the waveform sample. PHSEL[1:0] Source 0 0 Phase A 0 1 Phase B 1 0 Phase C 1 1 Reserved 2 to 4 WAVSEL 0 These bits are used to select the type of waveform. WAVSEL[2:0] Source 0 0 0 Current 0 0 1 Voltage 0 1 0 Active Power Multiplier Output 0 1 1 Reactive Power Multiplier Output 1 0 0 VA Multiplier Output Others- Reserved 5 to 6 DTRT 0 These bits are used to select the data rate. DTRT[1:0] Update Rate 0 0 26.04 kSPS (CLKIN/3/128) 0 1 13.02 kSPS (CLKIN/3/256) 1 0 6.51 kSPS (CLKIN/3/512) 1 1 3.25 kSPS (CLKIN/3/1024) 7 VACF 0 Setting this bit to Logic 1 switches the VARCF output pin to an output frequency that is proportional to the total apparent power (VA). In the default state, Logic 0, the VARCF pin outputs a frequency proportional to the total reactive power (VAR). ADE7758 Data Sheet Rev. E | Page 66 of 72 COMPUTATIONAL MODE REGISTER (0x16) The computational method of the ADE7758 is defined by writing to the COMPMODE register. Table 21 summarizes the functionality of each bit in the COMPMODE register. Table 21. COMPMODE Register Bit Location Bit Mnemonic Default Value Description 0 to 1 CONSEL 0 These bits are used to select the input to the energy accumulation registers. CONSEL[1:0] = 11 is reserved. IA, IB, and IC are IA, IB, and IC phase shifted by –90°, respectively. Registers CONSEL[1, 0] = 00 CONSEL[1, 0] = 01 CONSEL[1, 0] = 10 AWATTHR VA × IA VA × (IA – IB) VA × (IA–IB) BWATTHR VB × IB 0 0 CWATTHR VC × IC VC × (IC – IB) VC × IC AVARHR VA × IA VA × (IA – IB) VA × (IA–IB) BVARHR VB × IB 0 0 CVARHR VC × IC VC × (IC – IB) VC × IC AVAHR VARMS × IARMS VARMS × IARMS VARMS × ARMS BVAHR VBRMS × IBRMS (VARMS + VCRMS)/2 × IBRMS VARMS × IBRMS CVAHR VCRMS × ICRMS VCRMS × ICRMS VCRMS × ICRMS 2 to 4 TERMSEL 7 These bits are used to select the phases to be included in the APCF and VARCF pulse outputs. Setting Bit 2 selects Phase A (the inputs to AWATTHR and AVARHR registers) to be included. Bit 3 and Bit 4 are for Phase B and Phase C, respectively. Setting all three bits enables the sum of all three phases to be included in the frequency outputs (see the Active Power Frequency Output and the Reactive Power Frequency Output sections). 5 ABS 0 Setting this bit places the APCF output pin in absolute only mode. Namely, the APCF output frequency is proportional to the sum of the absolute values of the watt-hour accumulation registers (AWATTHR, BWATTHR, and CWATTHR). Note that this bit only affects the APCF pin and has no effect on the content of the corresponding registers. 6 SAVAR 0 Setting this bit places the VARCF output pin in the signed adjusted mode. Namely, the VARCF output frequency is proportional to the sign-adjusted sum of the VAR-hour accumulation registers (AVARHR, BVARHR, and CVARHR). The sign of the VAR is determined from the sign of the watt calculation from the corresponding phase, that is, the sign of the VAR is flipped if the sign of the watt is negative, and if the watt is positive, there is no change to the sign of the VAR. Note that this bit only affects the VARCF pin and has no effect on the content of the corresponding registers. 7 NOLOAD 0 Setting this bit activates the no-load threshold in the ADE7758. Data Sheet ADE7758 Rev. E | Page 67 of 72 LINE CYCLE ACCUMULATION MODE REGISTER (0x17) The functionalities involved the line-cycle accumulation mode in the ADE7758 are defined by writing to the LCYCMODE register. Table 22 summarizes the functionality of each bit in the LCYCMODE register. Table 22. LCYCMODE Register Bit Location Bit Mnemonic Default Value Description 0 LWATT 0 Setting this bit places the watt-hour accumulation registers (AWATTHR, BWATTHR, and CWATTHR registers) into line-cycle accumulation mode. 1 LVAR 0 Setting this bit places the VAR-hour accumulation registers (AVARHR, BVARHR, and CVARHR registers) into line-cycle accumulation mode. 2 LVA 0 Setting this bit places the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR registers) into line-cycle accumulation mode. 3 to 5 ZXSEL 7 These bits select the phases used for counting the number of zero crossings in the line-cycle accumulation mode. Bit 3, Bit 4, and Bit 5 select Phase A, Phase B, and Phase C, respectively. More than one phase can be selected for the zero-crossing detection, and the accumulation time is shortened accordingly. 6 RSTREAD 1 Setting this bit enables the read-with-reset for all the WATTHR, VARHR, and VAHR registers for all three phases, that is, a read to those registers resets the registers to 0 after the content of the registers have been read. This bit should be set to Logic 0 when the LWATT, LVAR, or LVA bits are set to Logic 1. 7 FREQSEL 0 Setting this bit causes the FREQ (0x10) register to display the period, instead of the frequency of the line input. ADE7758 Data Sheet Rev. E | Page 68 of 72 INTERRUPT MASK REGISTER (0x18) When an interrupt event occurs in the ADE7758, the IRQ logic output goes active low if the mask bit for this event is Logic 1 in the MASK register. The IRQ logic output is reset to its default collector open state when the RSTATUS register is read. describes the function of each bit in the interrupt mask register. Table 23 Table 23. Function of Each Bit in the Interrupt Mask Register Bit Location Interrupt Flag Default Value Description 0 AEHF 0 Enables an interrupt when there is a change in Bit 14 of any one of the three WATTHR registers, that is, the WATTHR register is half full. 1 REHF 0 Enables an interrupt when there is a change in Bit 14 of any one of the three VARHR registers, that is, the VARHR register is half full. 2 VAEHF 0 Enables an interrupt when there is a 0 to 1 transition in the MSB of any one of the three VAHR registers, that is, the VAHR register is half full. 3 SAGA 0 Enables an interrupt when there is a SAG on the line voltage of the Phase A. 4 SAGB 0 Enables an interrupt when there is a SAG on the line voltage of the Phase B. 5 SAGC 0 Enables an interrupt when there is a SAG on the line voltage of the Phase C. 6 ZXTOA 0 Enables an interrupt when there is a zero-crossing timeout detection on Phase A. 7 ZXTOB 0 Enables an interrupt when there is a zero-crossing timeout detection on Phase B. 8 ZXTOC 0 Enables an interrupt when there is a zero-crossing timeout detection on Phase C. 9 ZXA 0 Enables an interrupt when there is a zero crossing in the voltage channel of Phase A (see the Zero-Crossing Detection section). 10 ZXB 0 Enables an interrupt when there is a zero crossing in the voltage channel of Phase B (see the Zero-Crossing Detection section). 11 ZXC 0 Enables an interrupt when there is a zero crossing in the voltage channel of Phase C (see the Zero-Crossing Detection section). 12 LENERGY 0 Enables an interrupt when the energy accumulations over LINECYC are finished. 13 Reserved 0 Reserved. 14 PKV 0 Enables an interrupt when the voltage input selected in the MMODE register is above the value in the VPINTLVL register. 15 PKI 0 Enables an interrupt when the current input selected in the MMODE register is above the value in the IPINTLVL register. 16 WFSM 0 Enables an interrupt when data is present in the WAVEMODE register. 17 REVPAP 0 Enables an interrupt when there is a sign change in the watt calculation among any one of the phases specified by the TERMSEL bits in the COMPMODE register. 18 REVPRP 0 Enables an interrupt when there is a sign change in the VAR calculation among any one of the phases specified by the TERMSEL bits in the COMPMODE register. 19 SEQERR 0 Enables an interrupt when the zero crossing from Phase A is followed not by the zero crossing of Phase C but with that of Phase B. Data Sheet ADE7758 Rev. E | Page 69 of 72 INTERRUPT STATUS REGISTER (0x19)/RESET INTERRUPT STATUS REGISTER (0x1A) The interrupt status register is used to determine the source of an interrupt event. When an interrupt event occurs in the ADE7758, the corresponding flag in the interrupt status register is set. The IRQ pin goes active low if the corresponding bit in the interrupt mask register is set. When the MCU services the interrupt, it must first carry out a read from the interrupt status register to determine the source of the interrupt. All the interrupts in the interrupt status register stay at their logic high state after an event occurs. The state of the interrupt bit in the interrupt status register is reset to its default value once the reset interrupt status register is read. Table 24. Interrupt Status Register Bit Location Interrupt Flag Default Value Event Description 0 AEHF 0 Indicates that an interrupt was caused by a change in Bit 14 among any one of the three WATTHR registers, that is, the WATTHR register is half full. 1 REHF 0 Indicates that an interrupt was caused by a change in Bit 14 among any one of the three VARHR registers, that is, the VARHR register is half full. 2 VAEHF 0 Indicates that an interrupt was caused by a 0 to 1 transition in Bit 15 among any one of the three VAHR registers, that is, the VAHR register is half full. 3 SAGA 0 Indicates that an interrupt was caused by a SAG on the line voltage of the Phase A. 4 SAGB 0 Indicates that an interrupt was caused by a SAG on the line voltage of the Phase B. 5 SAGC 0 Indicates that an interrupt was caused by a SAG on the line voltage of the Phase C. 6 ZXTOA 0 Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase A. 7 ZXTOB 0 Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase B. 8 ZXTOC 0 Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase C. 9 ZXA 0 Indicates a detection of a rising edge zero crossing in the voltage channel of Phase A. 10 ZXB 0 Indicates a detection of a rising edge zero crossing in the voltage channel of Phase B. 11 ZXC 0 Indicates a detection of a rising edge zero crossing in the voltage channel of Phase C. 12 LENERGY 0 In line energy accumulation, indicates the end of an integration over an integer number of half-line cycles (LINECYC). See the Calibration section. 13 Reset 1 After Bit 6 (SWRST) in OPMODE register is set to 1, the ADE7758 enters software reset. This bit becomes 1 after 166 μsec, indicating the reset process has ended and the registers are set to their default values. It stays 1 until the reset interrupt status register is read and then becomes 0. 14 PKV 0 Indicates that an interrupt was caused when the selected voltage input is above the value in the VPINTLVL register. 15 PKI 0 Indicates that an interrupt was caused when the selected current input is above the value in the IPINTLVL register. 16 WFSM 0 Indicates that new data is present in the waveform register. 17 REVPAP 0 Indicates that an interrupt was caused by a sign change in the watt calculation among any one of the phases specified by the TERMSEL bits in the COMPMODE register. 18 REVPRP 0 Indicates that an interrupt was caused by a sign change in the VAR calculation among any one of the phases specified by the TERMSEL bits in the COMPMODE register. 19 SEQERR 0 Indicates that an interrupt was caused by a zero crossing from Phase A followed not by the zero crossing of Phase C but by that of Phase B. ADE7758 Data Sheet Rev. E | Page 70 of 72 OUTLINE DIMENSIONS COMPLIANTTOJEDECSTANDARDSMS-013-ADCONTROLLINGDIMENSIONSAREINMILLIMETERS;INCHDIMENSIONS(INPARENTHESES)AREROUNDED-OFFMILLIMETEREQUIVALENTSFORREFERENCEONLYANDARENOTAPPROPRIATEFORUSEINDESIGN.15.60(0.6142)15.20(0.5984)0.30(0.0118)0.10(0.0039)2.65(0.1043)2.35(0.0925)10.65(0.4193)10.00(0.3937)7.60(0.2992)7.40(0.2913)0.75(0.0295)0.25(0.0098)45°1.27(0.0500)0.40(0.0157)COPLANARITY0.100.33(0.0130)0.20(0.0079)0.51(0.0201)0.31(0.0122)SEATINGPLANE8°0°24131211.27(0.0500)BSC12-09-2010-A Figure 95. 24-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-24) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADE7758ARWZ −40°C to + 85°C 24-Lead Wide Body SOIC_W RW-24 ADE7758ARWZRL −40°C to + 85°C 24-Lead Wide Body SOIC_W RW-24 EVAL-ADE7758ZEB Evaluation Board 1 Z = RoHS Compliant Part. Data Sheet ADE7758 Rev. E | Page 71 of 72 NOTES ADE7758 Data Sheet Rev. E | Page 72 of 72 NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04443-0-10/11(E) 1 2 3 4 8 7 6 5 GND TRIG OUT RESET VCC DISCH THRES CONT 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 NC DISCH NC THRES NC NC TRIG NC OUT NC NC GND NC CONT NC VCC NC NC RESET NC NC – No internal connection NA555...D OR P PACKAGE NE555...D, P, PS, OR PW PACKAGE SA555...D OR P PACKAGE SE555...D, JG, OR P PACKAGE (TOP VIEW) SE555...FK PACKAGE (TOP VIEW) NA555, NE555, SA555, SE555 www.ti.com SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010 PRECISION TIMERS Check for Samples: NA555, NE555, SA555, SE555 1FEATURES • Timing From Microseconds to Hours • Adjustable Duty Cycle • Astable or Monostable Operation • TTL-Compatible Output Can Sink or Source up to 200 mA DESCRIPTION/ORDERING INFORMATION These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground. The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1973–2010, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not On products compliant to MIL-PRF-38535, all parameters are necessarily include testing of all parameters. tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. NA555, NE555, SA555, SE555 SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010 www.ti.com ORDERING INFORMATION(1) T VTHRES MAX A V PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING CC = 15 V PDIP – P Tube of 50 NE555P NE555P Tube of 75 NE555D SOIC – D NE555 Reel of 2500 NE555DR 0°C to 70°C 11.2 V SOP – PS Reel of 2000 NE555PSR N555 Tube of 150 NE555PW TSSOP – PW N555 Reel of 2000 NE555PWR PDIP – P Tube of 50 SA555P SA555P –40°C to 85°C 11.2 V Tube of 75 SA555D SOIC – D SA555 Reel of 2000 SA555DR PDIP – P Tube of 50 NA555P NA555P –40°C to 105°C 11.2 V Tube of 75 NA555D SOIC – D NA555 Reel of 2000 NA555DR PDIP – P Tube of 50 SE555P SE555P Tube of 75 SE555D SOIC – D SE555D –55°C to 125°C 10.6 Reel of 2500 SE555DR CDIP – JG Tube of 50 SE555JG SE555JG LCCC – FK Tube of 55 SE555FK SE555FK (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Table 1. FUNCTION TABLE RESET TRIGGER THRESHOLD OUTPUT DISCHARGE VOLTAGE(1) VOLTAGE(1) SWITCH Low Irrelevant Irrelevant Low On High <1/3 VCC Irrelevant High Off High >1/3 VCC >2/3 VCC Low On High >1/3 VCC <2/3 VCC As previously established (1) Voltage levels shown are nominal. 2 Submit Documentation Feedback Copyright © 1973–2010, Texas Instruments Incorporated Product Folder Link(s): NA555 NE555 SA555 SE555 1 S R R1 TRIG THRES VCC CONT RESET OUT DISCH GND ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Î ÎÎÎ 8 4 5 6 2 1 7 3 NA555, NE555, SA555, SE555 www.ti.com SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010 FUNCTIONAL BLOCK DIAGRAM A. Pin numbers shown are for the D, JG, P, PS, and PW packages. B. RESET can override TRIG, which can override THRES. Copyright © 1973–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): NA555 NE555 SA555 SE555 NA555, NE555, SA555, SE555 SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010 www.ti.com Absolute Maximum Ratings(1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage(2) 18 V VI Input voltage CONT, RESET, THRES, TRIG VCC V IO Output current ±225 mA D package 97 P package 85 qJA Package thermal impedance(3) (4) °C/W PS package 95 PW package 149 FK package 5.61 qJC Package thermal impedance(5) (6) °C/W JG package 14.5 TJ Operating virtual junction temperature 150 °C Case temperature for 60 s FK package 260 °C Lead temperature 1, 6 mm (1/16 in) from case for 60 s JG package 300 °C Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to GND. (3) Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability. (4) The package thermal impedance is calculated in accordance with JESD 51-7. (5) Maximum power dissipation is a function of TJ(max), qJC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) - TC)/qJC. Operating at the absolute maximum TJ of 150°C can affect reliability. (6) The package thermal impedance is calculated in accordance with MIL-STD-883. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT NA555, NE555, SA555 4.5 16 VCC Supply voltage V SE555 4.5 18 VI Input voltage CONT, RESET, THRES, and TRIG VCC V IO Output current ±200 mA NA555 –40 105 NE555 0 70 TA Operating free-air temperature °C SA555 –40 85 SE555 –55 125 4 Submit Documentation Feedback Copyright © 1973–2010, Texas Instruments Incorporated Product Folder Link(s): NA555 NE555 SA555 SE555 NA555, NE555, SA555, SE555 www.ti.com SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010 Electrical Characteristics VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted) NA555 SE555 NE555 PARAMETER TEST CONDITIONS SA555 UNIT MIN TYP MAX MIN TYP MAX VCC = 15 V 9.4 10 10.6 8.8 10 11.2 THRES voltage level V VCC = 5 V 2.7 3.3 4 2.4 3.3 4.2 THRES current(1) 30 250 30 250 nA 4.8 5 5.2 4.5 5 5.6 VCC = 15 V TA = –55°C to 125°C 3 6 TRIG voltage level V 1.45 1.67 1.9 1.1 1.67 2.2 VCC = 5 V TA = –55°C to 125°C 1.9 TRIG current TRIG at 0 V 0.5 0.9 0.5 2 mA 0.3 0.7 1 0.3 0.7 1 RESET voltage level V TA = –55°C to 125°C 1.1 RESET at VCC 0.1 0.4 0.1 0.4 RESET current mA RESET at 0 V –0.4 –1 –0.4 –1.5 DISCH switch off-state 20 100 20 100 nA current 9.6 10 10.4 9 10 11 VCC = 15 V CONT voltage TA = –55°C to 125°C 9.6 10.4 (open circuit) V 2.9 3.3 3.8 2.6 3.3 4 VCC = 5 V TA = –55°C to 125°C 2.9 3.8 0.1 0.15 0.1 0.25 VCC = 15 V, IOL = 10 mA TA = –55°C to 125°C 0.2 0.4 0.5 0.4 0.75 VCC = 15 V, IOL = 50 mA TA = –55°C to 125°C 1 2 2.2 2 2.5 VCC = 15 V, IOL = 100 mA Low-level output voltage TA = –55°C to 125°C 2.7 V VCC = 15 V, IOL = 200 mA 2.5 2.5 VCC = 5 V, IOL = 3.5 mA TA = –55°C to 125°C 0.35 0.1 0.2 0.1 0.35 VCC = 5 V, IOL = 5 mA TA = –55°C to 125°C 0.8 VCC = 5 V, IOL = 8 mA 0.15 0.25 0.15 0.4 13 13.3 12.75 13.3 VCC = 15 V, IOL = –100 mA TA = –55°C to 125°C 12 High-level output voltage VCC = 15 V, IOH = –200 mA 12.5 12.5 V 3 3.3 2.75 3.3 VCC = 5 V, IOL = –100 mA TA = –55°C to 125°C 2 VCC = 15 V 10 12 10 15 Output low, No load VCC = 5 V 3 5 3 6 Supply current mA VCC = 15 V 9 10 9 13 Output high, No load VCC = 5 V 2 4 2 5 (1) This parameter influences the maximum value of the timing resistors RA and RB in the circuit of Figure 12. For example, when VCC = 5 V, the maximum value is R = RA + RB ≉ 3.4 MΩ, and for VCC = 15 V, the maximum value is 10 MΩ. Copyright © 1973–2010, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): NA555 NE555 SA555 SE555 NA555, NE555, SA555, SE555 SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010 www.ti.com Operating Characteristics VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted) NA555 TEST SE555 NE555 PARAMETER CONDITIONS(1) SA555 UNIT MIN TYP MAX MIN TYP MAX Initial error of timing Each timer, monostable(3) TA = 25°C 0.5 1.5(4) 1 3 interval(2) % Each timer, astable(5) 1.5 2.25 Temperature coefficient of Each timer, monostable(3) TA = MIN to MAX 30 100(4) 50 ppm/ timing interval Each timer, astable(5) 90 150 °C Supply-voltage sensitivity of Each timer, monostable(3) TA = 25°C 0.05 0.2(4) 0.1 0.5 timing interval %/V Each timer, astable(5) 0.15 0.3 Output-pulse rise time CL = 15 pF, 100 200(4) 100 300 ns TA = 25°C Output-pulse fall time CL = 15 pF, 100 200(4) 100 300 ns TA = 25°C (1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. (2) Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. (3) Values specified are for a device in a monostable circuit similar to Figure 9, with the following component values: RA = 2 kΩ to 100 kΩ, C = 0.1 mF. (4) On products compliant to MIL-PRF-38535, this parameter is not production tested. (5) Values specified are for a device in an astable circuit similar to Figure 12, with the following component values: RA = 1 kΩ to 100 kΩ, C = 0.1 mF. 6 Submit Documentation Feedback Copyright © 1973–2010, Texas Instruments Incorporated Product Folder Link(s): NA555 NE555 SA555 SE555 ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ TA = 125°C ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ TA = 25°C IOL − Low-Level Output Current − mA ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ VCC = 5 V LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ TA = −55°C 0.1 0.04 0.01 1 2 4 7 10 20 40 70 100 0.07 1 0.4 0.7 10 4 7 0.02 0.2 2 VOL − Low-Level Output Voltage − V ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ VCC = 10 V LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT VOL − Low-Level Output Voltage − V IOL − Low-Level Output Current − mA 0.1 0.04 0.01 1 2 4 7 10 20 40 70 100 0.07 1 0.4 0.7 10 4 7 0.02 0.2 2 ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ TA = 125°C ÏÏÏÏÏÏÏÏÏÏÏÏ TA = 25°C TA= −55°C TA = 125°C TA = 25°C TA = −55°C ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ VCC = 15 V LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT VOL − Low-Level Output Voltage − V IOL − Low-Level Output Current − mA 0.1 0.04 0.01 1 2 4 7 10 20 40 70 100 0.07 1 0.4 0.7 10 4 7 0.02 0.2 2 1 0.6 0.2 0 1.4 1.8 2.0 0.4 1.6 0.8 1.2 − IOH − High-Level Output Current − mA ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ TA = 125°C ÏÏÏÏÏÏÏÏÏÏÏÏ TA = 25°C 1 2 4 7 10 20 40 70 100 ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ VCC = 5 V to 15 V ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ TA = −55°C (VCC VOH) − Voltage Drop − V DROP BETWEEN SUPPLY VOLTAGE AND OUTPUT vs HIGH-LEVEL OUTPUT CURRENT NA555, NE555, SA555, SE555 www.ti.com SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010 TYPICAL CHARACTERISTICS Data for temperatures below 0°C and above 70°C are applicable for SE555 circuits only. Figure 1. Figure 2. Figure 3. Figure 4. Copyright © 1973–2010, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): NA555 NE555 SA555 SE555 5 4 2 1 0 9 3 5 6 7 8 9 10 11 − Supply Current − mA 7 6 8 SUPPLY CURRENT vs SUPPLY VOLTAGE 10 12 13 14 15 TA = 25°C TA = 125°C TA = −55°C Output Low, No Load ICC VCC − Supply Voltage − V 1 0.995 0.990 0.985 0 5 10 1.005 1.010 NORMALIZED OUTPUT PULSE DURATION (MONOSTABLE OPERATION) vs SUPPLY VOLTAGE 1.015 15 20 Pulse Duration Relative to Value at V C C = 10 V VCC − Supply Voltage − V 1 0.995 0.990 0.985 −75 −25 25 1.005 1.010 NORMALIZED OUTPUT PULSE DURATION (MONOSTABLE OPERATION) vs FREE-AIR TEMPERATURE 1.015 75 125 TA − Free-Air Temperature − °C −50 0 50 100 VCC = 10 V Pulse Duration Relative to Value at TA = 25C 0 100 200 300 400 500 600 700 800 900 1000 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Lowest Level of Trigger Pulse – ×VCC tPD – Propagation Delay Time – ns TA = 125°C TA = 70°C TA = 25°C TA = 0°C TA = –55°C PROPAGATION DELAY TIME vs LOWEST VOLTAGE LEVEL OF TRIGGER PULSE NA555, NE555, SA555, SE555 SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Data for temperatures below 0°C and above 70°C are applicable for SE555 circuits only. Figure 5. Figure 6. Figure 7. Figure 8. 8 Submit Documentation Feedback Copyright © 1973–2010, Texas Instruments Incorporated Product Folder Link(s): NA555 NE555 SA555 SE555 VCC (5 V to 15 V) RA RL Output GND OUT CONT VCC RESET DISCH THRES Input TRIG ÎÎÎ 5 8 4 7 6 2 3 1 Pin numbers shown are for the D, JG, P, PS, and PW packages. NA555, NE555, SA555, SE555 www.ti.com SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010 APPLICATION INFORMATION Monostable Operation For monostable operation, any of these timers can be connected as shown in Figure 9. If the output is low, application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high, and turns off Q1. Capacitor C then is charged through RA until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1. Figure 9. Circuit for Monostable Operation Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the sequence ends only if TRIG is high for at least 10 μs before the end of the timing interval. When the trigger is grounded, the comparator storage time can be as long as 10 μs, which limits the minimum monostable pulse width to 10 μs. Because of the threshold level and saturation voltage of Q1, the output pulse duration is approximately tw = 1.1RAC. Figure 11 is a plot of the time constant for various values of RA and C. The threshold levels and charge rates both are directly proportional to the supply voltage, VCC. The timing interval is, therefore, independent of the supply voltage, so long as the supply voltage is constant during the time interval. Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to VCC. Copyright © 1973–2010, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): NA555 NE555 SA555 SE555 − Output Pulse Duration − s C − Capacitance − mF 10 1 10−1 10−2 10−3 10−4 0.01 0.1 1 10 100 10−5 0.001 tw RA = 10 MW RA = 10 kW RA = 1 kW RA = 100 kW RA = 1 MW Voltage − 2 V/div Time − 0.1 ms/div ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ Capacitor Voltage Output Voltage Input Voltage ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ RA = 9.1 kW CL = 0.01 mF RL = 1 kW See Figure 9 Voltage − 1 V/div Time − 0.5 ms/div tH Capacitor Voltage tL Output Voltage ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RA = 5 k RL = 1 k RB = 3 k See Figure 12 C = 0.15 mF GND OUT CONT VCC RESET DISCH THRES TRIG C RB RA Output RL 0.01 mF VCC (5 V to 15 V) (see Note A) ÎÎÎ NOTE A: Decoupling CONT voltage to ground with a capacitor can improve operation. This should be evaluated for individual applications. Open 5 8 4 7 6 2 3 1 Pin numbers shown are for the D, JG, P, PS, and PW packages. NA555, NE555, SA555, SE555 SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010 www.ti.com Figure 10. Typical Monostable Waveforms Figure 11. Output Pulse Duration vs Capacitance Astable Operation As shown in Figure 12, adding a second resistor, RB, to the circuit of Figure 9 and connecting the trigger input to the threshold input causes the timer to self-trigger and run as a multivibrator. The capacitor C charges through RA and RB and then discharges through RB only. Therefore, the duty cycle is controlled by the values of RA and RB. This astable connection results in capacitor C charging and discharging between the threshold-voltage level (≉0.67 × VCC) and the trigger-voltage level (≉0.33 × VCC). As in the monostable circuit, charge and discharge times (and, therefore, the frequency and duty cycle) are independent of the supply voltage. Figure 12. Circuit for Astable Operation Figure 13. Typical Astable Waveforms 10 Submit Documentation Feedback Copyright © 1973–2010, Texas Instruments Incorporated Product Folder Link(s): NA555 NE555 SA555 SE555 tH  0.693 (RARB) C tL  0.693 (RB) C Other useful relationships are shown below. period  tHtL  0.693 (RA2RB) C frequency  1.44 (RA2RB) C Output driver duty cycle  tL tHtL  RB RA2RB Output waveform duty cycle  tL tH  RB RARB Low-to-high ratio  tH tHtL  1– RB RA2RB f − Free-Running Frequency − Hz C − Capacitance − mF 100 k 10 k 1 k 100 10 1 0.01 0.1 1 10 100 0.1 0.001 RA + 2 RB = 10 MW RA + 2 RB = 1 MW RA + 2 RB = 100 kW RA + 2 RB = 10 kW RA + 2 RB = 1 kW Time − 0.1 ms/div Voltage − 2 V/div ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VCC = 5 V RA = 1 kW C = 0.1 mF See Figure 15 Capacitor Voltage ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Voltage Input Voltage VCC (5 V to 15 V) DISCH OUT RESET VCC RL RA A5T3644 C THRES GND CONT TRIG Input 0.01 mF ÎÎÎÎÎÎÎÎÎÎÎÎ Output 4 8 3 7 6 2 5 1 Pin numbers shown are shown for the D, JG, P, PS, and PW packages. NA555, NE555, SA555, SE555 www.ti.com SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010 Figure 12 shows typical waveforms generated during astable operation. The output high-level duration tH and low-level duration tL can be calculated as follows: Figure . Figure 14. Free-Running Frequency Missing-Pulse Detector The circuit shown in Figure 15 can be used to detect a missing pulse or abnormally long spacing between consecutive pulses in a train of pulses. The timing interval of the monostable circuit is retriggered continuously by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing, missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output pulse as shown in Figure 16. Figure 15. Circuit for Missing-Pulse Detector Figure 16. Completed Timing Waveforms for Missing-Pulse Detector Copyright © 1973–2010, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): NA555 NE555 SA555 SE555 Voltage − 2 V/div Time − 0.1 ms/div Capacitor Voltage Output Voltage ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏInput Voltage VCC = 5 V RA = 1250 W C = 0.02 mF See Figure 9 NA555, NE555, SA555, SE555 SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010 www.ti.com Frequency Divider By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency divider. Figure 17 shows a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle. Figure 17. Divide-by-Three Circuit Waveforms 12 Submit Documentation Feedback Copyright © 1973–2010, Texas Instruments Incorporated Product Folder Link(s): NA555 NE555 SA555 SE555 THRES GND C RL RA VCC (5 V to 15 V) Output DISCH OUT RESET VCC TRIG CONT Modulation Input (see Note A) Clock Input NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. 4 8 3 7 6 2 5 Pin numbers shown are for the D, JG, P, PS, and PW packages. 1 Voltage − 2 V/div Time − 0.5 ms/div ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ Capacitor VoltageÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ Output Voltage ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ Clock Input Voltage ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ RA = 3 kW C = 0.02 mF RL = 1 kW See Figure 18 ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ Modulation Input Voltage NA555, NE555, SA555, SE555 www.ti.com SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010 Pulse-Width Modulation The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is accomplished by applying an external voltage (or current) to CONT. Figure 18 shows a circuit for pulse-width modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the threshold voltage. Figure 19 shows the resulting output pulse-width modulation. While a sine-wave modulation signal is shown, any wave shape could be used. Figure 18. Circuit for Pulse-Width Modulation Figure 19. Pulse-Width-Modulation Waveforms Copyright © 1973–2010, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link(s): NA555 NE555 SA555 SE555 Voltage − 2 V/div ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RA = 3 kW RB = 500 W RL = 1 kW See Figure 20 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Capacitor Voltage ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Voltage ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Modulation Input Voltage Time − 0.1 ms/div RB Modulation Input (see Note A) CONT TRIG RESET VCC OUT DISCH VCC (5 V to 15 V) RL RA C GND THRES NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. Pin numbers shown are for the D, JG, P, PS, and PW packages. 4 8 3 7 6 2 5 Output NA555, NE555, SA555, SE555 SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010 www.ti.com Pulse-Position Modulation As shown in Figure 20, any of these timers can be used as a pulse-position modulator. This application modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. Figure 21 shows a triangular-wave modulation signal for such a circuit; however, any wave shape could be used. Figure 20. Circuit for Pulse-Position Modulation Figure 21. Pulse-Position-Modulation Waveforms 14 Submit Documentation Feedback Copyright © 1973–2010, Texas Instruments Incorporated Product Folder Link(s): NA555 NE555 SA555 SE555 S VCC RESET VCC OUT DISCH GND CONT TRIG 4 8 3 7 6 1 5 2 THRES RC CC 0.01 CC = 14.7 mF RC = 100 kW Output C RESET VCC OUT DISCH GND CONT TRIG 4 8 3 7 6 1 5 2 THRES RB 33 kW 0.001 0.01 mF CB = 4.7 mF RB = 100 kW RA = 100 kW Output A Output B CA = 10 mF mF 0.01 mF 0.001 RA 33 kW THRES 2 5 1 6 7 3 4 8 TRIG CONT GND DISCH OUT RESET VCC mF mF CA CB Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: S closes momentarily at t = 0. Voltage − 5 V/div t − Time − 1 s/div ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ See Figure 22 ÏÏÏÏÏÏÏÏÏÏÏÏ Output A ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ Output B ÏÏÏÏÏÏÏÏÏÏÏÏ Output C ÏÏÏÏÏÏÏÏÏÏÏÏ t = 0 ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ twC = 1.1 RCCC ÏÏÏÏÏÏ twC ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ twB = 1.1 RBCB ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ twA = 1.1 RACA ÏÏÏÏÏÏÏÏÏÏÏÏ twA ÏÏÏÏÏÏÏÏÏÏÏÏ twB NA555, NE555, SA555, SE555 www.ti.com SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010 Sequential Timer Many applications, such as computers, require signals for initializing conditions during start-up. Other applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be connected to provide such sequential control. The timers can be used in various combinations of astable or monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 22 shows a sequencer circuit with possible applications in many systems, and Figure 23 shows the output waveforms. Figure 22. Sequential Timer Circuit Figure 23. Sequential Timer Waveforms Copyright © 1973–2010, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Link(s): NA555 NE555 SA555 SE555 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples JM38510/10901BPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510 /10901BPA M38510/10901BPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510 /10901BPA NA555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555 NA555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555 NA555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555 NA555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555 NA555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 105 NA555P NA555PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 105 NA555P NE555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555DE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 NE555 NE555DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555DRG3 PREVIEW SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 NE555 NE555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU | CU SN N / A for Pkg Type 0 to 70 NE555P NE555PE3 PREVIEW PDIP P 8 50 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 NE555P PACKAGE OPTION ADDENDUM www.ti.com 24-May-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples NE555PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 NE555P NE555PSLE OBSOLETE SO PS 8 TBD Call TI Call TI 0 to 70 NE555PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWE4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWRE4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555Y OBSOLETE 0 TBD Call TI Call TI 0 to 70 SA555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555DE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 SA555 SA555DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA555P PACKAGE OPTION ADDENDUM www.ti.com 24-May-2014 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SA555PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA555P SE555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555FKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SE555FKB SE555JG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 SE555JG SE555JGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 SE555JGB SE555N OBSOLETE PDIP N 8 TBD Call TI Call TI -55 to 125 SE555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 SE555P (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. PACKAGE OPTION ADDENDUM www.ti.com 24-May-2014 Addendum-Page 4 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF SE555, SE555M : • Catalog: SE555 • Military: SE555M • Space: SE555-SP, SE555-SP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant NA555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NA555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE555DR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 NE555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 NE555PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 NE555PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 SA555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SA555DR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 SA555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SE555DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SE555DRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) NA555DR SOIC D 8 2500 340.5 338.1 20.6 NA555DR SOIC D 8 2500 367.0 367.0 35.0 NE555DR SOIC D 8 2500 364.0 364.0 27.0 NE555DR SOIC D 8 2500 340.5 338.1 20.6 NE555DRG4 SOIC D 8 2500 340.5 338.1 20.6 NE555DRG4 SOIC D 8 2500 367.0 367.0 35.0 NE555PSR SO PS 8 2000 367.0 367.0 38.0 NE555PWR TSSOP PW 8 2000 367.0 367.0 35.0 SA555DR SOIC D 8 2500 340.5 338.1 20.6 SA555DR SOIC D 8 2500 364.0 364.0 27.0 SA555DRG4 SOIC D 8 2500 340.5 338.1 20.6 SE555DR SOIC D 8 2500 367.0 367.0 35.0 SE555DRG4 SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2013 Pack Materials-Page 2 MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) Seating Plane 4040107/C 08/96 5 4 0.065 (1,65) 0.045 (1,14) 8 1 0.020 (0,51) MIN 0.400 (10,16) 0.355 (9,00) 0.015 (0,38) 0.023 (0,58) 0.063 (1,60) 0.015 (0,38) 0.200 (5,08) MAX 0.130 (3,30) MIN 0.245 (6,22) 0.280 (7,11) 0.100 (2,54) 0°–15° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated CC1100 SWRS038D Page 1 of 92 CC1100 Low-Power Sub- 1 GHz RF Transceiver Applications • Ultra low-power wireless applications operating in the 315/433/868/915 MHz ISM/SRD bands • Wireless alarm and security systems • Industrial monitoring and control • Wireless sensor networks • AMR – Automatic Meter Reading • Home and building automation Product Description The CC1100 is a low-cost sub- 1 GHz transceiver designed for very low-power wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands at 315, 433, 868, and 915 MHz, but can easily be programmed for operation at other frequencies in the 300-348 MHz, 400-464 MHz and 800-928 MHz bands. The RF transceiver is integrated with a highly configurable baseband modem. The modem supports various modulation formats and has a configurable data up to 500 kBaud. CC1100 provides extensive hardware support for packet handling, data buffering, burst transmissions, clear channel assessment, link quality indication, and wake-on-radio. The main operating parameters and the 64- byte transmit/receive FIFOs of CC1100 can be controlled via an SPI interface. In a typical system, the CC1100 will be used together with a microcontroller and a few additional passive components. 6 7 8 9 10 20 19 18 17 16 1 2 3 4 5 15 14 13 12 11 CC1100 This product shall not be used in any of the following products or systems without prior express written permission from Texas Instruments: (i) implantable cardiac rhythm management systems, including without limitation pacemakers, defibrillators and cardiac resynchronization devices, (ii) external cardiac rhythm management systems that communicate directly with one or more implantable medical devices; or (iii) other devices used to monitor or treat cardiac function, including without limitation pressure sensors, biochemical sensors and neurostimulators. Please contact lpw-medical-approval@list.ti.com if your application might fall within the category described above. CC1100 SWRS038D Page 2 of 92 Key Features RF Performance • High sensitivity (–111 dBm at 1.2 kBaud, 868 MHz, 1% packet error rate) • Low current consumption (14.4 mA in RX, 1.2 kBaud, 868 MHz) • Programmable output power up to +10 dBm for all supported frequencies • Excellent receiver selectivity and blocking performance • Programmable data rate from 1.2 to 500 kBaud • Frequency bands: 300-348 MHz, 400-464 MHz and 800-928 MHz Analog Features • 2-FSK, GFSK, and MSK supported as well as OOK and flexible ASK shaping • Suitable for frequency hopping systems due to a fast settling frequency synthesizer: 90us settling time • Automatic Frequency Compensation (AFC) can be used to align the frequency synthesizer to the received centre frequency • Integrated analog temperature sensor Digital Features • Flexible support for packet oriented systems: On-chip support for sync word detection, address check, flexible packet length, and automatic CRC handling • Efficient SPI interface: All registers can be programmed with one “burst” transfer • Digital RSSI output • Programmable channel filter bandwidth • Programmable Carrier Sense (CS) indicator • Programmable Preamble Quality Indicator (PQI) for improved protection against false sync word detection in random noise • Support for automatic Clear Channel Assessment (CCA) before transmitting (for listen-before-talk systems) • Support for per-package Link Quality Indication (LQI) • Optional automatic whitening and dewhitening of data Low-Power Features • 400nA SLEEP mode current consumption • Fast startup time: 240us from sleep to RX or TX mode (measured on EM reference design [5] and [6]) • Wake-on-radio functionality for automatic low-power RX polling • Separate 64-byte RX and TX data FIFOs (enables burst mode data transmission) General • Few external components: Completely onchip frequency synthesizer, no external filters or RF switch needed • Green package: RoHS compliant and no antimony or bromine • Small size (QLP 4x4 mm package, 20 pins) • Suited for systems targeting compliance with EN 300 220 (Europe) and FCC CFR Part 15 (US). • Support for asynchronous and synchronous serial receive/transmit mode for backwards compatibility with existing radio communication protocols CC1100 SWRS038D Page 3 of 92 Abbreviations Abbreviations used in this data sheet are described below. ACP Adjacent Channel Power MSK Minimum Shift Keying ADC Analog to Digital Converter N/A Not Applicable AFC Automatic Frequency Compensation NRZ Non Return to Zero (Coding) AGC Automatic Gain Control OOK On-Off Keying AMR Automatic Meter Reading PA Power Amplifier ASK Amplitude Shift Keying PCB Printed Circuit Board BER Bit Error Rate PD Power Down BT Bandwidth-Time product PER Packet Error Rate CCA Clear Channel Assessment PLL Phase Locked Loop CFR Code of Federal Regulations POR Power-On Reset CRC Cyclic Redundancy Check PQI Preamble Quality Indicator CS Carrier Sense PQT Preamble Quality Threshold CW Continuous Wave (Unmodulated Carrier) PTAT Proportional To Absolute Temperature DC Direct Current QLP Quad Leadless Package DVGA Digital Variable Gain Amplifier QPSK Quadrature Phase Shift Keying ESR Equivalent Series Resistance RC Resistor-Capacitor FCC Federal Communications Commission RF Radio Frequency FEC Forward Error Correction RSSI Received Signal Strength Indicator FIFO First-In-First-Out RX Receive, Receive Mode FHSS Frequency Hopping Spread Spectrum SAW Surface Aqustic Wave 2-FSK Binary Frequency Shift Keying SMD Surface Mount Device GFSK Gaussian shaped Frequency Shift Keying SNR Signal to Noise Ratio IF Intermediate Frequency SPI Serial Peripheral Interface I/Q In-Phase/Quadrature SRD Short Range Devices ISM Industrial, Scientific, Medical TBD To Be Defined LC Inductor-Capacitor T/R Transmit/Receive LNA Low Noise Amplifier TX Transmit, Transmit Mode LO Local Oscillator UHF Ultra High frequency LSB Least Significant Bit VCO Voltage Controlled Oscillator LQI Link Quality Indicator WOR Wake on Radio, Low power polling MCU Microcontroller Unit XOSC Crystal Oscillator MSB Most Significant Bit XTAL Crystal CC1100 SWRS038D Page 4 of 92 Table Of Contents APPLICATIONS..................................................................................................................................................1 PRODUCT DESCRIPTION................................................................................................................................1 KEY FEATURES .................................................................................................................................................2 RF PERFORMANCE ..........................................................................................................................................2 ANALOG FEATURES ........................................................................................................................................2 DIGITAL FEATURES.........................................................................................................................................2 LOW-POWER FEATURES................................................................................................................................2 GENERAL ............................................................................................................................................................2 ABBREVIATIONS...............................................................................................................................................3 TABLE OF CONTENTS.....................................................................................................................................4 1 ABSOLUTE MAXIMUM RATINGS.....................................................................................................7 2 OPERATING CONDITIONS .................................................................................................................7 3 GENERAL CHARACTERISTICS.........................................................................................................7 4 ELECTRICAL SPECIFICATIONS.......................................................................................................8 4.1 CURRENT CONSUMPTION ............................................................................................................................8 4.2 RF RECEIVE SECTION..................................................................................................................................9 4.3 RF TRANSMIT SECTION .............................................................................................................................13 4.4 CRYSTAL OSCILLATOR..............................................................................................................................14 4.5 LOW POWER RC OSCILLATOR...................................................................................................................15 4.6 FREQUENCY SYNTHESIZER CHARACTERISTICS..........................................................................................15 4.7 ANALOG TEMPERATURE SENSOR ..............................................................................................................16 4.8 DC CHARACTERISTICS ..............................................................................................................................16 4.9 POWER-ON RESET .....................................................................................................................................16 5 PIN CONFIGURATION........................................................................................................................17 6 CIRCUIT DESCRIPTION ....................................................................................................................18 7 APPLICATION CIRCUIT....................................................................................................................19 8 CONFIGURATION OVERVIEW........................................................................................................22 9 CONFIGURATION SOFTWARE........................................................................................................24 10 4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE..................................................24 10.1 CHIP STATUS BYTE ...................................................................................................................................26 10.2 REGISTER ACCESS.....................................................................................................................................26 10.3 SPI READ ..................................................................................................................................................27 10.4 COMMAND STROBES .................................................................................................................................27 10.5 FIFO ACCESS ............................................................................................................................................27 10.6 PATABLE ACCESS...................................................................................................................................28 11 MICROCONTROLLER INTERFACE AND PIN CONFIGURATION ..........................................28 11.1 CONFIGURATION INTERFACE.....................................................................................................................28 11.2 GENERAL CONTROL AND STATUS PINS .....................................................................................................28 11.3 OPTIONAL RADIO CONTROL FEATURE ......................................................................................................29 12 DATA RATE PROGRAMMING..........................................................................................................29 13 RECEIVER CHANNEL FILTER BANDWIDTH..............................................................................30 14 DEMODULATOR, SYMBOL SYNCHRONIZER, AND DATA DECISION..................................30 14.1 FREQUENCY OFFSET COMPENSATION........................................................................................................30 14.2 BIT SYNCHRONIZATION.............................................................................................................................30 14.3 BYTE SYNCHRONIZATION..........................................................................................................................31 15 PACKET HANDLING HARDWARE SUPPORT..............................................................................31 15.1 DATA WHITENING.....................................................................................................................................31 15.2 PACKET FORMAT.......................................................................................................................................32 15.3 PACKET FILTERING IN RECEIVE MODE......................................................................................................34 15.4 PACKET HANDLING IN TRANSMIT MODE...................................................................................................34 15.5 PACKET HANDLING IN RECEIVE MODE .....................................................................................................35 CC1100 SWRS038D Page 5 of 92 15.6 PACKET HANDLING IN FIRMWARE.............................................................................................................35 16 MODULATION FORMATS.................................................................................................................36 16.1 FREQUENCY SHIFT KEYING.......................................................................................................................36 16.2 MINIMUM SHIFT KEYING...........................................................................................................................36 16.3 AMPLITUDE MODULATION ........................................................................................................................36 17 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION ............................37 17.1 SYNC WORD QUALIFIER............................................................................................................................37 17.2 PREAMBLE QUALITY THRESHOLD (PQT) ..................................................................................................37 17.3 RSSI..........................................................................................................................................................37 17.4 CARRIER SENSE (CS).................................................................................................................................39 17.5 CLEAR CHANNEL ASSESSMENT (CCA) .....................................................................................................40 17.6 LINK QUALITY INDICATOR (LQI)..............................................................................................................40 18 FORWARD ERROR CORRECTION WITH INTERLEAVING.....................................................40 18.1 FORWARD ERROR CORRECTION (FEC)......................................................................................................40 18.2 INTERLEAVING ..........................................................................................................................................41 19 RADIO CONTROL................................................................................................................................42 19.1 POWER-ON START-UP SEQUENCE.............................................................................................................42 19.2 CRYSTAL CONTROL...................................................................................................................................43 19.3 VOLTAGE REGULATOR CONTROL..............................................................................................................43 19.4 ACTIVE MODES .........................................................................................................................................44 19.5 WAKE ON RADIO (WOR)..........................................................................................................................44 19.6 TIMING ......................................................................................................................................................45 19.7 RX TERMINATION TIMER ..........................................................................................................................46 20 DATA FIFO ............................................................................................................................................46 21 FREQUENCY PROGRAMMING........................................................................................................48 22 VCO.........................................................................................................................................................48 22.1 VCO AND PLL SELF-CALIBRATION ..........................................................................................................48 23 VOLTAGE REGULATORS .................................................................................................................49 24 OUTPUT POWER PROGRAMMING ................................................................................................49 25 SHAPING AND PA RAMPING............................................................................................................50 26 SELECTIVITY.......................................................................................................................................52 27 CRYSTAL OSCILLATOR....................................................................................................................53 27.1 REFERENCE SIGNAL ..................................................................................................................................54 28 EXTERNAL RF MATCH .....................................................................................................................54 29 PCB LAYOUT RECOMMENDATIONS.............................................................................................54 30 GENERAL PURPOSE / TEST OUTPUT CONTROL PINS.............................................................55 31 ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION..............................................57 31.1 ASYNCHRONOUS OPERATION....................................................................................................................57 31.2 SYNCHRONOUS SERIAL OPERATION ..........................................................................................................57 32 SYSTEM CONSIDERATIONS AND GUIDELINES.........................................................................57 32.1 SRD REGULATIONS...................................................................................................................................57 32.2 FREQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS............................................................................58 32.3 WIDEBAND MODULATION NOT USING SPREAD SPECTRUM .......................................................................58 32.4 DATA BURST TRANSMISSIONS...................................................................................................................58 32.5 CONTINUOUS TRANSMISSIONS ..................................................................................................................59 32.6 CRYSTAL DRIFT COMPENSATION ..............................................................................................................59 32.7 SPECTRUM EFFICIENT MODULATION.........................................................................................................59 32.8 LOW COST SYSTEMS .................................................................................................................................59 32.9 BATTERY OPERATED SYSTEMS .................................................................................................................59 32.10 INCREASING OUTPUT POWER ................................................................................................................59 33 CONFIGURATION REGISTERS........................................................................................................60 33.1 CONFIGURATION REGISTER DETAILS – REGISTERS WITH PRESERVED VALUES IN SLEEP STATE...............64 33.2 CONFIGURATION REGISTER DETAILS – REGISTERS THAT LOSE PROGRAMMING IN SLEEP STATE............84 33.3 STATUS REGISTER DETAILS.......................................................................................................................85 CC1100 SWRS038D Page 6 of 92 34 PACKAGE DESCRIPTION (QLP 20).................................................................................................88 34.1 RECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 20) ...........................................................................88 34.2 SOLDERING INFORMATION ........................................................................................................................88 35 ORDERING INFORMATION..............................................................................................................89 36 REFERENCES .......................................................................................................................................90 37 GENERAL INFORMATION................................................................................................................91 37.1 DOCUMENT HISTORY ................................................................................................................................91 CC1100 SWRS038D Page 7 of 92 1 Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. Parameter Min Max Units Condition Supply voltage –0.3 3.9 V All supply pins must have the same voltage Voltage on any digital pin –0.3 VDD+0.3 max 3.9 V Voltage on the pins RF_P, RF_N, and DCOUPL –0.3 2.0 V Voltage ramp-up rate 120 kV/μs Input RF level +10 dBm Storage temperature range –50 150 °C Solder reflow temperature 260 °C According to IPC/JEDEC J-STD-020C ESD <500 V According to JEDEC STD 22, method A114, Human Body Model Table 1: Absolute Maximum Ratings 2 Operating Conditions The operating conditions for CC1100 are listed Table 2 in below. Parameter Min Max Unit Condition Operating temperature -40 85 °C Operating supply voltage 1.8 3.6 V All supply pins must have the same voltage Table 2: Operating Conditions 3 General Characteristics Parameter Min Typ Max Unit Condition/Note Frequency range 300 348 MHz 400 464 MHz 800 928 MHz Data rate 1.2 1.2 26 500 250 500 kBaud kBaud kBaud 2-FSK GFSK, OOK, and ASK (Shaped) MSK (also known as differential offset QPSK) Optional Manchester encoding (the data rate in kbps will be half the baud rate) Table 3: General Characteristics CC1100 SWRS038D Page 8 of 92 4 Electrical Specifications 4.1 Current Consumption Tc = 25°C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the CC1100EM reference designs ([5] and [6]). Reduced current settings (MDMCFG2.DEM_DCFILT_OFF=1) gives a slightly lower current consumption at the cost of a reduction in sensitivity. See Table 5 for additional details on current consumption and sensitivity. Parameter Min Typ Max Unit Condition 400 nA Voltage regulator to digital part off, register values retained (SLEEP state). All GDO pins programmed to 0x2F (HW to 0) 900 nA Voltage regulator to digital part off, register values retained, lowpower RC oscillator running (SLEEP state with WOR enabled 95 μA Voltage regulator to digital part off, register values retained, XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set) Current consumption in power down modes 160 μA Voltage regulator to digital part on, all other modules in power down (XOFF state) 9.8 μA Automatic RX polling once each second, using low-power RC oscillator, with 460 kHz filter bandwidth and 250 kBaud data rate, PLL calibration every 4th wakeup. Average current with signal in channel below carrier sense level (MCSM2.RX_TIME_RSSI=1). 34.2 μA Same as above, but with signal in channel above carrier sense level, 1.95 ms RX timeout, and no preamble/sync word found. 1.5 μA Automatic RX polling every 15th second, using low-power RC oscillator, with 460kHz filter bandwidth and 250 kBaud data rate, PLL calibration every 4th wakeup. Average current with signal in channel below carrier sense level (MCSM2.RX_TIME_RSSI=1). 39.3 μA Same as above, but with signal in channel above carrier sense level, 29.3 ms RX timeout, and no preamble/sync word found. 1.6 mA Only voltage regulator to digital part and crystal oscillator running (IDLE state) Current consumption 8.2 mA Only the frequency synthesizer is running (FSTXON state). This currents consumption is also representative for the other intermediate states when going from IDLE to RX or TX, including the calibration state. 15.1 mA Receive mode, 1.2 kBaud, reduced current, input at sensitivity limit 13.9 mA Receive mode, 1.2 kBaud, reduced current, input well above sensitivity limit 14.9 mA Receive mode, 38.4 kBaud, reduced current, input at sensitivity limit 14.1 mA Receive mode,38.4 kBaud, reduced current, input well above sensitivity limit 15.9 mA Receive mode, 250 kBaud, reduced current, input at sensitivity limit 14.5 mA Receive mode, 250 kBaud, reduced current, input well above sensitivity limit 27.0 mA Transmit mode, +10 dBm output power 14.8 mA Transmit mode, 0 dBm output power Current consumption, 315MHz 12.3 mA Transmit mode, –6 dBm output power CC1100 SWRS038D Page 9 of 92 Table 4: Electrical Specifications 4.2 RF Receive Section Tc = 25°C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the CC1100EM reference designs ([5] and [6]). Parameter Min Typ Max Unit Condition/Note Digital channel filter bandwidth 58 812 kHz User programmable. The bandwidth limits are proportional to crystal frequency (given values assume a 26.0 MHz crystal). 315 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) Receiver sensitivity -111 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.1 mA to 15.1 mA at sensitivity limit. The sensitivity is typically reduced to -109 dBm 315 MHz, 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 250 kBaud) (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth) -88 dBm Parameter Min Typ Max Unit Condition 15.5 mA Receive mode, 1.2 kBaud , reduced current, input at sensitivity limit 14.5 mA Receive mode, 1.2 kBaud , reduced current, input well above sensitivity limit 15.4 mA Receive mode, 38.4 kBaud , reduced current, input at sensitivity limit 14.4 mA Receive mode, 38.4 kBaud , reduced current, input well above sensitivity limit 16.5 mA Receive mode, 250 kBaud , reduced current, input at sensitivity limit 15.2 mA Receive mode, 250 kBaud , reduced current, input well above sensitivity limit 28.9 mA Transmit mode, +10 dBm output power 15.5 mA Transmit mode, 0 dBm output power Current consumption, 433MHz 13.1 mA Transmit mode, –6 dBm output power 15.4 mA Receive mode, 1.2 kBaud , reduced current, input at sensitivity limit 14.4 mA Receive mode, 1.2 kBaud , reduced current, input well above sensitivity limit 15.2 mA Receive mode, 38.4 kBaud , reduced current, input at sensitivity limit 14.4 mA Receive mode,38.4 kBaud , reduced current, input well above sensitivity limit 16.4 mA Receive mode, 250 kBaud , reduced current, input at sensitivity limit 15.1 mA Receive mode, 250 kBaud , reduced current, input well above sensitivity limit 31.1 mA Transmit mode, +10 dBm output power 16.9 mA Transmit mode, 0 dBm output power Current consumption, 868/915MHz 13.5 mA Transmit mode, –6 dBm output power CC1100 SWRS038D Page 10 of 92 Parameter Min Typ Max Unit Condition/Note 433 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth Receiver sensitivity –110 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.4 mA to 15.5 mA at sensitivity limit. The sensitivity is typically reduced to -108 dBm 433 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) Receiver sensitivity –103 dBm 433 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth) Receiver sensitivity –94 dBm 433 MHz, 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 250 kBaud) (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth) Receiver sensitivity –88 dBm 868 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) Receiver sensitivity –111 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.7 mA to 15.4 mA at sensitivity limit. The sensitivity is typically reduced to -109 dBm Saturation –15 dBm Adjacent channel rejection 33 dB Desired channel 3 dB above the sensitivity limit. 100 kHz channel spacing Alternate channel rejection 33 dB Desired channel 3 dB above the sensitivity limit. 100 kHz channel spacing See Figure 25 for plot of selectivity versus frequency offset Image channel rejection, 868MHz 30 dB IF frequency 152 kHz Desired channel 3 dB above the sensitivity limit. 868 MHz, 38.4 kBaud data rate (2-FSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) Receiver sensitivity –103 dBm Saturation –16 dBm Adjacent channel rejection 20 dB Desired channel 3 dB above the sensitivity limit. 200 kHz channel spacing Alternate channel rejection 28 dB Desired channel 3 dB above the sensitivity limit. 200 kHz channel spacing See Figure 26 for plot of selectivity versus frequency offset Image channel rejection, 868MHz 23 dB IF frequency 152 kHz Desired channel 3 dB above the sensitivity limit. CC1100 SWRS038D Page 11 of 92 Parameter Min Typ Max Unit Condition/Note 868 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth) Receiver sensitivity –93 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 18.8 mA to 16.4 mA at sensitivity limit. The sensitivity is typically reduced to -91 dBm Saturation –16 dBm Adjacent channel rejection 24 dB Desired channel 3 dB above the sensitivity limit. 750 kHz channel spacing Alternate channel rejection 37 dB Desired channel 3 dB above the sensitivity limit. 750 kHz channel spacing See Figure 27 for plot of selectivity versus frequency offset Image channel rejection, 868MHz 14 dB IF frequency 254 kHz Desired channel 3 dB above the sensitivity limit. 868 MHz, 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 250 kBaud ) (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth) Receiver sensitivity –88 dBm 868 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (OOK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth) Receiver sensitivity -86 dBm 915 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 5.2kHz deviation, 1% packet error rate, 20 bytes packet length, 58 kHz digital channel filter bandwidth) Receiver sensitivity –111 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.7 mA to 15.4 mA at sensitivity limit. The sensitivity is typically reduced to -109 dBm 915 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) Receiver sensitivity –104 dBm 915 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth) Receiver sensitivity –93 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 18.8 mA to 16.4 mA at sensitivity limit. The sensitivity is typically reduced to -92 dBm 915 MHz, 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 250 kBaud ) (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth) Receiver sensitivity –87 dBm CC1100 SWRS038D Page 12 of 92 Parameter Min Typ Max Unit Condition/Note Blocking Blocking at ±2 MHz offset, 1.2 kBaud, 868 MHz -53 dBm Desired channel 3dB above the sensitivity limit. Compliant with ETSI EN 300 220 class 2 receiver requirement. Blocking at ±2 MHz offset, 500 kBaud, 868 MHz -51 dBm Desired channel 3dB above the sensitivity limit. Compliant with ETSI EN 300 220 class 2 receiver requirement. Blocking at ±10 MHz offset, 1.2 kBaud, 868 MHz -43 dBm Desired channel 3dB above the sensitivity limit. Compliant with ETSI EN 300 220 class 2 receiver requirement. Blocking at ±10 MHz offset, 500 kBaud, 868 MHz -43 dBm Desired channel 3dB above the sensitivity limit. Compliant with ETSI EN 300 220 class 2 receiver requirement. General Spurious emissions -68 -66 –57 –47 dBm dBm 25 MHz – 1 GHz (Maximum figure is the ETSI EN 300 220 limit) Above 1 GHz (Maximum figure is the ETSI EN 300 220 limit) RX latency 9 bit Serial operation. Time from start of reception until data is available on the receiver data output pin is equal to 9 bit. Table 5: RF Receive Section CC1100 SWRS038D Page 13 of 92 4.3 RF Transmit Section Tc = 25°C, VDD = 3.0V, +10dBm if nothing else stated. All measurement results are obtained using the CC1100EM reference designs ([5] and [6]). Parameter Min Typ Max Unit Condition/Note Differential load impedance 315 MHz 433 MHz 868/915 MHz 122 + j31 116 + j41 86.5 + j43 Ω Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna. Follow the CC1100EM reference design ([5] and [6]) available from theTI website. Output power, highest setting +10 dBm Output power is programmable, and full range is available in all frequency bands (Output power may be restricted by regulatory limits. See also Application Note AN039 [3]. Delivered to a 50Ω single-ended load via CC1100EM reference design ([5] and [6]) RF matching network. Output power, lowest setting -30 dBm Output power is programmable, and full range is available in all frequency bands. Delivered to a 50Ω single-ended load via CC1100EM reference design([5] and [6]) RF matching network. Harmonics, radiated 2nd Harm, 433 MHz 3rd Harm, 433 MHz 2nd Harm, 868 MHz 3rd Harm, 868 MHz -50 -40 -34 -45 dBm Measured on CC1100EM reference designs([5] and [6]) with CW, 10 dBm output power The antennas used during the radiated measurements (SMAFF- 433 from R.W.Badland and Nearson S331 868/915) plays a part in attenuating the harmonics Harmonics, conducted 315 MHz 433 MHz 868 MHz 915 MHz < -33 < -38 < -51 < -34 < -32 < -30 dBm Measured with 10 dBm CW, TX frequency at 315.00 MHz, 433.00 MHz, 868.00 MHz, or 915.00 MHz Frequencies below 960 MHz Frequencies above 960 MHz Frequencies below 1 GHz Frequencies above 1 GHz CC1100 SWRS038D Page 14 of 92 Spurious emissions, conducted Harmonics not included 315 MHz 433 MHz 868 MHz 915 MHz < -58 < -53 < -50 < -54 < -56 < -50 < -51 < -53 < -51 < -51 dBm Measured with 10 dBm CW, TX frequency at 315.00 MHz, 433.00 MHz, 868.00 MHz or 915.00 MHz Frequencies below 960 MHz Frequencies above 960 MHz Frequencies below 1 GHz Frequencies above 1 GHz Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz Frequencies below 1 GHz Frequencies above 1 GHz Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz. The peak conducted spurious emission is -53dBm @ 699 MHz, which is in an EN300220 restricted band limited to -54dBm. All radiated spurious emissions are within the limits of ETSI. Frequencies below 960 MHz Frequencies above 960 MHz General TX latency 8 bit Serial operation. Time from sampling the data on the transmitter data input DIO pin until it is observed on the RF output ports. Table 6: RF Transmit Section 4.4 Crystal Oscillator Tc = 25°C @ VDD = 3.0 V if nothing else is stated. Parameter Min Typ Max Unit Condition/Note Crystal frequency 26 26 27 MHz Tolerance ±40 ppm This is the total tolerance including a) initial tolerance, b) crystal loading, c) aging, and d) temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth. ESR 100 Ω Start-up time 150 μs Measured on the CC1100EM reference designs ([5] and [6]) using crystal AT-41CD2 from NDK. This parameter is to a large degree crystal dependent. Table 7: Crystal Oscillator Parameters CC1100 SWRS038D Page 15 of 92 4.5 Low Power RC Oscillator Tc = 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1100EM reference designs ([5] and [6]). Parameter Min Typ Max Unit Condition/Note Calibrated frequency 34.7 34.7 36 kHz Calibrated RC Oscillator frequency is XTAL frequency divided by 750 Frequency accuracy after calibration ±1 % Temperature coefficient +0.5 % / °C Frequency drift when temperature changes after calibration Supply voltage coefficient +3 % / V Frequency drift when supply voltage changes after calibration Initial calibration time 2 ms When the RC Oscillator is enabled, calibration is continuously done in the background as long as the crystal oscillator is running. Table 8: RC Oscillator Parameters 4.6 Frequency Synthesizer Characteristics Tc = 25°C @ VDD = 3.0 V if nothing else is stated. All measurement results are obtained using the CC1100EM reference designs ([5] and [6]). Min figures are given using a 27 MHz crystal. Typ and max are given using a 26 MHz crystal. Parameter Min Typ Max Unit Condition/Note Programmed frequency resolution 397 FXOSC/ 216 412 Hz 26-27 MHz crystal. The resolution (in Hz) is equal for all frequency bands. Synthesizer frequency tolerance ±40 ppm Given by crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth / spacing. RF carrier phase noise –89 dBc/Hz @ 50 kHz offset from carrier RF carrier phase noise –89 dBc/Hz @ 100 kHz offset from carrier RF carrier phase noise –90 dBc/Hz @ 200 kHz offset from carrier RF carrier phase noise –98 dBc/Hz @ 500 kHz offset from carrier RF carrier phase noise –107 dBc/Hz @ 1 MHz offset from carrier RF carrier phase noise –113 dBc/Hz @ 2 MHz offset from carrier RF carrier phase noise –119 dBc/Hz @ 5 MHz offset from carrier RF carrier phase noise –129 dBc/Hz @ 10 MHz offset from carrier PLL turn-on / hop time 85.1 88.4 88.4 μs Time from leaving the IDLE state until arriving in the RX, FSTXON or TX state, when not performing calibration. Crystal oscillator running. PLL RX/TX settling time 9.3 9.6 9.6 μs Settling time for the 1·IF frequency step from RX to TX PLL TX/RX settling time 20.7 21.5 21.5 μs Settling time for the 1·IF frequency step from TX to RX PLL calibration time 694 721 721 μs Calibration can be initiated manually or automatically before entering or after leaving RX/TX. Table 9: Frequency Synthesizer Parameters CC1100 SWRS038D Page 16 of 92 4.7 Analog Temperature Sensor The characteristics of the analog temperature sensor at 3.0 V supply voltage are listed in Table 10 below. Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state. Parameter Min Typ Max Unit Condition/Note Output voltage at –40°C 0.651 V Output voltage at 0°C 0.747 V Output voltage at +40°C 0.847 V Output voltage at +80°C 0.945 V Temperature coefficient 2.45 mV/°C Fitted from –20 °C to +80 °C Error in calculated temperature, calibrated -2 * 0 2 * °C From –20 °C to +80 °C when using 2.45 mV / °C, after 1-point calibration at room temperature * The indicated minimum and maximum error with 1- point calibration is based on simulated values for typical process parameters Current consumption increase when enabled 0.3 mA Table 10: Analog Temperature Sensor Parameters 4.8 DC Characteristics Tc = 25°C if nothing else stated. Digital Inputs/Outputs Min Max Unit Condition Logic "0" input voltage 0 0.7 V Logic "1" input voltage VDD-0.7 VDD V Logic "0" output voltage 0 0.5 V For up to 4 mA output current Logic "1" output voltage VDD-0.3 VDD V For up to 4 mA output current Logic "0" input current N/A –50 nA Input equals 0V Logic "1" input current N/A 50 nA Input equals VDD Table 11: DC Characteristics 4.9 Power-On Reset When the power supply complies with the requirements in Table 12 below, proper Power-On-Reset functionality is guaranteed. Otherwise, the chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface. See Section 19.1 on page 42 for further details. Parameter Min Typ Max Unit Condition/Note Power-up ramp-up time. 5 ms From 0V until reaching 1.8V Power off time 1 ms Minimum time between power-on and power-off Table 12: Power-On Reset Requirements CC1100 SWRS038D Page 17 of 92 5 Pin Configuration 1 20 19 18 17 16 15 14 13 12 11 6 7 8 9 10 5 4 3 2 GND Exposed die attach pad SCLK SO (GDO1) GDO2 DVDD DCOUPL GDO0 (ATEST) XOSC_Q1 AVDD XOSC_Q2 AVDD RF_P RF_N GND AVDD RBIAS DGUARD GND SI CSn AVDD Figure 1: Pinout Top View Note: The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip. Pin # Pin Name Pin type Description 1 SCLK Digital Input Serial configuration interface, clock input 2 SO (GDO1) Digital Output Serial configuration interface, data output. Optional general output pin when CSn is high 3 GDO2 Digital Output Digital output pin for general use: • Test signals • FIFO status signals • Clear Channel Indicator • Clock output, down-divided from XOSC • Serial output RX data 4 DVDD Power (Digital) 1.8 - 3.6 V digital power supply for digital I/O’s and for the digital core voltage regulator 5 DCOUPL Power (Digital) 1.6 - 2.0 V digital power supply output for decoupling. NOTE: This pin is intended for use with the CC1100 only. It can not be used to provide supply voltage to other devices. 6 GDO0 (ATEST) Digital I/O Digital output pin for general use: • Test signals • FIFO status signals • Clear Channel Indicator • Clock output, down-divided from XOSC • Serial output RX data • Serial input TX data Also used as analog test I/O for prototype/production testing 7 CSn Digital Input Serial configuration interface, chip select 8 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input 9 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection 10 XOSC_Q2 Analog I/O Crystal oscillator pin 2 CC1100 SWRS038D Page 18 of 92 Pin # Pin Name Pin type Description 11 AVDD Power (Analog) 1.8 -3.6 V analog power supply connection 12 RF_P RF I/O Positive RF input signal to LNA in receive mode Positive RF output signal from PA in transmit mode 13 RF_N RF I/O Negative RF input signal to LNA in receive mode Negative RF output signal from PA in transmit mode 14 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection 15 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection 16 GND Ground (Analog) Analog ground connection 17 RBIAS Analog I/O External bias resistor for reference current 18 DGUARD Power (Digital) Power supply connection for digital noise isolation 19 GND Ground (Digital) Ground connection for digital noise isolation 20 SI Digital Input Serial configuration interface, data input Table 13: Pinout Overview 6 Circuit Description BIAS PA RBIAS XOSC_Q1 XOSC_Q2 CSn SI SO (GDO1) XOSC SCLK LNA 0 90 FREQ SYNTH ADC ADC DEMODULATOR FEC / INTERLEAVER PACKET HANDLER RXFIFO MODULATOR TXFIFO DIGITAL INTERFACE TO MCU RADIO CONTROL RF_P RF_N GDO2 GDO0 (ATEST) RC OSC Figure 2: CC1100 Simplified Block Diagram A simplified block diagram of CC1100 is shown in Figure 2. CC1100 features a low-IF receiver. The received RF signal is amplified by the lownoise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signals are digitised by the ADCs. Automatic gain control (AGC), fine channel filtering and demodulation bit/packet synchronization are performed digitally. The transmitter part of CC1100 is based on direct synthesis of the RF frequency. The frequency synthesizer includes a completely on-chip LC VCO and a 90 degree phase shifter for generating the I and Q LO signals to the down-conversion mixers in receive mode. A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the ADC and the digital part. A 4-wire SPI serial interface is used for configuration and data buffer access. The digital baseband includes support for channel configuration, packet handling, and data buffering. CC1100 SWRS038D Page 19 of 92 7 Application Circuit Only a few external components are required for using the CC1100. The recommended application circuits are shown in Figure 3 and Figure 4. The external components are described in Table 14, and typical values are given in Table 15. Bias Resistor The bias resistor R171 is used to set an accurate bias current. Balun and RF Matching The components between the RF_N/RF_P pins and the point where the two signals are joined together (C131, C121, L121 and L131 for the 315/433 MHz reference design [5]. L121, L131, C121, L122, C131, C122 and L132 for the 868/915 MHz reference design [6]) form a balun that converts the differential RF signal on CC1100 to a single-ended RF signal. C124 is needed for DC blocking. Together with an appropriate LC network, the balun components also transform the impedance to match a 50 Ω antenna (or cable). Suggested values for 315 MHz, 433 MHz, and 868/915 MHz are listed in Table 15. The balun and LC filter component values and their placement are important to keep the performance optimized. It is highly recommended to follow the CC1100EM reference design [5] and [6]. Crystal The crystal oscillator uses an external crystal with two loading capacitors (C81 and C101). See Section 27 on page 53 for details. Additional Filtering Additional external components (e.g. an RF SAW filter) may be used in order to improve the performance in specific applications. Power Supply Decoupling The power supply must be properly decoupled close to the supply pins. Note that decoupling capacitors are not shown in the application circuit. The placement and the size of the decoupling capacitors are very important to achieve the optimum performance. The CC1100EM reference design ([5] and [6]) should be followed closely. Component Description C51 Decoupling capacitor for on-chip voltage regulator to digital part C81/C101 Crystal loading capacitors, see Section 27 on page 53 for details C121/C131 RF balun/matching capacitors C122 RF LC filter/matching filter capacitor (315 and 433 MHz). RF balun/matching capacitor (868/915 MHz). C123 RF LC filter/matching capacitor C124 RF balun DC blocking capacitor C125 RF LC filter DC blocking capacitor (only needed if there is a DC path in the antenna) L121/L131 RF balun/matching inductors (inexpensive multi-layer type) L122 RF LC filter/matching filter inductor (315 and 433 MHz). RF balun/matching inductor (868/915 MHz). (inexpensive multi-layer type) L123 RF LC filter/matching filter inductor (inexpensive multi-layer type) L124 RF LC filter/matching filter inductor (inexpensive multi-layer type) L132 RF balun/matching inductor. (inexpensive multi-layer type) R171 Resistor for internal bias current reference. XTAL 26MHz - 27MHz crystal, see Section 27 on page 53 for details. Table 14: Overview of External Components (excluding supply decoupling capacitors) CC1100 SWRS038D Page 20 of 92 Antenna (50 Ohm) Digital Inteface 1.8V-3.6V power supply 6 GDO0 7 CSn 8 XOSC_Q1 9 AVDD 10 XOSC_Q2 SI 20 GND 19 DGUARD 18 RBIAS 17 GND 16 1 SCLK 2 SO (GDO1) 3 GDO2 4 DVDD 5 DCOUPL AVDD 15 AVDD 14 RF_N 13 RF_P 12 AVDD 11 XTAL L122 L123 C122 C123 C125 R171 C81 C101 C51 CSn GDO0 (optional) GDO2 (optional) SO (GDO1) SCLK SI CC1100 DIE ATTACH PAD: C131 C121 L121 L131 C124 Figure 3: Typical Application and Evaluation Circuit 315/433 MHz (excluding supply decoupling capacitors) Antenna (50 Ohm) Digital Inteface 1.8V-3.6V power supply 6 GDO0 7 CSn 8 XOSC_Q1 9 AVDD 10 XOSC_Q2 SI 20 GND 19 DGUARD 18 RBIAS 17 GND 16 1 SCLK 2 SO (GDO1) 3 GDO2 4 DVDD 5 DCOUPL AVDD 15 AVDD 14 RF_N 13 RF_P 12 AVDD 11 XTAL C121 C122 L122 L132 C131 L121 L123 C125 R171 C81 C101 C51 CSn GDO0 (optional) GDO2 (optional) SO (GDO1) SCLK SI DIE ATTACH PAD: L131 C124 C123 L124 Figure 4: Typical Application and Evaluation Circuit 868/915 MHz (excluding supply decoupling capacitors) CC1100 SWRS038D Page 21 of 92 Component Value at 315MHz Value at 433MHz Value at 868/915MHz Manufacturer C51 100 nF ± 10%, 0402 X5R Murata GRM1555C series C81 27 pF ± 5%, 0402 NP0 Murata GRM1555C series C101 27 pF ± 5%, 0402 NP0 Murata GRM1555C series C121 6.8 pF ± 0.5 pF, 0402 NP0 3.9 pF ± 0.25 pF, 0402 NP0 1.0 pF ± 0.25 pF, 0402 NP0 Murata GRM1555C series C122 12 pF ± 5%, 0402 NP0 8.2 pF ± 0.5 pF, 0402 NP0 1.5 pF ± 0.25 pF, 0402 NP0 Murata GRM1555C series C123 6.8 pF ± 0.5 pF, 0402 NP0 5.6 pF ± 0.5 pF, 0402 NP0 3.3 pF ± 0.25 pF, 0402 NP0 Murata GRM1555C series C124 220 pF ± 5%, 0402 NP0 220 pF ± 5%, 0402 NP0 100 pF ± 5%, 0402 NP0 Murata GRM1555C series C125 220 pF ± 5%, 0402 NP0 220 pF ± 5%, 0402 NP0 100 pF ± 5%, 0402 NP0 Murata GRM1555C series C131 6.8 pF ± 0.5 pF, 0402 NP0 3.9 pF ± 0.25 pF, 0402 NP0 1.5 pF ± 0.25 pF, 0402 NP0 Murata GRM1555C series L121 33 nH ± 5%, 0402 monolithic 27 nH ± 5%, 0402 monolithic 12 nH ± 5%, 0402 monolithic Murata LQG15HS series L122 18 nH ± 5%, 0402 monolithic 22 nH ± 5%, 0402 monolithic 18 nH ± 5%, 0402 monolithic Murata LQG15HS series L123 33 nH ± 5%, 0402 monolithic 27 nH ± 5%, 0402 monolithic 12 nH ± 5%, 0402 monolithic Murata LQG15HS series L124 12 nH ± 5%, 0402 monolithic Murata LQG15HS series L131 33 nH ± 5%, 0402 monolithic 27 nH ± 5%, 0402 monolithic 12 nH ± 5%, 0402 monolithic Murata LQG15HS series L132 18 nH ± 5%, 0402 monolithic Murata LQG15HS series R171 56 kΩ ± 1%, 0402 Koa RK73 series XTAL 26.0 MHz surface mount crystal NDK, AT-41CD2 Table 15: Bill Of Materials for the Application Circuit The Gerber files for the CC1100EM reference designs ([5] and [6]) are available from the TI website. CC1100 SWRS038D Page 22 of 92 8 Configuration Overview CC1100 can be configured to achieve optimum performance for many different applications. Configuration is done using the SPI interface. The following key parameters can be programmed: • Power-down / power up mode • Crystal oscillator power-up / power-down • Receive / transmit mode • RF channel selection • Data rate • Modulation format • RX channel filter bandwidth • RF output power • Data buffering with separate 64-byte receive and transmit FIFOs • Packet radio hardware support • Forward Error Correction (FEC) with interleaving • Data Whitening • Wake-On-Radio (WOR) Details of each configuration register can be found in Section 33, starting on page 60. Figure 5 shows a simplified state diagram that explains the main CC1100 states, together with typical usage and current consumption. For detailed information on controlling the CC1100 state machine, and a complete state diagram, see Section 19, starting on page 42. CC1100 SWRS038D Page 23 of 92 Transmit mode Receive mode IDLE Manual freq. synth. calibration RX FIFO overflow TX FIFO underflow Frequency synthesizer on SFSTXON SRX or wake-on-radio (WOR) STX STX STX or RXOFF_MODE=10 RXOFF_MODE = 00 SFTX SRX or TXOFF_MODE = 11 SIDLE SCAL SFRX IDLE TXOFF_MODE = 00 SFSTXON or RXOFF_MODE = 01 SRX or STX or SFSTXON or wake-on-radio (WOR) Sleep SPWD or wake-on-radio (WOR) Crystal oscillator off SXOFF CSn = 0 CSn = 0 TXOFF_MODE = 01 Frequency synthesizer startup, optional calibration, settling Optional freq. synth. calibration Default state when the radio is not receiving or transmitting. Typ. current consumption: 1.6 mA. Lowest power mode. Most register values are retained. Current consumption typ 400 nA, or typ 900 nA when wake-on-radio (WOR) is enabled. All register values are retained. Typ. current consumption; 0.16 mA. Used for calibrating frequency synthesizer upfront (entering receive or transmit mode can then be done quicker). Transitional state. Typ. current consumption: 8.2 mA. Frequency synthesizer is turned on, can optionally be calibrated, and then settles to the correct frequency. Transitional s Frequency synthesizer is on, tate. Typ. current consumption: 8.2 mA. ready to start transmitting. Transmission starts very quickly after receiving the STX command strobe.Typ. current consumption: 8.2 mA. Typ. current consumption: 13.5 mA at -6 dBm output, 16.9 mA at 0 dBm output, 30.7 mA at +10 dBm output. Typ. current consumption: from 14.4 mA (strong input signal) to 15.4mA (weak input signal). Optional transitional state. Typ. In FIFO-based modes, current consumption: 8.2mA. transmission is turned off and this state entered if the TX FIFO becomes empty in the middle of a packet. Typ. current consumption: 1.6 mA. In FIFO-based modes, reception is turned off and this state entered if the RX FIFO overflows. Typ. current consumption: 1.6 mA. Figure 5: Simplified State Diagram, with Typical Current Consumption at 1.2 kBaud Data Rate and MDMCFG2.DEM_DCFILT_OFF=1 (current optimized). Freq. Band = 868 MHz CC1100 SWRS038D Page 24 of 92 9 Configuration Software CC1100 can be configured using the SmartRF® Studio software [7]. The SmartRF® Studio software is highly recommended for obtaining optimum register settings, and for evaluating performance and functionality. A screenshot of the SmartRF® Studio user interface for CC1100 is shown in Figure 6. After chip reset, all the registers have default values as shown in the tables in Section 33. The optimum register setting might differ from the default value. After a reset all registers that shall be different from the default value therefore needs to be programmed through the SPI interface. Figure 6: SmartRF® Studio [7] User Interface 10 4-wire Serial Configuration and Data Interface CC1100 is configured via a simple 4-wire SPIcompatible interface (SI, SO, SCLK and CSn) where CC1100 is the slave. This interface is also used to read and write buffered data. All transfers on the SPI interface are done most significant bit first. All transactions on the SPI interface start with a header byte containing a R/W;¯ bit, a burst access bit (B), and a 6-bit address (A5 – A0). The CSn pin must be kept low during transfers on the SPI bus. If CSn goes high during the transfer of a header byte or during read/write from/to a register, the transfer will be cancelled. The timing for the address and data transfer on the SPI interface is shown in Figure 7 with reference to Table 16. When CSn is pulled low, the MCU must wait until CC1100 SO pin goes low before starting to transfer the header byte. This indicates that the crystal is running. Unless the chip was in CC1100 SWRS038D Page 25 of 92 the SLEEP or XOFF states, the SO pin will always go low immediately after taking CSn low. Figure 7: Configuration Registers Write and Read Operations Parameter Description Min Max Units SCLK frequency 100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access). - 10 SCLK frequency, single access No delay between address and data byte - 9 fSCLK SCLK frequency, burst access No delay between address and data byte, or between data bytes - 6.5 MHz tsp,pd CSn low to positive edge on SCLK, in power-down mode 150 - μs tsp CSn low to positive edge on SCLK, in active mode 20 - ns tch Clock high 50 - ns tcl Clock low 50 - ns trise Clock rise time - 5 ns tfall Clock fall time - 5 ns tsd Setup data (negative SCLK edge) to positive edge on SCLK (tsd applies between address and data bytes, and between data bytes) Single access Burst access 55 76 - - ns thd Hold data after positive edge on SCLK 20 - ns tns Negative edge on SCLK to CSn high. 20 - ns Table 16: SPI Interface Timing Requirements Note: The minimum tsp,pd figure in Table 16 can be used in cases where the user does not read the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-down depends on the start-up time of the crystal being used. The 150 us in Table 16 is the crystal oscillator start-up time measured on CC1100EM reference designs ([5] and [6]) using crystal AT-41CD2 from NDK. CC1100 SWRS038D Page 26 of 92 10.1 Chip Status Byte When the header byte, data byte, or command strobe is sent on the SPI interface, the chip status byte is sent by the CC1100 on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running. Bits 6, 5, and 4 comprise the STATE value. This value reflects the state of the chip. The XOSC and power to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and channel configuration should only be updated when the chip is in this state. The RX state will be active when the chip is in receive mode. Likewise, TX is active when the chip is transmitting. The last four bits (3:0) in the status byte contains FIFO_BYTES_AVAILABLE. For read operations (the R/W;¯ bit in the header byte is set to 1), the FIFO_BYTES_AVAILABLE field contains the number of bytes available for reading from the RX FIFO. For write operations (the R/W;¯ bit in the header byte is set to 0), the FIFO_BYTES_AVAILABLE field contains the number of bytes that can be written to the TX FIFO. When FIFO_BYTES_AVAILABLE=15, 15 or more bytes are available/free. Table 17 gives a status byte summary. Bits Name Description 7 CHIP_RDYn Stays high until power and crystal have stabilized. Should always be low when using the SPI interface. 6:4 STATE[2:0] Indicates the current main state machine mode Value State Description 000 IDLE IDLE state (Also reported for some transitional states instead of SETTLING or CALIBRATE) 001 RX Receive mode 010 TX Transmit mode 011 FSTXON Fast TX ready 100 CALIBRATE Frequency synthesizer calibration is running 101 SETTLING PLL is settling 110 RXFIFO_OVERFLOW RX FIFO has overflowed. Read out any useful data, then flush the FIFO with SFRX 111 TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with SFTX 3:0 FIFO_BYTES_AVAILABLE[3:0] The number of bytes available in the RX FIFO or free bytes in the TX FIFO Table 17: Status Byte Summary 10.2 Register Access The configuration registers on the CC1100 are located on SPI addresses from 0x00 to 0x2E. Table 36 on page 61 lists all configuration registers. It is highly recommended to use SmartRF® Studio [7] to generate optimum register settings. The detailed description of each register is found in Section 33.1 and 33.2, starting on page 64. All configuration registers can be both written to and read. The R/W;¯ bit controls if the register should be written to or read. When writing to registers, the status byte is sent on the SO pin each time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte is sent on the SO pin each time a header byte is transmitted on the SI pin. Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit (B) in the header byte. The address bits (A5 – A0) set the start address in an internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a CC1100 SWRS038D Page 27 of 92 read or a write access and must be terminated by setting CSn high. For register addresses in the range 0x30- 0x3D, the burst bit is used to select between status registers, burst bit is one, and command strobes, burst bit is zero (see 10.4 below). Because of this, burst access is not available for status registers and they must be accesses one at a time. The status registers can only be read. 10.3 SPI Read When reading register fields over the SPI interface while the register fields are updated by the radio hardware (e.g. MARCSTATE or TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the CC1100 Errata Notes [1] for more details. 10.4 Command Strobes Command Strobes may be viewed as single byte instructions to CC1100. By addressing a command strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable receive mode, enable wake-on-radio etc. The 13 command strobes are listed in Table 35 on page 60. The command strobe registers are accessed by transferring a single header byte (no data is being transferred). That is, only the R/W;¯ bit, the burst access bit (set to 0), and the six address bits (in the range 0x30 through 0x3D) are written. The R/W;¯ bit can be either one or zero and will determine how the FIFO_BYTES_AVAILABLE field in the status byte should be interpreted. When writing command strobes, the status byte is sent on the SO pin. A command strobe may be followed by any other SPI access without pulling CSn high. However, if an SRES strobe is being issued, one will have to waith for SO to go low again before the next header byte can be issued as shown in Figure 8. The command strobes are executed immediately, with the exception of the SPWD and the SXOFF strobes that are executed when CSn goes high. Figure 8: SRES Command Strobe 10.5 FIFO Access The 64-byte TX FIFO and the 64-byte RX FIFO are accessed through the 0x3F address. When the R/W;¯ bit is zero, the TX FIFO is accessed, and the RX FIFO is accessed when the R/W;¯ bit is one. The TX FIFO is write-only, while the RX FIFO is read-only. The burst bit is used to determine if the FIFO access is a single byte access or a burst access. The single byte access method expects a header byte with the burst bit set to zero and one data byte. After the data byte a new header byte is expected; hence, CSn can remain low. The burst access method expects one header byte and then consecutive data bytes until terminating the access by setting CSn high. The following header bytes access the FIFOs: • 0x3F: Single byte access to TX FIFO • 0x7F: Burst access to TX FIFO • 0xBF: Single byte access to RX FIFO • 0xFF: Burst access to RX FIFO When writing to the TX FIFO, the status byte (see Section 10.1) is output for each new data byte on SO, as shown in Figure 7. This status byte can be used to detect TX FIFO underflow while writing data to the TX FIFO. Note that the status byte contains the number of bytes free before writing the byte in progress to the TX FIFO. When the last byte that fits in the TX FIFO is transmitted on SI, the status byte received concurrently on SO will indicate that one byte is free in the TX FIFO. The TX FIFO may be flushed by issuing a SFTX command strobe. Similarly, a SFRX command strobe will flush the RX FIFO. A SFTX or SFRX command strobe can only be issued in the IDLE, TXFIFO_UNDERLOW, or RXFIFO_OVERFLOW states. Both FIFOs are flushed when going to the SLEEP state. Figure 9 gives a brief overview of different register access types possible. CC1100 SWRS038D Page 28 of 92 10.6 PATABLE Access The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings. The SPI expects up to eight data bytes after receiving the address. By programming the PATABLE, controlled PA power ramp-up and ramp-down can be achieved, as well as ASK modulation shaping for reduced bandwidth. Note that both the ASK modulation shaping and the PA ramping is limited to output powers up to -1 dBm, and the PATABLE settings allowed are 0x00 and 0x30 to 0x3F. See SmartRF® Studio [7] for recommended shaping / PA ramping sequences. See Section 24 on page 49 for details on output power programming. The PATABLE is an 8-byte table that defines the PA control settings to use for each of the eight PA power values (selected by the 3-bit value FREND0.PA_POWER). The table is written and read from the lowest setting (0) to the highest (7), one byte at a time. An index counter is used to control the access to the table. This counter is incremented each time a byte is read or written to the table, and set to the lowest index when CSn is high. When the highest value is reached the counter restarts at zero. The access to the PATABLE is either single byte or burst access depending on the burst bit. When using burst access the index counter will count up; when reaching 7 the counter will restart at 0. The R/W;¯ bit controls whether the access is a read or a write access. If one byte is written to the PATABLE and this value is to be read out then CSn must be set high before the read access in order to set the index counter back to zero. Note that the content of the PATABLE is lost when entering the SLEEP state, except for the first byte (index 0). Figure 9: Register Access Types 11 Microcontroller Interface and Pin Configuration In a typical system, CC1100 will interface to a microcontroller. This microcontroller must be able to: • Program CC1100 into different modes • Read and write buffered data • Read back status information via the 4-wire SPI-bus configuration interface (SI, SO, SCLK and CSn). 11.1 Configuration Interface The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK and CSn). The SPI is described in Section 10 on page 24. 11.2 General Control and Status Pins The CC1100 has two dedicated configurable pins (GDO0 and GDO2) and one shared pin (GDO1) that can output internal status information useful for control software. These pins can be used to generate interrupts on the MCU. See Section 30 page 55 for more details on the signals that can be programmed. GDO1 is shared with the SO pin in the SPI interface. The default setting for GDO1/SO is 3-state output. By selecting any other of the programming options, the GDO1/SO pin will become a generic pin. When CSn is low, the pin will always function as a normal SO pin. In the synchronous and asynchronous serial modes, the GDO0 pin is used as a serial TX data input pin while in transmit mode. The GDO0 pin can also be used for an on-chip analog temperature sensor. By measuring the voltage on the GDO0 pin with an external ADC, the temperature can be calculated. Specifications for the temperature sensor are found in Section 4.7 on page 16. CC1100 SWRS038D Page 29 of 92 With default PTEST register setting (0x7F) the temperature sensor output is only available when the frequency synthesizer is enabled (e.g. the MANCAL, FSTXON, RX, and TX states). It is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state. Before leaving the IDLE state, the PTEST register should be restored to its default value (0x7F). 11.3 Optional Radio Control Feature The CC1100 has an optional way of controlling the radio, by reusing SI, SCLK, and CSn from the SPI interface. This feature allows for a simple three-pin control of the major states of the radio: SLEEP, IDLE, RX, and TX. This optional functionality is enabled with the MCSM0.PIN_CTRL_EN configuration bit. State changes are commanded as follows: When CSn is high the SI and SCLK is set to the desired state according to Table 18. When CSn goes low the state of SI and SCLK is latched and a command strobe is generated internally according to the pin configuration. It is only possible to change state with this functionality. That means that for instance RX will not be restarted if SI and SCLK are set to RX and CSn toggles. When CSn is low the SI and SCLK has normal SPI functionality. All pin control command strobes are executed immediately, except the SPWD strobe, which is delayed until CSn goes high. CSn SCLK SI Function 1 X X Chip unaffected by SCLK/SI ↓ 0 0 Generates SPWD strobe ↓ 0 1 Generates STX strobe ↓ 1 0 Generates SIDLE strobe ↓ 1 1 Generates SRX strobe 0 SPI mode SPI mode SPI mode (wakes up into IDLE if in SLEEP/XOFF) Table 18: Optional Pin Control Coding 12 Data Rate Programming The data rate used when transmitting, or the data rate expected in receive is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As the formula shows, the programmed data rate depends on the crystal frequency. ( ) XOSC DRATE E DATA R = + DRATE M ⋅ ⋅ f 28 _ 2 256 _ 2 The following approach can be used to find suitable values for a given data rate: 256 2 2 _ 2 _ log _ 28 20 2 − ⋅ ⋅ = ⎥ ⎥⎦ ⎥ ⎢ ⎢⎣ ⎢ ⎟ ⎟⎠ ⎞ ⎜ ⎜⎝ ⎛ ⋅ = DRATE E XOSC DATA XOSC DATA f DRATE M R f DRATE E R If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use DRATE_M = 0. The data rate can be set from 1.2 kBaud to 500 kBaud with the minimum step size of: Min Data Rate [kBaud] Typical Data Rate [kBaud] Max Data Rate [kBaud] Data rate Step Size [kBaud] 0.8 1.2 / 2.4 3.17 0.0062 3.17 4.8 6.35 0.0124 6.35 9.6 12.7 0.0248 12.7 19.6 25.4 0.0496 25.4 38.4 50.8 0.0992 50.8 76.8 101.6 0.1984 101.6 153.6 203.1 0.3967 203.1 250 406.3 0.7935 406.3 500 500 1.5869 Table 19: Data Rate Step Size CC1100 SWRS038D Page 30 of 92 13 Receiver Channel Filter Bandwidth In order to meet different channel width requirements, the receiver channel filter is programmable. The MDMCFG4.CHANBW_E and MDMCFG4.CHANBW_M configuration registers control the receiver channel filter bandwidth, which scales with the crystal oscillator frequency. The following formula gives the relation between the register settings and the channel filter bandwidth: CHANBW E XOSC channel CHANBW M BW f 8⋅ (4 + _ )·2 _ = The CC1100 supports the following channel filter bandwidths: MDMCFG4. MDMCFG4.CHANBW_E CHANBW_M 00 01 10 11 00 812 406 203 102 01 650 325 162 81 10 541 270 135 68 11 464 232 116 58 Table 20: Channel Filter Bandwidths [kHz] (Assuming a 26MHz crystal) For best performance, the channel filter bandwidth should be selected so that the signal bandwidth occupies at most 80% of the channel filter bandwidth. The channel centre tolerance due to crystal accuracy should also be subtracted from the signal bandwidth. The following example illustrates this: With the channel filter bandwidth set to 500 kHz, the signal should stay within 80% of 500 kHz, which is 400 kHz. Assuming 915 MHz frequency and ±20 ppm frequency uncertainty for both the transmitting device and the receiving device, the total frequency uncertainty is ±40 ppm of 915MHz, which is ±37 kHz. If the whole transmitted signal bandwidth is to be received within 400kHz, the transmitted signal bandwidth should be maximum 400kHz – 2·37 kHz, which is 326 kHz. 14 Demodulator, Symbol Synchronizer, and Data Decision CC1100 contains an advanced and highly configurable demodulator. Channel filtering and frequency offset compensation is performed digitally. To generate the RSSI level (see Section 17.3 for more information) the signal level in the channel is estimated. Data filtering is also included for enhanced performance. 14.1 Frequency Offset Compensation When using 2-FSK, GFSK, or MSK modulation, the demodulator will compensate for the offset between the transmitter and receiver frequency, within certain limits, by estimating the centre of the received data. This value is available in the FREQEST status register. Writing the value from FREQEST into FSCTRL0.FREQOFF the frequency synthesizer is automatically adjusted according to the estimated frequency offset. The tracking range of the algorithm is selectable as fractions of the channel bandwidth with the FOCCFG.FOC_LIMIT configuration register. If the FOCCFG.FOC_BS_CS_GATE bit is set, the offset compensator will freeze until carrier sense asserts. This may be useful when the radio is in RX for long periods with no traffic, since the algorithm may drift to the boundaries when trying to track noise. The tracking loop has two gain factors, which affects the settling time and noise sensitivity of the algorithm. FOCCFG.FOC_PRE_K sets the gain before the sync word is detected, and FOCCFG.FOC_POST_K selects the gain after the sync word has been found. Note that frequency offset compensation is not supported for ASK or OOK modulation. 14.2 Bit Synchronization The bit synchronization algorithm extracts the clock from the incoming symbols. The algorithm requires that the expected data rate is programmed as described in Section 12 on page 29. Re-synchronization is performed continuously to adjust for error in the incoming symbol rate. CC1100 SWRS038D Page 31 of 92 14.3 Byte Synchronization Byte synchronization is achieved by a continuous sync word search. The sync word is a 16 bit configurable field (can be repeated to get a 32 bit) that is automatically inserted at the start of the packet by the modulator in transmit mode. The demodulator uses this field to find the byte boundaries in the stream of bits. The sync word will also function as a system identifier, since only packets with the correct predefined sync word will be received if the sync word detection in RX is enabled in register MDMCFG2 (see Section 17.1). The sync word detector correlates against the user-configured 16 or 32 bit sync word. The correlation threshold can be set to 15/16, 16/16, or 30/32 bits match. The sync word can be further qualified using the preamble quality indicator mechanism described below and/or a carrier sense condition. The sync word is configured through the SYNC1 and SYNC0 registers. In order to make false detections of sync words less likely, a mechanism called preamble quality indication (PQI) can be used to qualify the sync word. A threshold value for the preamble quality must be exceeded in order for a detected sync word to be accepted. See Section 17.2 on page 37 for more details. 15 Packet Handling Hardware Support The CC1100 has built-in hardware support for packet oriented radio protocols. In transmit mode, the packet handler can be configured to add the following elements to the packet stored in the TX FIFO: • A programmable number of preamble bytes • A two byte synchronization (sync) word. Can be duplicated to give a 4-byte sync word (recommended). It is not possible to only insert preamble or only insert a sync word. • A CRC checksum computed over the data field. • • The recommended setting is 4-byte preamble and 4-byte sync word, except for 500 kBaud data rate where the recommended preamble length is 8 bytes. • • In addition, the following can be implemented on the data field and the optional 2-byte CRC checksum: • • Whitening of the data with a PN9 sequence. • Forward error correction by the use of interleaving and coding of the data (convolutional coding). • In receive mode, the packet handling support will de-construct the data packet by implementing the following (if enabled): • Preamble detection. • Sync word detection. • CRC computation and CRC check. • One byte address check. • Packet length check (length byte checked against a programmable maximum length). • De-whitening • De-interleaving and decoding • Optionally, two status bytes (see Table 21 and Table 22) with RSSI value, Link Quality Indication, and CRC status can be appended in the RX FIFO. • Bit Field Name Description 7:0 RSSI RSSI value Table 21: Received Packet Status Byte 1 (first byte appended after the data) Bit Field Name Description 7 CRC_OK 1: CRC for received data OK (or CRC disabled) 0: CRC error in received data 6:0 LQI Indicating the link quality Table 22: Received Packet Status Byte 2 (second byte appended after the data) • • Note that register fields that control the packet handling features should only be altered when CC1100 is in the IDLE state. 15.1 Data Whitening From a radio perspective, the ideal over the air data are random and DC free. This results in the smoothest power distribution over the occupied bandwidth. This also gives the regulation loops in the receiver uniform operation conditions (no data dependencies). CC1100 SWRS038D Page 32 of 92 Real world data often contain long sequences of zeros and ones. Performance can then be improved by whitening the data before transmitting, and de-whitening the data in the receiver. With CC1100, this can be done automatically by setting PKTCTRL0.WHITE_DATA=1. All data, except the preamble and the sync word, are then XOR-ed with a 9-bit pseudo-random (PN9) sequence before being transmitted, as shown in Figure 10. At the receiver end, the data are XOR-ed with the same pseudo-random sequence. This way, the whitening is reversed, and the original data appear in the receiver. The PN9 sequence is initialized to all 1’s. Figure 10: Data Whitening in TX Mode 15.2 Packet Format The format of the data packet can be configured and consists of the following items (see Figure 11): • Preamble • Synchronization word • Optional length byte • Optional address byte • Payload • Optional 2 byte CRC • Preamble bits (1010...1010) Sync word Length field Address field Data field CRC-16 Optional CRC-16 calculation Optionally FEC encoded/decoded 8 x n bits 16/32 bits 8 bits 8 bits 8 x n bits 16 bits Optional data whitening Legend: Inserted automatically in TX, processed and removed in RX. Optional user-provided fields processed in TX, processed but not removed in RX. Unprocessed user data (apart from FEC and/or whitening) Figure 11: Packet Format The preamble pattern is an alternating sequence of ones and zeros (10101010…). The minimum length of the preamble is programmable. When enabling TX, the modulator will start transmitting the preamble. When the programmed number of preamble bytes has been transmitted, the modulator will send the sync word and then data from the TX FIFO if data is available. If the TX FIFO is empty, the modulator will continue to send CC1100 SWRS038D Page 33 of 92 preamble bytes until the first byte is written to the TX FIFO. The modulator will then send the sync word and then the data bytes. The number of preamble bytes is programmed with the MDMCFG1.NUM_PREAMBLE value. The synchronization word is a two-byte value set in the SYNC1 and SYNC0 registers. The sync word provides byte synchronization of the incoming packet. A one-byte synch word can be emulated by setting the SYNC1 value to the preamble pattern. It is also possible to emulate a 32 bit sync word by using MDMCFG2.SYNC_MODE set to 3 or 7. The sync word will then be repeated twice. CC1100 supports both constant packet length protocols and variable length protocols. Variable or fixed packet length mode can be used for packets up to 255 bytes. For longer packets, infinite packet length mode must be used. Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG=0. The desired packet length is set by the PKTLEN register. In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the packet length is configured by the first byte after the sync word. The packet length is defined as the payload data, excluding the length byte and the optional CRC. The PKTLEN register is used to set the maximum packet length allowed in RX. Any packet received with a length byte with a value greater than PKTLEN will be discarded. With PKTCTRL0.LENGTH_CONFIG=2, the packet length is set to infinite and transmission and reception will continue until turned off manually. As described in the next section, this can be used to support packet formats with different length configuration than natively supported by CC1100. One should make sure that TX mode is not turned off during the transmission of the first half of any byte. Refer to the CC1100 Errata Notes [1] for more details. Note that the minimum packet length supported (excluding the optional length byte and CRC) is one byte of payload data. 15.2.1 Arbitrary Length Field Configuration The packet length register, PKTLEN, can be reprogrammed during receive and transmit. In combination with fixed packet length mode (PKTCTRL0.LENGTH_CONFIG=0) this opens the possibility to have a different length field configuration than supported for variable length packets (in variable packet length mode the length byte is the first byte after the sync word). At the start of reception, the packet length is set to a large value. The MCU reads out enough bytes to interpret the length field in the packet. Then the PKTLEN value is set according to this value. The end of packet will occur when the byte counter in the packet handler is equal to the PKTLEN register. Thus, the MCU must be able to program the correct length, before the internal counter reaches the packet length. 15.2.2 Packet Length > 255 Also the packet automation control register, PKTCTRL0, can be reprogrammed during TX and RX. This opens the possibility to transmit and receive packets that are longer than 256 bytes and still be able to use the packet handling hardware support. At the start of the packet, the infinite packet length mode (PKTCTRL0.LENGTH_CONFIG=2) must be active. On the TX side, the PKTLEN register is set to mod(length, 256). On the RX side the MCU reads out enough bytes to interpret the length field in the packet and sets the PKTLEN register to mod(length, 256). When less than 256 bytes remains of the packet the MCU disables infinite packet length mode and activates fixed packet length mode. When the internal byte counter reaches the PKTLEN value, the transmission or reception ends (the radio enters the state determined by TXOFF_MODE or RXOFF_MODE). Automatic CRC appending/checking can also be used (by setting PKTCTRL0.CRC_EN=1). When for example a 600-byte packet is to be transmitted, the MCU should do the following (see also Figure 12) • Set PKTCTRL0.LENGTH_CONFIG=2. • Pre-program the PKTLEN register to mod(600, 256) = 88. • Transmit at least 345 bytes (600 - 255), for example by filling the 64-byte TX FIFO six times (384 bytes transmitted). • Set PKTCTRL0.LENGTH_CONFIG=0. • The transmission ends when the packet counter reaches 88. A total of 600 bytes are transmitted. CC1100 SWRS038D Page 34 of 92 0,1,..........,88,....................255,0,........,88,..................,255,0,........,88,..................,255,0,....................... Internal byte counter in packet handler counts from 0 to 255 and then starts at 0 again Length field transmitted and received. Rx and Tx PKTLEN value set to mod(600,256) = 88 Infinite packet length enabled Fixed packet length enabled when less than 256 bytes remains of packet 600 bytes transmitted and received Figure 12: Packet Length > 255 15.3 Packet Filtering in Receive Mode CC1100 supports three different types of packet-filtering; address filtering, maximum length filtering, and CRC filtering. 15.3.1 Address Filtering Setting PKTCTRL1.ADR_CHK to any other value than zero enables the packet address filter. The packet handler engine will compare the destination address byte in the packet with the programmed node address in the ADDR register and the 0x00 broadcast address when PKTCTRL1.ADR_CHK=10 or both 0x00 and 0xFF broadcast addresses when PKTCTRL1.ADR_CHK=11. If the received address matches a valid address, the packet is received and written into the RX FIFO. If the address match fails, the packet is discarded and receive mode restarted (regardless of the MCSM1.RXOFF_MODE setting). If the received address matches a valid address when using infinite packet length mode and address filtering is enabled, 0xFF will be written into the RX FIFO followed by the address byte and then the payload data. 15.3.2 Maximum Length Filtering In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the PKTLEN.PACKET_LENGTH register value is used to set the maximum allowed packet length. If the received length byte has a larger value than this, the packet is discarded and receive mode restarted (regardless of the MCSM1.RXOFF_MODE setting). 15.3.3 CRC Filtering The filtering of a packet when CRC check fails is enabled by setting PKTCTRL1.CRC_AUTOFLUSH=1. The CRC auto flush function will flush the entire RX FIFO if the CRC check fails. After auto flushing the RX FIFO, the next state depends on the MCSM1.RXOFF_MODE setting. When using the auto flush function, the maximum packet length is 63 bytes in variable packet length mode and 64 bytes in fixed packet length mode. Note that the maximum allowed packet length is reduced by two bytes when PKTCTRL1.APPEND_STATUS is enabled, to make room in the RX FIFO for the two status bytes appended at the end of the packet. Since the entire RX FIFO is flushed when the CRC check fails, the previously received packet must be read out of the FIFO before receiving the current packet. The MCU must not read from the current packet until the CRC has been checked as OK. 15.4 Packet Handling in Transmit Mode The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be the length byte when variable packet length is enabled. The length byte has a value equal to the payload of the packet (including the optional address byte). If address recognition is enabled on the receiver, the second byte written to the TX FIFO must be the address byte. If fixed packet length is enabled, then the first byte written to the TX FIFO should be the address (if the receiver uses address recognition). The modulator will first send the programmed number of preamble bytes. If data is available in the TX FIFO, the modulator will send the two-byte (optionally 4-byte) sync word and then the payload in the TX FIFO. If CRC is enabled, the checksum is calculated over all the data pulled from the TX FIFO and the result is sent as two extra bytes following the payload data. If the TX FIFO runs empty before the complete packet has been CC1100 SWRS038D Page 35 of 92 transmitted, the radio will enter TXFIFO_UNDERFLOW state. The only way to exit this state is by issuing an SFTX strobe. Writing to the TX FIFO after it has underflowed will not restart TX mode. If whitening is enabled, everything following the sync words will be whitened. This is done before the optional FEC/Interleaver stage. Whitening is enabled by setting PKTCTRL0.WHITE_DATA=1. If FEC/Interleaving is enabled, everything following the sync words will be scrambled by the interleaver and FEC encoded before being modulated. FEC is enabled by setting MDMCFG1.FEC_EN=1. 15.5 Packet Handling in Receive Mode In receive mode, the demodulator and packet handler will search for a valid preamble and the sync word. When found, the demodulator has obtained both bit and byte synchronism and will receive the first payload byte. If FEC/Interleaving is enabled, the FEC decoder will start to decode the first payload byte. The interleaver will de-scramble the bits before any other processing is done to the data. If whitening is enabled, the data will be dewhitened at this stage. When variable packet length mode is enabled, the first byte is the length byte. The packet handler stores this value as the packet length and receives the number of bytes indicated by the length byte. If fixed packet length mode is used, the packet handler will accept the programmed number of bytes. Next, the packet handler optionally checks the address and only continues the reception if the address matches. If automatic CRC check is enabled, the packet handler computes CRC and matches it with the appended CRC checksum. At the end of the payload, the packet handler will optionally write two extra packet status bytes (see Table 21 and Table 22) that contain CRC status, link quality indication, and RSSI value. 15.6 Packet Handling in Firmware When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet has been received/transmitted. Additionally, for packets longer than 64 bytes the RX FIFO needs to be read while in RX and the TX FIFO needs to be refilled while in TX. This means that the MCU needs to know the number of bytes that can be read from or written to the RX FIFO and TX FIFO respectively. There are two possible solutions to get the necessary status information: a) Interrupt Driven Solution In both RX and TX one can use one of the GDO pins to give an interrupt when a sync word has been received/transmitted and/or when a complete packet has been received/transmitted (IOCFGx.GDOx_CFG=0x06). In addition, there are 2 configurations for the IOCFGx.GDOx_CFG register that are associated with the RX FIFO (IOCFGx.GDOx_CFG=0x00 and IOCFGx.GDOx_CFG=0x01) and two that are associated with the TX FIFO (IOCFGx.GDOx_CFG=0x02 and IOCFGx.GDOx_CFG=0x03) that can be used as interrupt sources to provide information on how many bytes are in the RX FIFO and TX FIFO respectively. See Table 34. b) SPI Polling The PKTSTATUS register can be polled at a given rate to get information about the current GDO2 and GDO0 values respectively. The RXBYTES and TXBYTES registers can be polled at a given rate to get information about the number of bytes in the RX FIFO and TX FIFO respectively. Alternatively, the number of bytes in the RX FIFO and TX FIFO can be read from the chip status byte returned on the MISO line each time a header byte, data byte, or command strobe is sent on the SPI bus. It is recommended to employ an interrupt driven solution as high rate SPI polling will reduce the RX sensitivity. Furthermore, as explained in Section 10.3 and the CC1100 Errata Notes [1], when using SPI polling there is a small, but finite, probability that a single read from registers PKTSTATUS , RXBYTES and TXBYTES is being corrupt. The same is the case when reading the chip status byte. Refer to the TI website for SW examples ([8] and [9]). CC1100 SWRS038D Page 36 of 92 16 Modulation Formats CC1100 supports amplitude, frequency, and phase shift modulation formats. The desired modulation format is set in the MDMCFG2.MOD_FORMAT register. Optionally, the data stream can be Manchester coded by the modulator and decoded by the demodulator. This option is enabled by setting MDMCFG2.MANCHESTER_EN=1. Manchester encoding is not supported at the same time as using the FEC/Interleaver option. 16.1 Frequency Shift Keying 2-FSK can optionally be shaped by a Gaussian filter with BT = 1, producing a GFSK modulated signal. The frequency deviation is programmed with the DEVIATION_M and DEVIATION_E values in the DEVIATN register. The value has an exponent/mantissa form, and the resultant deviation is given by: xosc DEVIATION E dev f f DEVIATION M _ 17 (8 _ ) 2 2 = ⋅ + ⋅ The symbol encoding is shown in Table 23. Format Symbol Coding 2-FSK/GFSK ‘0’ – Deviation ‘1’ + Deviation Table 23: Symbol Encoding for 2-FSK/GFSK Modulation 16.2 Minimum Shift Keying When using MSK1, the complete transmission (preamble, sync word, and payload) will be MSK modulated. Phase shifts are performed with a constant transition time. The fraction of a symbol period used to change the phase can be modified with the DEVIATN.DEVIATION_M setting. This is equivalent to changing the shaping of the symbol. The MSK modulation format implemented in CC1100 inverts the sync word and data compared to e.g. signal generators. 16.3 Amplitude Modulation CC1100 supports two different forms of amplitude modulation: On-Off Keying (OOK) and Amplitude Shift Keying (ASK). OOK modulation simply turns on or off the PA to modulate 1 and 0 respectively. The ASK variant supported by the CC1100 allows programming of the modulation depth (the difference between 1 and 0), and shaping of the pulse amplitude. Pulse shaping will produce a more bandwidth constrained output spectrum. Note that the pulse shaping feature on the CC1100 does only support output power up to about -1dBm. The PATABLE settings that can be used for pulse shaping are 0x00 and 0x30 to 0x3F. 1 Identical to offset QPSK with half-sine shaping (data coding may differ) CC1100 SWRS038D Page 37 of 92 17 Received Signal Qualifiers and Link Quality Information CC1100 has several qualifiers that can be used to increase the likelihood that a valid sync word is detected. 17.1 Sync Word Qualifier If sync word detection in RX is enabled in register MDMCFG2 the CC1100 will not start filling the RX FIFO and perform the packet filtering described in Section 15.3 before a valid sync word has been detected. The sync word qualifier mode is set by MDMCFG2.SYNC_MODE and is summarized in Table 24. Carrier sense is described in Section 17.4. MDMCFG2. SYNC_MODE Sync Word Qualifier Mode 000 No preamble/sync 001 15/16 sync word bits detected 010 16/16 sync word bits detected 011 30/32 sync word bits detected 100 No preamble/sync, carrier sense above threshold 101 15/16 + carrier sense above threshold 110 16/16 + carrier sense above threshold 111 30/32 + carrier sense above threshold Table 24: Sync Word Qualifier Mode 17.2 Preamble Quality Threshold (PQT) The Preamble Quality Threshold (PQT) syncword qualifier adds the requirement that the received sync word must be preceded with a preamble with a quality above the programmed threshold. Another use of the preamble quality threshold is as a qualifier for the optional RX termination timer. See Section 19.7 on page 46 for details. The preamble quality estimator increases an internal counter by one each time a bit is received that is different from the previous bit, and decreases the counter by 8 each time a bit is received that is the same as the last bit. The threshold is configured with the register field PKTCTRL1.PQT. A threshold of 4·PQT for this counter is used to gate sync word detection. By setting the value to zero, the preamble quality qualifier of the synch word is disabled. A “Preamble Quality Reached” signal can be observed on one of the GDO pins by setting IOCFGx.GDOx_CFG=8. It is also possible to determine if preamble quality is reached by checking the PQT_REACHED bit in the PKTSTATUS register. This signal / bit asserts when the received signal exceeds the PQT. 17.3 RSSI The RSSI value is an estimate of the signal power level in the chosen channel. This value is based on the current gain setting in the RX chain and the measured signal level in the channel. In RX mode, the RSSI value can be read continuously from the RSSI status register until the demodulator detects a sync word (when sync word detection is enabled). At that point the RSSI readout value is frozen until the next time the chip enters the RX state. The RSSI value is in dBm with ½dB resolution. The RSSI update rate, fRSSI, depends on the receiver filter bandwidth (BWchannel defined in Section 13) and AGCCTRL0.FILTER_LENGTH. FILTER LENGTH channel RSSI f BW8 2 _ 2 ⋅ = ⋅ If PKTCTRL1.APPEND_STATUS is enabled the last RSSI value of the packet is automatically added to the first byte appended after the payload. The RSSI value read from the RSSI status register is a 2’s complement number. The following procedure can be used to convert the RSSI reading to an absolute power level (RSSI_dBm). 1) Read the RSSI status register 2) Convert the reading from a hexadecimal number to a decimal number (RSSI_dec) 3) If RSSI_dec ≥ 128 then RSSI_dBm = (RSSI_dec - 256)/2 – RSSI_offset 4) Else if RSSI_dec < 128 then RSSI_dBm = (RSSI_dec)/2 – RSSI_offset Table 25 gives typical values for the RSSI_offset. Figure 13 and Figure 14 shows typical plots of RSSI reading as a function of input power level for different data rates. CC1100 SWRS038D Page 38 of 92 Data rate [kBaud] RSSI_offset [dB], 433 MHz RSSI_offset [dB], 868 MHz 1.2 75 74 38.4 75 74 250 79 78 500 79 77 Table 25: Typical RSSI_offset Values Figure 13: Typical RSSI Value vs. Input Power Level for Different Data Rates at 433 MHz Figure 14: Typical RSSI Value vs. Input Power Level for Different Data Rates at 868 MHz -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Power [dBm] 1.2 kBuad 38.4 kBaud 250 kBaud 500 kBaud RSSI Readout [dBm] -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Power [dBm] RSSI Readout [ dBm] 1.2 kBaud 38.4 kBuad 250 kBaud 500 kBaud CC1100 SWRS038D Page 39 of 92 17.4 Carrier Sense (CS) Carrier Sense (CS) is used as a sync word qualifier and for CCA and can be asserted based on two conditions, which can be individually adjusted: • CS is asserted when the RSSI is above a programmable absolute threshold, and deasserted when RSSI is below the same threshold (with hysteresis). • CS is asserted when the RSSI has increased with a programmable number of dB from one RSSI sample to the next, and de-asserted when RSSI has decreased with the same number of dB. This setting is not dependent on the absolute signal level and is thus useful to detect signals in environments with time varying noise floor. Carrier Sense can be used as a sync word qualifier that requires the signal level to be higher than the threshold for a sync word search to be performed. The signal can also be observed on one of the GDO pins by setting IOCFGx.GDOx_CFG=14 and in the status register bit PKTSTATUS.CS. Other uses of Carrier Sense include the TX-if- CCA function (see Section 17.5 on page 40) and the optional fast RX termination (see Section 19.7 on page 46). CS can be used to avoid interference from other RF sources in the ISM bands. 17.4.1 CS Absolute Threshold The absolute threshold related to the RSSI value depends on the following register fields: • AGCCTRL2.MAX_LNA_GAIN • AGCCTRL2.MAX_DVGA_GAIN • AGCCTRL1.CARRIER_SENSE_ABS_THR • AGCCTRL2.MAGN_TARGET • For a given AGCCTRL2.MAX_LNA_GAIN and AGCCTRL2.MAX_DVGA_GAIN setting the absolute threshold can be adjusted ±7 dB in steps of 1 dB using CARRIER_SENSE_ABS_THR. The MAGN_TARGET setting is a compromise between blocker tolerance/selectivity and sensitivity. The value sets the desired signal level in the channel into the demodulator. Increasing this value reduces the headroom for blockers, and therefore close-in selectivity. It is strongly recommended to use SmartRF® Studio to generate the correct MAGN_TARGET setting. Table 26 and Table 27 show the typical RSSI readout values at the CS threshold at 2.4 kBaud and 250 kBaud data rate respectively. The default CARRIER_SENSE_ABS_THR=0 (0 dB) and MAGN_TARGET=3 (33 dB) have been used. For other data rates the user must generate similar tables to find the CS absolute threshold. MAX_DVGA_GAIN[1:0] 00 01 10 11 000 -97.5 -91.5 -85.5 -79.5 001 -94 -88 -82.5 -76 010 -90.5 -84.5 -78.5 -72.5 011 -88 -82.5 -76.5 -70.5 100 -85.5 -80 -73.5 -68 101 -84 -78 -72 -66 110 -82 -76 -70 -64 MAX_LNA_GAIN[2:0] 111 -79 -73.5 -67 -61 Table 26: Typical RSSI Value in dBm at CS Threshold with Default MAGN_TARGET at 2.4 kBaud, 868 MHz MAX_DVGA_GAIN[1:0] 00 01 10 11 000 -90.5 -84.5 -78.5 -72.5 001 -88 -82 -76 -70 010 -84.5 -78.5 -72 -66 011 -82.5 -76.5 -70 -64 100 -80.5 -74.5 -68 -62 101 -78 -72 -66 -60 110 -76.5 -70 -64 -58 MAX_LNA_GAIN[2:0] 111 -74.5 -68 -62 -56 Table 27: Typical RSSI Value in dBm at CS Threshold with Default MAGN_TARGET at 250 kBaud, 868 MHz If the threshold is set high, i.e. only strong signals are wanted, the threshold should be adjusted upwards by first reducing the MAX_LNA_GAIN value and then the MAX_DVGA_GAIN value. This will reduce power consumption in the receiver front end, since the highest gain settings are avoided. CC1100 SWRS038D Page 40 of 92 17.4.2 CS Relative Threshold The relative threshold detects sudden changes in the measured signal level. This setting is not dependent on the absolute signal level and is thus useful to detect signals in environments with a time varying noise floor. The register field AGCCTRL1.CARRIER_SENSE_REL_THR is used to enable/disable relative CS, and to select threshold of 6 dB, 10 dB, or 14 dB RSSI change. 17.5 Clear Channel Assessment (CCA) The Clear Channel Assessment (CCA) is used to indicate if the current channel is free or busy. The current CCA state is viewable on any of the GDO pins by setting IOCFGx.GDOx_ CFG=0x09. MCSM1.CCA_MODE selects the mode to use when determining CCA. When the STX or SFSTXON command strobe is given while CC1100 is in the RX state, the TX or FSTXON state is only entered if the clear channel requirements are fulfilled. The chip will otherwise remain in RX (if the channel becomes available, the radio will not enter TX or FSTXON state before a new strobe command is sent on the SPI interface). This feature is called TX-if-CCA. Four CCA requirements can be programmed: • Always (CCA disabled, always goes to TX) • If RSSI is below threshold • Unless currently receiving a packet • Both the above (RSSI below threshold and not currently receiving a packet) 17.6 Link Quality Indicator (LQI) The Link Quality Indicator is a metric of the current quality of the received signal. If PKTCTRL1.APPEND_STATUS is enabled, the value is automatically added to the last byte appended after the payload. The value can also be read from the LQI status register. The LQI gives an estimate of how easily a received signal can be demodulated by accumulating the magnitude of the error between ideal constellations and the received signal over the 64 symbols immediately following the sync word. LQI is best used as a relative measurement of the link quality (a high value indicates a better link than what a low value does), since the value is dependent on the modulation format. 18 Forward Error Correction with Interleaving 18.1 Forward Error Correction (FEC) CC1100 has built in support for Forward Error Correction (FEC). To enable this option, set MDMCFG1.FEC_EN to 1. FEC is only supported in fixed packet length mode (PKTCTRL0.LENGTH_CONFIG=0). FEC is employed on the data field and CRC word in order to reduce the gross bit error rate when operating near the sensitivity limit. Redundancy is added to the transmitted data in such a way that the receiver can restore the original data in the presence of some bit errors. The use of FEC allows correct reception at a lower SNR, thus extending communication range if the receiver bandwidth remains constant. Alternatively, for a given SNR, using FEC decreases the bit error rate (BER). As the packet error rate (PER) is related to BER by: PER = 1− (1− BER) packet _ length a lower BER can be used to allow longer packets, or a higher percentage of packets of a given length, to be transmitted successfully. Finally, in realistic ISM radio environments, transient and time-varying phenomena will produce occasional errors even in otherwise good reception conditions. FEC will mask such errors and, combined with interleaving of the coded data, even correct relatively long periods of faulty reception (burst errors). The FEC scheme adopted for CC1100 is convolutional coding, in which n bits are generated based on k input bits and the m most recent input bits, forming a code stream able to withstand a certain number of bit errors between each coding state (the m-bit window). The convolutional coder is a rate 1/2 code with a constraint length of m = 4. The coder codes one input bit and produces two output bits; hence, the effective data rate is halved. I.e. to transmit at the same effective datarate when using FEC, it is necessary to use twice as high over-the-air datarate. This will require a higher receiver bandwidth, and thus reduce sensitivity. In other words the improved CC1100 SWRS038D Page 41 of 92 reception by using FEC and the degraded sensitivity from a higher receiver bandwidth will be counteracting factors. 18.2 Interleaving Data received through radio channels will often experience burst errors due to interference and time-varying signal strengths. In order to increase the robustness to errors spanning multiple bits, interleaving is used when FEC is enabled. After de-interleaving, a continuous span of errors in the received stream will become single errors spread apart. CC1100 employs matrix interleaving, which is illustrated in Figure 15. The on-chip interleaving and de-interleaving buffers are 4 x 4 matrices. In the transmitter, the data bits from the rate ½ convolutional coder are written into the rows of the matrix, whereas the bit sequence to be transmitted is read from the columns of the matrix. Conversely, in the receiver, the received symbols are written into the columns of the matrix, whereas the data passed onto the convolutional decoder is read from the rows of the matrix. When FEC and interleaving is used at least one extra byte is required for trellis termination. In addition, the amount of data transmitted over the air must be a multiple of the size of the interleaver buffer (two bytes). The packet control hardware therefore automatically inserts one or two extra bytes at the end of the packet, so that the total length of the data to be interleaved is an even number. Note that these extra bytes are invisible to the user, as they are removed before the received packet enters the RX FIFO. When FEC and interleaving is used the minimum data payload is 2 bytes. Packet Engine FEC Encoder Modulator Interleaver Write buffer Interleaver Read buffer Demodulator FEC Decoder Packet Engine Interleaver Write buffer Interleaver Read buffer Figure 15: General Principle of Matrix Interleaving CC1100 SWRS038D Page 42 of 92 19 Radio Control TX 19,20 RX 13,14,15 IDLE 1 CALIBRATE 8 MANCAL 3,4,5 SETTLING 9,10,11 RX_OVERFLOW 17 TX_UNDERFLOW 22 RXTX_SETTLING 21 FSTXON 18 SFSTXON FS_AUTOCAL = 00 | 10 | 11 & SRX | STX | SFSTXON | WOR STX SRX | WOR STX TXFIFO_UNDERFLOW STX | RXOFF_MODE = 10 RXOFF_MODE = 00 & FS_AUTOCAL = 10 | 11 SFTX SRX | TXOFF_MODE = 11 SIDLE SCAL CAL_COMPLETE FS_AUTOCAL = 01 & SRX | STX | SFSTXON | WOR RXFIFO_OVERFLOW CAL_COMPLETE SFRX CALIBRATE 12 IDLE 1 TXOFF_MODE = 00 & FS_AUTOCAL = 10 | 11 RXOFF_MODE = 00 & FS_AUTOCAL = 00 | 01 TXOFF_MODE = 00 & FS_AUTOCAL = 00 | 01 TXOFF_MODE = 10 RXOFF_MODE = 11 SFSTXON | RXOFF_MODE = 01 TXRX_SETTLING 16 SRX | STX | SFSTXON | WOR SLEEP 0 SPWD | SWOR XOFF 2 SXOFF CSn = 0 CSn = 0 | WOR ( STX | SFSTXON ) & CCA | RXOFF_MODE = 01 | 10 TXOFF_MODE=01 FS_WAKEUP 6,7 SRX Figure 16: Complete Radio Control State Diagram CC1100 has a built-in state machine that is used to switch between different operational states (modes). The change of state is done either by using command strobes or by internal events such as TX FIFO underflow. A simplified state diagram, together with typical usage and current consumption, is shown in Figure 5 on page 23. The complete radio control state diagram is shown in Figure 16. The numbers refer to the state number readable in the MARCSTATE status register. This register is primarily for test purposes. 19.1 Power-On Start-Up Sequence When the power supply is turned on, the system must be reset. This is achieved by one of the two sequences described below, i.e. automatic power-on reset (POR) or manual reset. After the automatic power-on reset or manual reset it is also recommended to change the signal that is output on the GDO0 pin. The default setting is to output a clock signal with a frequency of CLK_XOSC/192, but to optimize CC1100 SWRS038D Page 43 of 92 performance in TX and RX an alternative GDO setting should be selected from the settings found in Table 34 on page 56. 19.1.1 Automatic POR A power-on reset circuit is included in the CC1100. The minimum requirements stated in Table 12 must be followed for the power-on reset to function properly. The internal powerup sequence is completed when CHIP_RDYn goes low. CHIP_RDYn is observed on the SO pin after CSn is pulled low. See Section 10.1 for more details on CHIP_RDYn. When the CC1100 reset is completed the chip will be in the IDLE state and the crystal oscillator will be running. If the chip has had sufficient time for the crystal oscillator to stabilize after the power-on-reset the SO pin will go low immediately after taking CSn low. If CSn is taken low before reset is completed the SO pin will first go high, indicating that the crystal oscillator is not stabilized, before going low as shown in Figure 17. Figure 17: Power-On Reset 19.1.2 Manual Reset The other global reset possibility on CC1100 uses the SRES command strobe. By issuing this strobe, all internal registers and states are set to the default, IDLE state. The manual power-up sequence is as follows (see Figure 18): • Set SCLK = 1 and SI = 0, to avoid potential problems with pin control mode (see Section 11.3 on page 29). • Strobe CSn low / high. • Hold CSn high for at least 40μs relative to pulling CSn low • Pull CSn low and wait for SO to go low (CHIP_RDYn). • Issue the SRES strobe on the SI line. • When SO goes low again, reset is complete and the chip is in the IDLE state. CSn SO XOSC Stable XOSC and voltage regulator switched on SI SRES 40 us Figure 18: Power-On Reset with SRES Note that the above reset procedure is only required just after the power supply is first turned on. If the user wants to reset the CC1100 after this, it is only necessary to issue an SRES command strobe. 19.2 Crystal Control The crystal oscillator (XOSC) is either automatically controlled or always on, if MCSM0.XOSC_FORCE_ON is set. In the automatic mode, the XOSC will be turned off if the SXOFF or SPWD command strobes are issued; the state machine then goes to XOFF or SLEEP respectively. This can only be done from the IDLE state. The XOSC will be turned off when CSn is released (goes high). The XOSC will be automatically turned on again when CSn goes low. The state machine will then go to the IDLE state. The SO pin on the SPI interface must be pulled low before the SPI interface is ready to be used; as described in Section 10.1 on page 26. If the XOSC is forced on, the crystal will always stay on even in the SLEEP state. Crystal oscillator start-up time depends on crystal ESR and load capacitances. The electrical specification for the crystal oscillator can be found in Section 4.4 on page 14. 19.3 Voltage Regulator Control The voltage regulator to the digital core is controlled by the radio controller. When the chip enters the SLEEP state, which is the state with the lowest current consumption, the voltage regulator is disabled. This occurs after CSn is released when a SPWD command strobe has been sent on the SPI interface. The chip is now in the SLEEP state. Setting CSn CC1100 SWRS038D Page 44 of 92 low again will turn on the regulator and crystal oscillator and make the chip enter the IDLE state. When wake on radio is enabled, the WOR module will control the voltage regulator as described in Section 19.5. 19.4 Active Modes CC1100 has two active modes: receive and transmit. These modes are activated directly by the MCU by using the SRX and STX command strobes, or automatically by Wake on Radio. The frequency synthesizer must be calibrated regularly. CC1100 has one manual calibration option (using the SCAL strobe), and three automatic calibration options, controlled by the MCSM0.FS_AUTOCAL setting: • Calibrate when going from IDLE to either RX or TX (or FSTXON) • Calibrate when going from either RX or TX to IDLE automatically • Calibrate every fourth time when going from either RX or TX to IDLE automatically If the radio goes from TX or RX to IDLE by issuing an SIDLE strobe, calibration will not be performed. The calibration takes a constant number of XOSC cycles (see Table 28 for timing details). When RX is activated, the chip will remain in receive mode until a packet is successfully received or the RX termination timer expires (see Section 19.7). Note: the probability that a false sync word is detected can be reduced by using PQT, CS, maximum sync word length, and sync word qualifier mode as described in Section 17. After a packet is successfully received the radio controller will then go to the state indicated by the MCSM1.RXOFF_MODE setting. The possible destinations are: • IDLE • FSTXON: Frequency synthesizer on and ready at the TX frequency. Activate TX with STX . • TX: Start sending preamble • RX: Start search for a new packet Similarly, when TX is active the chip will remain in the TX state until the current packet has been successfully transmitted. Then the state will change as indicated by the MCSM1.TXOFF_MODE setting. The possible destinations are the same as for RX. The MCU can manually change the state from RX to TX and vice versa by using the command strobes. If the radio controller is currently in transmit and the SRX strobe is used, the current transmission will be ended and the transition to RX will be done. If the radio controller is in RX when the STX or SFSTXON command strobes are used, the TXif- CCA function will be used. If the channel is not clear, the chip will remain in RX. The MCSM1.CCA_MODE setting controls the conditions for clear channel assessment. See Section 17.5 on page 40 for details. The SIDLE command strobe can always be used to force the radio controller to go to the IDLE state. 19.5 Wake On Radio (WOR) The optional Wake on Radio (WOR) functionality enables CC1100 to periodically wake up from SLEEP and listen for incoming packets without MCU interaction. When the WOR strobe command is sent on the SPI interface, the CC1100 will go to the SLEEP state when CSn is released. The RC oscillator must be enabled before the WOR strobe can be used, as it is the clock source for the WOR timer. The on-chip timer will set CC1100 into IDLE state and then RX state. After a programmable time in RX, the chip will go back to the SLEEP state, unless a packet is received. See Figure 19 and Section 19.7 for details on how the timeout works. Set the CC1100 into the IDLE state to exit WOR mode. CC1100 can be set up to signal the MCU that a packet has been received by using the GDO pins. If a packet is received, the MCSM1.RXOFF_MODE will determine the behaviour at the end of the received packet. When the MCU has read the packet, it can put the chip back into SLEEP with the SWOR strobe from the IDLE state. The FIFO will loose its contents in the SLEEP state. The WOR timer has two events, Event 0 and Event 1. In the SLEEP state with WOR activated, reaching Event 0 will turn on the digital regulator and start the crystal oscillator. Event 1 follows Event 0 after a programmed timeout. CC1100 SWRS038D Page 45 of 92 The time between two consecutive Event 0 is programmed with a mantissa value given by WOREVT1.EVENT0 and WOREVT0.EVENT0, and an exponent value set by WORCTRL.WOR_RES. The equation is: WOR RES XOSC Event EVENT f t 5 _ 0 = 750 ⋅ 0 ⋅ 2 ⋅ The Event 1 timeout is programmed with WORCTRL.EVENT1. Figure 19 shows the timing relationship between Event 0 timeout and Event 1 timeout. Figure 19: Event 0 and Event 1 Relationship The time from the CC1100 enters SLEEP state until the next Event0 is programmed to appear (tSLEEP in Figure 19) should be larger than 11.08 ms when using a 26 MHz crystal and 10.67 ms when a 27 MHz crystal is used. If tSLEEP is less than 11.08 (10.67) ms there is a chance that the consecutive Event 0 will occur 750 ⋅128 XOSC f seconds too early. Application Note AN047 [4] explains in detail the theory of operation and the different registers involved when using WOR, as well as highlighting important aspects when using WOR mode. 19.5.1 RC Oscillator and Timing The frequency of the low-power RC oscillator used for the WOR functionality varies with temperature and supply voltage. In order to keep the frequency as accurate as possible, the RC oscillator will be calibrated whenever possible, which is when the XOSC is running and the chip is not in the SLEEP state. When the power and XOSC is enabled, the clock used by the WOR timer is a divided XOSC clock. When the chip goes to the sleep state, the RC oscillator will use the last valid calibration result. The frequency of the RC oscillator is locked to the main crystal frequency divided by 750. In applications where the radio wakes up very often, typically several times every second, it is possible to do the RC oscillator calibration once and then turn off calibration (WORCTRL.RC_CAL=0) to reduce the current consumption. This requires that RC oscillator calibration values are read from registers RCCTRL0_STATUS and RCCTRL1_STATUS and written back to RCCTRL0 and RCCTRL1 respectively. If the RC oscillator calibration is turned off it will have to be manually turned on again if temperature and supply voltage changes. Refer to Application Note AN047 [4] for further details. 19.6 Timing The radio controller controls most of the timing in CC1100, such as synthesizer calibration, PLL lock time, and RX/TX turnaround times. Timing from IDLE to RX and IDLE to TX is constant, dependent on the auto calibration setting. RX/TX and TX/RX turnaround times are constant. The calibration time is constant 18739 clock periods. Table 28 shows timing in crystal clock cycles for key state transitions. Power on time and XOSC start-up times are variable, but within the limits stated in Table 7. Note that in a frequency hopping spread spectrum or a multi-channel protocol the calibration time can be reduced from 721 μs to approximately 150 μs. This is explained in Section 32.2. Description XOSC Periods 26 MHz Crystal IDLE to RX, no calibration 2298 88.4μs IDLE to RX, with calibration ~21037 809μs IDLE to TX/FSTXON, no calibration 2298 88.4μs IDLE to TX/FSTXON, with calibration ~21037 809μs TX to RX switch 560 21.5μs RX to TX switch 250 9.6μs RX or TX to IDLE, no calibration 2 0.1μs RX or TX to IDLE, with calibration ~18739 721μs Manual calibration ~18739 721μs Table 28: State Transition Timing CC1100 SWRS038D Page 46 of 92 19.7 RX Termination Timer CC1100 has optional functions for automatic termination of RX after a programmable time. The main use for this functionality is wake-onradio (WOR), but it may be useful for other applications. The termination timer starts when in RX state. The timeout is programmable with the MCSM2.RX_TIME setting. When the timer expires, the radio controller will check the condition for staying in RX; if the condition is not met, RX will terminate. The programmable conditions are: • MCSM2.RX_TIME_QUAL=0: Continue receive if sync word has been found • MCSM2.RX_TIME_QUAL=1: Continue receive if sync word has been found or preamble quality is above threshold (PQT) If the system can expect the transmission to have started when enabling the receiver, the MCSM2.RX_TIME_RSSI function can be used. The radio controller will then terminate RX if the first valid carrier sense sample indicates no carrier (RSSI below threshold). See Section 17.4 on page 39 for details on Carrier Sense. For ASK/OOK modulation, lack of carrier sense is only considered valid after eight symbol periods. Thus, the MCSM2.RX_TIME_RSSI function can be used in ASK/OOK mode when the distance between “1” symbols is 8 or less. If RX terminates due to no carrier sense when the MCSM2.RX_TIME_RSSI function is used, or if no sync word was found when using the MCSM2.RX_TIME timeout function, the chip will always go back to IDLE if WOR is disabled and back to SLEEP if WOR is enabled. Otherwise, the MCSM1.RXOFF_MODE setting determines the state to go to when RX ends. This means that the chip will not automatically go back to SLEEP once a sync word has been received. It is therefore recommended to always wake up the microcontroller on sync word detection when using WOR mode. This can be done by selecting output signal 6 (see Table 34 on page 56) on one of the programmable GDO output pins, and programming the microcontroller to wake up on an edge-triggered interrupt from this GDO pin. 20 Data FIFO The CC1100 contains two 64 byte FIFOs, one for received data and one for data to be transmitted. The SPI interface is used to read from the RX FIFO and write to the TX FIFO. Section 10.5 contains details on the SPI FIFO access. The FIFO controller will detect overflow in the RX FIFO and underflow in the TX FIFO. When writing to the TX FIFO it is the responsibility of the MCU to avoid TX FIFO overflow. A TX FIFO overflow will result in an error in the TX FIFO content. Likewise, when reading the RX FIFO the MCU must avoid reading the RX FIFO past its empty value, since an RX FIFO underflow will result in an error in the data read out of the RX FIFO. The chip status byte that is available on the SO pin while transferring the SPI header contains the fill grade of the RX FIFO if the access is a read operation and the fill grade of the TX FIFO if the access is a write operation. Section 10.1 on page 26 contains more details on this. The number of bytes in the RX FIFO and TX FIFO can be read from the status registers RXBYTES.NUM_RXBYTES and TXBYTES.NUM_TXBYTES respectively. If a received data byte is written to the RX FIFO at the exact same time as the last byte in the RX FIFO is read over the SPI interface, the RX FIFO pointer is not properly updated and the last read byte is duplicated. To avoid this problem one should never empty the RX FIFO before the last byte of the packet is received. For packet lengths less than 64 bytes it is recommended to wait until the complete packet has been received before reading it out of the RX FIFO. If the packet length is larger than 64 bytes the MCU must determine how many bytes can be read from the RX FIFO (RXBYTES.NUM_RXBYTES-1) and the following software routine can be used: 1. Read RXBYTES.NUM_RXBYTES repeatedly at a rate guaranteed to be at least twice that of which RF bytes are received until the same value is returned twice; store value in n. 2. If n < # of bytes remaining in packet, read n-1 bytes from the RX FIFO. CC1100 SWRS038D Page 47 of 92 3. Repeat steps 1 and 2 until n = # of bytes remaining in packet. 4. Read the remaining bytes from the RX FIFO. The 4-bit FIFOTHR.FIFO_THR setting is used to program threshold points in the FIFOs. Table 29 lists the 16 FIFO_THR settings and the corresponding thresholds for the RX and TX FIFOs. The threshold value is coded in opposite directions for the RX FIFO and TX FIFO. This gives equal margin to the overflow and underflow conditions when the threshold is reached. A signal will assert when the number of bytes in the FIFO is equal to or higher than the programmed threshold. This signal can be viewed on the GDO pins (see Table 34 on page 56). Figure 21 shows the number of bytes in both the RX FIFO and TX FIFO when the threshold signal toggles, in the case of FIFO_THR=13. Figure 20 shows the signal as the respective FIFO is filled above the threshold, and then drained below. 53 54 55 56 57 56 55 54 53 6 7 8 9 10 9 8 7 6 NUM_RXBYTES GDO NUM_TXBYTES GDO Figure 20: FIFO_THR=13 vs. Number of Bytes in FIFO (GDOx_CFG=0x00 in RX and GDOx_CFG=0x02 in TX) FIFO_THR Bytes in TX FIFO Bytes in RX FIFO 0 (0000) 61 4 1 (0001) 57 8 2 (0010) 53 12 3 (0011) 49 16 4 (0100) 45 20 5 (0101) 41 24 6 (0110) 37 28 7 (0111) 33 32 8 (1000) 29 36 9 (1001) 25 40 10 (1010) 21 44 11 (1011) 17 48 12 (1100) 13 52 13 (1101) 9 56 14 (1110) 5 60 15 (1111) 1 64 Table 29: FIFO_THR Settings and the Corresponding FIFO Thresholds 56 bytes 8 bytes Overflow margin Underflow margin FIFO_TH R=13 FIFO_THR=13 RXFIFO TXFIFO Figure 21: Example of FIFOs at Threshold CC1100 SWRS038D Page 48 of 92 21 Frequency Programming The frequency programming in CC1100 is designed to minimize the programming needed in a channel-oriented system. To set up a system with channel numbers, the desired channel spacing is programmed with the MDMCFG0.CHANSPC_M and MDMCFG1.CHANSPC_E registers. The channel spacing registers are mantissa and exponent respectively. The base or start frequency is set by the 24 bit frequency word located in the FREQ2, FREQ1, and FREQ0 registers. This word will typically be set to the centre of the lowest channel frequency that is to be used. The desired channel number is programmed with the 8-bit channel number register, CHANNR.CHAN, which is multiplied by the channel offset. The resultant carrier frequency is given by: ( (( ) _ 2 )) 16 256 _ 2 2 = XOSC ⋅ + ⋅ + ⋅ CHANSPC E− carrier f f FREQ CHAN CHANSPC M With a 26 MHz crystal the maximum channel spacing is 405 kHz. To get e.g. 1 MHz channel spacing one solution is to use 333 kHz channel spacing and select each third channel in CHANNR.CHAN. The preferred IF frequency is programmed with the FSCTRL1.FREQ_IF register. The IF frequency is given by: f fXOSC FREQ IF IF _ 210 = ⋅ Note that the SmartRF® Studio software [7] automatically calculates the optimum FSCTRL1.FREQ_IF register setting based on channel spacing and channel filter bandwidth. If any frequency programming register is altered when the frequency synthesizer is running, the synthesizer may give an undesired response. Hence, the frequency programming should only be updated when the radio is in the IDLE state. 22 VCO The VCO is completely integrated on-chip. 22.1 VCO and PLL Self-Calibration The VCO characteristics will vary with temperature and supply voltage changes, as well as the desired operating frequency. In order to ensure reliable operation, CC1100 includes frequency synthesizer self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel). The number of XOSC cycles for completing the PLL calibration is given in Table 28 on page 45. The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off automatically. This is configured with the MCSM0.FS_AUTOCAL register setting. In manual mode, the calibration is initiated when the SCAL command strobe is activated in the IDLE mode. Note that the calibration values are maintained in SLEEP mode, so the calibration is still valid after waking up from SLEEP mode (unless supply voltage or temperature has changed significantly). To check that the PLL is in lock the user can program register IOCFGx.GDOx_CFG to 0x0A and use the lock detector output available on the GDOx pin as an interrupt for the MCU (x = 0,1, or 2). A positive transition on the GDOx pin means that the PLL is in lock. As an alternative the user can read register FSCAL1. The PLL is in lock if the register content is different from 0x3F. Refer also to the CC1100 Errata Notes [1]. For more robust operation the source code could include a check so that the PLL is re-calibrated until PLL lock is achieved if the PLL does not lock the first time. CC1100 SWRS038D Page 49 of 92 23 Voltage Regulators CC1100 contains several on-chip linear voltage regulators, which generate the supply voltage needed by low-voltage modules. These voltage regulators are invisible to the user, and can be viewed as integral parts of the various modules. The user must however make sure that the absolute maximum ratings and required pin voltages in Table 1 and Table 13 are not exceeded. The voltage regulator for the digital core requires one external decoupling capacitor. Setting the CSn pin low turns on the voltage regulator to the digital core and starts the crystal oscillator. The SO pin on the SPI interface must go low before the first positive edge of SCLK. (setup time is given in Table 16). If the chip is programmed to enter power-down mode, (SPWD strobe issued), the power will be turned off after CSn goes high. The power and crystal oscillator will be turned on again when CSn goes low. The voltage regulator output should only be used for driving the CC1100. 24 Output Power Programming The RF output power level from the device has two levels of programmability, as illustrated in Figure 22. Firstly, the special PATABLE register can hold up to eight user selected output power settings. Secondly, the 3-bit FREND0.PA_POWER value selects the PATABLE entry to use. This two-level functionality provides flexible PA power ramp up and ramp down at the start and end of transmission, as well as ASK modulation shaping. All the PA power settings in the PATABLE from index 0 up to the FREND0.PA_POWER value are used. The power ramping at the start and at the end of a packet can be turned off by setting FREND0.PA_POWER to zero and then program the desired output power to index 0 in the PATABLE. If OOK modulation is used, the logic 0 and logic 1 power levels shall be programmed to index 0 and 1 respectively. Table 30 contains recommended PATABLE settings for various output levels and frequency bands. Using PA settings from 0x61 to 0x6F is not recommended. See Section 10.6 on page 28 for PATABLE programming details. Table 31 contains output power and current consumption for default PATABLE setting (0xC6). PATABLE must be programmed in burst mode if you want to write to other entries than PATABLE[0]. Note that all content of the PATABLE, except for the first byte (index 0) is lost when entering the SLEEP state. 315 MHz 433 MHz 868 MHz 915 MHz Output Power [dBm] Setting Current Consumption, Typ. [mA] Setting Current Consumption, Typ. [mA] Setting Current Consumption, Typ. [mA] Setting Current Consumption, Typ. [mA] -30 0x04 10.6 0x04 11.5 0x03 11.9 0x11 11.8 -20 0x17 11.1 0x17 12.1 0x0D 12.4 0x0D 12.3 -15 0x1D 11.8 0x1C 12.7 0x1C 13.0 0x1C 13.0 -10 0x26 13.0 0x26 14.0 0x34 14.5 0x26 14.3 -5 0x57 12.9 0x57 13.7 0x57 14.1 0x57 13.9 0 0x60 14.8 0x60 15.6 0x8E 16.9 0x8E 16.7 5 0x85 18.1 0x85 19.1 0x85 20.0 0x83 19.9 7 0xCB 22.1 0xC8 24.2 0xCC 25.8 0xC9 25.8 10 0xC2 27.1 0xC0 29.2 0xC3 31.1 0xC0 32.3 Table 30: Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands CC1100 SWRS038D Page 50 of 92 315 MHz 433 MHz 868 MHz 915 MHz Default Power Setting Output Power [dBm] Current Consumption, Typ. [mA] Output Power [dBm] Current Consumption, Typ. [mA] Output Power [dBm] Current Consumption, Typ. [mA] Output Power [dBm] Current Consumption, Typ. [mA] 0xC6 8.7 24.5 7.9 25.2 8.9 28.3 7.9 26.8 Table 31: Output Power and Current Consumption for Default PATABLE Setting 25 Shaping and PA Ramping With ASK modulation, up to eight power settings are used for shaping. The modulator contains a counter that counts up when transmitting a one and down when transmitting a zero. The counter counts at a rate equal to 8 times the symbol rate. The counter saturates at FREND0.PA_POWER and 0 respectively. This counter value is used as an index for a lookup in the power table. Thus, in order to utilize the whole table, FREND0.PA_POWER should be 7 when ASK is active. The shaping of the ASK signal is dependent on the configuration of the PATABLE. Note that the ASK shaping feature is only supported for output power levels up to -1 dBm and only values in the range 0x30–0x3F, together with 0x00 can be used. The same is the case when implementing PA ramping for other modulations formats. Figure 23 shows some examples of ASK shaping. e.g 6 PA_POWER[2:0] in FREND0 register PATABLE(0)[7:0] PATABLE(1)[7:0] PATABLE(2)[7:0] PATABLE(3)[7:0] PATABLE(4)[7:0] PATABLE(5)[7:0] PATABLE(6)[7:0] PATABLE(7)[7:0] Index into PATABLE(7:0) The PA uses this setting. Settings 0 to PA_POWER are used during ramp-up at start of transmission and ramp-down at end of transmission, and for ASK/OOK modulation. The SmartRF® Studio software should be used to obtain optimum PATABLE settings for various output powers. Figure 22: PA_POWER and PATABLE 1 0 0 1 0 1 1 0 Bit Sequence FREND0.PA_POWER = 3 FREND0.PA_POWER = 7 Time PATABLE[0] PATABLE[1] PATABLE[2] PATABLE[3] PATABLE[4] PATABLE[5] PATABLE[6] PATABLE[7] Output Power Figure 23: Shaping of ASK Signal CC1100 SWRS038D Page 51 of 92 Output Power [dBm] PATABLE Setting 315 MHz 433 MHz 868 MHz 915 MHz 0x00 -62.0 -62.0 -57.1 -56.0 0x30 -41.7 -39.0 -33.6 -33.1 0x31 -21.8 -21.7 -21.2 -21.0 0x32 -16.2 -16.1 -16.0 -15.8 0x33 -12.8 -12.7 -12.7 -12.5 0x34 -10.5 -10.4 -10.5 -10.3 0x35 -8.6 -8.5 -8.7 -8.5 0x36 -7.2 -7.1 -7.4 -7.2 0x37 -5.9 -5.8 -6.2 -6.0 0x38 -4.8 -4.9 -5.3 -5.1 0x39 -3.9 -4.0 -4.5 -4.3 0x3A -3.2 -3.3 -3.8 -3.7 0x3B -2.5 -2.7 -3.3 -3.1 0x3C -2.1 -2.3 -2.8 -2.7 0x3D -1.7 -1.9 -2.5 -2.3 0x3E -1.3 -1.6 -2.1 -2.0 0x3F -1.1 -1.3 -1.9 -1.7 Table 32: PATABLE Settings used together with ASK Shaping and PA Ramping Assume working in the 433 MHz and using FSK. The desired output power is -10 dBm. Figure 24 shows how the PATABLE should look like in the two cases where no ramping is used (A) and when PA ramping is being implemented (B). In case A, the PATABLE value is taken from Table 30, while in case B, the values are taken from Table 32. PATABLE[7] = 0x00 PATABLE[6] = 0x00 PATABLE[5] = 0x00 PATABLE[4] = 0x00 PATABLE[3] = 0x00 PATABLE[2] = 0x00 PATABLE[1] = 0x00 PATABLE[0] = 0x26 FREND0.PA_POWER = 0 PATABLE[7] = 0x00 PATABLE[6] = 0x00 PATABLE[5] = 0x34 PATABLE[4] = 0x33 PATABLE[3] = 0x32 PATABLE[2] = 0x31 PATABLE[1] = 0x30 PATABLE[0] = 0x00 FREND0.PA_POWER = 5 A: Output Power = -10 dBm, No PA Ramping B: Output Power = -10 dBm, PA Ramping Figure 24: PA Ramping CC1100 SWRS038D Page 52 of 92 26 Selectivity Figure 25 to Figure 27 show the typical selectivity performance (adjacent and alternate rejection). -10.0 0.0 10.0 20.0 30.0 40.0 50.0 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.4 0.5 Frequency offset [MHz] Selectivity [dB] Figure 25: Typical Selectivity at 1.2 kBaud Data Rate, 868 MHz, 2-FSK, 5.2 kHz Deviation. IF Frequency is 152.3 kHz and the Digital Channel Filter Bandwidth is 58 kHz -20.0 -10.0 0.0 10.0 20.0 30.0 40.0 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.4 0.5 Frequency offset [MHz] Selectivity [dB] Figure 26: Typical Selectivity at 38.4 kBaud Data Rate, 868 MHz, 2-FSK, 20 kHz Deviation. IF Frequency is 152.3 kHz and the Digital Channel Filter Bandwidth is 100 kHz CC1100 SWRS038D Page 53 of 92 -20.0 -10.0 0.0 10.0 20.0 30.0 40.0 50.0 -2.3 1.5 -1.0 -0.8 0.0 0.8 1.0 1.5 2.3 Frequency offset [MHz] Selectivity [dB] Figure 27: Typical Selectivity at 250 kBaud Data Rate, 868 MHz, MSK, IF Frequency is 254 kHz and the Digital Channel Filter Bandwidth is 540 kHz 27 Crystal Oscillator A crystal in the frequency range 26-27 MHz must be connected between the XOSC_Q1 and XOSC_Q2 pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading capacitors (C81 and C101) for the crystal are required. The loading capacitor values depend on the total load capacitance, CL, specified for the crystal. The total load capacitance seen between the crystal terminals should equal CL for the crystal to oscillate at the specified frequency. L parasitic C C C C + + = 81 101 1 1 1 The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Total parasitic capacitance is typically 2.5 pF. The crystal oscillator circuit is shown in Figure 28. Typical component values for different values of CL are given in Table 33. The crystal oscillator is amplitude regulated. This means that a high current is used to start up the oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain approximately 0.4 Vpp signal swing. This ensures a fast start-up, and keeps the drive level to a minimum. The ESR of the crystal should be within the specification in order to ensure a reliable start-up (see Section 4.4 on page 14). The initial tolerance, temperature drift, aging and load pulling should be carefully specified in order to meet the required frequency accuracy in a certain application. XOSC_Q1 XOSC_Q2 XTAL C81 C101 Figure 28: Crystal Oscillator Circuit Component CL = 10 pF CL = 13 pF CL = 16 pF C81 15 pF 22 pF 27 pF C101 15 pF 22 pF 27 pF Table 33: Crystal Oscillator Component Values CC1100 SWRS038D Page 54 of 92 27.1 Reference Signal The chip can alternatively be operated with a reference signal from 26 to 27 MHz instead of a crystal. This input clock can either be a fullswing digital signal (0 V to VDD) or a sine wave of maximum 1 V peak-peak amplitude. The reference signal must be connected to the XOSC_Q1 input. The sine wave must be connected to XOSC_Q1 using a serial capacitor. When using a full-swing digital signal this capacitor can be omitted. The XOSC_Q2 line must be left un-connected. C81 and C101 can be omitted when using a reference signal. 28 External RF Match The balanced RF input and output of CC1100 share two common pins and are designed for a simple, low-cost matching and balun network on the printed circuit board. The receive- and transmit switching at the CC1100 front-end is controlled by a dedicated on-chip function, eliminating the need for an external RX/TXswitch. A few passive external components combined with the internal RX/TX switch/termination circuitry ensures match in both RX and TX mode. Although CC1100 has a balanced RF input/output, the chip can be connected to a single-ended antenna with few external low cost capacitors and inductors. The passive matching/filtering network connected to CC1100 should have the following differential impedance as seen from the RFport (RF_P and RF_N) towards the antenna: Zout 315 MHz = 122 + j31 Ω Zout 433 MHz = 116 + j41 Ω Zout 868/915 MHz = 86.5 + j43 Ω To ensure optimal matching of the CC1100 differential output it is recommended to follow the CC1100EM reference design ([5] or [6]) as closely as possible. Gerber files for the reference designs are available for download from the TI website. 29 PCB Layout Recommendations The top layer should be used for signal routing, and the open areas should be filled with metallization connected to ground using several vias. The area under the chip is used for grounding and shall be connected to the bottom ground plane with several vias. In the CC1100EM reference designs ([5] and [6]) we have placed 5 vias inside the exposed die attached pad. These vias should be “tented” (covered with solder mask) on the component side of the PCB to avoid migration of solder through the vias during the solder reflow process. The solder paste coverage should not be 100%. If it is, out gassing may occur during the reflow process, which may cause defects (splattering, solder balling). Using “tented” vias reduces the solder paste coverage below 100%. See Figure 29 for top solder resist and top paste masks. Each decoupling capacitor should be placed as close as possible to the supply pin it is supposed to decouple. Each decoupling capacitor should be connected to the power line (or power plane) by separate vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the CC1100 supply pin. Supply power filtering is very important. Each decoupling capacitor ground pad should be connected to the ground plane using a separate via. Direct connections between neighboring power pins will increase noise coupling and should be avoided unless absolutely necessary. The external components should ideally be as small as possible (0402 is recommended) and surface mount devices are highly recommended. Please note that components smaller than those specified may have differing characteristics. Precaution should be used when placing the microcontroller in order to avoid noise interfering with the RF circuitry. A CC1100/1150DK Development Kit with a fully assembled CC1100EM Evaluation Module is available. It is strongly advised that this reference layout is followed very closely in order to get the best performance. The schematic, BOM and layout Gerber files are all available from the TI website ([5] and [6]). CC1100 SWRS038D Page 55 of 92 Figure 29: Left: Top Solder Resist Mask (Negative). Right: Top Paste Mask. Circles are Vias 30 General Purpose / Test Output Control Pins The three digital output pins GDO0, GDO1, and GDO2 are general control pins configured with IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, and IOCFG2.GDO3_CFG respectively. Table 34 shows the different signals that can be monitored on the GDO pins. These signals can be used as inputs to the MCU. GDO1 is the same pin as the SO pin on the SPI interface, thus the output programmed on this pin will only be valid when CSn is high. The default value for GDO1 is 3- stated, which is useful when the SPI interface is shared with other devices. The default value for GDO0 is a 135-141 kHz clock output (XOSC frequency divided by 192). Since the XOSC is turned on at poweron- reset, this can be used to clock the MCU in systems with only one crystal. When the MCU is up and running, it can change the clock frequency by writing to IOCFG0.GDO0_CFG. An on-chip analog temperature sensor is enabled by writing the value 128 (0x80) to the IOCFG0 register. The voltage on the GDO0 pin is then proportional to temperature. See Section 4.7 on page 16 for temperature sensor specifications. If the IOCFGx.GDOx_CFG setting is less than 0x20 and IOCFGx_GDOx_INV is 0 (1), the GDO0 and GDO2 pins will be hardwired to 0 (1) and the GDO1 pin will be hardwired to 1 (0) in the SLEEP state. These signals will be hardwired until the CHIP_RDYn signal goes low. If the IOCFGx.GDOx_CFG setting is 0x20 or higher the GDO pins will work as programmed also in SLEEP state. As an example, GDO1 is high impedance in all states if IOCFG1.GDO1_CFG=0x2E. CC1100 SWRS038D Page 56 of 92 GDOx_CFG[5:0] Description 0 (0x00) Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold. De-asserts when RX FIFO is drained below the same threshold. 1 (0x01) Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold or the end of packet is reached. De-asserts when the RX FIFO is empty. 2 (0x02) Associated to the TX FIFO: Asserts when the TX FIFO is filled at or above the TX FIFO threshold. De-asserts when the TX FIFO is below the same threshold. 3 (0x03) Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below theTX FIFO threshold. 4 (0x04) Asserts when the RX FIFO has overflowed. De-asserts when the FIFO has been flushed. 5 (0x05) Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed. 6 (0x06) Asserts when sync word has been sent / received, and de-asserts at the end of the packet. In RX, the pin will de-assert when the optional address check fails or the RX FIFO overflows. In TX the pin will de-assert if the TX FIFO underflows. 7 (0x07) Asserts when a packet has been received with CRC OK. De-asserts when the first byte is read from the RX FIFO. 8 (0x08) Preamble Quality Reached. Asserts when the PQI is above the programmed PQT value. 9 (0x09) Clear channel assessment. High when RSSI level is below threshold (dependent on the current CCA_MODE setting) 10 (0x0A) Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To check for PLL lock the lock detector output should be used as an interrupt for the MCU. 11 (0x0B) Serial Clock. Synchronous to the data in synchronous serial mode. In RX mode, data is set up on the falling edge by CC1100 when GDOx_INV=0. In TX mode, data is sampled by CC1100 on the rising edge of the serial clock when GDOx_INV=0. 12 (0x0C) Serial Synchronous Data Output. Used for synchronous serial mode. 13 (0x0D) Serial Data Output. Used for asynchronous serial mode. 14 (0x0E) Carrier sense. High if RSSI level is above threshold. 15 (0x0F) CRC_OK. The last CRC comparison matched. Cleared when entering/restarting RX mode. 16 (0x10) Reserved – used for test. 17 (0x11) Reserved – used for test. 18 (0x12) Reserved – used for test. 19 (0x13) Reserved – used for test. 20 (0x14) Reserved – used for test. 21 (0x15) Reserved – used for test. 22 (0x16) RX_HARD_DATA[1]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output. 23 (0x17) RX_HARD_DATA[0]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output. 24 (0x18) Reserved – used for test. 25 (0x19) Reserved – used for test. 26 (0x1A) Reserved – used for test. 27 (0x1B) PA_PD. Note: PA_PD will have the same signal level in SLEEP and TX states. To control an external PA or RX/TX switch in applications where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F instead. 28 (0x1C) LNA_PD. Note: LNA_PD will have the same signal level in SLEEP and RX states. To control an external LNA or RX/TX switch in applications where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F instead. 29 (0x1D) RX_SYMBOL_TICK. Can be used together with RX_HARD_DATA for alternative serial RX output. 30 (0x1E) Reserved – used for test. 31 (0x1F) Reserved – used for test. 32 (0x20) Reserved – used for test. 33 (0x21) Reserved – used for test. 34 (0x22) Reserved – used for test. 35 (0x23) Reserved – used for test. 36 (0x24) WOR_EVNT0 37 (0x25) WOR_EVNT1 38 (0x26) Reserved – used for test. 39 (0x27) CLK_32k 40 (0x28) Reserved – used for test. 41 (0x29) CHIP_RDYn 42 (0x2A) Reserved – used for test. 43 (0x2B) XOSC_STABLE 44 (0x2C) Reserved – used for test. 45 (0x2D) GDO0_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data). 46 (0x2E) High impedance (3-state) 47 (0x2F) HW to 0 (HW1 achieved by setting GDOx_INV=1). Can be used to control an external LNA/PA or RX/TX switch. 48 (0x30) CLK_XOSC/1 49 (0x31) CLK_XOSC/1.5 50 (0x32) CLK_XOSC/2 51 (0x33) CLK_XOSC/3 52 (0x34) CLK_XOSC/4 53 (0x35) CLK_XOSC/6 54 (0x36) CLK_XOSC/8 55 (0x37) CLK_XOSC/12 56 (0x38) CLK_XOSC/16 57 (0x39) CLK_XOSC/24 58 (0x3A) CLK_XOSC/32 59 (0x3B) CLK_XOSC/48 60 (0x3C) CLK_XOSC/64 61 (0x3D) CLK_XOSC/96 62 (0x3E) CLK_XOSC/128 63 (0x3F) CLK_XOSC/192 Note: There are 3 GDO pins, but only one CLK_XOSC/n can be selected as an output at any time. If CLK_XOSC/n is to be monitored on one of the GDO pins, the other two GDO pins must be configured to values less than 0x30. The GDO0 default value is CLK_XOSC/192. To optimize rf performance, these signal should not be used while the radio is in RX or TX mode. Table 34: GDOx Signal Selection (x = 0, 1, or 2) CC1100 SWRS038D Page 57 of 92 31 Asynchronous and Synchronous Serial Operation Several features and modes of operation have been included in the CC1100 to provide backward compatibility with previous Chipcon products and other existing RF communication systems. For new systems, it is recommended to use the built-in packet handling features, as they can give more robust communication, significantly offload the microcontroller, and simplify software development. 31.1 Asynchronous Operation For backward compatibility with systems already using the asynchronous data transfer from other Chipcon products, asynchronous transfer is also included in CC1100. When asynchronous transfer is enabled, several of the support mechanisms for the MCU that are included in CC1100 will be disabled, such as packet handling hardware, buffering in the FIFO, and so on. The asynchronous transfer mode does not allow the use of the data whitener, interleaver, and FEC, and it is not possible to use Manchester encoding. Note that MSK is not supported for asynchronous transfer. Setting PKTCTRL0.PKT_FORMAT to 3 enables asynchronous serial mode. In TX, the GDO0 pin is used for data input (TX data). Data output can be on GDO0, GDO1, or GDO2. This is set by the IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG and IOCFG2.GDO2_CFG fields. The CC1100 modulator samples the level of the asynchronous input 8 times faster than the programmed data rate. The timing requirement for the asynchronous stream is that the error in the bit period must be less than one eighth of the programmed data rate. 31.2 Synchronous Serial Operation Setting PKTCTRL0.PKT_FORMAT to 1 enables synchronous serial mode. In the synchronous serial mode, data is transferred on a two wire serial interface. The CC1100 provides a clock that is used to set up new data on the data input line or sample data on the data output line. Data input (TX data) is the GDO0 pin. This pin will automatically be configured as an input when TX is active. The data output pin can be any of the GDO pins; this is set by the IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, and IOCFG2.GDO2_CFG fields. Preamble and sync word insertion/detection may or may not be active, dependent on the sync mode set by the MDMCFG2.SYNC_MODE. If preamble and sync word is disabled, all other packet handler features and FEC should also be disabled. The MCU must then handle preamble and sync word insertion and detection in software. If preamble and sync word insertion/detection is left on, all packet handling features and FEC can be used. One exception is that the address filtering feature is unavailable in synchronous serial mode. When using the packet handling features in synchronous serial mode, the CC1100 will insert and detect the preamble and sync word and the MCU will only provide/get the data payload. This is equivalent to the recommended FIFO operation mode. 32 System Considerations and Guidelines 32.1 SRD Regulations International regulations and national laws regulate the use of radio receivers and transmitters. Short Range Devices (SRDs) for license free operation below 1 GHz are usually operated in the 433 MHz, 868 MHz or 915 MHz frequency bands. The CC1100 is specifically designed for such use with its 300 - 348 MHz, 400 - 464 MHz, and 800 - 928 MHz operating ranges. The most important regulations when using the CC1100 in the 433 MHz, 868 MHz, or 915 MHz frequency bands are EN 300 220 (Europe) and FCC CFR47 part 15 (USA). A summary of the most important aspects of these regulations can be found in Application Note AN001 [2]. Please note that compliance with regulations is dependent on complete system performance. It is the customer’s responsibility to ensure that the system complies with regulations. CC1100 SWRS038D Page 58 of 92 32.2 Frequency Hopping and Multi- Channel Systems The 433 MHz, 868 MHz, or 915 MHz bands are shared by many systems both in industrial, office, and home environments. It is therefore recommended to use frequency hopping spread spectrum (FHSS) or a multi-channel protocol because the frequency diversity makes the system more robust with respect to interference from other systems operating in the same frequency band. FHSS also combats multipath fading. CC1100 is highly suited for FHSS or multichannel systems due to its agile frequency synthesizer and effective communication interface. Using the packet handling support and data buffering is also beneficial in such systems as these features will significantly offload the host controller. Charge pump current, VCO current, and VCO capacitance array calibration data is required for each frequency when implementing frequency hopping for CC1100. There are 3 ways of obtaining the calibration data from the chip: 1) Frequency hopping with calibration for each hop. The PLL calibration time is approximately 720 μs. The blanking interval between each frequency hop is then approximately 810 us. 2) Fast frequency hopping without calibration for each hop can be done by calibrating each frequency at startup and saving the resulting FSCAL3, FSCAL2, and FSCAL1 register values in MCU memory. Between each frequency hop, the calibration process can then be replaced by writing the FSCAL3, FSCAL2and FSCAL1 register values corresponding to the next RF frequency. The PLL turn on time is approximately 90 μs. The blanking interval between each frequency hop is then approximately 90 us. The VCO current calibration result available in FSCAL2 is not dependent on the RF frequency. Neither is the charge pump current calibration result available in FSCAL3. The same value can therefore be used for all frequencies. 3) Run calibration on a single frequency at startup. Next write 0 to FSCAL3[5:4] to disable the charge pump calibration. After writing to FSCAL3[5:4] strobe SRX (or STX) with MCSM0.FS_AUTOCAL=1 for each new frequency hop. That is, VCO current and VCO capacitance calibration is done but not charge pump current calibration. When charge pump current calibration is disabled the calibration time is reduced from approximately 720 μs to approximately 150 μs. The blanking interval between each frequency hop is then approximately 240 us. There is a trade off between blanking time and memory space needed for storing calibration data in non-volatile memory. Solution 2) above gives the shortest blanking interval, but requires more memory space to store calibration values. Solution 3) gives approximately 570 μs smaller blanking interval than solution 1). Note that the recommended settings for TEST0.VCO_SEL_CAL_EN will change with frequency. This means that one should always use SmartRF® Studio [7] to get the correct settings for a specific frequency before doing a calibration, regardless of which calibration method is being used. It must be noted that the TESTn registers (n = 0, 1, or 2) content is not retained in SLEEP state, and thus it is necessary to re-write these registers when returning from the SLEEP state. 32.3 Wideband Modulation not Using Spread Spectrum Digital modulation systems under FFC part 15.247 includes 2-FSK and GFSK modulation. A maximum peak output power of 1W (+30 dBm) is allowed if the 6 dB bandwidth of the modulated signal exceeds 500 kHz. In addition, the peak power spectral density conducted to the antenna shall not be greater than +8 dBm in any 3 kHz band. Operating at high data rates and frequency separation, the CC1100 is suited for systems targeting compliance with digital modulation system as defined by FFC part 15.247. An external power amplifier is needed to increase the output above +10 dBm. 32.4 Data Burst Transmissions The high maximum data rate of CC1100 opens up for burst transmissions. A low average data rate link (e.g. 10 kBaud), can be realized using a higher over-the-air data rate. Buffering the data and transmitting in bursts at high data rate (e.g. 500 kBaud) will reduce the time in active mode, and hence also reduce the average current consumption significantly. Reducing the time in active mode will reduce the likelihood of collisions with other systems in the same frequency range. CC1100 SWRS038D Page 59 of 92 32.5 Continuous Transmissions In data streaming applications the CC1100 opens up for continuous transmissions at 500 kBaud effective data rate. As the modulation is done with a closed loop PLL, there is no limitation in the length of a transmission (open loop modulation used in some transceivers often prevents this kind of continuous data streaming and reduces the effective data rate). 32.6 Crystal Drift Compensation The CC1100 has a very fine frequency resolution (see Table 9). This feature can be used to compensate for frequency offset and drift. The frequency offset between an ‘external’ transmitter and the receiver is measured in the CC1100 and can be read back from the FREQEST status register as described in Section 14.1. The measured frequency offset can be used to calibrate the frequency using the ‘external’ transmitter as the reference. That is, the received signal of the device will match the receiver’s channel filter better. In the same way the centre frequency of the transmitted signal will match the ‘external’ transmitter’s signal. 32.7 Spectrum Efficient Modulation CC1100 also has the possibility to use Gaussian shaped 2-FSK (GFSK). This spectrum-shaping feature improves adjacent channel power (ACP) and occupied bandwidth. In ‘true’ 2-FSK systems with abrupt frequency shifting, the spectrum is inherently broad. By making the frequency shift ‘softer’, the spectrum can be made significantly narrower. Thus, higher data rates can be transmitted in the same bandwidth using GFSK. 32.8 Low Cost Systems As the CC1100 provides 500 kBaud multichannel performance without any external filters, a very low cost system can be made. A differential antenna will eliminate the need for a balun, and the DC biasing can be achieved in the antenna topology, see Figure 3 and Figure 4. A HC-49 type SMD crystal is used in the CC1100EM reference designs ([5] and [6]). Note that the crystal package strongly influences the price. In a size constrained PCB design a smaller, but more expensive, crystal may be used. 32.9 Battery Operated Systems In low power applications, the SLEEP state with the crystal oscillator core switched off should be used when the CC1100 is not active. It is possible to leave the crystal oscillator core running in the SLEEP state if start-up time is critical. The WOR functionality should be used in low power applications. 32.10 Increasing Output Power In some applications it may be necessary to extend the link range. Adding an external power amplifier is the most effective way of doing this. The power amplifier should be inserted between the antenna and the balun, and two T/R switches are needed to disconnect the PA in RX mode. See Figure 30. Figure 30: Block Diagram of CC1100 Usage with External Power Amplifier Balun CC1100 Filter Antenna T/R switch T/R switch PA CC1100 SWRS038D Page 60 of 92 33 Configuration Registers The configuration of CC1100 is done by programming 8-bit registers. The optimum configuration data based on selected system parameters are most easily found by using the SmartRF® Studio software [7]. Complete descriptions of the registers are given in the following tables. After chip reset, all the registers have default values as shown in the tables. The optimum register setting might differ from the default value. After a reset all registers that shall be different from the default value therefore needs to be programmed through the SPI interface. There are 13 command strobe registers, listed in Table 35. Accessing these registers will initiate the change of an internal state or mode. There are 47 normal 8-bit configuration registers, listed in Table 36. Many of these registers are for test purposes only, and need not be written for normal operation of CC1100. There are also 12 Status registers, which are listed in Table 37. These registers, which are read-only, contain information about the status of CC1100. The two FIFOs are accessed through one 8-bit register. Write operations write to the TX FIFO, while read operations read from the RX FIFO. During the header byte transfer and while writing data to a register or the TX FIFO, a status byte is returned on the SO line. This status byte is described in Table 17 on page 26. Table 38 summarizes the SPI address space. The address to use is given by adding the base address to the left and the burst and read/write bits on the top. Note that the burst bit has different meaning for base addresses above and below 0x2F. Address Strobe Name Description 0x30 SRES Reset chip. 0x31 SFSTXON Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). If in RX (with CCA): Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround). 0x32 SXOFF Turn off crystal oscillator. 0x33 SCAL Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without setting manual calibration mode (MCSM0.FS_AUTOCAL=0) 0x34 SRX Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1. 0x35 STX In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled: Only go to TX if channel is clear. 0x36 SIDLE Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable. 0x38 SWOR Start automatic RX polling sequence (Wake-on-Radio) as described in Section 19.5 if WORCTRL.RC_PD=0. 0x39 SPWD Enter power down mode when CSn goes high. 0x3A SFRX Flush the RX FIFO buffer. Only issue SFRX in IDLE or, RXFIFO_OVERFLOW states. 0x3B SFTX Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states. 0x3C SWORRST Reset real time clock to Event1 value. 0x3D SNOP No operation. May be used to get access to the chip status byte. Table 35: Command Strobes CC1100 SWRS038D Page 61 of 92 Address Register Description Preserved in SLEEP State Details on Page Number 0x00 IOCFG2 GDO2 output pin configuration Yes 64 0x01 IOCFG1 GDO1 output pin configuration Yes 64 0x02 IOCFG0 GDO0 output pin configuration Yes 64 0x03 FIFOTHR RX FIFO and TX FIFO thresholds Yes 65 0x04 SYNC1 Sync word, high byte Yes 65 0x05 SYNC0 Sync word, low byte Yes 65 0x06 PKTLEN Packet length Yes 65 0x07 PKTCTRL1 Packet automation control Yes 66 0x08 PKTCTRL0 Packet automation control Yes 67 0x09 ADDR Device address Yes 67 0x0A CHANNR Channel number Yes 67 0x0B FSCTRL1 Frequency synthesizer control Yes 68 0x0C FSCTRL0 Frequency synthesizer control Yes 68 0x0D FREQ2 Frequency control word, high byte Yes 68 0x0E FREQ1 Frequency control word, middle byte Yes 68 0x0F FREQ0 Frequency control word, low byte Yes 68 0x10 MDMCFG4 Modem configuration Yes 69 0x11 MDMCFG3 Modem configuration Yes 69 0x12 MDMCFG2 Modem configuration Yes 70 0x13 MDMCFG1 Modem configuration Yes 71 0x14 MDMCFG0 Modem configuration Yes 71 0x15 DEVIATN Modem deviation setting Yes 72 0x16 MCSM2 Main Radio Control State Machine configuration Yes 73 0x17 MCSM1 Main Radio Control State Machine configuration Yes 74 0x18 MCSM0 Main Radio Control State Machine configuration Yes 75 0x19 FOCCFG Frequency Offset Compensation configuration Yes 76 0x1A BSCFG Bit Synchronization configuration Yes 77 0x1B AGCTRL2 AGC control Yes 78 0x1C AGCTRL1 AGC control Yes 79 0x1D AGCTRL0 AGC control Yes 80 0x1E WOREVT1 High byte Event 0 timeout Yes 80 0x1F WOREVT0 Low byte Event 0 timeout Yes 81 0x20 WORCTRL Wake On Radio control Yes 81 0x21 FREND1 Front end RX configuration Yes 82 0x22 FREND0 Front end TX configuration Yes 82 0x23 FSCAL3 Frequency synthesizer calibration Yes 82 0x24 FSCAL2 Frequency synthesizer calibration Yes 83 0x25 FSCAL1 Frequency synthesizer calibration Yes 83 0x26 FSCAL0 Frequency synthesizer calibration Yes 83 0x27 RCCTRL1 RC oscillator configuration Yes 83 0x28 RCCTRL0 RC oscillator configuration Yes 83 0x29 FSTEST Frequency synthesizer calibration control No 84 0x2A PTEST Production test No 84 0x2B AGCTEST AGC test No 84 0x2C TEST2 Various test settings No 84 0x2D TEST1 Various test settings No 84 0x2E TEST0 Various test settings No 84 Table 36: Configuration Registers Overview CC1100 SWRS038D Page 62 of 92 Address Register Description Details on page number 0x30 (0xF0) PARTNUM Part number for CC1100 85 0x31 (0xF1) VERSION Current version number 85 0x32 (0xF2) FREQEST Frequency Offset Estimate 85 0x33 (0xF3) LQI Demodulator estimate for Link Quality 85 0x34 (0xF4) RSSI Received signal strength indication 85 0x35 (0xF5) MARCSTATE Control state machine state 86 0x36 (0xF6) WORTIME1 High byte of WOR timer 86 0x37 (0xF7) WORTIME0 Low byte of WOR timer 86 0x38 (0xF8) PKTSTATUS Current GDOx status and packet status 87 0x39 (0xF9) VCO_VC_DAC Current setting from PLL calibration module 87 0x3A (0xFA) TXBYTES Underflow and number of bytes in the TX FIFO 87 0x3B (0xFB) RXBYTES Overflow and number of bytes in the RX FIFO 87 0x3C (0xFC) RCCTRL1_STATUS Last RC oscillator calibration result 87 0x3D (0xFD) RCCTRL0_STATUS Last RC oscillator calibration result 88 Table 37: Status Registers Overview CC1100 SWRS038D Page 63 of 92 Write Read Single Byte Burst Single Byte Burst +0x00 +0x40 +0x80 +0xC0 0x00 IOCFG2 0x01 IOCFG1 0x02 IOCFG0 0x03 FIFOTHR 0x04 SYNC1 0x05 SYNC0 0x06 PKTLEN 0x07 PKTCTRL1 0x08 PKTCTRL0 0x09 ADDR 0x0A CHANNR 0x0B FSCTRL1 0x0C FSCTRL0 0x0D FREQ2 0x0E FREQ1 0x0F FREQ0 0x10 MDMCFG4 0x11 MDMCFG3 0x12 MDMCFG2 0x13 MDMCFG1 0x14 MDMCFG0 0x15 DEVIATN 0x16 MCSM2 0x17 MCSM1 0x18 MCSM0 0x19 FOCCFG 0x1A BSCFG 0x1B AGCCTRL2 0x1C AGCCTRL1 0x1D AGCCTRL0 0x1E WOREVT1 0x1F WOREVT0 0x20 WORCTRL 0x21 FREND1 0x22 FREND0 0x23 FSCAL3 0x24 FSCAL2 0x25 FSCAL1 0x26 FSCAL0 0x27 RCCTRL1 0x28 RCCTRL0 0x29 FSTEST 0x2A PTEST 0x2B AGCTEST 0x2C TEST2 0x2D TEST1 0x2E TEST0 0x2F R/W configuration registers, burst access possible 0x30 SRES SRES PARTNUM 0x31 SFSTXON SFSTXON VERSION 0x32 SXOFF SXOFF FREQEST 0x33 SCAL SCAL LQI 0x34 SRX SRX RSSI 0x35 STX STX MARCSTATE 0x36 SIDLE SIDLE WORTIME1 0x37 WORTIME0 0x38 SWOR SWOR PKTSTATUS 0x39 SPWD SPWD VCO_VC_DAC 0x3A SFRX SFRX TXBYTES 0x3B SFTX SFTX RXBYTES 0x3C SWORRST SWORRST RCCTRL1_STATUS 0x3D SNOP SNOP RCCTRL0_STATUS 0x3E PATABLE PATABLE PATABLE PATABLE 0x3F TX FIFO TX FIFO RX FIFO RX FIFO Command Strobes, Status registers (read only) and multi byte registers Table 38: SPI Address Space CC1100 SWRS038D Page 64 of 92 33.1 Configuration Register Details – Registers with preserved values in SLEEP state 0x00: IOCFG2 – GDO2 Output Pin Configuration Bit Field Name Reset R/W Description 7 Reserved R0 6 GDO2_INV 0 R/W Invert output, i.e. select active low (1) / high (0) 5:0 GDO2_CFG[5:0] 41 (0x29) R/W Default is CHP_RDYn (See Table 34 on page 56). 0x01: IOCFG1 – GDO1 Output Pin Configuration Bit Field Name Reset R/W Description 7 GDO_DS 0 R/W Set high (1) or low (0) output drive strength on the GDO pins. 6 GDO1_INV 0 R/W Invert output, i.e. select active low (1) / high (0) 5:0 GDO1_CFG[5:0] 46 (0x2E) R/W Default is 3-state (See Table 34 on page 56). 0x02: IOCFG0 – GDO0 Output Pin Configuration Bit Field Name Reset R/W Description 7 TEMP_SENSOR_ENABLE 0 R/W Enable analog temperature sensor. Write 0 in all other register bits when using temperature sensor. 6 GDO0_INV 0 R/W Invert output, i.e. select active low (1) / high (0) 5:0 GDO0_CFG[5:0] 63 (0x3F) R/W Default is CLK_XOSC/192 (See Table 34 on page 56). It is recommended to disable the clock output in initialization, in order to optimize RF performance. CC1100 SWRS038D Page 65 of 92 0x03: FIFOTHR – RX FIFO and TX FIFO Thresholds Bit Field Name Reset R/W Description 7:4 Reserved 0 R/W Write 0 for compatibility with possible future extensions 3:0 FIFO_THR[3:0] 7 (0111) R/W Set the threshold for the TX FIFO and RX FIFO. The threshold is exceeded when the number of bytes in the FIFO is equal to or higher than the threshold value. Setting Bytes in TX FIFO Bytes in RX FIFO 0 (0000) 61 4 1 (0001) 57 8 2 (0010) 53 12 3 (0011) 49 16 4 (0100) 45 20 5 (0101) 41 24 6 (0110) 37 28 7 (0111) 33 32 8 (1000) 29 36 9 (1001) 25 40 10 (1010) 21 44 11 (1011) 17 48 12 (1100) 13 52 13 (1101) 9 56 14 (1110) 5 60 15 (1111) 1 64 0x04: SYNC1 – Sync Word, High Byte Bit Field Name Reset R/W Description 7:0 SYNC[15:8] 211 (0xD3) R/W 8 MSB of 16-bit sync word 0x05: SYNC0 – Sync Word, Low Byte Bit Field Name Reset R/W Description 7:0 SYNC[7:0] 145 (0x91) R/W 8 LSB of 16-bit sync word 0x06: PKTLEN – Packet Length Bit Field Name Reset R/W Description 7:0 PACKET_LENGTH 255 (0xFF) R/W Indicates the packet length when fixed packet length mode is enabled. If variable packet length mode is used, this value indicates the maximum packet length allowed. CC1100 SWRS038D Page 66 of 92 0x07: PKTCTRL1 – Packet Automation Control Bit Field Name Reset R/W Description 7:5 PQT[2:0] 0 (0x00) R/W Preamble quality estimator threshold. The preamble quality estimator increases an internal counter by one each time a bit is received that is different from the previous bit, and decreases the counter by 8 each time a bit is received that is the same as the last bit. A threshold of 4·PQT for this counter is used to gate sync word detection. When PQT=0 a sync word is always accepted. 4 Reserved 0 R0 3 CRC_AUTOFLUSH 0 R/W Enable automatic flush of RX FIFO when CRC in not OK. This requires that only one packet is in the RXIFIFO and that packet length is limited to the RX FIFO size. 2 APPEND_STATUS 1 R/W When enabled, two status bytes will be appended to the payload of the packet. The status bytes contain RSSI and LQI values, as well as CRC OK. 1:0 ADR_CHK[1:0] 0 (00) R/W Controls address check configuration of received packages. Setting Address check configuration 0 (00) No address check 1 (01) Address check, no broadcast 2 (10) Address check and 0 (0x00) broadcast 3 (11) Address check and 0 (0x00) and 255 (0xFF) broadcast CC1100 SWRS038D Page 67 of 92 0x08: PKTCTRL0 – Packet Automation Control Bit Field Name Reset R/W Description 7 Reserved R0 6 WHITE_DATA 1 R/W Turn data whitening on / off 0: Whitening off 1: Whitening on 5:4 PKT_FORMAT[1:0] 0 (00) R/W Format of RX and TX data Setting Packet format 0 (00) Normal mode, use FIFOs for RX and TX 1 (01) Synchronous serial mode, used for backwards compatibility. Data in on GDO0 2 (10) Random TX mode; sends random data using PN9 generator. Used for test. Works as normal mode, setting 0 (00), in RX. 3 (11) Asynchronous serial mode. Data in on GDO0 and Data out on either of the GDO0 pins 3 Reserved 0 R0 2 CRC_EN 1 R/W 1: CRC calculation in TX and CRC check in RX enabled 0: CRC disabled for TX and RX 1:0 LENGTH_CONFIG[1:0] 1 (01) R/W Configure the packet length Setting Packet length configuration 0 (00) Fixed packet length mode. Length configured in PKTLEN register 1 (01) Variable packet length mode. Packet length configured by the first byte after sync word 2 (10) Infinite packet length mode 3 (11) Reserved 0x09: ADDR – Device Address Bit Field Name Reset R/W Description 7:0 DEVICE_ADDR[7:0] 0 (0x00) R/W Address used for packet filtration. Optional broadcast addresses are 0 (0x00) and 255 (0xFF). 0x0A: CHANNR – Channel Number Bit Field Name Reset R/W Description 7:0 CHAN[7:0] 0 (0x00) R/W The 8-bit unsigned channel number, which is multiplied by the channel spacing setting and added to the base frequency. CC1100 SWRS038D Page 68 of 92 0x0B: FSCTRL1 – Frequency Synthesizer Control Bit Field Name Reset R/W Description 7:5 Reserved R0 4:0 FREQ_IF[4:0] 15 (0x0F) R/W The desired IF frequency to employ in RX. Subtracted from FS base frequency in RX and controls the digital complex mixer in the demodulator. f f XOSC FREQ IF IF _ 210 = ⋅ The default value gives an IF frequency of 381kHz, assuming a 26.0 MHz crystal. 0x0C: FSCTRL0 – Frequency Synthesizer Control Bit Field Name Reset R/W Description 7:0 FREQOFF[7:0] 0 (0x00) R/W Frequency offset added to the base frequency before being used by the frequency synthesizer. (2s-complement). Resolution is FXTAL/214 (1.59kHz-1.65kHz); range is ±202 kHz to ±210 kHz, dependent of XTAL frequency. 0x0D: FREQ2 – Frequency Control Word, High Byte Bit Field Name Reset R/W Description 7:6 FREQ[23:22] 0 (00) R FREQ[23:22] is always 0 (the FREQ2 register is less than 36 with 26-27 MHz crystal) 5:0 FREQ[21:16] 30 (0x1E) R/W FREQ[23:22] is the base frequency for the frequency synthesiser in increments of FXOSC/216. [23 : 0] 216 f f XOSC FREQ carrier = ⋅ 0x0E: FREQ1 – Frequency Control Word, Middle Byte Bit Field Name Reset R/W Description 7:0 FREQ[15:8] 196 (0xC4) R/W Ref. FREQ2 register 0x0F: FREQ0 – Frequency Control Word, Low Byte Bit Field Name Reset R/W Description 7:0 FREQ[7:0] 236 (0xEC) R/W Ref. FREQ2 register CC1100 SWRS038D Page 69 of 92 0x10: MDMCFG4 – Modem Configuration Bit Field Name Reset R/W Description 7:6 CHANBW_E[1:0] 2 (0x02) R/W 5:4 CHANBW_M[1:0] 0 (0x00) R/W Sets the decimation ratio for the delta-sigma ADC input stream and thus the channel bandwidth. CHANBW E XOSC channel CHANBW M BW f 8 ⋅ (4 + _ )·2 _ = The default values give 203 kHz channel filter bandwidth, assuming a 26.0 MHz crystal. 3:0 DRATE_E[3:0] 12 (0x0C) R/W The exponent of the user specified symbol rate 0x11: MDMCFG3 – Modem Configuration Bit Field Name Reset R/W Description 7:0 DRATE_M[7:0] 34 (0x22) R/W The mantissa of the user specified symbol rate. The symbol rate is configured using an unsigned, floating-point number with 9-bit mantissa and 4-bit exponent. The 9th bit is a hidden ‘1’. The resulting data rate is: ( ) XOSC DRATE E DATA R = + DRATE M ⋅ ⋅ f 28 _ 2 256 _ 2 The default values give a data rate of 115.051 kBaud (closest setting to 115.2 kBaud), assuming a 26.0 MHz crystal. CC1100 SWRS038D Page 70 of 92 0x12: MDMCFG2 – Modem Configuration Bit Field Name Reset R/W Description 7 DEM_DCFILT_OFF 0 R/W Disable digital DC blocking filter before demodulator. 0 = Enable (better sensitivity) 1 = Disable (current optimized). Only for data rates ≤ 250 kBaud The recommended IF frequency changes when the DC blocking is disabled. Please use SmartRF® Studio [7] to calculate correct register setting. 6:4 MOD_FORMAT[2:0] 0 (000) R/W The modulation format of the radio signal Setting Modulation format 0 (000) 2-FSK 1 (001) GFSK 2 (010) - 3 (011) ASK/OOK 4 (100) - 5 (101) - 6 (110) - 7 (111) MSK ASK is only supported for output powers up to -1 dBm MSK is only supported for datarates above 26 kBaud 3 MANCHESTER_EN 0 R/W Enables Manchester encoding/decoding. 0 = Disable 1 = Enable 2:0 SYNC_MODE[2:0] 2 (010) R/W Combined sync-word qualifier mode. The values 0 (000) and 4 (100) disables preamble and sync word transmission in TX and preamble and sync word detection in RX. The values 1 (001), 2 (010), 5 (101) and 6 (110) enables 16-bit sync word transmission in TX and 16-bits sync word detection in RX. Only 15 of 16 bits need to match in RX when using setting 1 (001) or 5 (101). The values 3 (011) and 7 (111) enables repeated sync word transmission in TX and 32-bits sync word detection in RX (only 30 of 32 bits need to match). Setting Sync-word qualifier mode 0 (000) No preamble/sync 1 (001) 15/16 sync word bits detected 2 (010) 16/16 sync word bits detected 3 (011) 30/32 sync word bits detected 4 (100) No preamble/sync, carrier-sense above threshold 5 (101) 15/16 + carrier-sense above threshold 6 (110) 16/16 + carrier-sense above threshold 7 (111) 30/32 + carrier-sense above threshold CC1100 SWRS038D Page 71 of 92 0x13: MDMCFG1– Modem Configuration Bit Field Name Reset R/W Description 7 FEC_EN 0 R/W Enable Forward Error Correction (FEC) with interleaving for packet payload 0 = Disable 1 = Enable (Only supported for fixed packet length mode, i.e. PKTCTRL0.LENGTH_CONFIG=0) 6:4 NUM_PREAMBLE[2:0] 2 (010) R/W Sets the minimum number of preamble bytes to be transmitted Setting Number of preamble bytes 0 (000) 2 1 (001) 3 2 (010) 4 3 (011) 6 4 (100) 8 5 (101) 12 6 (110) 16 7 (111) 24 3:2 Reserved R0 1:0 CHANSPC_E[1:0] 2 (10) R/W 2 bit exponent of channel spacing 0x14: MDMCFG0– Modem Configuration Bit Field Name Reset R/W Description 7:0 CHANSPC_M[7:0] 248 (0xF8) R/W 8-bit mantissa of channel spacing. The channel spacing is multiplied by the channel number CHAN and added to the base frequency. It is unsigned and has the format: XOSC ( ) CHANSPC E CHANNEL f f CHANSPC M _ 18 256 _ 2 2 Δ = ⋅ + ⋅ The default values give 199.951 kHz channel spacing (the closest setting to 200 kHz), assuming 26.0 MHz crystal frequency. CC1100 SWRS038D Page 72 of 92 0x15: DEVIATN – Modem Deviation Setting Bit Field Name Reset R/W Description 7 Reserved R0 6:4 DEVIATION_E[2:0] 4 (0x04) R/W Deviation exponent 3 Reserved R0 2:0 DEVIATION_M[2:0] 7 (111) R/W When MSK modulation is enabled: Sets fraction of symbol period used for phase change. Refer to the SmartRF® Studio software [7] for correct deviation setting when using MSK. When 2-FSK/GFSK modulation is enabled: Deviation mantissa, interpreted as a 4-bit value with MSB implicit 1. The resulting frequency deviation is given by: xosc DEVIATION E dev f f DEVIATION M _ 17 (8 _ ) 2 2 = ⋅ + ⋅ The default values give ±47.607 kHz deviation, assuming 26.0 MHz crystal frequency. CC1100 SWRS038D Page 73 of 92 0x16: MCSM2 – Main Radio Control State Machine Configuration Bit Field Name Reset R/W Description 7:5 Reserved R0 Reserved 4 RX_TIME_RSSI 0 R/W Direct RX termination based on RSSI measurement (carrier sense). For ASK/OOK modulation, RX times out if there is no carrier sense in the first 8 symbol periods. 3 RX_TIME_QUAL 0 R/W When the RX_TIME timer expires, the chip checks if sync word is found when RX_TIME_QUAL=0, or either sync word is found or PQI is set when RX_TIME_QUAL=1. RX_TIME[2:0] 7 (111) R/W Timeout for sync word search in RX for both WOR mode and normal RX operation. The timeout is relative to the programmed EVENT0 timeout. 2:0 The RX timeout in μs is given by EVENT0·C(RX_TIME, WOR_RES) ·26/X, where C is given by the table below and X is the crystal oscillator frequency in MHz: Setting WOR_RES = 0 WOR_RES = 1 WOR_RES = 2 WOR_RES = 3 0 (000) 3.6058 18.0288 32.4519 46.8750 1 (001) 1.8029 9.0144 16.2260 23.4375 2 (010) 0.9014 4.5072 8.1130 11.7188 3 (011) 0.4507 2.2536 4.0565 5.8594 4 (100) 0.2254 1.1268 2.0282 2.9297 5 (101) 0.1127 0.5634 1.0141 1.4648 6 (110) 0.0563 0.2817 0.5071 0.7324 7 (111) Until end of packet As an example, EVENT0=34666, WOR_RES=0 and RX_TIME=6 corresponds to 1.96 ms RX timeout, 1 s polling interval and 0.195% duty cycle. Note that WOR_RES should be 0 or 1 when using WOR because using WOR_RES > 1 will give a very low duty cycle. In applications where WOR is not used all settings of WOR_RES can be used. The duty cycle using WOR is approximated by: Setting WOR_RES=0 WOR_RES=1 0 (000) 12.50% 1.95% 1 (001) 6.250% 9765ppm 2 (010) 3.125% 4883ppm 3 (011) 1.563% 2441ppm 4 (100) 0.781% NA 5 (101) 0.391% NA 6 (110) 0.195% NA 7 (111) NA Note that the RC oscillator must be enabled in order to use setting 0-6, because the timeout counts RC oscillator periods. WOR mode does not need to be enabled. The timeout counter resolution is limited: With RX_TIME=0, the timeout count is given by the 13 MSBs of EVENT0, decreasing to the 7MSBs of EVENT0 with RX_TIME=6. CC1100 SWRS038D Page 74 of 92 0x17: MCSM1– Main Radio Control State Machine Configuration Bit Field Name Reset R/W Description 7:6 Reserved R0 5:4 CCA_MODE[1:0] 3 (11) R/W Selects CCA_MODE; Reflected in CCA signal Setting Clear channel indication 0 (00) Always 1 (01) If RSSI below threshold 2 (10) Unless currently receiving a packet 3 (11) If RSSI below threshold unless currently receiving a packet 3:2 RXOFF_MODE[1:0] 0 (00) R/W Select what should happen when a packet has been received Setting Next state after finishing packet reception 0 (00) IDLE 1 (01) FSTXON 2 (10) TX 3 (11) Stay in RX It is not possible to set RXOFF_MODE to be TX or FSTXON and at the same time use CCA. 1:0 TXOFF_MODE[1:0] 0 (00) R/W Select what should happen when a packet has been sent (TX) Setting Next state after finishing packet transmission 0 (00) IDLE 1 (01) FSTXON 2 (10) Stay in TX (start sending preamble) 3 (11) RX CC1100 SWRS038D Page 75 of 92 0x18: MCSM0– Main Radio Control State Machine Configuration Bit Field Name Reset R/W Description 7:6 Reserved R0 5:4 FS_AUTOCAL[1:0] 0 (00) R/W Automatically calibrate when going to RX or TX, or back to IDLE Setting When to perform automatic calibration 0 (00) Never (manually calibrate using SCAL strobe) 1 (01) When going from IDLE to RX or TX (or FSTXON) 2 (10) When going from RX or TX back to IDLE automatically 3 (11) Every 4th time when going from RX or TX to IDLE automatically In some automatic wake-on-radio (WOR) applications, using setting 3 (11) can significantly reduce current consumption. 3:2 PO_TIMEOUT 1 (01) R/W Programs the number of times the six-bit ripple counter must expire after XOSC has stabilized before CHP_RDYn goes low. If XOSC is on (stable) during power-down, PO_TIMEOUT should be set so that the regulated digital supply voltage has time to stabilize before CHP_RDYn goes low (PO_TIMEOUT=2 recommended). Typical start-up time for the voltage regulator is 50 us. If XOSC is off during power-down and the regulated digital supply voltage has sufficient time to stabilize while waiting for the crystal to be stable, PO_TIMEOUT can be set to 0. For robust operation it is recommended to use PO_TIMEOUT=2. Setting Expire count Timeout after XOSC start 0 (00) 1 Approx. 2.3 – 2.4 μs 1 (01) 16 Approx. 37 – 39 μs 2 (10) 64 Approx. 149 – 155 μs 3 (11) 256 Approx. 597 – 620 μs Exact timeout depends on crystal frequency. 1 PIN_CTRL_EN 0 R/W Enables the pin radio control option 0 XOSC_FORCE_ON 0 R/W Force the XOSC to stay on in the SLEEP state. CC1100 SWRS038D Page 76 of 92 0x19: FOCCFG – Frequency Offset Compensation Configuration Bit Field Name Reset R/W Description 7:6 Reserved R0 5 FOC_BS_CS_GATE 1 R/W If set, the demodulator freezes the frequency offset compensation and clock recovery feedback loops until the CS signal goes high. 4:3 FOC_PRE_K[1:0] 2 (10) R/W The frequency compensation loop gain to be used before a sync word is detected. Setting Freq. compensation loop gain before sync word 0 (00) K 1 (01) 2K 2 (10) 3K 3 (11) 4K 2 FOC_POST_K 1 R/W The frequency compensation loop gain to be used after a sync word is detected. Setting Freq. compensation loop gain after sync word 0 Same as FOC_PRE_K 1 K/2 1:0 FOC_LIMIT[1:0] 2 (10) R/W The saturation point for the frequency offset compensation algorithm: Setting Saturation point (max compensated offset) 0 (00) ±0 (no frequency offset compensation) 1 (01) ±BWCHAN/8 2 (10) ±BWCHAN/4 3 (11) ±BWCHAN/2 Frequency offset compensation is not supported for ASK/OOK; Always use FOC_LIMIT=0 with these modulation formats. CC1100 SWRS038D Page 77 of 92 0x1A: BSCFG – Bit Synchronization Configuration Bit Field Name Reset R/W Description 7:6 BS_PRE_KI[1:0] 1 (01) R/W The clock recovery feedback loop integral gain to be used before a sync word is detected (used to correct offsets in data rate): Setting Clock recovery loop integral gain before sync word 0 (00) KI 1 (01) 2KI 2 (10) 3KI 3 (11) 4 KI 5:4 BS_PRE_KP[1:0] 2 (10) R/W The clock recovery feedback loop proportional gain to be used before a sync word is detected. Setting Clock recovery loop proportional gain before sync word 0 (00) KP 1 (01) 2KP 2 (10) 3KP 3 (11) 4KP 3 BS_POST_KI 1 R/W The clock recovery feedback loop integral gain to be used after a sync word is detected. Setting Clock recovery loop integral gain after sync word 0 Same as BS_PRE_KI 1 KI /2 2 BS_POST_KP 1 R/W The clock recovery feedback loop proportional gain to be used after a sync word is detected. Setting Clock recovery loop proportional gain after sync word 0 Same as BS_PRE_KP 1 KP 1:0 BS_LIMIT[1:0] 0 (00) R/W The saturation point for the data rate offset compensation algorithm: Setting Data rate offset saturation (max data rate difference) 0 (00) ±0 (No data rate offset compensation performed) 1 (01) ±3.125% data rate offset 2 (10) ±6.25% data rate offset 3 (11) ±12.5% data rate offset CC1100 SWRS038D Page 78 of 92 0x1B: AGCCTRL2 – AGC Control Bit Field Name Reset R/W Description 7:6 MAX_DVGA_GAIN[1:0] 0 (00) R/W Reduces the maximum allowable DVGA gain. Setting Allowable DVGA settings 0 (00) All gain settings can be used 1 (01) The highest gain setting can not be used 2 (10) The 2 highest gain settings can not be used 3 (11) The 3 highest gain settings can not be used 5:3 MAX_LNA_GAIN[2:0] 0 (000) R/W Sets the maximum allowable LNA + LNA 2 gain relative to the maximum possible gain. Setting Maximum allowable LNA + LNA 2 gain 0 (000) Maximum possible LNA + LNA 2 gain 1 (001) Approx. 2.6 dB below maximum possible gain 2 (010) Approx. 6.1 dB below maximum possible gain 3 (011) Approx. 7.4 dB below maximum possible gain 4 (100) Approx. 9.2 dB below maximum possible gain 5 (101) Approx. 11.5 dB below maximum possible gain 6 (110) Approx. 14.6 dB below maximum possible gain 7 (111) Approx. 17.1 dB below maximum possible gain 2:0 MAGN_TARGET[2:0] 3 (011) R/W These bits set the target value for the averaged amplitude from the digital channel filter (1 LSB = 0 dB). Setting Target amplitude from channel filter 0 (000) 24 dB 1 (001) 27 dB 2 (010) 30 dB 3 (011) 33 dB 4 (100) 36 dB 5 (101) 38 dB 6 (110) 40 dB 7 (111) 42 dB CC1100 SWRS038D Page 79 of 92 0x1C: AGCCTRL1 – AGC Control Bit Field Name Reset R/W Description 7 Reserved R0 6 AGC_LNA_PRIORITY 1 R/W Selects between two different strategies for LNA and LNA 2 gain adjustment. When 1, the LNA gain is decreased first. When 0, the LNA 2 gain is decreased to minimum before decreasing LNA gain. 5:4 CARRIER_SENSE_REL_THR[1:0] 0 (00) R/W Sets the relative change threshold for asserting carrier sense Setting Carrier sense relative threshold 0 (00) Relative carrier sense threshold disabled 1 (01) 6 dB increase in RSSI value 2 (10) 10 dB increase in RSSI value 3 (11) 14 dB increase in RSSI value 3:0 CARRIER_SENSE_ABS_THR[3:0] 0 (0000) R/W Sets the absolute RSSI threshold for asserting carrier sense. The 2-complement signed threshold is programmed in steps of 1 dB and is relative to the MAGN_TARGET setting. Setting Carrier sense absolute threshold (Equal to channel filter amplitude when AGC has not decreased gain) -8 (1000) Absolute carrier sense threshold disabled -7 (1001) 7 dB below MAGN_TARGET setting … … -1 (1111) 1 dB below MAGN_TARGET setting 0 (0000) At MAGN_TARGET setting 1 (0001) 1 dB above MAGN_TARGET setting … … 7 (0111) 7 dB above MAGN_TARGET setting CC1100 SWRS038D Page 80 of 92 0x1D: AGCCTRL0 – AGC Control Bit Field Name Reset R/W Description 7:6 HYST_LEVEL[1:0] 2 (10) R/W Sets the level of hysteresis on the magnitude deviation (internal AGC signal that determine gain changes). Setting Description 0 (00) No hysteresis, small symmetric dead zone, high gain 1 (01) Low hysteresis, small asymmetric dead zone, medium gain 2 (10) Medium hysteresis, medium asymmetric dead zone, medium gain 3 (11) Large hysteresis, large asymmetric dead zone, low gain 5:4 WAIT_TIME[1:0] 1 (01) R/W Sets the number of channel filter samples from a gain adjustment has been made until the AGC algorithm starts accumulating new samples. Setting Channel filter samples 0 (00) 8 1 (01) 16 2 (10) 24 3 (11) 32 3:2 AGC_FREEZE[1:0] 0 (00) R/W Control when the AGC gain should be frozen. Setting Function 0 (00) Normal operation. Always adjust gain when required. 1 (01) The gain setting is frozen when a sync word has been found. 2 (10) Manually freeze the analogue gain setting and continue to adjust the digital gain. 3 (11) Manually freezes both the analogue and the digital gain setting. Used for manually overriding the gain. 1:0 FILTER_LENGTH[1:0] 1 (01) R/W Sets the averaging length for the amplitude from the channel filter. Sets the OOK/ASK decision boundary for OOK/ASK reception. Setting Channel filter samples OOK decision 0 (00) 8 4 dB 1 (01) 16 8 dB 2 (10) 32 12 dB 3 (11) 64 16 dB 0x1E: WOREVT1 – High Byte Event0 Timeout Bit Field Name Reset R/W Description 7:0 EVENT0[15:8] 135 (0x87) R/W High byte of EVENT0 timeout register WOR RES XOSC Event EVENT f t 5 _ 0 = 750 ⋅ 0⋅ 2 ⋅ CC1100 SWRS038D Page 81 of 92 0x1F: WOREVT0 –Low Byte Event0 Timeout Bit Field Name Reset R/W Description 7:0 EVENT0[7:0] 107 (0x6B) R/W Low byte of EVENT0 timeout register. The default EVENT0 value gives 1.0s timeout, assuming a 26.0 MHz crystal. 0x20: WORCTRL – Wake On Radio Control Bit Field Name Reset R/W Description 7 RC_PD 1 R/W Power down signal to RC oscillator. When written to 0, automatic initial calibration will be performed 6:4 EVENT1[2:0] 7 (111) R/W Timeout setting from register block. Decoded to Event 1 timeout. RC oscillator clock frequency equals FXOSC/750, which is 34.7 – 36 kHz, depending on crystal frequency. The table below lists the number of clock periods after Event 0 before Event 1 times out. Setting tEvent1 0 (000) 4 (0.111 – 0.115 ms) 1 (001) 6 (0.167 – 0.173 ms) 2 (010) 8 (0.222 – 0.230 ms) 3 (011) 12 (0.333 – 0.346 ms) 4 (100) 16 (0.444 – 0.462 ms) 5 (101) 24 (0.667 – 0.692 ms) 6 (110) 32 (0.889 – 0.923 ms) 7 (111) 48 (1.333 – 1.385 ms) 3 RC_CAL 1 R/W Enables (1) or disables (0) the RC oscillator calibration. 2 Reserved R0 1:0 WOR_RES 0 (00) R/W Controls the Event 0 resolution as well as maximum timeout of the WOR module and maximum timeout under normal RX operation:: Setting Resolution (1 LSB) Max timeout 0 (00) 1 period (28μs – 29μs) 1.8 – 1.9 seconds 1 (01) 25 periods (0.89ms –0.92 ms) 58 – 61 seconds 2 (10) 210 periods (28 – 30 ms) 31 – 32 minutes 3 (11) 215 periods (0.91 – 0.94 s) 16.5 – 17.2 hours Note that WOR_RES should be 0 or 1 when using WOR because WOR_RES > 1 will give a very low duty cycle. In normal RX operation all settings of WOR_RES can be used. CC1100 SWRS038D Page 82 of 92 0x21: FREND1 – Front End RX Configuration Bit Field Name Reset R/W Description 7:6 LNA_CURRENT[1:0] 1 (01) R/W Adjusts front-end LNA PTAT current output 5:4 LNA2MIX_CURRENT[1:0] 1 (01) R/W Adjusts front-end PTAT outputs 3:2 LODIV_BUF_CURRENT_RX[1:0] 1 (01) R/W Adjusts current in RX LO buffer (LO input to mixer) 1:0 MIX_CURRENT[1:0] 2 (10) R/W Adjusts current in mixer 0x22: FREND0 – Front End TX Configuration Bit Field Name Reset R/W Description 7:6 Reserved R0 5:4 LODIV_BUF_CURRENT_TX[1:0] 1 (0x01) R/W Adjusts current TX LO buffer (input to PA). The value to use in this field is given by the SmartRF® Studio software [7]. 3 Reserved R0 2:0 PA_POWER[2:0] 0 (0x00) R/W Selects PA power setting. This value is an index to the PATABLE, which can be programmed with up to 8 different PA settings. In OOK/ASK mode, this selects the PATABLE index to use when transmitting a ‘1’. PATABLE index zero is used in OOK/ASK when transmitting a ‘0’. The PATABLE settings from index ‘0’ to the PA_POWER value are used for ASK TX shaping, and for power ramp-up/ramp-down at the start/end of transmission in all TX modulation formats. 0x23: FSCAL3 – Frequency Synthesizer Calibration Bit Field Name Reset R/W Description 7:6 FSCAL3[7:6] 2 (0x02) R/W Frequency synthesizer calibration configuration. The value to write in this field before calibration is given by the SmartRF® Studio software. 5:4 CHP_CURR_CAL_EN[1:0] 2 (0x02) R/W Enable charge pump calibration stage when 1 3:0 FSCAL3[3:0] 9 (1001) R/W Frequency synthesizer calibration result register. Digital bit vector defining the charge pump output current, on an exponential scale: IOUT = I0·2FSCAL3[3:0]/4 Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. CC1100 SWRS038D Page 83 of 92 0x24: FSCAL2 – Frequency Synthesizer Calibration Bit Field Name Reset R/W Description 7:6 Reserved R0 5 VCO_CORE_H_EN 0 R/W Choose high (1) / low (0) VCO 4:0 FSCAL2[4:0] 10 (0x0A) R/W Frequency synthesizer calibration result register. VCO current calibration result and override value Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. 0x25: FSCAL1 – Frequency Synthesizer Calibration Bit Field Name Reset R/W Description 7:6 Reserved R0 5:0 FSCAL1[5:0] 32 (0x20) R/W Frequency synthesizer calibration result register. Capacitor array setting for VCO coarse tuning. Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. 0x26: FSCAL0 – Frequency Synthesizer Calibration Bit Field Name Reset R/W Description 7 Reserved R0 6:0 FSCAL0[6:0] 13 (0x0D) R/W Frequency synthesizer calibration control. The value to use in this register is given by the SmartRF® Studio software [7]. 0x27: RCCTRL1 – RC Oscillator Configuration Bit Field Name Reset R/W Description 7 Reserved 0 R0 6:0 RCCTRL1[6:0] 65 (0x41) R/W RC oscillator configuration. 0x28: RCCTRL0 – RC Oscillator Configuration Bit Field Name Reset R/W Description 7 Reserved 0 R0 6:0 RCCTRL0[6:0] 0 (0x00) R/W RC oscillator configuration. CC1100 SWRS038D Page 84 of 92 33.2 Configuration Register Details – Registers that Lose Programming in SLEEP State 0x29: FSTEST – Frequency Synthesizer Calibration Control Bit Field Name Reset R/W Description 7:0 FSTEST[7:0] 89 (0x59) R/W For test only. Do not write to this register. 0x2A: PTEST – Production Test Bit Field Name Reset R/W Description 7:0 PTEST[7:0] 127 (0x7F) R/W Writing 0xBF to this register makes the on-chip temperature sensor available in the IDLE state. The default 0x7F value should then be written back before leaving the IDLE state. Other use of this register is for test only. 0x2B: AGCTEST – AGC Test Bit Field Name Reset R/W Description 7:0 AGCTEST[7:0] 63 (0x3F) R/W For test only. Do not write to this register. 0x2C: TEST2 – Various Test Settings Bit Field Name Reset R/W Description 7:0 TEST2[7:0] 136 (0x88) R/W The value to use in this register is given by the SmartRF® Studio software [7]. 0x2D: TEST1 – Various Test Settings Bit Field Name Reset R/W Description 7:0 TEST1[7:0] 49 (0x31) R/W The value to use in this register is given by the SmartRF® Studio software [7]. 0x2E: TEST0 – Various Test Settings Bit Field Name Reset R/W Description 7:2 TEST0[7:2] 2 (0x02) R/W The value to use in this register is given by the SmartRF® Studio software [7]. 1 VCO_SEL_CAL_EN 1 R/W Enable VCO selection calibration stage when 1 0 TEST0[0] 1 R/W The value to use in this register is given by the SmartRF® Studio software [7]. CC1100 SWRS038D Page 85 of 92 33.3 Status Register Details 0x30 (0xF0): PARTNUM – Chip ID Bit Field Name Reset R/W Description 7:0 PARTNUM[7:0] 0 (0x00) R Chip part number 0x31 (0xF1): VERSION – Chip ID Bit Field Name Reset R/W Description 7:0 VERSION[7:0] 3 (0x03) R Chip version number. 0x32 (0xF2): FREQEST – Frequency Offset Estimate from Demodulator Bit Field Name Reset R/W Description 7:0 FREQOFF_EST R The estimated frequency offset (2’s complement) of the carrier. Resolution is FXTAL/214 (1.59 - 1.65 kHz); range is ±202 kHz to ±210 kHz, dependent of XTAL frequency. Frequency offset compensation is only supported for 2-FSK, GFSK, and MSK modulation. This register will read 0 when using ASK or OOK modulation. 0x33 (0xF3): LQI – Demodulator Estimate for Link Quality Bit Field Name Reset R/W Description 7 CRC OK R The last CRC comparison matched. Cleared when entering/restarting RX mode. 6:0 LQI_EST[6:0] R The Link Quality Indicator estimates how easily a received signal can be demodulated. Calculated over the 64 symbols following the sync word 0x34 (0xF4): RSSI – Received Signal Strength Indication Bit Field Name Reset R/W Description 7:0 RSSI R Received signal strength indicator CC1100 SWRS038D Page 86 of 92 0x35 (0xF5): MARCSTATE – Main Radio Control State Machine State Bit Field Name Reset R/W Description 7:5 Reserved R0 4:0 MARC_STATE[4:0] R Main Radio Control FSM State Value State name State (Figure 16, page 42) 0 (0x00) SLEEP SLEEP 1 (0x01) IDLE IDLE 2 (0x02) XOFF XOFF 3 (0x03) VCOON_MC MANCAL 4 (0x04) REGON_MC MANCAL 5 (0x05) MANCAL MANCAL 6 (0x06) VCOON FS_WAKEUP 7 (0x07) REGON FS_WAKEUP 8 (0x08) STARTCAL CALIBRATE 9 (0x09) BWBOOST SETTLING 10 (0x0A) FS_LOCK SETTLING 11 (0x0B) IFADCON SETTLING 12 (0x0C) ENDCAL CALIBRATE 13 (0x0D) RX RX 14 (0x0E) RX_END RX 15 (0x0F) RX_RST RX 16 (0x10) TXRX_SWITCH TXRX_SETTLING 17 (0x11) RXFIFO_OVERFLOW RXFIFO_OVERFLOW 18 (0x12) FSTXON FSTXON 19 (0x13) TX TX 20 (0x14) TX_END TX 21 (0x15) RXTX_SWITCH RXTX_SETTLING 22 (0x16) TXFIFO_UNDERFLOW TXFIFO_UNDERFLOW Note: it is not possible to read back the SLEEP or XOFF state numbers because setting CSn low will make the chip enter the IDLE mode from the SLEEP or XOFF states. 0x36 (0xF6): WORTIME1 – High Byte of WOR Time Bit Field Name Reset R/W Description 7:0 TIME[15:8] R High byte of timer value in WOR module 0x37 (0xF7): WORTIME0 – Low Byte of WOR Time Bit Field Name Reset R/W Description 7:0 TIME[7:0] R Low byte of timer value in WOR module CC1100 SWRS038D Page 87 of 92 0x38 (0xF8): PKTSTATUS – Current GDOx Status and Packet Status Bit Field Name Reset R/W Description 7 CRC_OK R The last CRC comparison matched. Cleared when entering/restarting RX mode. 6 CS R Carrier sense 5 PQT_REACHED R Preamble Quality reached 4 CCA R Channel is clear 3 SFD R Sync word found 2 GDO2 R Current GDO2 value. Note: the reading gives the non-inverted value irrespective of what IOCFG2.GDO2_INV is programmed to. It is not recommended to check for PLL lock by reading PKTSTATUS[2] with GDO2_CFG=0x0A. 1 Reserved R0 0 GDO0 R Current GDO0 value. Note: the reading gives the non-inverted value irrespective of what IOCFG0.GDO0_INV is programmed to. It is not recommended to check for PLL lock by reading PKTSTATUS[0] with GDO0_CFG=0x0A. 0x39 (0xF9): VCO_VC_DAC – Current Setting from PLL Calibration Module Bit Field Name Reset R/W Description 7:0 VCO_VC_DAC[7:0] R Status register for test only. 0x3A (0xFA): TXBYTES – Underflow and Number of Bytes Bit Field Name Reset R/W Description 7 TXFIFO_UNDERFLOW R 6:0 NUM_TXBYTES R Number of bytes in TX FIFO 0x3B (0xFB): RXBYTES – Overflow and Number of Bytes Bit Field Name Reset R/W Description 7 RXFIFO_OVERFLOW R 6:0 NUM_RXBYTES R Number of bytes in RX FIFO 0x3C (0xFC): RCCTRL1_STATUS – Last RC Oscillator Calibration Result Bit Field Name Reset R/W Description 7 Reserved R0 6:0 RCCTRL1_STATUS[6:0] R Contains the value from the last run of the RC oscillator calibration routine. For usage description refer to AN047 [4] CC1100 SWRS038D Page 88 of 92 0x3D (0xFC): RCCTRL0_STATUS – Last RC Oscillator Calibration Result Bit Field Name Reset R/W Description 7 Reserved R0 6:0 RCCTRL0_STATUS[6:0] R Contains the value from the last run of the RC oscillator calibration routine. For usage description refer to Aplication Note AN047 [4]. 34 Package Description (QLP 20) 34.1 Recommended PCB Layout for Package (QLP 20) Figure 31: Recommended PCB Layout for QLP 20 Package Note: Figure 31 is an illustration only and not to scale. There are five 10 mil via holes distributed symmetrically in the ground pad under the package. See also the CC1100EM reference designs ([5] and [6]). 34.2 Soldering Information The recommendations for lead-free reflow in IPC/JEDEC J-STD-020 should be followed. CC1100 SWRS038D Page 89 of 92 35 Ordering Information Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead Finish MSL Peak Temp (3) CC1100RTKR NRND QLP RTK 20 3000 Green (RoHS & no Sb/Br) Cu NiPdAu LEVEL3-260C 1 YEAR CC1100RTK NRND QLP RTK 20 92 Green (RoHS & no Sb/Br) Cu NiPdAu LEVEL3-260C 1 YEAR Table 39: Ordering Information CC1100 SWRS038D Page 90 of 92 36 References [1] CC1100 Errata Notes (swrz012.pdf) [2] AN001 SRD Regulations for Licence Free Transceiver Operation (swra090.pdf) [3] AN039 Using the CC1100 in the European 433 and 868 MHz ISM Bands (swra054.pdf) [4] AN047 CC1100/CC2500 – Wake-On-Radio (swra126.pdf) [5] CC1100EM 315 - 433 MHz Reference Design 1.0 (swrr037.zip) [6] CC1100EM 868 – 915 MHz Reference Design 2.0 (swrr038.zip) [7] SmartRF® Studio (swrc046.zip) [8] CC1100 CC2500 Examples Libraries (swrc021.zip) [9] CC1100/CC1150DK, CC1101DK, and CC2500/CC2550DK Examples and Libraries User Manual (swru109.pdf) CC1100 SWRS038D Page 91 of 92 37 General Information 37.1 Document History Revision Date Description/Changes SWRS038D 2009-05-26 Updated packet and ordering information. Removed Product Status Definition, Address Information and TI World Wide Support section. Removed Low-Cost from datasheet title. SWRS038C 2008-05-22 Added product information on front page SWRS038B 2007-07-09 Added info to ordering information Changes in the General Principle of Matrix Interleaving figure. Changes in Table: Bill Of Materials for the Application Circuit Changes in Figure: Typical Application and Evaluation Circuit 868/915 MHz Changed the equation for channel spacing in the MDMCFG0 register. kbps replaced by kBaud throughout the document. Some of the sections have been re-written to be easier to read without having any new info added. Absolute maximum supply voltage rating increased from 3.6 V to 3.9 V. Changed the frequency accuracy after calibration for the low power RC oscillator from ±0.3 to ±1 %. Updates to sensitivity and current consumption numbers listed under Key Features. FSK changed to 2-FSK throughout the document. Updates to the Abbreviation table. Updates to the Electrical Specifications section. Added info about RX and TX latency. Added info in the Pinout Overview table regarding GDO0 and GDO2. Changed current consumption in RX and TX in the simplified state diagram. Added info about default values after reset vs. optimum register settings in the Configuration Software section Changes to the SPI Interface Timing Requirements. Info added about tsp,pd The following figures have been changed: Configuration Registers Write and Read Operations, SRES Command Strobe, and Register Access Types. In the Register Access section, the address range is changed. In the PATABLE Access section, info is added regarding limitations on output power programming when using PA ramping. In the Packet Format section, preamble pattern is changed to 10101010 and info about bug related to turning off the transmitter in infinite packet length mode is added. Added info to the Frequency Offset Compensation section. Added info about the initial value of the PN9 sequence in the Data Whitening section. In the Packet Handling in Transmit Mode section, info about TX FIFO underflow state is added. Added section Packet Handling in Firmware. 0x00 is added as a valid PATABLE setting in addition to 0x30-0x3F when using ASK. In the PQT section a change is made as to how much the counter decreases. The RSSI value is in dBm and not dB. The whole CS Absolute Threshold section has been re-written and the equation calculating the threshold has been removed. Added info in the CCA section on what happens if the channel is not clear. Added info to the LQI section for better understanding. Removed all references to the voltage regulator in relation with the CHP_RDYn signal, as this signal is only related to the crystal. Removed references to the voltage regulator in the figures: Power-On Reset and Power-On Reset with SRES. Changes to the SI line in the Power-On Reset with SRES figure Added info on the three automatic calibration options. Removed the autosync feature from the WOR section and added info on how to exit WOR mode. Also added info about minimum sleep time and references to App. Note 047 together with info about calibration of the RC oscillator. The figure: Event 0 and Event 1 Relationship is changed for better readability. Info added to the Timing section related to reduced calibration time. The Output Power Programming section is divided into 2 new sections; Output Power Programming and Shaping and PA Ramping. Added info on programming of PATABLE when using OOK, and about PATABLE when entering SLEEP mode. 2 new figures added to the Shaping and PA Ramping section: Shaping of ASK Signal and PA Ramping, together with one new table: PATABLE Settings Used Together with ASK Shaping and PA Ramping. Changed made to current consumption in the Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands table. Added section Layout Recommendations. In section General Purpose / Test Output Control Pins: Added info on GDO pins in SLEEP CC1100 SWRS038D Page 92 of 92 Revision Date Description/Changes state. Better explanation of some of the signals in the GDOx Signal Selection table. Also added some more signals. Asynchronous transparent mode is called asynchronous serial mode throughout the document. Removed comments about having to use NRZ coding in synchronous serial mode. Added info that Manschester encoding cannot be used in this mode. Added a third calibration method plus additional info about the 3 methods in the Frequency Hopping and Multi-Channel Systems section. Added info about differential antenna in the Low Cost Systems section. Changes number of commands strobes from 14 to 13. Changed description of SFRX, SFTX, SWORRST, and SNOP in the Command Strobes table. Added two new registers; RCCTRL1_STATUS and RCCTRL0_STATUS Changed field name and/or description of the following registers: PKTCTRL1, MCSM2, MCSM0, WORCTRL, FSCAL3, FSCAL2, FSCAL1, and TEST0. Changed tray width in the Tray Specification table. Added references. SWRS038A 2006-06-20 Updates to Electrical Specifications due to increased amount of measurement data. Updated application circuit for 868 MHz. Updated balun component values. Updated current consumption figures in state diagrams. Added figures to table on SPI interface timing requirements. Added information about SPI read. Added table for channel filter bandwidths. Added figure showing data whitening. Updates to text and included new figure in section on arbitrary length configuration. References to SAFC strobe removed. Added additional information about support of ASK modulation. Added information about CRC filtering. Added information about sync word qualifier. Added information on RSSI offset, RSSI update rate, RSSI calculation and typical RSSI curves. Added information on CS and tables with register settings versus CS threshold. Updates to text and included new figures in section on power-on start-up sequence. Changes to wake-on-radio current consumption figures under electrical specifications. Updates to text in section on data FIFO. Corrected formula for calculation of output frequency in Frequency Programming section. Added information about how to check for PLL lock in section on VCO. Corrected table with PATABLE setting versus output power. Added typical selectivity curves for selected datarates. Added information on how to interface external clock signal. Added optimal match impedances in RF match section. Better explanation of some of the signals in table of GDO signal selection. Also added some more signals. Added information on system considerations. Added CRC_AUTOFLUSH option in PCTRL1 register. Added information on timeout for sync word search in RX in register MCSM2. Changes to wake-on-radio control register WORCTRL. WOR_RES[1:0] settings 10 b and 11b changed to NA. Added more detailed information on PO_TIMEOUT in register MCSM0. Added description of programming bits in registers FOCCFG, BSCFG, AGCCTRL2, AGCCTRL1, AGCCTRL0, FREND1, FSCAL3. 1.0 2005-04-25 First preliminary Data Sheet release Table 40: Document History PACKAGE OPTION ADDENDUM www.ti.com 24-Apr-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CC1100-RTR1 NRND VQFN RTK 20 3000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 CC1100 CC1100-RTY1 NRND VQFN RTK 20 92 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 CC1100 CC1100RTK NRND VQFN RTK 20 92 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 CC1100 CC1100RTKG3 NRND VQFN RTK 20 92 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 CC1100 CC1100RTKR NRND VQFN RTK 20 3000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 CC1100 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. PACKAGE OPTION ADDENDUM www.ti.com 24-Apr-2014 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant CC1100RTKR VQFN RTK 20 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jan-2014 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CC1100RTKR VQFN RTK 20 3000 338.1 338.1 20.6 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jan-2014 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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FEATURES Converts an ac voltage waveform to a dc voltage and then converts to the true rms, average rectified, or absolute value 200 mV rms full-scale input range (larger inputs with input attenuator) High input impedance: 1012 Ω Low input bias current: 25 pA maximum High accuracy: ±0.3 mV ± 0.3% of reading RMS conversion with signal crest factors up to 5 Wide power supply range: +2.8 V, −3.2 V to ±16.5 V Low power: 200 μA maximum supply current Buffered voltage output No external trims needed for specified accuracy Related device: the AD737—features a power-down control with standby current of only 25 μA; the dc output voltage is negative and the output impedance is 8 kΩ GENERAL DESCRIPTION The AD736 is a low power, precision, monolithic true rms-to-dc converter. It is laser trimmed to provide a maximum error of ±0.3 mV ± 0.3% of reading with sine wave inputs. Furthermore, it maintains high accuracy while measuring a wide range of input waveforms, including variable duty-cycle pulses and triac (phase)-controlled sine waves. The low cost and small size of this converter make it suitable for upgrading the performance of non-rms precision rectifiers in many applications. Compared to these circuits, the AD736 offers higher accuracy at an equal or lower cost. The AD736 can compute the rms value of both ac and dc input voltages. It can also be operated as an ac-coupled device by adding one external capacitor. In this mode, the AD736 can resolve input signal levels of 100 μV rms or less, despite variations in temperature or supply voltage. High accuracy is also maintained for input waveforms with crest factors of 1 to 3. In addition, crest factors as high as 5 can be measured (introducing only 2.5% additional error) at the 200 mV full-scale input level. The AD736 has its own output buffer amplifier, thereby pro-viding a great deal of design flexibility. Requiring only 200 μA of power supply current, the AD736 is optimized for use in portable multimeters and other battery-powered applications. FUNCTIONAL BLOCK DIAGRAM CC8kΩ–VSCAVCOMVINCAVOUTFULL WAVERECTIFIERRMSCORE8kΩCF(OPT)CFBIASSECTION+VS00834-001 Figure 1. The AD736 allows the choice of two signal input terminals: a high impedance FET input (1012 Ω) that directly interfaces with High-Z input attenuators and a low impedance input (8 kΩ) that allows the measurement of 300 mV input levels while operating from the minimum power supply voltage of +2.8 V, −3.2 V. The two inputs can be used either single ended or differentially. The AD736 has a 1% reading error bandwidth that exceeds 10 kHz for the input amplitudes from 20 mV rms to 200 mV rms while consuming only 1 mW. The AD736 is available in four performance grades. The AD736J and AD736K grades are rated over the 0°C to +70°C and −20°C to +85°C commercial temperature ranges. The AD736A and AD736B grades are rated over the −40°C to +85°C industrial temperature range. The AD736 is available in three low cost, 8-lead packages: PDIP, SOIC, and CERDIP. PRODUCT HIGHLIGHTS 1. The AD736 is capable of computing the average rectified value, absolute value, or true rms value of various input signals. 2. Only one external component, an averaging capacitor, is required for the AD736 to perform true rms measurement. 3. The low power consumption of 1 mW makes the AD736 suitable for many battery-powered applications. 4. A high input impedance of 1012 Ω eliminates the need for an external buffer when interfacing with input attenuators. 5. A low impedance input is available for those applications that require an input signal up to 300 mV rms operating from low power supply voltages. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1  Low Supply-Voltage Range: 1.8 V to 3.6 V  Ultralow Power Consumption − Active Mode: 330 μA at 1 MHz, 2.2 V − Standby Mode: 1.1 μA − Off Mode (RAM Retention): 0.2 μA  Five Power-Saving Modes  Wake-Up From Standby Mode in Less Than 6 μs  16-Bit RISC Architecture, 125-ns Instruction Cycle Time  Three-Channel Internal DMA  12-Bit Analog-to-Digital (A/D) Converter With Internal Reference, Sample-and-Hold, and Autoscan Feature  Dual 12-Bit Digital-to-Analog (D/A) Converters With Synchronization  16-Bit Timer_A With Three Capture/Compare Registers  16-Bit Timer_B With Three or Seven Capture/Compare-With-Shadow Registers  On-Chip Comparator  Serial Communication Interface (USART0), Functions as Asynchronous UART or Synchronous SPI or I2CTM Interface  Serial Communication Interface (USART1), Functions as Asynchronous UART or Synchronous SPI Interface  Supply Voltage Supervisor/Monitor With Programmable Level Detection  Brownout Detector  Bootstrap Loader I2C is a registered trademark of Philips Incorporated.  Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse  Family Members Include − MSP430F155 16KB+256B Flash Memory 512B RAM − MSP430F156 24KB+256B Flash Memory 1KB RAM − MSP430F157 32KB+256B Flash Memory, 1KB RAM − MSP430F167 32KB+256B Flash Memory, 1KB RAM − MSP430F168 48KB+256B Flash Memory, 2KB RAM − MSP430F169 60KB+256B Flash Memory, 2KB RAM − MSP430F1610 32KB+256B Flash Memory 5KB RAM − MSP430F1611 48KB+256B Flash Memory 10KB RAM − MSP430F1612 55KB+256B Flash Memory 5KB RAM  Available in 64-Pin QFP Package (PM) and 64-Pin QFN Package (RTD)  For Complete Module Descriptions, See the MSP430x1xx Family User’s Guide, Literature Number SLAU049 description The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 μs. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection. PRODUCTION DATA information is current as of publication date. Copyright © 2011, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MSP430F15x, MSP430F16x, MSP430F161x MIXED SIGNAL MICROCONTROLLER SLAS368G − OCTOBER 2002 − REVISED MARCH 2011 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) The MSP430F15x/16x/161x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit A/D converter, dual 12-bit D/A converter, one or two universal serial synchronous/asynchronous communication interfaces (USART), I2C, DMA, and 48 I/O pins. In addition, the MSP430F161x series offers extended RAM addressing for memory-intensive applications and large C-stack requirements. Typical applications include sensor systems, industrial control applications, hand-held meters, etc. AVAILABLE OPTIONS T PACKAGED DEVICES TA PLASTIC 64-PIN QFP (PM) PLASTIC 64-PIN QFN (RTD) −40°C to 85°C MSP430F155IPM MSP430F156IPM MSP430F157IPM MSP430F167IPM MSP430F168IPM MSP430F169IPM MSP430F1610IPM MSP430F1611IPM MSP430F1612IPM MSP430F155IRTD MSP430F156IRTD MSP430F157IRTD MSP430F167IRTD MSP430F168IRTD MSP430F169IRTD MSP430F1610IRTD MSP430F1611IRTD MSP430F1612IRTD † Fo