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Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Recherche intégrée

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

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Voltage Level Translation

Puce électronique / Microchip :

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Raspberry Pi board B product overview

Logiciels :

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Introduction to Cadsoft EAGLE PCB Design Software in Chinese

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Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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Ben's Autodesk 123D Tutorial Trailer

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Ben's CadSoft EAGLE Tutorial Trailer

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Ben Heck's Soldering Tutorial Trailer

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Ben Heck's AVR Dev Board tutorial

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Ben Heck's Pinball Tutorial Trailer

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Ben Heck's Interface Tutorial Trailer

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First Stage with Python and PiFace Digital

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Cypress - Getting Started with PSoC® 3 - Part 2

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

Autres documentations :

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82-001925-01 a ADMC401 DSP Motor Controller Developer’s Reference Manual Revision 2.0 2 March 2000 ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 2 Table of Contents 1. INTRODUCTION..............................................................................................................................6 2. REFERENCED DOCUMENTS ........................................................................................................6 3. UPGRADE INFORMATION............................................................................................................7 4. GETTING STARTED .......................................................................................................................7 5. IMPORTANT SAFETY INFORMATION.......................................................................................7 6. SOFTWARE DEVELOPMENT........................................................................................................9 6.1 EVALUATION KIT SOFTWARE....................................................................................................... 11 6.2 GETTING STARTED WITH THE MOTION CONTROL DEBUGGER ........................................................ 12 6.2.1 Saving the Debugger Windows Configuration ..................................................................... 22 6.2.2 Modifying Your Program Directly From the Disassembly Window...................................... 23 6.2.3 Automatic Program Exit Function ...................................................................................... 23 6.2.4 Troubleshooting.................................................................................................................. 24 6.2.5 Error Messages .................................................................................................................. 24 6.3 PROGRAMMING SERIAL PROMS WITH MAKEPROM.................................................................... 26 6.4 USING INCLUDE FILES IN YOUR CODE........................................................................................... 27 7. ADMC401 HARDWARE OVERVIEW.......................................................................................... 28 7.1 MOTOR CONTROL PERIPHERAL REGISTERS................................................................................... 28 7.2 ADDRESS AND DATA BUS............................................................................................................. 28 8. MEMORY MAP.............................................................................................................................. 29 8.1 (MMAP = BMODE= 1 CONFIGURATION) ................................................................................... 29 8.2 (MMAP = BMODE= 0 CONFIGURATION) ................................................................................... 29 9. ON-CHIP ROM MONITOR OPERATION ................................................................................... 30 9.1 POWER-UP / RESET SEQUENCE ..................................................................................................... 30 9.2 SPORT1..................................................................................................................................... 30 9.3 THE ROM CODE MONITOR .......................................................................................................... 30 10. SOURCE CODE LIBRARY........................................................................................................ 35 11. BOOTING FROM EXTERNAL EPROM WITH MMAP=BMODE=0.................................... 36 12. INTERRUPT OPERATION........................................................................................................ 40 12.1 USING PUT_VECTOR................................................................................................................ 42 12.2 PERIPHERAL INTERRUPT CONSIDERATIONS ................................................................................... 42 13. WATCHDOG TIMER OPERATION......................................................................................... 43 14. SOFTWARE PERIPHERAL RESET FUNCTION.................................................................... 44 15. SROM/EEPROM RESET FUNCTION ...................................................................................... 44 16. TUTORIAL.................................................................................................................................. 45 16.1 EXAMPLE 1: SIMPLE CONFIGURATION EXAMPLE ........................................................................... 45 ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 3 17. APPENDICES .............................................................................................................................. 47 Figures Figure 1. The Software Development Process .............................................................................................9 Figure 2. Debugger Target Selection Dialog Box ...................................................................................... 12 Figure 3. Debugger Disassembly Window................................................................................................. 13 Figure 4. Loading an Executable File .................................................................................................... 14 Figure 5. Using the Find Text Window ..................................................................................................... 14 Figure 6. Finding Symbols in the Program................................................................................................ 15 Figure 7. Browsing the List of Symbols .................................................................................................... 15 Figure 8. The GoTo Address Box........................................................................................................... 16 Figure 9. Selecting Breaks from the Debug Menu................................................................................. 16 Figure 10. The Breaks Dialog Box ......................................................................................................... 16 Figure 11. Running the Program............................................................................................................ 17 Figure 12. Halting and Single-Stepping ................................................................................................. 18 Figure 13. Selecting a Register from the Registers Menu ..................................................................... 18 Figure 14. Viewing the PWM Registers................................................................................................. 19 Figure 15. Viewing the Program Memory (PM).................................................................................... 19 Figure 16. Selecting Format of Data Memory ....................................................................................... 20 Figure 17. Viewing the Memory Map .................................................................................................... 20 Figure 18. Dumping Memory ................................................................................................................. 20 Figure 19. Fill Memory........................................................................................................................... 21 Figure 20. Plot Memory Configuration Dialog ...................................................................................... 21 Figure 21. Plot Memory Output ............................................................................................................. 21 Figure 22. Motion Control Debugger Version........................................................................................... 22 Figure 23. Required Timing for Interfacing to an External Device............................................................ 32 Figure 24. Monitor Operation at Reset...................................................................................................... 34 Figure 25. Watchdog Timer Register ........................................................................................................ 43 Figure 26. Boot Load Timing (XC17128E, AT17C128, or 37LV128)....................................................... 57 Figure 27. UART Protocol........................................................................................................................ 60 ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 4 Tables Table 1. Summary of Debugger HotKeys .................................................................................................. 22 Table 2. ADMC401 Evaluation Board Memory Map (MMAP = BMODE = 1 Configuration)................... 29 Table 3. Two Byte Sequence for each Monitor Supported Interface........................................................... 31 Table 4. Interrupt Vector Addresses by Priority ........................................................................................ 40 Table 5. SROM / EEPROM Pin Connections............................................................................................ 55 Table 6. SROM boot loader error codes. ................................................................................................... 56 Table 7. File Syntax For All Boot Load Interfaces..................................................................................... 58 Table 8. Available Commands (Debugger Interface)................................................................................. 62 Table 9. Data Memory Write Command ................................................................................................... 62 Table 10. Data Memory Read Command .................................................................................................. 62 Table 11. 16-Bit Program Memory Write Command................................................................................. 62 Table 12. 16-Bit Program Memory Read Command.................................................................................. 63 Table 13. 24-Bit Program Memory Write Command................................................................................. 63 Table 14. 24-Bit Program Memory Read Command.................................................................................. 63 Table 15. Monitor Variables for Executing User Code .............................................................................. 64 Table 16. DM Write Commands to Start Program at 0x0060 .................................................................... 64 ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 5 Appendices Appendix A. System Specification File..................................................................................................... 47 Appendix B. Architecture Description File ............................................................................................... 48 Appendix C. ADMC401 Include File (ADMC401.H) ............................................................................... 49 Appendix D. Constant Include File (Constant.h) ...................................................................................... 52 Appendix E. Macro Include File (Macro.h) .............................................................................................. 54 Appendix F. SROM/EEPROM Boot Loader Protocol................................................................................ 55 Appendix G. UART Boot Loader Protocol ................................................................................................ 59 Appendix H. UART Debugger Protocol .................................................................................................... 61 Appendix I. Synchronous Master Boot Load Protocol ............................................................................... 65 Appendix J. Synchronous Master Debugger Protocol ................................................................................ 66 Appendix K. Synchronous Slave Boot Loader Protocol ............................................................................. 67 Appendix L. Synchronous Slave Debugger Protocol ................................................................................. 68 ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 6 1. Introduction The ADMC401 is a single chip DSP motor controller optimized for standalone motor control applications. The device combines a 26MHz fixed point ADSP-2171 core with on-chip memory, two serial ports, a programmable timer, and a set of on-chip motor control peripherals. In addition, the address and data bus of the DSP core are connected to package leads allowing external memory and peripheral expansion. Together with the list of referenced documents, this manual provides the information necessary to understand and evaluate the processors’ architecture and to develop an ADMC401-based system. 2. Referenced Documents Reference 1. ADMC401 Single Chip DSP Motor Controller Data Sheet, Analog Devices. Reference 2. ADSP-2100 Family User’s Manual, Third Edition, 9/95, Analog Devices. See “ADSP-2100 Family User’s Manual” on the Analog Devices web site at http://www.analog.com/support/product_documentation/dsp_prdoc.html Reference 3. ADSP-2100 Family Assembler Tools & Simulator Manual, Second Edition, 11/94, Analog Devices. See “ADSP-2100 Assembler Tools Manual” on the Analog Devices web site at http://www.analog.com/support/product_documentation/dsp_prdoc.html Reference 4. ADSP-2100 Family C Tools Manual, Second Edition, 11/94, Analog Devices. See “ADSP-2100 C Tools Manual” on the Analog Devices web site at http://www.analog.com/support/product_documentation/dsp_prdoc.html Reference 5. Digital Signal Processing Applications using the ADSP-2100 Family, Volume 1, Analog Devices, 1992. See “Using the ADSP-2100 Family Volume 1” on the Analog Devices web site at http://www.analog.com/support/product_documentation/dsp_prdoc.html Reference 6 Visual DSP Debugger Guide & Reference, First Edition, July 6, 1998, Analog Devices. See “Visual DSP 6.0 Debugger Guide” on the Analog Devices web site at http://www.analog.com/support/product_documentation/dsp_prdoc.html ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 7 3. Upgrade Information Each evaluation kit is shipped with a software version that is fully functional for basic DSP development operations such as assembling, linking, debugging, and serial PROM formatting. This version is powerful enough to fill the needs of most users. Those who want to use the software simulator or write C code may add the standard development software for the ADSP-2100 Family (part number ADDS-21XX-PC-1). NOTE: While it is possible to use the C compiler to generate code for the 2171 based motor control DSPs, the efficiency of this code is questionable. Due to the overhead needed by the C compiler, and the memory constraints of the 2171 based motor control DSPs, C code development is not recommended by the Motion Control Group. The C compiler does not come with direct support for the 2171 based motor control DSPs. In addition to the features found in the software shipped with the evaluation kit the ADSP-2100 Family Development Software adds: · System Builder Define your target system hardware in an architecture description file. The linker and the simulators use this information to know how much memory is in your system, which memory is RAM and which is ROM, which memory is internal to the processor and which is external, and what memory-mapped peripherals you have. You don’t need this tool since the kit software includes an architecture description file for the ADMC401. If you need to modify the file, you can do this simply by editing the file and following the syntax contained therein. You should not need to modify the file unless you want to create your own memory segments. · Simulators Run an instruction level simulation of any ADSP-2100 Family processor. All of the ADSP-2100 Family Simulators provide an interactive, instruction-level simulation, displaying the cycle-by-cycle operation of different portions of the processor and system hardware through a window-based graphical user interface. NOTE: The simulators model only 21xx family general purpose DSPs. None of the motor control peripherals are modeled. · Librarian, C Compiler, C Runtime Library, C Debugger The C level software tools that come with the ADSP-2100 Family development software may be used to develop user code but it is not recommended by the Motion Control Group (see the NOTE above). 4. Getting Started Start by reading the release notes which accompany the evaluation kit you received. They describe what is new in the latest release and how to install the development software on the disks that accompany each board. In addition to the software development tools, documentation and demonstration software will also be installed. Take the time to become familiar with the documentation so that you know where to find information when needed. Also familiarize yourself with the documents referenced by this document. Because the ADMC401 is a combination of an ADSP-2171 DSP core and a set of motor control peripherals, needed technical information may be located in the ADSP-2100 Family User’s Manual, the ADMC401 data sheet, application notes, or in this document. 5. Important Safety Information The Motion Control Debugger should be used in a live system only with extreme caution. Your software should first be developed with an ADMC401 evaluation kit or target board that is not connected to a motor. ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 8 WARNING: PWM SIGNALS TO THE MOTOR REMAIN ACTIVE AT A BREAKPOINT! If you want the motor shut down then use the HALT function to stop your program from executing. The halt function performs a peripheral reset when halting your program. The halt function is executed by selecting Halt from the Debug menu or by clicking the Halt button . DO NOT use breakpoints with a live system because the PWM stage will remain active. ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 9 6. Software Development Figure 1 shows the software development process that a user will follow to create an ADMC401 application. The software tools used, shown in boxes in Figure 1, run on an IBM compatible PC. The System Builder, Assembler, Linker, C Compiler, and PROM splitter, and MAKEPROM utility must be run in a DOS window. The Motion Control Debugger and Simulator are invoked from Windows 95 or Windows NT. Although ADMC401 specific information is contained in this document, the basic tool operations are discussed in the references. The System Builder, Assembler, Linker, and PROM splitter are discussed in Reference 3. The C Compiler is discussed in Reference 4. The Simulators are discussed in Reference 6. The Motion Control Debugger is discussed in this document and in the latest version of its release notes. The MAKEPROM utility is discussed in this document. The tools shown as optional are not needed by most users and, therefore, are not included in the ADMC401 evaluation kit. They can be acquired by ordering the standard development software for the ADSP-2100 Family (part number ADDS-21XX-PC-1). The operation of this optional software is described in Italic font. System Architecture File System Specification File System Builder C Source Files Linker ANSI C Compiler Libraries Executable File Assembler Assembler Source Files STEP 1: Describe Architecture STEP 2: Generate Code Software Simulator ADMCxxx Evaluation Board Motion Control Debugger Target Board MAKEPROM (SROM or EEPROM) Motion Control Debugger STEP 3: Debug Software STEP 4: Final Version for Production User File or Hardware Software Development Tool Hardware Development Tool Optional Software Development Tool PROM Splitter Figure 1. The Software Development Process ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 10 (Optional software) The software development process begins with the task of defining the target system architecture. To do this you use the system builder. You must write a system specification file as input to the system builder; this file describes the target hardware configuration and memory map. The system builder reads the file and generates an architecture description file which passes this information to the linker and simulator. The above step may be skipped if you choose to use the ADMC401 architecture description file that is installed when the development software is installed. The system specification file that was used to create this architecture description file is also installed and can be used as a starting point for your own target hardware. These files are also available in Appendix A and Appendix B. If you do not have the system builder tool and wish to make a change to the .ach file you can edit it since it is a text file. Just mimic the syntax observable within the file. You begin code generation by creating assembly language source code modules. An assembly code module is a unit of assembly language comprising a main program, subroutine, or data variable declarations. Include files are provided in the appendices that contain things like ADMC401 specific constants and macros that can be used in your code. These files can be included in source routines to provide a simple interface to the ADMC401’s motor peripheral registers, and interrupt vector table addresses. These files are also installed along with the development software and used in the tutorial given in this document. They can be found in the main installation directory in a subdirectory called TgtFiles. (Optional software) Each code module is assembled separately by the assembler into ADSP-2171 machine code. Alternatively, the C compiler can be used to generate machine code from C source code. The linker reads the target hardware information from the architecture description file to determine placement of code and data fragments. In the assembly modules you may specify each code/data fragment as completely relocatable, relocatable within a defined memory segment, or non-relocatable (placed at an absolute address). Non-relocatable code or data modules are placed at the specified memory address, provided the memory area has the correct attributes. Relocatable objects are placed in memory by the linker. Using the architecture description file and assembled code modules, the linker determines the placement of relocatable code and data modules, and places all modules in memory locations with the correct attributes (CODE or DATA, RAM or ROM). The linker generates a memory image file containing a single executable program which may be loaded into a simulator, or downloaded to the evaluation kit or target hardware, using the Motion Control Debugger, for testing. (Optional software) The simulator provides windows that display different portions of the hardware environment. To replicate the target hardware, the simulator configures its memory according to the architecture description file. To simulate ADMC401 code you must use the ADSP-2101 simulator because the ADSP-2171 simulator does not support the memory map of the ADMC401. ADMC401 peripherals are not supported on any of the ADSP-21XX family simulators. You can configure the peripheral registers as I/O ports on the simulator to verify that you are initializing them correctly, but you can’t view the operation of the peripherals. For this reason it is recommended that you use the simulator only for basic DSP core programming issues and that you use the ADMC401 evaluation kit with the Motion Control Debugger for true application development. The Motion Control Debugger allows you to download your executable file to an ADMC401 processor board or your own target hardware, to debug your code, and to test your application directly over a standard UART interface. Similar to the simulators, the debugger displays the hardware environment of the ADMC401 through a series of windows. However, with the debugger you have full access to all of the registers and memory on the ADMC401. ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 11 As Figure 1 shows, the software development process is an iterative one as you continue to debug and add to your application code. Once your code is stable you have the option of programming a serial ROM or EEPROM, or a byte-wide EPROM so that your code is boot loaded automatically to the ADMC401 on power-up or reset. The serial ROM boot load interface is provided by the on-chip ROM monitor program. To use this interface you must format your executable file using the MAKEPROM utility which takes your executable file and converts it into a PROM programmer compatible file that has the correct boot loader protocol. Use of the MAKEPROM utility is discussed later in this document. The byte-wide EPROM method of booting takes advantage of the built in boot memory interface of the ADMC401 core. This interface is available when the BMODE and MMAP pins are tied low. To use this interface you must format your executable file using the PROM splitter tool. Use of the PROM splitter is discussed later in this document. In addition to the methods of booting described above you also have the option of booting from an external UART. This interface is also provided by the on-chip ROM monitor and is discussed later in this document. 6.1 Evaluation Kit Software If you have any older versions of the Motion Control Development Tools installed on your computer, you must fully uninstall them before installing this version. If you have any older versions of the Analog Devices 16 bit DSP development tools, such as ADSP 21XX, or VDSP, it is strongly recommended that you upgrade to the latest VisualDSP tool set before installing the Motion Control Development Tools. Whether you are installing from CD-ROM or downloading from the WEB, the executable file, SETUP.EXE, will install the development tools, applications notes, developer’s reference manual, and example software onto your computer. You will be prompted for instructions during the installation. If asked whether you want to install the 16 bit DSP tools, you should answer YES only if you have NOT already installed some version of the Analog Devices 16 bit DSP development tools, such as VisualDSP. If you answer YES, a subset of these tools (assembler, linker, librarian, and prom splitter) will be installed onto your computer. If you already have these tools on your computer, then you should answer NO to this prompt. When prompted to select targets, select the ADMC401 and any other targets that you are installing at this time. After installation you will have a directory structure, similar to the following, added to your PC. This example shows what the directory structure looks like if you choose the default directories. Drive:\Program Files\Analog Devices\Motion Control Development Tools Main installation directory The following subdirectories are contained in the main installation directory. Documentation\ReleaseNotes Release notes (if applicable) Documentation\ReferenceManuals Developer's reference and user manuals Documentation\ApplicationNotes Application notes (if applicable) Documentation\DataSheets Data sheets Examples Demonstration/Evaluation software Bin Debugger executables TgtFiles Target specific files (.h, .ach,.sys) SrcLib Source code for library functions WindowFiles Saved windows configurations Uninstall.isu Used to uninstall software ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 12 21XX\Makeprom.exe Makeprom utility program If you install the 16 bit tools, the files listed below will have been installed. In addition, your autoexec.bat file will have been updated so that your PATH variable includes the directory: Drive:\Program Files\AnalogDevices\Motion Control Debugger\21XX\ 21XX\Spl21.exe ADSP-21XX Family Splitter 21XX\Asm21.exe ADSP-21XX Family Assembler 21XX\Ld21.exe ADSP-21XX Family Linker 21XX\Asmpp.exe ADSP-21XX Family Pre-Processor 21XX\Asm2.exe ADSP-21XX Family Assembler Driver 21XX\Lib21.exe ADSP-21XX Family Librarian NOTE: For more example software and the latest documentation always consult the Analog Devices Motor Control website at http://www.analog.com/motorcontrol 6.2 Getting Started with the Motion Control Debugger The following steps will help you get started using the Motion Control Debugger. They can be performed alone, or in conjunction with the tutorial in section 16. The Debugger provides a toolbar, a menu, and several shortcut keys. Many of the steps listed below describe two or three different ways of doing the same thing. This is not meant to confuse, but to allow you to choose the method with which you are most accustomed. Install the Motion Control Development Tools. Refer to the release notes that came with the installation CD. Connect the ADMC401 board to a communication port on your computer using a standard 9 pin male-tofemale serial cable. Apply power to the target board, and press the hardware-reset button. Run the Debugger. To start the debugger under Windows 95/NT select it from the start menu (Programs-> ADI Motion Control -> Debugger). The Target Selection Dialog Box (Figure 2) will appear, displaying default values for the communications port, baud rate, clock (crystal) frequency, target, and platform. Figure 2. Debugger Target Selection Dialog Box Create New Platform Delete Platform Platform Name ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 13 Select a Target. Use the Debug_Target field to select the Debug Target that you wish to communicate with. The Platform field enables you to save multiple configurations for the same target, by defining new platforms, in case you have more than one evaluation board for the same chip. Select the COMM PORT that is connected to the processor board, and select the desired BAUD RATE for the port. Select the appropriate CLKIN RATE, and click OK. If you select CANCEL, you will exit the Debugger. Attach to the Target. The Debugger will now attempt to attach to the target using the parameters you have selected. When the Debugger has successfully attached to the target, the disassembly window (shown below) will appear with the start location at 0x0060 highlighted. This is the point at which user code will begin execution when a run or single step command is executed, so the beginning of your program must be linked at 0x0060. You now have full emulation capability of your target design. Figure 3. Debugger Disassembly Window The greater-than sign (>) next to the address field of a code line represents the processor’s program counter (PC) register. The program counter (PC) register points to the instruction that the processor is going to execute next. The processor status is shown at the bottom of the main window. The processor is currently in the state “Reset”. Program Counter Processor Status ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 14 Load a Program. A DSP program may consist of program memory (PM) blocks, data memory (DM) blocks, and flash program memory (FM) blocks. To load a program containing these block types, select Load Program from the File menu and navigate to the directory containing your executable file (.exe). Double click the desired executable program and the debugger will load the PM Blocks, DM Blocks, and symbols. Figure 4. Loading an Executable File View the User Program. To view the program, use the page up, page down, up arrow, and down arrow keys in the disassembly window. If the disassembly window hides behind another window, you can bring it to the front by selecting Disassembly from the Window menu, or by clicking the Disassembly Window button . To go back to displaying the current program counter (PC) address, press the F12 key. Search for a Symbol. To find the line of code where a symbol is defined, select Find from the Search menu, or press Ctrl- F, or click the Find button , and then enter the symbol name. Figure 5. Using the Find Text Window ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 15 The disassembly window will display the code where that symbol is defined or referenced, without modifying the program counter (PC) register. To find the next occurrence of the symbol, select Find Again from the Search menu, or press the F3 key, or click the Find Again button . Go To a Symbol. To select from the list of all symbols, and display the code where that symbol is defined or referenced, select Go To from the Search menu, or press Ctrl-G, or click the Go To button , and then click the Browse button. Select the symbol from the list displayed. The disassembly window will display the code where that symbol is defined or referenced without modifying the program counter (PC) register. Figure 6. Finding Symbols in the Program Figure 7. Browsing the List of Symbols ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 16 Go To an Address. To display the code at a particular address, select Go To from the Search menu, or press Ctrl-G, or click the Go To button , and then enter the desired address. Hexadecimal numbers must be prefixed with “0x”, and octal numbers with “0”. Decimal numbers must be entered starting with the most significant non-zero digit. Display Additional Files. To display a file in its own window, select Open from the File menu or click the Open button , and then navigate to the desired file. Set a Breakpoint. To set a breakpoint, select Breaks from the Debug menu and add the desired line of code to the list displayed, or click the Break button while the desired line of code is highlighted. If you prefer a shortcut method, double click the desired line of code, or move the cursor to the line and press the F9 key. Clear a Breakpoint. To clear a break point, select Breaks from the Debug menu. Either delete the desired line of code from the list, or click the Toggle Break button with the line of code highlighted. If you prefer a shortcut method, either double click the line of code where the break point is set, or move the cursor to the line and press the F9 key. Clear All Breakpoints. To clear all break points, select Breaks from the Debug menu and then select Clear All and OK, or simply click the Clear Breaks button . Figure 8. The GoTo Address Box Figure 9. Selecting Breaks from the Debug Menu Figure 10. The Breaks Dialog Box ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 17 Run the Program. To run your program, select Run from the Debug menu, or press the F5 key, or click on the Run button . Observe the processor status at the bottom of the main window change from “Reset” to “Running”. WARNING! PWM SIGNALS TO THE MOTOR REMAIN ACTIVE AT A BREAKPOINT! If you want the motor shut down then use the HALT function to stop your program from executing. The HALT function performs a peripheral reset when halting your program. The HALT function is executed by selecting Halt from the Debug menu or by clicking the Halt button . DO NOT use breakpoints with a live system, as the PWM stage will remain active. Figure 11. Running the Program ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 18 Halt the Program. To halt a program while it is running, select Halt from the Debug menu, or press the F6 key, or click the Halt button . Observe the processor status at the bottom of the main window change from “Running” to “Halted”. The disassembly window will display the location at which your code halted. The greater-than sign signifies the location in the program counter (PC) register. Single Step. To single step through your code, select Step Into from the Debug menu, or press the F11 key, or click on the Single Step button . Observe the processor status change from “Halted” to “Stepping” to “Halted” again. Figure 12. Halting and Single-Stepping Figure 13. Selecting a Register from the Registers Menu ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 19 View Registers. To view register values while debugging your code, select them from the Register menu. Register values are updated each time the program is halted or a breakpoint is reached. Stacks are also selected from the Register menu. Figure 14 shows an example of viewing the PWM registers. For a more customized register window, select Custom from the Register menu. This allows you to select the specific registers you want to view and places them all in the same window. Some targetspecific registers are available only from Custom selection. View Memory. Viewing of program or data memory can be selected from the Memory menu. Clicking the right mouse button while the cursor is in a memory window will bring up a menu that allows you to change the format of the data displayed. Figure 16 shows data memory displayed in fractional format, as the user is selecting hexadecimal format. Figure 14. Viewing the PWM Registers Figure 15. Viewing the Program Memory (PM) ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 20 You can also select tracking from this menu. This allows you to track the data pointed to by a DAG or PC register. View Memory Map. To see the memory map for the target you are running select Memory Map from the Memory menu. Dump Memory. To dump memory to the output window or to a file, select Dump from the Memory menu and fill in the dialog box. Figure 16. Selecting Format of Data Memory Figure 17. Viewing the Memory Map Figure 18. Dumping Memory ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 21 Fill Memory. To fill memory with a specified value, select Fill from the Memory menu and fill in the dialog box. Memory can also be filled from a file. Plot Memory. To plot memory, select Plot from the Memory menu and fill in the dialog box. The plot will be displayed in its own window. Clicking the right mouse button while the cursor is in a plot window will bring up a menu that allows you to configure the plot in different ways. Software Reset. To execute a soft reset of the processor, select Reset from the Debug menu, or press the F7 key, or click the Reset button . Observe the processor status change to “Reset”. Restart. To restart your program, select Reset from the Debug menu and then Run. Reload. To reload the most recently loaded executable file, select it from the most recently loaded list found on the File menu. Alternatively, you can press the F4 key. There are up to 4 files listed on the most recently loaded list. Pressing the F4 key will always load the first file on that list. Figure 19. Fill Memory Figure 20. Plot Memory Configuration Dialog Figure 21. Plot Memory Output ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 22 Display Version. To display which version of the Motion Control Debugger you have installed, select About Debugger from the Help menu, or click the About button . Exit the Debugger. To exit the debugger, select Exit from the File menu, or press the Ctrl-E key combination. NOTE: The reset and halt functions perform a peripheral reset which puts the peripheral blocks in their power-up state (disabled). Loading an executable file will also perform a peripheral reset. HotKey Function F3 Find again F4 Reload most recently loaded program F5 Run F6 Halt F7 Software reset F9 Toggle breakpoint F11 Single step F12 Update all windows Ctrl-L Load program Ctrl-O Open file Ctrl-E Exit debugger Ctrl-F Find Ctrl-G Goto address or symbol Table 1. Summary of Debugger HotKeys 6.2.1 Saving the Debugger Windows Configuration The debugger will automatically save the current configuration of all open windows before it exits. The next time you start the debugger the windows will be restored to the way you last left them. In addition, it is possible to save multiple window configurations. For example, you could have one configuration that you use to debug the PWM portion of your application, and another that you use to debug the ADC portion. The debugger saves the windows configuration in a motion control window (.mcw) file. The default file used is “default.mcw”. All window configuration files are saved in the WindowFiles directory found in the main installation directory. To force a save of the current windows configuration select SaveWindows from the File menu. The current windows configuration will be saved to the currently selected file. To save to a different file select SaveWindowsAs from the File menu. This will change the currently selected file to this new file you’ve chosen and then save the configuration. You can save multiple window configuration files in the WindowFiles directory. To load a previously saved window configuration file select LoadWindows from the File menu. The filename for the currently selected window configuration is saved in the registry so it can be reloaded the next time the debugger is started. Figure 22. Motion Control Debugger Version ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 23 NOTE: Do not remove or edit the currently selected .mcw file in the WindowFiles directory. If you do the debugger might crash or you might receive a warning that the windows configuration file cannot be opened. If this happens you must reinstall the debugger software. This will restore the default.mcw file. Motion Control Windows files (.mcw) are not portable between versions of the debugger software. If you upgrade to a new version of the debugger software you must recreate your windows configuration. Because of this requirement the debugger software installation script will delete all .mcw files from the WindowFiles directory and copy in the new default.mcw file. 6.2.2 Modifying Your Program Directly From the Disassembly Window The disassembly window shows the contents of program memory in disassembled format. When you load your program executable (.exe) file you will see it displayed in the disassembly window. The standard method of changing your program is to edit the original source code and then assemble, link, and reload the file with the debugger. Alternatively, you can modify your program by typing assembly language directly into the disassembly window. This can be extremely helpful for making quick changes while testing. For example, if you are trying to find the correct value for a delay loop it is much quicker and easier to enter the new constant directly into your program in the disassembly window and rerun the program rather than to recompile and reload your code each time you want to try a new value. Once the correct value has been determined you can enter it into your source code file. As another example, suppose you suspect a certain line of code might be causing a bug in your program. You can quickly modify that line of code or enter a NOP in that location and rerun the program. To reverse the changes you made simply reload your executable file using the F4 key. Remember that any changes you make in the disassembly window will be lost if you reset or power down the processor, or if you load another program. It’s a good idea to keep your source files up to date with any changes you want to keep. For a quick record of the changes you have made you can dump program memory to a file. Select Assembly as the format and the file will contain the code in disassembled format similar to the disassembly window. When typing in the disassembly window you can use any symbols that are currently loaded. This means you can call routines and load variables by name rather than address. You can also refer to any of the memory mapped peripheral registers by name. You cannot refer to symbols directly until you have loaded a program because that’s when the internal symbol table used by the debugger is created. 6.2.3 Automatic Program Exit Function Typically, when the debugger runs a user’s DSP program the only way to pass control back to the debugger is by hitting a breakpoint or by executing a Halt from the debugger. The user usually creates an infinite loop in the program so that the DSP will continue to run until the Halt is executed. As another option, you may insert an automatic exit back to the debugger by jumping to the Exit library function. Exit.dsp performs the same DSP functions as the debugger’s Halt function so it’s effect is to return control back to the debugger automatically when the user’s program has finished. You will see the debugger halt when this happens. If you try to continue running the program it will just return back to the debugger immediately. You can execute a reset or reload the program to run it again. To use the Exit function, assemble and link the exit.dsp file (found in the SrcLib directory) with your code. You can then insert a JUMP EXIT wherever you wish the program to return to the debugger. ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 24 6.2.4 Troubleshooting The following is a list of remedies to problems you may encounter when using the Motion Control Debugger. a. If the debugger is not responding, your target could be in run mode. Try selecting Halt from the Debug pulldown menu. b. If the debugger is hung, try resetting the target board. If the debugger is not responding, invoke the ‘Close Program’ dialog box by pressing Alt-Ctrl-Delete, select Debugapp, and click ‘End Task’. Also, End any tasks called “Motion Control Debugger”. Next press Reset on the target board and restart the debugger. c. If the debugger hangs, you could be writing to a part of data memory that is being used by the debugger. See the ADMC401 memory map in this document which shows the data memory locations that are reserved by the monitor and make sure you are not using that memory. If you created a .map file with the -x option when you linked your program, it will show you where your program resides in memory. d. The debugger uses the SPORT1 transmit and receive interrupts. Keep them enabled in your code and do not modify the corresponding interrupt vectors at locations 0x0020 and 0x0024. Failure to do this can cause the debugger to hang. e. The debugger also uses locations 0x0001 and 0x0002 in the interrupt vector table. Do not modify these locations, or the debugger will hang. f. If the debugger frequently hangs, and your PC is located in an electrically noisy environment, try lowering the baud rate. This can be done in the Target Selection Dialog Box, when you first start the Debugger. Lowering the baud rate will slow down the debugger, but may alleviate the problem. 6.2.5 Error Messages The following is a list of error messages that may be encountered while running the debugger. Following each error message is an explanation for the error and possible steps to take to correct the problem. If the problem can not be fixed contact the Motion Control Group for help. ERROR_MCG0001:: Com line status change or power failure The debugger has detected a change in the serial communications. Exit the debugger. If the debugger is not responding, invoke the ‘Close Program’ dialog box by pressing Alt-Ctrl-Delete, select Debugapp, and click ‘End Task’. Reset the board, and then restart the debugger. ERROR_MCG0002:: Target communication not established The debugger is unable to communicate with the ROM Monitor Program. Exit the debugger. If the debugger is not responding, invoke the ‘Close Program’ dialog box by pressing Alt-Ctrl-Delete, select Debugapp, and click ‘End Task’. Check all connections, reset the board, and then restart the debugger. If you have the debugger installed for multiple targets make sure you are running the correct one. Also, make sure the clock frequency for the board is correct. The clock frequency is displayed in the target selection box when you start the Motion Control Debugger. ERROR_MCG0003:: Serial line status error. Check continuity of serial cable and connections. The wrong com port could be connected to the target. The serial cable could be unconnected or broken. A board connector could be broken. Exit the debugger. If the debugger is not responding, invoke the ‘Close Program’ dialog box by pressing Alt-Ctrl-Delete, select Debugapp, and click ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 25 ‘End Task’. Verify the connection, reconnect or fix the serial line and reset the board. Re-run the debugger and verify the comm port selections in the target selection box. ERROR_MCG0004:: Unable to open com port The com port is being used by another application, or by a previous debugger session that hasn’t `terminated properly. Exit all other applications that might be using the com port. Exit the debugger. If the debugger is not responding, invoke the ‘Close Program’ dialog box by pressing Alt-Ctrl-Delete, select Debugapp, and click ‘End Task’. If there are other occurrences of Debugapp, exit them the same way. End any tasks with the name “Debugapp” or “…Motion Control Debugger…”. Reset the board then restart the debugger. ERROR_MCG0005:: Registry parameters not found The registry has been corrupted. Uninstall, then Reinstall the development software on your PC. ERROR_MCG0006:: Failed to open registry The registry has been corrupted. Uninstall, then Reinstall the development software on your PC. ERROR_MCG0007:: Detected a board reset or power failure. You have performed a H/W reset of the board, or there was a power failure, while the debugger was running. Acknowledge the error windows that pop up, then select Reset from the debug menu. If the debugger is not responding, invoke the ‘Close Program’ dialog box by pressing Alt-Ctrl- Delete, select Debugapp, and click ‘End Task’. Reset the board, then restart the debugger. ERROR_MCG0008:: Error loading the monitor tasks The development software might be corrupted. Try reinstalling the software on your PC. ERROR_MCG0009:: Invalid target response The debugger can’t reconnect with the ROM Monitor Program after running a user program. Make sure you have the SPORT1 interrupts enabled in your code, you do not corrupt the SPORT1 interrupt vectors, and you do not corrupt any of the SPORT1 configuration registers. ERROR_MCG0010:: Unable to read target memory while target is running You’ve tried to access memory while your program is running. Halt the program and try again. ERROR_MCG0011:: Unable to write to target memory while target is running You’ve tried to access memory while your program is running. Halt the program and try again. ERROR_MCG0012:: Unable to find the DSP monitor task files The files might be corrupted. Reinstall the development software on your PC. ERROR_MCG0013:: Target is running Cannot perform operation while the target is running. Halt the target first. ERROR_MCG0014:: Target communication not established after reset The debugger is unable to communicate with the ROM monitor program. Exit the debugger. If the debugger is not responding, invoke the ‘Close Program’ dialog box by pressing Alt-Ctrl-Delete, select Debugapp, and click ‘End Task’. Reset the board, and then restart the debugger. If you have the debugger installed for multiple targets make sure you are running the correct one. ERROR_MCG0015:: Target communication Failure The debugger is unable to communicate with the ROM Monitor Program using the parameters specified in the target selection box which appears when you start the debugger.. Exit the debugger. If the debugger is not responding, invoke the ‘Close Program’ dialog box by pressing Alt-Ctrl-Delete, select Debugapp, and click ‘End Task’. Reset the board, and then restart the ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 26 debugger. If the problem persists it could be due to noise or a hardware fault. Try lowering the baud rate in the target selection box, which appears when you start the debugger. ERROR_MCG0016:: Communications Failure. The debugger cannot communicate with the target board. The most common cause of this is failure to press the hardware reset button, or to cycle power on the target before starting the debugger. Each time you start the debugger you must first reset the target. If you get an “ERROR_MCG0003:: Serial line status error” prior to this error, then there is a problem with the com port connection. The serial cable might be disconnected or you might be configured for the wrong com port. Verify the communication parameters in the target selection box which appears when you start the debugger.. Also, check the serial cable connection. This error can also occur if the SPORT1 interrupts become unmasked in the IMASK register or if the SPORT1 interrupt vectors at locations 0x20 and 0x24 are destroyed (for example if you load something at these locations). This error can also occur if you accidentally reset the target while the debugger is running. Another possible cause is noise on the serial line, which can happen when you run the debugger in a fully loaded motor application. The debugger can sometimes recover from this error. Try pressing the h/w reset button and then clicking Retry. This combination may have to be performed several times to recover. If the debugger is not responding, invoke the ‘Close Program’ dialog box by pressing Alt-Ctrl-Delete, select Debugapp, and click ‘End Task’. Reset the target, and then restart the debugger. ERROR_MCG0017:: The target never acknowledged the halt! Possibly the SPORT1 interrupts were disabled by the user program. When you issue a halt command to the debugger (click the Halt button), the debugger sends a halt command to the target over the SPORT1 serial connection. In order for the target to receive this command, the SPORT1 interrupts must be enabled and the SPORT1 received interrupt must be serviced. Possibly your program masked the SPORT1 interrupts in the IMASK register. This is a common problem. To run with the debugger your program must keep the SPORT1 interrupts unmasked in the IMASK register (IMASK=6) and keep the SPORT1 interrupt vectors at locations 0x20 and 0x24 uncorrupted. If your program spends a lot of time in interrupt service routines, you should add the line “IMASK=6” at the top of your interrupt service routine. This will override the automatic setting of IMASK=0 that is done when a non-nested interrupt is serviced. This will allow the debugger to halt the target in an interrupt service routine. Another possible cause of this error may occur if your program spends so much time in higher priority interrupt service routines that the SPORT1 receive interrupt is never serviced. 6.3 Programming Serial PROMs with MAKEPROM By using the Makeprom utility and a standard PROM programmer, a user’s code may be programmed into a serial PROM for boot loading the ADMC401 at reset. The Makeprom utility will convert an executable file (.EXE) into a binary file (.DBS) for use with the PROM programmer. The binary file created is automatically formatted to work with the boot loader of the ADMC401. The boot loading protocol is compatible with the Xilinx XC17128E SROM, the Atmel AT17C128 EEPROM, and the Microchip 37LV128 EPROM. The Makeprom Utility (MAKEPROM.EXE) is installed with the Motion Control Development Tools software. It runs from an MS-DOS window similar to the other development tools. Follow these steps to create a serial device containing your executable image: 1. Your executable code must be linked to start executing at the beginning of user program memory (0x0060), to which the boot loader will jump after loading the executable program. Consequently, you are required to have a minimum of 1 block of code linked into program memory for the boot loader to succeed. You are not required to have data linked into data memory. However, if this is the case, the boot loader will automatically write 4 zeros at the start of data memory (0x3800). NOTE: Do not try loading the interrupt vector table during a boot load. This would overwrite the default interrupt vector ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 27 table, which is needed by the boot loader. Instead you should modify the interrupt vector table from within your program by using the library routine PUT_VECTOR. (See the putvctr.dsp file in the SrcLib directory. 2. Run Makeprom which has the following syntax: usage: Makeprom -i -t [-o ] [-c] -i Input file -t Target (e.g. ADMC401) -o Output file (default = input_file.dbs) -c Display checksums -x Create text file. (default = binary) -h Header disable. Suppresses SROM/EEPROM header -m Mirror image disable. Data will be MSB…LSB. 3. Load the output file into your PROM programmer and select one of the devices listed above. The data format of the file is absolute binary. NOTE: Make sure the polarity option is set to program an active low reset ( RESET /OE). 4. Program the device and place it in the SROM/EEPROM socket of the processor or target board. 5. On power-up or reset, your executable code will be loaded at the start of user memory and executed. 6.4 Using Include Files in Your Code Include files are useful for reusing code and data items that are shared between programs without having to duplicate them in each program. The ADMC401 development software contains a number of include files which can be used throughout your code. For example, the ADMC401.h file contains constants set equal to the memory-mapped registers and interrupt vector table addresses. If you include this file you can refer to the ADMC401 registers and interrupt vector table locations by name instead of by address. The code snippet below illustrates how to use the ADMC401.h include file for setting up the PWMSYNC interrupt vector table entry. PWMSYNC_INT_ADDR and PUT_VECTOR are constants defined in ADMC401.h. #include ; Initialize_Interrupts: I4 = PWMSYNC_INT_ADDR; MR0 = ^YOUR_PWMSYNC_ISR CALL PUT_VECTOR; IMPORTANT: The last line of an include file must contain a carriage return or subsequent include statements will be ignored. Also, always use the #include directive instead of the .INCLUDE directive. #include allows you to put precompiler directives in your include files while .INCLUDE doesn’t. ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 28 7. ADMC401 Hardware Overview The ADMC401 uses several ADSP-21XX family resources including: an ADSP-2171 core, 2K of on-chip program RAM, 2K of on-chip program ROM, 1K of on-chip data RAM, two serial ports, and a programmable timer. The operation of each of these units is described fully in Reference 2. 7.1 Motor Control Peripheral Registers In addition to the ADSP-2171 core peripherals, the ADMC401 contains a set of motor control peripherals that are controlled through registers that are memory-mapped into the core’s data memory. The operation of the peripherals is described in Reference 1. 7.2 Address and Data Bus The ADMC401 provides the 14-bit address bus and 24-bit data bus on external pins for memory and peripheral expansion. See Reference 1 for details about this capability. ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 29 8. Memory Map 8.1 (MMAP = BMODE= 1 Configuration) The following table shows the memory map for the ADMC401 evaluation board when the MMAP and BMODE pins are both connected to a logic 1. This is the mode that enables the ROM monitor Programs and thus allows use of the Motion Control Debugger, as well as programs to be boot loaded from serial ROM or EEPROM. If you are booting the ADMC401 in any other mode other than MMAP = BMODE = 1, consult References 1 and 2 for proper operation. There are a few memory restrictions when using the evaluation board in the MMAP = BMODE = 1 configuration. For proper operation of the Motion Control Debugger and SROM boot loader, never link programs into the Data Memory RAM locations marked “Reserved by Monitor”. In addition, the debugger uses locations 0x0001, 0x0002, 0x0020, and 0x0024 of the interrupt vector table. Do not modify these locations when running with the debugger. Program Memory Address Range Memory Type Function 0x0000 - 0x005F Internal RAM Interrupt Vector Table 0x0060 - 0x07FF Internal RAM User Program Space 0x0800 - 0x0FFF ROM Monitor 0x1000 - 0x3FFF External RAM User Program Space Data Memory Address Range Memory Type Function 0x0000 - 0x1FFF External RAM User Data Space 0x2000 - 0x23FF Memory Mapped Peripheral Registers 0x2400 - 0x37FF External RAM User Data Space 0x3800 - 0x3B5F Internal RAM User Data Space 0x3B60 - 0x3BFF Internal RAM Reserved by Monitor 0x3C00 - 0x3FFF Memory Mapped DSP Core Registers Table 2. ADMC401 Evaluation Board Memory Map (MMAP = BMODE = 1 Configuration) 8.2 (MMAP = BMODE= 0 Configuration) When the MMAP and BMODE pins are tied low, the processor boots from an external EPROM using its boot memory interface. In this mode the on-chip ROM is disabled, so there is no access to the monitor program. The memory map when running in this mode is identical to that shown in Table 2, except that there is no DM RAM reserved by the monitor, because the monitor is not running. In this mode the user application has access to the entire PM and DM address space. ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 30 9. On-Chip ROM Monitor Operation The ADMC401 has a 2K ROM which contains a monitor program that supports boot loading and debugging of user code. This monitor only operates when MMAP=BMODE=1. This section describes the functions of the on-chip ROM monitor. 9.1 Power-up / Reset Sequence When the MMAP and BMODE pins are tied to a logic 1, the on-chip ROM is enabled. A reset starts execution of the monitor program at location 0x800. 9.2 SPORT1 The ADMC401 has two synchronous serial ports, SPORT0 and SPORT1, that support a variety of serial data communication protocols. Both SPORTs are identical to the serial ports described in Reference 2 and so can be programmed by user code to support the timing and framing options described therein. In addition, the ADMC401 contains added circuitry on SPORT1 that, when combined with software in the ROM monitor, will emulate a UART. The monitor program contained in the ADMC401 ROM uses SPORT1 as it’s interface to external devices for booting and debugging user code. After boot loading, a user application can reconfigure SPORT1 for general serial port operation. 9.3 The ROM code Monitor The monitor program's basic function is to do one of two things at reset: 1. Download and execute a user program. Four boot load protocols are supported: · Synchronous EEPROM/SROM. · Asynchronous UART (SCI compatible) with Autobaud feature. · Synchronous Master (internal SCLK) with Autobaud feature. · Synchronous Slave (external SCLK) with Autobaud feature. 2. Or, enter the debugger interface in which commands are received and processed from a host. There are three protocols supported in this mode: · Asynchronous UART (SCI compatible) with Autobaud feature. · Synchronous Master (internal clock) with Autobaud feature. · Synchronous Slave (external clock) with Autobaud feature. The Analog Devices Motion Control Debugger uses the UART protocol to connect to the debugger interface on the ADMC401. Typically, an application is developed and debugged using the Motion Control Debugger. Once the application is stable, it is programmed into serial ROM (SROM), EEPROM, or some other external device and boot loaded to the ADMC401 on reset. For users of the Motion Control Debugger to initially download and debug their programs, it is not necessary to understand the UART protocol used because the communications between the debugger and the ADMC401 are transparent to the user. Also, for users that will be programming the supported SROMs or EEPROMs for boot loading their programs, it is not necessary to understand the synchronous protocol used because the MAKEPROM utility will automatically format a user’s executable file into the correct syntax for this protocol. But for those who want to boot load a program or use the debugger interface from some other external device, the protocols listed above are further specified below and in the appendices. ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 31 At startup the monitor first performs initialization and copies a default interrupt vector table to locations 0x0000 - 0x005F of program memory RAM. The section on interrupt operation in this document contains information about how the ADMC401 processes interrupts and what is provided for a default interrupt vector table by the ROM monitor. Following initialization, the monitor tries to boot load and execute a user program from an SROM or EEPROM connected to SPORT1 through the DR1A pin. If successful, execution of the user’s code then starts at location 0x0060. The SROM/EEPROM boot load interface is discussed further in Appendix F. If the monitor fails to detect an SROM or EEPROM on DR1A, it switches the input on SPORT1 to the DR1B pin and waits to receive a two byte sequence from an external device. The two byte sequence tells the monitor which protocol to use, at what baud rate, and whether it is to attempt a boot load or to run the debugger interface. These two bytes are received asynchronously (no clock is required), MSB first. The first byte in the sequence is called the autobaud byte. It is used to calculate the baud rate at which to communicate with the external device. This is known as the autobaud feature. The external device must send an autobaud byte equal to 0x70 at the desired baud rate. The ADMC401 will lock onto this baud rate automatically and initialize SPORT1 to communicate at this rate. The maximum baud rate that the ADMC401 can lock onto is 300 kHz for a 26 MHz CLKOUT. The second byte in the sequence is called the header byte. It tells the monitor what type of interface it is connected to. The protocols supported and their corresponding two byte sequence are listed in Table 3. Autobaud Byte Header Byte Protocol 0x70 0x70 UART Debugger Interface 0x70 0x71 UART Boot Load (SCI compatible) 0x70 0x72 Synchronous Master Debugger Interface (Internal SCLK) 0x70 0x73 Synchronous Master Boot Load (Internal SCLK) 0x70 0x74 Synchronous Slave Debugger Interface (External SCLK) 0x70 0x75 Synchronous Slave Boot Load (External SCLK) Table 3. Two Byte Sequence for each Monitor Supported Interface Once the monitor has received the header byte it will configure SPORT1 for the correct protocol and then will either execute the boot loader or the debugger interface depending upon which interface has been selected. The required timing from reset of the two byte sequence in order for an external device to connect to one of the interfaces described in Table 3 is shown in Figure 23. The example shown is for the UART boot load interface. All other interfaces are the same except the corresponding header byte, and the slave interfaces would use an external SCLK. Note that this is not the same as the timing for the SROM/EEPROM boot load interface which is shown in Appendix F. ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 32 RESET pin 01110000 01110001 0101 2000 cycles SCLK1 DR1B pin (data from external device) Required timing Allow SROM boot to fall Send autobaud byte Allow monitor to set baud rate Send header byte Allow monitor to synch with interface Send rest of data 0x70 0x71 #PM blocks, PM start address, etc. Monitor turns on SCLK for SROM boot attempt SROM boot attempt times out Monitor turns internal SCLk on for UART boot load cycles CLKOUT SCLK 10 x cycles CLKOUT SCLK 10 x cycles CLKOUT SCLK 10 x cycles CLKOUT SCLK 10 x Example Shown: UART Boot Load. Timing of the byte sequence is the same for all interfaces. Figure 23. Required Timing for Interfacing to an External Device The debugger interface provides full emulation-like capability of the ADMC401 without the use of a separate emulator pod. Through a set of commands an external device can read and write the ADMC401’s registers and memory, and can control the execution of code on the processor. Each boot load interface allows a user’s program to be loaded and executed from an external device at reset in much the same way as the SROM/EEPROM boot loader interface. Detailed descriptions for each of the protocols described in this section can be found in Appendix G through Appendix L. The operation of the monitor at reset is summarized in the following flowchart. ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 33 A RESET Configure SPORT1 for SROM boot SCLK1 = CLKOUT (1.0 MHz @ 26 MHz) Reset SROM (toggles RFS1 Load program/data memory from SROM Compute checksum on program and data Compare checksum to that received from SROM SROM Boot Load SROM boot load successful? Valid Header Byte Received?* Run User Program (Execution starts at 0x0060) Output Error Code on DT1** No Turn off SCLK1 Switch input to DR1B Receive 2 Byte Autobaud Sequence 1st byte: Autobaud byte = 0x70 Calculate baud rate on 1st byte 2nd byte: Header byte SROM boot load times out? No Yes No Yes * See Table 3. ** See Table 6 in Appendix F: SROM Boot Loader Error Codes. B Yes ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 34 *- See Appendix H. ** - See Table 7 Figure 24. Monitor Operation at Reset . A UART Debugger Interface Header Byte = 0x70 Header Byte = 0x71 UART Boot Loader Header Byte = 0x72 Synchronous Master Debugger Interface Header Byte = 0x73 Synchronous Master Boot Loader Header Byte = 0x74 Synchronous Slave Debugger Interface Header Byte = 0x75 Synchronous Slave Boot Loader SCLK1 on at 3 times autobaud rate SCLK1 on at 3 times autobaud rate SCLK1 on at autobaud rate SCLK1 on at autobaud rate SCLK1 is external SCLK1 is external Monitor Serial Communication Loop Executed* Monitor Serial Communication Loop Executed* Monitor Serial Communication Loop Executed* Load file through SPORT1 configured as UART. Use load file syntax.** Run User Program at 0x0060 PM or DM Checksum Failure? B Load file through SPORT1 configured as SPORT. Use load file syntax.** Run User Program at 0x0060 PM or DM Checksum Failure? Load file through SPORT1 configured as SPORT. Use load file syntax.** Run User Program at 0x0060 PM or DM Checksum Failure? Yes Yes Yes No No No Echoes Header Byte Echoes Header Byte ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 35 10. Source Code Library The SrcLib directory, contained in the main installation directory of the Motion Control Development Tools software, contains source code for a number of math and motor control functions that can be called from user programs. Each library routine contains a commented header which describes the function as well as the registers it uses. To use a library function, assemble and link the source code file (.dsp) together with your program files and call the label, given in the .ENTRY directive at the top of the file, from your program. In addition to the source code being available in the SrcLib directory, the PUT_VECTOR routine, used to insert vectors in the interrupt vector table, is also contained in the on-chip ROM. You can call PUT_VECTOR by including the admc401.h file in the routine where the call is made. A constant is declared in the .h file which contains the address of PUT_VECTOR in the ROM. The PUT_VECTOR routine source code is provided in the SrcLib directory for those who wish to link and call the routine from RAM. NOTE: The files in this directory are provided for backward compatibility for users of the originally released part who may already be using these routines. In many instances these files have been obsoleted by new files, available on the web, and so are not supported. For all new users who want the latest library routines, consult the application code page of the Analog Devices Motor Control website at http://www.analog.com/motorcontrol. ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 36 11. Booting from External EPROM with MMAP=BMODE=0 In addition to booting the ADMC401 using the interfaces provided by the on-chip ROM monitor program, the ADMC401 may also be booted from an external byte-wide EPROM using its built-in boot memory interface. To use the ADMC401 in this mode connect the MMAP and BMODE pins to a logic 0. This disables the on-chip ROM and enables the built-in boot memory interface of the processor. When in this mode up to 15K of program and/or data memory locations can be loaded from EPROM at reset. Following the boot load procedure execution of the user program is automatically started at address 0x0000 in PM RAM. A low cost byte-wide EPROM such as the 27C64 or 27C512 can be used in this mode. It is important to note that because the on-chip ROM monitor is disabled in this mode, you do not have access to any of the debug capabilities provided by the monitor such as the Motion Control Debugger. Therefore, use this mode only as an alternative to the other booting methods, for boot loading final applications in an embedded system. To format your program into a file that can be burned into EPROM you use the PROM splitter tool. The PROM splitter formats your program into the proper syntax for the boot memory interface, and creates a file in the right format for burning into an EPROM. To format your program invoke the PROM splitter with the following command: SPL21 imagefile PROMfile -loader [-s] [-i] where: imagefile is your executable file (the .EXE output from the linker) PROMfile is the output file to be burned into the EPROM The -loader switch enables multiple page boot loading. The -s and -i are optional file format switches that create an output file in Motorola S record or Intel Hex record format respectively. If no switch is given the default is Motorola S record. Using the -loader switch causes the PROM splitter to scan the input .EXE file for external PM RAM segments and internal or external DM RAM segments. It creates as many boot pages as necessary to store the code and data, regardless of how many pages are declared in the system architecture file. In addition, small loader routines are placed at the beginning of each page. After page 0 is booted, code and data segments are copied by the page 0 loader routine to the appropriate destinations. Page 0 then forces a software boot of page 1, whose loader performs the same operation. Successive boots continue until your entire program is loaded, up to a maximum memory space of 15K locations. The amount of program and data memory to be loaded from EPROM is limited in this mode to 15K total locations, whether they be program memory or data memory. Although program memory is 3 bytes wide and data memory is 2 bytes wide, they both occupy the same amount of space on the EPROM because each location, whether it be PM or DM, is stored in 4 bytes on the EPROM. Therefore, the total memory that can be booted in this mode is 64K / 4 - 1K = 15K locations. The 1K is for overhead created by the loader routines. NOTE: If you need to boot load more than 15K combined locations of PM and DM RAM you cannot use this method of boot loading. Use one of the other methods of boot loading provided by the on-chip ROM monitor (enabled by BMODE=MMAP=1). The PROM splitter generates three output files PROMfile.bnu, PROMfile.bnm, and PROMfile.bnl. Of these, however, only the PROMfile.bnm file is used in burning the EPROM. ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 37 IMPORTANT: In order for your program to boot successfully in this mode you must have an interrupt vector table containing a JUMP to the start of your main program linked at location 0x0000 in the .MODULE statement. You must also insert JUMPs to your interrupt service routines in the interrupt vector locations for each interrupt you will be enabling. For all other interrupt vector locations an RTI instruction can be inserted so that any unexpected interrupts will simply return rather than result in some unexpected behavior. The following is an example interrupt vector table. As can be seen, the first location is a jump to the beginning of the main program at label STARTUP, and interrupt vectors have been created for the PWMSYNC and PWMTRIP interrupts. {-------------------------------------------------------------} .MODULE/RAM/ABS=0 interrupt_vector_table; .EXTERNAL startup, pwmsync_isr, pwmtrip_isr; .VAR/DM/RAM/SEG=USER_DM3 TEMP_I4_SAVE; #include ; ivt: JUMP startup; {execution starts here at powerup/reset} NOP; NOP; NOP; DM(TEMP_I4_SAVE)=I4; I4=DM(PICVECTOR); JUMP (I4); NOP; RTI; NOP;NOP;NOP; RTI; NOP;NOP;NOP; RTI; {SPORT0 TRANSMIT} NOP;NOP;NOP; RTI; {SPORT0 RECEIVE} NOP;NOP;NOP; RTI; {Software Interrupt 1} NOP;NOP;NOP; NOP; {Software Interrupt 0} RTI;NOP;NOP; RTI; {SPORT1 TRANSMIT} NOP;NOP;NOP; RTI; {SPORT1 RECEIVE} NOP;NOP;NOP; RTI; {Timer} NOP;NOP;NOP; RTI; {Powerdown} NOP;NOP;NOP; ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 38 I4=DM(TEMP_I4_SAVE); {ADC end of conversion} RTI; {insert vector here} NOP; NOP; I4=DM(TEMP_I4_SAVE); {PWMSYNC} jump PWMSYNC_ISR; {insert vector here} NOP; NOP; I4=DM(TEMP_I4_SAVE); {EIU loop timer timeout} RTI; {insert vector here} NOP; NOP; I4=DM(TEMP_I4_SAVE); {PIO4 to PIO11} RTI; {insert vector here} NOP; NOP; I4=DM(TEMP_I4_SAVE); {EIU counter error} RTI; {insert vector here} NOP; NOP; I4=DM(TEMP_I4_SAVE); {ETU} RTI; {insert vector here} NOP; NOP; I4=DM(TEMP_I4_SAVE); {PIO 0} RTI; {insert vector here} NOP; NOP; I4=DM(TEMP_I4_SAVE); {PIO 1} RTI; {insert vector here} NOP; NOP; I4=DM(TEMP_I4_SAVE); {PIO 2} RTI; {insert vector here} NOP; NOP; I4=DM(TEMP_I4_SAVE); {PIO 3} RTI; {insert vector here} NOP; NOP; I4=DM(TEMP_I4_SAVE); {PWMTRIP} jump PWMTRIP_ISR; {insert vector here} NOP; NOP; {-------------------------------------------------------} .ENDMOD; ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 39 The following is an example procedure for creating a bootable EPROM for the program Example1. The ivt.dsp file contains the interrupt vector table shown above. The code contained in the example1.dsp file is unimportant for this example. You can replace the example1.dsp program with your own program. 1. Assemble and link the Example1 program by executing the following commands at the DOS prompt. asm21 ivt.dsp -2171 -l -dADMC401 asm21 example1.dsp -2171 -l -dADMC401 ld21 ivt example1 -a admc401 -g -e example1 -x example1 2. Invoke the PROM splitter by executing the following command at the DOS prompt. spl21 example1 example1 -loader -i 3. Load the file example1.bnm that is created into your PROM programmer. Select a 27C512 device and Intel Hex as the input format. 4. Program the EPROM. 5. Plug the EPROM into the EPROM socket on the ADMC401 evaluation board or on your own target board. Make sure the MMAP and BMODE pins are tied low (via jumpers on the evaluation board). 6. Boot the program by powering on or resetting the ADMC401. For more information on the PROM splitter see Reference 3. ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 40 12. Interrupt Operation Interrupts work as described for an ADSP-2171 core in Reference 2 with the following exceptions: · Peripheral interrupts (Vector addresses 0x0030 - 0x0058) are internally wired to IRQ2 (vector at 0x0004). Software further determines which interrupt is activated and jumps to the appropriate interrupt service routine. The interrupt controller allows the processor core to respond to ten possible interrupts with minimum overhead. The ADMC401 supports nine internal interrupts from the timer, the two serial ports, the software interrupts, powerdown, and reset. The tenth interrupt, IRQ2 on the 2171 core, is actually wired internally to the ADMC401 peripheral interrupt controller (PIC). This peripheral interrupt is generated by any of the sources listed at addresses 0x0030 - 0x0058 in Table 4. All interrupts are internally prioritized and individually maskable, except for the Powerdown interrupt which is non-maskable. The interrupt vector addresses and priorities are shown in Table 4. (Interrupts can be masked or unmasked with the IMASK register.) Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. Peripheral interrupts are individually maskable in the same way with the PICMASK register. The ADMC401 masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect autobuffering. Interrupt Source Interrupt Vector Address RESET Startup (or Power Up with PUCR = 1) 0x0000 (Highest Priority) 1Peripheral Interrupt ( IRQ2 ) 0x0004 Power- Down (non-maskable) 0x002C ADC End-of-Conversion 0x0030 PWMSYNC 0x0034 EIU Loop Timer Timeout 0x0038 PIO Interrupt (PIO4 to PIO11) 0x003C EIU Counter Error 0x0040 Event Timer Unit Interrupt 0x0044 PIO0 Interrupt 0x0048 PIO1 Interrupt 0x004C PIO2 Interrupt 0x0050 PIO3 Interrupt 0x0054 PWMTRIP Interrupt 0x0058 SPORT0 Transmit 0x0010 SPORT0 Receive 0x0014 Software Interrupt 1 0x0018 Software Interrupt 0 0x001C SPORT1 Transmit or IRQ1 0x0020 SPORT1 Receive or IRQ0 0x0024 Timer 0x0028 (Lowest Priority) 1peripheral interrupt ( IRQ2 ) starts execution at 0x0004, from which it jumps to an interrupt vector address from 0x0030 - 0x0058 as appropriate. Table 4. Interrupt Vector Addresses by Priority ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 41 The interrupt control register, ICNTL, allows the external interrupts to be either edge or level-sensitive. Since the IRQ2 line is a combination of all peripheral interrupt sources they will all be set to edge or level-sensitive. The ICNTL register also allows interrupts to be processed sequentially or nested with higher priority interrupts taking precedence. Since the peripheral interrupts are all on the same level ( IRQ2 ) they can only be nested by manually unmasking them with the IMASK and PICMASK registers from inside the interrupt service routine. The IFC register is a write-only register that is used to force and clear interrupts from software. On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks are 12 levels deep to allow interrupt nesting. A set of shadow registers is provided for single cycle context switching. The following instructions allow global enabling or disabling of interrupts regardless of the state of IMASK. Disabling the interrupts does not affect autobuffering. ENA INTS; DIS INTS; When you reset the processor, interrupt servicing is disabled. During initialization the ADMC401 monitor creates a default interrupt vector table at location 0. Interrupt vector locations are spaced four locations apart which allows short interrupt service routines to be coded in place, with no jump to the service routine required. For interrupt service routines with more than four instructions, a jump (or vector) to the interrupt service routine must be placed at the interrupt vector location. The PUT_VECTOR library routine can be used to perform this task. As a default, interrupt vector locations that are not in use contain RTI instructions so that inadvertent activation of the interrupt will only cause it to return and not to jump to some unknown instruction. For peripheral interrupts the default code at location 0x0004 is slightly different, and so is shown below: Location_0x0004: DM(I4_SAVE) = I4; I4 = DM(PICVECTOR); JUMP (I4); And the peripheral interrupt locations that are entered by the JUMP (I4) statement contain the following default code: Location_0x0034: I4 = DM(I4_SAVE); RTI; Note that this default code restores I4 to its value before the interrupt. The user should replace the RTI with a JUMP to their interrupt service routine. See the section “Using Put_Vector” for instructions on how to place vectors to your routines in the interrupt vector table. The default interrupt vector table contains code at locations 0x0001 and 0x0002 and at the SPORT1 transmit and receive interrupt vector locations (0x0020 and 0x0024) which is used when in debug mode to talk to the Motion Control Debugger. These locations must not be changed when operating in this mode or the debugger may crash. Also, the SPORT1 transmit and receive interrupts must be kept enabled by your code in order to run it with the debugger. ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 42 12.1 Using PUT_VECTOR The PUT_VECTOR routine can be called to replace the default RTI in the interrupt vector table with a JUMP to your interrupt service routine. PUT_VECTOR is contained in the ROM and can be called by including the admc401.h file. If you wish to run PUT_VECTOR from RAM the source code is contained in the SrcLib directory. The following example illustrates how to use PUT_VECTOR. Given the following default interrupt vector table code for the PWMSYNC interrupt: Location_0x0034: I4 = DM(I4_SAVE); RTI; the following call to PUT_VECTOR in your initialization code: I4 = PWMSYNC_INT_ADDR; MR0 = ^YOUR_PWMSYNC_ISR CALL PUT_VECTOR; would change the code at 0x0034 to: Location_0x0034: I4 = DM(I4_SAVE); JUMP YOUR_PWMSYNC_ISR; In this example YOUR_PWMSYNC_ISR is the label at the start of your PWMSYNC interrupt service routine. PWMSYNC_INT_ADDR is a constant equal to 0x0035 in the ADMC401.h file that you would include in your code module. 12.2 Peripheral Interrupt Considerations The user should be aware of the following considerations of peripheral interrupt operations: · The PWMSYNC interrupt is detected on a low to high transition on the PWMSYNC pulse. · The PWMTRIP interrupt is detected on a high to low transition on the PWMTRIP pin. Additionally, each of the 12 PIO lines can be configured as a PWM trip source based on the settings in the PIOPWM register. In this mode, a low-level transition on the PIO pin will cause a PWM trip interrupt. · At reset all PIO lines are configured as PWM trip sources (PIOPWM = 0xFFF). Because all PIO lines are also configured as inputs and have internal pull-down resistors, any unconnected PIO lines will cause a PWM trip. Therefore, prior to using the PWM unit, it is imperative that the PIO state be correctly configured for the particular application. If no PIO lines are to be used as PWM trip sources, the PIOPWM register must be cleared to zero prior to using the PWM unit. · A PIO interrupt is detected based on the settings in the PIOLEVEL, PIOMODE, and PIOINTEN registers. When a PIO interrupt is detected for PIO4 - PIO11, a flag bit is set in the PIOFLAG register. The user’s interrupt service routine starting at 0x003C must read the PIOFLAG register to determine which PIO pin is the source of the interrupt. · PIO0 - PIO3 each have their own dedicated interrupt vector so the added PIOFLAG processing is not required for these interrupts. · Reading the PIOFLAG register clears all bits in the register so it’s up to the user’s code to save the PIOFLAG value to allow later processing of any simultaneous PIO interrupts that may have occurred. ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 43 13. Watchdog Timer Operation The watchdog timer is used to time critical control loops and to reset the peripherals and DSP if a loop takes too long to complete. The watchdog timer is enabled by writing a value to the watchdog timer register, WDTIMER, shown in Figure 25. A counter in the watchdog hardware counts down from this value at the peripheral clock rate (CLKIN). If the DSP “hangs”, the counter will count down to zero and the watchdog timer hardware will force a DSP and peripheral reset. Under normal operation a section of DSP code at the end of the control loop would reset the counter to its initial value, preventing it from reaching zero. Thus only under incorrect operation of the DSP would the watchdog timer trip. Once the watchdog timer has been enabled, to prevent it from timing out, the user need only include the following line of code at the end of the control loop: DM(WDTIMER) = AX0; The value in AX0 is irrelevant. Once the watchdog timer is enabled, rewriting to WDTIMER will reset the timer to the original value that was written when the watchdog timer was initially enabled. When a watchdog trip occurs and the peripheral block is reset, all peripheral registers are zeroed and thus the PWM signals to the motor are shut down. The WDFLAG (bit 1 of the SYSSTAT register) is set when a watchdog trip occurs. The DSP can read this flag during its boot up sequence to determine if the reset came from a watchdog trip. The watchdog remains disabled while the WDFLAG is set. Writing a nonzero value to the WDTIMER register will reset the WDFLAG bit and enable the watchdog timer. Writing zero to the WDTIMER register will reset the WDFLAG bit and disable the watchdog timer. The watchdog timer is disabled on power-up. WDTIMER (W) 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 TIMEOUT (# of CLKINcycles) 9 DM(0x2018) Figure 25. Watchdog Timer Register ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 44 14. Software Peripheral Reset Function A full reset of the peripherals can be performed from software by executing the following code: PER_RST: SET FL2; TOGGLE FL2; TOGGLE FL2; RTS; This resets all peripheral registers to their power on state and turns off PWM signals to the motor. This routine is available in the source code library. 15. SROM/EEPROM Reset Function When UARTEN (bit 5 of the MODECTRL register) is set, the FL1 port of the DSP core is internally connected to the external RFS1 pin. In this mode, this pin becomes an output and is intended to be used to reset the external serial ROM device. This is accomplished by toggling the FL1 flag using the following code segment: SROMRESET: SET FL1; TOGGLE FL1; TOGGLE FL1; RTS; ADMC401 DSP Motor Controller Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 45 16. Tutorial The following tutorial leads the user through a demonstration example on the ADMC401 evaluation kit. For additional software examples and the latest updates consult the Analog Devices motor control website at http://www.analog.com/motorcontrol. The example source code files for this tutorial are installed during the Motion Control Development Tools installation. The example is installed automatically into the subdirectory Drive:\Progra~\Analog~1\Motion~1\Examples\ADMC401\Example1 · EXAMPLE1: This example sets up the PWM system of the ADMC401 and produces constant duty cycle outputs on the six PWM output pins. In addition, the lower three PWM signals are chopped with a 1 MHz signal. No additional hardware is required to run this example on the ADMC401 evaluation kit using the debugger. This file is a good template from which it is possible to build more complex programs. 16.1 Example 1: Simple Configuration Example This demonstration example is located in the \Example1 subdirectory. It is a simple program that can be used to validate the operation of the ADMC401 evaluation kit. It can also be used as a learning tool for the Motion Control Debugger and as a template from which more complex programs can be developed. The subdirectory contains the following files: · example1.dsp Assembly language source code · build.bat Batch file to assemble and link the example file to create the executable module. The executable module can be loaded using the debugger. In addition, the following files are used from the Tgtfiles subdirectory: · ADMC401.h Include file of device specific constant definitions · ADMC401.ach Architecture file used by linker This demo program may be summarized with the following pseudocode. STARTUP: Initialize PWM registers for 10 kHz, 1us dead time, 1.5 us pulse deletion. Enable high frequency chopping on the low-side PWM signals at 1.0 MHz and enable all PWM outputs. Use PUT_VECTOR routine to place jumps in the interrupt vector table to the appropriate routines for both the PWMSYNC and PWMTRIP interrupts. Enable both PWMSYNC and PWMTRIP interrupts by writing to the PICMASK register of the ADMC401. Clear any pending interrupts, disable interrupt nesting and set level sensitivity using IFC and ICNTL registers. Enable peripheral interrupt ( IRQ2 ) on ADMC401 using IMASK register. MAINLOOP: Do nothing. Wait for either PWMSYNC or PWMTRIP interrupt. ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 46 PWMSYNC_ISR: At each PWMSYNC interrupt, execute this code. In this example, the three PWM registers PWMCHA, PWMCHB and PWMCHC are written with constant values. PWMTRIP_ISR: At each PWMTRIP interrupt, execute this code. In this example, do nothing. Running the batch file build.bat will create some additional files. These include the object file (.obj), the code file (.cde) and the initialization file (.int) created by the assembler and the map listing file (.map), the symbol table file (.sym) and the executable file (.exe) created by the linker. The executable file EXAMPLE1.EXE can be run on the evaluation kit using the debugger. See the section “Getting Started with the Motion Control Debugger” for instructions on how to load and run the program. ADMC401 DSP Motor Controller Appendix A. System Specification File Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 47 17. Appendices Appendix A. System Specification File { For the ADMC401 the following line must be ADSP2101 when you run the System Builder. Then you must edit the .ACH file that is generated and change the target to ADSP2171. The System Builder won't take a target of ADSP2171 in this case because for the ADMC401 data RAM has been modified to start at location 0x3800 instead of 0x3000 as for the basic 2171 core. } .ADSP2101; .MMAP0; { User Program Memory Area } .SEG/PM/RAM/ABS=H#0/CODE/DATA VECTOR[96]; .SEG/PM/RAM/ABS=H#60/CODE/DATA USER_PM1[1952]; .SEG/PM/RAM/ABS=H#1000/CODE/DATA USER_PM2[12288]; { ROM Code Program Memory Area } .SEG/PM/ROM/ABS=H#800/CODE ROMCODE[2048]; { User Data Memory Area } .SEG/DM/RAM/ABS=H#0000/DATA USER_DM1[8192]; .SEG/DM/RAM/ABS=H#2400/DATA USER_DM2[3072]; {hole at 0x3000-0x37FF on eval board} .SEG/DM/RAM/ABS=H#3800/DATA USER_DM3[864]; .SEG/DM/RAM/ABS=H#3B60/DATA ROMDATA[160]; {never put data here, monitor reserved} .ENDSYS; Appendix B. Architecture Description File ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 48 Appendix B. Architecture Description File $ADMC401 $ADSP2171 $MMAP0 $0000 005F paxVECTOR t $0060 07FF paxUSER_PM1 t $1000 3FFF paxUSER_PM2 t $0800 0FFF pomROMCODE t $0000 1FFF dadUSER_DM1 t $2400 2FFF dadUSER_DM2 t $3800 3BFF dadUSER_DM3 t $ ADMC401 DSP Motor Controller Appendix C. ADMC401 Include File (ADMC401.H) Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 49 Appendix C. ADMC401 Include File (ADMC401.H) #ifndef ADMC401_INCLUDE #define ADMC401_INCLUDE { This include file defines important ADMC401 addresses. The names defined below can be used in user programs by "including" this file. This file defines: - names for the peripheral registers of the ADMC401 - names for the memory mapped core registers of the ADMC401 - interrupt vector table addresses } { peripheral registers of the ADMC401 } .CONST PWMTM = 0x2008; {PWM timer register} .CONST PWMDT = 0x2009; {PWM dead time register} .CONST PWMPD = 0x200A; {PWM pulse deletion} .CONST PWMGATE = 0x200B; {PWM gate register} .CONST PWMCHA = 0x200C; {PWM channel A register} .CONST PWMCHB = 0x200D; {PWM channel B register} .CONST PWMCHC = 0x200E; {PWM channel C register} .CONST PWMSEG = 0x200F; {PWM segment selection} .CONST AUXCH0 = 0x2010; {Auxiliary PWM channel 0 duty cycle} .CONST AUXCH1 = 0x2011; {Auxiliary PWM channel 1 duty cycle} .CONST AUXTM0 = 0x2012; {Auxiliary PWM channel 0 period} .CONST AUXTM1 = 0x2013; {Auxiliary PWM channel 1 period} .CONST MODECTRL = 0x2015; {MODE control register} .CONST SYSSTAT = 0x2016; {System status register} .CONST WDTIMER = 0x2018; {Watchdog timer register} .CONST PICVECTOR = 0x201C; {ISR address } .CONST PICMASK = 0x201D; {IRD mask register } .CONST EIUCNT = 0x2020; {Encoder count register } .CONST EIUMAXCNT = 0x2021; {Encoder max count register } .CONST EIUSTAT = 0x2022; {Encoder status register } .CONST EIUCTRL = 0x2023; {Encoder control register } .CONST EIUPERIOD = 0x2024; {Encoder loop timer period register} .CONST EIUSCALE = 0x2025; {Encoder loop timer scale register} .CONST EIUTIMER = 0x2026; {Encoder loop timer} .CONST EETCNT = 0x2027; {Latched value of EIUCNT register} .CONST EIUFILTER = 0x2028; {EIU filter control register} .CONST EIZLATCH = 0x2029; {EIZ latch register} .CONST EISLATCH = 0x202A; {EIS latch register} .CONST ADC0 = 0x2030; {ADC0 register } .CONST ADC1 = 0x2031; {ADC1 register } .CONST ADC2 = 0x2032; {ADC2 register } .CONST ADC3 = 0x2033; {ADC3 register } .CONST ADC4 = 0x2034; {ADC4 register } .CONST ADC5 = 0x2035; {ADC5 register } .CONST ADC6 = 0x2036; {ADC6 register } .CONST ADC7 = 0x2037; {ADC7 register } .CONST ADCCTRL = 0x2038; {ADC control register } .CONST ADCSTAT = 0x2039; {ADC status register } .CONST ADCXTRA = 0x203B; {extra ADC data register } .CONST ADCOTR = 0x203C; {ADC out of range register } .CONST PIOLEVEL = 0x2040; {PIO level control register } .CONST PIOMODE = 0x2041; {PIO mode control register } Appendix C. ADMC401 Include File (ADMC401.H) ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 50 .CONST PIOPWM = 0x2042; {PIO PWMTRIP control register } .CONST PIODIR = 0x2044; {PIO direction register } .CONST PIODATA = 0x2045; {PIO data register} .CONST PIOINTEN = 0x2046; {PIO interrupt enable register } .CONST PIOFLAG = 0x2047; {PIO interrupt flag register } .CONST ETUA0 = 0x2050; {ETU0 Event A capture register } .CONST ETUB0 = 0x2051; {ETU0 Event B capture register } .CONST ETUAA0 = 0x2052; {ETU0 Event AA capture register } .CONST ETUA1 = 0x2053; {ETU1 Event A capture register} .CONST ETUB1 = 0x2054; {ETU1 Event B capture register} .CONST ETUAA1 = 0x2055; {ETU1 Event AA capture register} .CONST ETUTIME = 0x2056; {ETU timer value} .CONST ETUCONFIG = 0x205C; {ETU configuration register } .CONST ETUDIVIDE = 0x205D; {ETU clock divide register } .CONST ETUSTAT = 0x205E; {ETU status register } .CONST ETUCTRL = 0x205F; {ETU control register } .CONST PWMSYNCWT = 0x2060; {PWMSYNC width register} .CONST PWMSWT = 0x2061; {PWM software trip register} .CONST EETN = 0x2070; {EET pulse decimator register } .CONST EETDIV = 0x2071; {EET timer decimator register } .CONST EETDELTAT = 0x2072; {EET delta timer register } .CONST EETT = 0x2073; {EET timer period register } .CONST EETSTAT = 0x2074; {EET overflow status register } { memory mapped core registers of the ADMC401 } .CONST SYSCNTL = 0x3fff; .CONST MEMWAIT = 0x3ffe; .CONST TPERIOD = 0x3ffd; .CONST TCOUNT = 0x3ffc; .CONST TSCALE = 0x3ffb; .CONST Sport0_Rx_Words1 = 0x3ffa; .CONST Sport0_Rx_Words0 = 0x3ff9; .CONST Sport0_Tx_Words1 = 0x3ff8; .CONST Sport0_Tx_Words0 = 0x3ff7; .CONST Sport0_Ctrl_Reg = 0x3ff6; .CONST Sport0_Sclkdiv = 0x3ff5; .CONST Sport0_Rfsdiv = 0x3ff4; .CONST Sport0_Autobuf_Ctrl = 0x3ff3; .CONST Sport1_Ctrl_Reg = 0x3ff2; .CONST Sport1_Sclkdiv = 0x3ff1; .CONST Sport1_Rfsdiv = 0x3ff0; .CONST Sport1_Autobuf_Ctrl = 0x3fef; { interrupt vector table addresses for ADMC401 } .CONST ADC_INT_ADDR = 0x30+1; {ADC INTERRUPT } .CONST PWMSYNC_INT_ADDR = 0x34+1; {PWMSYNC interrupt } .CONST EIUTIMER_INT_ADDR = 0x38+1; {EIU timer interrupt } .CONST PIO_INT_ADDR = 0x3C+1; {PIO4 - PIO11 interrupt } .CONST EIUERROR_INT_ADDR = 0x40+1; {EIU error interrupt } .CONST ETU_INT_ADDR = 0x44+1; {ETU interrupt } .CONST PIO0_INT_ADDR = 0x48+1; {PIO0 interrupt } .CONST PIO1_INT_ADDR = 0x4C+1; {PIO1 interrupt } .CONST PIO2_INT_ADDR = 0x50+1; {PIO2 interrupt } .CONST PIO3_INT_ADDR = 0x54+1; {PIO3 interrupt } .CONST PWMTRIP_INT_ADDR = 0x58+1; {PWMTRIP interrupt} .CONST TX0_INT_ADDR = 0x10; {SPORT0 transmit interrupt} .CONST RX0_INT_ADDR = 0x14; {SPORT0 receive interrupt} .CONST SW1_INT_ADDR = 0x18; {software interrupt 1} ADMC401 DSP Motor Controller Appendix C. ADMC401 Include File (ADMC401.H) Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 51 .CONST SW0_INT_ADDR = 0x1C+1; {software interrupt 0} .CONST TX1_INT_ADDR = 0x20; {SPORT1 transmit interrupt} .CONST RX1_INT_ADDR = 0x24; {SPORT1 receive interrupt} .CONST TIMER_INT_ADDR = 0x28; {Timer interrupt} { ROM addresses } .CONST PUT_VECTOR = 0x0D8E; {PUT_VECTOR routine in ROM} .CONST HALT_FLAG = 0x3B68; {used by exit library function} .CONST IDE_SP = 0x0C9E; {used by exit library function} #endif Appendix D. Constant Include File (Constant.h) ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 52 Appendix D. Constant Include File (Constant.h) {This include file contains many useful constants. To use include the file in the module where you want to use the constants. Then refer to the constants by the names given below in your code. VERSION # 1.2 08/07/97 Name Date Description ---- -------- ----------- MOD/HISTORY: Correction made to some constants P.Kettle 1/15/98 CALLED BY: } #ifndef CONSTANT_INCLUDE #define CONSTANT_INCLUDE .CONST OnePiOverTwo = 0x4000; { Hex equivalent of 1pi/2 } .CONST OnePiOverFour = 0x2000; { Hex equivalent of 1pi/4 } .CONST OnePiOverTwelve = 0x0AAA; { Hex equivalent of 1pi/12 } .CONST OnePiOverThree = 0x2AAA; { Hex equivalent of 1pi/3 } .CONST PiOverTwo = 0x4000; { Hex equivalent of pi/2 } .CONST PiOverFour = 0x2000; { Hex equivalent of pi/4 } .CONST PiOverTwelve = 0x0AAA; { Hex equivalent of pi/12 } .CONST PiOverThree = 0x2AAA; { Hex equivalent of pi/3 } .CONST TwoPiOverThree = 0x5555; { Hex equivalent of 2pi/3 } .CONST ThreePiOverThree = 0x7FFF; { Hex equivalent of 3pi/3 } .CONST FourPiOverThree = 0xAAAA; { Hex equivalent of 4pi/3 } .CONST FivePiOverThree = 0xD555;{ Hex equivalent of 5pi/3 } .CONST NOnePiOverThree = -OnePiOverThree-1; { Hex equivalent of -1pi/3 } .CONST NTwoPiOverThree = -TwoPiOverThree-1; { Hex equivalent of -2pi/3 } .CONST NThreePiOverThree = -ThreePiOverThree-1; { Hex equivalent of -2pi/3 } .CONST HALF = 0x4000; .CONST OnePiOverSix = 0x1555; { Hex equivalent of 1pi/6 } .CONST PiOverSix = 0x1555; { Hex equivalent of pi/6 } .CONST TwoPiOverSix = 0x2AAA; { Hex equivalent of 2pi/6 } .CONST ThreePiOverSix = 0x4000; { Hex equivalent of 3pi/6 } .CONST FourPiOverSix = 0x5555; { Hex equivalent of 4pi/6 } .CONST FivePiOverSix = 0x6AAA; { Hex equivalent of 5pi/6 } .CONST SixPiOverSix = 0x7FFF; { Hex equivalent of 6pi/6 } .CONST SevenPiOverSix = 0x9555; { Hex equivalent of 7pi/6 } .CONST EightPiOverSix = 0xAAAA; { Hex equivalent of 8pi/6 } .CONST NinePiOverSix = 0xC000;{ Hex equivalent of 9pi/6 } .CONST TenPiOverSix = 0xD555;{ Hex equivalent of 10pi/6} .CONST ElevenPiOverSix = 0xEAAA; { Hex equivalent of 11pi/6} .CONST TwelvePiOverSix = 0xFFFF;{ Hex equivalent of 12pi/6} .CONST Pi = 0x7FFF; { Hex equivalent of pi } .CONST NPi = 0x8000; { Hex equivalent of -pi } .CONST Zero = 0x0; .CONST NULL = 0x0; .CONST TwoPiOverTwelve = 2*PiOverTwelve;{ Hex equivalent of 2pi/12} .CONST ThreePiOverTwelve = 3*PiOverTwelve;{ Hex equivalent of 3pi/12} .CONST FourPiOverTwelve = 4*PiOverTwelve;{ Hex equivalent of 4pi/12} .CONST FivePiOverTwelve = 5*PiOverTwelve;{ Hex equivalent of 5pi/12} ADMC401 DSP Motor Controller Appendix D. Constant Include File (Constant.h) Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 53 .CONST SixPiOverTwelve = 6*PiOverTwelve; { Hex equivalent of 6pi/12} .CONST SevenPiOverTwelve = 7*PiOverTwelve; { Hex equivalent of 7pi/12} .CONST EightPiOverTwelve = 8*PiOverTwelve; { Hex equivalent of 8pi/12} .CONST NinePiOverTwelve = 9*PiOverTwelve; { Hex equivalent of 9pi/12} .CONST TenPiOverTwelve = 10*PiOverTwelve; { Hex equivalent of 10pi/12} .CONST ElevenPiOverTwelve = 11*PiOverTwelve; { Hex equivalent of 11pi/12} .CONST TwelvePiOverTwelve = 12*PiOverTwelve; { Hex equivalent of 12pi/12} .CONST ThirteenPiOverTwelve = 13*PiOverTwelve; { Hex equivalent of 13pi/12} .CONST FourteenPiOverTwelve = 14*PiOverTwelve; { Hex equivalent of 14pi/12} .CONST FifteenPiOverTwelve = 15*PiOverTwelve; { Hex equivalent of 15pi/12} .CONST SixteenPiOverTwelve = 16*PiOverTwelve; { Hex equivalent of 16pi/12} .CONST SeventeenPiOverTwelve = 17*PiOverTwelve; { Hex equivalent of 17pi/12} .CONST EighteenPiOverTwelve = 18*PiOverTwelve; { Hex equivalent of 18pi/12} .CONST NineteenPiOverTwelve = 19*PiOverTwelve; { Hex equivalent of 19pi/12} .CONST NOnePiOverTwelve = -1*0x0AAA; { Hex equivalent of 1pi/12} .CONST NTwoPiOverTwelve = -2*PiOverTwelve; { Hex equivalent of 2pi/12} .CONST NThreePiOverTwelve = -3*PiOverTwelve; { Hex equivalent of 3pi/12} .CONST NFourPiOverTwelve = -4*PiOverTwelve; { Hex equivalent of 4pi/12} .CONST NFivePiOverTwelve = -5*PiOverTwelve; { Hex equivalent of 5pi/12} .CONST NSixPiOverTwelve = -6*PiOverTwelve; { Hex equivalent of 6pi/12} .CONST NSevenPiOverTwelve = -7*PiOverTwelve; { Hex equivalent of 7pi/12} .CONST NEightPiOverTwelve = -8*PiOverTwelve; { Hex equivalent of 8pi/12} .CONST NNinePiOverTwelve = -9*PiOverTwelve; { Hex equivalent of 9pi/12} .CONST NTenPiOverTwelve = -10*PiOverTwelve; { Hex equivalent of 10pi/12} .CONST NElevenPiOverTwelve = -11*PiOverTwelve; { Hex equivalent of 11pi/12} .CONST NTwelvePiOverTwelve = -12*PiOverTwelve; { Hex equivalent of 12pi/12} .CONST NThirteenPiOverTwelve = -13*PiOverTwelve; { Hex equivalent of 13pi/12} .CONST NFourteenPiOverTwelve = -14*PiOverTwelve; { Hex equivalent of 14pi/12} .CONST NFifteenPiOverTwelve = -15*PiOverTwelve; { Hex equivalent of 15pi/12} .CONST NSixteenPiOverTwelve = -16*PiOverTwelve; { Hex equivalent of 16pi/12} .CONST NSeventeenPiOverTwelve = -17*PiOverTwelve; { Hex equivalent of 17pi/12} .CONST NEighteenPiOverTwelve = -18*PiOverTwelve; { Hex equivalent of 18pi/12} .CONST NNineteenPiOverTwelve = -19*PiOverTwelve; { Hex equivalent of 19pi/12} #endif Appendix E. Macro Include File (Macro.h) ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 54 Appendix E. Macro Include File (Macro.h) {VERSION # 1.008/07/97 Name Date Description ---- -------- ----------- MOD/HISTORY: none CALLED BY: } #ifndef MACRO_INCLUDE #define MACRO_INCLUDE .MACRO Write_dm(%0,%1); ar=%1; dm(%0)=ar; .ENDMACRO; .MACRO Copy_dm(%0,%1); ar=dm(%0); dm(%1)=ar; .ENDMACRO; .MACRO SetVect(%0,%1); I4 = %0; MR0 =^%1; CALL PUT_VECTOR; .ENDMACRO; .MACRO Sin(%0); PUSH STS; DIS M_MODE, DIS AR_SAT; ax0 =%0; M5 = 1; L5 = 0; call ADMC_SIN; POP STS; .ENDMACRO; .MACRO Cos(%0); PUSH STS; DIS M_MODE, DIS AR_SAT; ax0 =%0; M5 = 1; L5 = 0; call ADMC_COS; POP STS; .ENDMACRO; .MACRO PWM_DAC(%0,%1); ar=%0; sr = LSHIFT ar BY -8 (LO); {Value to be written in ar } ay0=0x80; {Shift to 8 LSBs and add } ar=sr0+ay0; {offset of 0x80 = 2.5V } ay0= 0xff; ar = ar AND ay0; DM(%1) = ar; {Write value to PWMTIM0 } .ENDMACRO; #endif ADMC401 DSP Motor Controller Appendix F. SROM/EEPROM Boot Loader Protocol Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 55 Appendix F. SROM/EEPROM Boot Loader Protocol The SROM/EEPROM boot loader interface was designed to be used with a Xilinx XC17128E serial configuration PROM, or Atmel AT17C128 EEPROM, or Microchip 37LV128 OTP EPROM. If using any of these devices, the MAKEPROM utility can be used to format an executable file into a .DBS file that can be programmed into the device. The MAKEPROM utility automatically formats the code and data to boot properly from the device. If the ADMC401 is successful in loading a user program from the SROM/EEPROM, then execution of the program will start at 0x0060. The SROM/EEPROM boot loader can be used with devices other than those listed above if they adhere to the same timing and protocol given in this appendix. The SROM/EEPROM boot loader uses a two-wire (data and clock) serial protocol in which the ADMC401 provides a clock to the device equal to 1/26 of CLKOUT. On the ADMC401 processor board the device socket is connected as follows: PIN # SROM/EEPROM pin Connected to 1 DATA DR1A pin on ADMC401 2 CLK SCLK1 pin on ADMC401 3 RESET /OE RFS1 pin on ADMC401 4 CE GND 5 GND GND 6 CEO Floating 7 VPP/SER_EN VCC (+5V) 8 VCC VCC (+5V) Table 5. SROM / EEPROM Pin Connections The ROM monitor program resets the DR1SEL bit of the MODECTRL register (see Reference 1) to connect the DR1A pin (the device’s data line) to the DR1 input of SPORT1. It then sets the UARTEN bit which connects the DR1 and RFS1 inputs together so that the first word in the input data will act as the receive frame sync. UARTEN also connects FL1 to the RFS1 pin to be used as a reset signal for the SROM/EEPROM. SPORT1 is then configured for synchronous communications as follows: SPORT1 control register = 0x5E07 · internal serial clock (SCLK) used · external receive frame synch (RFS) enabled · RFS required on 1st word only · active high RFS · alternate receive framing used · right justify, zero-fill unused MSBs · serial word length is 8 bits SPORT1 SCLKDIV register = 12 (1 MHz SCLK freq. @ 26MHz DSP CLKOUT) FL1 is reset, causing the SROM/EEPROM to be reset, then FL1 is set, causing data to be clocked from the device in a continuous stream. When the SPORT receives the RFS (the leading edge of the first header byte 0xFF), it starts receiving a continuous stream of bits. When each byte is accumulated, an interrupt is generated and the byte is loaded by the DSP. The DSP can immediately start accepting data; however, it will wait up to 1000 cycles (38.5 us @ 26MHz) to receive the first header byte. This allows for different startup times if a different device is being used to download the data. The data receive line must be held low until the first header byte is received. The format of the data expected by the boot loader is given in Appendix F. SROM/EEPROM Boot Loader Protocol ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 56 Table 7. The format is the same for the other boot load interfaces except that the SROM header bytes are not used. The MAKEPROM utility automatically converts a user’s executable file into a PROM programmer file having this format. The boot load timing from reset (RFS1) is summarized in Figure 26. The program memory and data memory are loaded according to the blocks defined in the boot load file syntax (Table 7). Both the program and data memory portions of the boot load file contain checksums that are used by the monitor to verify correct loading. The PM checksum is calculated by the monitor by accumulating, in the MR0 register, the upper 16 bits of each PM location received. The lower 8 bits are accumulated in the MR1 register. When all locations have been received, the MR1 register is masked with 0xFF, removing any overflow from the lower 8 bits. The MR0 register is then compared to the upper 16 bits of the received checksum and the MR1 register is compared to the lower 8 bits of the received checksum. The DM checksum is calculated in the same way as the upper 16 bits of the PM checksum. Note: When boot loading from an SROM, the ADMC401 receives data MSB first. The Atmel, Xilinx, and Microchip devices transmit LSB first. Therefore, the MAKEPROM program bit-reverses all data before writing it to the programmer file (.dbs). For example, the SROM header bytes FF, AA, 33 would look like FF, 55, CC in the .dbs file. If the monitor times out (i.e., receives no data on DR1A) it will switch the SPORT1 input to DR1B and try to communicate over the other interfaces. If the monitor receives data on DR1A, but that data results in an error, the monitor will output an error code on DT1 and then will restart itself, thus trying to reboot. Possible errors and their codes are detailed in the following table: Error Code Description 0x50 SROM PM Header does not match 0xFF, 0xAA, 0x33. 0x51 SROM PM Checksum Error 0x52 SROM DM Header does not match 0xFF, 0xAA, 0x33. 0x53 SROM DM Checksum Error Table 6. SROM boot loader error codes. If the monitor successfully loads the program and data memories without error then it starts execution of the program at location 0x0060. ADMC401 DSP Motor Controller Appendix F. SROM/EEPROM Boot Loader Protocol Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 57 SCLK 16.8 ms (1 MHz @ 26 MHz CLKOUT) 17.0 ms 8.0 ms 32.0 ms 8.0 ms 8.0 ms 8.0 ms RFS1 pin (SROM/EEPROM reset from ADMC401) DRA1 pin/ RFS1 (internal) (Data from device) 4 ZEROs 0xFF 0xAA 0x33 #PM blocks Program Memory Header Record RFS RESET pin Figure 26. Boot Load Timing (XC17128E, AT17C128, or 37LV128) Appendix F. SROM/EEPROM Boot Loader Protocol ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 58 0x00 (SROM only*) 0x00 (SROM only*) 0x00 (SROM only*) 0x00 (SROM only*) 0xFF (SROM only*) 0xAA (SROM only*) 0x33 (SROM only*) Number of PM Blocks PM Start Address Block 1 (MSB) PM Start Address Block 1 (LSB) Number of PM Lines in Block 1 (MSB) Number of PM Lines in Block 1 (LSB) . . Block 1 Code . PM Start Address Block N (MSB) PM Start Address Block N (LSB) Number of PM Lines in Block N (MSB) Number of PM Lines in Block N (LSB) . . Block N Code . PM Checksum (Upper Byte) PM Checksum (Middle Byte) PM Checksum (Lower Byte) 0x00 (SROM only*) 0x00 (SROM only*) 0x00 (SROM only*) 0x00 (SROM only*) 0xFF (SROM only*) 0xAA (SROM only*) 0x33 (SROM only*) Number of DM Blocks DM Start Address Block 1 (MSB) DM Start Address Block 1 (LSB) Number of DM Lines in Block 1 (MSB) Number of DM Lines in Block 1 (LSB) . . Block 1 Data . DM Start Address Block N (MSB) DM Start Address Block N (LSB) Number of DM Lines in Block N (MSB) Number of DM Lines in Block N (LSB) . . Block N Data . DM Checksum (Upper Byte) DM Checksum (Lower Byte) * - The 4 zeros up front and bytes FF, AA, 33 are only used in the SROM boot load file syntax. All other boot load interfaces omit these bytes. Table 7. File Syntax For All Boot Load Interfaces ADMC401 DSP Motor Controller Appendix G. UART Boot Loader Protocol Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 59 Appendix G. UART Boot Loader Protocol The UART boot loader interface can be used with any external device that can be configured as a UART and can adhere to the timing and protocol given in this appendix. This interface is compatible with the Motorola M68HC11 SCI port. If the ADMC401 is successful in loading a user program over the UART boot loader interface, then execution of the program will start at 0x0060. The UART boot loader uses the standard asynchronous protocol using only the data receive (RXD) and data transmit (TXD) lines. To communicate in this mode, an external device need only connect its transmit data line to DR1B and its receive data line to DT1. The ADMC401 processor board uses an RS- 232 line driver chip to convert from the SPORT1 data receive (DR1B) and data transmit (DT1) TTL signals to the RS-232 standard. Following a failure of the SROM/EEPROM boot loader, the ROM monitor program switches the input on SPORT1 to DR1B and waits for two bytes of information. These two bytes are received asynchronously (no clock is required), MSB first. The first byte received is called the autobaud byte. It is used to calculate the baud rate at which the data is arriving. This is known as the autobaud feature. The ADMC401 will lock onto the baud rate of the external device automatically if it sends a byte equal to 0x70. The maximum baud rate that the ADMC401 can lock onto is 300 kHz at a 26 MHz CLKOUT. The second byte received is called the header byte. It tells the monitor what type of interface it is connected to. For the UART boot loader, a header byte equal to 0x71 must be sent. The required timing for this interface is shown in Figure 23. After the monitor verifies that it is connected to a device that is ready to boot load a program as a UART, it sets up SPORT1 as follows: SPORT1 control register = 0x5E4F · internal serial clock (SCLK) used · external receive frame synch (RFS) enabled · RFS required on 1st word only · active low RFS (start bit acts as RFS) · alternate receive framing used · right justify, zero-fill unused MSBs · serial word length is 16 bits The autobaud feature determines the SPORT1 SCLKDIV register value. SCLKDIV is set to a value that represents the baud rate at which the autobaud byte was received, multiplied by 3. The incoming data is sampled at 3 times the baud rate to minimize data errors. Each byte received is represented by 11 bits (1 start bit, 8 data bits, and 2 stop bits, no parity) as shown in Figure 27. Since the incoming data is sampled at three times the baud rate each bit is represented by 3 bits in the received data. Thus each 11-bit word transmitted to the ADMC401 is received as a 33-bit word (actually the last stop bit is dropped to make 32 bits). In the ADMC401 the 32 bits are received as two 16-bit serial word transfers. Words are transmitted and received LSB first. The ADMC401 monitor extracts the byte of information from the 32 bits of received data. As data is received, it is loaded into memory in the same manner as with the other boot load interfaces. The format of the data is given in Table 7. Each data byte received, starting with the header byte, is echoed back over DT1. The autobaud byte is not echoed back. The external device may use this echo as a means of synchronization and verification that the data has been received correctly. As with the other boot load interfaces, the monitor calculates a checksum for the program and data memory words. If the monitor detects a checksum miscompare it will restart itself as if a reset has occurred. Appendix G. UART Boot Loader Protocol ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 60 If the monitor successfully loads the program and data memories without error then it starts execution of the program at location 0x0060. 0 1 0 1 1 0 1 0 0 1 1 000 111 000 111 111 000 111 000 000 111 111 Start Bit LSB Data Bits MSB Stop Bits Data received by ADMC401 (Sampled at 3 times the baud rate.) Figure 27. UART Protocol ADMC401 DSP Motor Controller Appendix H. UART Debugger Protocol Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 61 Appendix H. UART Debugger Protocol In the UART Debugger mode the monitor emulates a standard UART and processes commands received over SPORT1 from an external device. For example, in the case of the Motion Control Debugger, the external device is a PC. While this interface is designed to be used with the Motion Control Debugger it can also be used with any external device that can adhere to the timing and protocol detailed in this appendix. The UART debugger interface uses the same protocol as the UART boot loader interface discussed above. The timing required to connect to this interface is shown in Figure 23. Similar to the UART boot loader, the monitor receives two bytes of information (after failing the SROM/EEPROM boot load). However, this time the header byte must be equal to 0x70. Once the monitor verifies that it is connected to a device that wants to communicate over the UART debugger interface, it sets up SPORT1 identically to the UART boot loader interface. The difference here is that when in debug mode the data received must adhere to the command protocol discussed below. Debug Mode Commands The following commands are available when in debug mode: · data memory write · data memory read · 16-bit program memory write · 16-bit program memory read · 24-bit program memory write · 24-bit program memory read Not only can these commands be used to read and write to the ADMC401 memories, the data memory write command can also be used to modify any memory-mapped registers. In addition it can be used to set variables in the monitor to start the execution of user code (see Starting User Code). Each of the commands consists of a unique 8 byte sequence that is sent to the ADMC401. For each byte that is received, the ADMC401 will transmit a corresponding response byte. The external device has the option of reading this known response as a means of synchronizing with the ADMC401. While not required, this is recommended. It is important to note that when the data memory write command is used to modify memory-mapped registers, the register will be modified after the 7th byte of the command is received. The 8th byte is still required to stay synchronized, but this is its only purpose. In some cases, it is advantageous to write only 7 bytes of the data memory write command to the ADMC401 and then re-synchronize with it after the register modification takes place (see Synchronizing Communication). One such example is changing SPORT1’s baud rate in the SCLKDIV register. If an 8 byte command were used, the baud rate would actually change while the 8th byte is being transferred, resulting in unpredictable behavior. The ADMC401 monitor command syntax is given in Table 9 through Table 14. For each command byte, 0 is the first byte sent over the interface. Bytes listed as “dummy bytes” can be any value because the monitor ignores them. Whatever byte is sent, will be echoed back verbatim. Appendix H. UART Debugger Protocol ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 62 Command Code Command 0 Data memory write 1 Data memory read 2 16-bit program memory write 3 16-bit program memory read 4 24-bit program memory write 5 24-bit program memory read Table 8. Available Commands (Debugger Interface) BYTE Description Expected Response 0 0x00 (dummy byte) Byte 0 is echoed back 1 Lower Byte of DM Data Word Byte 1 is echoed back 2 Upper Byte of DM Data Word Byte 2 is echoed back 3 Lower Byte of DM Destination Address Byte 3 is echoed back 4 Upper Byte of DM Destination Address Byte 4 is echoed back 5 0x00 (Command code - from Table 8) Byte 5 is echoed back 6 0x00 (dummy byte) 0xAA 7 0x00 (dummy byte) 0x55 Table 9. Data Memory Write Command BYTE Description Expected Response 0 0x00 (dummy byte) Byte 0 is echoed back 1 0x00 (dummy byte) Byte 1 is echoed back 2 0x00 (dummy byte) Byte 2 is echoed back 3 Lower Byte of DM Address Byte 3 is echoed back 4 Upper Byte of DM Address Byte 4 is echoed back 5 0x01 (Command code - from Table 8) Byte 5 is echoed back 6 0x00 (dummy byte) Lower byte of DM word 7 0x00 (dummy byte) Upper byte of DM word Table 10. Data Memory Read Command BYTE Description Expected Response 0 0x00 (dummy byte) Byte 0 is echoed back 1 Middle Byte of PM Data Word Byte 1 is echoed back 2 Upper Byte of PM Data Word Byte 2 is echoed back 3 Lower Byte of PM Destination Address Byte 3 is echoed back 4 Upper Byte of PM Destination Address Byte 4 is echoed back 5 0x02 (Command code - from Table 8) Byte 5 is echoed back 6 0x00 (dummy byte) 0xAA 7 0x00 (dummy byte) 0x55 Table 11. 16-Bit Program Memory Write Command ADMC401 DSP Motor Controller Appendix H. UART Debugger Protocol Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 63 BYTE Description Expected Response 0 0x00 (dummy byte) Byte 0 is echoed back 1 0x00 (dummy byte) Byte 1 is echoed back 2 0x00 (dummy byte) Byte 2 is echoed back 3 Lower Byte of PM Address Byte 3 is echoed back 4 Upper Byte of PM Address Byte 4 is echoed back 5 0x03 (Command code - from Table 8) Byte 5 is echoed back 6 0x00 (dummy byte) Lower byte of PM data word 7 0x00 (dummy byte) Upper byte of PM data word Table 12. 16-Bit Program Memory Read Command BYTE Description Expected Response 0 Lower Byte of PM Data Word byte 0 is echoed back 1 Middle Byte of PM Data Word byte 1 is echoed back 2 Upper Byte of PM Data Word byte 2 is echoed back 3 Lower Byte of PM Destination Address byte 3 is echoed back 4 Upper Byte of PM Destination Address byte 4 is echoed back 5 0x04 (Command code - from Table 8) byte 5 is echoed back 6 0x00 (dummy byte) 0xAA 7 0x00 (dummy byte) 0x55 Table 13. 24-Bit Program Memory Write Command BYTE Description Expected Response 0 0x00 (dummy byte) byte 0 is echoed back 1 0x00 (dummy byte) byte 1 is echoed back 2 0x00 (dummy byte) byte 2 is echoed back 3 Lower Byte of PM Address byte 3 is echoed back 4 Upper Byte of PM Address byte 4 is echoed back 5 0x05 (Command code - from Table 8) Lower byte of PM word 6 0x00 (dummy byte) Middle byte of PM word 7 0x00 (dummy byte) Upper byte of PM word Table 14. 24-Bit Program Memory Read Command Starting User Code A user program can be started on the ADMC401 by writing the program’s starting address to the START_ADR variable and then writing the code 0xABCD to the EXECUTE_FLAG variable, both contained in the monitor’s data memory. This can be done with two data memory write commands to the addresses contained in Table 15. For example, Table 16 shows the two-command sequence that an external device would send to the ADMC401 to start a user program at 0x0060 in program memory. As can be seen, the second data memory write is only a 7-byte command. This is because the ADMC401 actually writes the value following the 7th byte thus causing the execution of the user program. There is no need to send an 8th byte because it would never be received by the ADMC401. Appendix H. UART Debugger Protocol ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 64 Variable Address Description START_ADR 0x3BC0 START_ADR contains location where execution will begin EXECUTE_FLAG 0x3BC1 0xABCD written here causes execution to begin Table 15. Monitor Variables for Executing User Code BYTE Description Expected Response 0 0x00 0x00 1 0x60 0x60 2 0x00 0x00 3 0xC0 0xC0 4 0x3B 0x3B 5 0x00 0x00 6 0x00 0xAA 7 0x00 0x55 0 0x00 0x00 1 0xCD 0xCD 2 0xAB 0xAB 3 0xC1 0xC1 4 0x3B 0x3B 5 0x00 0x00 6 0x00 0xAA Table 16. DM Write Commands to Start Program at 0x0060 Synchronizing Communication For the ADMC401 to properly handle incoming commands it must be synchronous with an external device. In other words, it must know when it is receiving the first word of a command. This step must be performed prior to issuing the first of any commands in debug mode. The external device can synchronize with the ADMC401 by using the monitor protocol given above and detecting when it receives the two byte sequence 0xAA, 0x55 from the ADMC401. At this point both devices know that the next byte sent will be the first byte of a command. It is only necessary to synchronize once at the beginning of a series of debug commands as long as 8 bytes are sent for each command. The easiest way to synchronize is to continually transmit a byte and receive its echo. When the received echo of two subsequent bytes is 0xAA, 0x55, the synchronization is complete. The byte that is continually sent to the ADMC401 for this purpose can be any byte except 0x00 - 0x05, 0xAA, or 0x55. ADMC401 DSP Motor Controller Appendix I. Synchronous Master Boot Load Protocol Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 65 Appendix I. Synchronous Master Boot Load Protocol The synchronous master boot load interface allows an external device to boot load the ADMC401 synchronously using the SCLK on the ADMC401. The ADMC401 acts as the master, controlling the clock, while the external device acts as the slave. SPORT1 is configured as a synchronous serial port. The timing required to connect to this interface is shown in Figure 23. The ADMC401 switches to this interface when it receives a two-byte sequence of 0x70, 0x73 after failing an SROM/EEPROM boot load. The ADMC401 turns on SCLK1 at the rate at which it receives the autobaud byte 0x70. It then receives the data to be loaded in the order given in Table 7. If the ADMC401 is successful in loading a user program over this interface, then execution of the program will start at 0x0060. Once the monitor verifies the header byte is 0x73, it sets up SPORT1 as follows: SPORT1 control register = 0x7E07 · internal serial clock (SCLK) used · external receive frame synch (RFS) enabled · internal transmit frame synch (TFS) enabled · RFS and TFS required on every word · active high RFS and TFS · alternate receive and transmit framing used · right justify, zero-fill unused MSBs · serial word length is 8 bits The autobaud feature determines the SPORT1 SCLKDIV register value. SCLKDIV is set to a value that represents the clock rate at which the autobaud byte was received. The data received is sampled at this rate, not at 3 times the rate as for the UART, and each word is 1 byte in length. Words are transmitted and received MSB first. As data is received, it is loaded into memory in the same manner as with the other boot load interfaces. The format of the data is given in Table 7. Each data byte received, starting with the number of PM data words byte, is echoed back over DT1. The autobaud and header bytes are not echoed back. The external device may use this echo as a means of synchronization and verification that the data has been received correctly. As with the other boot load interfaces, the monitor calculates a checksum for the program and data memory words. If the monitor detects a checksum miscompare it will restart itself as if a reset has occurred. If the monitor successfully loads the program and data memories without error, then it starts execution of the program at location 0x0060. Appendix J. Synchronous Master Debugger ProtocolADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 66 Appendix J. Synchronous Master Debugger Protocol The synchronous master debugger interface allows an external device to connect to the debugger interface on the ADMC401 synchronously, using the SCLK on the ADMC401. The ADMC401 acts as the master, controlling the clock, while the external device acts as the slave. SPORT1 is configured as a synchronous serial port. The timing required to connect to this interface is shown in Figure 23. The ADMC401 switches to this interface when it receives a two-byte sequence of 0x70, 0x72 after failing an SROM/EEPROM boot load. The ADMC401 turns on SCLK1 at the rate at which it receives the autobaud byte 0x70. It then processes commands received over SPORT1 from the external device. Once the monitor verifies the header byte is 0x72, it sets up SPORT1 as follows: SPORT1 control register = 0x7E07 · internal serial clock (SCLK) used · external receive frame synch (RFS) enabled · internal transmit frame synch (TFS) enabled · RFS and TFS required on every word · active high RFS and TFS · alternate receive and transmit framing used · right justify, zero-fill unused MSBs · serial word length is 8 bits The autobaud feature determines the SPORT1 SCLKDIV register value. SCLKDIV is set to a value that represents the clock rate at which the autobaud byte was received. The data received is sampled at this rate, not at 3 times the rate as for the UART, and each word is 1 byte in length. Words are transmitted and received MSB first. A complete description of the available commands is given in Appendix H. ADMC401 DSP Motor Controller Appendix K. Synchronous Slave Boot Loader Protocol Developer’s Reference Manual 2 March 2000 Rev. 2.0 82-001925-01 67 Appendix K. Synchronous Slave Boot Loader Protocol The synchronous slave boot load interface allows an external device to boot load the ADMC401 synchronously, using its own SCLK. The external device acts as the master, controlling the clock, while the ADMC401 acts as the slave. SPORT1 is configured as a synchronous serial port. The timing required to connect to this interface is shown in Figure 23. The ADMC401 switches to this interface when it receives a two-byte sequence of 0x70, 0x75 after failing an SROM/EEPROM boot load. The ADMC401 configures SPORT1 to use the external clock connected to SCLK1. It then receives the data to be loaded in the order given in Table 7. If the ADMC401 is successful in loading a user program over this interface, then execution of the program will start at 0x0060. Once the monitor verifies the header byte is 0x75, it sets up SPORT1 as follows: SPORT1 control register = 0x3E07 · external serial clock (SCLK) used · external receive frame synch (RFS) enabled · internal transmit frame synch (TFS) enabled · RFS and TFS required on every word · active high RFS and TFS · alternate receive and transmit framing used · right justify, zero-fill unused MSBs · serial word length is 8 bits Words are transmitted and received MSB first. As data is received, it is loaded into memory in the same manner as with the other boot load interfaces. The format of the data is given in Table 7. Each data byte received, starting with the number of PM data words byte, is echoed back over DT1. The autobaud and header bytes are not echoed back. The external device may use this echo as a means of synchronization and verification that the data has been received correctly. As with the other boot load interfaces, the monitor calculates a checksum for the program and data memory words. If the monitor detects a checksum miscompare it will restart itself as if a reset has occurred. If the monitor successfully loads the program and data memories without error, then it starts execution of the program at location 0x0060. Appendix L. Synchronous Slave Debugger Protocol ADMC401 DSP Motor Controller Developer’s Reference Manual Rev. 2.0 2 March 2000 82-001925-01 68 Appendix L. Synchronous Slave Debugger Protocol The synchronous slave debugger interface allows an external device to connect to the debugger interface on the ADMC401 synchronously, using its own SCLK. The external device acts as the master, controlling the clock, while the ADMC401 acts as the slave. SPORT1 is configured as a synchronous serial port. The timing required to connect to this interface is shown in Figure 23. The ADMC401 switches to this interface when it receives a two-byte sequence of 0x70, 0x74 after failing an SROM/EEPROM boot load. The ADMC401 configures SPORT1 to use the external clock connected to SCLK1. It then processes commands received over SPORT1 from the external device. Once the monitor verifies the header byte is 0x74, it sets up SPORT1 as follows: SPORT1 control register = 0x3E07 · external serial clock (SCLK) used · external receive frame synch (RFS) enabled · internal transmit frame synch (TFS) enabled · RFS and TFS required on every word · active high RFS and TFS · alternate receive and transmit framing used · right justify, zero-fill unused MSBs · serial word length is 8 bits Words are transmitted and received MSB first. A complete description of the available commands is given in Appendix H CHAPTER 12 The Fast Fourier Transform There are several ways to calculate the Discrete Fourier Transform (DFT), such as solving simultaneous linear equations or the correlation method described in Chapter 8. The Fast Fourier Transform (FFT) is another method for calculating the DFT. While it produces the same result as the other approaches, it is incredibly more efficient, often reducing the computation time by hundreds. This is the same improvement as flying in a jet aircraft versus walking! If the FFT were not available, many of the techniques described in this book would not be practical. While the FFT only requires a few dozen lines of code, it is one of the most complicated algorithms in DSP. But don't despair! You can easily use published FFT routines without fully understanding the internal workings. Real DFT Using the Complex DFT J.W. Cooley and J.W. Tukey are given credit for bringing the FFT to the world in their paper: "An algorithm for the machine calculation of complex Fourier Series," Mathematics Computation, Vol. 19, 1965, pp 297-301. In retrospect, others had discovered the technique many years before. For instance, the great German mathematician Karl Friedrich Gauss (1777-1855) had used the method more than a century earlier. This early work was largely forgotten because it lacked the tool to make it practical: the digital computer. Cooley and Tukey are honored because they discovered the FFT at the right time, the beginning of the computer revolution. The FFT is based on the complex DFT, a more sophisticated version of the real DFT discussed in the last four chapters. These transforms are named for the way each represents data, that is, using complex numbers or using real numbers. The term complex does not mean that this representation is difficult or complicated, but that a specific type of mathematics is used. Complex mathematics often is difficult and complicated, but that isn't where the name comes from. Chapter 29 discusses the complex DFT and provides the background needed to understand the details of the FFT algorithm. The 226 The Scientist and Engineer's Guide to Digital Signal Processing FIGURE 12-1 Comparing the real and complex DFTs. The real DFT takes an N point time domain signal and creates two N/2% 1 point frequency domain signals. The complex DFT takes two N point time domain signals and creates two N point frequency domain signals. The crosshatched regions shows the values common to the two transforms. Real DFT Complex DFT Time Domain Time Domain Frequency Domain Frequency Domain 0 N-1 0 N-1 0 N-1 0 N/2 0 N/2 0 0 N-1 N-1 N/2 N/2 Real Part Imaginary Part Real Part Imaginary Part Real Part Imaginary Part Time Domain Signal topic of this chapter is simpler: how to use the FFT to calculate the real DFT, without drowning in a mire of advanced mathematics. Since the FFT is an algorithm for calculating the complex DFT, it is important to understand how to transfer real DFT data into and out of the complex DFT format. Figure 12-1 compares how the real DFT and the complex DFT store data. The real DFT transforms an N point time domain signal into two N/2 % 1 point frequency domain signals. The time domain signal is called just that: the time domain signal. The two signals in the frequency domain are called the real part and the imaginary part, holding the amplitudes of the cosine waves and sine waves, respectively. This should be very familiar from past chapters. In comparison, the complex DFT transforms two N point time domain signals into two N point frequency domain signals. The two time domain signals are called the real part and the imaginary part, just as are the frequency domain signals. In spite of their names, all of the values in these arrays are just ordinary numbers. (If you are familiar with complex numbers: the j's are not included in the array values; they are a part of the mathematics. Recall that the operator, Im( ), returns a real number). Chapter 12- The Fast Fourier Transform 227 6000 'NEGATIVE FREQUENCY GENERATION 6010 'This subroutine creates the complex frequency domain from the real frequency domain. 6020 'Upon entry to this subroutine, N% contains the number of points in the signals, and 6030 'REX[ ] and IMX[ ] contain the real frequency domain in samples 0 to N%/2. 6040 'On return, REX[ ] and IMX[ ] contain the complex frequency domain in samples 0 to N%-1. 6050 ' 6060 FOR K% = (N%/2+1) TO (N%-1) 6070 REX[K%] = REX[N%-K%] 6080 IMX[K%] = -IMX[N%-K%] 6090 NEXT K% 6100 ' 6110 RETURN TABLE 12-1 Suppose you have an N point signal, and need to calculate the real DFT by means of the Complex DFT (such as by using the FFT algorithm). First, move the N point signal into the real part of the complex DFT's time domain, and then set all of the samples in the imaginary part to zero. Calculation of the complex DFT results in a real and an imaginary signal in the frequency domain, each composed of N points. Samples 0 through N/2 of these signals correspond to the real DFT's spectrum. As discussed in Chapter 10, the DFT's frequency domain is periodic when the negative frequencies are included (see Fig. 10-9). The choice of a single period is arbitrary; it can be chosen between -1.0 and 0, -0.5 and 0.5, 0 and 1.0, or any other one unit interval referenced to the sampling rate. The complex DFT's frequency spectrum includes the negative frequencies in the 0 to 1.0 arrangement. In other words, one full period stretches from sample 0 to sample N&1 , corresponding with 0 to 1.0 times the sampling rate. The positive frequencies sit between sample 0 and N/2 , corresponding with 0 to 0.5. The other samples, between N/2% 1 and N&1 , contain the negative frequency values (which are usually ignored). Calculating a real Inverse DFT using a complex Inverse DFT is slightly harder. This is because you need to insure that the negative frequencies are loaded in the proper format. Remember, points 0 through N/2 in the complex DFT are the same as in the real DFT, for both the real and the imaginary parts. For the real part, point N/2% 1 is the same as point N/2& 1 , point N/2% 2 is the same as point N/2& 2 , etc. This continues to point N&1 being the same as point 1. The same basic pattern is used for the imaginary part, except the sign is changed. That is, point N/2% 1 is the negative of point N/2& 1 , point N/2% 2 is the negative of point N/2& 2 , etc. Notice that samples 0 and N/2 do not have a matching point in this duplication scheme. Use Fig. 10-9 as a guide to understanding this symmetry. In practice, you load the real DFT's frequency spectrum into samples 0 to N/2 of the complex DFT's arrays, and then use a subroutine to generate the negative frequencies between samples N/2% 1 and N&1 . Table 12-1 shows such a program. To check that the proper symmetry is present, after taking the inverse FFT, look at the imaginary part of the time domain. It will contain all zeros if everything is correct (except for a few parts-permillion of noise, using single precision calculations). 228 The Scientist and Engineer's Guide to Digital Signal Processing FIGURE 12-2 The FFT decomposition. An N point signal is decomposed into N signals each containing a single point. Each stage uses an interlace decomposition, separating the even and odd numbered samples. 1 signal of 16 points 2 signals of 8 points 4 signals of 4 points 8 signals of 2 points 16 signals of 1 point 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 2 4 6 8 10 12 14 1 3 5 7 9 11 13 15 0 4 8 12 2 6 10 14 1 5 9 13 3 7 11 15 0 8 4 12 2 10 6 14 1 9 5 13 3 11 7 15 0 8 4 12 2 10 6 14 1 9 5 13 3 11 7 15 How the FFT works The FFT is a complicated algorithm, and its details are usually left to those that specialize in such things. This section describes the general operation of the FFT, but skirts a key issue: the use of complex numbers. If you have a background in complex mathematics, you can read between the lines to understand the true nature of the algorithm. Don't worry if the details elude you; few scientists and engineers that use the FFT could write the program from scratch. In complex notation, the time and frequency domains each contain one signal made up of N complex points. Each of these complex points is composed of two numbers, the real part and the imaginary part. For example, when we talk about complex sample X[42] , it refers to the combination of ReX[42] and ImX[42]. In other words, each complex variable holds two numbers. When two complex variables are multiplied, the four individual components must be combined to form the two components of the product (such as in Eq. 9-1). The following discussion on "How the FFT works" uses this jargon of complex notation. That is, the singular terms: signal, point, sample, and value, refer to the combination of the real part and the imaginary part. The FFT operates by decomposing an N point time domain signal into N time domain signals each composed of a single point. The second step is to calculate the N frequency spectra corresponding to these N time domain signals. Lastly, the N spectra are synthesized into a single frequency spectrum. Figure 12-2 shows an example of the time domain decomposition used in the FFT. In this example, a 16 point signal is decomposed through four Chapter 12- The Fast Fourier Transform 229 Sample numbers Sample numbers in normal order after bit reversal Decimal Binary Decimal Binary 0 0000 0 0000 1 0001 8 1000 2 0010 4 0100 3 0011 12 1100 4 0100 2 0010 5 0101 10 1010 6 0110 6 0100 7 0111 14 1110 8 1000 1 0001 9 1001 9 1001 10 1010 5 0101 11 1011 13 1101 12 1100 3 0011 13 1101 11 1011 14 1110 7 0111 15 1111 15 1111 FIGURE 12-3 The FFT bit reversal sorting. The FFT time domain decomposition can be implemented by sorting the samples according to bit reversed order. separate stages. The first stage breaks the 16 point signal into two signals each consisting of 8 points. The second stage decomposes the data into four signals of 4 points. This pattern continues until there are N signals composed of a single point. An interlaced decomposition is used each time a signal is broken in two, that is, the signal is separated into its even and odd numbered samples. The best way to understand this is by inspecting Fig. 12-2 until you grasp the pattern. There are Log stages required in this decomposition, i.e., 2N a 16 point signal (24) requires 4 stages, a 512 point signal (27) requires 7 stages, a 4096 point signal (212) requires 12 stages, etc. Remember this value, Log ; it will be referenced many times in this chapter. 2N Now that you understand the structure of the decomposition, it can be greatly simplified. The decomposition is nothing more than a reordering of the samples in the signal. Figure 12-3 shows the rearrangement pattern required. On the left, the sample numbers of the original signal are listed along with their binary equivalents. On the right, the rearranged sample numbers are listed, also along with their binary equivalents. The important idea is that the binary numbers are the reversals of each other. For example, sample 3 (0011) is exchanged with sample number 12 (1100). Likewise, sample number 14 (1110) is swapped with sample number 7 (0111), and so forth. The FFT time domain decomposition is usually carried out by a bit reversal sorting algorithm. This involves rearranging the order of the N time domain samples by counting in binary with the bits flipped left-for-right (such as in the far right column in Fig. 12-3). 230 The Scientist and Engineer's Guide to Digital Signal Processing a b c d a 0 b 0 c 0 d 0 A B C D A B C D A B C D e f g h 0 e 0 f 0 g 0 h E F G H F G H E F G H × sinusoid Time Domain Frequency Domain E FIGURE 12-4 The FFT synthesis. When a time domain signal is diluted with zeros, the frequency domain is duplicated. If the time domain signal is also shifted by one sample during the dilution, the spectrum will additionally be multiplied by a sinusoid. The next step in the FFT algorithm is to find the frequency spectra of the 1 point time domain signals. Nothing could be easier; the frequency spectrum of a 1 point signal is equal to itself. This means that nothing is required to do this step. Although there is no work involved, don't forget that each of the 1 point signals is now a frequency spectrum, and not a time domain signal. The last step in the FFT is to combine the N frequency spectra in the exact reverse order that the time domain decomposition took place. This is where the algorithm gets messy. Unfortunately, the bit reversal shortcut is not applicable, and we must go back one stage at a time. In the first stage, 16 frequency spectra (1 point each) are synthesized into 8 frequency spectra (2 points each). In the second stage, the 8 frequency spectra (2 points each) are synthesized into 4 frequency spectra (4 points each), and so on. The last stage results in the output of the FFT, a 16 point frequency spectrum. Figure 12-4 shows how two frequency spectra, each composed of 4 points, are combined into a single frequency spectrum of 8 points. This synthesis must undo the interlaced decomposition done in the time domain. In other words, the frequency domain operation must correspond to the time domain procedure of combining two 4 point signals by interlacing. Consider two time domain signals, abcd and efgh. An 8 point time domain signal can be formed by two steps: dilute each 4 point signal with zeros to make it an Chapter 12- The Fast Fourier Transform 231 + + + + + + + + Eight Point Frequency Spectrum Odd- Four Point Frequency Spectrum Even- Four Point Frequency Spectrum xS xS xS xS FIGURE 12-5 FFT synthesis flow diagram. This shows the method of combining two 4 point frequency spectra into a single 8 point frequency spectrum. The ×S operation means that the signal is multiplied by a sinusoid with an appropriately selected frequency. 2 point input 2 point output xS FIGURE 12-6 The FFT butterfly. This is the basic calculation element in the FFT, taking two complex points and converting them into two other complex points. 8 point signal, and then add the signals together. That is, abcd becomes a0b0c0d0, and efgh becomes 0e0f0g0h. Adding these two 8 point signals produces aebfcgdh. As shown in Fig. 12-4, diluting the time domain with zeros corresponds to a duplication of the frequency spectrum. Therefore, the frequency spectra are combined in the FFT by duplicating them, and then adding the duplicated spectra together. In order to match up when added, the two time domain signals are diluted with zeros in a slightly different way. In one signal, the odd points are zero, while in the other signal, the even points are zero. In other words, one of the time domain signals (0e0f0g0h in Fig. 12-4) is shifted to the right by one sample. This time domain shift corresponds to multiplying the spectrum by a sinusoid. To see this, recall that a shift in the time domain is equivalent to convolving the signal with a shifted delta function. This multiplies the signal's spectrum with the spectrum of the shifted delta function. The spectrum of a shifted delta function is a sinusoid (see Fig 11-2). Figure 12-5 shows a flow diagram for combining two 4 point spectra into a single 8 point spectrum. To reduce the situation even more, notice that Fig. 12- 5 is formed from the basic pattern in Fig 12-6 repeated over and over. 232 The Scientist and Engineer's Guide to Digital Signal Processing Time Domain Data Frequency Domain Data Bit Reversal Data Sorting Overhead Overhead Calculation Decomposition Synthesis Time Domain Frequency Domain Butterfly FIGURE 12-7 Flow diagram of the FFT. This is based on three steps: (1) decompose an N point time domain signal into N signals each containing a single point, (2) find the spectrum of each of the N point signals (nothing required), and (3) synthesize the N frequency spectra into a single frequency spectrum. Loop for each Butterfly Loop for Leach sub-DFT Loop for Log2N stages This simple flow diagram is called a butterfly due to its winged appearance. The butterfly is the basic computational element of the FFT, transforming two complex points into two other complex points. Figure 12-7 shows the structure of the entire FFT. The time domain decomposition is accomplished with a bit reversal sorting algorithm. Transforming the decomposed data into the frequency domain involves nothing and therefore does not appear in the figure. The frequency domain synthesis requires three loops. The outer loop runs through the Log stages (i.e., each level in Fig. 12-2, starting from the bottom 2N and moving to the top). The middle loop moves through each of the individual frequency spectra in the stage being worked on (i.e., each of the boxes on any one level in Fig. 12-2). The innermost loop uses the butterfly to calculate the points in each frequency spectra (i.e., looping through the samples inside any one box in Fig. 12-2). The overhead boxes in Fig. 12-7 determine the beginning and ending indexes for the loops, as well as calculating the sinusoids needed in the butterflies. Now we come to the heart of this chapter, the actual FFT programs. Chapter 12- The Fast Fourier Transform 233 5000 'COMPLEX DFT BY CORRELATION 5010 'Upon entry, N% contains the number of points in the DFT, and 5020 'XR[ ] and XI[ ] contain the real and imaginary parts of the time domain. 5030 'Upon return, REX[ ] and IMX[ ] contain the frequency domain data. 5040 'All signals run from 0 to N%-1. 5050 ' 5060 PI = 3.14159265 'Set constants 5070 ' 5080 FOR K% = 0 TO N%-1 'Zero REX[ ] and IMX[ ], so they can be used 5090 REX[K%] = 0 'as accumulators during the correlation 5100 IMX[K%] = 0 5110 NEXT K% 5120 ' 5130 FOR K% = 0 TO N%-1 'Loop for each value in frequency domain 5140 FOR I% = 0 TO N%-1 'Correlate with the complex sinusoid, SR & SI 5150 ' 5160 SR = COS(2*PI*K%*I%/N%) 'Calculate complex sinusoid 5170 SI = -SIN(2*PI*K%*I%/N%) 5180 REX[K%] = REX[K%] + XR[I%]*SR - XI[I%]*SI 5190 IMX[K%] = IMX[K%] + XR[I%]*SI + XI[I%]*SR 5200 ' 5210 NEXT I% 5220 NEXT K% 5230 ' 5240 RETURN TABLE 12-2 FFT Programs As discussed in Chapter 8, the real DFT can be calculated by correlating the time domain signal with sine and cosine waves (see Table 8-2). Table 12-2 shows a program to calculate the complex DFT by the same method. In an apples-to-apples comparison, this is the program that the FFT improves upon. Tables 12-3 and 12-4 show two different FFT programs, one in FORTRAN and one in BASIC. First we will look at the BASIC routine in Table 12-4. This subroutine produces exactly the same output as the correlation technique in Table 12-2, except it does it much faster. The block diagram in Fig. 12-7 can be used to identify the different sections of this program. Data are passed to this FFT subroutine in the arrays: REX[ ] and IMX[ ], each running from sample 0 to N&1 . Upon return from the subroutine, REX[ ] and IMX[ ] are overwritten with the frequency domain data. This is another way that the FFT is highly optimized; the same arrays are used for the input, intermediate storage, and output. This efficient use of memory is important for designing fast hardware to calculate the FFT. The term in-place computation is used to describe this memory usage. While all FFT programs produce the same numerical result, there are subtle variations in programming that you need to look out for. Several of these 234 The Scientist and Engineer's Guide to Digital Signal Processing TABLE 12-3 The Fast Fourier Transform in FORTRAN. Data are passed to this subroutine in the variables X( ) and M. The integer, M, is the base two logarithm of the length of the DFT, i.e., M = 8 for a 256 point DFT, M = 12 for a 4096 point DFT, etc. The complex array, X( ), holds the time domain data upon entering the DFT. Upon return from this subroutine, X( ) is overwritten with the frequency domain data. Take note: this subroutine requires that the input and output signals run from X(1) through X(N), rather than the customary X(0) through X(N-1). SUBROUTINE FFT(X,M) COMPLEX X(4096),U,S,T PI=3.14159265 N=2**M DO 20 L=1,M LE=2**(M+1-L) LE2=LE/2 U=(1.0,0.0) S=CMPLX(COS(PI/FLOAT(LE2)),-SIN(PI/FLOAT(LE2))) DO 20 J=1,LE2 DO 10 I=J,N,LE IP=I+LE2 T=X(I)+X(IP) X(IP)=(X(I)-X(IP))*U 10 X(I)=T 20 U=U*S ND2=N/2 NM1=N-1 J=1 DO 50 I=1,NM1 IF(I.GE.J) GO TO 30 T=X(J) X(J)=X(I) X(I)=T 30 K=ND2 40 IF(K.GE.J) GO TO 50 J=J-K K=K/2 GO TO 40 50 J=J+K RETURN END of these differences are illustrated by the FORTRAN program listed in Table 12-3. This program uses an algorithm called decimation in frequency, while the previously described algorithm is called decimation in time. In a decimation in frequency algorithm, the bit reversal sorting is done after the three nested loops. There are also FFT routines that completely eliminate the bit reversal sorting. None of these variations significantly improve the performance of the FFT, and you shouldn't worry about which one you are using. The important differences between FFT algorithms concern how data are passed to and from the subroutines. In the BASIC program, data enter and leave the subroutine in the arrays REX[ ] and IMX[ ], with the samples running from index 0 to N&1 . In the FORTRAN program, data are passed in the complex array X( ), with the samples running from 1 to N. Since this is an array of complex variables, each sample in X( ) consists of two numbers, a real part and an imaginary part. The length of the DFT must also be passed to these subroutines. In the BASIC program, the variable N% is used for this purpose. In comparison, the FORTRAN program uses the variable M, which is defined to equal Log . For instance, M will be 2N Chapter 12- The Fast Fourier Transform 235 TABLE 12-4 The Fast Fourier Transform in BASIC. 1000 'THE FAST FOURIER TRANSFORM 1010 'Upon entry, N% contains the number of points in the DFT, REX[ ] and 1020 'IMX[ ] contain the real and imaginary parts of the input. Upon return, 1030 'REX[ ] and IMX[ ] contain the DFT output. All signals run from 0 to N%-1. 1040 ' 1050 PI = 3.14159265 'Set constants 1060 NM1% = N%-1 1070 ND2% = N%/2 1080 M% = CINT(LOG(N%)/LOG(2)) 1090 J% = ND2% 1100 ' 1110 FOR I% = 1 TO N%-2 'Bit reversal sorting 1120 IF I% >= J% THEN GOTO 1190 1130 TR = REX[J%] 1140 TI = IMX[J%] 1150 REX[J%] = REX[I%] 1160 IMX[J%] = IMX[I%] 1170 REX[I%] = TR 1180 IMX[I%] = TI 1190 K% = ND2% 1200 IF K% > J% THEN GOTO 1240 1210 J% = J%-K% 1220 K% = K%/2 1230 GOTO 1200 1240 J% = J%+K% 1250 NEXT I% 1260 ' 1270 FOR L% = 1 TO M% 'Loop for each stage 1280 LE% = CINT(2^L%) 1290 LE2% = LE%/2 1300 UR = 1 1310 UI = 0 1320 SR = COS(PI/LE2%) 'Calculate sine & cosine values 1330 SI = -SIN(PI/LE2%) 1340 FOR J% = 1 TO LE2% 'Loop for each sub DFT 1350 JM1% = J%-1 1360 FOR I% = JM1% TO NM1% STEP LE% 'Loop for each butterfly 1370 IP% = I%+LE2% 1380 TR = REX[IP%]*UR - IMX[IP%]*UI 'Butterfly calculation 1390 TI = REX[IP%]*UI + IMX[IP%]*UR 1400 REX[IP%] = REX[I%]-TR 1410 IMX[IP%] = IMX[I%]-TI 1420 REX[I%] = REX[I%]+TR 1430 IMX[I%] = IMX[I%]+TI 1440 NEXT I% 1450 TR = UR 1460 UR = TR*SR - UI*SI 1470 UI = TR*SI + UI*SR 1480 NEXT J% 1490 NEXT L% 1500 ' 1510 RETURN 236 The Scientist and Engineer's Guide to Digital Signal Processing 2000 'INVERSE FAST FOURIER TRANSFORM SUBROUTINE 2010 'Upon entry, N% contains the number of points in the IDFT, REX[ ] and 2020 'IMX[ ] contain the real and imaginary parts of the complex frequency domain. 2030 'Upon return, REX[ ] and IMX[ ] contain the complex time domain. 2040 'All signals run from 0 to N%-1. 2050 ' 2060 FOR K% = 0 TO N%-1 'Change the sign of IMX[ ] 2070 IMX[K%] = -IMX[K%] 2080 NEXT K% 2090 ' 2100 GOSUB 1000 'Calculate forward FFT (Table 12-3) 2110 ' 2120 FOR I% = 0 TO N%-1 'Divide the time domain by N% and 2130 REX[I%] = REX[I%]/N% 'change the sign of IMX[ ] 2140 IMX[I%] = -IMX[I%]/N% 2150 NEXT I% 2160 ' 2170 RETURN TABLE 12-5 8 for a 256 point DFT, 12 for a 4096 point DFT, etc. The point is, the programmer who writes an FFT subroutine has many options for interfacing with the host program. Arrays that run from 1 to N, such as in the FORTRAN program, are especially aggravating. Most of the DSP literature (including this book) explains algorithms assuming the arrays run from sample 0 to N&1 . For instance, if the arrays run from 1 to N, the symmetry in the frequency domain is around points 1 and N/2% 1 , rather than points 0 and N/2 , Using the complex DFT to calculate the real DFT has another interesting advantage. The complex DFT is more symmetrical between the time and frequency domains than the real DFT. That is, the duality is stronger. Among other things, this means that the Inverse DFT is nearly identical to the Forward DFT. In fact, the easiest way to calculate an Inverse FFT is to calculate a Forward FFT, and then adjust the data. Table 12-5 shows a subroutine for calculating the Inverse FFT in this manner. Suppose you copy one of these FFT algorithms into your computer program and start it running. How do you know if it is operating properly? Two tricks are commonly used for debugging. First, start with some arbitrary time domain signal, such as from a random number generator, and run it through the FFT. Next, run the resultant frequency spectrum through the Inverse FFT and compare the result with the original signal. They should be identical, except round-off noise (a few parts-per-million for single precision). The second test of proper operation is that the signals have the correct symmetry. When the imaginary part of the time domain signal is composed of all zeros (the normal case), the frequency domain of the complex DFT will be symmetrical around samples 0 and N/2 , as previously described. Chapter 12- The Fast Fourier Transform 237 EQUATION 12-1 DFT execution time. The time required to calculate a DFT by correlation is proportional to the length of the DFT squared. ExecutionTime ’ kDFT N2 EQUATION 12-2 FFT execution time. The time required to calculate a DFT using the FFT is proportional to N multiplied by the logarithm of N. ExecutionTime ’ kFFT N log2N Likewise, when this correct symmetry is present in the frequency domain, the Inverse DFT will produce a time domain that has an imaginary part composes of all zeros (plus round-off noise). These debugging techniques are essential for using the FFT; become familiar with them. Speed and Precision Comparisons When the DFT is calculated by correlation (as in Table 12-2), the program uses two nested loops, each running through N points. This means that the total number of operations is proportional to N times N. The time to complete the program is thus given by: where N is the number of points in the DFT and kDFT is a constant of proportionality. If the sine and cosine values are calculated within the nested loops, kDFT is equal to about 25 microseconds on a Pentium at 100 MHz. If you precalculate the sine and cosine values and store them in a look-up-table, kDFT drops to about 7 microseconds. For example, a 1024 point DFT will require about 25 seconds, or nearly 25 milliseconds per point. That's slow! Using this same strategy we can derive the execution time for the FFT. The time required for the bit reversal is negligible. In each of the Log stages 2N there are N/2 butterfly computations. This means the execution time for the program is approximated by: The value of kFFT is about 10 microseconds on a 100 MHz Pentium system. A 1024 point FFT requires about 70 milliseconds to execute, or 70 microseconds per point. This is more than 300 times faster than the DFT calculated by correlation! Not only is NLog less than , it increases much more slowly as N 2N N 2 becomes larger. For example, a 32 point FFT is about ten times faster than the correlation method. However, a 4096 point FFT is one-thousand times faster. For small values of N (say, 32 to 128), the FFT is important. For large values of N (1024 and above), the FFT is absolutely critical. Figure 12-8 compares the execution times of the two algorithms in a graphical form. 238 The Scientist and Engineer's Guide to Digital Signal Processing Number points in DFT 8 16 32 64 128 256 512 1024 2048 4096 0.001 0.01 0.1 1 10 100 1000 FFT correlation correlation w/LUT FIGURE 12-8 Execution times for calculating the DFT. The correlation method refers to the algorithm described in Table 12-2. This method can be made faster by precalculating the sine and cosine values and storing them in a look-up table (LUT). The FFT (Table 12-3) is the fastest algorithm when the DFT is greater than 16 points long. The times shown are for a Pentium processor at 100 MHz. Execution time (seconds) Number of points in DFT 16 32 64 128 256 512 1024 0 10 20 30 40 50 60 70 FFT correlation FIGURE 12-9 DFT precision. Since the FFT calculates the DFT faster than the correlation method, it also calculates it with less round-off error. Error (parts per million) The FFT has another advantage besides raw speed. The FFT is calculated more precisely because the fewer number of calculations results in less round-off error. This can be demonstrated by taking the FFT of an arbitrary signal, and then running the frequency spectrum through an Inverse FFT. This reconstructs the original time domain signal, except for the addition of roundoff noise from the calculations. A single number characterizing this noise can be obtained by calculating the standard deviation of the difference between the two signals. For comparison, this same procedure can be repeated using a DFT calculated by correlation, and a corresponding Inverse DFT. How does the round-off noise of the FFT compare to the DFT by correlation? See for yourself in Fig. 12-9. Further Speed Increases There are several techniques for making the FFT even faster; however, the improvements are only about 20-40%. In one of these methods, the time Chapter 12- The Fast Fourier Transform 239 4000 'INVERSE FFT FOR REAL SIGNALS 4010 'Upon entry, N% contains the number of points in the IDFT, REX[ ] and 4020 'IMX[ ] contain the real and imaginary parts of the frequency domain running from 4030 'index 0 to N%/2. The remaining samples in REX[ ] and IMX[ ] are ignored. 4040 'Upon return, REX[ ] contains the real time domain, IMX[ ] contains zeros. 4050 ' 4060 ' 4070 FOR K% = (N%/2+1) TO (N%-1) 'Make frequency domain symmetrical 4080 REX[K%] = REX[N%-K%] '(as in Table 12-1) 4090 IMX[K%] = -IMX[N%-K%] 4100 NEXT K% 4110 ' 4120 FOR K% = 0 TO N%-1 'Add real and imaginary parts together 4130 REX[K%] = REX[K%]+IMX[K%] 4140 NEXT K% 4150 ' 4160 GOSUB 3000 'Calculate forward real DFT (TABLE 12-6) 4170 ' 4180 FOR I% = 0 TO N%-1 'Add real and imaginary parts together 4190 REX[I%] = (REX[I%]+IMX[I%])/N% 'and divide the time domain by N% 4200 IMX[I%] = 0 4210 NEXT I% 4220 ' 4230 RETURN TABLE 12-6 domain decomposition is stopped two stages early, when each signals is composed of only four points. Instead of calculating the last two stages, highly optimized code is used to jump directly into the frequency domain, using the simplicity of four point sine and cosine waves. Another popular algorithm eliminates the wasted calculations associated with the imaginary part of the time domain being zero, and the frequency spectrum being symmetrical. In other words, the FFT is modified to calculate the real DFT, instead of the complex DFT. These algorithms are called the real FFT and the real Inverse FFT (or similar names). Expect them to be about 30% faster than the conventional FFT routines. Tables 12-6 and 12-7 show programs for these algorithms. There are two small disadvantages in using the real FFT. First, the code is about twice as long. While your computer doesn't care, you must take the time to convert someone else's program to run on your computer. Second, debugging these programs is slightly harder because you cannot use symmetry as a check for proper operation. These algorithms force the imaginary part of the time domain to be zero, and the frequency domain to have left-right symmetry. For debugging, check that these programs produce the same output as the conventional FFT algorithms. Figures 12-10 and 12-11 illustrate how the real FFT works. In Fig. 12-10, (a) and (b) show a time domain signal that consists of a pulse in the real part, and all zeros in the imaginary part. Figures (c) and (d) show the corresponding frequency spectrum. As previously described, the frequency domain's real part has an even symmetry around sample 0 and sample N/2 , while the imaginary part has an odd symmetry around these same points. 240 The Scientist and Engineer's Guide to Digital Signal Processing Sample number 0 16 32 48 64 -1 0 1 2 63 a. Real part Freqeuncy 0 16 32 48 -8 -4 0 4 8 c. Real part (even symmetry) 63 Frequency 0 16 32 48 -8 -4 0 4 8 d. Imaginary part (odd symmetry) 63 Time Domain Frequency Domain Sample number 0 16 32 48 64 -1 0 1 2 63 b. Imaginary part FIGURE 12-10 Real part symmetry of the DFT. Amplitude Amplitude Amplitude Amplitude Now consider Fig. 12-11, where the pulse is in the imaginary part of the time domain, and the real part is all zeros. The symmetry in the frequency domain is reversed; the real part is odd, while the imaginary part is even. This situation will be discussed in Chapter 29. For now, take it for granted that this is how the complex DFT behaves. What if there is a signal in both parts of the time domain? By additivity, the frequency domain will be the sum of the two frequency spectra. Now the key element: a frequency spectrum composed of these two types of symmetry can be perfectly separated into the two component signals. This is achieved by the even/odd decomposition discussed in Chapter 6. In other words, two real DFT's can be calculated for the price of single FFT. One of the signals is placed in the real part of the time domain, and the other signal is placed in the imaginary part. After calculating the complex DFT (via the FFT, of course), the spectra are separated using the even/odd decomposition. When two or more signals need to be passed through the FFT, this technique reduces the execution time by about 40%. The improvement isn't a full factor of two because of the calculation time required for the even/odd decomposition. This is a relatively simple technique with few pitfalls, nothing like writing an FFT routine from scratch. Chapter 12- The Fast Fourier Transform 241 Sample number 0 16 32 48 64 -1 0 1 2 63 a. Real part Frequency 0 16 32 48 -8 -4 0 4 8 c. Real part (odd symmetry) 63 Frequency 0 16 32 48 -8 -4 0 4 8 d. Imaginary part (even symmetry) 63 Time Domain Frequency Domain Sample number 0 16 32 48 64 -1 0 1 2 63 b. Imaginary part FIGURE 12-11 Imaginary part symmetry of the DFT. Amplitude Amplitude Amplitude Amplitude The next step is to modify the algorithm to calculate a single DFT faster. It's ugly, but here is how it is done. The input signal is broken in half by using an interlaced decomposition. The N/2 even points are placed into the real part of the time domain signal, while the N/2 odd points go into the imaginary part. An N/2 point FFT is then calculated, requiring about one-half the time as an N point FFT. The resulting frequency domain is then separated by the even/odd decomposition, resulting in the frequency spectra of the two interlaced time domain signals. These two frequency spectra are then combined into a single spectrum, just as in the last synthesis stage of the FFT. To close this chapter, consider that the FFT is to Digital Signal Processing what the transistor is to electronics. It is a foundation of the technology; everyone in the field knows its characteristics and how to use it. However, only a small number of specialists really understand the details of the internal workings. 242 The Scientist and Engineer's Guide to Digital Signal Processing 3000 'FFT FOR REAL SIGNALS 3010 'Upon entry, N% contains the number of points in the DFT, REX[ ] contains 3020 'the real input signal, while values in IMX[ ] are ignored. Upon return, 3030 'REX[ ] and IMX[ ] contain the DFT output. All signals run from 0 to N%-1. 3040 ' 3050 NH% = N%/2-1 'Separate even and odd points 3060 FOR I% = 0 TO NH% 3070 REX(I%) = REX(2*I%) 3080 IMX(I%) = REX(2*I%+1) 3090 NEXT I% 3100 ' 3110 N% = N%/2 'Calculate N%/2 point FFT 3120 GOSUB 1000 '(GOSUB 1000 is the FFT in Table 12-3) 3130 N% = N%*2 3140 ' 3150 NM1% = N%-1 'Even/odd frequency domain decomposition 3160 ND2% = N%/2 3170 N4% = N%/4-1 3180 FOR I% = 1 TO N4% 3190 IM% = ND2%-I% 3200 IP2% = I%+ND2% 3210 IPM% = IM%+ND2% 3220 REX(IP2%) = (IMX(I%) + IMX(IM%))/2 3230 REX(IPM%) = REX(IP2%) 3240 IMX(IP2%) = -(REX(I%) - REX(IM%))/2 3250 IMX(IPM%) = -IMX(IP2%) 3260 REX(I%) = (REX(I%) + REX(IM%))/2 3270 REX(IM%) = REX(I%) 3280 IMX(I%) = (IMX(I%) - IMX(IM%))/2 3290 IMX(IM%) = -IMX(I%) 3300 NEXT I% 3310 REX(N%*3/4) = IMX(N%/4) 3320 REX(ND2%) = IMX(0) 3330 IMX(N%*3/4) = 0 3340 IMX(ND2%) = 0 3350 IMX(N%/4) = 0 3360 IMX(0) = 0 3370 ' 3380 PI = 3.14159265 'Complete the last FFT stage 3390 L% = CINT(LOG(N%)/LOG(2)) 3400 LE% = CINT(2^L%) 3410 LE2% = LE%/2 3420 UR = 1 3430 UI = 0 3440 SR = COS(PI/LE2%) 3450 SI = -SIN(PI/LE2%) 3460 FOR J% = 1 TO LE2% 3470 JM1% = J%-1 3480 FOR I% = JM1% TO NM1% STEP LE% 3490 IP% = I%+LE2% 3500 TR = REX[IP%]*UR - IMX[IP%]*UI 3510 TI = REX[IP%]*UI + IMX[IP%]*UR 3520 REX[IP%] = REX[I%]-TR 3530 IMX[IP%] = IMX[I%]-TI 3540 REX[I%] = REX[I%]+TR 3550 IMX[I%] = IMX[I%]+TI 3560 NEXT I% 3570 TR = UR 3580 UR = TR*SR - UI*SI 3590 UI = TR*SI + UI*SR 3600 NEXT J% 3610 RETURN TABLE 12-7 CHAPTER 15 EQUATION 15-1 Equation of the moving average filter. In this equation, x[ ] is the input signal, y[ ] is the output signal, and M is the number of points used in the moving average. This equation only uses points on one side of the output sample being calculated. y[i ] ’ 1 M j M&1 j’ 0 x [ i %j ] y [80] ’ x [80] % x [81] % x [82] % x [83] % x [84] 5 Moving Average Filters The moving average is the most common filter in DSP, mainly because it is the easiest digital filter to understand and use. In spite of its simplicity, the moving average filter is optimal for a common task: reducing random noise while retaining a sharp step response. This makes it the premier filter for time domain encoded signals. However, the moving average is the worst filter for frequency domain encoded signals, with little ability to separate one band of frequencies from another. Relatives of the moving average filter include the Gaussian, Blackman, and multiplepass moving average. These have slightly better performance in the frequency domain, at the expense of increased computation time. Implementation by Convolution As the name implies, the moving average filter operates by averaging a number of points from the input signal to produce each point in the output signal. In equation form, this is written: Where x [ ] is the input signal, y [ ] is the output signal, and M is the number of points in the average. For example, in a 5 point moving average filter, point 80 in the output signal is given by: 278 The Scientist and Engineer's Guide to Digital Signal Processing y [80] ’ x [78] % x [79] % x [80] % x [81] % x [82] 5 100 'MOVING AVERAGE FILTER 110 'This program filters 5000 samples with a 101 point moving 120 'average filter, resulting in 4900 samples of filtered data. 130 ' 140 DIM X[4999] 'X[ ] holds the input signal 150 DIM Y[4999] 'Y[ ] holds the output signal 160 ' 170 GOSUB XXXX 'Mythical subroutine to load X[ ] 180 ' 190 FOR I% = 50 TO 4949 'Loop for each point in the output signal 200 Y[I%] = 0 'Zero, so it can be used as an accumulator 210 FOR J% = -50 TO 50 'Calculate the summation 220 Y[I%] = Y[I%] + X(I%+J%] 230 NEXT J% 240 Y[I%] = Y[I%]/101 'Complete the average by dividing 250 NEXT I% 260 ' 270 END TABLE 15-1 As an alternative, the group of points from the input signal can be chosen symmetrically around the output point: This corresponds to changing the summation in Eq. 15-1 from: j ’ 0 to M&1 , to: j ’ &(M&1) /2 to (M&1) /2 . For instance, in an 11 point moving average filter, the index, j, can run from 0 to 11 (one side averaging) or -5 to 5 (symmetrical averaging). Symmetrical averaging requires that M be an odd number. Programming is slightly easier with the points on only one side; however, this produces a relative shift between the input and output signals. You should recognize that the moving average filter is a convolution using a very simple filter kernel. For example, a 5 point filter has the filter kernel: þ 0, 0, 1/5, 1/5, 1/5, 1/5, 1/5, 0, 0 þ . That is, the moving average filter is a convolution of the input signal with a rectangular pulse having an area of one. Table 15-1 shows a program to implement the moving average filter. Noise Reduction vs. Step Response Many scientists and engineers feel guilty about using the moving average filter. Because it is so very simple, the moving average filter is often the first thing tried when faced with a problem. Even if the problem is completely solved, there is still the feeling that something more should be done. This situation is truly ironic. Not only is the moving average filter very good for many applications, it is optimal for a common problem, reducing random white noise while keeping the sharpest step response. Chapter 15- Moving Average Filters 279 Sample number 0 100 200 300 400 500 -1 0 1 2 a. Original signal Sample number 0 100 200 300 400 500 -1 0 1 2 b. 11 point moving average FIGURE 15-1 Example of a moving average filter. In (a), a rectangular pulse is buried in random noise. In (b) and (c), this signal is filtered with 11 and 51 point moving average filters, respectively. As the number of points in the filter increases, the noise becomes lower; however, the edges becoming less sharp. The moving average filter is the optimal solution for this problem, providing the lowest noise possible for a given edge sharpness. Sample number 0 100 200 300 400 500 -1 0 1 2 c. 51 point moving average Amplitude Amplitude Amplitude Figure 15-1 shows an example of how this works. The signal in (a) is a pulse buried in random noise. In (b) and (c), the smoothing action of the moving average filter decreases the amplitude of the random noise (good), but also reduces the sharpness of the edges (bad). Of all the possible linear filters that could be used, the moving average produces the lowest noise for a given edge sharpness. The amount of noise reduction is equal to the square-root of the number of points in the average. For example, a 100 point moving average filter reduces the noise by a factor of 10. To understand why the moving average if the best solution, imagine we want to design a filter with a fixed edge sharpness. For example, let's assume we fix the edge sharpness by specifying that there are eleven points in the rise of the step response. This requires that the filter kernel have eleven points. The optimization question is: how do we choose the eleven values in the filter kernel to minimize the noise on the output signal? Since the noise we are trying to reduce is random, none of the input points is special; each is just as noisy as its neighbor. Therefore, it is useless to give preferential treatment to any one of the input points by assigning it a larger coefficient in the filter kernel. The lowest noise is obtained when all the input samples are treated equally, i.e., the moving average filter. (Later in this chapter we show that other filters are essentially as good. The point is, no filter is better than the simple moving average). 280 The Scientist and Engineer's Guide to Digital Signal Processing EQUATION 15-2 Frequency response of an M point moving average filter. The frequency, f, runs between 0 and 0.5. For f ’ 0, use: H[ f ] ’ 1 H [ f ] ’ sin(Bf M ) M sin(Bf ) Frequency 0 0.1 0.2 0.3 0.4 0.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 3 point 11 point 31 point FIGURE 15-2 Frequency response of the moving average filter. The moving average is a very poor low-pass filter, due to its slow roll-off and poor stopband attenuation. These curves are generated by Eq. 15-2. Amplitude Frequency Response Figure 15-2 shows the frequency response of the moving average filter. It is mathematically described by the Fourier transform of the rectangular pulse, as discussed in Chapter 11: The roll-off is very slow and the stopband attenuation is ghastly. Clearly, the moving average filter cannot separate one band of frequencies from another. Remember, good performance in the time domain results in poor performance in the frequency domain, and vice versa. In short, the moving average is an exceptionally good smoothing filter (the action in the time domain), but an exceptionally bad low-pass filter (the action in the frequency domain). Relatives of the Moving Average Filter In a perfect world, filter designers would only have to deal with time domain or frequency domain encoded information, but never a mixture of the two in the same signal. Unfortunately, there are some applications where both domains are simultaneously important. For instance, television signals fall into this nasty category. Video information is encoded in the time domain, that is, the shape of the waveform corresponds to the patterns of brightness in the image. However, during transmission the video signal is treated according to its frequency composition, such as its total bandwidth, how the carrier waves for sound & color are added, elimination & restoration of the DC component, etc. As another example, electromagnetic interference is best understood in the frequency domain, even if Chapter 15- Moving Average Filters 281 Sample number 0 6 12 18 24 0.0 0.1 0.2 2 pass 4 pass 1 pass a. Filter kernel Sample number 0 6 12 18 24 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1 pass 4 pass 2 pass b. Step response Frequency 0 0.1 0.2 0.3 0.4 0.5 -120 -100 -80 -60 -40 -20 0 20 40 1 pass 2 pass 4 pass d. Frequency response (dB) FIGURE 15-3 Characteristics of multiple-pass moving average filters. Figure (a) shows the filter kernels resulting from passing a seven point moving average filter over the data once, twice and four times. Figure (b) shows the corresponding step responses, while (c) and (d) show the corresponding frequency responses. FFT Integrate 20 Log( ) Amplitude Amplitude Frequency 0 0.1 0.2 0.3 0.4 0.5 0.00 0.25 0.50 0.75 1.00 1.25 1 pass 2 pass 4 pass c. Frequency response Amplitude (dB) Amplitude the signal's information is encoded in the time domain. For instance, the temperature monitor in a scientific experiment might be contaminated with 60 hertz from the power lines, 30 kHz from a switching power supply, or 1320 kHz from a local AM radio station. Relatives of the moving average filter have better frequency domain performance, and can be useful in these mixed domain applications. Multiple-pass moving average filters involve passing the input signal through a moving average filter two or more times. Figure 15-3a shows the overall filter kernel resulting from one, two and four passes. Two passes are equivalent to using a triangular filter kernel (a rectangular filter kernel convolved with itself). After four or more passes, the equivalent filter kernel looks like a Gaussian (recall the Central Limit Theorem). As shown in (b), multiple passes produce an "s" shaped step response, as compared to the straight line of the single pass. The frequency responses in (c) and (d) are given by Eq. 15-2 multiplied by itself for each pass. That is, each time domain convolution results in a multiplication of the frequency spectra. 282 The Scientist and Engineer's Guide to Digital Signal Processing Figure 15-4 shows the frequency response of two other relatives of the moving average filter. When a pure Gaussian is used as a filter kernel, the frequency response is also a Gaussian, as discussed in Chapter 11. The Gaussian is important because it is the impulse response of many natural and manmade systems. For example, a brief pulse of light entering a long fiber optic transmission line will exit as a Gaussian pulse, due to the different paths taken by the photons within the fiber. The Gaussian filter kernel is also used extensively in image processing because it has unique properties that allow fast two-dimensional convolutions (see Chapter 24). The second frequency response in Fig. 15-4 corresponds to using a Blackman window as a filter kernel. (The term window has no meaning here; it is simply part of the accepted name of this curve). The exact shape of the Blackman window is given in Chapter 16 (Eq. 16-2, Fig. 16-2); however, it looks much like a Gaussian. How are these relatives of the moving average filter better than the moving average filter itself? Three ways: First, and most important, these filters have better stopband attenuation than the moving average filter. Second, the filter kernels taper to a smaller amplitude near the ends. Recall that each point in the output signal is a weighted sum of a group of samples from the input. If the filter kernel tapers, samples in the input signal that are farther away are given less weight than those close by. Third, the step responses are smooth curves, rather than the abrupt straight line of the moving average. These last two are usually of limited benefit, although you might find applications where they are genuine advantages. The moving average filter and its relatives are all about the same at reducing random noise while maintaining a sharp step response. The ambiguity lies in how the risetime of the step response is measured. If the risetime is measured from 0% to 100% of the step, the moving average filter is the best you can do, as previously shown. In comparison, measuring the risetime from 10% to 90% makes the Blackman window better than the moving average filter. The point is, this is just theoretical squabbling; consider these filters equal in this parameter. The biggest difference in these filters is execution speed. Using a recursive algorithm (described next), the moving average filter will run like lightning in your computer. In fact, it is the fastest digital filter available. Multiple passes of the moving average will be correspondingly slower, but still very quick. In comparison, the Gaussian and Blackman filters are excruciatingly slow, because they must use convolution. Think a factor of ten times the number of points in the filter kernel (based on multiplication being about 10 times slower than addition). For example, expect a 100 point Gaussian to be 1000 times slower than a moving average using recursion. Recursive Implementation A tremendous advantage of the moving average filter is that it can be implemented with an algorithm that is very fast. To understand this Chapter 15- Moving Average Filters 283 FIGURE 15-4 Frequency response of the Blackman window and Gaussian filter kernels. Both these filters provide better stopband attenuation than the moving average filter. This has no advantage in removing random noise from time domain encoded signals, but it can be useful in mixed domain problems. The disadvantage of these filters is that they must use convolution, a terribly slow algorithm. Frequency 0 0.1 0.2 0.3 0.4 0.5 -140 -120 -100 -80 -60 -40 -20 0 20 Gaussian Blackman Amplitude (dB) y [50] ’ x [47] % x [48] % x [49] % x [50] % x [51] % x [52] % x [53] y [51] ’ x [48] % x [49] % x [50] % x [51] % x [52] % x [53] % x [54] y [51] ’ y [50] % x [54] & x [47] EQUATION 15-3 Recursive implementation of the moving average filter. In this equation, x[ ] is the input signal, y[ ] is the output signal, M is the number of points in the moving average (an odd number). Before this equation can be used, the first point in the signal must be calculated using a standard summation. y [i ] ’ y [i &1] % x [i %p] & x [i &q] q ’ p % 1 where: p ’ (M&1) /2 algorithm, imagine passing an input signal, x [ ], through a seven point moving average filter to form an output signal, y [ ]. Now look at how two adjacent output points, y [50] and y [51], are calculated: These are nearly the same calculation; points x [48] through x [53] must be added for y [50], and again for y [51]. If y [50] has already been calculated, the most efficient way to calculate y [51] is: Once y [51] has been found using y [50], then y [52] can be calculated from sample y [51], and so on. After the first point is calculated in y [ ], all of the other points can be found with only a single addition and subtraction per point. This can be expressed in the equation: Notice that this equation use two sources of data to calculate each point in the output: points from the input and previously calculated points from the output. This is called a recursive equation, meaning that the result of one calculation 284 The Scientist and Engineer's Guide to Digital Signal Processing 100 'MOVING AVERAGE FILTER IMPLEMENTED BY RECURSION 110 'This program filters 5000 samples with a 101 point moving 120 'average filter, resulting in 4900 samples of filtered data. 130 'A double precision accumulator is used to prevent round-off drift. 140 ' 150 DIM X[4999] 'X[ ] holds the input signal 160 DIM Y[4999] 'Y[ ] holds the output signal 170 DEFDBL ACC 'Define the variable ACC to be double precision 180 ' 190 GOSUB XXXX 'Mythical subroutine to load X[ ] 200 ' 210 ACC = 0 'Find Y[50] by averaging points X[0] to X[100] 220 FOR I% = 0 TO 100 230 ACC = ACC + X[I%] 240 NEXT I% 250 Y[[50] = ACC/101 260 ' 'Recursive moving average filter (Eq. 15-3) 270 FOR I% = 51 TO 4949 280 ACC = ACC + X[I%+50] - X[I%-51] 290 Y[I%] = ACC 300 NEXT I% 310 ' 320 END TABLE 15-2 CHAPTER 6 Convolution Convolution is a mathematical way of combining two signals to form a third signal. It is the single most important technique in Digital Signal Processing. Using the strategy of impulse decomposition, systems are described by a signal called the impulse response. Convolution is important because it relates the three signals of interest: the input signal, the output signal, and the impulse response. This chapter presents convolution from two different viewpoints, called the input side algorithm and the output side algorithm. Convolution provides the mathematical framework for DSP; there is nothing more important in this book. The Delta Function and Impulse Response The previous chapter describes how a signal can be decomposed into a group of components called impulses. An impulse is a signal composed of all zeros, except a single nonzero point. In effect, impulse decomposition provides a way to analyze signals one sample at a time. The previous chapter also presented the fundamental concept of DSP: the input signal is decomposed into simple additive components, each of these components is passed through a linear system, and the resulting output components are synthesized (added). The signal resulting from this divide-and-conquer procedure is identical to that obtained by directly passing the original signal through the system. While many different decompositions are possible, two form the backbone of signal processing: impulse decomposition and Fourier decomposition. When impulse decomposition is used, the procedure can be described by a mathematical operation called convolution. In this chapter (and most of the following ones) we will only be dealing with discrete signals. Convolution also applies to continuous signals, but the mathematics is more complicated. We will look at how continious signals are processed in Chapter 13. Figure 6-1 defines two important terms used in DSP. The first is the delta function, symbolized by the Greek letter delta, *[n]. The delta function is a normalized impulse, that is, sample number zero has a value of one, while 108 The Scientist and Engineer's Guide to Digital Signal Processing all other samples have a value of zero. For this reason, the delta function is frequently called the unit impulse. The second term defined in Fig. 6-1 is the impulse response. As the name suggests, the impulse response is the signal that exits a system when a delta function (unit impulse) is the input. If two systems are different in any way, they will have different impulse responses. Just as the input and output signals are often called x[n] and y[n] , the impulse response is usually given the symbol, h[n]. Of course, this can be changed if a more descriptive name is available, for instance, f [n] might be used to identify the impulse response of a filter. Any impulse can be represented as a shifted and scaled delta function. Consider a signal, a[n] , composed of all zeros except sample number 8, which has a value of -3. This is the same as a delta function shifted to the right by 8 samples, and multiplied by -3. In equation form: a[n] ’ &3*[n&8]. Make sure you understand this notation, it is used in nearly all DSP equations. If the input to a system is an impulse, such as &3*[n&8] , what is the system's output? This is where the properties of homogeneity and shift invariance are used. Scaling and shifting the input results in an identical scaling and shifting of the output. If *[n] results in h[n] , it follows that &3*[n&8] results in &3h[n&8] . In words, the output is a version of the impulse response that has been shifted and scaled by the same amount as the delta function on the input. If you know a system's impulse response, you immediately know how it will react to any impulse. Convolution Let's summarize this way of understanding how a system changes an input signal into an output signal. First, the input signal can be decomposed into a set of impulses, each of which can be viewed as a scaled and shifted delta function. Second, the output resulting from each impulse is a scaled and shifted version of the impulse response. Third, the overall output signal can be found by adding these scaled and shifted impulse responses. In other words, if we know a system's impulse response, then we can calculate what the output will be for any possible input signal. This means we know everything about the system. There is nothing more that can be learned about a linear system's characteristics. (However, in later chapters we will show that this information can be represented in different forms). The impulse response goes by a different name in some applications. If the system being considered is a filter, the impulse response is called the filter kernel, the convolution kernel, or simply, the kernel. In image processing, the impulse response is called the point spread function. While these terms are used in slightly different ways, they all mean the same thing, the signal produced by a system when the input is a delta function. Chapter 6- Convolution 109 System -2 -1 0 1 2 3 4 5 6 -1 0 1 2 -2 -1 0 1 2 3 4 5 6 -1 0 1 2 *[n] h[n] Delta Impulse Response Linear Function FIGURE 6-1 Definition of delta function and impulse response. The delta function is a normalized impulse. All of its samples have a value of zero, except for sample number zero, which has a value of one. The Greek letter delta, *[n] , is used to identify the delta function. The impulse response of a linear system, usually denoted by h[n] , is the output of the system when the input is a delta function. x[n] h[n] = y[n] x[n] y[n] Linear System h[n] FIGURE 6-2 How convolution is used in DSP. The output signal from a linear system is equal to the input signal convolved with the system's impulse response. Convolution is denoted by a star when writing equations. Convolution is a formal mathematical operation, just as multiplication, addition, and integration. Addition takes two numbers and produces a third number, while convolution takes two signals and produces a third signal. Convolution is used in the mathematics of many fields, such as probability and statistics. In linear systems, convolution is used to describe the relationship between three signals of interest: the input signal, the impulse response, and the output signal. Figure 6-2 shows the notation when convolution is used with linear systems. An input signal, x[n] , enters a linear system with an impulse response, h[n] , resulting in an output signal, y[n] . In equation form: x[n] t h[n] ’ y[n] . Expressed in words, the input signal convolved with the impulse response is equal to the output signal. Just as addition is represented by the plus, +, and multiplication by the cross, ×, convolution is represented by the star, t. It is unfortunate that most programming languages also use the star to indicate multiplication. A star in a computer program means multiplication, while a star in an equation means convolution. 110 The Scientist and Engineer's Guide to Digital Signal Processing Sample number 0 10 20 30 40 50 60 70 80 90 100 110 -2 -1 0 1 2 3 4 S 0 10 20 30 -0.25 0.00 0.25 0.50 0.75 1.00 1.25 S 0 10 20 30 -0.02 0.00 0.02 0.04 0.06 0.08 a. Low-pass Filter b. High-pass Filter Sample number 0 10 20 30 40 50 60 70 80 -2 -1 0 1 2 3 4 Sample number 0 10 20 30 40 50 60 70 80 90 100 110 -2 -1 0 1 2 3 4 Sample number 0 10 20 30 40 50 60 70 80 -2 -1 0 1 2 3 4 Sample number Sample number Input Signal Impulse Response Output Signal Amplitude Amplitude Amplitude Amplitude Amplitude Amplitude FIGURE 6-3 Examples of low-pass and high-pass filtering using convolution. In this example, the input signal is a few cycles of a sine wave plus a slowly rising ramp. These two components are separated by using properly selected impulse responses. Figure 6-3 shows convolution being used for low-pass and high-pass filtering. The example input signal is the sum of two components: three cycles of a sine wave (representing a high frequency), plus a slowly rising ramp (composed of low frequencies). In (a), the impulse response for the low-pass filter is a smooth arch, resulting in only the slowly changing ramp waveform being passed to the output. Similarly, the high-pass filter, (b), allows only the more rapidly changing sinusoid to pass. Figure 6-4 illustrates two additional examples of how convolution is used to process signals. The inverting attenuator, (a), flips the signal top-for-bottom, and reduces its amplitude. The discrete derivative (also called the first difference), shown in (b), results in an output signal related to the slope of the input signal. Notice the lengths of the signals in Figs. 6-3 and 6-4. The input signals are 81 samples long, while each impulse response is composed of 31 samples. In most DSP applications, the input signal is hundreds, thousands, or even millions of samples in length. The impulse response is usually much shorter, say, a few points to a few hundred points. The mathematics behind convolution doesn't restrict how long these signals are. It does, however, specify the length of the output signal. The length of the output signal is Chapter 6- Convolution 111 S 0 10 20 30 -2.00 -1.00 0.00 1.00 2.00 S 0 10 20 30 -2.00 -1.00 0.00 1.00 2.00 a. Inverting Attenuator b. Discrete Derivative Sample number 0 10 20 30 40 50 60 70 80 90 100 110 -2 -1 0 1 2 3 4 Sample number 0 10 20 30 40 50 60 70 80 90 100 110 -2 -1 0 1 2 3 4 Sample number 0 10 20 30 40 50 60 70 80 -2 -1 0 1 2 3 4 Sample number 0 10 20 30 40 50 60 70 80 -2 -1 0 1 2 3 4 Input Signal Impulse Response Output Signal Sample number Sample number Amplitude Amplitude Amplitude Amplitude Amplitude Amplitude FIGURE 6-4 Examples of signals being processed using convolution. Many signal processing tasks use very simple impulse responses. As shown in these examples, dramatic changes can be achieved with only a few nonzero points. equal to the length of the input signal, plus the length of the impulse response, minus one. For the signals in Figs. 6-3 and 6-4, each output signal is: 81% 31& 1 ’ 111 samples long. The input signal runs from sample 0 to 80, the impulse response from sample 0 to 30, and the output signal from sample 0 to 110. Now we come to the detailed mathematics of convolution. As used in Digital Signal Processing, convolution can be understood in two separate ways. The first looks at convolution from the viewpoint of the input signal. This involves analyzing how each sample in the input signal contributes to many points in the output signal. The second way looks at convolution from the viewpoint of the output signal. This examines how each sample in the output signal has received information from many points in the input signal. Keep in mind that these two perspectives are different ways of thinking about the same mathematical operation. The first viewpoint is important because it provides a conceptual understanding of how convolution pertains to DSP. The second viewpoint describes the mathematics of convolution. This typifies one of the most difficult tasks you will encounter in DSP: making your conceptual understanding fit with the jumble of mathematics used to communicate the ideas. 112 The Scientist and Engineer's Guide to Digital Signal Processing 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 0 1 2 3 4 5 6 7 8 -3 -2 -1 0 1 2 3 0 1 2 3 -3 -2 -1 0 1 2 3 x[n] h[n] y[n] FIGURE 6-5 Example convolution problem. A nine point input signal, convolved with a four point impulse response, results in a twelve point output signal. Each point in the input signal contributes a scaled and shifted impulse response to the output signal. These nine scaled and shifted impulse responses are shown in Fig. 6-6. Now examine sample x[8] , the last point in the input signal. This sample is at index number eight, and has a value of -0.5. As shown in the lower-right graph of Fig. 6-6, x[8] results in an impulse response that has been shifted to the right by eight points and multiplied by -0.5. Place holding zeros have been added at points 0-7. Lastly, examine the effect of points x[0] and x[7] . Both these samples have a value of zero, and therefore produce output components consisting of all zeros. The Input Side Algorithm Figure 6-5 shows a simple convolution problem: a 9 point input signal, x[n] , is passed through a system with a 4 point impulse response, h[n] , resulting in a 9% 4& 1 ’ 12 point output signal, y[n] . In mathematical terms, x[n] is convolved with h[n] to produce y[n] . This first viewpoint of convolution is based on the fundamental concept of DSP: decompose the input, pass the components through the system, and synthesize the output. In this example, each of the nine samples in the input signal will contribute a scaled and shifted version of the impulse response to the output signal. These nine signals are shown in Fig. 6-6. Adding these nine signals produces the output signal, y[n] . Let's look at several of these nine signals in detail. We will start with sample number four in the input signal, i.e., x[4] . This sample is at index number four, and has a value of 1.4. When the signal is decomposed, this turns into an impulse represented as: 1.4*[n&4]. After passing through the system, the resulting output component will be: 1.4 h[n&4]. This signal is shown in the center box of the nine signals in Fig. 6-6. Notice that this is the impulse response, h[n] , multiplied by 1.4, and shifted four samples to the right. Zeros have been added at samples 0-3 and at samples 8-11 to serve as place holders. To make this more clear, Fig. 6-6 uses squares to represent the data points that come from the shifted and scaled impulse response, and diamonds for the added zeros. Chapter 6- Convolution 113 FIGURE 6-6 Output signal components for the convolution in Fig. 6-5. In these signals, each point that results from a scaled and shifted impulse response is represented by a square marker. The remaining data points, represented by diamonds, are zeros that have been added as place holders. 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 contribution from x[ ] h[n- ] 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 contribution from x[ ] h[n- ] 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 contribution from x[ ] h[n- ] 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 contribution from x[ ] h[n- ] 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 contribution from x[ ] h[n- ] 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 contribution from x[ ] h[n- ] 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 contribution from x[ ] h[n- ] 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 contribution from x[ ] h[n- ] 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 contribution from x[ ] h[n- ] 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 In this example, x[n] is a nine point signal and h[n] is a four point signal. In our next example, shown in Fig. 6-7, we will reverse the situation by making x[n] a four point signal, and h[n] a nine point signal. The same two waveforms are used, they are just swapped. As shown by the output signal components, the four samples in x[n] result in four shifted and scaled versions of the nine point impulse response. Just as before, leading and trailing zeros are added as place holders. But wait just one moment! The output signal in Fig. 6-7 is identical to the output signal in Fig. 6-5. This isn't a mistake, but an important property. Convolution is commutative: a[n]tb[n] ’ b[n]ta[n] . The mathematics does not care which is the input signal and which is the impulse response, only that two signals are convolved with each other. Although the mathematics may allow it, exchanging the two signals has no physical meaning in system theory. The input signal and impulse response are two totally different things and exchanging them doesn't make sense. What the commutative property provides is a mathematical tool for manipulating equations to achieve various results. 114 The Scientist and Engineer's Guide to Digital Signal Processing TABLE 6-1 100 'CONVOLUTION USING THE INPUT SIDE ALGORITHM 110 ' 120 DIM X[80] 'The input signal, 81 points 130 DIM H[30] 'The impulse response, 31 points 140 DIM Y[110] 'The output signal, 111 points 150 ' 160 GOSUB XXXX 'Mythical subroutine to load X[ ] and H[ ] 170 ' 180 FOR I% = 0 TO 110 'Zero the output array 190 Y(I%) = 0 200 NEXT I% 210 ' 220 FOR I% = 0 TO 80 'Loop for each point in X[ ] 230 FOR J% = 0 TO 30 'Loop for each point in H[ ] 240 Y[I%+J%] = Y[I%+J%] + X[I%]tH[J%] 250 NEXT J% 260 NEXT I% '(remember, t is multiplication in programs!) 270 ' 280 GOSUB XXXX 'Mythical subroutine to store Y[ ] 290 ' 300 END A program for calculating convolutions using the input side algorithm is shown in Table 6-1. Remember, the programs in this book are meant to convey algorithms in the simplest form, even at the expense of good programming style. For instance, all of the input and output is handled in mythical subroutines (lines 160 and 280), meaning we do not define how these operations are conducted. Do not skip over these programs; they are a key part of the material and you need to understand them in detail. The program convolves an 81 point input signal, held in array X[ ], with a 31 point impulse response, held in array H[ ], resulting in a 111 point output signal, held in array Y[ ]. These are the same lengths shown in Figs. 6-3 and 6-4. Notice that the names of these arrays use upper case letters. This is a violation of the naming conventions previously discussed, because upper case letters are reserved for frequency domain signals. Unfortunately, the simple BASIC used in this book does not allow lower case variable names. Also notice that line 240 uses a star for multiplication. Remember, a star in a program means multiplication, while a star in an equation means convolution. A star in text (such as documentation or program comments) can mean either. The mythical subroutine in line 160 places the input signal into X[ ] and the impulse response into H[ ]. Lines 180-200 set all of the values in Y[ ] to zero. This is necessary because Y[ ] is used as an accumulator to sum the output components as they are calculated. Lines 220 to 260 are the heart of the program. The FOR statement in line 220 controls a loop that steps through each point in the input signal, X[ ]. For each sample in the input signal, an inner loop (lines 230-250) calculates a scaled and shifted version of the impulse response, and adds it to the array accumulating the output signal, Y[ ]. This nested loop structure (one loop within another loop) is a key characteristic of convolution programs; become familiar with it. Chapter 6- Convolution 115 FIGURE 6-7 A second example of convolution. The waveforms for the input signal and impulse response are exchanged from the example of Fig. 6-5. Since convolution is commutative, the output signals for the two examples are identical. 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 0 1 2 3 4 5 6 7 8 -3 -2 -1 0 1 2 3 0 1 2 3 -3 -2 -1 0 1 2 3 x[n] h[n] y[n] 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 contribution from x[ ] h[n- ] 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 contribution from x[ ] h[n- ] 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 contribution from x[ ] h[n- ] 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 contribution from x[ ] h[n- ] 0 0 1 1 2 2 3 3 Output signal components Keeping the indexing straight in line 240 can drive you crazy! Let's say we are halfway through the execution of this program, so that we have just begun action on sample X[40], i.e., I% = 40. The inner loop runs through each point in the impulse response doing three things. First, the impulse response is scaled by multiplying it by the value of the input sample. If this were the only action taken by the inner loop, line 240 could be written, Y[J%] = X[40]tH[J%]. Second, the scaled impulse is shifted 40 samples to the right by adding this number to the index used in the output signal. This second action would change line 240 to: Y[40+J%] = X[40]tH[J%]. Third, Y[ ] must accumulate (synthesize) all the signals resulting from each sample in the input signal. Therefore, the new information must be added to the information that is already in the array. This results in the final command: Y[40+J%] = Y[40+J%] + X[40]tH[J%]. Study this carefully; it is very confusing, but very important. 116 The Scientist and Engineer's Guide to Digital Signal Processing The Output Side Algorithm The first viewpoint of convolution analyzes how each sample in the input signal affects many samples in the output signal. In this second viewpoint, we reverse this by looking at individual samples in the output signal, and finding the contributing points from the input. This is important from both mathematical and practical standpoints. Suppose that we are given some input signal and impulse response, and want to find the convolution of the two. The most straightforward method would be to write a program that loops through the output signal, calculating one sample on each loop cycle. Likewise, equations are written in the form: y[n] ’ some combination of other variables. That is, sample n in the output signal is equal to some combination of the many values in the input signal and impulse response. This requires a knowledge of how each sample in the output signal can be calculated independently of all other samples in the output signal. The output side algorithm provides this information. Let's look at an example of how a single point in the output signal is influenced by several points from the input. The example point we will use is y[6] in Fig. 6-5. This point is equal to the sum of all the sixth points in the nine output components, shown in Fig. 6-6. Now, look closely at these nine output components and identify which can affect y[6] . That is, find which of these nine signals contains a nonzero sample at the sixth position. Five of the output components only have added zeros (the diamond markers) at the sixth sample, and can therefore be ignored. Only four of the output components are capable of having a nonzero value in the sixth position. These are the output components generated from the input samples: x[3], x[4], x[5], and x[6] . By adding the sixth sample from each of these output components, y[6] is determined as: y[6] ’ x[3]h[3] % x[4]h[2] % x[5]h[1] % x[6]h[0] . That is, four samples from the input signal are multiplied by the four samples in the impulse response, and the products added. Figure 6-8 illustrates the output side algorithm as a convolution machine, a flow diagram of how convolution occurs. Think of the input signal, x[n] , and the output signal, y[n] , as fixed on the page. The convolution machine, everything inside the dashed box, is free to move left and right as needed. The convolution machine is positioned so that its output is aligned with the output sample being calculated. Four samples from the input signal fall into the inputs of the convolution machine. These values are multiplied by the indicated samples in the impulse response, and the products are added. This produces the value for the output signal, which drops into its proper place. For example, y[6] i s s h own b e i n g c a l c u l a t e d f r om t h e f o u r i n p u t s amp l e s : x[3], x[4], x[5], and x[6] . To calculate y[7] , the convolution machine moves one sample to the right. This results in another four samples entering the machine, x[4] through x[7] , and the value for y[7] dropping into the proper place. This process is repeated for all points in the output signal needing to be calculated. Chapter 6- Convolution 117 0 1 2 3 4 5 6 7 8 -3 -2 -1 0 1 2 3 -3 -2 -1 0 3.0 2.0 1.0 0.0 1.0 2.0 3.0 x[n] y[n] h[n] 0 -1 -2 -3 2 3 1 (flipped) FIGURE 6-8 The convolution machine. This is a flow diagram showing how each sample in the output signal is influenced by the input signal and impulse response. See the text for details. 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 The arrangement of the impulse response inside the convolution machine is very important. The impulse response is flipped left-for-right. This places sample number zero on the right, and increasingly positive sample numbers running to the left. Compare this to the normal impulse response in Fig. 6-5 to understand the geometry of this flip. Why is this flip needed? It simply falls out of the mathematics. The impulse response describes how each point in the input signal affects the output signal. This results in each point in the output signal being affected by points in the input signal weighted by a flipped impulse response. 118 The Scientist and Engineer's Guide to Digital Signal Processing FIGURE 6-9 The convolution machine in action. Figures (a) through (d) show the convolution machine set to calculate four different output signal samples, y[0], y[3], y[8], and y[11]. 0 1 2 3 4 5 6 7 8 -3 -2 -1 0 1 2 3 -3 -2 -1 0 3.0 2.0 1.0 0.0 1.0 2.0 3.0 x[n] y[n] h[n] 0 -1 -2 -3 2 3 1 (flipped) a. Set to calculate y[0] 0 1 2 3 4 5 6 7 8 -3 -2 -1 0 1 2 3 -3 -2 -1 0 3.0 2.0 1.0 0.0 1.0 2.0 3.0 x[n] y[n] h[n] 0 -1 -2 -3 2 3 1 (flipped) b. Set to calculate y[3] 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 Figure 6-9 shows the convolution machine being used to calculate several samples in the output signal. This diagram also illustrates a real nuisance in convolution. In (a), the convolution machine is located fully to the left with its output aimed at y[0] . In this position, it is trying to receive input from samples: x[&3], x[&2], x[&1], and x[0] . The problem is, three of these samples: x[&3], x[&2], and x[&1] , do not exist! This same dilemma arises in (d), where the convolution machine tries to accept samples to the right of the defined input signal, points x[9], x[10], and x[11] . One way to handle this problem is by inventing the nonexistent samples. This involves adding samples to the ends of the input signal, with each of the added samples having a value of zero. This is called padding the signal with zeros. Instead of trying to access a nonexistent value, the convolution machine receives a sample that has a value of zero. Since this zero is eliminated during the multiplication, the result is mathematically the same as ignoring the nonexistent inputs. Chapter 6- Convolution 119 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 0 1 2 3 4 5 6 7 8 9 10 11 -3 -2 -1 0 1 2 3 0 1 2 3 4 5 6 7 8 -3 -2 -1 0 1 2 3 -3 -2 -1 0 3.0 2.0 1.0 0.0 1.0 2.0 3.0 x[n] y[n] h[n] 0 -1 -2 -3 2 3 1 (flipped) c. Set to calculate y[8] 0 1 2 3 4 5 6 7 8 -3 -2 -1 0 1 2 3 -3 -2 -1 0 3.0 2.0 1.0 0.0 1.0 2.0 3.0 x[n] y[n] h[n] 0 -1 -2 -3 2 3 1 (flipped) d. Set to calculate y[11] Figure 6-9 (continued) The important part is that the far left and far right samples in the output signal are based on incomplete information. In DSP jargon, the impulse response is not fully immersed in the input signal. If the impulse response is M points in length, the first and last M&1 samples in the output signal are based on less information than the samples between. This is analogous to an electronic circuit requiring a certain amount of time to stabilize after the power is applied. The difference is that this transient is easy to ignore in electronics, but very prominent in DSP. Figure 6-10 shows an example of the trouble these end effects can cause. The input signal is a sine wave plus a DC component. The desire is to remove the DC part of the signal, while leaving the sine wave intact. This calls for a highpass filter, such as the impulse response shown in the figure. The problem is, the first and last 30 points are a mess! The shape of these end regions can be understood by imagining the input signal padded with 30 zeros on the left side, samples x[&1] through x[&30] , and 30 zeros on the right, samples x[81] through x[110] . The output signal can then be viewed as a filtered version of this longer waveform. These "end effect" problems are widespread in 120 The Scientist and Engineer's Guide to Digital Signal Processing EQUATION 6-1 The convolution summation. This is the formal definition of convolution, written in the shorthand: y [n] ’ x [n] t h[n]. In this equation, h[n] is an M point signal with indexes running from 0 to M-1. y [i ] ’ jM&1 j ’0 h[ j ] x [i&j ] DSP. As a general rule, expect that the beginning and ending samples in processed signals will be quite useless. Now the math. Using the convolution machine as a guideline, we can write the standard equation for convolution. If x[n] is an N point signal running from 0 to N-1, and h[n] is an M point signal running from 0 to M-1, the convolution of the two: y[n] ’ x[n] t h[n], is an N+M-1 point signal running from 0 to N+M-2, given by: This equation is called the convolution sum. It allows each point in the output signal to be calculated independently of all other points in the output signal. The index, i, determines which sample in the output signal is being calculated, and therefore corresponds to the left-right position of the convolution machine. In computer programs performing convolution, a loop makes this index run through each sample in the output signal. To calculate one of the output samples, the index, j, is used inside of the convolution machine. As j runs through 0 to M-1, each sample in the impulse response, h[ j], is multiplied by the proper sample from the input signal, x[i& j ]. All these products are added to produce the output sample being calculated. Study Eq. 6-1 until you fully understand how it is implemented by the convolution machine. Much of DSP is based on this equation. (Don't be confused by the n in y[n] ’ x[n] t h[n]. This is merely a place holder to indicate that some variable is the index into the array. Sometimes the equations are written: y[ ] ’ x[ ] t h[ ], just to avoid having to bring in a meaningless symbol). Table 6-2 shows a program for performing convolutions using the output side algorithm, a direct use of Eq. 6-1. This program produces the same output signal as the program for the input side algorithm, shown previously in Table 6-1. Notice the main difference between these two programs: the input side algorithm loops through each sample in the input signal (line 220 of Table 6- 1), while the output side algorithm loops through each sample in the output signal (line 180 of Table 6-2). Here is a detailed operation of this program. The FOR-NEXT loop in lines 180 to 250 steps through each sample in the output signal, using I% as the index. For each of these values, an inner loop, composed of lines 200 to 230, calculates the value of the output sample, Y[I%]. The value of Y[I%] is set to zero in line 190, allowing it to accumulate the products inside of the convolution machine. The FOR-NEXT loop in lines 200 to 240 provide a direct implementation of Eq. 6-1. The index, J%, steps through each Chapter 6- Convolution 121 sample in the impulse response. Line 230 provides the multiplication of each sample in the impulse response, H[J%], with the appropriate sample from the input signal, X[I%-J%], and adds the result to the accumulator. In line 230, the sample taken from the input signal is: X[I%-J%]. Lines 210 and 220 prevent this from being outside the defined array, X[0] to X[80]. In other words, this program handles undefined samples in the input signal by ignoring them. Another alternative would be to define the input signal's array from X[-30] to X[110], allowing 30 zeros to be padded on each side of the true data. As a third alternative, the FOR-NEXT loop in line 180 could be changed to run from 30 to 80, rather than 0 to 110. That is, the program would only calculate the samples in the output signal where the impulse response is fully immersed in the input signal. The important thing is that you must use one of these three techniques. If you don't, the program will crash when it tries to read the out-of-bounds data. S 0 10 20 30 -0.5 0.0 0.5 1.0 1.5 Sample number 0 10 20 30 40 50 60 70 80 -4 -2 0 2 4 Sample number 0 10 20 30 40 50 60 70 80 90 100 110 -4 -2 0 2 4 Input signal Impulse response Output signal unusable usable unusable Sample number Amplitude Amplitude Amplitude FIGURE 6-10 End effects in convolution. When an input signal is convolved with an M point impulse response, the first and last M-1 points in the output signal may not be usable. In this example, the impulse response is a high-pass filter used to remove the DC component from the input signal. 100 'CONVOLUTION USING THE OUTPUT SIDE ALGORITHM 110 ' 120 DIM X[80] 'The input signal, 81 points 130 DIM H[30] 'The impulse response, 31 points 140 DIM Y[110] 'The output signal, 111 points 150 ' 160 GOSUB XXXX 'Mythical subroutine to load X[ ] and H[ ] 170 ' 180 FOR I% = 0 TO 110 'Loop for each point in Y[ ] 190 Y[I%] = 0 'Zero the sample in the output array 200 FOR J% = 0 TO 30 'Loop for each point in H[ ] 210 IF (I%-J% < 0) THEN GOTO 240 220 IF (I%-J% > 80) THEN GOTO 240 230 Y(I%) = Y(I%) + H(J%) t X(I%-J%) 240 NEXT J% 250 NEXT I% 260 ' 270 GOSUB XXXX 'Mythical subroutine to store Y[ ] 280 ' 290 END TABLE 6-2 122 The Scientist and Engineer's Guide to Digital Signal Processing The Sum of Weighted Inputs The characteristics of a linear system are completely described by its impulse response. This is the basis of the input side algorithm: each point in the input signal contributes a scaled and shifted version of the impulse response to the output signal. The mathematical consequences of this lead to the output side algorithm: each point in the output signal receives a contribution from many points in the input signal, multiplied by a flipped impulse response. While this is all true, it doesn't provide the full story on why convolution is important in signal processing. Look back at the convolution machine in Fig. 6-8, and ignore that the signal inside the dotted box is an impulse response. Think of it as a set of weighing coefficients that happen to be embedded in the flow diagram. In this view, each sample in the output signal is equal to a sum of weighted inputs. Each sample in the output is influenced by a region of samples in the input signal, as determined by what the weighing coefficients are chosen to be. For example, imagine there are ten weighing coefficients, each with a value of onetenth. This makes each sample in the output signal the average of ten samples from the input. Taking this further, the weighing coefficients do not need to be restricted to the left side of the output sample being calculated. For instance, Fig. 6-8 shows y[6] being calculated from: x[3], x[4], x[5], and x[6] . Viewing the convolution machine as a sum of weighted inputs, the weighing coefficients could be chosen symmetrically around the output sample. For example, y[6] might receive contributions from: x[4], x[5], x[6], x[7], and x[8] . Using the same indexing notation as in Fig. 6-8, the weighing coefficients for these five inputs would be held in: h[2], h[1], h[0], h[&1], and h[&2] . In other words, the impulse response that corresponds to our selection of symmetrical weighing coefficients requires the use of negative indexes. We will return to this in the next chapter. Mathematically, there is only one concept here: convolution as defined by Eq. 6-1. However, science and engineering problems approach this single concept from two distinct directions. Sometimes you will want to think of a system in terms of what its impulse response looks like. Other times you will understand the system as a set of weighing coefficients. You need to become familiar with both views, and how to toggle between them. Digital Signal Processors Digital Signal Processing is carried out by mathematical operations. In comparison, word processing and similar programs merely rearrange stored data. This means that computers designed for business and other general applications are not optimized for algorithms such as digital filtering and Fourier analysis. Digital Signal Processors are microprocessors specifically designed to handle Digital Signal Processing tasks. These devices have seen tremendous growth in the last decade, finding use in everything from cellular telephones to advanced scientific instruments. In fact, hardware engineers use "DSP" to mean Digital Signal Processor, just as algorithm developers use "DSP" to mean Digital Signal Processing. This chapter looks at how DSPs are different from other types of microprocessors, how to decide if a DSP is right for your application, and how to get started in this exciting new field. In the next chapter we will take a more detailed look at one of these sophisticated products: the Analog Devices SHARC® family. How DSPs are Different from Other Microprocessors In the 1960s it was predicted that artificial intelligence would revolutionize the way humans interact with computers and other machines. It was believed that by the end of the century we would have robots cleaning our houses, computers driving our cars, and voice interfaces controlling the storage and retrieval of information. This hasn't happened; these abstract tasks are far more complicated than expected, and very difficult to carry out with the step-by-step logic provided by digital computers. However, the last forty years have shown that computers are extremely capable in two broad areas, (1) data manipulation, such as word processing and database management, and (2) mathematical calculation, used in science, engineering, and Digital Signal Processing. All microprocessors can perform both tasks; however, it is difficult (expensive) to make a device that is optimized for both. There are technical tradeoffs in the hardware design, such as the size of the instruction set and how interrupts are handled. Even 504 The Scientist and Engineer's Guide to Digital Signal Processing Data Manipulation Math Calculation Word processing, database management, spread sheets, operating sytems, etc. Digital Signal Processing, motion control, scientific and engineering simulations, etc. data movement (A º B) value testing (If A=B then ...) addition (A+B=C ) multiplication (A×B=C ) Typical Applications Main Operations FIGURE 28-1 Data manipulation versus mathematical calculation. Digital computers are useful for two general tasks: data manipulation and mathematical calculation. Data manipulation is based on moving data and testing inequalities, while mathematical calculation uses multiplication and addition. more important, there are marketing issues involved: development and manufacturing cost, competitive position, product lifetime, and so on. As a broad generalization, these factors have made traditional microprocessors, such as the Pentium®, primarily directed at data manipulation. Similarly, DSPs are designed to perform the mathematical calculations needed in Digital Signal Processing. Figure 28-1 lists the most important differences between these two categories. Data manipulation involves storing and sorting information. For instance, consider a word processing program. The basic task is to store the information (typed in by the operator), organize the information (cut and paste, spell checking, page layout, etc.), and then retrieve the information (such as saving the document on a floppy disk or printing it with a laser printer). These tasks are accomplished by moving data from one location to another, and testing for inequalities (A=B, AB THEN ...). Second, if the two entries are not in alphabetical order, switch them so that they are (AWB). When this two step process is repeated many times on all adjacent pairs, the list will eventually become alphabetized. As another example, consider how a document is printed from a word processor. The computer continually tests the input device (mouse or keyboard) for the binary code that indicates "print the document." When this code is detected, the program moves the data from the computer's memory to the printer. Here we have the same two basic operations: moving data and inequality testing. While mathematics is occasionally used in this type of Chapter 28- Digital Signal Processors 505 y[n] ’ a0 x[n] % a1 x[n&1] % a2 x[n&2] % a3 x[n&3] % a4 x[n&4] % þ ×a0 ×a1 ×a2 ×a3 ×a4 ×a5 ×a6 ×a7 Input Signal, x[ ] Output signal, y[ ] x[n] x[n-1] x[n-2] x[n-3] y[n] FIGURE 28-2 FIR digital filter. In FIR filtering, each sample in the output signal, y[n], is found by multiplying samples from the input signal, x[n], x[n-1], x[n-2], ..., by the filter kernel coefficients, a0, a1, a2, a3 ..., and summing the products. application, it is infrequent and does not significantly affect the overall execution speed. In comparison, the execution speed of most DSP algorithms is limited almost completely by the number of multiplications and additions required. For example, Fig. 28-2 shows the implementation of an FIR digital filter, the most common DSP technique. Using the standard notation, the input signal is referred to by x[ ], while the output signal is denoted by y[ ]. Our task is to calculate the sample at location n in the output signal, i.e., y[n] . An FIR filter performs this calculation by multiplying appropriate samples from the input signal by a group of coefficients, denoted by: a , and then adding 0, a1, a2, a3,þ the products. In equation form, y[n] is found by: This is simply saying that the input signal has been convolved with a filter kernel (i.e., an impulse response) consisting of: a . Depending on 0, a1, a2, a3,þ the application, there may only be a few coefficients in the filter kernel, or many thousands. While there is some data transfer and inequality evaluation in this algorithm, such as to keep track of the intermediate results and control the loops, the math operations dominate the execution time. 506 The Scientist and Engineer's Guide to Digital Signal Processing In addition to preforming mathematical calculations very rapidly, DSPs must also have a predictable execution time. Suppose you launch your desktop computer on some task, say, converting a word-processing document from one form to another. It doesn't matter if the processing takes ten milliseconds or ten seconds; you simply wait for the action to be completed before you give the computer its next assignment. In comparison, most DSPs are used in applications where the processing is continuous, not having a defined start or end. For instance, consider an engineer designing a DSP system for an audio signal, such as a hearing aid. If the digital signal is being received at 20,000 samples per second, the DSP must be able to maintain a sustained throughput of 20,000 samples per second. However, there are important reasons not to make it any faster than necessary. As the speed increases, so does the cost, the power consumption, the design difficulty, and so on. This makes an accurate knowledge of the execution time critical for selecting the proper device, as well as the algorithms that can be applied. Circular Buffering Digital Signal Processors are designed to quickly carry out FIR filters and similar techniques. To understand the hardware, we must first understand the algorithms. In this section we will make a detailed list of the steps needed to implement an FIR filter. In the next section we will see how DSPs are designed to perform these steps as efficiently as possible. To start, we need to distinguish between off-line processing and real-time processing. In off-line processing, the entire input signal resides in the computer at the same time. For example, a geophysicist might use a seismometer to record the ground movement during an earthquake. After the shaking is over, the information may be read into a computer and analyzed in some way. Another example of off-line processing is medical imaging, such as computed tomography and MRI. The data set is acquired while the patient is inside the machine, but the image reconstruction may be delayed until a later time. The key point is that all of the information is simultaneously available to the processing program. This is common in scientific research and engineering, but not in consumer products. Off-line processing is the realm of personal computers and mainframes. In real-time processing, the output signal is produced at the same time that the input signal is being acquired. For example, this is needed in telephone communication, hearing aids, and radar. These applications must have the information immediately available, although it can be delayed by a short amount. For instance, a 10 millisecond delay in a telephone call cannot be detected by the speaker or listener. Likewise, it makes no difference if a radar signal is delayed by a few seconds before being displayed to the operator. Real-time applications input a sample, perform the algorithm, and output a sample, over-and-over. Alternatively, they may input a group Chapter 28- Digital Signal Processors 507 x[n-3] x[n-2] x[n-1] x[n] x[n-6] x[n-5] x[n-4] x[n-7] 20040 20041 20042 20043 20044 20045 20046 20047 20048 20049 -0.225767 -0.269847 -0.228918 -0.113940 -0.048679 -0.222977 -0.371370 -0.462791 ADDRESS VALUE newest sample oldest sample MEMORY STORED x[n-4] x[n-3] x[n-2] x[n-1] x[n-7] x[n-6] x[n-5] x[n] 20040 20041 20042 20043 20044 20045 20046 20047 20048 20049 -0.225767 -0.269847 -0.228918 -0.113940 -0.062222 -0.222977 -0.371370 -0.462791 ADDRESS VALUE newest sample oldest sample MEMORY STORED a. Circular buffer at some instant b. Circular buffer after next sample FIGURE 28-3 Circular buffer operation. Circular buffers are used to store the most recent values of a continually updated signal. This illustration shows how an eight sample circular buffer might appear at some instant in time (a), and how it would appear one sample later (b). of samples, perform the algorithm, and output a group of samples. This is the world of Digital Signal Processors. Now look back at Fig. 28-2 and imagine that this is an FIR filter being implemented in real-time. To calculate the output sample, we must have access to a certain number of the most recent samples from the input. For example, suppose we use eight coefficients in this filter, a . This means we 0, a1, þ a7 must know the value of the eight most recent samples from the input signal, x[n], x[n&1], þ x[n&7] . These eight samples must be stored in memory and continually updated as new samples are acquired. What is the best way to manage these stored samples? The answer is circular buffering. Figure 28-3 illustrates an eight sample circular buffer. We have placed this circular buffer in eight consecutive memory locations, 20041 to 20048. Figure (a) shows how the eight samples from the input might be stored at one particular instant in time, while (b) shows the changes after the next sample is acquired. The idea of circular buffering is that the end of this linear array is connected to its beginning; memory location 20041 is viewed as being next to 20048, just as 20044 is next to 20045. You keep track of the array by a pointer (a variable whose value is an address) that indicates where the most recent sample resides. For instance, in (a) the pointer contains the address 20044, while in (b) it contains 20045. When a new sample is acquired, it replaces the oldest sample in the array, and the pointer is moved one address ahead. Circular buffers are efficient because only one value needs to be changed when a new sample is acquired. Four parameters are needed to manage a circular buffer. First, there must be a pointer that indicates the start of the circular buffer in memory (in this example, 20041). Second, there must be a pointer indicating the end of the 508 The Scientist and Engineer's Guide to Digital Signal Processing 1. Obtain a sample with the ADC; generate an interrupt 2. Detect and manage the interrupt 3. Move the sample into the input signal's circular buffer 4. Update the pointer for the input signal's circular buffer 5. Zero the accumulator 6. Control the loop through each of the coefficients 7. Fetch the coefficient from the coefficient's circular buffer 8. Update the pointer for the coefficient's circular buffer 9. Fetch the sample from the input signal's circular buffer 10. Update the pointer for the input signal's circular buffer 11. Multiply the coefficient by the sample 12. Add the product to the accumulator 13. Move the output sample (accumulator) to a holding buffer 14. Move the output sample from the holding buffer to the DAC TABLE 28-1 FIR filter steps. array (e.g., 20048), or a variable that holds its length (e.g., 8). Third, the step size of the memory addressing must be specified. In Fig. 28-3 the step size is one, for example: address 20043 contains one sample, address 20044 contains the next sample, and so on. This is frequently not the case. For instance, the addressing may refer to bytes, and each sample may require two or four bytes to hold its value. In these cases, the step size would need to be two or four, respectively. These three values define the size and configuration of the circular buffer, and will not change during the program operation. The fourth value, the pointer to the most recent sample, must be modified as each new sample is acquired. In other words, there must be program logic that controls how this fourth value is updated based on the value of the first three values. While this logic is quite simple, it must be very fast. This is the whole point of this discussion; DSPs should be optimized at managing circular buffers to achieve the highest possible execution speed. As an aside, circular buffering is also useful in off-line processing. Consider a program where both the input and the output signals are completely contained in memory. Circular buffering isn't needed for a convolution calculation, because every sample can be immediately accessed. However, many algorithms are implemented in stages, with an intermediate signal being created between each stage. For instance, a recursive filter carried out as a series of biquads operates in this way. The brute force method is to store the entire length of each intermediate signal in memory. Circular buffering provides another option: store only those intermediate samples needed for the calculation at hand. This reduces the required amount of memory, at the expense of a more complicated algorithm. The important idea is that circular buffers are useful for off-line processing, but critical for real-time applications. Now we can look at the steps needed to implement an FIR filter using circular buffers for both the input signal and the coefficients. This list may seem trivial and overexamined- it's not! The efficient handling of these individual tasks is what separates a DSP from a traditional microprocessor. For each new sample, all the following steps need to be taken: Chapter 28- Digital Signal Processors 509 The goal is to make these steps execute quickly. Since steps 6-12 will be repeated many times (once for each coefficient in the filter), special attention must be given to these operations. Traditional microprocessors must generally carry out these 14 steps in serial (one after another), while DSPs are designed to perform them in parallel. In some cases, all of the operations within the loop (steps 6-12) can be completed in a single clock cycle. Let's look at the internal architecture that allows this magnificent performance. Architecture of the Digital Signal Processor One of the biggest bottlenecks in executing DSP algorithms is transferring information to and from memory. This includes data, such as samples from the input signal and the filter coefficients, as well as program instructions, the binary codes that go into the program sequencer. For example, suppose we need to multiply two numbers that reside somewhere in memory. To do this, we must fetch three binary values from memory, the numbers to be multiplied, plus the program instruction describing what to do. Figure 28-4a shows how this seemingly simple task is done in a traditional microprocessor. This is often called a Von Neumann architecture, after the brilliant American mathematician John Von Neumann (1903-1957). Von Neumann guided the mathematics of many important discoveries of the early twentieth century. His many achievements include: developing the concept of a stored program computer, formalizing the mathematics of quantum mechanics, and work on the atomic bomb. If it was new and exciting, Von Neumann was there! As shown in (a), a Von Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU). Multiplying two numbers requires at least three clock cycles, one to transfer each of the three numbers over the bus from the memory to the CPU. We don't count the time to transfer the result back to memory, because we assume that it remains in the CPU for additional manipulation (such as the sum of products in an FIR filter). The Von Neumann design is quite satisfactory when you are content to execute all of the required tasks in serial. In fact, most computers today are of the Von Neumann design. We only need other architectures when very fast processing is required, and we are willing to pay the price of increased complexity. This leads us to the Harvard architecture, shown in (b). This is named for the work done at Harvard University in the 1940s under the leadership of Howard Aiken (1900-1973). As shown in this illustration, Aiken insisted on separate memories for data and program instructions, with separate buses for each. Since the buses operate independently, program instructions and data can be fetched at the same time, improving the speed over the single bus design. Most present day DSPs use this dual bus architecture. Figure (c) illustrates the next level of sophistication, the Super Harvard Architecture. This term was coined by Analog Devices to describe the 510 The Scientist and Engineer's Guide to Digital Signal Processing internal operation of their ADSP-2106x and new ADSP-211xx families of Digital Signal Processors. These are called SHARC® DSPs, a contraction of the longer term, Super Harvard ARChitecture. The idea is to build upon the Harvard architecture by adding features to improve the throughput. While the SHARC DSPs are optimized in dozens of ways, two areas are important enough to be included in Fig. 28-4c: an instruction cache, and an I/O controller. First, let's look at how the instruction cache improves the performance of the Harvard architecture. A handicap of the basic Harvard design is that the data memory bus is busier than the program memory bus. When two numbers are multiplied, two binary values (the numbers) must be passed over the data memory bus, while only one binary value (the program instruction) is passed over the program memory bus. To improve upon this situation, we start by relocating part of the "data" to program memory. For instance, we might place the filter coefficients in program memory, while keeping the input signal in data memory. (This relocated data is called "secondary data" in the illustration). At first glance, this doesn't seem to help the situation; now we must transfer one value over the data memory bus (the input signal sample), but two values over the program memory bus (the program instruction and the coefficient). In fact, if we were executing random instructions, this situation would be no better at all. However, DSP algorithms generally spend most of their execution time in loops, such as instructions 6-12 of Table 28-1. This means that the same set of program instructions will continually pass from program memory to the CPU. The Super Harvard architecture takes advantage of this situation by including an instruction cache in the CPU. This is a small memory that contains about 32 of the most recent program instructions. The first time through a loop, the program instructions must be passed over the program memory bus. This results in slower operation because of the conflict with the coefficients that must also be fetched along this path. However, on additional executions of the loop, the program instructions can be pulled from the instruction cache. This means that all of the memory to CPU information transfers can be accomplished in a single cycle: the sample from the input signal comes over the data memory bus, the coefficient comes over the program memory bus, and the program instruction comes from the instruction cache. In the jargon of the field, this efficient transfer of data is called a high memoryaccess bandwidth. Figure 28-5 presents a more detailed view of the SHARC architecture, showing the I/O controller connected to data memory. This is how the signals enter and exit the system. For instance, the SHARC DSPs provides both serial and parallel communications ports. These are extremely high speed connections. For example, at a 40 MHz clock speed, there are two serial ports that operate at 40 Mbits/second each, while six parallel ports each provide a 40 Mbytes/second data transfer. When all six parallel ports are used together, the data transfer rate is an incredible 240 Mbytes/second. Chapter 28- Digital Signal Processors 511 Memory data and instructions Program Memory Data Memory instructions and secondary data data only Program Memory Data Memory instructions only data only a. Von Neumann Architecture ( ) b. Harvard Architecture ( ) c. Super Harvard Architecture ( ) address bus CPU data bus PM address bus PM data bus PM address bus PM data bus DM address bus DM data bus CPU DM address bus DM data bus single memory dual memory dual memory, instruction cache, I/O controller Instruction Cache CPU I/O Controller data FIGURE 28-4 Microprocessor architecture. The Von Neumann architecture uses a single memory to hold both data and instructions. In comparison, the Harvard architecture uses separate memories for data and instructions, providing higher speed. The Super Harvard Architecture improves upon the Harvard design by adding an instruction cache and a dedicated I/O controller. This is fast enough to transfer the entire text of this book in only 2 milliseconds! Just as important, dedicated hardware allows these data streams to be transferred directly into memory (Direct Memory Access, or DMA), without having to pass through the CPU's registers. In other words, tasks 1 & 14 on our list happen independently and simultaneously with the other tasks; no cycles are stolen from the CPU. The main buses (program memory bus and data memory bus) are also accessible from outside the chip, providing an additional interface to off-chip memory and peripherals. This allows the SHARC DSPs to use a four Gigaword (16 Gbyte) memory, accessible at 40 Mwords/second (160 Mbytes/second), for 32 bit data. Wow! This type of high speed I/O is a key characteristic of DSPs. The overriding goal is to move the data in, perform the math, and move the data out before the next sample is available. Everything else is secondary. Some DSPs have onboard analog-to-digital and digital-to-analog converters, a feature called mixed signal. However, all DSPs can interface with external converters through serial or parallel ports. 512 The Scientist and Engineer's Guide to Digital Signal Processing Now let's look inside the CPU. At the top of the diagram are two blocks labeled Data Address Generator (DAG), one for each of the two memories. These control the addresses sent to the program and data memories, specifying where the information is to be read from or written to. In simpler microprocessors this task is handled as an inherent part of the program sequencer, and is quite transparent to the programmer. However, DSPs are designed to operate with circular buffers, and benefit from the extra hardware to manage them efficiently. This avoids needing to use precious CPU clock cycles to keep track of how the data are stored. For instance, in the SHARC DSPs, each of the two DAGs can control eight circular buffers. This means that each DAG holds 32 variables (4 per buffer), plus the required logic. Why so many circular buffers? Some DSP algorithms are best carried out in stages. For instance, IIR filters are more stable if implemented as a cascade of biquads (a stage containing two poles and up to two zeros). Multiple stages require multiple circular buffers for the fastest operation. The DAGs in the SHARC DSPs are also designed to efficiently carry out the Fast Fourier transform. In this mode, the DAGs are configured to generate bit-reversed addresses into the circular buffers, a necessary part of the FFT algorithm. In addition, an abundance of circular buffers greatly simplifies DSP code generation- both for the human programmer as well as high-level language compilers, such as C. The data register section of the CPU is used in the same way as in traditional microprocessors. In the ADSP-2106x SHARC DSPs, there are 16 general purpose registers of 40 bits each. These can hold intermediate calculations, prepare data for the math processor, serve as a buffer for data transfer, hold flags for program control, and so on. If needed, these registers can also be used to control loops and counters; however, the SHARC DSPs have extra hardware registers to carry out many of these functions. The math processing is broken into three sections, a multiplier, an arithmetic logic unit (ALU), and a barrel shifter. The multiplier takes the values from two registers, multiplies them, and places the result into another register. The ALU performs addition, subtraction, absolute value, logical operations (AND, OR, XOR, NOT), conversion between fixed and floating point formats, and similar functions. Elementary binary operations are carried out by the barrel shifter, such as shifting, rotating, extracting and depositing segments, and so on. A powerful feature of the SHARC family is that the multiplier and the ALU can be accessed in parallel. In a single clock cycle, data from registers 0-7 can be passed to the multiplier, data from registers 8-15 can be passed to the ALU, and the two results returned to any of the 16 registers. There are also many important features of the SHARC family architecture that aren't shown in this simplified illustration. For instance, an 80 bit accumulator is built into the multiplier to reduce the round-off error associated with multiple fixed-point math operations. Another interesting Chapter 28- Digital Signal Processors 513 Program Memory Data Memory instructions and secondary data data only Address PM Data Generator Address DM Data Generator Data Registers Muliplier ALU Shifter PM address bus DM address bus PM data bus DM data bus Program Sequencer Instruction Cache I/O Controller (DMA) High speed I/O (serial, parallel, ADC, DAC, etc.) FIGURE 28-5 Typical DSP architecture. Digital Signal Processors are designed to implement tasks in parallel. This simplified diagram is of the Analog Devices SHARC DSP. Compare this architecture with the tasks needed to implement an FIR filter, as listed in Table 28-1. All of the steps within the loop can be executed in a single clock cycle. feature is the use of shadow registers for all the CPU's key registers. These are duplicate registers that can be switched with their counterparts in a single clock cycle. They are used for fast context switching, the ability to handle interrupts quickly. When an interrupt occurs in traditional microprocessors, all the internal data must be saved before the interrupt can be handled. This usually involves pushing all of the occupied registers onto the stack, one at a time. In comparison, an interrupt in the SHARC family is handled by moving the internal data into the shadow registers in a single clock cycle. When the interrupt routine is completed, the registers are just as quickly restored. This feature allows step 4 on our list (managing the sample-ready interrupt) to be handled very quickly and efficiently. Now we come to the critical performance of the architecture, how many of the operations within the loop (steps 6-12 of Table 28-1) can be carried out at the same time. Because of its highly parallel nature, the SHARC DSP can simultaneously carry out all of these tasks. Specifically, within a single clock cycle, it can perform a multiply (step 11), an addition (step 12), two data moves (steps 7 and 9), update two circular buffer pointers (steps 8 and 10), and 514 The Scientist and Engineer's Guide to Digital Signal Processing control the loop (step 6). There will be extra clock cycles associated with beginning and ending the loop (steps 3, 4, 5 and 13, plus moving initial values into place); however, these tasks are also handled very efficiently. If the loop is executed more than a few times, this overhead will be negligible. As an example, suppose you write an efficient FIR filter program using 100 coefficients. You can expect it to require about 105 to 110 clock cycles per sample to execute (i.e., 100 coefficient loops plus overhead). This is very impressive; a traditional microprocessor requires many thousands of clock cycles for this algorithm. Fixed versus Floating Point Digital Signal Processing can be divided into two categories, fixed point and floating point. These refer to the format used to store and manipulate numbers within the devices. Fixed point DSPs usually represent each number with a minimum of 16 bits, although a different length can be used. For instance, Motorola manufactures a family of fixed point DSPs that use 24 bits. There are four common ways that these 216 ’ 65,536 possible bit patterns can represent a number. In unsigned integer, the stored number can take on any integer value from 0 to 65,535. Similarly, signed integer uses two's complement to make the range include negative numbers, from -32,768 to 32,767. With unsigned fraction notation, the 65,536 levels are spread uniformly between 0 and 1. Lastly, the signed fraction format allows negative numbers, equally spaced between -1 and 1. In comparison, floating point DSPs typically use a minimum of 32 bits to store each value. This results in many more bit patterns than for fixed point, 232 ’ 4,294,967,296 to be exact. A key feature of floating point notation is that the represented numbers are not uniformly spaced. In the most common format (ANSI/IEEE Std. 754-1985), the largest and smallest numbers are ±3.4×1038 and ±1.2×10 , respectively. The represented values are unequally &38 spaced between these two extremes, such that the gap between any two numbers is about ten-million times smaller than the value of the numbers. This is important because it places large gaps between large numbers, but small gaps between small numbers. Floating point notation is discussed in more detail in Chapter 4. All floating point DSPs can also handle fixed point numbers, a necessity to implement counters, loops, and signals coming from the ADC and going to the DAC. However, this doesn't mean that fixed point math will be carried out as quickly as the floating point operations; it depends on the internal architecture. For instance, the SHARC DSPs are optimized for both floating point and fixed point operations, and executes them with equal efficiency. For this reason, the SHARC devices are often referred to as "32-bit DSPs," rather than just "Floating Point." Figure 28-6 illustrates the primary trade-offs between fixed and floating point DSPs. In Chapter 3 we stressed that fixed point arithmetic is much Chapter 28- Digital Signal Processors 515 Precision Product Cost Development Time Floating Point Fixed Point FIGURE 28-6 Dynamic Range Fixed versus floating point. Fixed point DSPs are generally cheaper, while floating point devices have better precision, higher dynamic range, and a shorter development cycle. faster than floating point in general purpose computers. However, with DSPs the speed is about the same, a result of the hardware being highly optimized for math operations. The internal architecture of a floating point DSP is more complicated than for a fixed point device. All the registers and data buses must be 32 bits wide instead of only 16; the multiplier and ALU must be able to quickly perform floating point arithmetic, the instruction set must be larger (so that they can handle both floating and fixed point numbers), and so on. Floating point (32 bit) has better precision and a higher dynamic range than fixed point (16 bit) . In addition, floating point programs often have a shorter development cycle, since the programmer doesn't generally need to worry about issues such as overflow, underflow, and round-off error. On the other hand, fixed point DSPs have traditionally been cheaper than floating point devices. Nothing changes more rapidly than the price of electronics; anything you find in a book will be out-of-date before it is printed. Nevertheless, cost is a key factor in understanding how DSPs are evolving, and we need to give you a general idea. When this book was completed in 1999, fixed point DSPs sold for between $5 and $100, while floating point devices were in the range of $10 to $300. This difference in cost can be viewed as a measure of the relative complexity between the devices. If you want to find out what the prices are today, you need to look today. Now let's turn our attention to performance; what can a 32-bit floating point system do that a 16-bit fixed point can't? The answer to this question is signal-to-noise ratio. Suppose we store a number in a 32 bit floating point format. As previously mentioned, the gap between this number and its adjacent neighbor is about one ten-millionth of the value of the number. To store the number, it must be round up or down by a maximum of one-half the gap size. In other words, each time we store a number in floating point notation, we add noise to the signal. The same thing happens when a number is stored as a 16-bit fixed point value, except that the added noise is much worse. This is because the gaps between adjacent numbers are much larger. For instance, suppose we store the number 10,000 as a signed integer (running from -32,768 to 32,767). The gap between numbers is one ten-thousandth of the value of the number we are storing. If we 516 The Scientist and Engineer's Guide to Digital Signal Processing want to store the number 1000, the gap between numbers is only one onethousandth of the value. Noise in signals is usually represented by its standard deviation. This was discussed in detail in Chapter 2. For here, the important fact is that the standard deviation of this quantization noise is about one-third of the gap size. This means that the signal-to-noise ratio for storing a floating point number is about 30 million to one, while for a fixed point number it is only about ten-thousand to one. In other words, floating point has roughly 30,000 times less quantization noise than fixed point. This brings up an important way that DSPs are different from traditional microprocessors. Suppose we implement an FIR filter in fixed point. To do this, we loop through each coefficient, multiply it by the appropriate sample from the input signal, and add the product to an accumulator. Here's the problem. In traditional microprocessors, this accumulator is just another 16 bit fixed point variable. To avoid overflow, we need to scale the values being added, and will correspondingly add quantization noise on each step. In the worst case, this quantization noise will simply add, greatly lowering the signalto- noise ratio of the system. For instance, in a 500 coefficient FIR filter, the noise on each output sample may be 500 times the noise on each input sample. The signal-to-noise ratio of ten-thousand to one has dropped to a ghastly twenty to one. Although this is an extreme case, it illustrates the main point: when many operations are carried out on each sample, it's bad, really bad. See Chapter 3 for more details. DSPs handle this problem by using an extended precision accumulator. This is a special register that has 2-3 times as many bits as the other memory locations. For example, in a 16 bit DSP it may have 32 to 40 bits, while in the SHARC DSPs it contains 80 bits for fixed point use. This extended range virtually eliminates round-off noise while the accumulation is in progress. The only round-off error suffered is when the accumulator is scaled and stored in the 16 bit memory. This strategy works very well, although it does limit how some algorithms must be carried out. In comparison, floating point has such low quantization noise that these techniques are usually not necessary. In addition to having lower quantization noise, floating point systems are also easier to develop algorithms for. Most DSP techniques are based on repeated multiplications and additions. In fixed point, the possibility of an overflow or underflow needs to be considered after each operation. The programmer needs to continually understand the amplitude of the numbers, how the quantization errors are accumulating, and what scaling needs to take place. In comparison, these issues do not arise in floating point; the numbers take care of themselves (except in rare cases). To give you a better understanding of this issue, Fig. 28-7 shows a table from the SHARC user manual. This describes the ways that multiplication can be carried out for both fixed and floating point formats. First, look at how floating point numbers can be multiplied; there is only one way! That Chapter 28- Digital Signal Processors 517 Rn MRF MRB Rn Rn MRF MRB Rn Rn MRF MRB Rn Rn MRF MRB Rn Rn MRF MRB MRF MRB MRxF MRxB Rn = MRF = MRB = MRF = MRB = MRF = MRB = MRF = MRB = SAT MRF = SAT MRB = SAT MRF = SAT MRB = RND MRF = RND MRB = RND MRF = RND MRB = 0 = Rn = MRxF MRxB = Rx * Ry + Rx * Ry - Rx * Ry S S F U U I FR S S (SI) (UI) (SF) (UF) (SF) (UF) ) S F U U I FR ) S F U U I FR ) Fn = Fx * Fy Fixed Point Floating Point ( ( ( FIGURE 28-7 Fixed versus floating point instructions. These are the multiplication instructions used in the SHARC DSPs. While only a single command is needed for floating point, many options are needed for fixed point. See the text for an explanation of these options. is, Fn = Fx * Fy, where Fn, Fx, and Fy are any of the 16 data registers. It could not be any simpler. In comparison, look at all the possible commands for fixed point multiplication. These are the many options needed to efficiently handle the problems of round-off, scaling, and format. In Fig. 28-7, Rn, Rx, and Ry refer to any of the 16 data registers, and MRF and MRB are 80 bit accumulators. The vertical lines indicate options. For instance, the top-left entry in this table means that all the following are valid commands: Rn = Rx * Ry, MRF = Rx * Ry, and MRB = Rx * Ry. In other words, the value of any two registers can be multiplied and placed into another register, or into one of the extended precision accumulators. This table also shows that the numbers may be either signed or unsigned (S or U), and may be fractional or integer (F or I). The RND and SAT options are ways of controlling rounding and register overflow. 518 The Scientist and Engineer's Guide to Digital Signal Processing There are other details and options in the table, but they are not important for our present discussion. The important idea is that the fixed point programmer must understand dozens of ways to carry out the very basic task of multiplication. In contrast, the floating point programmer can spend his time concentrating on the algorithm. Given these tradeoffs between fixed and floating point, how do you choose which to use? Here are some things to consider. First, look at how many bits are used in the ADC and DAC. In many applications, 12-14 bits per sample is the crossover for using fixed versus floating point. For instance, television and other video signals typically use 8 bit ADC and DAC, and the precision of fixed point is acceptable. In comparison, professional audio applications can sample with as high as 20 or 24 bits, and almost certainly need floating point to capture the large dynamic range. The next thing to look at is the complexity of the algorithm that will be run. If it is relatively simple, think fixed point; if it is more complicated, think floating point. For example, FIR filtering and other operations in the time domain only require a few dozen lines of code, making them suitable for fixed point. In contrast, frequency domain algorithms, such as spectral analysis and FFT convolution, are very detailed and can be much more difficult to program. While they can be written in fixed point, the development time will be greatly reduced if floating point is used. Lastly, think about the money: how important is the cost of the product, and how important is the cost of the development? When fixed point is chosen, the cost of the product will be reduced, but the development cost will probably be higher due to the more difficult algorithms. In the reverse manner, floating point will generally result in a quicker and cheaper development cycle, but a more expensive final product. Figure 28-8 shows some of the major trends in DSPs. Figure (a) illustrates the impact that Digital Signal Processors have had on the embedded market. These are applications that use a microprocessor to directly operate and control some larger system, such as a cellular telephone, microwave oven, or automotive instrument display panel. The name "microcontroller" is often used in referring to these devices, to distinguish them from the microprocessors used in personal computers. As shown in (a), about 38% of embedded designers have already started using DSPs, and another 49% are considering the switch. The high throughput and computational power of DSPs often makes them an ideal choice for embedded designs. As illustrated in (b), about twice as many engineers currently use fixed point as use floating point DSPs. However, this depends greatly on the application. Fixed point is more popular in competitive consumer products where the cost of the electronics must be kept very low. A good example of this is cellular telephones. When you are in competition to sell millions of your product, a cost difference of only a few dollars can be the difference between success and failure. In comparison, floating point is more common when greater performance is needed and cost is not important. For Chapter 28- Digital Signal Processors 519 No Plans Floating Point Next Year in 2000 Next Fixed Point Migrate Migrate Migrate Design b. DSP currently used c. Migration to floating point Considering Changed Considering Have Already Not a. Changing from uProc to DSP FIGURE 28-8 Major trends in DSPs. As illustrated in (a), about 38% of embedded designers have already switched from conventional microprocessors to DSPs, and another 49% are considering the change. In (b), about twice as many engineers use fixed point as use floating point DSPs. This is mainly driven by consumer products that must have low cost electronics, such as cellular telephones. However, as shown in (c), floating point is the fastest growing segment; over one-half of engineers currently using 16 bit devices plan to migrate to floating point DSPs instance, suppose you are designing a medical imaging system, such a computed tomography scanner. Only a few hundred of the model will ever be sold, at a price of several hundred-thousand dollars each. For this application, the cost of the DSP is insignificant, but the performance is critical. In spite of the larger number of fixed point DSPs being used, the floating point market is the fastest growing segment. As shown in (c), over one-half of engineers using 16-bits devices plan to migrate to floating point at some time in the near future. Before leaving this topic, we should reemphasize that floating point and fixed point usually use 32 bits and 16 bits, respectively, but not always. For 520 The Scientist and Engineer's Guide to Digital Signal Processing instance, the SHARC family can represent numbers in 32-bit fixed point, a mode that is common in digital audio applications. This makes the 232 quantization levels spaced uniformly over a relatively small range, say, between -1 and 1. In comparison, floating point notation places the 232 quantization levels logarithmically over a huge range, typically ±3.4×1038. This gives 32-bit fixed point better precision, that is, the quantization error on any one sample will be lower. However, 32-bit floating point has a higher dynamic range, meaning there is a greater difference between the largest number and the smallest number that can be represented. C versus Assembly DSPs are programmed in the same languages as other scientific and engineering applications, usually assembly or C. Programs written in assembly can execute faster, while programs written in C are easier to develop and maintain. In traditional applications, such as programs run on personal computers and mainframes, C is almost always the first choice. If assembly is used at all, it is restricted to short subroutines that must run with the utmost speed. This is shown graphically in Fig. 28-9a; for every traditional programmer that works in assembly, there are approximately ten that use C. However, DSP programs are different from traditional software tasks in two important respects. First, the programs are usually much shorter, say, onehundred lines versus ten-thousand lines. Second, the execution speed is often a critical part of the application. After all, that's why someone uses a DSP in the first place, for its blinding speed. These two factors motivate many software engineers to switch from C to assembly for programming Digital Signal Processors. This is illustrated in (b); nearly as many DSP programmers use assembly as use C. Figure (c) takes this further by looking at the revenue produced by DSP products. For every dollar made with a DSP programmed in C, two dollars are made with a DSP programmed in assembly. The reason for this is simple; money is made by outperforming the competition. From a pure performance standpoint, such as execution speed and manufacturing cost, assembly almost always has the advantage over C. For instance, C code usually requires a larger memory than assembly, resulting in more expensive hardware. However, the DSP market is continually changing. As the market grows, manufacturers will respond by designing DSPs that are optimized for programming in C. For instance, C is much more efficient when there is a large, general purpose register set and a unified memory space. These future improvements will minimize the difference in execution time between C and assembly, and allow C to be used in more applications. To better understand this decision between C and assembly, let's look at a typical DSP task programmed in each language. The example we will use is the calculation of the dot product of the two arrays, x [ ] and y [ ]. This is a simple mathematical operation, we multiply each coefficient in one Chapter 28- Digital Signal Processors 521 Assembly C b. DSP Programmers Assembly C a. Traditional Programmers Assembly C FIGURE 28-9 c. DSP Revenue Programming in C versus assembly. As shown in (a), only about 10% of traditional programmers (such as those that work on personal computers and mainframes) use assembly. However, as illustrated in (b), assembly is much more common in Digital Signal Processors. This is because DSP programs must operate as fast as possible, and are usually quite short. Figure (c) shows that assembly is even more common in products that generate a high revenue. TABLE 28-2 Dot product in C. This progam calculates the dot product of two arrays, x[ ] and y[ ], and stores the result in the variable, result. 001 #define LEN 20 002 float dm x[LEN]; 003 float pm y[LEN]; 004 float result; 005 006 main() 007 008 { 009 int n; 010 float s; 011 for (n=0;n