Consent Manager Tag v2.0 (for TCF 2.0) -->
Farnell PDF
Analog Devices Basic Mathematical Subroutines for the ADMC300
Analog Devices Basic Mathematical Subroutines for the ADMC300
- Revenir à l'accueil
Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
![[TXT]](http://www.audentia-gestion.fr/icons/text.gif)
Farnell-NA555-NE555-..> 08-Sep-2014 07:33 1.5M
Farnell-AD9834-Rev-D..> 08-Sep-2014 07:32 1.2M
Farnell-MSP430F15x-M..> 08-Sep-2014 07:32 1.3M
Farnell-AD736-Rev-I-..> 08-Sep-2014 07:31 1.3M
Farnell-AD8307-Data-..> 08-Sep-2014 07:30 1.3M
Farnell-Single-Chip-..> 08-Sep-2014 07:30 1.5M
Farnell-Quadruple-2-..> 08-Sep-2014 07:29 1.5M
Farnell-ADE7758-Rev-..> 08-Sep-2014 07:28 1.7M
Farnell-MAX3221-Rev-..> 08-Sep-2014 07:28 1.8M
Farnell-USB-to-Seria..> 08-Sep-2014 07:27 2.0M
Farnell-AD8313-Analo..> 08-Sep-2014 07:26 2.0M
Farnell-SN54HC164-SN..> 08-Sep-2014 07:25 2.0M
Farnell-AD8310-Analo..> 08-Sep-2014 07:24 2.1M
Farnell-AD8361-Rev-D..> 08-Sep-2014 07:23 2.1M
Farnell-2N3906-Fairc..> 08-Sep-2014 07:22 2.1M
Farnell-AD584-Rev-C-..> 08-Sep-2014 07:20 2.2M
Farnell-ADE7753-Rev-..> 08-Sep-2014 07:20 2.3M
Farnell-TLV320AIC23B..> 08-Sep-2014 07:18 2.4M
Farnell-AD586BRZ-Ana..> 08-Sep-2014 07:17 1.6M
Farnell-STM32F405xxS..> 27-Aug-2014 18:27 1.8M
Farnell-MSP430-Hardw..> 29-Jul-2014 10:36 1.1M
Farnell-LM324-Texas-..> 29-Jul-2014 10:32 1.5M
Farnell-LM386-Low-Vo..> 29-Jul-2014 10:32 1.5M
Farnell-NE5532-Texas..> 29-Jul-2014 10:32 1.5M
Farnell-Hex-Inverter..> 29-Jul-2014 10:31 875K
Farnell-AT90USBKey-H..> 29-Jul-2014 10:31 902K
Farnell-AT89C5131-Ha..> 29-Jul-2014 10:31 1.2M
Farnell-MSP-EXP430F5..> 29-Jul-2014 10:31 1.2M
Farnell-Explorer-16-..> 29-Jul-2014 10:31 1.3M
Farnell-TMP006EVM-Us..> 29-Jul-2014 10:30 1.3M
Farnell-Gertboard-Us..> 29-Jul-2014 10:30 1.4M
Farnell-LMP91051-Use..> 29-Jul-2014 10:30 1.4M
Farnell-Thermometre-..> 29-Jul-2014 10:30 1.4M
Farnell-user-manuel-..> 29-Jul-2014 10:29 1.5M
Farnell-fx-3650P-fx-..> 29-Jul-2014 10:29 1.5M
Farnell-2-GBPS-Diffe..> 28-Jul-2014 17:42 2.7M
Farnell-LMT88-2.4V-1..> 28-Jul-2014 17:42 2.8M
Farnell-Octal-Genera..> 28-Jul-2014 17:42 2.8M
Farnell-Dual-MOSFET-..> 28-Jul-2014 17:41 2.8M
Farnell-TLV320AIC325..> 28-Jul-2014 17:41 2.9M
Farnell-SN54LV4053A-..> 28-Jul-2014 17:20 5.9M
Farnell-TAS1020B-USB..> 28-Jul-2014 17:19 6.2M
Farnell-TPS40060-Wid..> 28-Jul-2014 17:19 6.3M
Farnell-TL082-Wide-B..> 28-Jul-2014 17:16 6.3M
Farnell-RF-short-tra..> 28-Jul-2014 17:16 6.3M
Farnell-maxim-integr..> 28-Jul-2014 17:14 6.4M
Farnell-TSV6390-TSV6..> 28-Jul-2014 17:14 6.4M
Farnell-Fast-Charge-..> 28-Jul-2014 17:12 6.4M
Farnell-NVE-datashee..> 28-Jul-2014 17:12 6.5M
Farnell-Excalibur-Hi..> 28-Jul-2014 17:10 2.4M
Farnell-Excalibur-Hi..> 28-Jul-2014 17:10 2.4M
Farnell-REF102-10V-P..> 28-Jul-2014 17:09 2.4M
Farnell-TMS320F28055..> 28-Jul-2014 17:09 2.7M
Farnell-MULTICOMP-Ra..> 22-Jul-2014 12:35 5.9M
Farnell-RASPBERRY-PI..> 22-Jul-2014 12:35 5.9M
Farnell-Dremel-Exper..> 22-Jul-2014 12:34 1.6M
Farnell-STM32F103x8-..> 22-Jul-2014 12:33 1.6M
Farnell-BD6xxx-PDF.htm 22-Jul-2014 12:33 1.6M
Farnell-L78S-STMicro..> 22-Jul-2014 12:32 1.6M
Farnell-RaspiCam-Doc..> 22-Jul-2014 12:32 1.6M
Farnell-SB520-SB5100..> 22-Jul-2014 12:32 1.6M
Farnell-iServer-Micr..> 22-Jul-2014 12:32 1.6M
Farnell-LUMINARY-MIC..> 22-Jul-2014 12:31 3.6M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:31 2.4M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:30 4.6M
Farnell-CLASS 1-or-2..> 22-Jul-2014 12:30 4.7M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:29 4.8M
Farnell-Evaluating-t..> 22-Jul-2014 12:28 4.9M
Farnell-LM3S6952-Mic..> 22-Jul-2014 12:27 5.9M
Farnell-Keyboard-Mou..> 22-Jul-2014 12:27 5.9M
Farnell-Full-Datashe..> 15-Jul-2014 17:08 951K
Farnell-pmbta13_pmbt..> 15-Jul-2014 17:06 959K
Farnell-EE-SPX303N-4..> 15-Jul-2014 17:06 969K
Farnell-Datasheet-NX..> 15-Jul-2014 17:06 1.0M
Farnell-Datasheet-Fa..> 15-Jul-2014 17:05 1.0M
Farnell-MIDAS-un-tra..> 15-Jul-2014 17:05 1.0M
Farnell-SERIAL-TFT-M..> 15-Jul-2014 17:05 1.0M
Farnell-MCOC1-Farnel..> 15-Jul-2014 17:05 1.0M
Farnell-TMR-2-series..> 15-Jul-2014 16:48 787K
Farnell-DC-DC-Conver..> 15-Jul-2014 16:48 781K
Farnell-Full-Datashe..> 15-Jul-2014 16:47 803K
Farnell-TMLM-Series-..> 15-Jul-2014 16:47 810K
Farnell-TEL-5-Series..> 15-Jul-2014 16:47 814K
Farnell-TXL-series-t..> 15-Jul-2014 16:47 829K
Farnell-TEP-150WI-Se..> 15-Jul-2014 16:47 837K
Farnell-AC-DC-Power-..> 15-Jul-2014 16:47 845K
Farnell-TIS-Instruct..> 15-Jul-2014 16:47 845K
Farnell-TOS-tracopow..> 15-Jul-2014 16:47 852K
Farnell-TCL-DC-traco..> 15-Jul-2014 16:46 858K
Farnell-TIS-series-t..> 15-Jul-2014 16:46 875K
Farnell-TMR-2-Series..> 15-Jul-2014 16:46 897K
Farnell-TMR-3-WI-Ser..> 15-Jul-2014 16:46 939K
Farnell-TEN-8-WI-Ser..> 15-Jul-2014 16:46 939K
Farnell-Full-Datashe..> 15-Jul-2014 16:46 947K
Farnell-HIP4081A-Int..> 07-Jul-2014 19:47 1.0M
Farnell-ISL6251-ISL6..> 07-Jul-2014 19:47 1.1M
Farnell-DG411-DG412-..> 07-Jul-2014 19:47 1.0M
Farnell-3367-ARALDIT..> 07-Jul-2014 19:46 1.2M
Farnell-ICM7228-Inte..> 07-Jul-2014 19:46 1.1M
Farnell-Data-Sheet-K..> 07-Jul-2014 19:46 1.2M
Farnell-Silica-Gel-M..> 07-Jul-2014 19:46 1.2M
Farnell-TKC2-Dusters..> 07-Jul-2014 19:46 1.2M
Farnell-CRC-HANDCLEA..> 07-Jul-2014 19:46 1.2M
Farnell-760G-French-..> 07-Jul-2014 19:45 1.2M
Farnell-Decapant-KF-..> 07-Jul-2014 19:45 1.2M
Farnell-1734-ARALDIT..> 07-Jul-2014 19:45 1.2M
Farnell-Araldite-Fus..> 07-Jul-2014 19:45 1.2M
Farnell-fiche-de-don..> 07-Jul-2014 19:44 1.4M
Farnell-safety-data-..> 07-Jul-2014 19:44 1.4M
Farnell-A-4-Hardener..> 07-Jul-2014 19:44 1.4M
Farnell-CC-Debugger-..> 07-Jul-2014 19:44 1.5M
Farnell-MSP430-Hardw..> 07-Jul-2014 19:43 1.8M
Farnell-SmartRF06-Ev..> 07-Jul-2014 19:43 1.6M
Farnell-CC2531-USB-H..> 07-Jul-2014 19:43 1.8M
Farnell-Alimentation..> 07-Jul-2014 19:43 1.8M
Farnell-BK889B-PONT-..> 07-Jul-2014 19:42 1.8M
Farnell-User-Guide-M..> 07-Jul-2014 19:41 2.0M
Farnell-T672-3000-Se..> 07-Jul-2014 19:41 2.0M
Farnell-0050375063-D..> 18-Jul-2014 17:03 2.5M
Farnell-Mini-Fit-Jr-..> 18-Jul-2014 17:03 2.5M
Farnell-43031-0002-M..> 18-Jul-2014 17:03 2.5M
Farnell-0433751001-D..> 18-Jul-2014 17:02 2.5M
Farnell-Cube-3D-Prin..> 18-Jul-2014 17:02 2.5M
Farnell-MTX-Compact-..> 18-Jul-2014 17:01 2.5M
Farnell-MTX-3250-MTX..> 18-Jul-2014 17:01 2.5M
Farnell-ATtiny26-L-A..> 18-Jul-2014 17:00 2.6M
Farnell-MCP3421-Micr..> 18-Jul-2014 17:00 1.2M
Farnell-LM19-Texas-I..> 18-Jul-2014 17:00 1.2M
Farnell-Data-Sheet-S..> 18-Jul-2014 17:00 1.2M
Farnell-LMH6518-Texa..> 18-Jul-2014 16:59 1.3M
Farnell-AD7719-Low-V..> 18-Jul-2014 16:59 1.4M
Farnell-DAC8143-Data..> 18-Jul-2014 16:59 1.5M
Farnell-BGA7124-400-..> 18-Jul-2014 16:59 1.5M
Farnell-SICK-OPTIC-E..> 18-Jul-2014 16:58 1.5M
Farnell-LT3757-Linea..> 18-Jul-2014 16:58 1.6M
Farnell-LT1961-Linea..> 18-Jul-2014 16:58 1.6M
Farnell-PIC18F2420-2..> 18-Jul-2014 16:57 2.5M
Farnell-DS3231-DS-PD..> 18-Jul-2014 16:57 2.5M
Farnell-RDS-80-PDF.htm 18-Jul-2014 16:57 1.3M
Farnell-AD8300-Data-..> 18-Jul-2014 16:56 1.3M
Farnell-LT6233-Linea..> 18-Jul-2014 16:56 1.3M
Farnell-MAX1365-MAX1..> 18-Jul-2014 16:56 1.4M
Farnell-XPSAF5130-PD..> 18-Jul-2014 16:56 1.4M
Farnell-DP83846A-DsP..> 18-Jul-2014 16:55 1.5M
Farnell-Dremel-Exper..> 18-Jul-2014 16:55 1.6M
Farnell-MCOC1-Farnel..> 16-Jul-2014 09:04 1.0M
Farnell-SL3S1203_121..> 16-Jul-2014 09:04 1.1M
Farnell-PN512-Full-N..> 16-Jul-2014 09:03 1.4M
Farnell-SL3S4011_402..> 16-Jul-2014 09:03 1.1M
Farnell-LPC408x-7x 3..> 16-Jul-2014 09:03 1.6M
Farnell-PCF8574-PCF8..> 16-Jul-2014 09:03 1.7M
Farnell-LPC81xM-32-b..> 16-Jul-2014 09:02 2.0M
Farnell-LPC1769-68-6..> 16-Jul-2014 09:02 1.9M
Farnell-Download-dat..> 16-Jul-2014 09:02 2.2M
Farnell-LPC3220-30-4..> 16-Jul-2014 09:02 2.2M
Farnell-LPC11U3x-32-..> 16-Jul-2014 09:01 2.4M
Farnell-SL3ICS1002-1..> 16-Jul-2014 09:01 2.5M
Farnell-T672-3000-Se..> 08-Jul-2014 18:59 2.0M
Farnell-tesa®pack63..> 08-Jul-2014 18:56 2.0M
Farnell-Encodeur-USB..> 08-Jul-2014 18:56 2.0M
Farnell-CC2530ZDK-Us..> 08-Jul-2014 18:55 2.1M
Farnell-2020-Manuel-..> 08-Jul-2014 18:55 2.1M
Farnell-Synchronous-..> 08-Jul-2014 18:54 2.1M
Farnell-Arithmetic-L..> 08-Jul-2014 18:54 2.1M
Farnell-NA555-NE555-..> 08-Jul-2014 18:53 2.2M
Farnell-4-Bit-Magnit..> 08-Jul-2014 18:53 2.2M
Farnell-LM555-Timer-..> 08-Jul-2014 18:53 2.2M
Farnell-L293d-Texas-..> 08-Jul-2014 18:53 2.2M
Farnell-SN54HC244-SN..> 08-Jul-2014 18:52 2.3M
Farnell-MAX232-MAX23..> 08-Jul-2014 18:52 2.3M
Farnell-High-precisi..> 08-Jul-2014 18:51 2.3M
Farnell-SMU-Instrume..> 08-Jul-2014 18:51 2.3M
Farnell-900-Series-B..> 08-Jul-2014 18:50 2.3M
Farnell-BA-Series-Oh..> 08-Jul-2014 18:50 2.3M
Farnell-UTS-Series-S..> 08-Jul-2014 18:49 2.5M
Farnell-270-Series-O..> 08-Jul-2014 18:49 2.3M
Farnell-UTS-Series-S..> 08-Jul-2014 18:49 2.8M
Farnell-Tiva-C-Serie..> 08-Jul-2014 18:49 2.6M
Farnell-UTO-Souriau-..> 08-Jul-2014 18:48 2.8M
Farnell-Clipper-Seri..> 08-Jul-2014 18:48 2.8M
Farnell-SOURIAU-Cont..> 08-Jul-2014 18:47 3.0M
Farnell-851-Series-P..> 08-Jul-2014 18:47 3.0M
Farnell-SL59830-Inte..> 06-Jul-2014 10:07 1.0M
Farnell-ALF1210-PDF.htm 06-Jul-2014 10:06 4.0M
Farnell-AD7171-16-Bi..> 06-Jul-2014 10:06 1.0M
Farnell-Low-Noise-24..> 06-Jul-2014 10:05 1.0M
Farnell-ESCON-Featur..> 06-Jul-2014 10:05 938K
Farnell-74LCX573-Fai..> 06-Jul-2014 10:05 1.9M
Farnell-1N4148WS-Fai..> 06-Jul-2014 10:04 1.9M
Farnell-FAN6756-Fair..> 06-Jul-2014 10:04 850K
Farnell-Datasheet-Fa..> 06-Jul-2014 10:04 861K
Farnell-ES1F-ES1J-fi..> 06-Jul-2014 10:04 867K
Farnell-QRE1113-Fair..> 06-Jul-2014 10:03 879K
Farnell-2N7002DW-Fai..> 06-Jul-2014 10:03 886K
Farnell-FDC2512-Fair..> 06-Jul-2014 10:03 886K
Farnell-FDV301N-Digi..> 06-Jul-2014 10:03 886K
Farnell-S1A-Fairchil..> 06-Jul-2014 10:03 896K
Farnell-BAV99-Fairch..> 06-Jul-2014 10:03 896K
Farnell-74AC00-74ACT..> 06-Jul-2014 10:03 911K
Farnell-NaPiOn-Panas..> 06-Jul-2014 10:02 911K
Farnell-LQ-RELAYS-AL..> 06-Jul-2014 10:02 924K
Farnell-ev-relays-ae..> 06-Jul-2014 10:02 926K
Farnell-ESCON-Featur..> 06-Jul-2014 10:02 931K
Farnell-Amplifier-In..> 06-Jul-2014 10:02 940K
Farnell-Serial-File-..> 06-Jul-2014 10:02 941K
Farnell-Both-the-Del..> 06-Jul-2014 10:01 948K
Farnell-Videk-PDF.htm 06-Jul-2014 10:01 948K
Farnell-EPCOS-173438..> 04-Jul-2014 10:43 3.3M
Farnell-Sensorless-C..> 04-Jul-2014 10:42 3.3M
Farnell-197.31-KB-Te..> 04-Jul-2014 10:42 3.3M
Farnell-PIC12F609-61..> 04-Jul-2014 10:41 3.7M
Farnell-PADO-semi-au..> 04-Jul-2014 10:41 3.7M
Farnell-03-iec-runds..> 04-Jul-2014 10:40 3.7M
Farnell-ACC-Silicone..> 04-Jul-2014 10:40 3.7M
Farnell-Series-TDS10..> 04-Jul-2014 10:39 4.0M
Farnell-03-iec-runds..> 04-Jul-2014 10:40 3.7M
Farnell-0430300011-D..> 14-Jun-2014 18:13 2.0M
Farnell-06-6544-8-PD..> 26-Mar-2014 17:56 2.7M
Farnell-3M-Polyimide..> 21-Mar-2014 08:09 3.9M
Farnell-3M-VolitionT..> 25-Mar-2014 08:18 3.3M
Farnell-10BQ060-PDF.htm 14-Jun-2014 09:50 2.4M
Farnell-10TPB47M-End..> 14-Jun-2014 18:16 3.4M
Farnell-12mm-Size-In..> 14-Jun-2014 09:50 2.4M
Farnell-24AA024-24LC..> 23-Jun-2014 10:26 3.1M
Farnell-50A-High-Pow..> 20-Mar-2014 17:31 2.9M
Farnell-197.31-KB-Te..> 04-Jul-2014 10:42 3.3M
Farnell-1907-2006-PD..> 26-Mar-2014 17:56 2.7M
Farnell-5910-PDF.htm 25-Mar-2014 08:15 3.0M
Farnell-6517b-Electr..> 29-Mar-2014 11:12 3.3M
Farnell-A-True-Syste..> 29-Mar-2014 11:13 3.3M
Farnell-ACC-Silicone..> 04-Jul-2014 10:40 3.7M
Farnell-AD524-PDF.htm 20-Mar-2014 17:33 2.8M
Farnell-ADL6507-PDF.htm 14-Jun-2014 18:19 3.4M
Farnell-ADSP-21362-A..> 20-Mar-2014 17:34 2.8M
Farnell-ALF1210-PDF.htm 04-Jul-2014 10:39 4.0M
Farnell-ALF1225-12-V..> 01-Apr-2014 07:40 3.4M
Farnell-ALF2412-24-V..> 01-Apr-2014 07:39 3.4M
Farnell-AN10361-Phil..> 23-Jun-2014 10:29 2.1M
Farnell-ARADUR-HY-13..> 26-Mar-2014 17:55 2.8M
Farnell-ARALDITE-201..> 21-Mar-2014 08:12 3.7M
Farnell-ARALDITE-CW-..> 26-Mar-2014 17:56 2.7M
Farnell-ATMEL-8-bit-..> 19-Mar-2014 18:04 2.1M
Farnell-ATMEL-8-bit-..> 11-Mar-2014 07:55 2.1M
Farnell-ATmega640-VA..> 14-Jun-2014 09:49 2.5M
Farnell-ATtiny20-PDF..> 25-Mar-2014 08:19 3.6M
Farnell-ATtiny26-L-A..> 13-Jun-2014 18:40 1.8M
Farnell-Alimentation..> 14-Jun-2014 18:24 2.5M
Farnell-Alimentation..> 01-Apr-2014 07:42 3.4M
Farnell-Amplificateu..> 29-Mar-2014 11:11 3.3M
Farnell-An-Improved-..> 14-Jun-2014 09:49 2.5M
Farnell-Atmel-ATmega..> 19-Mar-2014 18:03 2.2M
Farnell-Avvertenze-e..> 14-Jun-2014 18:20 3.3M
Farnell-BC846DS-NXP-..> 13-Jun-2014 18:42 1.6M
Farnell-BC847DS-NXP-..> 23-Jun-2014 10:24 3.3M
Farnell-BF545A-BF545..> 23-Jun-2014 10:28 2.1M
Farnell-BK2650A-BK26..> 29-Mar-2014 11:10 3.3M
Farnell-BT151-650R-N..> 13-Jun-2014 18:40 1.7M
Farnell-BTA204-800C-..> 13-Jun-2014 18:42 1.6M
Farnell-BUJD203AX-NX..> 13-Jun-2014 18:41 1.7M
Farnell-BYV29F-600-N..> 13-Jun-2014 18:42 1.6M
Farnell-BYV79E-serie..> 10-Mar-2014 16:19 1.6M
Farnell-BZX384-serie..> 23-Jun-2014 10:29 2.1M
Farnell-Battery-GBA-..> 14-Jun-2014 18:13 2.0M
Farnell-C.A-6150-C.A..> 14-Jun-2014 18:24 2.5M
Farnell-C.A 8332B-C...> 01-Apr-2014 07:40 3.4M
Farnell-CC2560-Bluet..> 29-Mar-2014 11:14 2.8M
Farnell-CD4536B-Type..> 14-Jun-2014 18:13 2.0M
Farnell-CIRRUS-LOGIC..> 10-Mar-2014 17:20 2.1M
Farnell-CS5532-34-BS..> 01-Apr-2014 07:39 3.5M
Farnell-Cannon-ZD-PD..> 11-Mar-2014 08:13 2.8M
Farnell-Ceramic-tran..> 14-Jun-2014 18:19 3.4M
Farnell-Circuit-Note..> 26-Mar-2014 18:00 2.8M
Farnell-Circuit-Note..> 26-Mar-2014 18:00 2.8M
Farnell-Cles-electro..> 21-Mar-2014 08:13 3.9M
Farnell-Conception-d..> 11-Mar-2014 07:49 2.4M
Farnell-Connectors-N..> 14-Jun-2014 18:12 2.1M
Farnell-Construction..> 14-Jun-2014 18:25 2.5M
Farnell-Controle-de-..> 11-Mar-2014 08:16 2.8M
Farnell-Cordless-dri..> 14-Jun-2014 18:13 2.0M
Farnell-Current-Tran..> 26-Mar-2014 17:58 2.7M
Farnell-Current-Tran..> 26-Mar-2014 17:58 2.7M
Farnell-Current-Tran..> 26-Mar-2014 17:59 2.7M
Farnell-Current-Tran..> 26-Mar-2014 17:59 2.7M
Farnell-DC-Fan-type-..> 14-Jun-2014 09:48 2.5M
Farnell-DC-Fan-type-..> 14-Jun-2014 09:51 1.8M
Farnell-Davum-TMC-PD..> 14-Jun-2014 18:27 2.4M
Farnell-De-la-puissa..> 29-Mar-2014 11:10 3.3M
Farnell-Directive-re..> 25-Mar-2014 08:16 3.0M
Farnell-Documentatio..> 14-Jun-2014 18:26 2.5M
Farnell-Download-dat..> 13-Jun-2014 18:40 1.8M
Farnell-ECO-Series-T..> 20-Mar-2014 08:14 2.5M
Farnell-ELMA-PDF.htm 29-Mar-2014 11:13 3.3M
Farnell-EMC1182-PDF.htm 25-Mar-2014 08:17 3.0M
Farnell-EPCOS-173438..> 04-Jul-2014 10:43 3.3M
Farnell-EPCOS-Sample..> 11-Mar-2014 07:53 2.2M
Farnell-ES2333-PDF.htm 11-Mar-2014 08:14 2.8M
Farnell-Ed.081002-DA..> 19-Mar-2014 18:02 2.5M
Farnell-F28069-Picco..> 14-Jun-2014 18:14 2.0M
Farnell-F42202-PDF.htm 19-Mar-2014 18:00 2.5M
Farnell-FDS-ITW-Spra..> 14-Jun-2014 18:22 3.3M
Farnell-FICHE-DE-DON..> 10-Mar-2014 16:17 1.6M
Farnell-Fastrack-Sup..> 23-Jun-2014 10:25 3.3M
Farnell-Ferric-Chlor..> 29-Mar-2014 11:14 2.8M
Farnell-Fiche-de-don..> 14-Jun-2014 09:47 2.5M
Farnell-Fiche-de-don..> 14-Jun-2014 18:26 2.5M
Farnell-Fluke-1730-E..> 14-Jun-2014 18:23 2.5M
Farnell-GALVA-A-FROI..> 26-Mar-2014 17:56 2.7M
Farnell-GALVA-MAT-Re..> 26-Mar-2014 17:57 2.7M
Farnell-GN-RELAYS-AG..> 20-Mar-2014 08:11 2.6M
Farnell-HC49-4H-Crys..> 14-Jun-2014 18:20 3.3M
Farnell-HFE1600-Data..> 14-Jun-2014 18:22 3.3M
Farnell-HI-70300-Sol..> 14-Jun-2014 18:27 2.4M
Farnell-HUNTSMAN-Adv..> 10-Mar-2014 16:17 1.7M
Farnell-Haute-vitess..> 11-Mar-2014 08:17 2.4M
Farnell-IP4252CZ16-8..> 13-Jun-2014 18:41 1.7M
Farnell-Instructions..> 19-Mar-2014 18:01 2.5M
Farnell-KSZ8851SNL-S..> 23-Jun-2014 10:28 2.1M
Farnell-L-efficacite..> 11-Mar-2014 07:52 2.3M
Farnell-LCW-CQ7P.CC-..> 25-Mar-2014 08:19 3.2M
Farnell-LME49725-Pow..> 14-Jun-2014 09:49 2.5M
Farnell-LOCTITE-542-..> 25-Mar-2014 08:15 3.0M
Farnell-LOCTITE-3463..> 25-Mar-2014 08:19 3.0M
Farnell-LUXEON-Guide..> 11-Mar-2014 07:52 2.3M
Farnell-Leaded-Trans..> 23-Jun-2014 10:26 3.2M
Farnell-Les-derniers..> 11-Mar-2014 07:50 2.3M
Farnell-Loctite3455-..> 25-Mar-2014 08:16 3.0M
Farnell-Low-cost-Enc..> 13-Jun-2014 18:42 1.7M
Farnell-Lubrifiant-a..> 26-Mar-2014 18:00 2.7M
Farnell-MC3510-PDF.htm 25-Mar-2014 08:17 3.0M
Farnell-MC21605-PDF.htm 11-Mar-2014 08:14 2.8M
Farnell-MCF532x-7x-E..> 29-Mar-2014 11:14 2.8M
Farnell-MICREL-KSZ88..> 11-Mar-2014 07:54 2.2M
Farnell-MICROCHIP-PI..> 19-Mar-2014 18:02 2.5M
Farnell-MOLEX-39-00-..> 10-Mar-2014 17:19 1.9M
Farnell-MOLEX-43020-..> 10-Mar-2014 17:21 1.9M
Farnell-MOLEX-43160-..> 10-Mar-2014 17:21 1.9M
Farnell-MOLEX-87439-..> 10-Mar-2014 17:21 1.9M
Farnell-MPXV7002-Rev..> 20-Mar-2014 17:33 2.8M
Farnell-MX670-MX675-..> 14-Jun-2014 09:46 2.5M
Farnell-Microchip-MC..> 13-Jun-2014 18:27 1.8M
Farnell-Microship-PI..> 11-Mar-2014 07:53 2.2M
Farnell-Midas-Active..> 14-Jun-2014 18:17 3.4M
Farnell-Midas-MCCOG4..> 14-Jun-2014 18:11 2.1M
Farnell-Miniature-Ci..> 26-Mar-2014 17:55 2.8M
Farnell-Mistral-PDF.htm 14-Jun-2014 18:12 2.1M
Farnell-Molex-83421-..> 14-Jun-2014 18:17 3.4M
Farnell-Molex-COMMER..> 14-Jun-2014 18:16 3.4M
Farnell-Molex-Crimp-..> 10-Mar-2014 16:27 1.7M
Farnell-Multi-Functi..> 20-Mar-2014 17:38 3.0M
Farnell-NTE_SEMICOND..> 11-Mar-2014 07:52 2.3M
Farnell-NXP-74VHC126..> 10-Mar-2014 16:17 1.6M
Farnell-NXP-BT136-60..> 11-Mar-2014 07:52 2.3M
Farnell-NXP-PBSS9110..> 10-Mar-2014 17:21 1.9M
Farnell-NXP-PCA9555 ..> 11-Mar-2014 07:54 2.2M
Farnell-NXP-PMBFJ620..> 10-Mar-2014 16:16 1.7M
Farnell-NXP-PSMN1R7-..> 10-Mar-2014 16:17 1.6M
Farnell-NXP-PSMN7R0-..> 10-Mar-2014 17:19 2.1M
Farnell-NXP-TEA1703T..> 11-Mar-2014 08:15 2.8M
Farnell-Nilï¬-sk-E-..> 14-Jun-2014 09:47 2.5M
Farnell-Novembre-201..> 20-Mar-2014 17:38 3.3M
Farnell-OMRON-Master..> 10-Mar-2014 16:26 1.8M
Farnell-OSLON-SSL-Ce..> 19-Mar-2014 18:03 2.1M
Farnell-OXPCIE958-FB..> 13-Jun-2014 18:40 1.8M
Farnell-PADO-semi-au..> 04-Jul-2014 10:41 3.7M
Farnell-PBSS5160T-60..> 19-Mar-2014 18:03 2.1M
Farnell-PDTA143X-ser..> 20-Mar-2014 08:12 2.6M
Farnell-PDTB123TT-NX..> 13-Jun-2014 18:43 1.5M
Farnell-PESD5V0F1BL-..> 13-Jun-2014 18:43 1.5M
Farnell-PESD9X5.0L-P..> 13-Jun-2014 18:43 1.6M
Farnell-PIC12F609-61..> 04-Jul-2014 10:41 3.7M
Farnell-PIC18F2455-2..> 23-Jun-2014 10:27 3.1M
Farnell-PIC24FJ256GB..> 14-Jun-2014 09:51 2.4M
Farnell-PMBT3906-PNP..> 13-Jun-2014 18:44 1.5M
Farnell-PMBT4403-PNP..> 23-Jun-2014 10:27 3.1M
Farnell-PMEG4002EL-N..> 14-Jun-2014 18:18 3.4M
Farnell-PMEG4010CEH-..> 13-Jun-2014 18:43 1.6M
Farnell-Panasonic-15..> 23-Jun-2014 10:29 2.1M
Farnell-Panasonic-EC..> 20-Mar-2014 17:36 2.6M
Farnell-Panasonic-EZ..> 20-Mar-2014 08:10 2.6M
Farnell-Panasonic-Id..> 20-Mar-2014 17:35 2.6M
Farnell-Panasonic-Ne..> 20-Mar-2014 17:36 2.6M
Farnell-Panasonic-Ra..> 20-Mar-2014 17:37 2.6M
Farnell-Panasonic-TS..> 20-Mar-2014 08:12 2.6M
Farnell-Panasonic-Y3..> 20-Mar-2014 08:11 2.6M
Farnell-Pico-Spox-Wi..> 10-Mar-2014 16:16 1.7M
Farnell-Pompes-Charg..> 24-Apr-2014 20:23 3.3M
Farnell-Ponts-RLC-po..> 14-Jun-2014 18:23 3.3M
Farnell-Portable-Ana..> 29-Mar-2014 11:16 2.8M
Farnell-Premier-Farn..> 21-Mar-2014 08:11 3.8M
Farnell-Produit-3430..> 14-Jun-2014 09:48 2.5M
Farnell-Proskit-SS-3..> 10-Mar-2014 16:26 1.8M
Farnell-Puissance-ut..> 11-Mar-2014 07:49 2.4M
Farnell-Q48-PDF.htm 23-Jun-2014 10:29 2.1M
Farnell-Radial-Lead-..> 20-Mar-2014 08:12 2.6M
Farnell-Realiser-un-..> 11-Mar-2014 07:51 2.3M
Farnell-Reglement-RE..> 21-Mar-2014 08:08 3.9M
Farnell-Repartiteurs..> 14-Jun-2014 18:26 2.5M
Farnell-S-TRI-SWT860..> 21-Mar-2014 08:11 3.8M
Farnell-SB175-Connec..> 11-Mar-2014 08:14 2.8M
Farnell-SMBJ-Transil..> 29-Mar-2014 11:12 3.3M
Farnell-SOT-23-Multi..> 11-Mar-2014 07:51 2.3M
Farnell-SPLC780A1-16..> 14-Jun-2014 18:25 2.5M
Farnell-SSC7102-Micr..> 23-Jun-2014 10:25 3.2M
Farnell-SVPE-series-..> 14-Jun-2014 18:15 2.0M
Farnell-Sensorless-C..> 04-Jul-2014 10:42 3.3M
Farnell-Septembre-20..> 20-Mar-2014 17:46 3.7M
Farnell-Serie-PicoSc..> 19-Mar-2014 18:01 2.5M
Farnell-Serie-Standa..> 14-Jun-2014 18:23 3.3M
Farnell-Series-2600B..> 20-Mar-2014 17:30 3.0M
Farnell-Series-TDS10..> 04-Jul-2014 10:39 4.0M
Farnell-Signal-PCB-R..> 14-Jun-2014 18:11 2.1M
Farnell-Strangkuhlko..> 21-Mar-2014 08:09 3.9M
Farnell-Supercapacit..> 26-Mar-2014 17:57 2.7M
Farnell-TDK-Lambda-H..> 14-Jun-2014 18:21 3.3M
Farnell-TEKTRONIX-DP..> 10-Mar-2014 17:20 2.0M
Farnell-Tektronix-AC..> 13-Jun-2014 18:44 1.5M
Farnell-Telemetres-l..> 20-Mar-2014 17:46 3.7M
Farnell-Termometros-..> 14-Jun-2014 18:14 2.0M
Farnell-The-essentia..> 10-Mar-2014 16:27 1.7M
Farnell-U2270B-PDF.htm 14-Jun-2014 18:15 3.4M
Farnell-USB-Buccanee..> 14-Jun-2014 09:48 2.5M
Farnell-USB1T11A-PDF..> 19-Mar-2014 18:03 2.1M
Farnell-V4N-PDF.htm 14-Jun-2014 18:11 2.1M
Farnell-WetTantalum-..> 11-Mar-2014 08:14 2.8M
Farnell-XPS-AC-Octop..> 14-Jun-2014 18:11 2.1M
Farnell-XPS-MC16-XPS..> 11-Mar-2014 08:15 2.8M
Farnell-YAGEO-DATA-S..> 11-Mar-2014 08:13 2.8M
Farnell-ZigBee-ou-le..> 11-Mar-2014 07:50 2.4M
Farnell-celpac-SUL84..> 21-Mar-2014 08:11 3.8M
Farnell-china_rohs_o..> 21-Mar-2014 10:04 3.9M
Farnell-cree-Xlamp-X..> 20-Mar-2014 17:34 2.8M
Farnell-cree-Xlamp-X..> 20-Mar-2014 17:35 2.7M
Farnell-cree-Xlamp-X..> 20-Mar-2014 17:31 2.9M
Farnell-cree-Xlamp-m..> 20-Mar-2014 17:32 2.9M
Farnell-cree-Xlamp-m..> 20-Mar-2014 17:32 2.9M
Farnell-ir1150s_fr.p..> 29-Mar-2014 11:11 3.3M
Farnell-manual-bus-p..> 10-Mar-2014 16:29 1.9M
Farnell-propose-plus..> 11-Mar-2014 08:19 2.8M
Farnell-techfirst_se..> 21-Mar-2014 08:08 3.9M
Farnell-testo-205-20..> 20-Mar-2014 17:37 3.0M
Farnell-testo-470-Fo..> 20-Mar-2014 17:38 3.0M
Farnell-uC-OS-III-Br..> 10-Mar-2014 17:20 2.0M
Sefram-7866HD.pdf-PD..> 29-Mar-2014 11:46 472K
Sefram-CAT_ENREGISTR..> 29-Mar-2014 11:46 461K
Sefram-CAT_MESUREURS..> 29-Mar-2014 11:46 435K
Sefram-GUIDE_SIMPLIF..> 29-Mar-2014 11:46 481K
Sefram-GUIDE_SIMPLIF..> 29-Mar-2014 11:46 442K
Sefram-GUIDE_SIMPLIF..> 29-Mar-2014 11:46 422K
Sefram-SP270.pdf-PDF..> 29-Mar-2014 11:46 464K
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 1 of 16
a
Basic Mathematical
Subroutines for the ADMC300
AN300-09
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 2 of 16
Table of Contents
SUMMARY...................................................................................................................... 3
1 THE MATHEMATICAL LIBRARY ROUTINES ........................................................ 3
1.1 Using the Mathematical Routines .................................................................................................................3
1.2 Formats of inputs and outputs and usage of DSP core registers ................................................................4
1.3 Square Root.....................................................................................................................................................4
1.4 Logarithm........................................................................................................................................................6
1.4.1 Common Logarithm (Base 10) ................................................................................................................6
1.4.2 Natural Logarithm....................................................................................................................................6
1.5 Reciprocal........................................................................................................................................................8
2.2 Division........................................................................................................................................................8
1.6 Access to the library: the header file.............................................................................................................9
2 SOFTWARE EXAMPLE: TESTING THE MATHEMATICAL FUNCTIONS ........... 10
2.1 The main program: main.dsp......................................................................................................................10
2.2 The main include file: main.h ......................................................................................................................12
2.3 Example outputs ...........................................................................................................................................13
2.3.1 Square Root ...........................................................................................................................................13
2.3.2 Logarithm ..............................................................................................................................................14
2.3.3 Division..................................................................................................................................................15
2.3.4 Reciprocal ..............................................................................................................................................15
3 DIFFERENCES BETWEEN LIBRARY AND ADMC300 “ROM-UTILITIES” ......... 16
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 3 of 16
Summary
This application note illustrates the usage of some basic trigonometric subroutines such as sine and
cosine. They are implemented in a library-like module for easy access. The realisation follows the one
described in chapter 4 of the DSP applications handbook1. Then, a software example will be described
that may be downloaded from the accompanying zipped files. Finally, some data will be shown
concerning the accuracy of the algorithms.
1 The Mathematical Library Routines
1.1 Using the Mathematical Routines
The routines are developed as an easy-to-use library, which has to be linked to the user’s application. The
library consists of two files. The file “mathfun.dsp” contains the assembly code for the subroutines. This
package has to be compiled and can then be linked to an application. The user simply has to include the
header file “mathfun.h”, which provides function-like calls to the routines. The following table
summarises the set of macros that are defined in this library. Note that every function stores the result in
the sr1 register, except for the division routine which makes the results available in ar.
Operation Usage Operands
Initialisation Set_DAG_registers_for_math_function; none
Square Root Square_Root (integer_part, fractional_part);
integer_part = dreg2 or constant
fractional_part = dreg3 or constant
Logarithm Base 10 Log10(integer_part, fractional_part);
integer_part = dreg2 or constant
fractional_part = dreg3 or constant
Natural Logarithm LogN(integer_part, fractional_part);
integer_part = dreg2 or constant
fractional_part = dreg3 or constant
Reciprocal Inverse(integer_part, fractional_part);
integer_part = dreg2 or constant
fractional_part = dreg3 or constant
Signed Division Signed_Division(integer_part, fractional_part);
integer_part = dreg2 or constant
fractional_part = dreg3 or constant
Table 1: Implemented routines
The routines do not require any configuration constants from the main include-file “main.h” that comes
with every application note. For more information about the general structure of the application notes and
including libraries into user applications refer to the Library Documentation File. Section 2 shows an
example of usage of this library. In the following sections each routine is explained in detail with the
relevant segments of code which is found in either “mathfun.h” or “mathfun.dsp”. For more information
see the comments in those files.
1 a ”Digital Signal Applications using the ADSP-2100 Family”, Volume 1, Prentice Hall, 1992
2 Any data register of the ADSP-2171 core except mr0
3 Any data register of the ADSP-2171 core except mr1
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 4 of 16
1.2 Formats of inputs and outputs and usage of DSP core registers
The implementation of the macros listed in the previous section is based on the subroutines of Table 2.
Note that the first four accept input in the unsigned 16.16 format and that the output is in various single
precision format. The division routine expects a signed double precision value (for instance 1.31 or 8.24
…). Its output is in the ar register in a format that is determined by the input.
It may also be noted that the DAG registers M5 and L5 must be set to 1 and 0 respectively and that they
are not modified by the mathematical routines. The already mentioned call to
Set_DAG_registers_for_math_function prepares these registers for the functions. It now becomes clear
that this routine is necessary only once if M5 and/or L5 are not modified in another part of the user’s
code, as shown in the example in section 2.
Refer to the above-mentioned DSP applications handbook for more details on the routines described in
the previous sections.
Subroutine Input Output Modified Registers Other registers
(Must be set)
sqrt_(x) MR1, MR0 unsigned
16.16 Format
0 ≤ X <65536
SR1 in unsigned
8.8 format
AX0,AX1,AY0,AY1,AF,AR,
MY0, MY1,MX0,MF, MR,
SE, SR, I5
M5=1
L5=0
Log10_(x) MR1, MR0 unsigned
16.16 format
0 ≤ X <65536
SR1 in signed 4.12
format
AX0, AX1,AY0,AR,
MY1, MX0, MX1, MF, MR,
SE, SR, I5
M5=1
L5=0
Ln_(x) MR1, MR0 unsigned
16.16 format
0 ≤ X <65536
SR1 in signed
5.11 format
AX0, AX1,AY0,AR,
MY1, MX0, MX1, MF, MR,
SE, SR, I5
M5=1
L5=0
inv_(x) MR1, MR0 16.16
Format 1 ≤ x <32768
SR1 in signed 1.15
format
AX0,AY1, AY0,
MR1, MR0,
SR1, SR0
---
div_(x) Dividend NL.NR format
Divisor DL.DR format
AR in signed (NL
–DL+1).(NR-DR-
1) format
AX0, AX1, AR, AF, AY0, AY1
---
Table 2: Input and output format, modified registers for the mathematical routines
1.3 Square Root
The following equation approximates the square root of the input value x, where 0.5 ≤ x ≤1:
0.0560605 0.1037903
0.5* ( ) 0.7274475 0.672455 0.553406 0.2682495
5
2 3 4
+ +
= − + − +
x
sqrt x x x x x
( 1)
Text Box 1.2 shows the part of subroutine for getting square root when the original input falls into the
equation valid range between 0.5 and 1.0.
In the square root subroutine, the input is in 16.16 format, with unsigned integer in MR1 register and full
fraction in MR0 register. Therefore, the valid input range for the square root subroutine is between 0 and
65536 (0xFFFF.FFFF). If the input value is out of the range between 0.5 and 1.0, the square root
subroutine will scale the input in MR1 and MR0 registers by shift operation so that the scaled value will
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 5 of 16
fall into the valid equation range as input to equation ( 1) for computation. Obviously, the square root of
the scaled input obtained from equation ( 1) must be multiplied by the square root of the scaling value to
produce the square root of the original input as implemented in the following segment.
.VAR/PM/RAM/SEG=USER_PM1 sqrt_coeff[5];
.INIT sqrt_coeff : 0x5D1D00, 0xA9ED00, 0x46D600, 0xDDAA00, 0x072D00;
sqrt_: AX1=MR1; { store for knowing MSB }
AR = PASS MR1;
IF GE JUMP calculation; {MSB = 1 ?}
SR = LSHIFT MR1 BY -1 (HI); { left shift by 1 }
SR = SR OR LSHIFT MR0 BY -1 (LO);
MR1 = SR1; MR0 = SR0;
calculation: I5 = ^sqrt_coeff; {pointer to coeff. buffer}
SE=EXP MR1 (HI); {Check for redundant bits}
SE=EXP MR0 (LO);
AX0=SE, SR=Norm MR1 (HI);
SR=SR OR NORM MR0 (LO);
MY0=SR1, AR=PASS SR1;
IF EQ RTS;
MR=0;
MR1=base; {Load constant value}
MF=AR*MY0 (RND), MX0=PM(I5,M5); {MF =x*x}
MR=MR+MX0*MY0 (SS), MX0=PM(I5,M5); {MR = base + C1*x}
CNTR=4;
DO approx UNTIL CE;
MR=MR+MX0*MF (SS), MX0=PM(I5,M5);
approx: MF=AR*MF (RND);
AY0=15;
MY0=MR1, AR=AX0+AY0; {SE + 15 = 0?}
IF NE JUMP scale; {No, compute scaling value}
SR=ASHIFT MR1 BY -6 (HI);
Jump modification;
The next segment shows that the scaling value (1 2) 15 = ÷ + SE s is calculated where SE is the exponent
detector value of the original input. If (SE+15) is negative, it means that original input is less than 0.5
and the approximated result of the scaled input is to be multiplied by the scaling number of
15 (1 2) ÷ + SE . Otherwise, the original value is larger than 1.0 and the approximated square root of the
scaled input is multiplied with the reciprocal of the scaling number in order to get the result of the original
input. It should be realised that equation ( 1) is for calculation of 0.5*Square_Root(x) and it is one of the
factors under consideration when the subroutine Square_Root(x) shifts the result to get 8.8 format for the
output of the original input.
scale: MR=0;
MR1=sqrt2a; {Load 1/sqrt2(2)}
MY1=MR1, AR=ABS AR;
AY0=AR;
AR=AY0-1;
IF EQ JUMP pwr_ok;
CNTR=AR; {Compute S=(1/sqrt2(2))^(ABS(SE+15)) }
DO compute UNTIL CE;
compute: MR=MR1*MY1 (RND);
pwr_ok: IF NEG JUMP frac; {If (SE+15) is negative, ...}
AY1=0x0080; {Load a 1 in 9.23 format}
AY0=0; {calculate 1/S, if (SE+15) positive }
DIVS AY1, MR1;
DIVQ MR1; DIVQ MR1; DIVQ MR1;
DIVQ MR1; DIVQ MR1; DIVQ MR1;
DIVQ MR1; DIVQ MR1; DIVQ MR1;
DIVQ MR1; DIVQ MR1; DIVQ MR1;
DIVQ MR1; DIVQ MR1; DIVQ MR1;
MX0=AY0;
MR=0;
MR0=0x2000;
MR=MR+MX0*MY0 (US); { 9.23 format in result }
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 6 of 16
SR=ASHIFT MR1 BY 2 (HI); { to compensate the coefficient scaling }
SR=SR OR LSHIFT MR0 BY 2 (LO); { and get 8.8 format }
Jump modification;
frac: MR=MR1*MY0 (RND);
SR=ASHIFT MR1 BY -6 (HI); { compensate coefficient scaling }
{ and get 8.8 format}
modification: AR = PASS AX1;
IF GE RTS; { MSB = 1? }
MY1 = sqrt_2; { if yes, the original left shifted 1 bit }
MR = SR1 * MY1(uu); { multiplied by sqrt2(2) to get final result }
SR1 = MR1;
RTS;
1.4 Logarithm
1.4.1 Common Logarithm (Base 10)
The following equation approximates the common logarithm of the input value 11, is shown here. If the input
falls outside of this valid range, the output will reach saturation and ALU overflow bit AC in the ASTAT
register will be set. The integer part of the input is stored in MR1 register in signed 16.0 twos complement
format, while the fractional part of the input in MR0 in 0.16 format. The final result is in signed 1.15
format in SR1 register.
inv_: AR = PASS MR1;
IF GE JUMP dps1; { x >= 0 ?? }
JUMP dps2;
dps1: AY1 = 0x1; AY0 = 0x0; { x > 1 ?? }
AR = MR0-AY0;
SR0=AR, AR = MR1-AY1+C-1;
JUMP overflow;
dps2: SR1 = 0xFFFF; SR0 = 0x0; { x < -1 }
AY1 = MR1; AY0 = MR0;
AR = SR0-AY0;
AR = SR1-AY1+C-1;
overflow: IF GT JUMP inv_1; { if ABS(x)<=1, overflow }
SR1 = 0x7FFF;
AR = PASS AY1;
IF GT JUMP Returning;
SR1 = 0x8000;
Returning: ASTAT=0x4; { set AV }
RTS;
inv_1: AY1=0x4000; { if ABS(x)>1, division start here }
AY0=0; { numerator = 1 }
SE=EXP MR1 (HI); {Check for redundant bits}
SR=NORM MR1 (HI);
SR=SR OR NORM MR0 (LO);
DIVS AY1, SR1;
DIVQ SR1; DIVQ SR1; DIVQ SR1;
DIVQ SR1; DIVQ SR1; DIVQ SR1;
DIVQ SR1; DIVQ SR1; DIVQ SR1;
DIVQ SR1; DIVQ SR1; DIVQ SR1;
DIVQ SR1; DIVQ SR1; DIVQ SR1;
MR1= AY0; { in 1.15 format }
AX0=-14; AY1=SE;
AR = AX0 - AY1;
SE = AR;
SR = ASHIFT MR1 (HI); { Output in SR1 in 1.15 format }
RTS;
2.2 Division
A single-precision division subroutine is implemented hereafter, with a 32-bit signed dividend
(numerator) and a 16-bit signed divisor (denominator) to yield a 16-bit quotient. The dividend is in
NL.NR format and divisor is in DL.DR format. The quotient will be in (NL-DL+1).(NR-DR-1) format.
For example, if the divisor is in 1.31 format and divisor 1.15 format, the quotient will be in 1.15 format.
Some format manipulation may be necessary to guarantee the validity of the quotient, otherwise, the
output may saturate and AV in ASTAT register is set. For example, if both operands are positive and
fully fractional with dividend and divisor in 1.31 and 1.15 signed format respectively, the result is fully
fractional in 1.15 format and therefore the dividend must be smaller than the divisor for a valid result.
This subroutine can not be used for integer division or unsigned division.
div_: AX1=AY1,AF=AX0-AY1;
AR=ABS AX0;
if NE JUMP test_2;
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 9 of 16
AR=0x7FFF;
AF=PASS AY1;
if LT AR= NOT AR; {return +/- infinity}
ASTAT=0x4; {Division by Zero }
RTS;
test_2: {Division by -1}
if NOT AV JUMP test_3;
AR = -AY1; {Return -x }
RTS;
test_3: {x=y therefore return 1}
AF=PASS AF;
if NE JUMP test_4;
AR=0x7FFF;
ASTAT=0x0;
RTS;
test_4:
AX1=AY1,AR=ABS AX0;
AF=ABS AX1;
AF=AF-AR;
if LT JUMP do_div;
AR=0x7FFF;
AF=PASS AY1;
if LT AR= NOT AR; {return - infinity}
AF=PASS AX0;
if LT AR= NOT AR; {return - * - infinity}
ASTAT=0x4; {Division Overflow}
RTS;
do_div:
DIVS AY1,AX0;
CNTR=15;
do do_div01 until ce;
do_div01: DIVQ AX0;
AR=AY0;
AF=PASS AX0;
if LT AR=-AR;
RTS;
1.6 Access to the library: the header file
The library may be accessed by including the header file “mathfun.h” into the application code.
The header file is intended to provide function-like calls to the routines presented in the previous section. It
defines the calls shown in Table 1. The file is self-explaining and needs no further comments.
It is worth adding a few comments about efficiency of these routines. The first macro simply sets the DAG
registers M5 and L5 to its correct values. The user may however just replace the macro with one of its
instructions when the application code modifies just one of these registers. The sine and cosine subroutines
expect the argument to be placed into certain registers. This is what the macros do. However, if the argument
is already in the correct registers, the macro call inserts obsolete instruction. In this case, it is more efficient
to replace the macro call by a call instruction to the corresponding subroutine.
.MACRO Set_DAG_registers_for_math_function;
M5 = 1;
L5 = 0;
.ENDMACRO;
.MACRO Square_Root(%0, %1);
MR1 = %0;
MR0 = %1;
call sqrt_;
.ENDMACRO;
.MACRO Log10(%0, %1);
MR1 = %0;
MR0 = %1;
call Log10_;
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 10 of 16
.ENDMACRO;
.MACRO LogN(%0, %1);
MR1 = %0;
MR0 = %1;
call ln_;
.ENDMACRO;
.MACRO Inverse(%0, %1);
MR1 = %0;
MR0 = %1;
call inv_;
.ENDMACRO;
.MACRO Signed_Division(%0,%1,%2);
AY1 = %0;
AY0 = %1;
AX0 = %2;
call div_;
.ENDMACRO;
.MACRO Atan(%0, %1);
mr1= %0;
mr0= %1;
call Atan_;
.ENDMACRO;
2 Software Example: Testing the Mathematical Functions
2.1 The main program: main.dsp
The example demonstrates how to use the routines. All it does is to cycle through parts of the range of
definition of the functions and converting the results by means of the digital to analog converter. The
application has been adapted from two previous notes4,5. This section will only explain the few and
intuitive modifications to those applications.
The file “main.dsp” contains the initialisation and PWM Sync and Trip interrupt service routines. To
activate, build the executable file using the attached build.bat either within your DOS prompt or clicking
on it from Windows Explorer. This will create the object files and the main.exe example file. This file
may be run on the Motion Control Debugger.
In the following, a brief description of the additional code (put in evidence by bold characters) is given.
Start of code – declaring start location in program memory
.MODULE/RAM/SEG=USER_PM1/ABS=0x60 Main_Program;
Next, the general systems constants and PWM configuration constants (main.h – see the next section) are
included. Also included are the PWM library, the DAC interface library, the trigonometric library and the
mathematical library.
{***************************************************************************************
* Include General System Parameters and Libraries *
***************************************************************************************}
#include ;
#include ;
#include ;
#include ;
4 AN300-03: Three-Phase Sine-Wave Generation using the PWM Unit of the ADMC300
5 AN300-06: Using the Serial Digital to Analog Converter of the ADMC Connector Board
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 11 of 16
#include ;
The argument variable Theta is defined hereafter.
{***************************************************************************************
* Local Variables Defined in this Module *
***************************************************************************************}
.VAR/DM/RAM/SEG=USER_DM Theta; { Current angle }
.INIT Theta : 0x0000;
First, the PWM block is set up to generate interrupts every 100μs (see “main.h” in the next Section). The
variable Theta, which stores the argument of the trigonometric functions, is set to zero. Before using the
trigonometric functions, it is necessary to initialise certain registers of the data-address-generator (DAG) of
the DSP core. This will be discussed in more detail in the next section. However, note that this is done only
once in this example. If those registers are modified in other parts of the user’s code, then it must be repeated
before a call to a trigonometric function.
The main loop just waits for interrupts.
{********************************************************************************************}
{ Start of program code }
{********************************************************************************************}
Startup:
PWM_Init(PWMSYNC_ISR, PWMTRIP_ISR);
DAC_Init;
IFC = 0x80; { Clear any pending IRQ2 inter. }
ay0 = 0x200; { unmask irq2 interrupts. }
ar = IMASK;
ar = ar or ay0;
IMASK = ar; { IRQ2 ints fully enabled here }
ar = pass 0;
DM(Theta)= ar;
Set_DAG_registers_for_trigonometric;
Main: { Wait for interrupt to occur }
jump Main;
rts;
The interrupt service routine simply shows how to use the described functions. Variable Theta is incremented
in every interrupt service and is used as input for testing the mathematical functions. This main routine is
very similar to the one used in Application Note: AN300-10.
{********************************************************************************************}
{ PWM Interrupt Service Routine }
{********************************************************************************************}
PWMSYNC_ISR:
AX1 = DM(THETA);
COS(ax1);
DAC_PUT(1, AR); { output cos(x) }
MY0 = 0x4000;
MR = AR * MY0(SS);
AY0 = 0x4000;
AR = MR1 + AY0;
SR = LSHIFT AR BY 1 (LO);
Square_Root(SR1, SR0);
SR = LSHIFT SR1 BY 7 (HI);
DAC_PUT(2, SR1); { output ABS(cos(x/2) }
SR1 = DM(THETA);
SR0 = 0;
Square_Root(SR1, SR0);
SR = LSHIFT SR1 BY -1 (HI); { output Square_Root(x) }
DAC_PUT(3, SR1);
AX1 = DM(THETA); { log10(x), fractional input }
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 12 of 16
LOG10(0x0000,AX1);
DAC_PUT(4, SR1);
AX1 = DM(THETA); { Log10(x), integer input }
LOG10(AX1, 0x0000);
DAC_PUT(5, SR1);
AX1 = DM(THETA); { LogN(x), fractional input }
LogN(0x0000,AX1);
DAC_PUT(6, SR1);
AX1 = DM(THETA); { LogN(x), integer input }
LogN(AX1, 0x0000);
DAC_PUT(7, SR1);
{ tan(x) for division test }
{ AX0= DM(THETA);
AY1 = 0x1FFF; AR=ABS AX0;
AR = AR - AY1;
IF GT JUMP No_div;
cos(AX0);
AX1 = AR;
sin(AX0);
Signed_Division(AR,0x0000,AX1);
Jump PUT;
No_div: AR = 0;
PUT: DAC_PUT(8, AR);
}
SR1 = DM(THETA); { Inverse(x) }
SR = ASHIFT SR1 by -11 (HI);
Inverse(SR1, SR0);
DAC_PUT(8, SR1);
DAC_Update;
ax1= DM(Theta);
ar= ax1 +1;
DM(Theta)= ar;
RTI;
2.2 The main include file: main.h
This file contains the definitions of ADMC300 constants, general-purpose macros and the configuration
parameters of the system and library routines. It should be included in every application. For more
information refer to the Library Documentation File.
This file is mostly self-explaining. As already mentioned, the trigonometric library does not require any
configuration parameters. The following defines the parameters for the PWM ISR used in this example.
{********************************************************************************************}
{ Library: PWM block }
{ file : PWM300.dsp }
{ Application Note: Usage of the ADMC300 Pulse Width Modulation Block }
.CONST PWM_freq = 10000; {Desired PWM switching frequency [Hz] }
.CONST PWM_deadtime = 1000; {Desired deadtime [nsec] }
.CONST PWM_minpulse = 1000; {Desired minimal pulse time [nsec] }
.CONST PWM_syncpulse = 1540; {Desired sync pulse time [nsec] }
{********************************************************************************************}
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 13 of 16
2.3 Example outputs
2.3.1 Square Root
The example applies the square root function to perform the calculation of equation (4.1). The result is
directed to the digital to analog converters on the connection board. Figure 1 shows the output waveforms
of cos(x) and cos(x / 2) .
It is well known that
2
cos( ) 1
cos( ) / 2) = + x
x ( 6)
Figure 1: cos(x) and cos(x / 2)
The valid input to the square root function is from 0x0000.0000 to 0xFFFF.FFFF in MR registers. For the
D/A converter, digital value 0 is corresponding to 2.5v, -1 to 0V and +1 to 5V in the DAC outputs.
Figure 2: Square _ Root(x)
Figure 2 shows the result in another test when x is increased from 0x0000.0000 to 0xFFFF.0000. The
output is in a range of 0x00.00 and 0xFF.00.
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 14 of 16
2.3.2 Logarithm
2.3.2.1 Common logarithm
Figure 3 shows the results of calculating log10(x) for an input range 0= 0 THEN PHASE[K%] = PHASE[K%] + PI
300 NEXT K%
310 '
320 '
330 ' 'Polar-to-rectangular conversion, Eq. 8-7
340 FOR K% = 0 TO 256
350 REX[K%] = MAG[K%] * COS( PHASE[K%] )
360 IMX[K%] = MAG[K%] * SIN( PHASE[K%] )
370 NEXT K%
380 '
390 END
TABLE 8-3
Nuisance 2: Divide by zero error
When converting from rectangular to polar notation, it is very common to
find frequencies where the real part is zero and the imaginary part is some
nonzero value. This simply means that the phase is exactly 90 or -90
degrees. Try to tell your computer this! When your program tries to
calculate the phase from: Phase X[k] ’ arctan( Im X[k] / Re X[k]) , a divide by
zero error occurs. Even if the program execution doesn't halt, the phase
you obtain for this frequency won't be correct. To avoid this problem, the
real part must be tested for being zero before the division. If it is zero, the
imaginary part must be tested for being positive or negative, to determine
whether to set the phase to B/2 or -B/2, respectively. Lastly, the division
needs to be bypassed. Nothing difficult in all these steps, just the potential
for aggravation. An alternative way to handle this problem is shown in
line 250 of Table 8-3. If the real part is zero, change it to a negligibly
small number to keep the math processor happy during the division.
Nuisance 3: Incorrect arctan
Consider a frequency domain sample where ReX[k] ’ 1 and Im X[k] ’ 1.
Equation 8-6 provides the corresponding polar values of Mag X[k] ’ 1.414 and
Phase X[k] ’ 45E. Now consider another sample where ReX[k] ’ &1 and
166 The Scientist and Engineer's Guide to Digital Signal Processing
FIGURE 8-11
The phase of small magnitude signals. At frequencies where the magnitude drops to a very low value, round-off
noise can cause wild excursions of the phase. Don't make the mistake of thinking this is a meaningful signal.
Frequency
0 0.1 0.2 0.3 0.4 0.5
0.0
0.5
1.0
1.5
a. Mag X[ ]
Frequency
0 0.1 0.2 0.3 0.4 0.5
-5
-4
-3
-2
-1
0
1
2
3
4
5
b. Phase X[ ]
Amplitude
Phase (radians)
Im X[k] ’ &1. Again, Eq. 8-6 provides the values of Mag X[k] ’ 1.414 and
Phase X[k] ’ 45E. The problem is, the phase is wrong! It should be &135E.
This error occurs whenever the real part is negative. This problem can be
corrected by testing the real and imaginary parts after the phase has been
calculated. If both the real and imaginary parts are negative, subtract 180E
(or B radians) from the calculated phase. If the real part is negative and the
imaginary part is positive, add 180E (or B radians). Lines 340 and 350 of the
program in Table 8-3 show how this is done. If you fail to catch this problem,
the calculated value of the phase will only run between -B/2 and B/2, rather
than between -B and B. Drill this into your mind. If you see the phase only
extending to ±1.5708, you have forgotten to correct the ambiguity in the
arctangent calculation.
Nuisance 4: Phase of very small magnitudes
Imagine the following scenario. You are grinding away at some DSP task, and
suddenly notice that part of the phase doesn't look right. It might be noisy,
jumping all over, or just plain wrong. After spending the next hour looking
through hundreds of lines of computer code, you find the answer. The
corresponding values in the magnitude are so small that they are buried in
round-off noise. If the magnitude is negligibly small, the phase doesn't have
any meaning, and can assume unusual values. An example of this is shown in
Fig. 8-11. It is usually obvious when an amplitude signal is lost in noise; the
values are so small that you are forced to suspect that the values are
meaningless. The phase is different. When a polar signal is contaminated
with noise, the values in the phase are random numbers between -B and B.
Unfortunately, this often looks like a real signal, rather than the nonsense it
really is.
Nuisance 5: 2B ambiguity of the phase
Look again at Fig. 8-10d, and notice the several discontinuities in the data.
Every time a point looks as if it is going to dip below -3.14592, it snaps
back to 3.141592. This is a result of the periodic nature of sinusoids. For
Chapter 8- The Discrete Fourier Transform 167
FIGURE 8-12
Example of phase unwrapping. The top curve
shows a typical phase signal obtained from a
rectangular-to-polar conversion routine. Each
value in the signal must be between -B and B
(i.e., -3.14159 and 3.14159). As shown in the
lower curve, the phase can be unwrapped by
adding or subtracting integer multiplies of 2B
from each sample, where the integer is chosen
to minimize the discontinuities between points.
Frequency
0 0.1 0.2 0.3 0.4 0.5
-40
-30
-20
-10
0
10
wrapped
unwrapped
Phase (radians)
100 ' PHASE UNWRAPPING
110 '
120 DIM PHASE[256] 'PHASE[ ] holds the original phase
130 DIM UWPHASE[256] 'UWPHASE[ ] holds the unwrapped phase
140 '
150 PI = 3.14159265
160 '
170 GOSUB XXXX 'Mythical subroutine to load data into PHASE[ ]
180 '
190 UWPHASE[0] = 0 'The first point of all phase signals is zero
200 '
210 ' 'Go through the unwrapping algorithm
220 FOR K% = 1 TO 256
230 C% = CINT( (UWPHASE[K%-1] - PHASE[K%]) / (2 * PI) )
240 UWPHASE[K%] = PHASE[K%] + C%*2*PI
250 NEXT K%
260 '
270 END
TABLE 8-4
example, a phase shift of q is exactly the same as a phase shift of q + 2p , q + 4p ,
q + 6p , etc. Any sinusoid is unchanged when you add an integer multiple of
2B to the phase. The apparent discontinuities in the signal are a result of the
computer algorithm picking its favorite choice from an infinite number of
equivalent possibilities. The smallest possible value is always chosen, keeping
the phase between -B and B.
It is often easier to understand the phase if it does not have these
discontinuities, even if it means that the phase extends above B, or below -B.
This is called unwrapping the phase, and an example is shown in Fig. 8-12.
As shown by the program in Table 8-4, a multiple of 2B is added or subtracted
from each value of the phase. The exact value is determined by an algorithm
that minimizes the difference between adjacent samples.
Nuisance 6: The magnitude is always positive (B ambiguity of the phase)
Figure 8-13 shows a frequency domain signal in rectangular and polar form.
The real part is smooth and quite easy to understand, while the imaginary
part is entirely zero. In comparison, the polar signals contain abrupt
168 The Scientist and Engineer's Guide to Digital Signal Processing
Frequency
0 0.1 0.2 0.3 0.4 0.5
-1
0
1
2
3
a. Re X[ ]
Frequency
0 0.1 0.2 0.3 0.4 0.5
-1
0
1
2
3
c. Mag X[ ]
Frequency
0 0.1 0.2 0.3 0.4 0.5
-5
-4
-3
-2
-1
0
1
2
3
4
5
d. Phase X[ ]
Rectangular Polar
FIGURE 8-13
Example signals in rectangular and polar form. Since the magnitude must always be positive (by definition),
the magnitude and phase may contain abrupt discontinuities and sharp corners. Figure (d) also shows
another nuisance: random noise can cause the phase to rapidly oscillate between B or -B.
Frequency
0 0.1 0.2 0.3 0.4 0.5
-3
-2
-1
0
1
2
3
b. Im X[ ]
Amplitude
Amplitude Amplitude
Phase (radians)
discontinuities and sharp corners. This is because the magnitude must always
be positive, by definition. Whenever the real part dips below zero, the
magnitude remains positive by changing the phase by B (or -B, which is the
same thing). While this is not a problem for the mathematics, the irregular
curves can be difficult to interpret.
One solution is to allow the magnitude to have negative values. In the example
of Fig. 8-13, this would make the magnitude appear the same as the real part,
while the phase would be entirely zero. There is nothing wrong with this if it
helps your understanding. Just be careful not to call a signal with negative
values the "magnitude" since this violates its formal definition. In this book we
use the weasel words: unwrapped magnitude to indicate a "magnitude" that is
allowed to have negative values.
Nuisance 7: Spikes between B and -B
Since B and -B represent the same phase shift, round-off noise can cause
adjacent points in the phase to rapidly switch between the two values. As
shown in Fig. 8-13d, this can produce sharp breaks and spikes in an otherwise
smooth curve. Don't be fooled, the phase isn't really this discontinuous.
Low Power, 12.65 mW, 2.3 V to 5.5 V,
Programmable Waveform Generator
Data Sheet AD9833
Rev. E Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2012 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Digitally programmable frequency and phase
12.65 mW power consumption at 3 V
0 MHz to 12.5 MHz output frequency range
28-bit resolution: 0.1 Hz at 25 MHz reference clock
Sinusoidal, triangular, and square wave outputs
2.3 V to 5.5 V power supply
No external components required
3-wire SPI interface
Extended temperature range: −40°C to +105°C
Power-down option
10-lead MSOP package
Qualified for automotive applications
APPLICATIONS
Frequency stimulus/waveform generation
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect detection
Line loss/attenuation
Test and medical equipment
Sweep/clock generators
Time domain reflectometry (TDR) applications
GENERAL DESCRIPTION
The AD9833 is a low power, programmable waveform generator capable of producing sine, triangular, and square wave outputs. Waveform generation is required in various types of sensing, actuation, and time domain reflectometry (TDR) applications. The output frequency and phase are software programmable, allowing easy tuning. No external components are needed. The frequency registers are 28 bits wide: with a 25 MHz clock rate, resolution of 0.1 Hz can be achieved; with a 1 MHz clock rate, the AD9833 can be tuned to 0.004 Hz resolution.
The AD9833 is written to via a 3-wire serial interface. This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards. The device operates with a power supply from 2.3 V to 5.5 V.
The AD9833 has a power-down function (SLEEP). This function allows sections of the device that are not being used to be powered down, thus minimizing the current consumption of the part. For example, the DAC can be powered down when a clock output is being generated.
The AD9833 is available in a 10-lead MSOP package.
FUNCTIONAL BLOCK DIAGRAM
SERIAL INTERFACEANDCONTROL LOGICSCLKSDATAFSYNCCONTROL REGISTERPHASE1 REGPHASE0 REGMUXSINROM10-BITDACMUXFREQ0 REGFREQ1 REG12ON-BOARDREFERENCEAGNDDGNDVDDAD9833PHASEACCUMULATOR(28-BIT)REGULATORCAP/2.5V2.5VAVDD/DVDDMUXDIVIDEBY 2MSBMUXFULL-SCALECONTROLCOMPVOUTR200ΩMCLK02704-001
Figure 1.
AD9833 Data Sheet
Rev. E | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Terminology .................................................................................... 10
Theory of Operation ...................................................................... 11
Circuit Description ......................................................................... 12
Numerically Controlled Oscillator Plus Phase Modulator ... 12
Sin ROM ...................................................................................... 12
Digital-to-Analog Converter (DAC) ....................................... 12
Regulator...................................................................................... 12
Functional Description .................................................................. 13
Serial Interface ............................................................................ 13
Powering Up the AD9833 ......................................................... 13
Latency Period ............................................................................ 13
Control Register ......................................................................... 13
Frequency and Phase Registers ................................................ 15
Reset Function ............................................................................ 16
Sleep Function ............................................................................ 16
VOUT Pin ................................................................................... 16
Applications Information .............................................................. 17
Grounding and Layout .............................................................. 17
Interfacing to Microprocessors ..................................................... 20
AD9833 to 68HC11/68L11 Interface ....................................... 20
AD9833 to 80C51/80L51 Interface .......................................... 20
AD9833 to DSP56002 Interface ............................................... 20
Evaluation Board ............................................................................ 21
System Demonstration Platform .............................................. 21
AD9833 to SPORT Interface ..................................................... 21
Evaluation Kit ............................................................................. 21
Crystal Oscillator vs. External Clock ....................................... 21
Power Supply ............................................................................... 21
Evaluation Board Schematics ................................................... 22
Evaluation Board Layout ........................................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
Automotive Products ................................................................. 24
REVISION HISTORY
9/12—Rev. D to Rev. E
Changed Input Current, IINH/IINL from 10 mA to 10 μA.............. 3
4/11—Rev. C to Rev. D
Change to Figure 13 ......................................................................... 8
Changes to Table 9 .......................................................................... 15
Deleted AD9833 to ADSP-2101/ADSP-2103 Interface Section .............................................................................................. 20
Changes to Evaluation Board Section .......................................... 21
Added System Demonstration Platform Section, AD9833 to SPORT Interface Section, and Evaluation Kit Section .......... 21
Changes to Crystal Oscillator vs. External Clock Section and Power Supply Section ............................................................. 21
Added Figure 32 and Figure 33; Renumbered Figures Sequentially ..................................................................................... 21
Deleted Prototyping Area Section and Figure 33 ....................... 22
Added Evaluation Board Schematics Section, Figure 34, and Figure 35 ................................................................................... 22
Deleted Table 16 .............................................................................. 23
Added Evaluation Board Layout Section, Figure 36, Figure 37, and Figure 38 ................................................................ 23
Changes to Ordering Guide .......................................................... 24
9/10—Rev. B to Rev. C
Changed 20 mW to 12.65 mW in Data Sheet Title and Features List ................................................................................ 1
Changes to Figure 6 Caption and Figure 7..................................... 7
6/10—Rev. A to Rev. B
Changes to Features Section ............................................................ 1
Changes to Serial Interface Section.............................................. 13
Changes to VOUT Pin Section ..................................................... 16
Changes to Grounding and Layout Section ................................ 17
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
Added Automotive Products Section .......................................... 24
6/03—Rev. 0 to Rev. A
Updated Ordering Guide ................................................................. 4
Data Sheet AD9833
Rev. E | Page 3 of 24
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 kΩ for VOUT, unless otherwise noted.
Table 1.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution
10
Bits
Update Rate
25
MSPS
VOUT Maximum
0.65
V
VOUT Minimum
38
mV
VOUT Temperature Coefficient
200
ppm/°C
DC Accuracy
Integral Nonlinearity
±1.0
LSB
Differential Nonlinearity
±0.5
LSB
DDS SPECIFICATIONS (SFDR)
Dynamic Specifications
Signal-to-Noise Ratio (SNR)
55
60
dB
fMCLK = 25 MHz, fOUT = fMCLK/4096
Total Harmonic Distortion (THD)
−66
−56
dBc
fMCLK = 25 MHz, fOUT = fMCLK/4096
Spurious-Free Dynamic Range (SFDR)
Wideband (0 to Nyquist)
−60
dBc
fMCLK = 25 MHz, fOUT = fMCLK/50
Narrow-Band (±200 kHz)
−78
dBc
fMCLK = 25 MHz, fOUT = fMCLK/50
Clock Feedthrough
−60
dBc
Wake-Up Time
1
ms
LOGIC INPUTS
Input High Voltage, VINH
1.7
V
2.3 V to 2.7 V power supply
2.0
V
2.7 V to 3.6 V power supply
2.8
V
4.5 V to 5.5 V power supply
Input Low Voltage, VINL
0.5
V
2.3 V to 2.7 V power supply
0.7
V
2.7 V to 3.6 V power supply
0.8
V
4.5 V to 5.5 V power supply
Input Current, IINH/IINL
10
μA
Input Capacitance, CIN
3
pF
POWER SUPPLIES
fMCLK = 25 MHz, fOUT = fMCLK/4096
VDD
2.3
5.5
V
IDD
4.5
5.5
mA
IDD code dependent; see Figure 7
Low Power Sleep Mode
0.5
mA
DAC powered down, MCLK running
1 Operating temperature range is −40°C to +105°C; typical specifications are at 25°C.
VOUTCOMP12AD983310-BIT DACSINROM20pF10nFVDDREGULATOR100nFCAP/2.5V02704-002
Figure 2. Test Circuit Used to Test Specifications
AD9833 Data Sheet
Rev. E | Page 4 of 24
TIMING CHARACTERISTICS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.1
Table 2.
Parameter
Limit at TMIN to TMAX
Unit
Description
t1
40
ns min
MCLK period
t2
16
ns min
MCLK high duration
t3
16
ns min
MCLK low duration
t4
25
ns min
SCLK period
t5
10
ns min
SCLK high duration
t6
10
ns min
SCLK low duration
t7
5
ns min
FSYNC to SCLK falling edge setup time
t8 min
10
ns min
FSYNC to SCLK hold time
t8 max
t4 − 5
ns max
t9
5
ns min
Data setup time
t10
3
ns min
Data hold time
t11
5
ns min
SCLK high to FSYNC falling edge setup time
1 Guaranteed by design, not production tested.
Timing Diagrams
t2t1MCLKt302704-003
Figure 3. Master Clock
t5t4t6t7t8t10t941D51DD0D1D2D14SCLKFSYNCSDATAD15t1102704-004
Figure 4. Serial Timing
Data Sheet AD9833
Rev. E | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Rating
VDD to AGND
−0.3 V to +6 V
VDD to DGND
−0.3 V to +6 V
AGND to DGND
−0.3 V to +0.3 V
CAP/2.5V
2.75 V
Digital I/O Voltage to DGND
−0.3 V to VDD + 0.3 V
Analog I/O Voltage to AGND
−0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version)
−40°C to +105°C
Storage Temperature Range
−65°C to +150°C
Maximum Junction Temperature
150°C
MSOP Package
θJA Thermal Impedance
206°C/W
θJC Thermal Impedance
44°C/W
Lead Temperature, Soldering (10 sec)
300°C
IR Reflow, Peak Temperature
220°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
AD9833 Data Sheet
Rev. E | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COMP1VDD2CAP/2.5V3DGND4MCLK5VOUT10AGND9FSYNC8SCLK7SDATA6AD9833TOP VIEW(Not to Scale)02704-005
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
COMP
DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
2
VDD
Positive Power Supply for the Analog and Digital Interface Sections. The on-board 2.5 V regulator is also supplied from VDD. VDD can have a value from 2.3 V to 5.5 V. A 0.1 μF and a 10 μF decoupling capacitor should be connected between VDD and AGND.
3
CAP/2.5V
The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from VDD using an on-board regulator when VDD exceeds 2.7 V. The regulator requires a decoupling capacitor of 100 nF typical, which is connected from CAP/2.5V to DGND. If VDD is less than or equal to 2.7 V, CAP/2.5V should be tied directly to VDD.
4
DGND
Digital Ground.
5
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock.
6
SDATA
Serial Data Input. The 16-bit serial data-word is applied to this input.
7
SCLK
Serial Clock Input. Data is clocked into the AD9833 on each falling edge of SCLK.
8
FSYNC
Active Low Control Input. FSYNC is the frame synchronization signal for the input data. When FSYNC is taken low, the internal logic is informed that a new word is being loaded into the device.
9
AGND
Analog Ground.
10
VOUT
Voltage Output. The analog and digital output from the AD9833 is available at this pin. An external load resistor is not required because the device has a 200 Ω resistor on board.
Data Sheet AD9833
Rev. E | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
MCLK FREQUENCY (MHz)IDD (mA)5.55.03.03.54.04.50510152025TA = 25°C02704-006VDD = 5VVDD = 3V
Figure 6. Typical Current Consumption (IDD) vs. MCLK Frequency for fOUT = MCLK/10
01234561001k10k100k1M10MIDD (
mA)fOUT (Hz)VDD = 5VVDD = 3V02704-007
Figure 7. Typical IDD vs. fOUT for fMCLK = 25 MHz
0510152025MCLK FREQUENCY (MHz)SFDR (dBc)–65–60–90–70–75–80–85MCLK/7MCLK/50VDD = 3VTA= 25°C02704-008
Figure 8. Narrow-Band SFDR vs. MCLK Frequency
–45–40–705791113151719212325–50–55–60–65MCLK FREQUENCY (MHz)SFDR (dBc)MCLK/7MCLK/50VDD = 3VTA= 25°C02704-009
Figure 9. Wideband SFDR vs. MCLK Frequency
fOUT/fMCLK–30–90–80–70–60–50–40SFDR (
dB)0–20–10fMCLK =1MHzfMCLK =10MHz0.0010.010.1110100fMCLK =25MHzVDD = 3VTA= 25°C02704-010fMCLK =18MHz
Figure 10. Wideband SFDR vs. fOUT/fMCLK for Various MCLK Frequencies
MCLK FREQUENCY (MHz)1.05.010.012.525.0SNR (
dB)–60–65–70–50–55–40–45VDD = 3VTA= 25°CfOUT= MCLK/409602704-011
Figure 11. SNR vs. MCLK Frequency
AD9833 Data Sheet
Rev. E | Page 8 of 24
5001000700650600550850750800900950–4025105TEMPERATURE (°C)WAKE-UP TIME (μs)VDD = 5.5V02704-012VDD = 2.3V
Figure 12. Wake-Up Time vs. Temperature
–4025105TEMPERATURE (°C)VREF (V)LOWER RANGEUPPER RANGE1.1501.1251.1001.1751.2001.2501.22502704-013
Figure 13. VREF vs. Temperature
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–100100kRWB 100ST 100 SECVWB 3002704-014
Figure 14. Power vs. Frequency, fMCLK = 10 MHz, fOUT = 2.4 kHz, Frequency Word = 0x000FBA9
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–1005MRWB 1kST 50 SECVWB 30002704-015
Figure 15. Power vs. Frequency, fMCLK = 10 MHz, fOUT = 1.43 MHz = fMCLK/7, Frequency Word = 0x2492492
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–1005MRWB 1kST 50 SECVWB 30002704-016
Figure 16. Power vs. Frequency, fMCLK = 10 MHz, fOUT = 3.33 MHz = fMCLK/3, Frequency Word = 0x5555555
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–100100kRWB 100ST 100 SECVWB 3002704-017
Figure 17. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 6 kHz, Frequency Word = 0x000FBA9
Data Sheet AD9833
Rev. E | Page 9 of 24
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–1001MRWB 300ST 100 SECVWB 10002704-018
Figure 18. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 60 kHz, Frequency Word = 0x009D495
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–10012.5MRWB 1kST 100 SECVWB 30002704-019
Figure 19. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 600 kHz, Frequency Word = 0x0624DD3
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–10012.5MRWB 1kST 100 SECVWB 30002704-020
Figure 20. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 2.4 MHz, Frequency Word = 0x189374D
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–10012.5MRWB 1kST 100 SECVWB 30002704-021
Figure 21. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 3.857 MHz = fMCLK/7, Frequency Word = 0x2492492
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–10012.5MRWB 1kST 100 SECVWB 30002704-022
Figure 22. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 8.333 MHz = fMCLK/3, Frequency Word = 0x5555555
AD9833 Data Sheet
Rev. E | Page 10 of 24
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The end-points of the transfer function are zero scale, a point 0.5 LSB below the first code transition (000 … 00 to 000 … 01), and full scale, a point 0.5 LSB above the last code transition (111 … 10 to 111 … 11). The error is expressed in LSBs.
Differential Nonlinearity (DNL)
DNL is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC. A specified DNL of ±1 LSB maximum ensures monotonicity.
Output Compliance
Output compliance refers to the maximum voltage that can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the output compli-ance are generated, the AD9833 may not meet the specifications listed in the data sheet.
Spurious-Free Dynamic Range (SFDR)
Along with the frequency of interest, harmonics of the funda-mental frequency and images of these frequencies are present at the output of a DDS device. SFDR refers to the largest spur or harmonic present in the band of interest. The wideband SFDR gives the magnitude of the largest spur or harmonic relative to the magnitude of the fundamental frequency in the zero to Nyquist bandwidth. The narrow-band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of ±200 kHz about the fundamental frequency.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD9833, THD is defined as
12625242322log20THDVVVVVV++++=
where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through sixth harmonics.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in decibels.
Clock Feedthrough
There is feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the output spectrum of the AD9833.
Data Sheet AD9833
Rev. E | Page 11 of 24 THEORY OF OPERATION
Sine waves are typically thought of in terms of their magnitude form: a(t) = sin(ωt). However, these sine waves are nonlinear and not easy to generate except through piecewise construction. On the other hand, the angular information is linear in nature. That
is, the phase angle rotates through a fixed angle for each unit of
time. The angular rate depends on the frequency of the signal
by the traditional rate of ω = 2πf.
MAGNITUDE
PHASE
+1
0
–1
2p
0
2π 4π
6π
2π 4π 6π
02704-023
Figure 23. Sine Wave
Knowing that the phase of a sine wave is linear and given a
reference interval (clock period), the phase rotation for that period can be determined.
ΔPhase = ωΔt
Solving for ω, ω = ΔPhase/Δt = 2πf
Solving for f and substituting the reference clock frequency for the reference period (1/fMCLK = Δt)
f = ΔPhase × fMCLK∕2π
The AD9833 builds the output based on this simple equation. A
simple DDS chip can implement this equation with three major
subcircuits: numerically controlled oscillator (NCO) and phase
modulator, SIN ROM, and digital-to-analog converter (DAC). Each subcircuit is described in the Circuit Description section.
AD9833 Data Sheet
Rev. E | Page 12 of 24
CIRCUIT DESCRIPTION
The AD9833 is a fully integrated direct digital synthesis (DDS) chip. The chip requires one reference clock, one low precision resistor, and decoupling capacitors to provide digitally created sine waves up to 12.5 MHz. In addition to the generation of this RF signal, the chip is fully capable of a broad range of simple and complex modulation schemes. These modulation schemes are fully implemented in the digital domain, allowing accurate and simple realization of complex modulation algorithms using DSP techniques.
The internal circuitry of the AD9833 consists of the following main sections: a numerically controlled oscillator (NCO), frequency and phase modulators, SIN ROM, a DAC, and a regulator.
NUMERICALLY CONTROLLED OSCILLATOR PLUS PHASE MODULATOR
This consists of two frequency select registers, a phase accumulator, two phase offset registers, and a phase offset adder. The main component of the NCO is a 28-bit phase accumulator. Continuous time signals have a phase range of 0 to 2π. Outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. The digital implementation is no different. The accumulator simply scales the range of phase numbers into a multibit digital word. The phase accumulator in the AD9833 is implemented with 28 bits. Therefore, in the AD9833, 2π = 228. Likewise, the ΔPhase term is scaled into this range of numbers:
0 < ΔPhase < 228 − 1
With these substitutions, the previous equation becomes
f = ΔPhase × fMCLK∕228
where 0 < ΔPhase < 228 − 1.
The input to the phase accumulator can be selected from either the FREQ0 register or the FREQ1 register and is controlled by the FSELECT bit. NCOs inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies.
Following the NCO, a phase offset can be added to perform phase modulation using the 12-bit phase registers. The contents of one of these phase registers are added to the most significant bits of the NCO. The AD9833 has two phase registers; their resolution is 2π/4096.
SIN ROM
To make the output from the NCO useful, it must be converted from phase information into a sinusoidal value. Because phase information maps directly into amplitude, the SIN ROM uses the digital phase information as an address to a lookup table and converts the phase information into amplitude. Although the NCO contains a 28-bit phase accumulator, the output of the NCO is truncated to 12 bits. Using the full resolution of the phase accumulator is impractical and unnecessary, because this would require a lookup table of 228 entries. It is necessary only to have sufficient phase resolution such that the errors due to truncation are smaller than the resolution of the 10-bit DAC. This requires that the SIN ROM have two bits of phase resolution more than the 10-bit DAC.
The SIN ROM is enabled using the mode bit (D1) in the control register (see Table 15).
DIGITAL-TO-ANALOG CONVERTER (DAC)
The AD9833 includes a high impedance, current source 10-bit DAC. The DAC receives the digital words from the SIN ROM and converts them into the corresponding analog voltages.
The DAC is configured for single-ended operation. An external load resistor is not required because the device has a 200 Ω resistor on board. The DAC generates an output voltage of typically 0.6 V p-p.
REGULATOR
VDD provides the power supply required for the analog section and the digital section of the AD9833. This supply can have a value of 2.3 V to 5.5 V.
The internal digital section of the AD9833 is operated at 2.5 V. An on-board regulator steps down the voltage applied at VDD to 2.5 V. When the applied voltage at the VDD pin of the AD9833 is less than or equal to 2.7 V, the CAP/2.5V and VDD pins should be tied together, thus bypassing the on-board regulator.
Data Sheet AD9833
Rev. E | Page 13 of 24
FUNCTIONAL DESCRIPTION
SERIAL INTERFACE
The AD9833 has a standard 3-wire serial interface that is compatible with the SPI, QSPI™, MICROWIRE®, and DSP interface standards.
Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is given in .
The FSYNC input is a level-triggered input that acts as a frame synchronization and chip enable. Data can be transferred into the device only when FSYNC is low. To start the serial data transfer, FSYNC should be taken low, observing the minimum FSYNC-to-SCLK falling edge setup time, t7. After FSYNC goes low, serial data is shifted into the input shift register of the device on the falling edges of SCLK for 16 clock pulses. FSYNC may be taken high after the 16th falling edge of SCLK, observing the minimum SCLK falling edge to FSYNC rising edge time, t8. Alternatively, FSYNC can be kept low for a multiple of 16 SCLK pulses and then brought high at the end of the data transfer. In this way, a continuous stream of 16-bit words can be loaded while FSYNC is held low; FSYNC goes high only after the 16th SCLK falling edge of the last word loaded.
The SCLK can be continuous, or it can idle high or low between write operations. In either case, it must be high when FSYNC goes low (t11).
For an example of how to program the AD9833, see the AN-1070 Application Note on the Analog Devices, Inc., website.
POWERING UP THE AD9833
The flowchart in Figure 26 shows the operating routine for the AD9833. When the AD9833 is powered up, the part should be reset. This resets the appropriate internal registers to 0 to provide an analog output of midscale.
To avoid spurious DAC outputs during AD9833 initialization, the reset bit should be set to 1 until the part is ready to begin generating an output. A reset does not reset the phase, frequency, or control registers. These registers will contain invalid data and, therefore, should be set to known values by the user. The reset bit should then be set to 0 to begin generating an output. The data appears on the DAC output seven or eight MCLK cycles after the reset bit is set to 0.
LATENCY PERIOD
A latency period is associated with each asynchronous write operation in the AD9833. If a selected frequency or phase register is loaded with a new word, there is a delay of seven or eight MCLK cycles before the analog output changes. The delay can be seven or eight cycles, depending on the position of the MCLK rising edge when the data is loaded into the destination register.
CONTROL REGISTER
The AD9833 contains a 16-bit control register that allows the user to configure the operation of the AD9833. All control bits other than the mode bit are sampled on the internal falling edge of MCLK.
Table 6 describes the individual bits of the control register. The different functions and the various output options of the AD9833 are described in more detail in the Frequency and Phase Registers section.
To inform the AD9833 that the contents of the control register will be altered, D15 and D14 must be set to 0, as shown in Table 5.
Table 5. Control Register Bits
D15
D14
D13
D0
0
0
Control Bits
SINROMPHASEACCUMULATOR(28-BIT)AD9833(LOW POWER)10-BIT DAC0MUX1SLEEP12SLEEP1RESETMODE + OPBITENDIV2OPBITENVOUT1MUX0DIGITALOUTPUT(ENABLE)DIVIDEBY 2DB150DB140DB13B28DB12HLBDB11FSELECTDB10PSELECTDB90DB8RESETDB7SLEEP1DB6SLEEP12DB5OPBITENDB40DB3DIV2DB20DB1MODEDB0002704-024
Figure 24. Function of Control Bits
AD9833 Data Sheet
Rev. E | Page 14 of 24
Table 6. Description of Bits in the Control Register
Bit
Name
Function
D13
B28
Two write operations are required to load a complete word into either of the frequency registers. B28 = 1 allows a complete word to be loaded into a frequency register in two consecutive writes. The first write contains the 14 LSBs of the frequency word, and the next write contains the 14 MSBs. The first two bits of each 16-bit word define the frequency register to which the word is loaded and should, therefore, be the same for both of the consecutive writes. See Table 8 for the appropriate addresses. The write to the frequency register occurs after both words have been loaded; therefore, the register never holds an intermediate value. An example of a complete 28-bit write is shown in Table 9. When B28 = 0, the 28-bit frequency register operates as two 14-bit registers, one containing the 14 MSBs and the other containing the 14 LSBs. This means that the 14 MSBs of the frequency word can be altered independent of the 14 LSBs, and vice versa. To alter the 14 MSBs or the 14 LSBs, a single write is made to the appropriate frequency address. The control bit D12 (HLB) informs the AD9833 whether the bits to be altered are the 14 MSBs or 14 LSBs.
D12
HLB
This control bit allows the user to continuously load the MSBs or LSBs of a frequency register while ignoring the remaining 14 bits. This is useful if the complete 28-bit resolution is not required. HLB is used in conjunction with D13 (B28). This control bit indicates whether the 14 bits being loaded are being transferred to the 14 MSBs or 14 LSBs of the addressed frequency register. D13 (B28) must be set to 0 to be able to change the MSBs and LSBs of a frequency word separately. When D13 (B28) = 1, this control bit is ignored. HLB = 1 allows a write to the 14 MSBs of the addressed frequency register. HLB = 0 allows a write to the 14 LSBs of the addressed frequency register.
D11
FSELECT
The FSELECT bit defines whether the FREQ0 register or the FREQ1 register is used in the phase accumulator.
D10
PSELECT
The PSELECT bit defines whether the PHASE0 register or the PHASE1 register data is added to the output of the phase accumulator.
D9
Reserved
This bit should be set to 0.
D8
Reset
Reset = 1 resets internal registers to 0, which corresponds to an analog output of midscale. Reset = 0 disables reset. This function is explained further in Table 13.
D7
SLEEP1
When SLEEP1 = 1, the internal MCLK clock is disabled, and the DAC output remains at its present value because the NCO is no longer accumulating. When SLEEP1 = 0, MCLK is enabled. This function is explained further in Table 14.
D6
SLEEP12
SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9833 is used to output the MSB of the DAC data.
SLEEP12 = 0 implies that the DAC is active. This function is explained further in Table 14.
D5
OPBITEN
The function of this bit, in association with D1 (mode), is to control what is output at the VOUT pin. This is explained further in Table 15. When OPBITEN = 1, the output of the DAC is no longer available at the VOUT pin. Instead, the MSB (or MSB/2) of the DAC data is connected to the VOUT pin. This is useful as a coarse clock source. The DIV2 bit controls whether it is the MSB or MSB/2 that is output. When OPBITEN = 0, the DAC is connected to VOUT. The mode bit determines whether it is a sinusoidal or a ramp output that is available.
D4
Reserved
This bit must be set to 0.
D3
DIV2
DIV2 is used in association with D5 (OPBITEN). This is explained further in Table 15. When DIV2 = 1, the MSB of the DAC data is passed directly to the VOUT pin. When DIV2 = 0, the MSB/2 of the DAC data is output at the VOUT pin.
D2
Reserved
This bit must be set to 0.
D1
Mode
This bit is used in association with OPBITEN (D5). The function of this bit is to control what is output at the VOUT pin when the on-chip DAC is connected to VOUT. This bit should be set to 0 if the control bit OPBITEN = 1. This is explained further in Table 15. When mode = 1, the SIN ROM is bypassed, resulting in a triangle output from the DAC. When mode = 0, the SIN ROM is used to convert the phase information into amplitude information, which results in a sinusoidal signal at the output.
D0
Reserved
This bit must be set to 0.
Data Sheet AD9833
Rev. E | Page 15 of 24 FREQUENCY AND PHASE REGISTERS
The AD9833 contains two frequency registers and two phase
registers, which are described in Table 7. Table 7. Frequency and Phase Registers
Register Size Description FREQ0 28 bits Frequency Register 0. When the FSELECT
bit = 0, this register defines the output
frequency as a fraction of the MCLK
frequency.
FREQ1 28 bits Frequency Register 1. When the FSELECT
bit = 1, this register defines the output
frequency as a fraction of the MCLK
frequency.
PHASE0 12 bits Phase Offset Register 0. When the PSELECT
bit = 0, the contents of this register are
added to the output of the phase
accumulator. PHASE1 12 bits Phase Offset Register 1. When the PSELECT
bit = 1, the contents of this register are
added to the output of the phase
accumulator. The analog output from the AD9833 is
fMCLK/228 × FREQREG
where FREQREG is the value loaded into the selected frequency
register. This signal is phase shifted by 2π/4096 × PHASEREG where PHASEREG is the value contained in the selected phase register. Consideration must be given to the relationship of the
selected output frequency and the reference clock frequency to avoid unwanted output anomalies. The flowchart in Figure 28 shows the routine for writing to the
frequency and phase registers of the AD9833. Writing to a Frequency Register
When writing to a frequency register, Bit D15 and Bit D14 give
the address of the frequency register.
Table 8. Frequency Register Bits
D15 D14 D13 D0
0 1 MSB 14 FREQ0 REG bits LSB
1 0 MSB 14 FREQ1 REG bits LSB
If the user wants to change the entire contents of a frequency
register, two consecutive writes to the same address must be
performed because the frequency registers are 28 bits wide. The
first write contains the 14 LSBs, and the second write contains the 14 MSBs. For this mode of operation, the B28 (D13) control
bit should be set to 1. An example of a 28-bit write is shown in Table 9. Table 9. Writing 0xFFFC000 to the FREQ0 Register SDATA Input Result of Input Word 0010 0000 0000 0000 Control word write (D15, D14 = 00), B28 (D13) = 1, HLB (D12) = X 0100 0000 0000 0000 FREQ0 register write
(D15, D14 = 01), 14 LSBs = 0x0000
0111 1111 1111 1111 FREQ0 register write
(D15, D14 = 01), 14 MSBs = 0x3FFF
In some applications, the user does not need to alter all 28 bits
of the frequency register. With coarse tuning, only the 14 MSBs
are altered, while with fine tuning, only the 14 LSBs are altered.
By setting the B28 (D13) control bit to 0, the 28-bit frequency
register operates as two, 14-bit registers, one containing the 14 MSBs
and the other containing the 14 LSBs. This means that the 14 MSBs of the frequency word can be altered independent of the 14 LSBs,
and vice versa. Bit HLB (D12) in the control register identifies
which 14 bits are being altered. Examples of this are shown in
Table 10 and Table 11. Table 10. Writing 0x3FFF to the 14 LSBs of the FREQ1 Register SDATA Input Result of Input Word 0000 0000 0000 0000 Control word write (D15, D14 = 00), B28 (D13) = 0; HLB (D12) = 0, that is, LSBs
1011 1111 1111 1111 FREQ1 REG write (D15, D14 = 10), 14 LSBs = 0x3FFF
Table 11. Writing 0x00FF to the 14 MSBs of the FREQ0 Register SDATA Input Result of Input Word 0001 0000 0000 0000 Control word write (D15, D14 = 00),
B28 (D13) = 0, HLB (D12) = 1, that is, MSBs 0100 0000 1111 1111 FREQ0 REG write (D15, D14 = 01), 14 MSBs = 0x00FF
Writing to a Phase Register
When writing to a phase register, Bit D15 and Bit D14 are set to 11.
Bit D13 identifies which phase register is being loaded. Table 12. Phase Register Bits
D15 D14 D13 D12 D11 D0
1 1 0 X MSB 12 PHASE0 bits LSB
1 1 1 X MSB 12 PHASE1 bits LSB
AD9833 Data Sheet
Rev. E | Page 16 of 24
RESET FUNCTION
The reset function resets appropriate internal registers to 0 to provide an analog output of midscale. Reset does not reset the phase, frequency, or control registers. When the AD9833 is powered up, the part should be reset. To reset the AD9833, set the reset bit to 1. To take the part out of reset, set the bit to 0. A signal appears at the DAC to output eight MCLK cycles after reset is set to 0.
Table 13. Applying the Reset Function
Reset Bit
Result
0
No reset applied
1
Internal registers reset
SLEEP FUNCTION
Sections of the AD9833 that are not in use can be powered down to minimize power consumption. This is done using the sleep function. The parts of the chip that can be powered down are the internal clock and the DAC. The bits required for the sleep function are outlined in Table 14.
Table 14. Applying the Sleep Function
SLEEP1 Bit
SLEEP12 Bit
Result
0
0
No power-down
0
1
DAC powered down
1
0
Internal clock disabled
1
1
Both the DAC powered down and the internal clock disabled
DAC Powered Down
This is useful when the AD9833 is used to output the MSB of the DAC data only. In this case, the DAC is not required; therefore, it can be powered down to reduce power consumption.
Internal Clock Disabled
When the internal clock of the AD9833 is disabled, the DAC output remains at its present value because the NCO is no longer accumulating. New frequency, phase, and control words can be written to the part when the SLEEP1 control bit is active. The synchronizing clock is still active, which means that the selected frequency and phase registers can also be changed using the control bits. Setting the SLEEP1 bit to 0 enables the MCLK. Any changes made to the registers while SLEEP1 is active will be seen at the output after a latency period.
VOUT PIN
The AD9833 offers a variety of outputs from the chip, all of which are available from the VOUT pin. The choice of outputs is the MSB of the DAC data, a sinusoidal output, or a triangle output.
The OPBITEN (D5) and mode (D1) bits in the control register are used to decide which output is available from the AD9833.
MSB of the DAC Data
The MSB of the DAC data can be output from the AD9833. By setting the OPBITEN (D5) control bit to 1, the MSB of the DAC data is available at the VOUT pin. This is useful as a coarse clock source. This square wave can also be divided by 2 before being output. The DIV2 (D3) bit in the control register controls the frequency of this output from the VOUT pin.
Sinusoidal Output
The SIN ROM is used to convert the phase information from the frequency and phase registers into amplitude information that results in a sinusoidal signal at the output. To have a sinusoidal output from the VOUT pin, set the mode (D1) bit to 0 and the OPBITEN (D5) bit to 0.
Triangle Output
The SIN ROM can be bypassed so that the truncated digital output from the NCO is sent to the DAC. In this case, the output is no longer sinusoidal. The DAC will produce a 10-bit linear triangular function. To have a triangle output from the VOUT pin, set the mode (D1) bit = 1.
Note that the SLEEP12 bit must be 0 (that is, the DAC is enabled) when using this pin.
Table 15. Outputs from the VOUT Pin
OPBITEN Bit
Mode Bit
DIV2 Bit
VOUT Pin
0
0
X1
Sinusoid
0
1
X1
Triangle
1
0
0
DAC data MSB/2
1
0
1
DAC data MSB
1
1
X1
Reserved
1 X = don’t care.
VOUT MINVOUT MAX2π4π6π02704-025
Figure 25. Triangle Output
Data Sheet AD9833
Rev. E | Page 17 of 24
APPLICATIONS INFORMATION
Because of the various output options available from the part, the AD9833 can be configured to suit a wide variety of applications.
One of the areas where the AD9833 is suitable is in modulation applications. The part can be used to perform simple modulation, such as FSK. More complex modulation schemes, such as GMSK and QPSK, can also be implemented using the AD9833.
In an FSK application, the two frequency registers of the AD9833 are loaded with different values. One frequency represents the space frequency, while the other represents the mark frequency. Using the FSELECT bit in the control register of the AD9833, the user can modulate the carrier frequency between the two values.
The AD9833 has two phase registers, which enables the part to perform PSK. With phase-shift keying, the carrier frequency is phase shifted, the phase being altered by an amount that is related to the bit stream being input to the modulator.
The AD9833 is also suitable for signal generator applications. Because the MSB of the DAC data is available at the VOUT pin, the device can be used to generate a square wave.
With its low current consumption, the part is suitable for applications in which it can be used as a local oscillator.
GROUNDING AND LAYOUT
The printed circuit board (PCB) that houses the AD9833 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes because it gives the best shielding. Digital and analog ground planes should be joined in one place only. If the AD9833 is the only device requiring an AGND-to-DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD9833. If the AD9833 is in a system where multiple devices require AGND-to-DGND connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD9833.
Avoid running digital lines under the device as these couple noise onto the die. The analog ground plane should be allowed to run under the AD9833 to avoid noise coupling. The power supply lines to the AD9833 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board.
Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the other side.
Good decoupling is important. The AD9833 should have supply bypassing of 0.1 μF ceramic capacitors in parallel with 10 μF tantalum capacitors. To achieve the best performance from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device.
AD9833 Data Sheet
Rev. E | Page 18 of 24
DATA WRITE(SEE FIGURE 28)SELECT DATASOURCESWAIT 7/8 MCLKCYCLESVOUT = VREF × 18 × RLOAD/ RSET× (1 + (SIN (2π (FREQREG ×fMCLK×t/228 + PHASEREG / 212))))DAC OUTPUTCHANGE PHASE?CHANGE FREQUENCY?CHANGE DAC OUTPUTFROM SIN TO RAMP?CHANGE OUTPUT TOA DIGITAL SIGNAL?CHANGEPSELECT?CHANGE PHASEREGISTER?CHANGEFSELECT?CHANGE FREQUENCYREGISTER?CONTROL REGISTERWRITE(SEE TABLE 6)INITIALIZATION(SEE FIGURE 27 BELOW)NONONONOYESNOYESYESNOYESYESYESYESYES02704-026
Figure 26. Flowchart for AD9833 Initialization and Operation
INITIALIZATIONAPPLY RESET(CONTROL REGISTER WRITE)RESET = 1WRITE TO FREQUENCY AND PHASE REGISTERSFREQ0 REG =fOUT0/fMCLK × 228FREQ1 REG =fOUT1/fMCLK × 228PHASE0 AND PHASE1 REG = (PHASESHIFT × 212)/2π(SEE FIGURE 28)SET RESET = 0SELECT FREQUENCY REGISTERSSELECT PHASE REGISTERS(CONTROL REGISTER WRITE)RESET BIT = 0FSELECT = SELECTED FREQUENCY REGISTERPSELECT = SELECTED PHASE REGISTER02704-027
Figure 27. Flowchart for Initialization
Data Sheet AD9833
Rev. E | Page 19 of 24
NOWRITE 14MSBs OR LSBsTO A FREQUENCY REGISTER?(CONTROL REGISTER WRITE)B28 (D13) = 0HLB (D12) = 0/1WRITE A 16-BIT WORD(SEE TABLE 10 AND TABLE 11FOR EXAMPLES)WRITE 14MSBs OR LSBsTO AFREQUENCY REGISTER?WRITE TO PHASEREGISTER?(16-BIT WRITE)D15, D14 = 11 D13 = 0/1 (CHOOSE THE PHASE REGISTER) D12 = XD11 ... D0 = PHASE DATAWRITE TO ANOTHERPHASE REGISTER?YESWRITE ANOTHER FULL28-BIT WORD TO AFREQUENCY REGISTER?WRITE TWO CONSECUTIVE16-BIT WORDS(SEE TABLE 9 FOR EXAMPLE)(CONTROL REGISTER WRITE)B28 (D13) = 1WRITE A FULL 28-BIT WORDTO A FREQUENCY REGISTER?DATA WRITENOYESYESNOYESONONYESYES02704-028
Figure 28. Flowchart for Data Writes
AD9833 Data Sheet
Rev. E | Page 20 of 24
INTERFACING TO MICROPROCESSORS
The AD9833 has a standard serial interface that allows the part to interface directly with several microprocessors. The device uses an external serial clock to write the data or control information into the device. The serial clock can have a frequency of 40 MHz maximum. The serial clock can be continuous, or it can idle high or low between write operations. When data or control informa-tion is written to the AD9833, FSYNC is taken low and is held low until the 16 bits of data are written into the AD9833. The FSYNC signal frames the 16 bits of information that are loaded into the AD9833.
AD9833 TO 68HC11/68L11 INTERFACE
Figure 29 shows the serial interface between the AD9833 and the 68HC11/68L11 microcontroller. The microcontroller is con-figured as the master by setting the MSTR bit in the SPCR to 1. This setting provides a serial clock on SCK; the MOSI output drives the serial data line SDATA. Because the microcontroller does not have a dedicated frame sync pin, the FSYNC signal is derived from a port line (PC7). The setup conditions for correct operation of the interface are as follows:
• SCK idles high between write operations (CPOL = 0)
• Data is valid on the SCK falling edge (CPHA = 1)
When data is being transmitted to the AD9833, the FSYNC line is taken low (PC7). Serial data from the 68HC11/68L11 is trans-mitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data into the AD9833, PC7 is held low after the first eight bits are transferred, and a second serial write operation is performed to the AD9833. Only after the second eight bits are transferred should FSYNC be taken high again.
AD9833FSYNCSDATASCLK68HC11/68L11PC7MOSISCK02704-030
Figure 29. 68HC11/68L11 to AD9833 Interface
AD9833 TO 80C51/80L51 INTERFACE
Figure 30 shows the serial interface between the AD9833 and the 80C51/80L51 microcontroller. The microcontroller is oper-ated in Mode 0 so that TxD of the 80C51/80L51 drives SCLK of the AD9833, and RxD drives the serial data line SDATA. The FSYNC signal is derived from a bit programmable pin on the port (P3.3 is shown in Figure 30).
When data is to be transmitted to the AD9833, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes, thus only eight falling SCLK edges occur in each cycle. To load the remaining eight bits to the AD9833, P3.3 is held low after the first eight bits are transmitted, and a second write operation is initiated to transmit the second byte of data. P3.3 is taken high following the completion of the second write operation. SCLK should idle high between the two write operations.
The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD9833 accepts the MSB first (the four MSBs are the control information, the next four bits are the address, and the eight LSBs contain the data when writing to a destination register). Therefore, the transmit routine of the 80C51/80L51 must take this into account and rearrange the bits so that the MSB is output first.
AD9833FSYNCSDATASCLK80C51/80L51P3.3RxDTxD02704-031
Figure 30. 80C51/80L51 to AD9833 Interface
AD9833 TO DSP56002 INTERFACE
Figure 31 shows the interface between the AD9833 and the DSP56002. The DSP56002 is configured for normal mode asyn-chronous operation with a gated internal clock (SYN = 0, GCK = 1, SCKD = 1). The frame sync pin is generated internally (SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and the frame sync signal frames the 16 bits (FSL = 0). The frame sync signal is available on the SC2 pin, but it must be inverted before it is applied to the AD9833. The interface to the DSP56000/DSP56001 is similar to that of the DSP56002.
AD9833FSYNCSDATASCLKDSP56002SC2STDSCK02704-032
Figure 31. DSP56002 to AD9833 Interface
Data Sheet AD9833
Rev. E | Page 21 of 24
EVALUATION BOARD
The AD9833 evaluation board allows designers to evaluate the high performance AD9833 DDS modulator with a minimum of effort.
SYSTEM DEMONSTRATION PLATFORM
The system demonstration platform (SDP) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. The SDP board is based on the Blackfin® ADSP-BF527 processor with USB connectivity to the PC through a USB 2.0 high speed port. For more information about the SDP board, see the SDP board product page.
Note that the SDP board is sold separately from the AD9833 evaluation board.
AD9833 TO SPORT INTERFACE
The Analog Devices SDP board has a SPORT serial port that is used to control the serial inputs to the AD9833. The connections are shown in Figure 32.
AD9833FSYNCSDATASCLK02704-034SPORT_TFSSPORT_TSCLKSPORT_DTOADSP-BF527
Figure 32. SDP to AD9833 Interface
EVALUATION KIT
The DDS evaluation kit includes a populated, tested AD9833 printed circuit board (PCB). The schematics of the evaluation board are shown in Figure 34 and Figure 35.
The software provided in the evaluation kit allows the user to easily program the AD9833 (see Figure 33). The evaluation soft-ware runs on any IBM-compatible PC with Microsoft® Windows® software installed (including Windows 7). The software is com-patible with both 32-bit and 64-bit operating systems.
More information about the evaluation software is available on the software CD and on the AD9833 product page.
02704-035
Figure 33. AD9833 Evaluation Software Interface
CRYSTAL OSCILLATOR VS. EXTERNAL CLOCK
The AD9833 can operate with master clocks up to 25 MHz. A 25 MHz oscillator is included on the evaluation board. This oscillator can be removed and, if required, an external CMOS clock can be connected to the part. Options for the general oscillator include the following:
• AEL 301-Series oscillators, AEL Crystals
• SG-310SCN oscillators, Epson Electronics
POWER SUPPLY
Power to the AD9833 evaluation board can be provided from the USB connector or externally through pin connections. The power leads should be twisted to reduce ground loops.
AD9833 Data Sheet
Rev. E | Page 22 of 24
EVALUATION BOARD SCHEMATICS
02704-036
Figure 34. Evaluation Board Schematic
02704-037
Figure 35. SDP Connector Schematic
Data Sheet AD9833
Rev. E | Page 23 of 24
EVALUATION BOARD LAYOUT
02704-038
Figure 36. AD9833 Evaluation Board Component Side
02704-039
Figure 37. AD9833 Evaluation Board Silkscreen
02704-040
Figure 38. AD9833 Evaluation Board Solder Side
AD9833 Data Sheet
Rev. E | Page 24 of 24 OUTLINE DIMENSIONS
COMPLIANTTOJEDECSTANDARDSMO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50BSC
0.30
0.15
1.10MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15°MAX 0.95
0.85
0.75
0.15
0.05
Figure 39. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3 Temperature Range Package Description Package Option Branding
AD9833BRM −40°C to +105°C 10-Lead MSOP RM-10 DJB
AD9833BRM-REEL −40°C to +105°C 10-Lead MSOP RM-10 DJB
AD9833BRM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 DJB
AD9833BRMZ −40°C to +105°C 10-Lead MSOP RM-10 D68
AD9833BRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D68
AD9833BRMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D68
AD9833WBRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D68
EVAL-AD9833SDZ Evaluation Board
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 The evaluation board for the AD9833 requires the system demonstration platform (SDP) board, which is sold separately. AUTOMOTIVE PRODUCTS
The AD9833WBRMZ-REEL model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models. ©2003–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02704-0-9/12(E)
Triple-Channel Digital Isolators
Data Sheet ADuM1300/ADuM1301
Rev. J Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES Qualified for automotive applications Low power operation 5 V operation
1.2 mA per channel maximum at 0 Mbps to 2 Mbps 3.5 mA per channel maximum at 10 Mbps 32 mA per channel maximum at 90 Mbps 3 V operation
0.8 mA per channel maximum at 0 Mbps to 2 Mbps 2.2 mA per channel maximum at 10 Mbps 20 mA per channel maximum at 90 Mbps Bidirectional communication 3 V/5 V level translation
High temperature operation: 125°C High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics 2 ns maximum pulse width distortion
2 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body package
RoHS-compliant models available
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak TÜV approval: IEC/EN/UL/CSA 61010-1 APPLICATIONS
General-purpose multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceivers Industrial field bus isolation
Automotive systems GENERAL DESCRIPTION
The ADuM130x1 are triple-channel digital isolators based on the
Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic transformer technology, these isolation components provide outstanding performance
characteristics superior to alternatives, such as optocouplers. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth
of the power of optocouplers at comparable signal data rates. The ADuM130x isolators provide three independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). Both models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. In addition, the ADuM130x provide low pulse width distortion (<2 ns for CRW grade) and tight channel-to-channel matching (<2 ns for CRW grade). Unlike other optocoupler alternatives,
the ADuM130x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and when power is not applied to one of the supplies. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. ADuM1300 Functional Block Diagram
Figure 2. ADuM1301 Functional Block Diagram
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
VDD1
GND1
VIA
VIB
VIC
NC
NC
GND1
VDD2
GND2
VOA
VOB
VOC
NC
VE2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
03787-001
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
VDD1
GND1
VIA
VIB
VOC
NC
VE1
GND1
VDD2
GND2
VOA
VOB
VIC
NC
VE2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
03787-002
ADuM1300/ADuM1301 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Electrical Characteristics—5 V, 105°C Operation ................... 4
Electrical Characteristics—3 V, 105°C Operation ................... 6
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V, 105°C Operation ........................................................................... 8
Electrical Characteristics—5 V, 125°C Operation ................. 11
Electrical Characteristics—3 V, 125°C Operation ................. 13
Electrical Characteristics—Mixed 5 V/3 V, 125°C Operation ... 15
Electrical Characteristics—Mixed 3 V/5 V 125°C Operation ... 17
Package Characteristics ............................................................. 19
Regulatory Information ............................................................. 19
Insulation and Safety-Related Specifications .......................... 19
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics ......................................................... 20
Recommended Operating Conditions .................................... 20
Absolute Maximum Ratings ......................................................... 21
ESD Caution................................................................................ 21
Pin Configurations and Function Descriptions ......................... 22
Typical Performance Characteristics ........................................... 23
Applications Information .............................................................. 25
PC Board Layout ........................................................................ 25
Propagation Delay-Related Parameters ................................... 25
DC Correctness and Magnetic Field Immunity .......................... 25
Power Consumption .................................................................. 26
Insulation Lifetime ..................................................................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
Automotive Products ................................................................. 29 Rev. J | Page 2 of 32
Data Sheet ADuM1300/ADuM1301
REVISION HISTORY
4/14—Rev. I to Rev. J
Change to Table 9 ............................................................................ 19
3/12—Rev. H to Rev. I
Created Hyperlink for Safety and Regulatory Approvals Entry in Features Section ................................................................. 1 Change to PC Board Layout Section ............................................ 25 Updated Outline Dimensions ........................................................ 28 Moved Automotive Products Section ........................................... 28
5/08—Rev. G to Rev. H
Added ADuM1300W and ADuM1301W Parts ............. Universal Changes to Features List ................................................................... 1 Added Table 4 .................................................................................. 11 Added Table 5 .................................................................................. 13 Added Table 6 .................................................................................. 15 Added Table 7 .................................................................................. 17 Changes to Table 12 ........................................................................ 20 Changes to Table 13 ........................................................................ 21 Added Automotive Products Section ........................................... 27 Changes to Ordering Guide ........................................................... 28
11/07—Rev. F to Rev. G
Changes to Note 1 and Figure 2 ...................................................... 1 Added ADuM130xARW Change vs. Temperature Parameter ... 3 Added ADuM130xARW Change vs. Temperature Parameter ... 5 Added ADuM130xARW Change vs. Temperature Parameter ... 8 Changes to Figure 14 ...................................................................... 16
6/07—Rev. E to Rev. F
Updated VDE Certification Throughout ....................................... 1 Changes to Features, Note 1, Figure 1, and Figure 2 .................... 1 Changes to Regulatory Information Section ............................... 10 Added Table 10 ................................................................................ 12 Added Insulation Lifetime Section ............................................... 17 Updated Outline Dimensions ........................................................ 19 Changes to Ordering Guide ........................................................... 19
2/06—Rev. D to Rev. E
Updated Format ................................................................. Universal Added TÜV Approval ....................................................... Universal Changes to Figure 2 .......................................................................... 1
5/05—Rev. C to Rev. D
Changes to Format ............................................................. Universal Changes to Figure 2 .......................................................................... 1 Changes to Table 6 .......................................................................... 10 Changes to Ordering Guide ........................................................... 18
6/04—Rev. B to Rev. C
Changes to Format ............................................................. Universal Changes to Features .......................................................................... 1 Changes to Electrical Characteristics—5 V Operation ................ 3 Changes to Electrical Characteristics—3 V Operation ................ 5 Changes to Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V Operation ............................................................................ 7 Changes to Ordering Guide ........................................................... 18
5/04—Rev. A to Rev. B
Changes to the Format ...................................................... Universal Changes to the Features.................................................................... 1 Changes to Table 7 and Table 8 ..................................................... 14 Changes to Table 9 .......................................................................... 15 Changes to the DC Correctness and Magnetic Field Immunity Section .............................................................................................. 19 Changes to the Power Consumption Section .............................. 20 Changes to the Ordering Guide .................................................... 21
9/03—Rev. 0 to Rev. A
Edits to Regulatory Information ................................................... 13 Edits to Absolute Maximum Ratings ............................................ 15 Deleted the Package Branding Information ................................ 16
9/03—Revision 0: Initial Version
Rev. J | Page 3 of 32
ADuM1300/ADuM1301 Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These specifications do not apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.50
0.53
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.19
0.24
mA
ADuM1300 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.6
2.5
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.7
1.0
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
6.5
8.1
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.9
2.5
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
57
77
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
16
18
mA
45 MHz logic signal freq.
ADuM1301 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.3
2.1
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
1.0
1.4
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
5.0
6.2
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
3.4
4.2
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
43
57
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
29
37
mA
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
2.0
V
Logic Low Input Threshold
VIL, VEL
0.8
V
Logic High Output Voltages
VOAH, VOBH, VOCH
(VDD1 or VDD2) − 0.1
5.0
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.4
4.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
65
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
11
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 4 of 32
Data Sheet ADuM1300/ADuM1301
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
ADuM130xBRW
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
32
50
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
15
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
ADuM130xCRW
Minimum Pulse Width2
PW
8.3
11.1
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
90
120
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
18
27
32
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
0.5
2
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
3
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
10
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
2
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.2
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
0.19
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.05
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. J | Page 5 of 32
ADuM1300/ADuM1301 Data Sheet
ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION
All voltages are relative to their respective ground. 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications do not apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.26
0.31
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.11
0.15
mA
ADuM1300 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.9
1.7
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.4
0.7
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
3.4
4.9
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.1
1.6
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
31
48
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
8
13
mA
45 MHz logic signal freq.
ADuM1301 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.7
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.6
0.9
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
2.6
3.7
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.8
2.5
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
24
36
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
16
23
mA
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
1.6
V
Logic Low Input Threshold
VIL, VEL
0.4
V
Logic High Output Voltages
VOAH, VOBH, VOCH
(VDD1 or VDD2) − 0.1
3.0
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.4
2.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
75
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
11
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 6 of 32
Data Sheet ADuM1300/ADuM1301
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
ADuM130xBRW
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
38
50
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
26
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
ADuM130xCRW
Minimum Pulse Width2
PW
8.3
11.1
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
90
120
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
34
45
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
0.5
2
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
3
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
16
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
2
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
0.10
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.03
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. J | Page 7 of 32
ADuM1300/ADuM1301 Data Sheet
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.0 V. These specifica-tions do not apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
5 V/3 V Operation
0.50
0.53
mA
3 V/5 V Operation
0.26
0.31
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
5 V/3 V Operation
0.11
0.15
mA
3 V/5 V Operation
0.19
0.24
mA
ADuM1300 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
5 V/3 V Operation
1.6
2.5
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
0.9
1.7
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
5 V/3 V Operation
0.4
0.7
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
0.7
1.0
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
5 V/3 V Operation
6.5
8.1
mA
5 MHz logic signal freq.
3 V/5 V Operation
3.4
4.9
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
5 V/3 V Operation
1.1
1.6
mA
5 MHz logic signal freq.
3 V/5 V Operation
1.9
2.5
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
5 V/3 V Operation
57
77
mA
45 MHz logic signal freq.
3 V/5 V Operation
31
48
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
5 V/3 V Operation
8
13
mA
45 MHz logic signal freq.
3 V/5 V Operation
16
18
mA
45 MHz logic signal freq.
ADuM1301 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
5 V/3 V Operation
1.3
2.1
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
0.7
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
5 V/3 V Operation
0.6
0.9
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
1.0
1.4
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
5 V/3 V Operation
5.0
6.2
mA
5 MHz logic signal freq.
3 V/5 V Operation
2.6
3.7
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
5 V/3 V Operation
1.8
2.5
mA
5 MHz logic signal freq.
3 V/5 V Operation
3.4
4.2
mA
5 MHz logic signal freq. Rev. J | Page 8 of 32
Data Sheet ADuM1300/ADuM1301
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
5 V/3 V Operation
43
57
mA
45 MHz logic signal freq.
3 V/5 V Operation
24
36
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
5 V/3 V Operation
16
23
mA
45 MHz logic signal freq.
3 V/5 V Operation
29
37
mA
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
5 V/3 V Operation
2.0
V
3 V/5 V Operation
1.6
V
Logic Low Input Threshold
VIL, VEL
5 V/3 V Operation
0.8
V
3 V/5 V Operation
0.4
V
Logic High Output Voltages
VOAH, VOBH, VOCH
(VDD1 or VDD2) − 0.1
(VDD1 or VDD2)
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.4
(VDD1 or VDD2) − 0.2
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
70
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
11
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels
ADuM130xBRW
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
15
35
50
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
6
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
22
ns
CL = 15 pF, CMOS signal levels
ADuM130xCRW
Minimum Pulse Width2
PW
8.3
11.1
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
90
120
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
30
40
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
0.5
2
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
3
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
14
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
2
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 9 of 32
ADuM1300/ADuM1301 Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
CL = 15 pF, CMOS signal levels
5 V/3 V Operation
3.0
ns
3 V/5 V Operation
2.5
ns
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
5 V/3 V Operation
1.2
Mbps
3 V/5 V Operation
1.1
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
5 V/3 V Operation
0.19
mA/Mbps
3 V/5 V Operation
0.10
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
5 V/3 V Operation
0.03
mA/Mbps
3 V/5 V Operation
0.05
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. J | Page 10 of 32
Data Sheet ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These specifications apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.50
0.53
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.19
0.24
mA
ADuM1300W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.6
2.5
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.7
1.0
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
6.5
8.1
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.9
2.5
mA
5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.3
2.1
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
1.0
1.4
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
5.0
6.2
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
3.4
4.2
mA
5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
2.0
V
Logic Low Input Threshold
VIL, VEL
0.8
V
Logic High Output Voltages
VOAH, VOBH, VOCH
VDD1, VDD2 − 0.1
5.0
V
IOx = −20 μA, VIx = VIxH
VDD1, VDD2 − 0.4
4.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
65
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
18
27
32
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
15
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 11 of 32
ADuM1300/ADuM1301 Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.2
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
0.19
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.05
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. J | Page 12 of 32
Data Sheet ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.26
0.31
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.11
0.15
mA
ADuM1300W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.9
1.7
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.4
0.7
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
3.4
4.9
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.1
1.6
mA
5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.7
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.6
0.9
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
2.6
3.7
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.8
2.5
mA
5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
1.6
V
Logic Low Input Threshold
VIL, VEL
0.4
V
Logic High Output Voltages
VOAH, VOBH, VOCH
VDD1, VDD2 − 0.1
3.0
V
IOx = −20 μA, VIx = VIxH
VDD1, VDD2 − 0.4
2.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
75
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
34
45
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
26
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 13 of 32
ADuM1300/ADuM1301 Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
0.10
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.03
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. J | Page 14 of 32
Data Sheet ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION1
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 5 V, VDD2 = 3.0 V. These specifications apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 6.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.50
0.53
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.11
0.15
mA
ADuM1300W, Total Supply Current, Three Channels2
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.6
2.5
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.4
0.7
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
6.5
8.1
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.1
1.6
mA
5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.3
2.1
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.6
0.9
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
5.0
6.2
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.8
2.5
mA
5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
2.0
V
Logic Low Input Threshold
VIL, VEL
0.8
V
Logic High Output Voltages
VOAH, VOBH, VOCH
VDD1, VDD2 − 0.1
VDD1, VDD2
V
IOx = −20 μA, VIx = VIxH
VDD1, VDD2 − 0.4
VDD1, VDD2 − 0.2
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width3
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay5
tPHL, tPLH
50
70
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Propagation Delay Skew6
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
30
40
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
6
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
22
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 15 of 32
ADuM1300/ADuM1301 Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
3.0
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output8
|CMH|
25
35
kV/μs
VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.2
Mbps
Input Dynamic Supply Current per Channel9
IDDI (D)
0.19
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.03
mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. J | Page 16 of 32
Data Sheet ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V. These apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 7.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.26
0.31
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.19
0.24
mA
ADuM1300W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.9
1.7
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2(Q)
0.7
1.0
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
3.4
4.9
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.9
2.5
mA
5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.7
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
1.0
1.4
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
2.6
3.7
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
3.4
4.2
mA
5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
1.6
V
Logic Low Input Threshold
VIL, VEL
0.4
V
Logic High Output Voltages
VOAH, VOBH, VOCH
VDD1, VDD2 − 0.1
VDD1, VDD2
V
IOx = −20 μA, VIx = VIxH
VDD1, VDD2 − 0.4
VDD1, VDD2 − 0.2
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
70
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
30
40
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
6
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
22
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 17 of 32
ADuM1300/ADuM1301 Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
CL = 15 pF, CMOS signal levels
5 V/3 V Operation
3.0
ns
3 V/5 V Operation
2.5
ns
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
0.10
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.05
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300W/ADuM1301W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. J | Page 18 of 32
Data Sheet ADuM1300/ADuM1301
PACKAGE CHARACTERISTICS
Table 8.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Resistance (Input-to-Output)1
RI-O
1012
Ω
Capacitance (Input-to-Output)1
CI-O
1.7
pF
f = 1 MHz
Input Capacitance2
CI
4.0
pF
IC Junction-to-Case Thermal Resistance, Side 1
θJCI
33
°C/W
Thermocouple located at center of package underside
IC Junction-to-Case Thermal Resistance, Side 2
θJCO
28
°C/W
1 Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM130x are approved by the organizations listed in Table 9. Refer to Table 14 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels.
Table 9.
UL
CSA
VDE
TÜV
Recognized under 1577 Component Recognition Program1
Approved under CSA Component Acceptance Notice #5A
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122
Approved according to IEC 61010-1:2001 (2nd Edition), EN 61010-1:2001 (2nd Edition), UL 61010-1:2004 CSA C22.2.61010.1:2005
Single protection, 2500 V rms isolation voltage
Basic insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage
Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage
Reinforced insulation, 560 V peak
Reinforced insulation, 400 V rms maximum working voltage
File E214100
File 205078
File 2471900-4880-0001
Certificate U8V 05 06 56232 002
1 In accordance with UL 1577, each ADuM130x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA).
2 In accordance with DIN V VDE V 0884-10, each ADuM130x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 10.
Parameter
Symbol
Value
Unit
Conditions
Rated Dielectric Insulation Voltage
2500
V rms
1-minute duration
Minimum External Air Gap (Clearance)
L(I01)
7.7 min
mm
Measured from input terminals to output terminals, shortest distance through air
Minimum External Tracking (Creepage)
L(I02)
8.1 min
mm
Measured from input terminals to output terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance)
0.017 min
mm
Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index)
CTI
>175
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. J | Page 19 of 32
ADuM1300/ADuM1301 Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage.
Table 11.
Description
Conditions
Symbol
Characteristic
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
I to IV
For Rated Mains Voltage ≤ 300 V rms
I to III
For Rated Mains Voltage ≤ 400 V rms
I to II
Climatic Classification
40/105/21
Pollution Degree per DIN VDE 0110, Table 1
2
Maximum Working Insulation Voltage
VIORM
560
V peak
Input-to-Output Test Voltage, Method B1
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC
VPR
1050
V peak
Input-to-Output Test Voltage, Method A
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
VPR
After Environmental Tests Subgroup 1
896
V peak
After Input and/or Safety Test Subgroup 2 and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
672
V peak
Highest Allowable Overvoltage
Transient overvoltage, tTR = 10 seconds
VTR
4000
V peak
Safety-Limiting Values
Maximum value allowed in the event of a failure (see Figure 3)
Case Temperature
TS
150
°C
Side 1 Current
IS1
265
mA
Side 2 Current
IS2
335
mA
Insulation Resistance at TS
VIO = 500 V
RS
>109
Ω
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 12.
Parameter
Rating
Operating Temperature (TA)1
−40°C to +105°C
Operating Temperature (TA)2
−40°C to +125°C
Supply Voltages (VDD1, VDD2)1, 3
2.7 V to 5.5 V
Supply Voltages (VDD1, VDD2) 2, 3
3.0 V to 5.5 V
Input Signal Rise and Fall Times
1.0 ms
1 Does not apply to ADuM1300W and ADuM1301W automotive grade versions.
2 Applies to ADuM1300W and ADuM1301W automotive grade versions.
3 All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields.
CASE TEMPERATURE (°C)SAFETY-LIMITING CURRENT (mA)003503002502001501005050100150200SIDE #1SIDE #203787-003
Rev. J | Page 20 of 32
Data Sheet ADuM1300/ADuM1301
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 13.
Parameter
Rating
Storage Temperature (TST)
−65°C to +150°C
Ambient Operating Temperature (TA)1
−40°C to +105°C
Ambient Operating Temperature (TA)2
−40°C to +125°C
Supply Voltages (VDD1, VDD2)3
−0.5 V to +7.0 V
Input Voltage (VIA, VIB, VIC, VE1, VE2)3, 4
−0.5 V to VDDI + 0.5 V
Output Voltage (VOA, VOB, VOC)3, 4
−0.5 V to VDDO + 0.5 V
Average Output Current per Pin5
Side 1 (IO1)
−23 mA to +23 mA
Side 2 (IO2)
−30 mA to +30 mA
Common-Mode Transients6
−100 kV/μs to +100 kV/μs
1 Does not apply to ADuM1300W and ADuM1301W automotive grade versions.
2 Applies to ADuM1300W and ADuM1301W automotive grade versions.
3 All voltages are relative to their respective ground.
4 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section.
5 See Figure 3 for maximum rated current values for various temperatures.
6 This refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Ratings may cause latch-up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Table 14. Maximum Continuous Working Voltage1
Parameter
Max
Unit
Constraint
AC Voltage, Bipolar Waveform
565
V peak
50-year minimum lifetime
AC Voltage, Unipolar Waveform
Basic Insulation
1131
V peak
Maximum approved working voltage per IEC 60950-1
Reinforced Insulation
560
V peak
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
DC Voltage
Basic Insulation
1131
V peak
Maximum approved working voltage per IEC 60950-1
Reinforced Insulation
560
V peak
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 15. Truth Table (Positive Logic)
VIx Input1
VEx Input1, 2
VDDI State1
VDDO State1
VOx Output1
Notes
H
H or NC
Powered
Powered
H
L
H or NC
Powered
Powered
L
X
L
Powered
Powered
Z
X
H or NC
Unpowered
Powered
H
Outputs return to the input state within 1 μs of VDDI power restoration.
X
L
Unpowered
Powered
Z
X
X
Powered
Unpowered
Indeterminate
Outputs return to the input state within 1 μs of VDDO power restoration if the VEx state is H or NC. Outputs return to a high impedance state within 8 ns of VDDO power restoration if the VEx state is L.
1 VIx and VOx refer to the input and output signals of a given channel (A, B, or C). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.
2 In noisy environments, connecting VEx to an external logic high or low is recommended.
Rev. J | Page 21 of 32
ADuM1300/ADuM1301 Data Sheet
Rev. J | Page 22 of 32 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. ADuM1300 Pin Configuration Figure 5. ADuM1301 Pin Configuration
Table 16. ADuM1300 Pin Function Descriptions Pin
No. Mnemonic Description 1 VDD1 Supply Voltage for Isolator Side 1. 2 GND1 Ground 1. Ground reference for Isolator Side 1. 3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 NC No Connect.
7 NC No Connect.
8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2 Output Enable 2. Active high logic input. VOA, VOB,
and VOC outputs are enabled when VE2 is high or disconnected. VOA, VOB, and VOC outputs are disabled
when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended. 11 NC No Connect.
12 VOC Logic Output C. 13 VOB Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 VDD2 Supply Voltage for Isolator Side 2. Table 17. ADuM1301 Pin Function Descriptions Pin
No. Mnemonic Description 1 VDD1 Supply Voltage for Isolator Side 1. 2 GND1 Ground 1. Ground reference for Isolator Side 1. 3 VIA Logic Input A.
4 VIB Logic Input B.
5 VOC Logic Output C. 6 NC No Connect.
7 VE1 Output Enable 1. Active high logic input. VOC output is enabled when VE1 is high or disconnected. VOC
output is disabled when VE1 is low. In noisy environ-
ments, connecting VE1 to an external logic high
or low is recommended. 8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2 Output Enable 2. Active high logic input. VOA and
VOB outputs are enabled when VE2 is high or discon-
nected. VOA and VOB outputs are disabled when VE2 is
low. In noisy environments, connecting VE2 to an external logic high or low is recommended.
11 NC No Connect.
12 VIC Logic Input C.
13 VOB Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 VDD2 Supply Voltage for Isolator Side 2. VDD1 1
*GND1 2
VIA 3
VIB 4
VDD2 16
15 GND2*
14 VOA
13 VOB
VIC 5 12 VOC
NC 6 11 NC
NC 7 10 VE2
*GND1 8 GND9 2*
NC = NO CONNECT
ADuM1300
TOP VIEW
(Not to Scale)
03787-004
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
03787-005
VDD1 1
*GND1 2
VIA 3
VIB 4
VDD2 16
GND15 2*
14 VOA
13 VOB
VOC 5 12 VIC
NC 6 11 NC
VE1 7 10 VE2
*GND1 8 GND9 2*
NC = NO CONNECT
ADuM1301
TOP VIEW
(Not to Scale)
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Data Sheet ADuM1300/ADuM1301
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. Typical Input Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation
Figure 7. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load)
Figure 8. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load)
Figure 9. Typical ADuM1300 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
Figure 10. Typical ADuM1300 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
Figure 11. Typical ADuM1301 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
DATA RATE (Mbps)CURRENT/CHANNEL (mA)006421412108161820402060801005V3V03787-008DATA RATE (Mbps)CURRENT/CHANNEL (mA)00243516204060801005V3V03787-009DATA RATE (Mbps)CURRENT/CHANNEL (mA)0010987654321204080601005V3V03787-010DATA RATE (Mbps)CURRENT (mA)02002010504030604060801005V3V03787-011DATA RATE (Mbps)CURRENT (mA)00421086121614402060801005V3V03787-012DATA RATE (Mbps)CURRENT (mA)001510545403530252050204060801005V3V03787-013
Rev. J | Page 23 of 32
ADuM1300/ADuM1301 Data Sheet
Figure 12. Typical ADuM1301 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
Figure 13. Propagation Delay vs. Temperature, C Grade
DATA RATE (Mbps)CURRENT (mA)0010520152530204060801005V3V03787-014TEMPERATURE (°C)PROPAGATION DELAY (ns)–50–252530354005075251003V5V03787-019
Rev. J | Page 24 of 32
Data Sheet ADuM1300/ADuM1301
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM130x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 14). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VDD2. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless the ground pair on each package side is connected close to the package.
Figure 14. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high output.
Figure 15. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADuM130x component.
Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM130x components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is therefore either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 15) by the watchdog timer circuit.
The ADuM130x is extremely immune to external magnetic fields. The limitation on the magnetic field immunity of the ADuM130x is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM130x is examined because it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt)ΣΠrn2; n = 1, 2, … , N
where: β is magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM130x and an imposed requirement that the induced voltage be 50% at most of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 16.
Figure 16. Maximum Allowable External Magnetic Flux Density
VDD1GND1VIAVIBVIC/VOCNCNC/VE1GND1VDD2GND2VOAVOBVOC/VICNCVE2GND203787-015INPUT (VIx)OUTPUT (VOx)tPLHtPHL50%50%03787-016MAGNETIC FIELD FREQUENCY (
Hz)100MAXIMUM ALLOWABLE MAGNETIC FLUXDENSITY (
kgauss)0.0011M100.011k10k10M0.11100M100k03787-017
Rev. J | Page 25 of 32
ADuM1300/ADuM1301 Data Sheet
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and has the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM130x transformers. Figure 17 shows these allowable current magnitudes as a function of frequency for selected distances. The ADuM130x is extremely immune and can be affected only by extremely large currents operated at a high frequency very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM130x to affect the operation of the component.
Figure 17. Maximum Allowable Current for Various Current-to-ADuM130x Spacings
Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM130x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel.
For each input channel, the supply current is given by
IDDI = IDDI (Q) f ≤ 0.5 fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5 fr
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5 fr
IDDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q) f > 0.5 fr
where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz); it is half of the input data rate expressed in units of Mbps. fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA).
To calculate the total VDD1 and VDD2 supply current, the supply currents for each input and output channel corresponding to VDD1 and VDD2 are calculated and totaled. Figure 6 and Figure 7 provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 8 provides per-channel supply current as a function of data rate for a 15 pF output condition. Figure 9 through Figure 12 provide total VDD1 and VDD2 supply current as a function of data rate for ADuM1300/ ADuM1301 channel configurations.
MAGNETIC FIELD FREQUENCY (Hz)MAXIMUM ALLOWABLE CURRENT (kA)10001001010.10.011k10k100M100k1M10MDISTANCE = 5mmDISTANCE = 1mDISTANCE = 100mm03787-018
Rev. J | Page 26 of 32
Data Sheet ADuM1300/ADuM1301
INSULATION LIFETIME
All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM130x.
Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Accel-eration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 14 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.
The insulation lifetime of the ADuM130x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 18, Figure 19, and Figure 20 illustrate these different isolation voltage waveforms, respectively.
Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage.
In the case of unipolar ac or dc voltage, the stress on the insu-lation is significantly lower, which allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 14 can be applied while main-taining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross insulation voltage waveform that does not conform to Figure 19 or Figure 20 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 14.
Note that the voltage presented in Figure 19 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.
Figure 18. Bipolar AC Waveform
Figure 19. Unipolar AC Waveform
Figure 20. DC Waveform
0VRATED PEAK VOLTAGE03787-0210VRATED PEAK VOLTAGE03787-0220VRATED PEAK VOLTAGE03787-023
Rev. J | Page 27 of 32
ADuM1300/ADuM1301 Data Sheet
OUTLINE DIMENSIONS
Figure 21. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters (and inches)
ORDERING GUIDE
Model1, 2, 3, 4
Number of Inputs, VDD1 Side
Number of Inputs, VDD2 Side
Maximum Data Rate (Mbps)
Maximum Propagation Delay, 5 V (ns)
Maximum Pulse Width Distortion (ns)
Temperature Range
Package Option5
ADuM1300ARW
3
0
1
100
40
−40°C to +105°C
RW-16
ADuM1300CRW
3
0
90
32
2
−40°C to +105°C
RW-16
ADuM1300ARWZ
3
0
1
100
40
−40°C to +105°C
RW-16
ADuM1300BRWZ
3
0
10
50
3
−40°C to +105°C
RW-16
ADuM1300CRWZ
3
0
90
32
2
−40°C to +105°C
RW-16
ADuM1300WSRWZ
3
0
1
100
40
−40°C to +125°C
RW-16
ADuM1300WTRWZ
3
0
10
32
3
−40°C to +125°C
RW-16
ADuM1301ARW
2
1
1
100
40
−40°C to +105°C
RW-16
ADuM1301BRW
2
1
10
50
3
−40°C to +105°C
RW-16
ADuM1301CRW
2
1
90
32
2
−40°C to +105°C
RW-16
ADuM1301ARWZ
2
1
1
100
40
−40°C to +105°C
RW-16
ADuM1301BRWZ
2
1
10
50
3
−40°C to +105°C
RW-16
ADuM1301CRWZ
2
1
90
32
2
−40°C to +105°C
RW-16
ADuM1301WSRWZ
2
1
1
100
40
−40°C to +125°C
RW-16
ADuM1301WTRWZ
2
1
10
32
3
−40°C to +125°C
RW-16
EVAL-ADuMQSEBZ
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape-and-reel option.
4 No tape-and-reel option is available for the ADuM1301CRW model.
5 RW-16 = 16-lead wide body SOIC.
CONTROLLINGDIMENSIONSAREINMILLIMETERS;INCHDIMENSIONS(INPARENTHESES)AREROUNDED-OFFMILLIMETEREQUIVALENTSFORREFERENCEONLYANDARENOTAPPROPRIATEFORUSEINDESIGN.COMPLIANTTOJEDECSTANDARDSMS-013-AA10.50(0.4134)10.10(0.3976)0.30(0.0118)0.10(0.0039)2.65(0.1043)2.35(0.0925)10.65(0.4193)10.00(0.3937)7.60(0.2992)7.40(0.2913)0.75(0.0295)0.25(0.0098)45°1.27(0.0500)0.40(0.0157)COPLANARITY0.100.33(0.0130)0.20(0.0079)0.51(0.0201)0.31(0.0122)SEATINGPLANE8°0°169811.27(0.0500)BSC03-27-2007-B
Rev. J | Page 28 of 32
Data Sheet ADuM1300/ADuM1301
AUTOMOTIVE PRODUCTS
The ADuM1300W/ADuM1301W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.
Rev. J | Page 29 of 32
ADuM1300/ADuM1301 Data Sheet
NOTES
Rev. J | Page 30 of 32
Data Sheet ADuM1300/ADuM1301
NOTES
Rev. J | Page 31 of 32
ADuM1300/ADuM1301 Data Sheet
NOTES
©2003–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03787-0-4/14(J)
Rev. J | Page 32 of 32
Dual-Channel Digital Isolators
Data Sheet ADuM1200/ADuM1201
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved. FEATURES Narrow body, RoHS-compliant, SOIC 8-lead package
Low power operation 5 V operation
1.1 mA per channel maximum @ 0 Mbps to 2 Mbps 3.7 mA per channel maximum @ 10 Mbps 8.2 mA per channel maximum @ 25 Mbps
3 V operation
0.8 mA per channel maximum @ 0 Mbps to 2 Mbps 2.2 mA per channel maximum @ 10 Mbps
4.8 mA per channel maximum @ 25 Mbps
Bidirectional communication 3 V/5 V level translation
High temperature operation: 125°C High data rate: dc to 25 Mbps (NRZ)
Precise timing characteristics 3 ns maximum pulse width distortion
3 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Qualified for automotive applications Safety and regulatory approvals
UL recognition 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
VIORM = 560 V peak APPLICATIONS
Size-critical multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceiver isolation Digital field bus isolation
Hybrid electric vehicles, battery monitor, and motor drive GENERAL DESCRIPTION
The ADuM120x1 are dual-channel digital isolators based on the Analog Devices, Inc., iCoupler® technology. Combining
high speed CMOS and monolithic transformer technologies,
these isolation components provide outstanding performance
characteristics superior to alternatives, such as optocouplers. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with opto-
couplers. The typical optocoupler concerns regarding uncertain
current transfer ratios, nonlinear transfer functions, and temper-
ature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The ADuM120x isolators provide two independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). Both parts operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. In addition, the ADuM120x provide low pulse width distortion (<3 ns for CR grade) and tight channel-to-channel matching (<3 ns for CR grade). Unlike other optocoupler alternatives, the ADuM120x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. The ADuM1200W and ADuM1201W are automotive grade
versions qualified for 125°C operation. See the Automotive Products section for more information. FUNCTIONAL BLOCK DIAGRAMS
ENCODE DECODE
ENCODE DECODE
VDD1
VIA
VIB
GND1
VDD2
VOA
VOB
GND2
1
2
3
4
8
7
6
5
04642-001
Figure 1. ADuM1200 Functional Block Diagram
ENCODE DECODE
DECODE ENCODE
VDD1
VOA
VIB
GND1
VDD2
VIA
VOB
GND2
1
2
3
4
8
7
6
5
04642-002
Figure 2. ADuM1201 Functional Block Diagram
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 2 of 28
TABLE OF CONTENTS
Features..............................................................................................1
Applications.......................................................................................1
General Description.........................................................................1
Functional Block Diagrams.............................................................1
Revision History...............................................................................3
Specifications.....................................................................................4
Electrical Characteristics—5 V, 105°C Operation...................4
Electrical Characteristics—3 V, 105°C Operation...................6
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V, 105°C Operation...........................................................................8
Electrical Characteristics—5 V, 125°C Operation.................11
Electrical Characteristics—3 V, 125°C Operation.................13
Electrical Characteristics—Mixed 5 V/3 V, 125°C Operation15
Electrical Characteristics—Mixed 3 V/5 V, 125°C Operation17
Package Characteristics.............................................................19
Regulatory Information.............................................................19
Insulation and Safety-Related Specifications..........................19
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Insulation Characteristics.........................................................20
Recommended Operating Conditions....................................20
Absolute Maximum Ratings.........................................................21
ESD Caution................................................................................21
Pin Configurations and Function Descriptions.........................22
Typical Performance Characteristics...........................................23
Applications Information..............................................................24
PCB Layout.................................................................................24
Propagation Delay-Related Parameters...................................24
DC Correctness and Magnetic Field Immunity...........................24
Power Consumption..................................................................25
Insulation Lifetime.....................................................................26
Outline Dimensions.......................................................................27
Ordering Guide..........................................................................27
Automotive Products.................................................................28
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 3 of 28
REVISION HISTORY
3/12—Rev. H to Rev. I
Created Hyperlink for Safety and Regulatory Approvals Entry in Features Section.................................................................1 Change to General Description Section.........................................1 Change to PCB Layout Section.....................................................24 Moved Automotive Products Section...........................................28
1/09—Rev. G to Rev. H
Changes to Table 5, Switching Specifications Parameter...........13 Changes to Table 6, Switching Specifications Parameter...........15 Changes to Table 7, Switching Specifications Parameter...........17
9/08—Rev. F to Rev. G
Changes to Table 9..........................................................................19
Changes to Table 13........................................................................21
Changes to Ordering Guide...........................................................27
3/08—Rev. E to Rev. F
Changes to Features Section............................................................1 Changes to Applications Section.....................................................1 Added Table 4..................................................................................11 Added Table 5..................................................................................13 Added Table 6..................................................................................15 Added Table 7..................................................................................17 Changes to Table 12........................................................................20 Changes to Table 13........................................................................21 Added Automotive Products Section...........................................26 Changes to Ordering Guide...........................................................27
11/07—Rev. D to Rev. E
Changes to Note 1.............................................................................1 Added ADuM120xAR Change vs. Temperature Parameter.......3 Added ADuM120xAR Change vs. Temperature Parameter.......5 Added ADuM120xAR Change vs. Temperature Parameter.......8
8/07—Rev. C to Rev. D
Updated VDE Certification Throughout.......................................1 Changes to Features, Note 1, Figure 1, and Figure 2....................1 Changes to Table 3............................................................................7 Changes to Regulatory Information Section...............................10 Added Table 10................................................................................12 Added Insulation Lifetime Section...............................................16 Updated Outline Dimensions........................................................18 Changes to Ordering Guide...........................................................18
2/06—Rev. B to Rev. C
Updated Format.................................................................Universal Added Note 1.....................................................................................1 Changes to Absolute Maximum Ratings......................................12 Changes to DC Correctness and Magnetic Field Immunity Section............................................................................15
9/04—Rev. A to Rev. B
Changes to Table 5..........................................................................10
6/04—Rev. 0 to Rev. A
Changes to Format.............................................................Universal Changes to General Description.....................................................1 Changes to Electrical Characteristics—5 V Operation................3 Changes to Electrical Characteristics—3 V Operation................5 Changes to Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V Operation............................................................................7
4/04—Revision 0: Initial Version
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 4 of 28
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION
All voltages are relative to their respective ground; 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V; this does not apply to the ADuM1200W and ADuM1201W automotive grade products.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.50
0.60
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.19
0.25
mA
ADuM1200 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.1
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.5
0.8
mA
DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
VDD1 Supply Current
IDD1 (10)
4.3
5.5
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.3
2.0
mA
5 MHz logic signal freq.
25 Mbps (CR Grade Only)
VDD1 Supply Current
IDD1 (25)
10
13
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
2.8
3.4
mA
12.5 MHz logic signal freq.
ADuM1201 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.8
1.1
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.8
1.1
mA
DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
VDD1 Supply Current
IDD1 (10)
2.8
3.5
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
2.8
3.5
mA
5 MHz logic signal freq.
25 Mbps (CR Grade Only)
VDD1 Supply Current
IDD1 (25)
6.3
8.0
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
6.3
8.0
mA
12.5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB
−10
+0.01
+10
μA
0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
VIH
0.7 (VDD1 or VDD2)
V
Logic Low Input Threshold
VIL
0.3 (VDD1 or VDD2)
V
Logic High Output Voltages
VOAH, VOBH
(VDD1 or VDD2) − 0.1
5.0
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5
4.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xAR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
1000
ns
Maximum Data Rate3
1
Mbps
Propagation Delay4 t
PHL, tPLH
50
150
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
Change vs. Temperature
11
ps/°C
Propagation Delay Skew5 t
PSK
100
ns
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
10
ns
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 5 of 28
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM120xBR
Minimum Pulse Width2
PW
100
ns
Maximum Data Rate3
10
Mbps
Propagation Delay4
tPHL, tPLH
20
50
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
15
ns
Channel-to-Channel Matching
3
Codirectional Channels6
tPSKCD
ns
Opposing Directional Channels6
tPSKOD
15
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
ADuM120xCR
Minimum Pulse Width2
PW
20
40
ns
Maximum Data Rate3
25
50
Mbps
Propagation Delay4
tPHL, tPLH
20
45
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
15
ns
Channel-to-Channel Matching
3
ns
Codirectional Channels6
tPSKCD
Opposing Directional Channels6
tPSKOD
15
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
For All Models
Common-Mode Transient Immunity
Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.2
Mbps
Dynamic Supply Current per Channel8
Input
IDDI (D)
0.19
mA/ Mbps
Output
IDDO (D)
0.05
mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
Power ConsumptionPower Consumption
Figure 6 Figure 6
Figure 8Figure 8
Figure 9
Figure 11
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply current for a given data rate.
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 6 of 28 ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION
All voltages are relative to their respective ground; 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V; this
does not apply to ADuM1200W and ADuM1201W automotive grade products.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.26 0.35 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.11 0.20 mA
ADuM1200 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.6 1.0 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.2 0.6 mA DC to 1 MHz logic signal freq. 10 Mbps (BR and CR Grades Only) VDD1 Supply Current IDD1 (10) 2.2 3.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 0.7 1.1 mA 5 MHz logic signal freq. 25 Mbps (CR Grade Only)
VDD1 Supply Current IDD1 (25) 5.2 7.7 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 1.5 2.0 mA 12.5 MHz logic signal freq. ADuM1201 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. 10 Mbps (BR and CR Grades Only) VDD1 Supply Current IDD1 (10) 1.5 2.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.5 2.2 mA 5 MHz logic signal freq. 25 Mbps (CR Grade Only)
VDD1 Supply Current IDD1 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold VIH 0.7 (VDD1 or VDD2) V
Logic Low Input Threshold VIL 0.3 (VDD1 or VDD2)
Logic High Output Voltages VOAH, VOBH (VDD1 or VDD2) − 0.1 3.0 V IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5 2.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xAR CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns
Maximum Data Rate3 1 Mbps
Propagation Delay4 tPHL, tPLH 50 150 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Change vs. Temperature 11 ps/°C
Propagation Delay Skew5 tPSK 100 ns
Channel-to-Channel Matching6 tPSKCD/tPSKOD 50 ns
Output Rise/Fall Time (10% to 90%) tR/tF 10 ns
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 7 of 28
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM120xBR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
100
ns
Maximum Data Rate3
10
Mbps
Propagation Delay4
tPHL, tPLH
20
60
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
22
ns
Channel-to-Channel Matching
Codirectional Channels6
tPSKCD
3
ns
Opposing Directional Channels6
tPSKOD
22
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
3.0
ns
ADuM120xCR
Minimum Pulse Width2
PW
20
40
ns
Maximum Data Rate3
25
50
Mbps
Propagation Delay4
tPHL, tPLH
20
55
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
16
ns
Channel-to-Channel Matching
Codirectional Channels6
tPSKCD
3
ns
Opposing Directional Channels6
tPSKOD
16
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
3.0
ns
For All Models
Common-Mode Transient Immunity
Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Dynamic Supply Current per Channel8
Input
IDDI (D)
0.10
mA/
Mbps
Output
IDDO (D)
0.03
mA/
Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through Figure 11 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
Power ConsumptionPower Consumption
Figure 6 Figure 6
Figure 8Figure 8
Figure 9
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply current for a given data rate.
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 8 of 28 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION
All voltages are relative to their respective ground; 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range,
unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5.0 V; or VDD1 = 5.0 V, VDD2 = 3.0 V; this does not
apply to ADuM1200W and ADuM1201W automotive grade products. Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
5 V/3 V Operation 0.50 0.6 mA
3 V/5 V Operation 0.26 0.35 mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
5 V/3 V Operation 0.11 0.20 mA
3 V/5 V Operation 0.19 0.25 mA
ADuM1200 Total Supply Current,
Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 1.1 1.4 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.6 1.0 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.2 0.6 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.5 0.8 mA DC to 1 MHz logic signal freq. 10 Mbps (BR and CR Grades Only) VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 4.3 5.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.2 3.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 0.7 1.1 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.3 2.0 mA 5 MHz logic signal freq. 25 Mbps (CR Grade Only)
VDD1 Supply Current IDD1 (25)
5 V/3 V Operation 10 13 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 5.2 7.7 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25)
5 V/3 V Operation 1.5 2.0 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 2.8 3.4 mA 12.5 MHz logic signal freq. ADuM1201 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq. 10 Mbps (BR and CR Grades Only) VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 2.8 3.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.5 2.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 1.5 2.2 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.8 3.5 mA 5 MHz logic signal freq.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 9 of 28
Parameter Symbol Min Typ Max Unit Test Conditions
25 Mbps (CR Grade Only)
VDD1 Supply Current
IDD1 (25)
5 V/3 V Operation
6.3
8.0
mA
12.5 MHz logic signal freq.
3 V/5 V Operation
3.4
4.8
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
5 V/3 V Operation
3.4
4.8
mA
12.5 MHz logic signal freq.
3 V/5 V Operation
6.3
8.0
mA
12.5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB
−10
+0.01
+10
μA
0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
VIH
0.7 (VDD1 or VDD2)
V
Logic Low Input Threshold
VIL
0.3 (VDD1 or VDD2)
V
Logic High Output Voltages
VOAH, VOBH
(VDD1 or VDD2) − 0.1
VDD1 or VDD2
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5
(VDD1 or VDD2) − 0.2
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xAR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
1000
ns
Maximum Data Rate3
1
Mbps
Propagation Delay4
tPHL, tPLH
50
150
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
Change vs. Temperature
11
ps/°C
Propagation Delay Skew5 t
PSK
50
ns
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
10
ns
ADuM120xBR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
100
ns
Maximum Data Rate3
10
Mbps
Propagation Delay4
tPHL, tPLH
15
55
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
22
ns
Channel-to-Channel Matching
Codirectional Channels6
tPSKCD
3
ns
Opposing Directional Channels6
tPSKOD
22
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
5 V/3 V Operation
3.0
ns
3 V/5 V Operation
2.5
ns
ADuM120xCR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
20
40
ns
Maximum Data Rate3
25
50
Mbps
Propagation Delay4
tPHL, tPLH
20
50
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
15
ns
Channel-to-Channel Matching
Codirectional Channels6
tPSKCD
3
ns
Opposing Directional Channels6
tPSKOD
15
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
5 V/3 V Operation
3.0
ns
3 V/5 V Operation
2.5
ns
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 10 of 28
Parameter Symbol Min Typ Max Unit Test Conditions
For All Models
Common-Mode Transient Immunity
Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
5 V/3 V Operation
1.2
Mbps
3 V/5 V Operation
1.1
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
5 V/3 V Operation
0.19
mA/ Mbps
3 V/5 V Operation
0.10
mA/ Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
5 V/3 V Operation
0.03
mA/ Mbps
3 V/5 V Operation
0.05
mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
Power ConsumptionPower Consumption
Figure 6 Figure 6
Figure 8Figure 8
Figure 9
Figure 11
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply current for a given data rate.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 11 of 28
ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION
All voltages are relative to their respective ground; 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V; this applies to ADuM1200W and ADuM1201W automotive grade products.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.50
0.60
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.19
0.25
mA
ADM1200W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.1
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.5
0.8
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
4.3
5.5
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.3
2.0
mA
5 MHz logic signal freq.
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
10
13
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
2.8
3.4
mA
12.5 MHz logic signal freq.
ADM1201W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.8
1.1
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.8
1.1
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
2.8
3.5
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
2.8
3.5
mA
5 MHz logic signal freq.
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
6.3
8.0
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
6.3
8.0
mA
12.5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB
−10
+0.01
+10
μA
0 ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
VIH
0.7 (VDD1 or VDD2)
V
Logic Low Input Threshold
VIL
0.3 (VDD1 or VDD2)
V
Logic High Output Voltages
VOAH, VOBH
(VDD1 or VDD2) − 0.1
5.0
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5
4.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xWSRZ
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
1000
ns
Maximum Data Rate3
1
Mbps
Propagation Delay4 t
PHL, tPLH
20
150
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
Propagation Delay Skew5
tPSK
100
ns
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 12 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 20 50 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns
Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 15 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns
ADuM120xWURZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 45 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns
Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 15 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns
For All Models Common-Mode Transient Immunity Logic High Output7 |CMH| 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V
Logic Low Output7 |CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Dynamic Supply Current per Channel8
Input IDDI (D) 0.19 mA/ Mbps
Output IDDO (D) 0.05 mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 13 of 28
ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION
All voltages are relative to their respective ground; 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products.
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.26
0.35
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.11
0.20
mA
ADM1200W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.6
1.0
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.2
0.6
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
2.2
3.4
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
0.7
1.1
mA
5 MHz logic signal freq.
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
5.2
7.7
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
1.5
2.0
mA
12.5 MHz logic signal freq.
ADM1201W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.4
0.8
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.4
0.8
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
1.5
2.2
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.5
2.2
mA
5 MHz logic signal freq.
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
3.4
4.8
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
3.4
4.8
mA
12.5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB
−10
+0.01
+10
μA
0 ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
VIH
0.7 (VDD1 or VDD2)
V
Logic Low Input Threshold
VIL
0.3 (VDD1 or VDD2)
Logic High Output Voltages
VOAH, VOBH
(VDD1 or VDD2) − 0.1
3.0
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5
2.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xWSRZ
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
1000
ns
Maximum Data Rate3
1
Mbps
Propagation Delay4 t
PHL, tPLH
20
150
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
Propagation Delay Skew5 t
PSK
100
ns
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 14 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 20 60 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 22 ns
Channel-to-Channel Matching
Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 22 ns
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns
ADuM120xWCR CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 55 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 16 ns Channel-to-Channel Matching
Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 16 ns Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns For All Models Common-Mode Transient Immunity Logic High Output7 |CMH| 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Logic Low Output7 |CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.1 Mbps
Dynamic Supply Current per Channel8
Input IDDI (D) 0.10 mA/ Mbps
Output IDDO (D) 0.03 mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulsewidth distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulsewidth distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 15 of 28 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION
All voltages are relative to their respective ground; 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation; all
minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications
are at TA = 25°C; VDD1 = 5.0 V, VDD2 = 3.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products. Table 6.
Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q) 0.50 0.6 mA
Output Supply Current per Channel, Quiescent
IDDO (Q) 0.11 0.20 mA
ADuM1200W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.1 1.4 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.2 0.6 mA DC to 1 MHz logic signal freq. 10 Mbps (TRZ and URZ Grades Only) VDD1 Supply Current IDD1 (10) 4.3 5.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 0.7 1.1 mA 5 MHz logic signal freq. 25 Mbps (URZ Grade Only) VDD1 Supply Current IDD1 (25) 10 13 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 1.5 2.0 mA 12.5 MHz logic signal freq. ADuM1201W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. 10 Mbps (TRZ and URZ Grades Only) VDD1 Supply Current IDD1 (10) 2.8 3.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.5 2.2 mA 5 MHz logic signal freq. 25 Mbps (URZ Grade Only) VDD1 Supply Current IDD1 (25) 6.3 8.0 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold VIH 0.7 (VDD1 or VDD2) V Logic Low Input Threshold VIL 0.3 (VDD1 or VDD2) V
Logic High Output Voltages VOAH, VOBH (VDD1 or VDD2) − 0.1 VDD1 or VDD2 V IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5 (VDD1 or VDD2) − 0.2 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xWSRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns Maximum Data Rate3 1 Mbps
Propagation Delay4 tPHL, tPLH 15 150 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Propagation Delay Skew5 tPSK 50 ns
Channel-to-Channel Matching6 tPSKCD/ tPSKOD 50 ns
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 16 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 15 55 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 22 ns
Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 22 ns
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns ADuM120xWURZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 50 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 15 ns
Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns For All Models Common-Mode Transient Immunity Logic High Output7 |CMH| 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Logic Low Output7 |CML| 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.2 Mbps
Dynamic Supply Current per Channel8
Input IDDI (D) 0.19 mA/ Mbps
Output IDDO (D) 0.03 mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 17 of 28 ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION
All voltages are relative to their respective ground; 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products. Table 7.
Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q) 0.26 0.35 mA
Output Supply Current per Channel, Quiescent
IDDO (Q) 0.19 0.25 mA
ADuM1200W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.6 1.0 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.5 0.8 mA DC to 1 MHz logic signal freq. 10 Mbps (TRZ and URZ Grades Only) VDD1 Supply Current IDD1 (10) 2.2 3.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.3 2.0 mA 5 MHz logic signal freq. 25 Mbps (URZ Grade Only) VDD1 Supply Current IDD1 (25) 5.2 7.7 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 2.8 3.4 mA 12.5 MHz logic signal freq. ADuM1201W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq. 10 Mbps (TRZ and URZ Grades Only) VDD1 Supply Current IDD1 (10) 1.5 2.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 2.8 3.5 mA 5 MHz logic signal freq. 25 Mbps (URZ Grade Only) VDD1 Supply Current IDD1 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 6.3 8.0 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold VIH 0.7 (VDD1 or VDD2) V Logic Low Input Threshold VIL 0.3 (VDD1 or VDD2) V
Logic High Output Voltages VOAH, VOBH (VDD1 or VDD2) − 0.1 VDD1 or VDD2 V IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5 (VDD1 or VDD2) − 0.2 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xWSRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns Maximum Data Rate3 1 Mbps
Propagation Delay4 tPHL, tPLH 15 150 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Propagation Delay Skew5 tPSK 50 ns
Channel-to-Channel Matching6 tPSKCD/
tPSKOD
50 ns Output Rise/Fall Time (10% to 90%) tR/tF 3 ns
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 18 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 15 55 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 22 ns
Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 22 ns
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns ADuM120xWURZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 50 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 15 ns
Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns For All Models Common-Mode Transient Immunity Logic High Output7 |CMH| 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Logic Low Output7 |CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel8
IDDI (D) 0.10 mA/ Mbps
Output Dynamic Supply Current per Channel8
IDDO (D) 0.05 mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 19 of 28 PACKAGE CHARACTERISTICS Table 8.
Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-to-Output)1 RI-O 1012 Ω Capacitance (Input-to-Output)1 CI-O 1.0 pF f = 1 MHz Input Capacitance CI 4.0 pF IC Junction-to-Case Thermal Resistance, Side 1 θJCI 46 °C/W Thermocouple located at center of package underside IC Junction-to-Case Thermal Resistance, Side 2 θJCO 41 °C/W 1 The device is considered a 2-terminal device; Pin 1, Pin, 2, Pin 3, and Pin 4 are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together.
REGULATORY INFORMATION
The ADuM1200/ADuM1201 and ADuM1200W/ADuM1201W are approved by the organizations listed in Table 9; refer to Table 14 and
the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 9.
UL CSA VDE Recognized Under 1577 Component Recognition Program1
Approved under CSA Component Acceptance Notice #5A; approval pending for ADuM1200W/
ADuM1201W automotive 125°C temperature grade
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-122
Single/Basic 2500 V rms Isolation Voltage Basic insulation per CSA 60950-1-03 and
IEC 60950-1, 400 V rms (566 peak) maximum working voltage Functional insulation per CSA 60950-1-03 and
IEC 60950-1, 800 V rms (1131 V peak) maximum
working voltage Reinforced insulation, 560 V peak
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM120x is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA). 2 In accordance with DIN V VDE V 0884-10, each ADuM120x is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 10.
Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 4.90 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 4.01 min mm Measured from input terminals to output terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 20 of 28
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. Note that the asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage.
Table 11.
Description
Conditions
Symbol
Characteristic
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
I to IV
For Rated Mains Voltage ≤ 300 V rms
I to III
For Rated Mains Voltage ≤ 400 V rms
I to II
Climatic Classification
40/105/21
Pollution Degree per DIN VDE 0110, Table 1
2
Maximum Working Insulation Voltage
VIORM
560
V peak
Input-to-Output Test Voltage, Method B1
VIORM × 1.875 = VPR, 100% production test, tm = 1 second, partial discharge < 5 pC
VPR
1050
V peak
Input-to-Output Test Voltage, Method A
VIORM × 1.6 = VPR, tm = 60 seconds, partial discharge < 5 pC
VPR
After Environmental Tests Subgroup 1
896
V peak
After Input and/or Safety Test Subgroup 2 and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 seconds, partial discharge < 5 pC
672
V peak
Highest Allowable Overvoltage
Transient overvoltage, tTR = 10 seconds
VTR
4000
V peak
Safety-Limiting Values
Maximum value allowed in the event of a failure (see Figure 3)
Case Temperature
TS
150
°C
Side 1 Current
IS1
160
mA
Side 2 Current
IS2
170
mA
Insulation Resistance at TS
VIO = 500 V
RS
>109
Ω
CASE TEMPERATURE (°C)SAFETY-LIMITING CURRENT (mA)002001801008060402050100150200SIDE #1SIDE #204642-003120140160
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values on Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 12. Parameter
Rating
Operating Temperature (TA)
−40°C to +105°C
Operating Temperature (TA)2
−40°C to +125°C
Supply Voltages (VDD1, VDD2)1, 3
2.7 V to 5.5 V
Supply Voltages (VDD1, VDD2)23
3.0 V to 5.5 V
Input Signal Rise and Fall Times
1.0 ms
Does not apply to ADuM1200W and ADuM1201W automotive grade products. 2 Applies to
ADuM1200W and ADuM1201W automotive grade products. 3 All voltages are relative to their respective ground. See the DC Correctnes
s unity to externamagnetic fields.
and Magnetic Field Immunity section for information on imml
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 21 of 28
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 13.
Parameter
Rating
Storage Temperature (TST)
−55°C to +150°C
Ambient Operating Temperature (TA)1
−40°C to +105°C
Ambient Operating Temperature (TA)2
−40°C to +125°C
Supply Voltages (VDD1, VDD2)3
−0.5 V to +7.0 V
Input Voltages (VIA, VIB)3, 4
−0.5 V to VDDI + 0.5 V
Output Voltages (VOA, VOB)3, 4
−0.5 V to VDDO + 0.5 V
Average Output Current per Pin (IO)5
−11 mA to +11 mA
Common-Mode Transients (CML, CMH)6
−100 kV/μs to +100 kV/μs
1 Does not apply to ADuM1200W and ADuM1200W automotive grade products.
2 Applies to ADuM1200W and ADuM1201W automotive grade products.
3 All voltages are relative to their respective ground.
4 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively.
5 See for maximum rated current values for various temperatures.
Figure 3
6 Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the absolute maximum ratings can cause latch-up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Table 14. Maximum Continuous Working Voltage1
Parameter
Max
Unit
Constraint
AC Voltage, Bipolar Waveform
565
V peak
50-year minimum lifetime
AC Voltage, Unipolar Waveform
Functional Insulation
1131
V peak
Maximum approved working voltage per IEC 60950-1
Basic Insulation
560
V peak
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
DC Voltage
Functional Insulation
1131
V peak
Maximum approved working voltage per IEC 60950-1
Basic Insulation
560
V peak
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 22 of 28 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 8
2 7
3 6
4 5
TOP VIEW
(Not to Scale)
ADuM1200
04642-004
VDD1
VIA
VIB
GND1
VDD2
VOA
VOB
GND2
04642-005
1 8
2 7
3 6
4 5
TOP VIEW
(Not to Scale)
ADuM1201
VDD1
VOA
VIB
GND1
VDD2
VIA
VOB
GND2
Figure 4. ADuM1200 Pin Configuration Figure 5. ADuM1201 Pin Configuration
Table 15. ADuM1200 Pin Function Descriptions
Pin
No. Mnemonic Description 1 VDD1 Supply Voltage for Isolator Side 1. 2 VIA Logic Input A.
3 VIB Logic Input B.
4 GND1 Ground 1. Ground Reference for Isolator Side 1. 5 GND2 Ground 2. Ground Reference for Isolator Side 2.
6 VOB Logic Output B.
7 VOA Logic Output A.
8 VDD2 Supply Voltage for Isolator Side 2. Table 16. ADuM1201 Pin Function Descriptions
Pin
No. Mnemonic Description 1 VDD1 Supply Voltage for Isolator Side 1. 2 VOA Logic Output A.
3 VIB Logic Input B.
4 GND1 Ground 1. Ground Reference for Isolator Side 1. 5 GND2 Ground 2. Ground Reference for Isolator Side 2. 6 VOB Logic Output B.
7 VIA Logic Input A.
8 VDD2 Supply Voltage for Isolator Side 2. Table 17. ADuM1200 Truth Table (Positive Logic)
VIA Input VIB Input VDD1 State VDD2 State VOA Output VOB Output Notes H H Powered Powered H H
L L Powered Powered L L
H L Powered Powered H L
L H Powered Powered L H
X X Unpowered Powered H H Outputs return to the input state within
1 μs of VDDI power restoration. X X Powered Unpowered Indeterminate Indeterminate Outputs return to the input state within
1 μs of VDDO power restoration. Table 18. ADuM1201 Truth Table (Positive Logic)
VIA Input VIB Input VDD1 State VDD2 State VOA Output VOB Output Notes H H Powered Powered H H
L L Powered Powered L L
H L Powered Powered H L
L H Powered Powered L H
X X Unpowered Powered Indeterminate H Outputs return to the input state within
1 μs of VDDI power restoration. X X Powered Unpowered H Indeterminate Outputs return to the input state within
1 μs of VDDO power restoration.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 23 of 28
04642-006
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. Typical Input Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation
04642-007DATA RATE (
Mbps)00102030
Figure 7. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load)
04642-0 DATA RATE (Mbps)0102030
Figure 8. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load)
04642-009DATA RATE (
Mbps)CURRENT (mA)0015105201020305V3V
Figure 9. Typical ADuM1200 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
04642-010DATA RATE (
Mbps)CURRENT (mA)0032141020305V3V
Figure 10. Typical ADuM1200 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
04642-011DATA RATE (
Mbps)CURRENT (mA)00628101020305V3V4
Figure 11. Typical ADuM1201 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 24 of 28 APPLICATIONS INFORMATION
PCB LAYOUT The ADuM120x digital isolators require no external interface
circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm. See the AN-1109 Application Note for board layout guidelines. PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation delay
to a logic high output.
INPUT (VIx)
OUTPUT (VOx)
tPLH tPHL
50%
50%
04642-012
Figure 12. Propagation Delay Parameters Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a
single ADuM120x component. Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM120x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input send narrow (~1 ns) pulses to the decoder via the transformer. The
decoder is bistable and is therefore either set or reset by the pulses,
indicating input logic transitions. In the absence of logic transi-
tions of more than ~1 μs at the input, a periodic set of refresh
pulses indicative of the correct input state is sent to ensure dc
correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output
is forced to a default state (see Table 17 and Table 18) by the
watchdog timer circuit. The ADuM120x are extremely immune to external magnetic
fields. The limitation on the magnetic field immunity of the ADuM120x is set by the condition in which induced voltage in
the receiving coil of the transformer is sufficiently large enough to either falsely set or reset the decoder. The following analysis
defines the conditions under which this can occur. The 3 V
operating condition of the ADuM120x is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ/dt)ΣΠrn
2; n = 1, 2, … , N
where: β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM120x and
an imposed requirement that the induced voltage be 50% at
most of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 13.
MAGNETIC FIELD FREQUENCY (Hz)
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
0.001
1M
10
0.01
1k 10k 10M
0.1
1
100M 100k
04642-013
Figure 13. Maximum Allowable External Magnetic Flux Density
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 25 of 28
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and has the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM120x transformers. Figure 14 expresses these allowable current magnitudes as a function of frequency for selected distances. As seen, the ADuM120x are extremely immune and can be affected only by extremely large currents operating very close to the component at a high frequency. For the 1 MHz example, a 0.5 kA current would have to be placed 5 mm away from the ADuM120x to affect the operation of the component.
MAGNETIC FIELD FREQUENCY (Hz)MAXIMUM ALLOWABLE CURRENT (kA)10001001010.10.011k10k100M100k1M10MDISTANCE = 5mmDISTANCE = 1mDISTANCE = 100mm04642-014
Figure 14. Maximum Allowable Current for Various Current-to-ADuM120x Spacings
Note that, at combinations of strong magnetic fields and high frequencies, any loops formed by PCB traces can induce suffi-ciently large error voltages to trigger the threshold of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM120x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel.
For each input channel, the supply current is given by
IDDI = IDDI (Q) f ≤ 0.5fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5fr
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5fr
IDDO = (IDDO (D) + (0.5 × 10−3) × CLVDDO) × (2f − fr) + IDDO (Q) f > 0.5fr
where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz, half of the input data rate, NRZ signaling). fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA).
To calculate the total IDD1 and IDD2 supply currents, the supply currents for each input and output channel corresponding to IDD1 and IDD2 are calculated and totaled. Figure 6 and Figure 7 provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 8 provides per-channel supply current as a function of data rate for a 15 pF output condition. Figure 9 through Figure 11 provide total VDD1 and VDD2 supply current as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 26 of 28
In the case of unipolar ac or dc voltage, the stress on the insu-lation is significantly lower, which allows operation at higher working voltages yet still achieves a 50-year service life. The working voltages listed in Table 14 can be applied while main-taining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross- insulation voltage waveform that does not conform to Figure 16 or Figure 17 is to be treated as a bipolar ac waveform, and its peak voltage is to be limited to the 50-year lifetime voltage value listed in Table 14.
INSULATION LIFETIME
All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insu-lation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM120x.
Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Accel-eration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 14 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working volt-ages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.
Note that the voltage presented in Figure 16 is shown as sinu-soidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. 0VRATED PEAK VOLTAGE04642-021
Figure 15. Bipolar AC Waveform
The insulation lifetime of the ADuM120x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 15, Figure 16, and Figure 17 illustrate these different isolation voltage waveforms, respectively.
0VRATED PEAK VOLTAGE04642-022
Figure 16. Unipolar AC Waveform
Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage.
0VRATED PEAK VOLTAGE04642-023
Figure 17. DC Waveform
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 27 of 28 OUTLINE DIMENSIONS
CONTROLLINGDIMENSIONSAREINMILLIMETERS;INCHDIMENSIONS
(IN PARENTHESES)AREROUNDED-OFFMILLIMETEREQUIVALENTSFOR
REFERENCEONLYANDARENOTAPPROPRIATEFORUSEINDESIGN.
COMPLIANTTOJEDECSTANDARDSMS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25(0.0098)
0.10(0.0040)
1 4
8 5
5.00 (0.1968)
4.80 (0.1890)
4.00(0.1574)
3.80(0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51(0.0201)
0.31(0.0122)
COPLANARITY
0.10
Figure 18. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1, 2
Number
of Inputs, VDD1 Side
Number
of Inputs,
VDD2 Side
Maximum
Data Rate (Mbps)
Maximum Propagation Delay, 5 V (ns) Maximum
Pulse Width Distortion (ns)
Temperature
Range Package
Option3
ADuM1200AR 2 0 1 150 40 −40°C to +105°C R-8
ADuM1200ARZ 2 0 1 150 40 −40°C to +105°C R-8
ADuM1200ARZ-RL7 2 0 1 150 40 −40°C to +105°C R-8
ADuM1200BR 2 0 10 50 3 −40°C to +105°C R-8
ADuM1200BR-RL7 2 0 10 50 3 −40°C to +105°C R-8
ADuM1200BRZ 2 0 10 50 3 −40°C to +105°C R-8
ADuM1200BRZ-RL7 2 0 10 50 3 −40°C to +105°C R-8
ADuM1200CR 2 0 25 45 3 −40°C to +105°C R-8
ADuM1200CR-RL7 2 0 25 45 3 −40°C to +105°C R-8
ADuM1200CRZ 2 0 25 45 3 −40°C to +105°C R-8
ADuM1200CRZ-RL7 2 0 25 45 3 −40°C to +105°C R-8
ADuM1200WSRZ 2 0 1 150 40 −40°C to +125°C R-8
ADuM1200WSRZ-RL7 2 0 1 150 40 −40°C to +125°C R-8
ADuM1200WTRZ 2 0 10 50 3 −40°C to +125°C R-8
ADuM1200WTRZ-RL7 2 0 10 50 3 −40°C to +125°C R-8
ADuM1200WURZ 2 0 25 45 3 −40°C to +125°C R-8
ADuM1200WURZ-RL7 2 0 25 45 3 −40°C to +125°C R-8
ADuM1201AR 1 1 1 150 40 −40°C to +105°C R-8
ADuM1201AR-RL7 1 1 1 150 40 −40°C to +105°C R-8
ADuM1201ARZ 1 1 1 150 40 −40°C to +105°C R-8
ADuM1201ARZ-RL7 1 1 1 150 40 −40°C to +105°C R-8
ADuM1201BR 1 1 10 50 3 −40°C to +105°C R-8
ADuM1201BR-RL7 1 1 10 50 3 −40°C to +105°C R-8
ADuM1201BRZ 1 1 10 50 3 −40°C to +105°C R-8
ADuM1201BRZ-RL7 1 1 10 50 3 −40°C to +105°C R-8
ADuM1201CR 1 1 25 45 3 −40°C to +105°C R-8
ADuM1201CRZ 1 1 25 45 3 −40°C to +105°C R-8
ADuM1201CRZ-RL7 1 1 25 45 3 −40°C to +105°C R-8
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 28 of 28 Model1, 2
Number
of Inputs, VDD1 Side
Number
of Inputs, VDD2 Side
Maximum
Data Rate (Mbps)
Maximum Propagation Delay, 5 V (ns) Maximum
Pulse Width Distortion (ns)
Temperature
Range Package
Option3
ADuM1201WSRZ 1 1 1 150 40 −40°C to +125°C R-8
ADuM1201WSRZ-RL7 1 1 1 150 40 −40°C to +125°C R-8
ADuM1201WTRZ 1 1 10 50 3 −40°C to +125°C R-8
ADuM1201WTRZ-RL7 1 1 10 50 3 −40°C to +125°C R-8
ADuM1201WURZ 1 1 25 45 3 −40°C to +125°C R-8
ADuM1201WURZ-RL7 1 1 25 45 3 −40°C to +125°C R-8
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 R-8 = 8-lead narrow-body SOIC_N. AUTOMOTIVE PRODUCTS
The ADuM1200W/ADuM1201W models are available with controlled manufacturing to support the quality and reliability requirements
of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models. ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04642-0-3/12(I)
High Precision
5 V Reference
AD586
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Laser trimmed to high accuracy
5.000 V ±2.0 mV (M grade)
Trimmed temperature coefficient
2 ppm/°C max, 0°C to 70°C (M grade)
5 ppm/°C max, −40°C to +85°C (B and L grades)
10 ppm/°C max, −55°C to +125°C (T grade)
Low noise, 100 nV/√Hz
Noise reduction capability
Output trim capability
MIL-STD-883-compliant versions available
Industrial temperature range SOICs available
Output capable of sourcing or sinking 10 mA
GENERAL DESCRIPTION
The AD586 represents a major advance in state-of-the-art monolithic voltage references. Using a proprietary ion-implanted buried Zener diode and laser wafer trimming of high stability thin-film resistors, the AD586 provides outstanding perform-ance at low cost.
The AD586 offers much higher performance than most other 5 V references. Because the AD586 uses an industry-standard pinout, many systems can be upgraded instantly with the AD586.
The buried Zener approach to reference design provides lower noise and drift than band gap voltage references. The AD586 offers a noise reduction pin that can be used to further reduce the noise level generated by the buried Zener.
The AD586 is recommended for use as a reference for 8-, 10-, 12-, 14-, or 16-bit DACs that require an external precision reference. The device is also ideal for successive approximation or integrating ADCs with up to 14 bits of accuracy and, in general, can offer better performance than the standard on-chip references.
The AD586J, AD586K, AD586L, and AD586M are specified for operation from 0°C to 70°C; the AD586A and AD586B are specified for −40°C to +85°C operation; and the AD586S and AD586T are specified for −55°C to +125°C operation.
The AD586J, AD586K, AD586L, and AD586M are available in an 8-lead PDIP; the AD586J, AD586K, AD586L, AD586A, and AD586B are available in an 8-lead SOIC package; and the AD586J, AD586K, AD586L, AD586S, and AD586T are available in an 8-lead CERDIP package. A1RSRZ1RZ2RFRTRIAD586GNDVINNOISE REDUCTIONVOUTTRIMNOTES1.PINS 1, 3, AND 7 ARE INTERNAL TEST POINTS.MAKE NO CONNECTIONS TO THESE POINTS.6548200529-001
Figure 1.
PRODUCT HIGHLIGHTS
1. Laser trimming of both initial accuracy and temperature coefficients results in very low errors over temperature without the use of external components. The AD586M has a maximum deviation from 5.000 V of ±2.45 mV between 0°C and 70°C, and the AD586T guarantees ±7.5 mV maximum total error between −55°C and +125°C.
2. For applications requiring higher precision, an optional fine-trim connection is provided.
3. Any system using an industry-standard pinout reference can be upgraded instantly with the AD586.
4. Output noise of the AD586 is very low, typically 4 μV p-p. A noise reduction pin is provided for additional noise filtering using an external capacitor.
5. The AD586 is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or the current AD586/883B data sheet for detailed specifications.
AD586
Rev. G | Page 2 of 16
TABLE OF CONTENTS
Specifications.....................................................................................3
AD586J, AD586K/AD586A, AD586L/AD586B.......................3
AD586M, AD586S, AD586T.......................................................4
Absolute Maximum Ratings............................................................5
ESD Caution..................................................................................5
Pin Configurations and Function Descriptions...........................6
Theory of Operation........................................................................7
Applying the AD586.....................................................................7
Noise Performance and Reduction............................................7
Turn-on Time................................................................................8
Dynamic Performance.................................................................8
Load Regulation............................................................................9
Temperature Performance............................................................9
Negative Reference Voltage from an AD586...........................10
Using the AD586 with Converters...........................................10
5 V Reference with Multiplying CMOS DACs or ADCs......11
Stacked Precision References for Multiple Voltages..............11
Precision Current Source..........................................................11
Precision High Current Supply................................................11
Outline Dimensions.......................................................................13
Ordering Guide..........................................................................14
REVISION HISTORY
3/05—Rev. F to Rev. G Updated Format..................................................................Universal Split Specifications Table into Table 1 and Table 2.......................3 Changes to Table 1............................................................................3 Added Figure 2 and Figure 4...........................................................6 Updated Outline Dimensions.......................................................13 Changes to Ordering Guide..........................................................14
1/04—Rev. E to Rev. F Changes to ORDERING GUIDE...................................................3
7/03—Rev. D to Rev. E Removed AD586J CHIPS..................................................Universal Updated ORDERING GUIDE........................................................3 Change to Figure 3...........................................................................4 Updated Figure 12............................................................................7 Updated OUTLINE DIMENSIONS..............................................9
4/01—Rev. C to Rev. D Changed Figure 10 to Table 1 (Maximum Output Change in mV)...............................................6
11/95—Revision 0: Initial Version
AD586
Rev. G | Page 3 of 16
SPECIFICATIONS
AD586J, AD586K/AD586A, AD586L/AD586B
@ TA = 25°C, VIN = 15 V, unless otherwise noted. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed, although only those shown in boldface are tested on all production units, unless otherwise specified.
Table 1.
AD586J
AD586K/AD586A
AD586L/AD586B
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
OUTPUT VOLTAGE
4.980
5.020
4.995
5.005
4.9975
5.0025
V
OUTPUT VOLTAGE DRIFT1
0°C to 70°C
25
15
5
ppm/°C
−55°C to +125°C
ppm/°C
GAIN ADJUSTMENT
+6
+6
+6
%
−2
−2
−2
%
LINE REGULATION1
10.8 V < + VIN < 36 V
TMIN to TMAX
±100
±100
±100
μV/V
11.4 V < +VIN < 36 V
TMIN to TMAX
μV/V
LOAD REGULATION1
Sourcing 0 mA < IOUT < 10 mA
25°C
100
100
100
μV/mA
TMIN to TMAX
100
100
100
μV/mA
Sinking −10 mA < IOUT < 0 mA
25°C
400
400
400
μV/mA
QUIESCENT CURRENT
2
3
2
3
2
3
mA
POWER CONSUMPTION
30
30
30
mW
OUTPUT NOISE
0.1 Hz to 10 Hz
4
4
4
μV p-p
Spectral Density, 100 Hz
100
100
100
nV/√Hz
LONG-TERM STABILITY
15
15
15
ppm/1000 hr
SHORT-CIRCUIT CURRENT-TO-GROUND
45
60
45
60
45
60
mA
TEMPERATURE RANGE
Specified Performance2
0
70
0
−40
(K grade)
(A grade)
70
+85
0
−40
(L grade)
(B grade)
70
+85
°C
°C
Operating Performance3
−40
+85
−40
+85
−40
+85
°C
1 Maximum output voltage drift is guaranteed for all packages and grades. CERDIP packaged parts are also 100°C production tested.
2 Lower row shows specified performance for A and B grades.
3 The operating temperature range is defined as the temperature extremes at which the device will still function. Parts may deviate from their specified performance outside their specified temperature range.
AD586
Rev. G | Page 4 of 16
AD586M, AD586S, AD586T
@ TA = 25°C, VIN = 15 V, unless otherwise noted. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed, although only those shown in boldface are tested on all production units, unless otherwise specified.
Table 2.
AD586M
AD586S
AD586T
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
OUTPUT VOLTAGE
4.998
5.002
4.990
5.010
4.9975
5.0025
V
OUTPUT VOLTAGE DRIFT1
0°C to 70°C
2
ppm/°C
−55°C to +125°C
20
10
ppm/°C
GAIN ADJUSTMENT
+6
+6
+6
%
−2
−2
−2
%
LINE REGULATION1
10.8 V < +VIN < 36 V
TMIN to TMAX
±100
μV/V
11.4 V < +VIN < 36 V
TMIN to TMAX
±150
±150
μV/V
LOAD REGULATION1
Sourcing 0 mA < IOUT < 10 mA
25°C
100
150
150
μV/mA
TMIN to TMAX
100
150
150
μV/mA
Sinking −10 mA < IOUT < 0 mA
25°C
400
400
400
μV/mA
QUIESCENT CURRENT
2
3
2
3
2
3
mA
POWER CONSUMPTION
30
30
30
mW
OUTPUT NOISE
0.1 Hz to 10 Hz
4
4
4
μV p-p
Spectral Density, 100 Hz
100
100
100
nV/√Hz
LONG-TERM STABILITY
15
15
15
ppm/1000 hr
SHORT-CIRCUIT CURRENT-TO-GROUND
45
60
45
60
45
60
mA
TEMPERATURE RANGE
Specified Performance2
0
70
−55
+125
−55
+125
°C
Operating Performance3
−40
+85
−55
+125
−55
+125
°C
1 Maximum output voltage drift is guaranteed for all packages and grades. CERDIP packaged parts are also 100°C production tested.
2 Lower row shows specified performance for A and B grades.
3 The operating temperature range is defined as the temperature extremes at which the device will still function. Parts may deviate from their specified performance outside their specified temperature range.
AD586
Rev. G | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
VIN to Ground
36 V
Power Dissipation (25°C)
500 mW
Storage Temperature
−65°C to +150°C
Lead Temperature (Soldering, 10 sec)
300°C
Package Thermal Resistance
θJC
22°C/W
θJA
110°C/W
Output Protection
Output safe for indefinite short to ground or VIN.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
AD586
Rev. G | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1TP DENOTES FACTORY TEST POINT.NO CONNECTIONS, EXCEPT DUMMY PCB PAD,SHOULD BE MADE TO THESE POINTS.TP11VIN2TP13GND4NOISEREDUCTION8TP17VOUT6TRIM5AD586TOP VIEW(Not to Scale)00529-002
Figure 2. Pin Configuration (N-8)
1TP DENOTES FACTORY TEST POINT.NO CONNECTIONS, EXCEPT DUMMY PCB PAD,SHOULD BE MADE TO THESE POINTS.00529-003TP11VIN2TP13GND4NOISEREDUCTION8TP17VOUT6TRIM5AD586TOP VIEW(Not to Scale)
Figure 3. Pin Configuration (Q-8)
1TP DENOTES FACTORY TEST POINT.NO CONNECTIONS, EXCEPT DUMMY PCB PAD,SHOULD BE MADE TO THESE POINTS.00529-004TP11VIN2TP13GND4NOISEREDUCTION8TP17VOUT6TRIM5AD586TOP VIEW(Not to Scale)
Figure 4. Pin Configuration (R-8)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
TP1
Factory Trim Pad (No Connect).
2
VIN
Input Voltage.
3
TP1
Factory Trim Pad (No Connect).
4
GND
Ground.
5
TRIM
Optional External Fine Trim. See the Applying the AD586 section.
6
VOUT
Output Voltage.
7
TP1
Factory Trim Pad (No Connect).
8
NOICE REDUCTION
Optional Noise Reduction Filter with External 1μF Capacitor to Ground.
AD586
Rev. G | Page 7 of 16
THEORY OF OPERATION
The AD586 consists of a proprietary buried Zener diode refer-ence, an amplifier to buffer the output, and several high stability thin-film resistors, as shown in the block diagram in Figure 5. This design results in a high precision monolithic 5 V output reference with initial offset of 2.0 mV or less. The temperature compensation circuitry provides the device with a temperature coefficient of under 2 ppm/°C.
Using the bias compensation resistor between the Zener output and the noninverting input to the amplifier, a capacitor can be added at the noise reduction pin (Pin 8) to form a low-pass filter and reduce the noise contribution of the Zener to the circuit. A1RSRZ1RZ2RFRTRIAD586GNDVINNOISE REDUCTIONVOUTTRIMNOTES1.PINS 1, 3, AND 7 ARE INTERNAL TEST POINTS.MAKE NO CONNECTIONS TO THESE POINTS.6548200529-001
Figure 5. Functional Block Diagram
APPLYING THE AD586
The AD586 is simple to use in virtually all precision reference applications. When power is applied to Pin 2 and Pin 4 is grounded, Pin 6 provides a 5 V output. No external components are required; the degree of desired absolute accuracy is achieved simply by selecting the required device grade. The AD586 requires less than 3 mA quiescent current from an operating supply of 12 V or 15 V.
An external fine trim may be desired to set the output level to exactly 5.000 V (calibrated to a main system reference). System calibration may also require a reference voltage that is slightly different from 5.000 V, for example, 5.12 V for binary applica-tions. In either case, the optional trim circuit shown in Figure 6 can offset the output by as much as 300 mV with minimal effect on other device characteristics. AD586GNDVINCN1μFVOTRIMOPTIONALNOISEREDUCTIONCAPACITORVINNOISEREDUCTIONOUTPUT10kΩ6524800529-005
Figure 6. Optional Fine-Trim Configuration
NOISE PERFORMANCE AND REDUCTION
The noise generated by the AD586 is typically less than 4 μV p-p over the 0.1 Hz to 10 Hz band. Noise in a 1 MHz bandwidth is approximately 200 μV p-p. The dominant source of this noise is the buried Zener, which contributes approximately 100 nV/√Hz. By comparison, contribution by the op amp is negligible. Figure 7 shows the 0.1 Hz to 10 Hz noise of a typical AD586. The noise measurement is made with a band-pass filter made of a 1-pole high-pass filter with a corner frequency at 0.1 Hz, and a 2-pole low-pass filter with a corner frequency at 12.6 Hz, to create a filter with a 9.922 Hz bandwidth.
If further noise reduction is desired, an external capacitor can be added between the noise reduction pin and ground, as shown in Figure 6. This capacitor, combined with the 4 kΩ RS and the Zener resistances, forms a low-pass filter on the output of the Zener cell. A 1 μF capacitor will have a 3 dB point at 12 Hz, and will reduce the high frequency (to 1 MHz) noise to about 160 μV p-p. Figure 8 shows the 1 MHz noise of a typical AD586, both with and without a 1 μF capacitor. 00529-0061μF5s1μF
Figure 7. 0.1 Hz to 10 Hz Noise
AD586
Rev. G | Page 8 of 16
00529-007CN =
1μFNO CN50μS200μV
Figure 8. Effect of 1 μF Noise Reduction Capacitor on Broadband Noise
TURN-ON TIME
Upon application of power (cold start), the time required for the output voltage to reach its final value within a specified error band is defined as the turn-on settling time. Two compo-nents normally associated with this are the time for the active circuits to settle, and the time for the thermal gradients on the chip to stabilize. Figure 9, Figure 10, and Figure 11 show the turn-on characteristics of the AD586. It shows the settling to be about 60 μs to 0.01%. Note the absence of any thermal tails when the horizontal scale is expanded to l ms/cm in Figure 10.
Output turn-on time is modified when an external noise reduc-tion capacitor is used. When present, this capacitor acts as an additional load to the current source of the internal Zener diode, resulting in a somewhat longer turn-on time. In the case of a 1 μF capacitor, the initial turn-on time is approximately 400 ms to 0.01% (see Figure 11). 00529-008VINVOUT10V1mV20μS
Figure 9. Electrical Turn-On 00529-009VINVOUT10V5V1mS
Figure 10. Extended Time Scale 00529-010VINVOUT10V1mV100mS
Figure 11. Turn-On with 1μF CN Characteristics
DYNAMIC PERFORMANCE
The output buffer amplifier is designed to provide the AD586 with static and dynamic load regulation superior to less com-plete references.
Many ADCs and DACs present transient current loads to the reference, and poor reference response can degrade the per-formance of the converter.
Figure 12, Figure 13, and Figure 14 display the characteristics of the AD586 output amplifier driving a 0 mA to 10 mA load. AD586VL5V0VVOUT500Ω3.5V00529-011
Figure 12. Transient Load Test Circuit
AD586
Rev. G | Page 9 of 16
00529-012VLVOUT5V50mV1μS
Figure 13. Large-Scale Transient Response 00529-013VLVOUT5V1mV2μS
Figure 14. Fine-Scale Setting for Transient Load
In some applications, a varying load may be both resistive and capacitive in nature, or the load may be connected to the AD586 by a long capacitive cable.
Figure 15 and Figure 16 display the output amplifier characteristics driving a 1000 pF, 0 mA to 10 mA load. AD586VL5V0VVOUTCL1000pF500Ω3.5V00529-014
Figure 15. Capacitive Load Transient Response Test Circuit
00529-015CL= 0CL= 1000pF5V200mV1μS
Figure 16. Output Response with Capacitive Load
LOAD REGULATION
The AD586 has excellent load regulation characteristics. Figure 17 shows that varying the load several mA changes the output by a few μV. The AD586 has somewhat better load regulation per-formance sourcing current than sinking current. –6–4–2246810LOAD (mA)0–500–10005001000ΔVOUT (μV)00529-016
Figure 17. Typical Load Regulation Characteristics
TEMPERATURE PERFORMANCE
The AD586 is designed for precision reference applications where temperature performance is critical. Extensive tempera-ture testing ensures that the device maintains a high level of performance over the operating temperature range.
Some confusion exists with defining and specifying reference voltage error over temperature. Historically, references have been characterized using a maximum deviation per degree Celsius, that is, ppm/°C. However, because of nonlinearities in temperature characteristics that originated in standard Zener references (such as “S” type characteristics), most manufacturers have begun to use a maximum limit error band approach to specify devices. This technique involves measuring the output at three or more different temperatures to specify an output volt-age error band.
AD586
Rev. G | Page 10 of 16
Figure 18 shows the typical output voltage drift for the AD586L and illustrates the test methodology. The box in Figure 18 is bounded on the sides by the operating temperature extremes and on the top and the bottom by the maximum and minimum output voltages measured over the operating temperature range. The slope of the diagonal drawn from the lower left to the upper right corner of the box determines the performance grade of the device. –200204060805.0035.000TEMPERATURE (°C) VMINVMAXVMAX–VMIN(TMAX–TMIN)×5×10–6SLOPETMINTMAXSLOPE = T.C. ===4.3ppm/°C5.0027– 5.0012(70°C– 0)×5×10–600625-017
Figure 18. Typical AD586L Temperature Drift
Each AD586J, AD586K, and AD586L grade unit is tested at 0°C, 25°C, and 70°C. Each AD586SQ and AD586TQ grade unit is tested at −55°C, +25°C, and +125°C. This approach ensures that the variations of output voltage that occur as the temperature changes within the specified range will be contained within a box whose diagonal has a slope equal to the maximum specified drift. The position of the box on the vertical scale will change from device to device as initial error and the shape of the curve vary. The maximum height of the box for the appropriate tem-perature range and device grade is shown in Table 5. Dupli-cation of these results requires a combination of high accuracy and stable temperature control in a test system. Evaluation of the AD586 will produce a curve similar to that in Figure 18, but output readings could vary depending on the test methods and equipment used.
Table 5. Maximum Output Change in mV
Maximum Output Change (mV)
Device Grade
0°C to 70°C
−40°C to +85°C
−55°C to +125°C
AD586J
8.75
AD586K
5.25
AD586L
1.75
AD586M
0.70
AD586A
9.37
AD586B
3.12
AD586S
18.00
AD586T
9.00
NEGATIVE REFERENCE VOLTAGE FROM AN AD586
The AD586 can be used to provide a precision −5.000 V output, as shown in Figure 19. The VIN pin is tied to at least a 6 V supply, the output pin is grounded, and the AD586 ground pin is con-nected through a resistor, RS, to a −15 V supply. The −5 V output is now taken from the ground pin (Pin 4) instead of VOUT. It is essential to arrange the output load and the supply resistor, RS, so that the net current through the AD586 is between 2.5 mA and 10.0 mA. The temperature characteristics and long-term stability of the device will be essentially the same as that of a unit used in the standard +5 V output configuration. AD586GND+6V→+30V2.5mA <–IL< 10mA10VRS–5VRSVOUTVINIL–15V24600529-018
Figure 19. AD586 as a Negative 5 V Reference
USING THE AD586 WITH CONVERTERS
The AD586 is an ideal reference for a wide variety of 8-, 12-, 14-, and 16-bit ADCs and DACs. Several representative examples are explained in the following sections.
AD586
Rev. G | Page 11 of 16
5 V REFERENCE WITH MULTIPLYING CMOS DACs OR ADCs
The AD586 is ideal for applications with 10- and 12-bit multiplying CMOS DACs. In the standard hookup, as shown in Figure 20, the AD586 is paired with the AD7545 12-bit multiplying DAC and the AD711 high speed BiFET op amp. The amplifier DAC configuration produces a unipolar 0 V to −5 V output range. Bipolar output applications and other operating details can be found in the individual product data sheets. AD586GNDVOUTVINAD711K0.1μF0.1μF–15V0VTO–5V+15VOUT 1AGNDDGNDDB11TODB0C133pFR268ΩRFB+15VVDDAD7545KVREF10kΩVOUTTRIM+15V20181965423127463200529-019
Figure 20. Low Power 12-Bit CMOS DAC Application
The AD586 can also be used as a precision reference for multi-ple DACs. Figure 21 shows the AD586, the AD7628 dual DAC, and the AD712 dual op amp hooked up for single-supply opera-tion to produce 0 V to −5 V outputs. Because both DACs are on the same die and share a common reference and output op amps, the DAC outputs will exhibit similar gain TCs. AD586GNDAD712OUT ADGNDAGNDDACADB0DB7DATAINPUTSOUT BDACBRFB BRFB AVREFAVREFBAD7628VINVOUTA=0TO–5VVOUTB=0TO–5VVOUT+15V+15V64471425317119202400529-020
Figure 21. AD586 as a 5 V Reference for a CMOS
STACKED PRECISION REFERENCES FOR MULTIPLE VOLTAGES
Often, a design requires several reference voltages. Three AD586s can be stacked, as shown in Figure 22, to produce 5.000 V, 10.000 V, and 15.000 V outputs. This scheme can be extended to any number of AD586s, provided the maximum load current is not exceeded. This design provides the addi-tional advantage of improved line regulation on the 5.0 V output. Changes in VIN of 18 V to 50 V produce output changes that are below the noise level of the references. 22V TO 46VAD586GNDVOUTVINTRIM10kΩAD586GNDVOUTVINTRIMAD586GNDVOUTVINTRIM10kΩ10kΩ15V10V5V24562456245600529-021
Figure 22. Multiple AD586s Stacked for Precision 5 V, 10 V, and 15 V Outputs
PRECISION CURRENT SOURCE
The design of the AD586 allows it to be easily configured as a current source. By choosing the control resistor RC in Figure 23, the user can vary the load current from the quiescent current (typically, 2 mA) to approximately 10 mA. The compliance volt-age of this circuit varies from about 5 V to 21 V, depending on the value of VIN. AD586GNDVOUTVIN5VRCIL = + IBIAS+VINRC(500Ω MIN)24600529-022
Figure 23. Precision Current Source
PRECISION HIGH CURRENT SUPPLY
For higher currents, the AD586 can easily be connected to a power PNP or power Darlington PNP device. The circuit in Figure 24 and Figure 25 can deliver up to 4 amps to the load. The 0.1 μF capacitor is required only if the load has a significant capacitive component. If the load is purely resistive, improved high frequency supply rejection results can be obtained by removing the capacitor.
AD586
Rev. G | Page 12 of 16
AD586GNDVOUTVIN5VRCIL = + IBIASRC0.1μF15V220Ω2N628526400529-023
Figure 24. Precision High Current Current Source
VOUT5V @ 4 AMPSAD586GNDVOUTVIN0.1μF15V220Ω2N628526400529-024
Figure 25. Precision High Current Voltage Source
AD586
Rev. G | Page 13 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-001-BA0.022 (0.56)0.018 (0.46)0.014 (0.36)SEATINGPLANE0.015(0.38)MIN0.210(5.33)MAXPIN 10.150 (3.81)0.130 (3.30)0.115 (2.92)0.070 (1.78)0.060 (1.52)0.045 (1.14)81450.280 (7.11)0.250 (6.35)0.240 (6.10)0.100 (2.54)BSC0.400 (10.16)0.365 (9.27)0.355 (9.02)0.060 (1.52)MAX0.430 (10.92)MAX0.014 (0.36)0.010 (0.25)0.008 (0.20)0.325 (8.26)0.310 (7.87)0.300 (7.62)0.195 (4.95)0.130 (3.30)0.115 (2.92)0.015 (0.38)GAUGEPLANE0.005 (0.13)MINCONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 26. 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.14580.310 (7.87)0.220 (5.59)0.005 (0.13)MIN0.055 (1.40)MAX0.100 (2.54) BSC15° 0°0.320 (8.13)0.290 (7.37)0.015 (0.38)0.008 (0.20)SEATINGPLANE0.200 (5.08)MAX0.405 (10.29) MAX0.150 (3.81)MIN0.200 (5.08)0.125 (3.18)0.023 (0.58)0.014 (0.36)0.070 (1.78)0.030 (0.76)0.060 (1.52)0.015 (0.38)PIN 1
Figure 27. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) 0.25 (0.0098)0.17 (0.0067)1.27 (0.0500)0.40 (0.0157)0.50 (0.0196)0.25 (0.0099)× 45°8°0°1.75 (0.0688)1.35 (0.0532)SEATINGPLANE0.25 (0.0098)0.10 (0.0040)41855.00 (0.1968)4.80 (0.1890)4.00 (0.1574)3.80 (0.1497)1.27 (0.0500)BSC6.20 (0.2440)5.80 (0.2284)0.51 (0.0201)0.31 (0.0122)COPLANARITY0.10CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGNCOMPLIANT TO JEDEC STANDARDS MS-012AA
Figure 28. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
AD586
Rev. G | Page 14 of 16
ORDERING GUIDE
Model
Initial Error
Temperature Coefficient
Temperature Range
Package Description
Package Option
Quantity Per Reel
AD586JN
20 mV
25 ppm/°C
0°C to 70°C
PDIP
N-8
AD586JNZ1
20 mV
25 ppm/°C
0°C to 70°C
PDIP
N-8
AD586JQ
20 mV
25 ppm/°C
0°C to 70°C
CERDIP
Q-8
AD586JR
20 mV
25 ppm/°C
0°C to 70°C
SOIC
R-8
AD586JR-REEL7
20 mV
25 ppm/°C
0°C to 70°C
SOIC
R-8
1,000
AD586JRZ1
20 mV
25 ppm/°C
0°C to 70°C
SOIC
R-8
AD586JRZ-REEL71
20 mV
25 ppm/°C
0°C to 70°C
SOIC
R-8
1,000
AD586KN
5 mV
15 ppm/°C
0°C to 70°C
PDIP
N-8
AD586KNZ1
5 mV
15 ppm/°C
0°C to 70°C
PDIP
N-8
AD586KQ
5 mV
15 ppm/°C
0°C to 70°C
CERDIP
Q-8
AD586KR
5 mV
15 ppm/°C
0°C to 70°C
SOIC
R-8
AD586KR-REEL
5 mV
15 ppm/°C
0°C to 70°C
SOIC
R-8
2,500
AD586KR-REEL7
5 mV
15 ppm/°C
0°C to 70°C
SOIC
R-8
1,000
AD586KRZ1
5 mV
15 ppm/°C
0°C to 70°C
SOIC
R-8
AD586KRZ-REEL1
5 mV
15 ppm/°C
0°C to 70°C
SOIC
R-8
2,500
AD586KRZ-REEL71
5 mV
15 ppm/°C
0°C to 70°C
SOIC
R-8
1,000
AD586LN
2.5 mV
5 ppm/°C
0°C to 70°C
PDIP
N-8
AD586LNZ1
2.5 mV
5 ppm/°C
0°C to 70°C
PDIP
N-8
AD586LR
2.5 mV
5 ppm/°C
0°C to 70°C
SOIC
R-8
AD586LR-REEL
2.5 mV
5 ppm/°C
0°C to 70°C
SOIC
R-8
2,500
AD586LR-REEL7
2.5 mV
5 ppm/°C
0°C to 70°C
SOIC
R-8
1,000
AD586LRZ1
2.5 mV
5 ppm/°C
0°C to 70°C
SOIC
R-8
AD586LRZ-REEL1
2.5 mV
5 ppm/°C
0°C to 70°C
SOIC
R-8
2,500
AD586LRZ-REEL71
2.5 mV
5 ppm/°C
0°C to 70°C
SOIC
R-8
1,000
AD586MN
2 mV
2 ppm/°C
0°C to 70°C
PDIP
N-8
AD586MNZ1
2 mV
2 ppm/°C
0°C to 70°C
PDIP
N-8
AD586AR
5 mV
15 ppm/°C
−40°C to +85°C
SOIC
R-8
AD586AR-REEL
5 mV
15 ppm/°C
−40°C to +85°C
SOIC
R-8
2,500
AD586ARZ1
5 mV
15 ppm/°C
−40°C to +85°C
SOIC
R-8
AD586ARZ-REEL1
5 mV
15 ppm/°C
−40°C to +85°C
SOIC
R-8
2,500
AD586ARZ-REEL71
5 mV
15 ppm/°C
−40°C to +85°C
SOIC
R-8
1,000
AD586BR
2.5 mV
5 ppm/°C
−40°C to +85°C
SOIC
R-8
AD586BR-REEL7
2.5 mV
5 ppm/°C
−40°C to +85°C
SOIC
R-8
1,000
AD586BRZ1
2.5 mV
5 ppm/°C
−40°C to +85°C
SOIC
R-8
AD586BRZ-REEL1
2.5 mV
5 ppm/°C
−40°C to +85°C
SOIC
R-8
2,500
AD586BRZ-REEL71
2.5 mV
5 ppm/°C
−40°C to +85°C
SOIC
R-8
1,000
AD586LQ
2.5 mV
5 ppm/°C
0°C to 70°C
CERDIP
Q-8
AD586SQ
10 mV
20 ppm/°C
−55°C to +125°C
CERDIP
Q-8
AD586TQ
2.5 mV
10 ppm/°C
−55°C to +125°C
CERDIP
Q-8
AD586TQ/883B2
2.5 mV
10 ppm/°C
−55°C to +125°C
CERDIP
Q-8
1 Z = Pb-free part.
2 For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or the current AD586/883B data sheet.
AD586
Rev. G | Page 15 of 16
NOTES
AD586
Rev. G | Page 16 of 16
NOTES
February 2004 Digital Audio Products
Data Manual
SLWS106H
iii
Contents
Section Title Page
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4
1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5
1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5
2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature
Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
2.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
2.3 Electrical Characteristics Over Recommended Operating
Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
2.3.1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
2.3.2 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3
2.3.3 Analog Line Input to Line Output (Bypass) . . . . . . . . . . . . . 2−3
2.3.4 Stereo Headphone Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4
2.3.5 Analog Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4
2.3.6 Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4
2.3.7 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4
2.4 Digital-Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5
2.4.1 Audio Interface (Master Mode) . . . . . . . . . . . . . . . . . . . . . . . 2−5
2.4.2 Audio Interface (Slave-Mode) . . . . . . . . . . . . . . . . . . . . . . . . 2−6
2.4.3 Three-Wire Control Interface (SDIN) . . . . . . . . . . . . . . . . . . 2−7
2.4.4 Two-Wire Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−7
3 How to Use the TLV320AIC23B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.1 Control Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.1.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.1.2 2-Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.1.3 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
3.2 Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
3.2.1 Line Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
3.2.2 Microphone Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
3.2.3 Line Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
3.2.4 Headphone Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
3.2.5 Analog Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3.2.6 Sidetone Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3.3 Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3.3.1 Digital Audio-Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . 3−7
iv
3.3.2 Audio Sampling Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
3.3.3 Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11
A Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A−1
v
List of Illustrations
Figure Title Page
2−1 System-Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5
2−2 Master-Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5
2−3 Slave-Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−6
2−4 Three-Wire Control Interface Timing Requirements . . . . . . . . . . . . . . . . . . 2−7
2−5 Two-Wire Control Interface Timing Requirements . . . . . . . . . . . . . . . . . . . 2−7
3−1 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3−2 2-Wire Compatible Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
3−3 Analog Line Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
3−4 Microphone Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
3−5 Right-Justified Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3−6 Left-Justified Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3−7 I2S Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3−8 DSP Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3−9 Digital De-Emphasis Filter Response − 44.1 kHz Sampling . . . . . . . . . . . 3−12
3−10 Digital De-Emphasis Filter Response − 48 kHz Sampling . . . . . . . . . . . . 3−12
3−11 ADC Digital Filter Response 0: USB Mode
(Group Delay = 12 Output Samples) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−13
3−12 ADC Digital Filter Ripple 0: USB
(Group Delay = 20 Output Samples) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−13
3−13 ADC Digital Filter Response 1: USB Mode Only . . . . . . . . . . . . . . . . . . . . 3−14
3−14 ADC Digital Filter Ripple 1: USB Mode Only . . . . . . . . . . . . . . . . . . . . . . . . 3−14
3−15 ADC Digital Filter Response 2: USB mode and Normal Modes
(Group Delay = 3 Output Samples) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−15
3−16 ADC Digital Filter Ripple 2: USB Mode and Normal Modes . . . . . . . . . . . 3−15
3−17 ADC Digital Filter Response 3: USB Mode Only . . . . . . . . . . . . . . . . . . . . 3−16
3−18 ADC Digital Filter Ripple 3: USB Mode Only . . . . . . . . . . . . . . . . . . . . . . . . 3−16
3−19 DAC Digital Filter Response 0: USB Mode . . . . . . . . . . . . . . . . . . . . . . . . . 3−17
3−20 DAC Digital Filter Ripple 0: USB Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−17
3−21 DAC Digital Filter Response 1: USB Mode Only . . . . . . . . . . . . . . . . . . . . 3−18
3−22 DAC Digital Filter Ripple 1: USB Mode Only . . . . . . . . . . . . . . . . . . . . . . . . 3−18
3−23 DAC Digital Filter Response 2: USB Mode and Normal Modes . . . . . . . . 3−19
3−24 DAC Digital Filter Ripple 2: USB Mode and Normal Modes . . . . . . . . . . . 3−19
3−25 DAC Digital Filter Response 3: USB Mode Only . . . . . . . . . . . . . . . . . . . . 3−20
3−26 DAC Digital Filter Ripple 3: USB Mode Only . . . . . . . . . . . . . . . . . . . . . . . . 3−20
vi
1−1
1 Introduction
The TLV320AIC23B is a high-performance stereo audio codec with highly integrated analog functionality. The
analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) within the TLV320AIC23B use multibit
sigma-delta technology with integrated oversampling digital interpolation filters. Data-transfer word lengths of 16, 20,
24, and 32 bits, with sample rates from 8 kHz to 96 kHz, are supported. The ADC sigma-delta modulator features
third-order multibit architecture with up to 90-dBA signal-to-noise ratio (SNR) at audio sampling rates up to 96 kHz,
enabling high-fidelity audio recording in a compact, power-saving design. The DAC sigma-delta modulator features
a second-order multibit architecture with up to 100-dBA SNR at audio sampling rates up to 96 kHz, enabling
high-quality digital audio-playback capability, while consuming less than 23 mW during playback only. The
TLV320AIC23B is the ideal analog input/output (I/O) choice for portable digital audio-player and recorder
applications, such as MP3 digital audio players.
Integrated analog features consist of stereo-line inputs with an analog bypass path, a stereo headphone amplifier,
with analog volume control and mute, and a complete electret-microphone-capsule biasing and buffering solution.
The headphone amplifier is capable of delivering 30 mW per channel into 32 Ω. The analog bypass path allows use
of the stereo-line inputs and the headphone amplifier with analog volume control, while completely bypassing the
codec, thus enabling further design flexibility, such as integrated FM tuners. A microphone bias-voltage output
provides a low-noise current source for electret-capsule biasing. The AIC23B has an integrated adjustable
microphone amplifier (gain adjustable from 1 to 5) and a programmable gain microphone amplifier (0 dB or 20 dB).
The microphone signal can be mixed with the output signals if a sidetone is required.
While the TLV320AIC23B supports the industry-standard oversampling rates of 256 fs and 384 fs, unique
oversampling rates of 250 fs and 272 fs are provided, which optimize interface considerations in designs using TI C54x
digital signal processors (DSPs) and universal serial bus (USB) data interfaces. A single 12-MHz crystal can supply
clocking to the DSP, USB, and codec. The TLV320AIC23B features an internal oscillator that, when connected to a
12-MHz external crystal, provides a system clock to the DSP and other peripherals at either 12 MHz or 6 MHz, using
an internal clock buffer and selectable divider. Audio sample rates of 48 kHz and compact-disc (CD) standard 44.1
kHz are supported directly from a 12-MHz master clock with 250 fs and 272 fs oversampling rates.
Low power consumption and flexible power management allow selective shutdown of codec functions, thus
extending battery life in portable applications. This design solution, coupled with the industry’s smallest package, the
TI proprietary MicroStar Junior using only 25 mm2 of board area, makes powerful portable stereo audio designs
easily realizable in a cost-effective, space-saving total analog I/O solution: the TLV320AIC23B.
1.1 Features
• High-Performance Stereo Codec
− 90-dB SNR Multibit Sigma-Delta ADC (A-weighted at 48 kHz)
− 100-dB SNR Multibit Sigma-Delta DAC (A-weighted at 48 kHz)
− 1.42 V – 3.6 V Core Digital Supply: Compatible With TI C54x DSP Core Voltages
− 2.7 V – 3.6 V Buffer and Analog Supply: Compatible Both TI C54x DSP Buffer Voltages
− 8-kHz – 96-kHz Sampling-Frequency Support
• Software Control Via TI McBSP-Compatible Multiprotocol Serial Port
− 2-wire-Compatible and SPI-Compatible Serial-Port Protocols
− Glueless Interface to TI McBSPs
• Audio-Data Input/Output Via TI McBSP-Compatible Programmable Audio Interface
− I2S-Compatible Interface Requiring Only One McBSP for both ADC and DAC
− Standard I2S, MSB, or LSB Justified-Data Transfers
− 16/20/24/32-Bit Word Lengths
MicroStar Junior is a trademark of Texas Instruments.
1−2
− Audio Master/Slave Timing Capability Optimized for TI DSPs (250/272 fs), USB mode
− Industry-Standard Master/Slave Support Provided Also (256/384 fs), Normal mode
− Glueless Interface to TI McBSPs
• Integrated Total Electret-Microphone Biasing and Buffering Solution
− Low-Noise MICBIAS pin at 3/4 AVDD for Biasing of Electret Capsules
− Integrated Buffer Amplifier With Tunable Fixed Gain of 1 to 5
− Additional Control-Register Selectable Buffer Gain of 0 dB or 20 dB
• Stereo-Line Inputs
− Integrated Programmable Gain Amplifier
− Analog Bypass Path of Codec
• ADC Multiplexed Input for Stereo-Line Inputs and Microphone
• Stereo-Line Outputs
− Analog Stereo Mixer for DAC and Analog Bypass Path
• Volume Control With Mute on Input and Output
• Highly Efficient Linear Headphone Amplifier
− 30 mW into 32 Ω From a 3.3-V Analog Supply Voltage
• Flexible Power Management Under Total Software Control
− 23-mW Power Consumption During Playback Mode
− Standby Power Consumption <150 μW
− Power-Down Power Consumption <15 μW
• Industry’s Smallest Package: 32-Pin TI Proprietary MicroStar Junior
− 25 mm2
Total Board Area
− 28-Pin TSSOP Also Is Available (62 mm2 Total Board Area)
• Ideally Suitable for Portable Solid-State Audio Players and Recorders
1−3
1.2 Functional Block Diagram
Control
Interface
Digital
Filters
Digital
Audio
Interface
Σ−Δ
DAC Σ
6 to −73 dB,
1 dB Steps
Headphone
Driver
Σ−Δ
DAC Σ
6 to −73 dB,
1 dB Steps
Headphone
Driver
CLKOUT
Divider
(1x, 1/2x)
OSC
CS
SDIN
SCLK
MODE
DVDD
BVDD
DGND
LRCIN
DIN
LRCOUT
DOUT
BCLK
AVDD
VMID
AGND
RLINEIN
LLINEIN
HPVDD
HPGND
RHPOUT
ROUT
LOUT
LHPOUT
XTI/MCLK
XTO
CLKOUT
DSPcodec
TLV320AIC23B
1.0X
1.0X
VMID
VADC
50 kΩ
50 kΩ
Σ−Δ
ADC
2:1
MUX
VDAC
Σ−Δ
ADC
2:1
MUX
Mute,
0 dB, 20 dB
VMID
50 kΩ
10 kΩ
VADC
12 to −34.5 dB,
1.5 dB Steps
1.0X
1.5X
VDAC
12 to −34 dB,
1.5 dB Steps
MICBIAS
MICIN
CLKIN
Divider
(1x, 1/2x)
Line
Mute
Line
Mute
Side Tone
Mute
Bypass
Mute
Bypass
Mute
NOTE: MCLK, BCLK, and SCLK are all asynchronous to each other.
1−4
1.3 Terminal Assignments
LRCIN
NC
1 2 3 4 5 6 7 8 9
25 24 23 22 21 20 19 18 17
10
11
12
13
14
15
16
32
31
30
29
28
27
26
DOUT
LRCOUT
HPVDD
LHPOUT
RHPOUT
HPGND
XTI/MCLK
SCLK
SDIN
MODE
CS
LLINEIN
RLINEIN
LOUT
ROUT
AVDD
AGND
VMID
MICBIAS
MICIN
NC
NC
DIN
BCLK
CLKOUT
BVDD
DGND
DVDD
XTO
NC
GQE/ZQE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
BVDD
CLKOUT
BCLK
DIN
LRCIN
DOUT
LRCOUT
HPVDD
LHPOUT
RHPOUT
HPGND
LOUT
ROUT
AVDD
DGND
DVDD
XTO
XTI/MCLK
SCLK
SDIN
MODE
CS
LLINEIN
RLINEIN
MICIN
MICBIAS
VMID
AGND
PW PACKAGE
(TOP VIEW)
NC − No internal connection
21
20
19
18
17
16
15
DIN
LRCIN
DOUT
LROUT
HPVDD
LHPOUT
RHPOUT
SCLK
SDIN
MODE
CS
LLNEIN
RUNEIN
MICIN
1
2
3
4
5
6
7
28
27
26
25
24
23
22
BCLK
CLKOUT
BVDD
DGND
DVDD
XTO
XTI/MCLK
HPGND
LOUT
ROUT
AVDD
AGND
VMID
MICBIAS
8
9
10
11
12
13
14
RHD PACKAGE
(TOP VIEW)
1−5
1.4 Ordering Information
PACKAGE
TA 32-Pin
MicroStar Junior GQE/ZQE
28-Pin
TSSOP PW
28-Pin
PQFP RHD
−10°C to 70°C TLV320AIC23BGQE/ZQE TLV320AIC23BPW TLV320AIC23BRHD
−40°C to 85°C TLV320AIC23BIGQE/ZQE TLV320AIC23BIPW TLV320AIC23BIRHD
1.5 Terminal Functions
TERMINAL
NO.
I/O DESCRIPTION
NAME GQE/
ZQE
PW RHD
AGND 5 15 12 Analog supply return
AVDD 4 14 11 Analog supply input. Voltage level is 3.3 V nominal.
BCLK 23 3 28 I/O I2S serial-bit clock. In audio master mode, the AIC23B generates this signal and sends it to the
DSP. In audio slave mode, the signal is generated by the DSP.
BVDD 21 1 26 Buffer supply input. Voltage range is from 2.7 V to 3.6 V.
CLKOUT 22 2 27 O Clock output. This is a buffered version of the XTI input and is available in 1X or 1/2X frequencies
of XTI. Bit 07 in the sample rate control register controls frequency selection.
CS 12 21 18 I Control port input latch/address select. For SPI control mode this input acts as the data latch
control. For 2-wire control mode this input defines the seventh bit in the device address field.
See Section 3.1 for details.
DIN 24 4 1 I I2S format serial data input to the sigma-delta stereo DAC
DGND 20 28 25 Digital supply return
DOUT 27 6 3 O I2S format serial data output from the sigma-delta stereo ADC
DVDD 19 27 24 Digital supply input. Voltage range is 1.4 V to 3.6 V.
HPGND 32 11 8 Analog headphone amplifier supply return
HPVDD 29 8 5 Analog headphone amplifier supply input. Voltage level is 3.3 V nominal.
LHPOUT 30 9 6 O Left stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS.
Gain of –73 dB to 6 dB is provided in 1-dB steps.
LLINEIN 11 20 17 I Left stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is
provided in 1.5-dB steps.
LOUT 2 12 9 O Left stereo mixer-channel line output. Nominal output level is 1.0 VRMS.
LRCIN 26 5 2 I/O I2S DAC-word clock signal. In audio master mode, the AIC23B generates this framing signal
and sends it to the DSP. In audio slave mode, the signal is generated by the DSP.
LRCOUT 28 7 4 I/O I2S ADC-word clock signal. In audio master mode, the AIC23B generates this framing signal
and sends it to the DSP. In audio slave mode, the signal is generated by the DSP.
MICBIAS 7 17 14 O Buffered low-noise-voltage output suitable for electret-microphone-capsule biasing. Voltage
level is 3/4 AVDD nominal.
MICIN 8 18 15 I Buffered amplifier input suitable for use with electret-microphone capsules. Without external
resistors a default gain of 5 is provided. See Section 2.3.1.2 for details.
MODE 13 22 19 I Serial-interface-mode input. See Section 3.1 for details.
NC 1, 9
17, 25
Not Used—No internal connection
RHPOUT 31 10 7 O Right stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS.
Gain of −73 dB to 6 dB is provided in 1-dB steps.
RLINEIN 10 19 16 I Right stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is
provided in 1.5-dB steps.
ROUT 3 13 10 O Right stereo mixer-channel line output. Nominal output level is 1.0 VRMS.
1−6
1.5 Terminal Functions (continued)
TERMINAL
NO.
I/O DESCRIPTION
NAME GQE/
ZQE
PW RHD
SCLK 15 24 21 I Control-port serial-data clock. For SPI and 2-wire control modes this is the serial-clock input.
See Section 3.1 for details.
SDIN 14 23 20 I Control-port serial-data input. For SPI and 2-wire control modes this is the serial-data input and
also is used to select the control protocol after reset. See Section 3.1 for details.
VMID 6 16 13 I Midrail voltage decoupling input. 10-μF and 0.1-μF capacitors should be connected in parallel to
this terminal for noise filtering. Voltage level is 1/2 AVDD nominal.
XTI/MCLK 16 25 22 I Crystal or external-clock input. Used for derivation of all internal clocks on the AIC23B.
XTO 18 26 23 O Crystal output. Connect to external crystal for applications where the AIC23B is the audio timing
master. Not used in applications where external clock source is used.
2−1
2 Specifications
2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless
otherwise noted)†
Supply voltage range, AVDD to AGND, DVDD to DGND, BVDD to DGND, HPVDD to HPGND
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 3.63 V
Analog supply return to digital supply return, AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 3 .63 V
Input voltage range, all input signals: Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DVDD + 0.3 V
Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V
Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Operating free-air temperature range, TA: Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10°C to 70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: DVDD may not exceed BVDD + 0.3V; BVDD may not exceed AVDD + 0.3V or HPVDD + 0.3.
2.2 Recommended Operating Conditions
MIN NOM MAX UNIT
Analog supply voltage, AVDD, HPVDD (see Note 2) 2.7 3.3 3.6 V
Digital buffer supply voltage, BVDD (see Note 2) 2.7 3.3 3.6 V
Digital core supply voltage, DVDD (see Note 2) 1.42 1.5 3.6 V
Analog input voltage, full scale − 0dB (AVDD = 3.3 V) 1 VRMS
Stereo-line output load resistance 10 kΩ
Headphone-amplifier output load resistance 0 Ω
CLKOUT digital output load capacitance 20 pF
All other digital output load capacitance 10 pF
Stereo-line output load capacitance 50 pF
XTI master clock Input 18.43 MHz
ADC or DAC conversion rate 96 kHz
Operating free-air temperature, TA
Commercial −10 70
°C
Industrial −40 85
NOTE 2: Digital voltage values are with respect to DGND; analog voltage values are with respect to AGND.
2−2
2.3 Electrical Characteristics Over Recommended Operating Conditions, AVDD,
HPVDD, BVDD = 3.3 V, DVDD = 1.5 V, Slave Mode, XTI/MCLK = 256fs, fs = 48 kHz
(unless otherwise stated)
2.3.1 ADC
2.3.1.1 Line Input to ADC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input signal level (0 dB) 1 VRMS
Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3
fs = 48 kHz (3.3 V) 85 90
dB
and 4) fs = 48 kHz (2.7 V) 90
Dynamic range, A-weighted, −60-dB full-scale input (see
AVDD = 3.3 V 85 90
dB
Note 4) AVDD = 2.7 V 90
Total harmonic distortion, −1-dB input, 0-dB gain
AVDD = 3.3 V –80
dB
AVDD = 2.7 V 80
Power supply rejection ratio 1 kHz, 100 mVpp 50 dB
ADC channel separation 1 kHz input tone 90 dB
Programmable gain 1 kHz input tone, RSOURCE < 50 Ω –34.5 12 dB
Programmable gain step size Monotonic 1.5 dB
Mute attenuation 0 dB, 1 kHz input tone 80 dB
Input resistance
12 dB Input gain 10 20
kΩ
0 dB input gain 30 35
Input capacitance 10 pF
NOTES: 3. Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz
to 20-kHz bandwidth using an audio analyzer.
4. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter
results in higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
2.3.1.2 Microphone Input to ADC, 0-dB Gain, fs = 8 kHz (40-KΩ Source Impedance, see Section 1.2,
Functional Block Diagram)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input signal level (0 dB) 1.0 VRMS
Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3 and 4)
AVDD = 3.3 V 80 85
dB
AVDD = 2.7 V 84
Dynamic range, A-weighted, −60-dB full-scale input (see Note 4)
AVDD = 3.3 V 80 85
dB
AVDD = 2.7 V 84
Total harmonic distortion, −1-dB input, 0-dB gain
AVDD = 3.3 V –60
dB
AVDD = 2.7 V −60
Power supply rejection ratio 1 kHz, 100 mVpp 50 dB
Programmable gain boost 1 kHz input tone, RSOURCE < 50 Ω 20 dB
Microphone-path gain MICBOOST = 0, RSOURCE < 50 Ω 14 dB
Mute attenuation 0 dB, 1 kHz input tone 60 80 dB
Input resistance 8 14 kΩ
Input capacitance 10 pF
NOTES: 3. Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz
to 20-kHz bandwidth using an audio analyzer.
4. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter
results in higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
2−3
2.3.1.3 Microphone Bias
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Bias voltage 3/4 AVDD − 100 m 3/4 AVDD 3/4 AVDD + 100 m V
Bias-current source 3 mA
Output noise voltage 1 kHz to 20 kHz 25 nV/√Hz
2.3.2 DAC
2.3.2.1 Line Output, Load = 10 kΩ, 50 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0-dB full-scale output voltage (FFFFFF) 1.0 VRMS
Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3, 4, and 5)
AVDD = 3.3 V fs = 48kHz 90 100
dB
AVDD = 2.7 V fs = 48 kHz 100
Dynamic range, A-weighted (see Note 4)
AVDD = 3.3 V 85 90
dB
AVDD = 2.7 V TBD
AVDD = 3.3 V
1 kHz, 0 dB –88 –80
dB
Total harmonic distortion
1 kHz, −3 dB −92 −86
AVDD = 2.7 V
1 kHz, 0 dB −85
dB
1 kHz, −3 dB −88
Power supply rejection ratio 1 kHz, 100 mVpp 50 dB
DAC channel separation 100 dB
NOTES: 3. Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz
to 20-kHz bandwidth using an audio analyzer.
4. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter
results in higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
5. Ratio of output level with 1-kHz full-scale input, to the output level with all zeros into the digital input, measured A-weighted over
a 20-Hz to 20-kHz bandwidth.
2.3.3 Analog Line Input to Line Output (Bypass)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0-dB full-scale output voltage 1.0 VRMS
Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3 and 4)
AVDD = 3.3 V 90 95
dB
AVDD = 2.7 V 95
AVDD = 3.3 V
1 kHz, 0 dB –86 –80
dB
Total harmonic distortion
1 kHz, −3 dB −92 −86
AVDD = 2.7 V
1 kHz, 0 dB −86
dB
1 kHz, −3 dB −92
Power supply rejection ratio 1 kHz, 100 mVpp 50 dB
DAC channel separation (left to right) 1 kHz, 0 dB 80 dB
NOTES: 3. Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz
to 20-kHz bandwidth using an audio analyzer.
4. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter
results in higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
2−4
2.3.4 Stereo Headphone Output
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0-dB full-scale output voltage 1.0 VRMS
Maximum output power, PO RL = 32 Ω 30
mW
RL = 16 Ω 40
Signal-to-noise ratio, A-weighted (see Note 4) AVDD = 3.3 V 90 97 dB
Total harmonic distortion
AVDD = 3.3 V,
PO = 10 mW 0.1
%
1 kHz output PO = 20 mW 1.0
Power supply rejection ratio 1 kHz, 100 mVpp 50 dB
Programmable gain 1 kHz output −73 6 dB
Programmable-gain step size 1 dB
Mute attenuation 1 kHz output 80 dB
NOTE 4: All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results
in higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values.
2.3.5 Analog Reference Levels
PARAMETER MIN TYP MAX UNIT
Reference voltage AVDD/2 − 50 mV AVDD/2 + 50 mV V
Divider resistance 40 50 60 kΩ
2.3.6 Digital I/O
PARAMETER MIN TYP MAX UNIT
VIL Input low level 0.3 × BVDD V
VIH Input high level 0.7 × BVDD V
VOL Output low level 0.1 × BVDD V
VOH Output high level 0.9 × BVDD V
2.3.7 Supply Current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Record and playback (all active) 20 24 26
Record and playback (osc, clk, and MIC output powered down) 16 18 20
Total supply current,
Line playback only 6 7.5 9
ITOT
Record only 11 13.5 15 mA
No input signal
Analog bypass (line in to line out) 4 4.5 6
Power down, DVDD = 1.5 V, Oscillator enabled 0.8 1.5 3
AVDD = BVDD = HPVDD = 3.3 V Oscillator disabled 0.01
2−5
2.4 Digital-Interface Timing
PARAMETER MIN TYP MAX UNIT
tw(1)
System-clock pulse duration, MCLK/XTI
High 18
ns
tw(2)
Low 18
tc(1) System-clock period, MCLK/XTI 54 ns
Duty cycle, MCLK/XTI 40/60% 60/40%
tpd(1) Propagation delay, CLKOUT 0 10 ns
tc(1)
tw(1) tw(2)
tpd(1)
MCLK/XTI
CLKOUT
CLKOUT
(Div 2)
Figure 2−1. System-Clock Timing Requirements
2.4.1 Audio Interface (Master Mode)
PARAMETER MIN TYP MAX UNIT
tpd(2) Propagation delay, LRCIN/LRCOUT 0 10 ns
tpd(3) Propagation delay, DOUT 0 10 ns
tsu(1) Setup time, DIN 10 ns
th(1) Hold time, DIN 10 ns
BCLK
LRCIN
DIN
tpd(2)
tsu(1) th(1)
tpd(3)
DOUT
LRCOUT
Figure 2−2. Master-Mode Timing Requirements
2−6
2.4.2 Audio Interface (Slave-Mode)
PARAMETER MIN TYP MAX UNIT
tw(3)
Pulse duration, BCLK
High 20
ns
tw(4)
Low 20
tc(2) Clock period, BCLK 50 ns
tpd(4) Propagation delay, DOUT 0 10 ns
tsu(2) Setup time, DIN 10 ns
th(2) Hold time, DIN 10 ns
tsu(3) Setup time, LRCIN 10 ns
th(3) Hold time, LRCIN 10 ns
BCLK
LRCIN
DIN
tc(2)
tw(4) tw(3)
tsu(3)
tsu(2) th(3)
th(2)
DOUT
tpd(2)
LRCOUT
Figure 2−3. Slave-Mode Timing Requirements
2−7
2.4.3 Three-Wire Control Interface (SDIN)
PARAMETER MIN TYP MAX UNIT
tw(5)
Clock pulse duration, SCLK
High 20
ns
tw(6)
Low 20
tc(3) Clock period, SCLK 80 ns
tsu(4) Clock rising edge to CS rising edge, SCLK 60 ns
tsu(5) Setup time, SDIN to SCLK 20 ns
th(4) Hold time, SCLK to SDIN 20 ns
tw(7)
Pulse duration, CS
High 20
ns
tw(8)
Low 20
LSB
tw(8)
tc(3)
tw(5) tw(6) tsu(4)
tsu(5) th(4)
CS
SCLK
DIN
Figure 2−4. Three-Wire Control Interface Timing Requirements
2.4.4 Two-Wire Control Interface
PARAMETER MIN TYP MAX UNIT
tw(9)
Clock pulse duration, SCLK
High 1.3 μs
tw(10)
Low 600 ns
f(sf) Clock frequency, SCLK 0 400 kHz
th(5) Hold time (start condition) 600 ns
tsu(6) Setup time (start condition) 600 ns
th(6) Data hold time 900 ns
tsu(7) Data setup time 100 ns
tr Rise time, SDIN, SCLK 300 ns
tf Fall time, SDIN, SCLK 300 ns
tsu(8) Setup time (stop condition) 600 ns
tsp Pulse width of spikes suppressed by input filter 0 50 ns
SCLK
DIN
tw(9) tw(10)
th(5) th(6) tsu(7) tsu(8)
tsp
Figure 2−5. Two-Wire Control Interface Timing Requirements
2−8
3−1
3 How to Use the TLV320AIC23B
3.1 Control Interfaces
The TLV320AIC23B has many programmable features. The control interface is used to program the registers of the
device. The control interface complies with SPI (three-wire operation) and two-wire operation specifications. The
state of the MODE terminal selects the control interface type. The MODE pin must be hardwired to the required level.
MODE INTERFACE
0 2-wire
1 SPI
3.1.1 SPI
In SPI mode, SDIN carries the serial data, SCLK is the serial clock and CS latches the data word into the
TLV320AIC23B. The interface is compatible with microcontrollers and DSPs with an SPI interface.
A control word consists of 16 bits, starting with the MSB. The data bits are latched on the rising edge of SCLK. A rising
edge on CS after the 16th rising clock edge latches the data word into the AIC (see Figure 3-1).
The control word is divided into two parts. The first part is the address block, the second part is the data block:
B[15:9] Control Address Bits
B[8:0] Control Data Bits
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MSB LSB
CS
SCLK
SDIN
Figure 3−1. SPI Timing
3.1.2 2-Wire
In 2-wire mode, the data transfer uses SDIN for the serial data and SCLK for the serial clock. The start condition is
a falling edge on SDIN while SCLK is high. The seven bits following the start condition determine which device on
the 2-wire bus receives the data. R/W determines the direction of the data transfer. The TLV320AIC23B is a write only
device and responds only if R/W is 0. The device operates only as a slave device whose address is selected by setting
the state of the CS pin as follows.
CS STATE
(Default = 0)
ADDRESS
0 0011010
1 0011011
3−2
The device that recognizes the address responds by pulling SDIN low during the ninth clock cycle, acknowledging
the data transfer. The control follows in the next two eight-bit blocks. The stop condition after the data transfer is a
rising edge on SDIN when SCLK is high (see Figure 3-2).
The 16-bit control word is divided into two parts. The first part is the address block, the second part is the data block:
B[15:9] Control Address Bits
B[8:0] Control Data Bits
SCLK
SDI ADDR R/W ACK B15 − B8 ACK B7 − B0 ACK
Start Stop
1 7 8 9 1 8 9 1 8 9
Figure 3−2. 2-Wire Compatible Timing
3.1.3 Register Map
The TLV320AIC23B has the following set of registers, which are used to program the modes of operation.
ADDRESS REGISTER
0000000 Left line input channel volume control
0000001 Right line input channel volume control
0000010 Left channel headphone volume control
0000011 Right channel headphone volume control
0000100 Analog audio path control
0000101 Digital audio path control
0000110 Power down control
0000111 Digital audio interface format
0001000 Sample rate control
0001001 Digital interface activation
0001111 Reset register
Left line input channel volume control (Address: 0000000)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function LRS LIM X X LIV4 LIV3 LIV2 LIV1 LIV0
Default 0 1 0 0 1 0 1 1 1
LRS Left/right line simultaneous volume/mute update
Simultaneous update 0 = Disabled 1 = Enabled
LIM Left line input mute 0 = Normal 1 = Muted
LIV[4:0] Left line input volume control (10111 = 0 dB default)
11111 = +12 dB down to 00000 = –34.5 dB in 1.5-dB steps
X Reserved
3−3
Right Line Input Channel Volume Control (Address: 0000001)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function RLS RIM X X RIV4 RIV3 RIV2 RIV1 RIV0
Default 0 1 0 0 1 0 1 1 1
RLS Right/left line simultaneous volume/mute update
Simultaneous update 0 = Disabled 1 = Enabled
RIM Right line input mute 0 = Normal 1 = Muted
RIV[4:0] Right line input volume control (10111 = 0 dB default)
11111 = +12 dB down to 00000 = –34.5 dB in 1.5-dB steps
X Reserved
Left Channel Headphone Volume Control (Address: 0000010)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function LRS LZC LHV6 LHV5 LHV4 LHV3 LHV2 LHV1 LHV0
Default 0 1 1 1 1 1 0 0 1
LRS Left/right headphone channel simultaneous volume/mute update
Simultaneous update 0 = Disabled 1 = Enabled
LZC Left-channel zero-cross detect
Zero-cross detect 0 = Off 1 = On
LHV[6:0] Left Headphone volume control (1111001 = 0 dB default)
1111111 = +6 dB, 79 steps between +6 dB and −73 dB (mute), 0110000 = −73 dB (mute),
any thing below 0110000 does nothing − you are still muted
Right Channel Headphone Volume Control (Address: 0000011)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function RLS RZC RHV6 RHV5 RHV4 RHV3 RHV2 RHV1 RHV0
Default 0 1 1 1 1 1 0 0 1
RLS Right/left headphone channel simultaneous volume/mute Update
Simultaneous update 0 = Disabled 1 = Enabled
RZC Right-channel zero-cross detect
Zero-cross detect 0 = Off 1 = On
RHV[6:0] Right headphone volume control (1111001 = 0 dB default)
1111111 = +6 dB, 79 steps between +6 dB and −73 dB (mute), 0110000 = −73 dB (mute),
any thing below 0110000 does nothing − you are still muted
Analog Audio Path Control (Address: 0000100)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function STA2 STA1 STA0 STE DAC BYP INSEL MICM MICB
Default 0 0 0 0 0 1 0 1 0
STA[2:0] and STE
STE STA2 STA1 STA0 ADDED SIDETONE
1 1 X X 0 dB
1 0 0 0 −6 dB
1 0 0 1 −9 dB
1 0 1 0 −12 dB
1 0 1 1 −18 dB
0 X X X Disabled
DAC DAC select 0 = DAC off 1 = DAC selected
BYP Bypass 0 = Disabled 1 = Enabled
3−4
INSEL Input select for ADC 0 = Line 1 = Microphone
MICM Microphone mute 0 = Normal 1 = Muted
MICB Microphone boost 0=dB 1 = 20dB
X Reserved
Digital Audio Path Control (Address: 0000101)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X X X X X DACM DEEMP1 DEEMP0 ADCHP
Default 0 0 0 0 0 1 0 0 0
DACM DAC soft mute 0 = Disabled 1 = Enabled
DEEMP[1:0] De-emphasis control 00 = Disabled 01 = 32 kHz 10 = 44.1 kHz 11 = 48 kHz
ADCHP ADC high-pass filter 1 = Disabled 0 = Enabled
X Reserved
Power Down Control (Address: 0000110)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X OFF CLK OSC OUT DAC ADC MIC LINE
Default 0 0 0 0 0 0 1 1 1
OFF Device power 0 = On 1 = Off
CLK Clock 0 = On 1 = Off
OSC Oscillator 0 = On 1 = Off
OUT Outputs 0 = On 1 = Off
DAC DAC 0 = On 1 = Off
ADC ADC 0 = On 1 = Off
MIC Microphone input 0 = On 1 = Off
LINE Line input 0 = On 1 = Off
X Reserved
Digital Audio Interface Format (Address: 0000111)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X X MS LRSWAP LRP IWL1 IWL0 FOR1 FOR0
Default 0 0 0 0 0 0 0 0 1
MS Master/slave mode 0 = Slave 1 = Master
LRSWAP DAC left/right swap 0 = Disabled 1 = Enabled
LRP DAC left/right phase 0 = Right channel on, LRCIN high
1 = Right channel on, LRCIN low
DSP mode
1 = MSB is available on 2nd BCLK rising edge after LRCIN rising edge
0 = MSB is available on 1st BCLK rising edge after LRCIN rising edge
IWL[1:0] Input bit length 00 = 16 bit 01 = 20 bit 10 = 24 bit 11 = 32 bit
FOR[1:0] Data format 11 = DSP format, frame sync followed by two data words
10 = I2S format, MSB first, left – 1 aligned
01 = MSB first, left aligned
00 = MSB first, right aligned
X Reserved
NOTES: 1. In Master mode, the TLV320AIC23B supplies the BCLK, LRCOUT, and LRCIN. In Slave mode, BCLK, LRCOUT, and LRCIN are
supplied to the TLV320AIC23B.
2. In normal mode, BCLK = MCLK/4 for all sample rates except for 88.2 kHz and 96 kHz. For 88.2 kHz and 96 kHz sample rate,
BCLK = MCLK.
3. In USB mode, bit BCLK = MCLK
3−5
Sample Rate Control (Address: 0001000)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Normal
Default 0 0 0 1 0 0 0 0 0
CLKIN Clock input divider 0 = MCLK 1 = MCLK/2
CLKOUT Clock output divider 0 = MCLK 1 = MCLK/2
SR[3:0] Sampling rate control (see Sections 3.3.2.1 AND 3.3.2.2)
BOSR Base oversampling rate
USB mode: 0 = 250 fs 1 = 272 fs
Normal mode: 0 = 256 fs 1 = 384 fs
USB/Normal Clock mode select: 0 = Normal 1 = USB
X Reserved
Digital Interface Activation (Address: 0001001)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X RES RES X X X X X ACT
Default 0 0 0 0 0 0 0 0 0
ACT Activate interface 0 = Inactive 1 = Active
X Reserved
Reset Register (Address: 0001111)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function RES RES RES RES RES RES RES RES RES
Default 0 0 0 0 0 0 0 0 0
RES Write 000000000 to this register triggers reset
3.2 Analog Interface
3.2.1 Line Inputs
The TLV320AIC23B has line inputs for the left and the right audio channels (RLINEIN and LLINEIN). Both line inputs
have independently programmable volume controls and mutes. Active and passive filters for the two channels
prevent high frequencies from folding back into the audio band.
The line-input gain is logarithmically adjustable from 12 dB to –34.5 dB in 1.5-dB steps. The ADC full-scale range
is 1.0 VRMS at AVDD = 3.3 V. The full-scale range tracks linearly with analog supply voltage AVDD. To avoid distortions,
it is important not to exceed the full-scale range.
The gain is independently programmable on both left and right line-inputs. To reduce the number of software write
cycles required. Both channels can be locked to the same value by setting the RLS and LRS bits (see Section 3.1.3).
The line inputs are biased internally to VMID. When the line inputs are muted or the device is set to standby mode,
the line inputs are kept biased to VMID using special antithump circuitry. This reduces audible clicks that otherwise
might be heard when reactivating the inputs.
For interfacing to a CD system, the line input should be scaled to 1 VRMS to avoid clipping, using the circuit shown
in Figure 3-3.
R
2
R1
C1
C2 +
CDIN LINEIN
AGND
Where:
R1 = 5 kΩ
R2 = 5 kΩ
C1 = 47 pF
C2 = 470 nF
Figure 3−3. Analog Line Input Circuit
R1 and R2 divide the input signal by two, reducing the 2 VRMS from the CD player to the nominal 1 VRMS of the AIC23B
inputs. C1 filters high-frequency noise, and C2 removes any dc component from the signal.
3−6
3.2.2 Microphone Input
MICIN is a high-impedance, low-capacitance input that is compatible with a wide range of microphones. It has a
programmable volume control and a mute function. Active and passive filters prevent high frequencies from folding
back into the audio band.
The MICIN signal path has two gain stages. The first stage has a nominal gain of G1 = 50 k/10 k = 5. By adding an
external resistor (RMIC) in series with MICIN, the gain of the first stage can be adjusted by G1 = 50 k/(10 k + RMIC).
For example, RMIC = 40 k gives a gain of 0 dB. The second stage has a software programmable gain of 0 dB or 20
dB (see Section 3.1.3).
50 kΩ
10 kΩ
VMID
0 dB/20 dB
To ADC
MICIN
Figure 3−4. Microphone Input Circuit
The microphone input is biased internally to VMID. When the line inputs are muted, the MICIN input is kept biased
to VMID using special antithump circuitry. This reduces audible clicks that may otherwise be heard when reactivating
the input.
The MICBIAS output provides a low-noise reference voltage suitable for biasing electret type microphones and the
associated external resistor biasing network. The maximum source current capability is 3 mA. This limits the smallest
value of external biasing resistors that safely can be used.
The MICBIAS output is not active in standby mode.
3.2.3 Line Outputs
The TLV320AIC23B has two low-impedance line outputs (LLINEOUT and RLINEOUT) capable of driving line loads
with 10-kΩ and 50-pF impedances.
The DAC full-scale output voltage is 1.0 VRMS at AVDD = 3.3 V. The full-scale range tracks linearly with the analog
supply voltage AVDD. The DAC is connected to the line outputs via a low-pass filter that removes out-of-band
components. No further external filtering is required in most applications.
The DAC outputs, line inputs, and the microphone signal are summed into the line outputs. These sources can be
switched off independently. For example, in bypass mode, the line inputs are routed to the line outputs, bypassing
the ADC and the DAC. If sidetone is enabled, the microphone signal is routed to both line outputs via a four-step
programmable attenuation circuit.
The line outputs are muted by either muting the DAC (analog) or soft muting (digital) and disabling the bypass and
sidetone paths (see Section 3.1.3).
3.2.4 Headphone Output
The TLV320AIC23B has stereo headphone outputs (LHPOUT and RHPOUT), and is designed to drive 16-Ω or 32-Ω
headphones. The headphone output includes a high-quality volume control and mute function.
The headphone volume is logarithmically adjustable from 6 dB to –73 dB in 1-dB steps. Writing 000000 to the
volume-control registers (see Section 3.1.3) mutes the headphone output. When the headphone output is muted or
the device is placed in standby mode, the dc voltage is maintained at the outputs to prevent audible clicks.
A zero-cross detection circuit is provided under the control of the LZC and RZC bits. If this circuit is enabled, the
volume-control values are updated only when the input signal to the gain stage is close to the analog ground level.
3−7
This minimizes audible clicks as the volume is changed or the device is muted. This circuit has no time-out, so, if only
dc levels are being applied to the gain stage input of more than 20 mV, the gain is not updated.
The gain is independently programmable on the left and right channels. Both channels can be locked to the same
value by setting the RLS and LRS bits (see Section 3.1.3).
3.2.5 Analog Bypass Mode
The TLV320AIC23B includes a bypass mode in which the analog line inputs are directly routed to the analog line
outputs, bypassing the ADC and DAC. This is enabled by selecting the bypass bit in the analog audio path control
register[see Section 3.1.3).
For a true bypass mode, the output from the DAC and the sidetone should be disabled. The line input and headphone
output volume controls and mutes are still operational in bypass mode. Therefore the line inputs, DAC output, and
microphone input can be summed together. The maximum signal at any point in the bypass path must be no greater
than 1.0Vrms at AVDD=3.3V to avoid clipping and distortion. This amplitude tracks linearly with AVDD.
3.2.6 Sidetone Insertion
The TLV320AIC23B has a sidetone insertion made where the microphone input is routed to the line and headphone
outputs. This is useful for telephony and headset applications. The attenuation of the sidetone signal may be set to
−6 dB, −9 dB, −12 dB, −15 dB, or 0dB, by software selection (see Section 3.1.3). If this mode is used to sum the
microphone input with the DAC output and line inputs, care must be taken not to exceed signal level to avoid clipping
and distortion.
3.3 Digital Audio Interface
3.3.1 Digital Audio-Interface Modes
The TLV320AIC23B supports four audio-interface modes.
• Right justified
• Left justified
• I2S mode
• DSP mode
The four modes are MSB first and operate with a variable word width between 16 to 32 bits (except right-justified
mode, which does not support 32 bits).
The digital audio interface consists of clock signal BCLK, data signals DIN and DOUT, and synchronization signals
LRCIN and LRCOUT. BCLK is an output in master mode and an input in slave mode.
3.3.1.1 Right-Justified Mode
In right-justified mode, the LSB is available on the rising edge of BCLK, preceding a falling edge on LRCIN or LRCOUT
(see Figure 3-5).
LRCIN/
BCLK
DIN/ n n−1 1 0 n n−1
1/fs
Left Channel Right Channel
0 1 0
MSB LSB
LRCOUT
DOUT
Figure 3−5. Right-Justified Mode Timing
3.3.1.2 Left-Justified Mode
In left-justified mode, the MSB is available on the rising edge of BCLK, following a rising edge on LRCIN or LRCOUT
(see Figure 3-6)
3−8
LRCIN/
BCLK
DIN/
n n−1 1 0 n n−1
1/fs
Left Channel Right Channel
1 0 n
MSB LSB
LRCOUT
DOUT
Figure 3−6. Left-Justified Mode Timing
3.3.1.3 I2S Mode
In I2S mode, the MSB is available on the second rising edge of BCLK, after the falling edge on LRCIN or LRCOUT
(see Figure 3-7).
LRCIN/
BCLK
DIN/ n n−1 1 0 n n−1
1/fs
Left Channel Right Channel
1 0
MSB LSB
1BCLK
LRCOUT
DOUT
Figure 3−7. I2S Mode Timing
3.3.1.4 DSP Mode
The DSP mode is compatible with the McBSP ports of TI DSPs. LRCIN and LRCOUT must be connected to the Frame
Sync signal of the McBSP. A falling edge on LRCIN or LRCOUT starts the data transfer. The left-channel data consists
of the first data word, which is immediately followed by the right channel data word (see Figure 3-8). Input word length
is defined by the IWL register. Figure 3−8 shows LRP = 1 (default LRP = 0).
LRCIN/
BCLK
DIN/
n n−1 1 0 n n−1
Left Channel Right Channel
1 0
MSB LSB MSB LSB
LRCOUT
DOUT
Figure 3−8. DSP Mode Timing
3−9
3.3.2 Audio Sampling Rates
The TLV320AIC23B can operate in master or slave clock mode. In the master mode, the TLV320AIC23B clock and
sampling rates are derived from a 12-MHz MCLK signal. This 12-MHz clock signal is compatible with the USB
specification. The TLV320AIC23B can be used directly in a USB system.
In the slave mode, an appropriate MCLK or crystal frequency and the sample rate control register settings control
the TLV320AIC23B clock and sampling rates.
The settings in the sample rate control register control the clock mode and sampling rates.
Sample Rate Control (Address: 0001000)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Normal
Default 0 0 0 1 0 0 0 0 0
CLKOUT Clock output divider 0 = MCLK 1 = MCLK/2
CLKIN Clock input divider 0 = MCLK 1 = MCLK/2
SR[3:0] Sampling rate control (see Sections 3.3.2.1 and 3.3.2.2)
BOSR Base oversampling rate
USB mode: 0 = 250 fs 1 = 272 fs
Normal mode: 0 = 256 fs 1 = 384 fs
USB/Normal Clock mode select: 0 = Normal 1 = USB
X Reserved
The clock circuit of the AIC23B has two internal dividers. The first, controlled by CLKIN, applies to the sampling-rate
generator of the codec. The second, controlled by CLKOUT, applies only to the CLKOUT terminal. By setting CLKIN
to 1, the entire codec is clocked with half the frequency, effectively dividing the resulting sampling rates by two. The
following sampling-rate tables are based on CLKIN = MCLK.
3.3.2.1 USB-Mode Sampling Rates (MCLK = 12 MHz)
In the USB mode, the following ADC and DAC sampling rates are available:
SAMPLING RATE†
SAMPLING-RATE CONTROL SETTINGS
ADC
DAC
FILTER TYPE
(kHz)
(kHz)
SR3 SR2 SR1 SR0 BOSR
96 96 3 0 1 1 1 0
88.2 88.2 2 1 1 1 1 1
48 48 0 0 0 0 0 0
44.1 44.1 1 1 0 0 0 1
32 32 0 0 1 1 0 0
8.021 8.021 1 1 0 1 1 1
8 8 0 0 0 1 1 0
48 8 0 0 0 0 1 0
44.1 8.021 1 1 0 0 1 1
8 48 0 0 0 1 0 0
8.021 44.1 1 1 0 1 0 1
† The sampling rates are derived from the 12-MHz master clock. The available oversampling rates do not produce exactly 8-kHz, 44.1-kHz, and
88.2-kHz sampling rates, but 8.021 kHz, 44.117 kHz, and 88.235 kHz, respectively. See Figures 3−17 through 3−34 for filter responses
3−10
3.3.2.2 Normal-Mode Sampling Rates
In normal mode, the following ADC and DAC sampling rates, depending on the MCLK frequency, are available:
MCLK = 12.288 MHz
SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS
ADC
DAC
FILTER TYPE
(kHz)
(kHz)
SR3 SR2 SR1 SR0 BOSR
96 96 2 0 1 1 1 0
48 48 1 0 0 0 0 0
32 32 1 0 1 1 0 0
8 8 1 0 0 1 1 0
48 8 1 0 0 0 1 0
8 48 1 0 0 1 0 0
MCLK = 11.2896 MHz
SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS
ADC
DAC
FILTER TYPE
(kHz)
(kHz)
SR3 SR2 SR1 SR0 BOSR
88.2 88.2 2 1 1 1 1 0
44.1 44.1 1 1 0 0 0 0
8.021 8.021 1 1 0 1 1 0
44.1 8.021 1 1 0 0 1 0
8.021 44.1 1 1 0 1 0 0
MCLK = 18.432 MHz
SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS
ADC
DAC
FILTER TYPE
(kHz)
(kHz)
SR3 SR2 SR1 SR0 BOSR
96 96 2 0 1 1 1 1
48 48 1 0 0 0 0 1
32 32 1 0 1 1 0 1
8 8 1 0 0 1 1 1
48 8 1 0 0 0 1 1
8 48 1 0 0 1 0 1
MCLK = 16.9344 MHz
SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS
ADC
DAC
FILTER TYPE
(kHz)
(kHz)
SR3 SR2 SR1 SR0 BOSR
88.2 88.2 2 1 1 1 1 1
44.1 44.1 1 1 0 0 0 1
8.021 8.021 1 1 0 1 1 1
44.1 8.021 1 1 0 0 1 1
8.021 44.1 1 1 0 1 0 1
3−11
3.3.3 Digital Filter Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC Filter Characteristics ( TI DSP 250 fs Mode Operation )
Passband ±0.05 dB 0.416 fs Hz
Stopband −6 dB 0.5 fs Hz
Passband ripple ±0.05 dB
Stopband attenuation f > 0.584 fs −60 dB
ADC Filter Characteristics ( TI DSP 272 fs and Normal Mode Operation )
Passband ±0.05 dB 0.4535 fs Hz
Stopband −6 dB 0.5 fs Hz
Passband ripple ±0.05 dB
Stopband attenuation f > 0.5465 fs −60 dB
ADC High-Pass Filter Characteristics
−3 dB, fs = 44.1 kHz 3.7 Hz
−3 dB, fs = 48 kHz 4.0 Hz
Corner frequency
−0.5 dB, fs = 44.1 kHz 10.4 Hz
−0.5 dB, fs = 48 kHz 11.3 Hz
−0.1 dB fs = 44.1 kHz 21.6 Hz
−0.1 dB, fs = 48 kHz 23.5 Hz
DAC Filter Characteristics (48-kHz Sampling Rate)
Passband ±0.03 dB 0.416 fs Hz
Stopband −6 dB 0.5 fs Hz
Passband ripple ±0.03 dB
Stopband attenuation f > 0.584 fs −50 dB
DAC Filter Characteristics (44.1-kHz Sampling Rate)
Passband ±0.03 dB 0.4535 fs Hz
Stopband −6 dB 0.5 fs Hz
Passband ripple ±0.03 dB
Stopband attenuation f > 0.5465 fs −50 dB
3−12
−6
−8
−10
Filter Response − dB
−4
−2
Normalized Audio Sampling Frequency
0
0 0.1 0.2 0.3
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
0.4 0.5
Figure 3−9. Digital De-Emphasis Filter Response − 44.1 kHz Sampling
−6
−8
−10
0 0.10 0.20 0.30
Filter Response − dB
−4
−2
Normalized Audio Sampling Frequency
0
0.40 0.50
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−10. Digital De-Emphasis Filter Response − 48 kHz Sampling
3−13
−70
−90
0 0.5 1 1.5
−50
−10
10
2 2.5 3
−30
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−11. ADC Digital Filter Response 0: USB Mode
(Group Delay = 12 Output Samples)
−0.04
−0.10
0 0.05 0.1 0.15 0.2 0.25 0.3
0
0.08
0.10
0.35 0.4 0.45 0.5
0.06
0.04
0.02
−0.02
−0.06
−0.08
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−12. ADC Digital Filter Ripple 0: USB
(Group Delay = 20 Output Samples)
3−14
−50
−90
0 0.5 1 1.5 2
−30
−10
10
2.5 3
−70
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−13. ADC Digital Filter Response 1: USB Mode Only
−0.04
−0.10
0 0.05 0.1 0.15 0.2 0.25 0.3
0
0.08
0.10
0.35 0.4 0.45 0.5
0.06
0.04
0.02
−0.02
−0.06
−0.08
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−14. ADC Digital Filter Ripple 1: USB Mode Only
3−15
−70
−90
0 0.5 1 1.5
−50
−10
10
2 2.5 3
−30
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−15. ADC Digital Filter Response 2: USB mode and Normal Modes
(Group Delay = 3 Output Samples)
−0.2
−0.4
0 0.05 0.1 0.15 0.2 0.25 0.3
0
0.3
0.4
0.35 0.4 0.45 0.5
0.2
0.1
−0.1
−0.3
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−16. ADC Digital Filter Ripple 2: USB Mode and Normal Modes
3−16
−50
−90
0 0.5 1 1.5
−30
−10
10
2 2.5 3
−70
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−17. ADC Digital Filter Response 3: USB Mode Only
−0.2
−0.4
0 0.05 0.10 0.15 0.20 0.25 0.30
0
0.3
0.4
0.35 0.40 0.45 0.50
0.2
0.1
−0.1
−0.3
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−18. ADC Digital Filter Ripple 3: USB Mode Only
3−17
−90
0 0.5 1 1.5
10
2 2.5 3
−10
−30
−50
−70
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−19. DAC Digital Filter Response 0: USB Mode
−0.04
−0.10
0 0.05 0.1 0.15 0.2 0.25 0.3
0
0.08
0.10
0.35 0.4 0.45 0.5
0.06
0.04
0.02
−0.02
−0.06
−0.08
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−20. DAC Digital Filter Ripple 0: USB Mode
3−18
−50
−90
0 0.5 1 1.5
−30
−10
10
2 2.5 3
−70
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−21. DAC Digital Filter Response 1: USB Mode Only
−0.04
−0.10
0 0.05 0.1 0.15 0.2 0.25 0.3
0.06
0.08
0.10
0.35 0.4 0.45 0.5
0.04
0.02
0
−0.02
−0.06
−0.08
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−22. DAC Digital Filter Ripple 1: USB Mode Only
3−19
−50
−90
0 0.5 1 1.5
−30
−10
10
2 2.5 3
−70
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−23. DAC Digital Filter Response 2: USB Mode and Normal Modes
−0.2
−0.4
0 0.05 0.1 0.15 0.2 0.25 0.3
0.2
0.3
0.4
0.35 0.4 0.45 0.5
0.1
0
−0.1
−0.3
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−24. DAC Digital Filter Ripple 2: USB Mode and Normal Modes
3−20
−70
−90
0 0.5 1 1.5
−30
−10
10
2 2.5 3
−50
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−25. DAC Digital Filter Response 3: USB Mode Only
−0.2
−0.4
0 0.05 0.1 0.15 0.2 0.25 0.3
0
0.3
0.4
0.35 0.4 0.45 0.5
0.2
0.1
−0.1
−0.3
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−26. DAC Digital Filter Ripple 3: USB Mode Only
The delay between the converter is a function of the sample rate. The group delays for the AIC23B are shown in the
following table. Each delay is one LR clock (1/sample rate).
Table 3−1. Group Dealys
FILTER GROUP DELAY
DAC type 0 11
DAC type 1 18
DAC type 2 5
DAC type 3 5
ADC type 0 12
ADC type 1 20
ADC type 2 3
ADC type 3 6
A−1
Appendix A
Mechanical Data
GQE/ZQE (S-PBGA-N80) PLASTIC BALL GRID ARRAY
5 6 7 8 9
J
H
G
F
E
D
1 2 3
C
B
A
4
4,00 TYP
5,10
4,90
SQ
0,50
0,50
4200461/C 10/00
Seating Plane
0,62
0,68
0,25
0,35
1,00 MAX
∅ 0,05 M 0,08
0,11
0,21
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar Junior BGA configuration
D. Falls within JEDEC MO-225
MicroStar Junior is a trademark of Texas Instruments.
A−2
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 0,10 M
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
16 20
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0°−8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
A−3
RHD (S−PQFP−N28) PLASTIC QUAD FLATPACK
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
B
0,08 C
D
4204400/A 05/02
1
28
0,05 MAX
SEATING PLANE
5,00
0,80
1,00
5,00
3,25
3,00
0,20 REF
DIE PAD
3,00
A
C
SQ
1
28
0,65
280,45
0,50
0,18
0,30
0,10 M C A B
EXPOSED THERMAL
0,435
0,435
0,18
0,18
PIN 1
INDEX AREA
IDENTIFIER
PIN 1
4
28
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. QFN (Quad Flatpack No−Lead) Package configuration.
D. The Package thermal performance may be enhanced by bonding the thermal die pad to
an external thermal plane. This pad is electrically and thermally connected to the backside
of the die and possibly selected ground leads.
E. Package complies to JEDEC MO-220.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLV320AIC23BGQE ACTIVE BGA
MICROSTAR
JUNIOR
GQE 80 360 TBD SNPB Level-2A-235C-4 WKS 0 to 70 AIC23BG
TLV320AIC23BIGQE ACTIVE BGA
MICROSTAR
JUNIOR
GQE 80 360 TBD SNPB Level-2A-235C-4 WKS -40 to 85 AIC23BIG
TLV320AIC23BIPW ACTIVE TSSOP PW 28 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 AIC23BI
TLV320AIC23BIPWG4 ACTIVE TSSOP PW 28 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 AIC23BI
TLV320AIC23BIPWR ACTIVE TSSOP PW 28 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 AIC23BI
TLV320AIC23BIPWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 AIC23BI
TLV320AIC23BIRHD ACTIVE VQFN RHD 28 73 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AIC23BI
TLV320AIC23BIRHDG4 ACTIVE VQFN RHD 28 73 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AIC23BI
TLV320AIC23BIRHDR ACTIVE VQFN RHD 28 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AIC23BI
TLV320AIC23BIZQE ACTIVE BGA
MICROSTAR
JUNIOR
ZQE 80 360 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR -40 to 85 AIC23BIZ
TLV320AIC23BIZQER OBSOLETE BGA
MICROSTAR
JUNIOR
ZQE 80 TBD Call TI Call TI -40 to 85 AIC23BIZ
TLV320AIC23BPW ACTIVE TSSOP PW 28 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 AIC23B
TLV320AIC23BPWG4 ACTIVE TSSOP PW 28 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 AIC23B
TLV320AIC23BPWR ACTIVE TSSOP PW 28 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 AIC23B
TLV320AIC23BPWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 AIC23B
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLV320AIC23BRHD ACTIVE VQFN RHD 28 73 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR 0 to 70 AIC23B
TLV320AIC23BRHDG4 ACTIVE VQFN RHD 28 73 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR 0 to 70 AIC23B
TLV320AIC23BRHDR ACTIVE VQFN RHD 28 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR 0 to 70 AIC23B
TLV320AIC23BRHDRG4 ACTIVE VQFN RHD 28 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR 0 to 70 AIC23B
TLV320AIC23BZQE ACTIVE BGA
MICROSTAR
JUNIOR
ZQE 80 360 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR 0 to 70 AIC23BZ
TLV320AIC23BZQER ACTIVE BGA
MICROSTAR
JUNIOR
ZQE 80 2500 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR 0 to 70 AIC23BZ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
Addendum-Page 3
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV320AIC23B :
• Automotive: TLV320AIC23B-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TLV320AIC23BIPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
TLV320AIC23BIRHDR VQFN RHD 28 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TLV320AIC23BPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
TLV320AIC23BRHDR VQFN RHD 28 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TLV320AIC23BZQER BGA MI
CROSTA
R JUNI
OR
ZQE 80 2500 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV320AIC23BIPWR TSSOP PW 28 2000 367.0 367.0 38.0
TLV320AIC23BIRHDR VQFN RHD 28 3000 338.1 338.1 20.6
TLV320AIC23BPWR TSSOP PW 28 2000 367.0 367.0 38.0
TLV320AIC23BRHDR VQFN RHD 28 3000 338.1 338.1 20.6
TLV320AIC23BZQER BGA MICROSTAR
JUNIOR
ZQE 80 2500 338.1 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
FEATURES High accuracy; supports IEC 60687/61036/61268 and IEC 62053-21/62053-22/62053-23 On-chip digital integrator enables direct interface to current
sensors with di/dt output A PGA in the current channel allows direct interface to shunts and current transformers
Active, reactive, and apparent energy; sampled waveform; current and voltage rms Less than 0.1% error in active energy measurement over a dynamic range of 1000 to 1 at 25°C Positive-only energy accumulation mode available On-chip user programmable threshold for line voltage surge
and SAG and PSU supervisory Digital calibration for power, phase, and input offset
On-chip temperature sensor (±3°C typical)
SPI® compatible serial interface
Pulse output with programmable frequency
Interrupt request pin (IRQ) and status register Reference 2.4 V with external overdrive capability Single 5 V supply, low power (25 mW typical)
GENERAL DESCRIPTION
The ADE77531 features proprietary ADCs and DSP for high accuracy over large variations in environmental conditions and
time. The ADE7753 incorporates two second-order 16-bit -Δ
ADCs, a digital integrator (on CH1), reference circuitry, temperature sensor, and all the signal processing required to perform active, reactive, and apparent energy measurements, line-voltage period measurement, and rms calculation on the
voltage and current. The selectable on-chip digital integrator provides direct interface to di/dt current sensors such as Rogowski coils, eliminating the need for an external analog
integrator and resulting in excellent long-term stability and pre-
cise phase matching between the current and voltage channels. The ADE7753 provides a serial interface to read data, and a
pulse output frequency (CF), which is proportional to the active power. Various system calibration features, i.e., channel offset
correction, phase calibration, and power calibration, ensure
high accuracy. The part also detects short duration low or high voltage variations. The positive-only accumulation mode gives the option to accumulate energy only when positive power is detected. An internal no-load threshold ensures that the part does not exhibit
any creep when there is no load. The zero-crossing output (ZX)
produces a pulse that is synchronized to the zero-crossing point
of the line voltage. This signal is used internally in the line cycle
active and apparent energy accumulation modes, which enables
faster calibration. The interrupt status register indicates the nature of the interrupt,
and the interrupt enable register controls which event produces an output on the IRQ pin, an open-drain, active low logic output.
The ADE7753 is available in a 20-lead SSOP package. FUNCTIONAL BLOCK DIAGRAM
AVDD RESET DVDDDGND
TEMP
SENSOR
ADC
ADC
DFC
x2
ADE7753
LPF2 MULTIPLIER
INTEGRATOR
CLKIN CLKOUT DINDOUTSCLK REFIN/OUT CS IRQ AGND
APOS[15:0]
VAGAIN[11:0]
VADIV[7:0]
IRMSOS[11:0]
VRMSOS[11:0]
WGAIN[11:0]
dt
REGISTERS AND
SERIAL INTERFACE
CFNUM[11:0]
CFDEN[11:0]
2.4V
REFERENCE
4k
PHCAL[5:0]
HPF1
LPF1
02875-A-001
V1P
V1N
V2N
V2P
PGA
PGA
ZX
SAG
CF
WDIV[7:0] % %
2
|x|
Figure 1.
1U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469.
ADE7753
Rev. C | Page 2 of 60
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Timing Characteristics ..................................................................... 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Terminology ...................................................................................... 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 16
Analog Inputs .............................................................................. 16
di/dt Current Sensor and Digital Integrator ............................... 17
Zero-Crossing Detection ........................................................... 18
Period Measurement .................................................................. 19
Power Supply Monitor ............................................................... 19
Line Voltage Sag Detection ....................................................... 19
Peak Detection ............................................................................ 20
ADE7753 Interrupts ................................................................... 21
Temperature Measurement ....................................................... 22
ADE7753 Analog-to-Digital Conversion ................................ 22
Channel 1 ADC .......................................................................... 23
Channel 2 ADC .......................................................................... 25
Phase Compensation .................................................................. 27
Active Power Calculation .......................................................... 28
Energy Calculation ..................................................................... 29
Power Offset Calibration ........................................................... 31
Energy-to-Frequency Conversion............................................ 31
Line Cycle Energy Accumulation Mode ................................. 33
Positive-Only Accumulation Mode ......................................... 33
No-Load Threshold .................................................................... 33
Reactive Power Calculation ...................................................... 33
Sign of Reactive Power Calculation ......................................... 35
Apparent Power Calculation ..................................................... 35
Apparent Energy Calculation ................................................... 36
Line Apparent Energy Accumulation ...................................... 37
Energies Scaling .......................................................................... 38
Calibrating an Energy Meter Based on the ADE7753 ........... 38
CLKIN Frequency ...................................................................... 48
Suspending ADE7753 Functionality ....................................... 48
Checksum Register..................................................................... 48
ADE7753 Serial Interface .......................................................... 49
ADE7753 Registers ......................................................................... 52
ADE7753 Register Descriptions ................................................... 55
Communications Register ......................................................... 55
Mode Register (0x09) ................................................................. 55
Interrupt Status Register (0x0B), Reset Interrupt Status Register (0x0C), Interrupt Enable Register (0x0A) .............. 57
CH1OS Register (0x0D) ............................................................ 58
Outline Dimensions ....................................................................... 59
Ordering Guide .......................................................................... 59
ADE7753
Rev. C | Page 3 of 60
REVISION HISTORY
1/10—Rev. B to Rev C
Changes to Figure 1 ........................................................................... 1
Changes to t6 Parameter (Table 2) ................................................... 6
Added Endnote 1 to Table 4 ............................................................. 9
Changes to Figure 32 ...................................................................... 16
Changes to Period Measurement Section .................................... 19
Changes to Temperature Measurement Section ......................... 22
Changes to Figure 51 ...................................................................... 24
Changes to Channel 1 RMS Calculation Section ........................ 25
Added Table 7 .................................................................................. 25
Changes to Channel 2 RMS Calculation Section ........................ 26
Added Table 8 .................................................................................. 26
Changes to Figure 64 ...................................................................... 29
Changes to Apparent Power Calculation Section ....................... 35
1/09—Rev. A to Rev B
Changes to Features Section ............................................................ 1
Changes to Zero-Crossing Detection Section and Period Measurement Section ..................................................................... 19
Changes to Channel 1 RMS Calculation Section, Channel 1 RMS Offset Compensation Section, and Equation 4 ................. 25
Changes to Figure 56 and Channel 2 RMS Calculation Section .............................................................................................. 26
Changes to Figure 57 ...................................................................... 27
Changes to Energy Calculation Section ....................................... 30
Changes to Energy-to-Frequency Conversion Section .............. 31
Changes to Apparent Energy Calculation Section...................... 36
Changes to Line Apparent Energy Accumulation Section ........ 37
Changes to Table 10 ........................................................................ 52
Changes to Table 12 ........................................................................ 56
Changes to Table 13 ........................................................................ 57
Changes to Ordering Guide ........................................................... 59
6/04—Rev. 0 to Rev A
Changes IEC Standards .................................................................... 1
Changes to Phase Error Between Channels Definition ............... 7
Changes to Figure 24 ...................................................................... 13
Changes to CH2OS Register .......................................................... 16
Change to the Period Measurement Section ............................... 18
Change to Temperature Measurement Section ........................... 21
Changes to Figure 69 ...................................................................... 31
Changes to Figure 71 ...................................................................... 33
Changes to the Apparent Energy Section .................................... 36
Changes to Energies Scaling Section ............................................ 37
Changes to Calibration Section ..................................................... 37
8/03—Revision 0: Initial Version
ADE7753
Rev. C | Page 4 of 60
SPECIFICATIONS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = −40°C to +85°C. See the plots in the Typical Performance Characteristics section.
Table 1.
Parameter
Spec
Unit
Test Conditions/Comments
ENERGY MEASUREMENT ACCURACY
Active Power Measurement Error
CLKIN = 3.579545 MHz
Channel 1 Range = 0.5 V Full Scale
Channel 2 = 300 mV rms/60 Hz, gain = 2
Gain = 1
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 2
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 4
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 8
0.1
% typ
Over a dynamic range 1000 to 1
Channel 1 Range = 0.25 V Full Scale
Gain = 1
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 2
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 4
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 8
0.2
% typ
Over a dynamic range 1000 to 1
Channel 1 Range = 0.125 V Full Scale
Gain = 1
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 2
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 4
0.2
% typ
Over a dynamic range 1000 to 1
Gain = 8
0.2
% typ
Over a dynamic range 1000 to 1
Active Power Measurement Bandwidth
14
kHz
Phase Error 1 between Channels1
±0.05
max
Line Frequency = 45 Hz to 65 Hz, HPF on
AC Power Supply Rejection1
AVDD = DVDD = 5 V + 175 mV rms/120 Hz
Output Frequency Variation (CF)
0.2
% typ
Channel 1 = 20 mV rms, gain = 16, range = 0.5 V
Channel 2 = 300 mV rms/60 Hz, gain = 1
DC Power Supply Rejection1
AVDD = DVDD = 5 V ± 250 mV dc
Output Frequency Variation (CF)
±0.3
% typ
Channel 1 = 20 mV rms/60 Hz, gain = 16, range = 0.5 V
Channel 2 = 300 mV rms/60 Hz, gain = 1
IRMS Measurement Error
0.5
% typ
Over a dynamic range 100 to 1
IRMS Measurement Bandwidth
14
kHz
VRMS Measurement Error
0.5
% typ
Over a dynamic range 20 to 1
VRMS Measurement Bandwidth
140
Hz
ANALOG INPUTS2
See the Analog Inputs section
Maximum Signal Levels
±0.5
V max
V1P, V1N, V2N, and V2P to AGND
Input Impedance (dc)
390
k min
Bandwidth
14
kHz
CLKIN/256, CLKIN = 3.579545 MHz
Gain Error1, 2
External 2.5 V reference, gain = 1 on Channels 1 and 2
Channel 1
Range = 0.5 V Full Scale
±4
% typ
V1 = 0.5 V dc
Range = 0.25 V Full Scale
±4
% typ
V1 = 0.25 V dc
Range = 0.125 V Full Scale
±4
% typ
V1 = 0.125 V dc
Channel 2
±4
% typ
V2 = 0.5 V dc
Offset Error1
±32
mV max
Gain 1
Channel 1
±13
mV max
Gain 16
±32
mV max
Gain 1
Channel 2
±13
mV max
Gain 16
WAVEFORM SAMPLING
Sampling CLKIN/128, 3.579545 MHz/128 = 27.9 kSPS
Channel 1
See the Channel 1 Sampling section
Signal-to-Noise Plus Distortion
62
dB typ
150 mV rms/60 Hz, range = 0.5 V, gain = 2
Bandwidth(–3 dB)
14
kHz
CLKIN = 3.579545 MHz
ADE7753
Rev. C | Page 5 of 60
Parameter Spec Unit Test Conditions/Comments
Channel 2
See the Channel 2 Sampling section
Signal-to-Noise Plus Distortion
60
dB typ
150 mV rms/60 Hz, gain = 2
Bandwidth (–3 dB)
140
Hz
CLKIN = 3.579545 MHz
REFERENCE INPUT
REFIN/OUT Input Voltage Range
2.6
V max
2.4 V + 8%
2.2
V min
2.4 V – 8%
Input Capacitance
10
pF max
ON-CHIP REFERENCE
Nominal 2.4 V at REFIN/OUT pin
Reference Error
±200
mV max
Current Source
10
μA max
Output Impedance
3.4
kΩ min
Temperature Coefficient
30
ppm/°C typ
CLKIN
All specifications CLKIN of 3.579545 MHz
Input Clock Frequency
4
MHz max
1
MHz min
LOGIC INPUTS
RESET, DIN, SCLK, CLKIN, and CS
Input High Voltage, VINH
2.4
V min
DVDD = 5 V ± 10%
Input Low Voltage, VINL
0.8
V max
DVDD = 5 V ± 10%
Input Current, IIN
±3
μA max
Typically 10 nA, VIN = 0 V to DVDD
Input Capacitance, CIN
10
pF max
LOGIC OUTPUTS
SAG and IRQ
Open-drain outputs, 10 kΩ pull-up resistor
Output High Voltage, VOH
4
V min
ISOURCE = 5 mA
Output Low Voltage, VOL 0.4
V max
ISINK = 0.8 mA
ZX and DOUT
Output High Voltage, VOH
4
V min
ISOURCE = 5 mA
Output Low Voltage, VOL 0.4
V max
ISINK = 0.8 mA
CF
Output High Voltage, VOH
4
V min
ISOURCE = 5 mA
Output Low Voltage, VOL 1
V max
ISINK = 7 mA
POWER SUPPLY
For specified performance
AVDD
4.75
V min
5 V – 5%
5.25
V max
5 V + 5%
DVDD
4.75
V min
5 V – 5%
5.25
V max
5 V + 5%
AIDD
3
mA max
Typically 2.0 mA
DIDD
4
mA max
Typically 3.0 mA
1 See the Terminology section for explanation of specifications.
2 See the Analog Inputs section.
+2.1V1.6mAIOHIOl200μACL50pF02875-0-002TOOUTPUTPIN
Figure 2. Load Circuit for Timing Specifications
ADE7753
Rev. C | Page 6 of 60
TIMING CHARACTERISTICS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = −40°C to +85°C. Sample tested during initial release and after any redesign or process change that could affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. See Figure 3, Figure 4, and the ADE7753 Serial Interface section.
Table 2.
Parameter
Spec
Unit
Test Conditions/Comments
Write Timing
t1
50
ns (min)
CS falling edge to first SCLK falling edge.
t2
50
ns (min)
SCLK logic high pulse width.
t3
50
ns (min)
SCLK logic low pulse width.
t4
10
ns (min)
Valid data setup time before falling edge of SCLK.
t5
5
ns (min)
Data hold time after SCLK falling edge.
t6
4
μs (min)
Minimum time between the end of data byte transfers.
t7
50
ns (min)
Minimum time between byte transfers during a serial write.
t8
100
ns (min)
CS hold time after SCLK falling edge.
Read Timing
t91
4
μs (min)
Minimum time between read command (i.e., a write to communication register) and data read.
t10
50
ns (min)
Minimum time between data byte transfers during a multibyte read.
t11
30
ns (min)
Data access time after SCLK rising edge following a write to the communications register.
t122
100
ns (max)
Bus relinquish time after falling edge of SCLK.
10
ns (min)
t133
100
ns (max)
Bus relinquish time after rising edge of CS.
10
ns (min)
1 Minimum time between read command and data read for all registers except waveform register, which is t9 = 500 ns min.
2 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
3 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. DINSCLKCSt2t3t1t4t5t7t6t8COMMAND BYTEMOST SIGNIFICANT BYTELEAST SIGNIFICANT BYTE10A4A5A3A2A1A0DB7DB0DB7DB0t702875-0-081
Figure 3. Serial Write Timing SCLKCSt1t10t1300A4A5A3A2A1A0DB0DB7DB0DB7DINDOUTt11t11t12COMMAND BYTEMOST SIGNIFICANT BYTELEAST SIGNIFICANT BYTEt902875-0-083
Figure 4. Serial Read Timing
ADE7753
Rev. C | Page 7 of 60
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Rating
AVDD to AGND
–0.3 V to +7 V
DVDD to DGND
–0.3 V to +7 V
DVDD to AVDD
–0.3 V to +0.3 V
Analog Input Voltage to AGND, V1P, V1N, V2P, and V2N
–6 V to +6 V
Reference Input Voltage to AGND
–0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND
–0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND
–0.3 V to DVDD + 0.3 V
Operating Temperature Range
Industrial
–40°C to +85°C
Storage Temperature Range
–65°C to +150°C
Junction Temperature
150°C
20-Lead SSOP, Power Dissipation
450 mW
θJA Thermal Impedance
112°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec)
215°C
Infrared (15 sec)
220°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ADE7753
Rev. C | Page 8 of 60
TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the ADE7753 is defined by the following formula: %1007753×⎟⎟⎠⎞⎜⎜⎝⎛−=EnergyTrueEnergyTrueADERegisterEnergyErrorPercentage
Phase Error between Channels
The digital integrator and the high-pass filter (HPF) in Channel 1 have a non-ideal phase response. To offset this phase response and equalize the phase response between channels, two phase-correction networks are placed in Channel 1: one for the digital integrator and the other for the HPF. The phase correction networks correct the phase response of the corresponding component and ensure a phase match between Channel 1 (current) and Channel 2 (voltage) to within ±0.1° over a range of 45 Hz to 65 Hz with the digital integrator off. With the digital integrator on, the phase is corrected to within ±0.4° over a range of 45 Hz to 65 Hz.
Power Supply Rejection
This quantifies the ADE7753 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when an ac (175 mV rms/120 Hz) signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading—see the Measurement Error definition.
For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±5%. Any error introduced is again expressed as a percentage of the reading.
ADC Offset Error
The dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection—see the Typical Performance Characteristics section. However, when HPF1 is switched on, the offset is removed from Channel 1 (current) and the power calculation is not affected by this offset. The offsets can be removed by performing an offset calibration—see the Analog Inputs section.
Gain Error
The difference between the measured ADC output code (minus the offset) and the ideal output code—see the Channel 1 ADC and Channel 2 ADC sections. It is measured for each of the input ranges on Channel 1 (0.5 V, 0.25 V, and 0.125 V). The difference is expressed as a percentage of the ideal code.
ADE7753
Rev. C | Page 9 of 60
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V2N6V2P7AGND8REFIN/OUT9DGND10CLKINIRQSAGZXCF1514131211ADE7753TOP VIEW(Not to Scale)DVDD2AVDD3V1P4V1N5DOUTSCLKCSCLKOUT1918RESET1DIN20171602875-0-005
Figure 5. Pin Configuration (SSOP Package)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RESET1
Reset Pin for the ADE7753. A logic low on this pin holds the ADCs and digital circuitry (including the serial interface) in a reset condition.
2
DVDD
Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7753. The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to DGND with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
3
AVDD
Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7753. The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. The typical performance graphs show the power supply rejection performance. This pin should be decoupled to AGND with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
4, 5
V1P, V1N
Analog Inputs for Channel 1. This channel is intended for use with a di/dt current transducer such as a Rogowski coil or another current sensor such as a shunt or current transformer (CT). These inputs are fully differential voltage inputs with maximum differential input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V, depending on the full-scale selection—see the Analog Inputs section. Channel 1 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±0.5 V. Both inputs have internal ESD protection circuitry, and, in addition, an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage.
6, 7
V2N, V2P
Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These inputs are fully differential voltage inputs with a maximum differential signal level of ±0.5 V. Channel 2 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±0.5 V. Both inputs have internal ESD protection circuitry, and an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage.
8
AGND
Analog Ground Reference. This pin provides the ground reference for the analog circuitry in the ADE7753, i.e., ADCs and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, for example, anti-aliasing filters, current and voltage transducers, etc. To keep ground noise around the ADE7753 to a minimum, the quiet ground plane should connected to the digital ground plane at only one point. It is acceptable to place the entire device on the analog ground plane.
9
REFIN/OUT
Access to the On-Chip Voltage Reference. The on-chip reference has a nominal value of 2.4 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source can also be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 μF ceramic capacitor.
10
DGND
Digital Ground Reference. This pin provides the ground reference for the digital circuitry in the ADE7753, i.e., multiplier, filters, and digital-to-frequency converter. Because the digital return currents in the ADE7753 are small, it is acceptable to connect this pin to the analog ground plane of the system. However, high bus capacitance on the DOUT pin could result in noisy digital current, which could affect performance.
11
CF
Calibration Frequency Logic Output. The CF logic output gives active power information. This output is intended to be used for operational and calibration purposes. The full-scale output frequency can be adjusted by writing to the CFDEN and CFNUM registers—see the Energy-to-Frequency Conversion section.
ADE7753
Rev. C | Page 10 of 60
Pin No. Mnemonic
Description
12
ZX
Voltage Waveform (Channel 2) Zero-Crossing Output. This output toggles logic high and logic low at the zero crossing of the differential signal on Channel 2—see the Zero-Crossing Detection section.
13
SAG
This open-drain logic output goes active low when either no zero crossings are detected or a low voltage threshold (Channel 2) is crossed for a specified duration—see the Line Voltage Sag Detection section.
14
IRQ
Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts include active energy register rollover, active energy register at half level, and arrivals of new waveform samples—see the ADE7753 Interrupts section.
15
CLKIN
Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7753. The clock frequency for specified operation is 3.579545 MHz. Ceramic load capacitors of between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for load capacitance requirements.
16
CLKOUT
A crystal can be connected across this pin and CLKIN as described for Pin 15 to provide a clock source for the ADE7753. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used.
17
CS
Chip Select. Part of the 4-wire SPI serial interface. This active low logic input allows the ADE7753 to share the serial bus with several other devices—see the ADE7753 Serial Interface section.
18
SCLK
Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this clock—see the ADE7753 Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock source that has a slow edge transition time, for example, opto-isolator output.
19
DOUT
Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic output is normally in a high impedance state unless it is driving data onto the serial data bus—see the ADE7753 Serial Interface section.
20
DIN
Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK—see the ADE7753 Serial Interface section.
1 It is recommended to drive the RESET, SCLK, and CS pins with either a push-pull without an external series resistor or with an open-collector with a 10 kΩ pull-up resistor. Pull-down resistors are not recommended because under some conditions, they may interact with internal circuitry.
ADE7753
Rev. C | Page 11 of 60
TYPICAL PERFORMANCE CHARACTERISTICS FULL-SCALE CURRENT (%)ERROR (%)0.1–0.5–0.1–0.2–0.3–0.40.20.10.50.40.3011010002875-0-006+85°C, PF = 0.5+25°C, PF = 0.5GAIN = 1INTEGRATOR OFFINTERNAL REFERENCE+25°C, PF = 1–40°C, PF = 0.5
Figure 6. Active Energy Error as a Percentage of Reading (Gain = 1) over Power Factor with Internal Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.4–0.2–0.1–0.30.10.40.30.2011010002875-0-008+25°C, PF = 1GAIN = 8INTEGRATOR OFFINTERNAL REFERENCE–40°C, PF = 1+85°C, PF = 1
Figure 7. Active Energy as a Percentage of Reading (Gain = 8) over Temperature with Internal Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.6–0.2–0.40.20.80.60.4011010002875-0-009+85°C, PF = 0.5GAIN = 8INTEGRATOR OFFINTERNAL REFERENCE–40°C, PF = 0.5+25°C, PF = 1+25°C, PF = 0.5
Figure 8. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.3–0.1–0.20.10.30.20110100GAIN = 8INTEGRATOR OFFEXTERNAL REFERENCE+85°C, PF = 102875-0-010–40°C, PF = 1+25°C, PF = 1
Figure 9. Active Energy Error as a Percentage of Reading (Gain = 8) over Temperature with External Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.6–0.2–0.40.20.60.40110100GAIN = 8INTEGRATOR OFFEXTERNAL REFERENCE+85°C, PF = 0.502875-0-011–40°C, PF = 0.5+25°C, PF = 0.5+25°C, PF = 1
Figure 10. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with External Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.5–0.1–0.2–0.3–0.40.20.10.50.40.3011010002875-0-012+85°C, PF = 0.5+25°C, PF = 0.5GAIN = 1INTEGRATOR OFFINTERNAL REFERENCE+25°C, PF = 0–40°C, PF = 0.5
Figure 11. Reactive Energy Error as a Percentage of Reading (Gain = 1) over Power Factor with Internal Reference and Integrator Off
ADE7753
Rev. C | Page 12 of 60
FULL-SCALE CURRENT (%)ERROR (%)0.1–0.5–0.1–0.2–0.3–0.40.20.10.50.40.3011010002875-0-013+85°C, PF = 0.5+25°C, PF = 0.5GAIN = 1INTEGRATOR OFFEXTERNAL REFERENCE+25°C, PF = 0–40°C, PF = 0.5
Figure 12. Reactive Energy Error as a Percentage of Reading (Gain = 1) over Power Factor with External Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.20–0.10–0.05–0.150.050.200.150.10011010002875-0-014+85°C, PF = 0GAIN = 8INTEGRATOR OFFINTERNAL REFERENCE–40°C, PF = 0+25°C, PF = 0
Figure 13. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Temperature with Internal Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.3–0.1–0.20.10.30.20110100GAIN = 8INTEGRATOR OFFINTERNAL REFERENCE02875-0-015+25°C, PF = 0.5+25°C, PF = 0–40°C, PF = 0.5+85°C, PF = 0.5
Figure 14. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.35–0.15–0.05–0.250.050.350.250.15110100GAIN = 8INTEGRATOR OFFEXTERNAL REFERENCE02875-0-016–40°C, PF = 0+85°C, PF = 0+25°C, PF = 0
Figure 15. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Temperature with External Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.5–0.1–0.2–0.3–0.40.20.10.50.40.3011010002875-0-017GAIN = 8INTEGRATOR OFFEXTERNAL REFERENCE+25°C, PF = 0+85°C, PF = 0.5–40°C, PF = 0.5+25°C, PF = 0.5
Figure 16. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with External Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.3–0.1–0.20.10.30.20110100GAIN = 8INTEGRATOR OFFINTERNAL REFERENCE5.25V02875-0-0184.75V5.0V
Figure 17. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Supply with Internal Reference and Integrator Off
ADE7753
Rev. C | Page 13 of 60
LINE FREQUENCY (Hz)ERROR (%)45–0.1–0.2–0.4–0.6–0.80.40.20.10.80.605055606502875-0-019PF = 0.5GAIN = 8INTEGRATOR OFFEXTERNAL REFERENCEPF = 1
Figure 18. Active Energy Error as a Percentage of Reading (Gain = 8) over Frequency with External Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.5–0.1–0.2–0.3–0.40.20.10.50.40.3011010002875-0-020GAIN = 8INTEGRATOR OFFINTERNAL REFERENCEPF = 1PF = 0.5
Figure 19. IRMS Error as a Percentage of Reading (Gain = 8) with Internal Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–1.0–0.2–0.4–0.6–0.80.40.21.00.80.6011010002875-0-022GAIN = 8INTEGRATOR ONINTERNAL REFERENCE+25°C, PF = 0.5–40°C, PF = 0.5+85°C, PF = 0.5+25°C, PF = 1
Figure 20. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator On FULL-SCALE CURRENT (%)ERROR (%)0.1–1.0–0.2–0.4–0.6–0.80.40.21.00.80.6011010002875-0-023GAIN = 8INTEGRATOR ONINTERNAL REFERENCE–40°C, PF = 185°C, PF = 125°C, PF = 1
Figure 21. Active Energy Error as a Percentage of Reading (Gain = 8) over Temperature with Internal Reference and Integrator On FULL-SCALE CURRENT (%)ERROR (%)0.1–1.0–0.2–0.4–0.6–0.80.40.21.00.80.6011010002875-0-024GAIN = 8INTEGRATOR ONINTERNAL REFERENCE+85°C, PF = 0.5–40°C, PF = 0.5+25°C, PF = 0.5+25°C, PF = 0
Figure 22. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator On FULL-SCALE CURRENT (%)ERROR (%)0.1–1.0–0.2–0.4–0.6–0.80.40.21.00.80.6011010002875-0-025GAIN = 8INTEGRATOR ONINTERNAL REFERENCE+85°C, PF = 0–40°C, PF = 0+25°C, PF = 0
Figure 23. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Temperature with Internal Reference and Integrator On
ADE7753
Rev. C | Page 14 of 60
02875-0-026–2.0–1.5–1.0–0.500.51.01.52.02.53.0ERROR (%)4547495153555759616365FREQUENCY (Hz)GAIN = 8INTEGRATOR ONINTERNAL REFERENCEPF = 0.5PF = 1
Figure 24. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator On FULL-SCALE CURRENT (%)ERROR (%)0.1–0.3–0.1–0.20.10.30.20110100GAIN = 8INTEGRATOR ONINTERNAL REFERENCE5.25V02875-0-0274.75V5.0V
Figure 25. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Supply with Internal Reference and Integrator On FULL-SCALE CURRENT (%)ERROR (%)0.1–0.5–0.1–0.2–0.3–0.40.20.10.50.40.3011010002875-0-028GAIN = 8INTEGRATOR ONINTERNAL REFERENCEPF = 1PF = 0.5
Figure 26. IRMS Error as a Percentage of Reading (Gain = 8) with Internal Reference and Integrator On FULL-SCALE VOLTAGEERROR (%)1–0.2–0.4–0.6–0.80.40.20.80.601010002875-0-029GAIN = 1EXTERNAL REFERENCE
Figure 27. VRMS Error as a Percentage of Reading (Gain = 1) with External Reference
02875-0-087CH1 OFFSET (0p5V_1X) (mV)HITS–15–12–9–6–303642068
Figure 28. Channel 1 Offset (Gain = 1)
ADE7753
Rev. C | Page 15 of 60
VDD10μF10μF10μF100nF100nFAVDDDVDDRESETDINDOUTSCLKCSCLKOUTCLKINIRQSAGZXCFAGNDDGNDV1PV1NV2NV2PREFIN/OUTU1ADE7753TOSPIBUS(USEDONLYFORCALIBRATION)22pF22pFY13.58MHzNOT CONNECTEDU3PS2501-1Idi/dt CURRENTSENSOR100Ω1kΩ33nF33nF100Ω1kΩ33nF33nF1kΩ33nF600kΩ110V1kΩ33nF100nFCHANNEL 1 GAIN = 8CHANNEL 2 GAIN = 1TOFREQUENCYCOUNTER02875-A-012
Figure 29. Test Circuit for Performance Curves with Integrator On CT TURN RATIO = 1800:1CHANNEL 2 GAIN = 1RB10Ω1.21ΩGAIN 1 (CH1)18NOT CONNECTEDVDD10μF1μF100nF100nFDINDOUTSCLKCSCLKOUTCLKINIRQSAGZXCFAGNDDGNDV1PV1NV2NV2PREFIN/OUTU1ADE7753TOSPIBUS(USEDONLYFORCALIBRATION)22pF22pFY13.58MHzU3PS2501-1ICURRENTTRANSFORMER1kΩ33nF1kΩ33nF1kΩ33nF600kΩ RB110V1kΩ33nF10μF100nFTOFREQUENCYCOUNTER02875-0-030AVDDDVDDRESET
Figure 30. Test Circuit for Performance Curves with Integrator Off
ADE7753
Rev. C | Page 16 of 60
THEORY OF OPERATION
ANALOG INPUTS
The ADE7753 has two fully differential voltage input channels.
The maximum differential input voltage for input pairs V1P/V1N
and V2P/V2N is ±0.5 V. In addition, the maximum signal level
on analog inputs for V1P/V1N and V2P/ V2N is ±0.5 V with respect to AGND. Each analog input channel has a programmable gain amplifier
(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The
gain selections are made by writing to the gain register—see Figure 32. Bits 0 to 2 select the gain for the PGA in Channel 1, and the gain selection for the PGA in Channel 2 is made via
Bits 5 to 7. Figure 31 shows how a gain selection for Channel 1
is made using the gain register. V1P
V1N
VIN K × VIN
+
GAIN[7:0]
7 6 543210
0 0 000000
7 6543210
0 0000000
GAIN (K)
SELECTION
OFFSET ADJUST
(±50mV)
CH1OS[7:0]
BITS 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION
BIT 6: NOT USED
BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT OFF)
02875-0-031
Figure 31. PGA in Channel 1
In addition to the PGA, Channel 1 also has a full-scale input
range selection for the ADC. The ADC analog input range
selection is also made using the gain register—see Figure 32. As mentioned previously, the maximum differential input voltage
is 0.5 V. However, by using Bits 3 and 4 in the gain register, the
maximum ADC input voltage can be set to 0.5 V, 0.25 V, or 0.125 V. This is achieved by adjusting the ADC reference—see
the ADE7753 Reference Circuit section. Table 5 summarizes the
maximum differential input signal level on Channel 1 for the
various ADC range and gain selections. Table 5. Maximum Input Signal Levels for Channel 1 Max Signal ADC Input Range Selection Channel 1 0.5 V 0.25 V 0.125 V 0.5 V Gain = 1 − −
0.25 V Gain = 2 Gain = 1 −
0.125 V Gain = 4 Gain = 2 Gain = 1 0.0625 V Gain = 8 Gain = 4 Gain = 2 0.0313 V Gain = 16 Gain = 8 Gain = 4 0.0156 V − Gain = 16 Gain = 8 0.00781 V − − Gain = 16 GAIN REGISTER*
CHANNEL 1 AND CHANNEL 2 PGA CONTROL
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 ADDR:
0x0F
*REGISTER CONTENTS
SHOW POWER-ON DEFAULTS
PGA 2 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
PGA 1 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
CHANNEL 1 FULL-SCALE SELECT
00 = 0.5V
01 = 0.25V
10 = 0.125V 02875-0-032
Figure 32. ADE7753 Analog Gain Register It is also possible to adjust offset errors on Channel 1 and
Channel 2 by writing to the offset correction registers, CH1OS
and CH2OS, respectively. These registers allow channel offsets in the range ±20 mV to ±50 mV (depending on the gain setting)
to be removed. Channel 1 and 2 offset registers are sign magni-
tude coded. A negative number is applied to the Channel 1
offset register, CH1OS, for a negative offset adjustment. Note that the Channel 2 offset register is inverted. A negative number is applied to CH2OS for a positive offset adjustment. It is not
necessary to perform an offset correction in an energy measure-
ment application if HPF in Channel 1 is switched on. Figure 33 shows the effect of offsets on the real power calculation. As seen from Figure 33, an offset on Channel 1 and Channel 2 contributes a dc component after multiplication. Because this dc component is extracted by LPF2 to generate the active (real) power information, the offsets contribute an error to the active power calculation. This problem is easily avoided by enabling HPF in Channel 1. By removing the offset from at least one
channel, no error component is generated at dc by the
multiplication. Error terms at cos(ωt) are removed by LPF2 and
by integration of the active power signal in the active energy register (AENERGY[23:0]) —see the Energy Calculation section.
ADE7753
Rev. C | Page 17 of 60
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
FREQUENCY (RAD/S)
IOS × V
VOS × I
VOS × IOS
V × I
2
0 ω 2ω
02875-0-033
Figure 33. Effect of Channel Offsets on the Real Power Calculation The contents of the offset correction registers are 6-bit, sign and
magnitude coded. The weight of the LSB depends on the gain setting, i.e., 1, 2, 4, 8, or 16. Table 6 shows the correctable offset
span for each of the gain settings and the LSB weight (mV) for
the offset correction registers. The maximum value that can be written to the offset correction registers is ±31d—see Figure 34. Figure 34 shows the relationship between the offset correction register contents and the offset (mV) on the analog inputs for a
gain setting of 1. In order to perform an offset adjustment, the analog inputs should be first connected to AGND, and there
should be no signal on either Channel 1 or Channel 2. A read from Channel 1 or Channel 2 using the waveform register indicates the offset in the channel. This offset can be canceled by writing an equal and opposite offset value to the Channel 1
offset register, or an equal value to the Channel 2 offset register.
The offset correction can be confirmed by performing another read. Note when adjusting the offset of Channel 1, one should disable the digital integrator and the HPF. Table 6. Offset Correction Range—Channels 1 and 2 Gain Correctable Span LSB Size 1 ±50 mV 1.61 mV/LSB
2 ±37 mV 1.19 mV/LSB
4 ±30 mV 0.97 mV/LSB
8 ±26 mV 0.84 mV/LSB
16 ±24 mV 0.77 mV/LSB
CH1OS[5:0]
SIGN + 5 BITS
+50mV
OFFSET
ADJUST
0x3F
0x00
0x1F
–50mV 0mV
SIGN + 5 BITS
01,1111b
11,1111b
02875-0-034
Figure 34. Channel 1 Offset Correction Range (Gain = 1) The current and voltage rms offsets can be adjusted with the
IRMSOS and VRMSOS registers—see Channel 1 RMS Offset Compensation and Channel 2 RMS Offset Compensation
sections. di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR
A di/dt sensor detects changes in magnetic field caused by ac
current. Figure 35 shows the principle of a di/dt current sensor.
MAGNETIC FIELD CREATED BY CURRENT
(DIRECTLY PROPORTIONAL TO CURRENT)
+ EMF (ELECTROMOTIVE FORCE)
– INDUCED BY CHANGES IN
MAGNETIC FLUX DENSITY (di/dt)
02875-0-035
Figure 35. Principle of a di/dt Current Sensor The flux density of a magnetic field induced by a current is
directly proportional to the magnitude of the current. The
changes in the magnetic flux density passing through a
conductor loop generate an electromotive force (EMF) between the two ends of the loop. The EMF is a voltage signal, which is
proportional to the di/dt of the current. The voltage output
from the di/dt current sensor is determined by the mutual inductance between the current-carrying conductor and the di/dt sensor. The current signal needs to be recovered from the
di/dt signal before it can be used. An integrator is therefore
necessary to restore the signal to its original form. The ADE7753
has a built-in digital integrator to recover the current signal from the di/dt sensor. The digital integrator on Channel 1 is switched off by default when the ADE7753 is powered up.
Setting the MSB of CH1OS register turns on the integrator.
Figure 36 to Figure 39 show the magnitude and phase response of the digital integrator.
FREQUENCY (Hz)
10
GAIN (dB)
0
–10
–20
–30
–40
–50
102 103
02875-0-036
Figure 36. Combined Gain Response of the Digital Integrator and Phase Compensator
ADE7753
Rev. C | Page 18 of 60
FREQUENCY (Hz)10210302875-0-037FREQ–88.0PHASE (
Degrees)–88.5–89.0–89.5–90.0–90.5
Figure 37. Combined Phase Response of the Digital Integrator and Phase Compensator
FREQUENCY (Hz)–1.0–6.0407045GAIN (
dB)50556065–1.5–2.0–2.5–3.5–4.5–5.5–3.0–4.0–5.002875-0-038
Figure 38. Combined Gain Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
–89.75–89.80–89.85–89.90–89.95–90.00FREQUENCY (Hz)PHASE (Degrees)40457050556065–90.05–89.7002875-0-039
Figure 39. Combined Phase Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
Note that the integrator has a –20 dB/dec attenuation and an approximately –90° phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. The di/dt sensor has a 20 dB/dec gain associated with it. It also generates signifi-cant high frequency noise, therefore a more effective anti-aliasing filter is needed to avoid noise due to aliasing—see the Antialias Filter section.
When the digital integrator is switched off, the ADE7753 can be used directly with a conventional current sensor such as a current transformer (CT) or with a low resistance current shunt.
ZERO-CROSSING DETECTION
The ADE7753 has a zero-crossing detection circuit on Channel 2. This zero crossing is used to produce an external zero-crossing signal (ZX), and it is also used in the calibration mode—see the Calibrating an Energy Meter Based on the ADE7753 section. The zero-crossing signal is also used to initiate a temperature measurement on the ADE7753—see the Temperature Measurement section.
Figure 40 shows how the zero-crossing signal is generated from the output of LPF1. ×1,×2,×1,×8,×16ADC 2REFERENCE1LPF1f–3dB = 140Hz–63%TO+63%FSPGA2{GAIN [7:5]}V2PV2NV2ZEROCROSSZXTOMULTIPLIER2.32° @ 60Hz1.00.93ZXV2LPF102875-0-040
Figure 40. Zero-Crossing Detection on Channel 2
The ZX signal goes logic high on a positive-going zero crossing and logic low on a negative-going zero crossing on Channel 2. The zero-crossing signal ZX is generated from the output of LPF1. LPF1 has a single pole at 140 Hz (at CLKIN = 3.579545 MHz). As a result, there is a phase lag between the analog input signal V2 and the output of LPF1. The phase response of this filter is shown in the Channel 2 Sampling section. The phase lag response of LPF1 results in a time delay of approximately 1.14 ms (@ 60 Hz) between the zero crossing on the analog inputs of Channel 2 and the rising or falling edge of ZX.
The zero-crossing detection also drives the ZX flag in the interrupt status register. The ZX flag is set to Logic 0 on the rising and falling edge of the voltage waveform. It stays low until the status register is read with reset. An active low in the IRQ output also appears if the corresponding bit in the interrupt enable register is set to Logic 1.
ADE7753
Rev. C | Page 19 of 60
The flag in the interrupt status register as well as the IRQ output are reset to their default values when the interrupt status register with reset (RSTSTATUS) is read.
Zero-Crossing Timeout
The zero-crossing detection also has an associated timeout register, ZXTOUT. This unsigned, 12-bit register is decremented (1 LSB) every 128/CLKIN seconds. The register is reset to its user programmed full-scale value every time a zero crossing is detected on Channel 2. The default power on value in this register is 0xFFF. If the internal register decrements to 0 before a zero crossing is detected and the DISSAG bit in the mode register is Logic 0, the SAG pin goes active low. The absence of a zero crossing is also indicated on the IRQ pin if the ZXTO enable bit in the interrupt enable register is set to Logic 1. Irrespective of the enable bit setting, the ZXTO flag in the interrupt status register is always set when the internal ZXTOUT register is decremented to 0—see the section. ADE7753 Interrupts
The ZXOUT register can be written/read by the user and has an address of 1Dh—see the ADE7753 Serial Interface section. The resolution of the register is 128/CLKIN seconds per LSB. Thus the maximum delay for an interrupt is 0.15 second (128/CLKIN × 212).
Figure 41 shows the mechanism of the zero-crossing timeout detection when the line voltage stays at a fixed dc level for more than CLKIN/128 × ZXTOUT seconds. 12-BIT INTERNALREGISTER VALUEZXTOUTCHANNEL 2ZXTODETECTIONBIT02875-0-041
Figure 41. Zero-Crossing Timeout Detection
PERIOD MEASUREMENT
The ADE7753 also provides the period measurement of the line. The period register is an unsigned 16-bit register and is updated every period. The MSB of this register is always zero.
The resolution of this register is 2.2 μs/LSB when CLKIN = 3.579545 MHz, which represents 0.013% when the line fre-quency is 60 Hz. When the line frequency is 60 Hz, the value of the period register is approximately CLKIN/4/32/60 Hz × 16 = 7457d. The length of the register enables the measurement of line frequencies as low as 13.9 Hz.
The period register is stable at ±1 LSB when the line is established and the measurement does not change. A settling time of 1.8 seconds is associated with this filter before the measurement is stable.
POWER SUPPLY MONITOR
The ADE7753 also contains an on-chip power supply monitor. The analog supply (AVDD) is continuously monitored by the ADE7753. If the supply is less than 4 V ± 5%, then the ADE7753 goes into an inactive state, that is, no energy is accumulated when the supply voltage is below 4 V. This is useful to ensure correct device operation at power-up and during power-down. The power supply monitor has built-in hysteresis and filtering, which give a high degree of immunity to false triggering due to noisy supplies. AVDD5V4V0VADE7753POWER-ONINACTIVESTATESAGINACTIVEACTIVEINACTIVETIME02875-0-042
Figure 42. On-Chip Power Supply Monitor
As seen in Figure 42, the trigger level is nominally set at 4 V. The tolerance on this trigger level is about ±5%. The SAG pin can also be used as a power supply monitor input to the MCU. The SAG pin goes logic low when the ADE7753 is in its inactive state. The power supply and decoupling for the part should be such that the ripple at AVDD does not exceed 5 V ±5%, as specified for normal operation.
LINE VOLTAGE SAG DETECTION
In addition to the detection of the loss of the line voltage signal (zero crossing), the ADE7753 can also be programmed to detect when the absolute value of the line voltage drops below a certain peak value for a number of line cycles. This condition is illustrated in Figure 43.
ADE7753
Rev. C | Page 20 of 60
SAGCYC [7:0] =0x043 LINE CYCLESSAG RESET HIGHWHEN CHANNEL 2EXCEEDS SAGLVL [7:0]FULL SCALESAGLVL [7:0]SAGCHANNEL 202875-0-043
Figure 43. ADE7753 Sag Detection
Figure 43 shows the line voltage falling below a threshold that is set in the sag level register (SAGLVL[7:0]) for three line cycles. The quantities 0 and 1 are not valid for the SAGCYC register, and the contents represent one more than the desired number of full line cycles. For example, when the sag cycle (SAGCYC[7:0]) contains 0x04, the SAG pin goes active low at the end of the third line cycle for which the line voltage (Channel 2 signal) falls below the threshold, if the DISSAG bit in the mode register is Logic 0. As is the case when zero crossings are no longer detected, the sag event is also recorded by setting the SAG flag in the interrupt status register. If the SAG enable bit is set to Logic 1, the IRQ logic output goes active low—see the section. The ADE7753 InterruptsSAG pin goes logic high again when the absolute value of the signal on Channel 2 exceeds the sag level set in the sag level register. This is shown in when the Figure 43SAG pin goes high again during the fifth line cycle from the time when the signal on Channel 2 first dropped below the threshold level.
Sag Level Set
The contents of the sag level register (1 byte) are compared to the absolute value of the most significant byte output from LPF1 after it is shifted left by one bit, thus, for example, the nominal maximum code from LPF1 with a full-scale signal on Channel 2 is 0x2518—see the Channel 2 Sampling section. Shifting one bit left gives 0x4A30. Therefore writing 0x4A to the SAG level register puts the sag detection level at full scale. Writing 0x00 or 0x01 puts the sag detection level at 0. The SAG level register is compared to the most significant byte of a waveform sample after the shift left and detection is made when the contents of the sag level register are greater.
PEAK DETECTION
The ADE7753 can also be programmed to detect when the absolute value of the voltage or current channel exceeds a specified peak value. Figure 44 illustrates the behavior of the peak detection for the voltage channel. Both Channel 1 and Channel 2 are monitored at the same time.
PKV RESET LOWWHEN RSTSTATUSREGISTER IS READVPKLVL[7:0]V2READ RSTSTATUSREGISTERPKV INTERRUPTFLAG (BIT 8 OFSTATUS REGISTER)02875-0-088
Figure 44. ADE7753 Peak Level Detection
Figure 44 shows a line voltage exceeding a threshold that is set in the voltage peak register (VPKLVL[7:0]). The voltage peak event is recorded by setting the PKV flag in the interrupt status register. If the PKV enable bit is set to Logic 1 in the interrupt mask register, the IRQ logic output goes active low. Similarly, the current peak event is recorded by setting the PKI flag in the interrupt status register—see the section. ADE7753 Interrupts
Peak Level Set
The contents of the VPKLVL and IPKLVL registers are respectively compared to the absolute value of Channel 1 and Channel 2 after they are multiplied by 2. Thus, for example, the nominal maximum code from the Channel 1 ADC with a full-scale signal is 0x2851EC—see the Channel 1 Sampling section. Multiplying by 2 gives 0x50A3D8. Therefore, writing 0x50 to the IPKLVL register, for example, puts the Channel 1 peak detection level at full scale and sets the current peak detection to its least sensitive value. Writing 0x00 puts the Channel 1 detection level at 0. The detection is done by comparing the contents of the IPKLVL register to the incoming Channel 1 sample. The IRQ pin indicates that the peak level is exceeded if the PKI or PKV bits are set in the interrupt enable register (IRQEN[15:0]) at Address 0x0A.
Peak Level Record
The ADE7753 records the maximum absolute value reached by Channel 1 and Channel 2 in two different registers—IPEAK and VPEAK, respectively. VPEAK and IPEAK are 24-bit unsigned registers. These registers are updated each time the absolute value of the waveform sample from the corresponding channel is above the value stored in the VPEAK or IPEAK register. The contents of the VPEAK register correspond to 2× the maximum absolute value observed on the Channel 2 input. The contents of IPEAK represent the maximum absolute value observed on the Channel 1 input. Reading the RSTVPEAK and RSTIPEAK registers clears their respective contents after the read operation.
ADE7753
Rev. C | Page 21 of 60
Using the ADE7753 Interrupts with an MCU
ADE7753 INTERRUPTS
Figure 46 shows a timing diagram with a suggested implemen-tation of ADE7753 interrupt management using an MCU. At time t1, the IRQ line goes active low indicating that one or more interrupt events have occurred in the ADE7753. The IRQ logic output should be tied to a negative edge-triggered external interrupt on the MCU. On detection of the negative edge, the MCU should be configured to start executing its interrupt service routine (ISR). On entering the ISR, all interrupts should be disabled by using the global interrupt enable bit. At this point, the MCU external interrupt flag can be cleared to capture interrupt events that occur during the current ISR. When the MCU interrupt flag is cleared, a read from the status register with reset is carried out. This causes the IRQ line to be reset logic high (t2)—see the section. The status register contents are used to determine the source of the interrupt(s) and therefore the appropriate action to be taken. If a subsequent interrupt event occurs during the ISR, that event is recorded by the MCU external interrupt flag being set again (t3). On returning from the ISR, the global interrupt mask is cleared (same instruction cycle), and the external interrupt flag causes the MCU to jump to its ISR once a gain. This ensures that the MCU does not miss any external interrupts. Interrupt Timing
ADE7753 interrupts are managed through the interrupt status register (STATUS[15:0]) and the interrupt enable register (IRQEN[15:0]). When an interrupt event occurs in the ADE7753, the corresponding flag in the status register is set to Logic 1—see the Interrupt Status Register section. If the enable bit for this interrupt in the interrupt enable register is Logic 1, then the IRQ logic output goes active low. The flag bits in the status register are set irrespective of the state of the enable bits.
To determine the source of the interrupt, the system master (MCU) should perform a read from the status register with reset (RSTSTATUS[15:0]). This is achieved by carrying out a read from Address 0x0C. The IRQ output goes logic high on completion of the interrupt status register read command—see the section. When carrying out a read with reset, the ADE7753 is designed to ensure that no interrupt events are missed. If an interrupt event occurs just as the status register is being read, the event is not lost and the Interrupt TimingIRQ logic output is guaranteed to go high for the duration of the interrupt status register data transfer before going logic low again to indicate the pending interrupt. See the next section for a more detailed description. IRQGLOBALINTERRUPTMASK SETISR RETURNGLOBAL INTERRUPTMASK RESETCLEAR MCUINTERRUPTFLAGREADSTATUS WITHRESET (0x05)ISR ACTION(BASED ON STATUS CONTENTS)MCUINTERRUPTFLAG SETMCUPROGRAMSEQUENCE02875-0-044t1t2t3JUMPTOISRJUMPTOISR
Figure 45. ADE7753 Interrupt Management
SCLKDINDOUTIRQt11t11t9t1READ STATUS REGISTER COMMANDSTATUS REGISTER CONTENTSDB7DB7DB0CS00000101DB002875-0-045
Figure 46. ADE7753 Interrupt Timing
ADE7753
Rev. C | Page 22 of 60
Interrupt Timing
The ADE7753 Serial Interface section should be reviewed first before reviewing the interrupt timing. As previously described, when the IRQ output goes low, the MCU ISR must read the interrupt status register to determine the source of the interrupt. When reading the status register contents, the IRQ output is set high on the last falling edge of SCLK of the first byte transfer (read interrupt status register command). The IRQ output is held high until the last bit of the next 15-bit transfer is shifted out (interrupt status register contents)—see . If an interrupt is pending at this time, the Figure 45IRQ output goes low again. If no interrupt is pending, the IRQ output stays high.
TEMPERATURE MEASUREMENT
The ADE7753 also includes an on-chip temperature sensor. A temperature measurement can be made by setting Bit 5 in the mode register. When Bit 5 is set logic high in the mode register, the ADE7753 initiates a temperature measurement on the next zero crossing. When the zero crossing on Channel 2 is detected, the voltage output from the temperature sensing circuit is connected to ADC1 (Channel 1) for digitizing. The resulting code is processed and placed in the temperature register (TEMP[7:0]) approximately 26 μs later (96/CLKIN seconds). If enabled in the interrupt enable register (Bit 5), the IRQ output goes active low when the temperature conversion is finished.
The contents of the temperature register are signed (twos complement) with a resolution of approximately 1.5 LSB/°C. The temperature register produces a code of 0x00 when the ambient temperature is approximately −25°C. The temperature measurement is uncalibrated in the ADE7753 and has an offset tolerance as high as ±25°C.
ADE7753 ANALOG-TO-DIGITAL CONVERSION
The analog-to-digital conversion in the ADE7753 is carried out using two second-order Σ-Δ ADCs. For simplicity, the block diagram in Figure 47 shows a first-order Σ-Δ ADC. The converter is made up of the Σ-Δ modulator and the digital low-pass filter. 24DIGITALLOW-PASSFILTERRCANALOGLOW-PASS FILTER+–VREF1-BIT DACINTEGRATORMCLK/4LATCHEDCOMPARATOR.....10100101.....+–02875-0-046
Figure 47. First-Order Σ-Δ ADC
A Σ-Δ modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. In the ADE7753, the sampling clock is equal to CLKIN/4. The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is subtracted from the input signal. If the loop gain is high enough, the average value of the DAC out-put (and therefore the bit stream) can approach that of the input signal level. For any given input value in a single sampling interval, the data from the 1-bit ADC is virtually meaningless. Only when a large number of samples are averaged is a meaningful result obtained. This averaging is carried out in the second part of the ADC, the digital low-pass filter. By averaging a large number of bits from the modulator, the low-pass filter can produce 24-bit data-words that are proportional to the input signal level.
The Σ-Δ converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. The first is oversampling. Oversampling means that the signal is sampled at a rate (frequency), which is many times higher than the bandwidth of interest. For example, the sampling rate in the ADE7753 is CLKIN/4 (894 kHz) and the band of interest is 40 Hz to 2 kHz. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered—see Figure 48. However, oversampling alone is not efficient enough to improve the signal-to-noise ratio (SNR) in the band of interest. For example, an oversampling ratio of 4 is required just to increase the SNR by only 6 dB (1 bit). To keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. In the Σ-Δ modulator, the noise is shaped by the integrator, which has a high-pass-type response for the quantization noise. The result is that most of the noise is at the higher frequencies where it can be removed by the digital low-pass filter. This noise shaping is shown in Figure 48. 44708942NOISESIGNALDIGITALFILTERANTILALIASFILTER (RC)SAMPLINGFREQUENCYHIGH RESOLUTIONOUTPUT FROM DIGITALLPFSHAPEDNOISE44708942NOISESIGNALFREQUENCY (kHz)FREQUENCY (kHz)02875-0-047
Figure 48. Noise Reduction Due to Oversampling and Noise Shaping in the Analog Modulator
ADE7753
Rev. C | Page 23 of 60
Antialias Filter
ADE7753 Reference Circuit
Figure 50 shows a simplified version of the reference output circuitry. The nominal reference voltage at the REFIN/OUT pin is 2.42 V. This is the reference voltage used for the ADCs in the ADE7753. However, Channel 1 has three input range selections that are selected by dividing down the reference value used for the ADC in Channel 1. The reference value used for Channel 1 is divided down to ½ and ¼ of the nominal value by using an internal resistor divider, as shown in Figure 50.
Figure 47 also shows an analog low-pass filter (RC) on the input to the modulator. This filter is present to prevent aliasing. Aliasing is an artifact of all sampled systems. Aliasing means that frequency components in the input signal to the ADC, which are higher than half the sampling rate of the ADC, appear in the sampled signal at a frequency below half the sampling rate. Figure 49 illustrates the effect. Frequency components (arrows shown in black) above half the sampling frequency (also know as the Nyquist frequency, i.e., 447 kHz) are imaged or folded back down below 447 kHz. This happens with all ADCs regardless of the architecture. In the example shown, only frequencies near the sampling frequency, i.e., 894 kHz, move into the band of interest for metering, i.e., 40 Hz to 2 kHz. This allows the use of a very simple LPF (low-pass filter) to attenuate high frequency (near 900 kHz) noise, and prevents distortion in the band of interest. For conventional current sensors, a simple RC filter (single-pole LPF) with a corner frequency of 10 kHz produces an attenuation of approximately 40 dB at 894 kHz—see Figure 49. The 20 dB per decade attenuation is usually sufficient to eliminate the effects of aliasing for conventional current sensors. However, for a di/dt sensor such as a Rogowski coil, the sensor has a 20 dB per decade gain. This neutralizes the –20 dB per decade attenuation produced by one simple LPF. Therefore, when using a di/dt sensor, care should be taken to offset the 20 dB per decade gain. One simple approach is to cascade two RC filters to produce the –40 dB per decade attenuation needed. 60μAPTAT2.5V1.7kΩ12.5kΩ12.5kΩ12.5kΩ12.5kΩREFIN/OUT2.42VMAXIMUMLOAD = 10μAOUTPUTIMPEDANCE6kΩREFERENCE INPUTTO ADC CHANNEL 1(RANGE SELECT)2.42V, 1.21V, 0.6V02875-0-049
Figure 50. ADE7753 Reference Circuit Output
The REFIN/OUT pin can be overdriven by an external source, for example, an external 2.5 V reference. Note that the nominal reference value supplied to the ADCs is now 2.5 V, not 2.42 V, which has the effect of increasing the nominal analog input signal range by 2.5/2.42 × 100% = 3% or from 0.5 V to 0.5165 V. SAMPLINGFREQUENCYIMAGEFREQUENCIESALIASING EFFECTS02447894FREQUENCY (kHz)02875-0-048
The voltage of the ADE7753 reference drifts slightly with temperature—see the ADE7753 Specifications for the temperature coefficient specification (in ppm/°C). The value of the temperature drift varies from part to part. Since the reference is used for the ADCs in both Channels 1 and 2, any x% drift in the reference results in 2×% deviation of the meter accuracy. The reference drift resulting from temperature changes is usually very small and it is typically much smaller than the drift of other components on a meter. However, if guaranteed temperature performance is needed, one needs to use an external voltage reference. Alternatively, the meter can be calibrated at multiple temperatures. Real-time compensation can be achieved easily by using the on-chip temperature sensor.
Figure 49. ADC and Signal Processing in Channel 1 Outline Dimensions
ADC Transfer Function
The following expression relates the output of the LPF in the Σ-Δ ADC to the analog input signal level. Both ADCs in the ADE7753 are designed to produce the same output code for the same input signal level.
CHANNEL 1 ADC 144,2620492.3)(××=OUTINVVADCCode (1)
Figure 51 shows the ADC and signal processing chain for Channel 1. In waveform sampling mode, the ADC outputs a signed twos complement 24-bit data-word at a maximum of 27.9 kSPS (CLKIN/128). With the specified full-scale analog input signal of 0.5 V (or 0.25 V or 0.125 V—see the Analog Inputs section) the ADC produces an output code that is approximately between 0x2851EC (+2,642,412d) and 0xD7AE14 (–2,642,412d)—see Figure 51.
Therefore with a full-scale signal on the input of 0.5 V and an internal reference of 2.42 V, the ADC output code is nominally 165,151 or 2851Fh. The maximum code from the ADC is ±262,144; this is equivalent to an input signal level of ±0.794 V. However, for specified performance, it is recommended that the full-scale input signal level of 0.5 V not be exceeded.
ADE7753
Rev. C | Page 24 of 60
⋅1,⋅2,⋅4,⋅8,⋅16ANALOGINPUTRANGEDIGITALINTEGRATOR*dtHPFADC 1REFERENCE2.42V, 1.21V, 0.6VV10V0.5V, 0.25V,0.125V, 62.5mV,31.3mV, 15.6mV,CHANNEL 1(CURRENT WAVEFORM)DATA RANGEACTIVE AND REACTIVEPOWER CALCULATIONWAVEFORM SAMPLEREGISTERCURRENT RMS (IRMS)CALCULATION50HzV1PV1NPGA1V1{GAIN[4:3]}{GAIN[2:0]}*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATEDDEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A –20dB/DECADEFREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT WILL NOT BE FURTHER ATTENUATED.ADC OUTPUTWORD RANGE0xD7AE140x000000x2851EC0xD7AE140x0000000x2851ECCHANNEL 1(CURRENT WAVEFORM)DATA RANGE AFTERINTEGRATOR (50Hz)0xEI08C40x0000000x1EF73C60HzCHANNEL 1(CURRENT WAVEFORM)DATA RANGE AFTERINTEGRATOR (60Hz)0xE631F80x0000000x19CE0802875-0-052
Figure 51. ADC and Signal Processing in Channel 1
Channel 1 Sampling
The waveform samples can also be routed to the waveform register (MODE[14:13] = 1,0) to be read by the system master (MCU). In waveform sampling mode, the WSMP bit (Bit 3) in the interrupt enable register must also be set to Logic 1. The active, apparent power, and energy calculation remain uninterrupted during waveform sampling.
When in waveform sampling mode, one of four output sample rates can be chosen by using Bits 11 and 12 of the mode register (WAVSEL1,0). The output sample rate can be 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS—see the Mode Register (0x09) section. The interrupt request output, IRQ, signals a new sample availability by going active low. The timing is shown in . The 24-bit waveform samples are transferred from the ADE7753 one byte (eight bits) at a time, with the most significant byte shifted out first. The 24-bit data-word is right justified—see the section. The interrupt request output Figure 52ADE7753 Serial InterfaceIRQ stays low until the interrupt routine reads the reset status register—see the section. ADE7753 Interrupts
CHANNEL 1 DATA(24 BITS)READ FROM WAVEFORMSIGN0IRQSCLKDINDOUT0001 HEX02875-0-050
Figure 52. Waveform Sampling Channel 1
Channel 1 RMS Calculation
Root mean square (rms) value of a continuous signal V(t) is defined as
VRMS = ∫×=TrmsdttVTV02)(1 (2)
For time sampling signals, rms calculation involves squaring the signal, taking the average and obtaining the square root:
VRMS = Σ=×=NirmsiVNV12)(1 (3)
The ADE7753 simultaneously calculates the rms values for Channel 1 and Channel 2 in different registers. Figure 53 shows the detail of the signal processing chain for the rms calculation on Channel 1. The Channel 1 rms value is processed from the samples used in the Channel 1 waveform sampling mode. The Channel 1 rms value is stored in an unsigned 24-bit register (IRMS). One LSB of the Channel 1 rms register is equivalent to one LSB of a Channel 1 waveform sample. The update rate of the Channel 1 rms measurement is CLKIN/4.
ADE7753
Rev. C | Page 25 of 60
IRMS(t)LPF3HPF1CHANNEL 10x1C82B30x00+IRMSOS[11:0]IRMSCURRENT SIGNAL (i(t))226225sgn22721721621502875-0-00510x2851EC0x000xD7AE142424
Figure 53. Channel 1 RMS Signal Processing
With the specified full-scale analog input signal of 0.5 V, the ADC produces an output code that is approximately ±2,642,412d—see the Channel 1 ADC section. The equivalent rms value of a full-scale ac signal are 1,868,467d (0x1C82B3). The current rms measurement provided in the ADE7753 is accurate to within 0.5% for signal input between full scale and full scale/100. Table 7 shows the settling time for the IRMS measurement, which is the time it takes for the rms register to reflect the value at the input to the current channel. The conversion from the register value to amps must be done externally in the microprocessor using an amps/LSB constant. To minimize noise, synchronize the reading of the rms register with the zero crossing of the voltage input and take the average of a number of readings.
Table 7.
95%
100%
Integrator Off
219 ms
895 ms
Integrator On
78.5 ms
1340 ms
Channel 1 RMS Offset Compensation
The ADE7753 incorporates a Channel 1 rms offset compensa-tion register (IRMSOS). This is a 12-bit signed register that can be used to remove offset in the Channel 1 rms calculation. An offset could exist in the rms calculation due to input noises that are integrated in the dc component of V2(t). The offset calibration allows the content of the IRMS register to match the theoretical value even when the Channel 1 input is low.
One LSB of the Channel 1 rms offset is equivalent to 32,768 LSB of the square of the Channel 1 rms register. Assuming that the maximum value from the Channel 1 rms calculation is 1,868,467d with full-scale ac inputs, then 1 LSB of the Channel 1 rms offset represents 0.46% of measurement error at –60 dB down of full scale.
IRMS = 3276820×+IRMSOSIRMS (4)
where IRMS0 is the rms measurement without offset correction. To measure the offset of the rms measurement, two data points are needed from non-zero input values, for example, the base current, Ib, and Imax/100. The offset can be calculated from these measurements.
CHANNEL 2 ADC
Channel 2 Sampling
In Channel 2 waveform sampling mode (MODE[14:13] = 1,1 and WSMP = 1), the ADC output code scaling for Channel 2 is not the same as Channel 1. The Channel 2 waveform sample is a 16-bit word and sign extended to 24 bits. For normal operation, the differential voltage signal between V2P and V2N should not exceed 0.5 V. With maximum voltage input (±0.5 V at PGA gain of 1), the output from the ADC swings between 0x2852 and 0xD7AE (±10,322d). However, before being passed to the wave-form register, the ADC output is passed through a single-pole, low-pass filter with a cutoff frequency of 140 Hz. The plots in Figure 54 show the magnitude and phase response of this filter. FREQUENCY (Hz)0101102103PHASE (
Degrees)–20–10–40–50–60–30–70–80–900–18GAIN (
dB)60Hz,–0.73dB50Hz,–0.52dB60Hz,–23.2°50Hz,–19.7°–8–10–14–12–16–2–4–602875-0-053
Figure 54. Magnitude and Phase Response of LPF1
The LPF1 has the effect of attenuating the signal. For example, if the line frequency is 60 Hz, then the signal at the output of LPF1 is attenuated by about 8%. dBHzHzfH73.0919.01406011)(2−==⎟⎟⎠⎞⎜⎜⎝⎛+= (5)
Note LPF1 does not affect the active power calculation. The signal processing chain in Channel 2 is illustrated in Figure 55.
ADE7753
Rev. C | Page 26 of 60
V1ADC 20VANALOGINPUT RANGE0.5V, 0.25, 0.125,62.5mV, 31.25mVREFERENCELPF1ACTIVEANDREACTIVEENERGYCALCULATIONVRMSCALCULATIONANDWAVEFORMSAMPLING(PEAK/SAG/ZX)PGA2×1,×2,×4,×8,×16{GAIN [7:5]}V2PV2NV22.42V0x28520x25810xDAE80xD7AE0x0000LPF OUTPUTWORD RANGE02875-0-054
Figure 55. ADC and Signal Processing in Channel 2
VRMS[23:0]LPF3|x|LPF1CHANNEL 20x17D3380x00++VRMOS[11:0]VOLTAGE SIGNAL (V(t))29sgn2822212002875-0-00550x25180x00xDAE8
Figure 56. Channel 2 RMS Signal Processing
Channel 2 has only one analog input range (0.5 V differential). Like Channel 1, Channel 2 has a PGA with gain selections of 1, 2, 4, 8, and 16. For energy measurement, the output of the ADC is passed directly to the multiplier and is not filtered. An HPF is not required to remove any dc offset since it is only required to remove the offset from one channel to eliminate errors due to offsets in the power calculation. When in waveform sampling mode, one of four output sample rates can be chosen by using Bits 11 and 12 of the mode register. The available output sample rates are 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS—see the Mode Register (0x09) section. The interrupt request output IRQ signals that a sample is available by going active low. The timing is the same as that for Channel 1, as shown in . Figure 52
Channel 2 RMS Calculation
Figure 56 shows the details of the signal processing chain for the rms estimation on Channel 2. This Channel 2 rms estimation is done in the ADE7753 using the mean absolute value calculation, as shown in Figure 56. The Channel 2 rms value is processed from the samples used in the Channel 2 waveform sampling mode. The rms value is slightly attenuated because of LPF1. Channel 2 rms value is stored in the unsigned 24-bit VRMS register. The update rate of the Channel 2 rms measurement is CLKIN/4.
With the specified full-scale ac analog input signal of 0.5 V, the output from the LPF1 swings between 0x2518 and 0xDAE8 at 60 Hz—see the Channel 2 ADC section. The equivalent rms value of this full-scale ac signal is approximately 1,561,400 (0x17D338) in the VRMS register. The voltage rms measure-ment provided in the ADE7753 is accurate to within ±0.5% for signal input between full scale and full scale/20. Table 8 shows the settling time for the VRMS measurement, which is the time it takes for the rms register to reflect the value at the input to the voltage channel. The conversion from the register value to volts must be done externally in the microprocessor using a volts/LSB constant. Since the low-pass filtering used for calculating the rms value is imperfect, there is some ripple noise from 2ω term present in the rms measurement. To minimize the noise effect in the reading, synchronize the rms reading with the zero crossings of the voltage input.
Table 8.
95%
100%
220 ms
670 ms
Channel 2 RMS Offset Compensation
The ADE7753 incorporates a Channel 2 rms offset compensation register (VRMSOS). This is a 12-bit signed register that can be used to remove offset in the Channel 2 rms calculation. An offset could exist in the rms calculation due to input noises and dc offset in the input samples. The offset calibration allows the contents of the VRMS register to be maintained at 0 when no voltage is applied. One LSB of the Channel 2 rms offset is equivalent to one LSB of the rms register. Assuming that the maximum value from the Channel 2 rms calculation is 1,561,400d with full-scale ac inputs, then one LSB of the Channel 2 rms offset represents 0.064% of measurement error at –60 dB down of full scale.
VRMS = VRMS0 + VRMSOS (6)
where VRMS0 is the rms measurement without offset correction. The voltage rms offset compensation should be done by testing the rms results at two non-zero input levels. One measurement can be done close to full scale and the other at approximately full scale/10. The voltage offset compensation can be derived
ADE7753
Rev. C | Page 27 of 60
from these measurements. If the voltage rms offset register does not have enough range, the CH2OS register can also be used.
PHASE COMPENSATION
When the HPF is disabled, the phase error between Channel 1 and Channel 2 is 0 from dc to 3.5 kHz. When HPF is enabled, Channel 1 has the phase response illustrated in Figure 58 and Figure 59. Also shown in Figure 60 is the magnitude response of the filter. As can be seen from the plots, the phase response is almost 0 from 45 Hz to 1 kHz. This is all that is required in typical energy measurement applications. However, despite being internally phase compensated, the ADE7753 must work with transducers, which could have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to part, and they must be corrected in order to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7753 provides a means of digitally calibrating these small phase errors. The ADE7753 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for small phase errors. Because the compensation is in time, this technique should be used only for small phase errors in the range of 0.1° to 0.5°. Correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics.
The phase calibration register (PHCAL[5:0]) is a twos comple-ment signed single-byte register that has values ranging from 0x21 (–31d) to 0x1F (31d).
The register is centered at 0x0D, so that writing 0x0D to the register gives 0 delay. By changing the PHCAL register, the time delay in the Channel 2 signal path can change from –102.12 μs to +39.96 μs (CLKIN = 3.579545 MHz). One LSB is equivalent to 2.22 μs (CLKIN/8) time delay or advance. A line frequency of 60 Hz gives a phase resolution of 0.048° at the fundamental (i.e., 360° × 2.22 μs × 60 Hz). Figure 57 illustrates how the phase compensation is used to remove a 0.1° phase lead in Channel 1 due to the external transducer. To cancel the lead (0.1°) in Channel 1, a phase lead must also be introduced into Channel 2. The resolution of the phase adjustment allows the introduction of a phase lead in increment of 0.048°. The phase lead is achieved by introducing a time advance into Channel 2. A time advance of 4.48 μs is made by writing −2 (0x0B) to the time delay block, thus reducing the amount of time delay by 4.48 μs, or equiva-lently, a phase lead of approximately 0.1° at line frequency of 60 Hz. 0x0B represents –2 because the register is centered with 0 at 0x0D. 110100150PGA1V1PV1NV1ADC 1HPF24PGA2V2PV2NV2ADC 2DELAY BLOCK2.24μs/LSB24LPF2V2V160Hz0.1°V1V2CHANNEL 2 DELAYREDUCED BY 4.48μs(0.1°LEAD AT 60Hz)0Bh IN PHCAL [5.0]PHCAL [5:0]--100μs TO +34μs60Hz02875-0-056
Figure 57. Phase Calibration
FREQUENCY (Hz)PHASE (Degrees)0.90.80.70.60.50.40.30.20.10–0.110210310402875-0-057
Figure 58. Combined Phase Response of the HPF and Phase Compensation (10 Hz to 1 kHz)
FREQUENCY (Hz)0.2040PHASE (
Degrees)0.180.160.140.120.100.0800.020.040.0645505560657002875-0-058
Figure 59. Combined Phase Response of the HPF and Phase Compensation (40 Hz to 70 Hz)
ADE7753
Rev. C | Page 28 of 60
FREQUENCY (Hz)0.4ERROR (%)545658606264660.30.20.10.0–0.1–0.2–0.3–0.402875-0-059
Figure 60. Combined Gain Response of the HPF and Phase Compensation
ACTIVE POWER CALCULATION
Power is defined as the rate of energy flow from source to load. It is defined as the product of the voltage and current wave-forms. The resulting waveform is called the instantaneous power signal and is equal to the rate of energy flow at every instant of time. The unit of power is the watt or joules/sec. Equation 9 gives an expression for the instantaneous power signal in an ac system.
v(t) = )sin(2tVω× (7)
i(t) = )sin(2tIω× (8)
where: V is the rms voltage. I is the rms current.
)()()(titvtp×=
)2cos()(tVIVItpω−= (9)
The average power over an integral number of line cycles (n) is given by the expression in Equation 10.
P = ∫=nTVIdttpnT0)(1 (10)
where: T is the line cycle period. P is referred to as the active or real power.
Note that the active power is equal to the dc component of the instantaneous power signal p(t) in Equation 8, i.e., VI. This is the relationship used to calculate active power in the ADE7753. The instantaneous power signal p(t) is generated by multiplying the current and voltage signals. The dc component of the instantaneous power signal is then extracted by LPF2 (low-pass filter) to obtain the active power information. This process is illustrated in Figure 61. INSTANTANEOUSPOWER SIGNALp(t) = v×i-v×i×cos(2ωt)ACTIVEREALPOWERSIGNAL=v×i0x19999AVI0xCCCCD0x00000CURRENTi(t) = 2×i×sin(ωt)VOLTAGEv(t) = 2×v×sin(ωt)02875-0-060
Figure 61. Active Power Calculation
Since LPF2 does not have an ideal “brick wall” frequency response—see Figure 62, the active power signal has some ripple due to the instantaneous power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Because the ripple is sinusoidal in nature, it is removed when the active power signal is integrated to calculate energy—see the Energy Calculation section. FREQUENCY (Hz)–241dB–2031030100–12–16–8–4002875-0-061
Figure 62. Frequency Response of LPF2
ADE7753
Rev. C | Page 29 of 60
APOS[15:0]WGAIN[11:0]WDIV[7:0]LPF2CURRENTCHANNELVOLTAGECHANNELOUTPUT LPF2TIME (nT)4CLKINTACTIVEPOWERSIGNAL++AENERGY [23:0]OUTPUTSFROMTHELPF2AREACCUMULATED(INTEGRATED)INTHEINTERNALACTIVEENERGYREGISTERUPPER24BITSAREACCESSIBLETHROUGHAENERGY[23:0]REGISTER230480WAVEFORMREGISTERVALUES02875-0-063%
Figure 63. ADE7753 Active Energy Calculation
Figure 63 shows the signal processing chain for the active power calculation in the ADE7753. As explained, the active power is calculated by low-pass filtering the instantaneous power signal. Note that when reading the waveform samples from the output of LPF2, the gain of the active energy can be adjusted by using the multiplier and watt gain register (WGAIN[11:0]). The gain is adjusted by writing a twos complement 12-bit word to the watt gain register. Equation 11 shows how the gain adjustment is related to the contents of the watt gain register: ⎟⎟⎠⎞⎜⎜⎝⎛⎭⎬⎫⎩⎨⎧+×=1221WGAINPowerActiveWGAINOutput (11)
For example, when 0x7FF is written to the watt gain register, the power output is scaled up by 50%. 0x7FF = 2047d, 2047/212 = 0.5. Similarly, 0x800 = –2048d (signed twos complement) and power output is scaled by –50%. Each LSB scales the power output by 0.0244%. Figure 64 shows the maximum code (in hex) output range for the active power signal (LPF2). Note that the output range changes depending on the contents of the watt gain register. The minimum output range is given when the watt gain register contents are equal to 0x800, and the maximum range is given by writing 0x7FF to the watt gain register. This can be used to calibrate the active power (or energy) calculation in the ADE7753. 0x1333330xCCCCD0x666660xF9999A0xF333330xECCCCD0x00000ACTIVE POWER OUTPUTPOSITIVEPOWERNEGATIVEPOWER0x0000x7FF0x800{WGAIN[11:0]}ACTIVE POWERCALIBRATION RANGE02875-0-062
Figure 64. Active Power Calculation Output Range
ENERGY CALCULATION
As stated earlier, power is defined as the rate of energy flow. This relationship can be expressed mathematically in Equation 12. dtdEP= (12)
where: P is power. E is energy.
Conversely, energy is given as the integral of power.
∫=PdtE (13)
ADE7753
Rev. C | Page 30 of 60
FORWAVEFORM
ACCUMULATIOIN
1
24
24
LPF2
V
I
0x19999
0x19999A
0x000000
INSTANTANEOUS
POWER SIGNAL – p(t)
FORWAVEF0RM
SAMPLING
32
0xCCCCD
CURRENT SIGNAL – i(t)
HPF
VOLTAGESIGNAL– v(t)
MULTIPLIER
+ +
APOS [15:0]
sgn 26 25 2-6 2-7 2-8
02875-0-064
WGAIN[11:0]
Figure 65. Active Power Signal Processing
The ADE7753 achieves the integration of the active power signal by continuously accumulating the active power signal in an internal nonreadable 49-bit energy register. The active energy register
(AENERGY[23:0]) represents the upper 24 bits of this internal
register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 14
expresses the relationship. ⎭ ⎬ ⎫
⎩ ⎨ ⎧
= × = ∫ Σ
∞
→0 =1
) ( ) (
t n
T nTpLimdttpE (14)
where: n is the discrete time sample number.
T is the sample period. The discrete time sample period (T) for the accumulation register in the ADE7753 is 1.1μs (4/CLKIN). As well as
calculating the energy, this integration removes any sinusoidal components that might be in the active power signal. Figure 65
shows this discrete time integration or accumulation. The active power signal in the waveform register is continuously added to the internal active energy register. This addition is a signed addition; therefore negative energy is subtracted from the active energy contents. The exception to this is when POAM is
selected in the MODE[15:0] register. In this case, only positive
energy contributes to the active energy accumulation—see the
Positive-Only Accumulation Mode section. The output of the multiplier is divided by WDIV. If the value in the WDIV register is equal to 0, then the internal active energy register is divided by 1. WDIV is an 8-bit unsigned register.
After dividing by WDIV, the active energy is accumulated in a
49-bit internal energy accumulation register. The upper 24 bits
of this register are accessible through a read to the active energy register (AENERGY[23:0]). A read to the RAENERGY register
returns the content of the AENERGY register and the upper 24 bits of the internal register are cleared. As shown in Figure 65, the active power signal is accumulated in an internal 49-bit signed
register. The active power signal can be read from the waveform register by setting MODE[14:13] = 0,0 and setting the WSMP
bit (Bit 3) in the interrupt enable register to 1. Like the Channel 1 and Channel 2 waveform sampling modes, the waveform date is available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS—see Figure 52.
Figure 66 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three curves displayed
illustrate the minimum period of time it takes the energy register to roll over when the active power gain register contents are
0x7FF, 0x000, and 0x800. The watt gain register is used to carry
out power calibration in the ADE7753. As shown, the fastest
integration time occurs when the watt gain register is set to maximum full scale, i.e., 0x7FF. 0x00,0000
0x7F,FFFF
0x3F,FFFF
0x40,0000
0x80,0000
AENERGY [23:0]
4 6.2 8 12.5
TIME (minutes)
WGAIN = 0x7FF
WGAIN = 0x000
WGAIN = 0x800
02875-0-065
Figure 66. Energy Register Rollover Time for Full-Scale Power (Minimum and Maximum Power Gain) Note that the energy register contents rolls over to full-scale
negative (0x800000) and continues to increase in value when
the power or energy flow is positive—see Figure 66. Conversely, if the power is negative, the energy register underflows to full-
scale positive (0x7FFFFF) and continues to decrease in value. By using the interrupt enable register, the ADE7753 can be
configured to issue an interrupt (IRQ) when the active energy register is greater than half-full (positive or negative) or when an overflow or underflow occurs. Integration Time under Steady Load As mentioned in the last section, the discrete time sample period (T) for the accumulation register is 1.1 μs (4/CLKIN).
With full-scale sinusoidal signals on the analog inputs and the
WGAIN register set to 0x000, the average word value from each
LPF2 is 0xCCCCD—see Figure 61. The maximum positive
value that can be stored in the internal 49-bit register is 248 or
ADE7753
Rev. C | Page 31 of 60
0xFFFF,FFFF,FFFF before it overflows. The integration time under these conditions with WDIV = 0 is calculated as follows:
Time = xCCCCD0FFFFFFFF,xFFFF,0× 1.12 μs = 375.8 s = 6.26 min(15)
When WDIV is set to a value different from 0, the integration time varies, as shown in Equation 16.
WDIVTimeTimeWDIV×==0 (16)
POWER OFFSET CALIBRATION
The ADE7753 also incorporates an active power offset register (APOS[15:0]). This is a signed twos complement 16-bit register that can be used to remove offsets in the active power calculation—see Figure 65. An offset could exist in the power calculation due to crosstalk between channels on the PCB or in the IC itself. The offset calibration allows the contents of the active power register to be maintained at 0 when no power is being consumed.
The 256 LSBs (APOS = 0x0100) written to the active power offset register are equivalent to 1 LSB in the waveform sample register. Assuming the average value, output from LPF2 is 0xCCCCD (838,861d) when inputs on Channels 1 and 2 are both at full scale. At −60 dB down on Channel 1 (1/1000 of the Channel 1 full-scale input), the average word value output from LPF2 is 838.861 (838,861/1,000). One LSB in the LPF2 output has a measurement error of 1/838.861 × 100% = 0.119% of the average value. The active power offset register has a resolution equal to 1/256 LSB of the waveform register, therefore the power offset correction resolution is 0.00047%/LSB (0.119%/256) at –60 dB.
ENERGY-TO-FREQUENCY CONVERSION
ADE7753 also provides energy-to-frequency conversion for calibration purposes. After initial calibration at manufacturing, the manufacturer or end customer often verify the energy meter calibration. One convenient way to verify the meter calibration is for the manufacturer to provide an output frequency, which is proportional to the energy or active power under steady load conditions. This output frequency can provide a simple, single-wire, optically isolated interface to external calibration equipment. Figure 67 illustrates the energy-to-frequency conversion in the ADE7753. CFNUM[11:0]CF110CFDEN[11:0]110AENERGY[48:0]48002875-0-066%DFC
Figure 67. ADE7753 Energy-to-Frequency Conversion
A digital-to-frequency converter (DFC) is used to generate the CF pulsed output. The DFC generates a pulse each time 1 LSB in the active energy register is accumulated. An output pulse is generated when (CFDEN + 1)/(CFNUM + 1) number of pulses are generated at the DFC output. Under steady load conditions, the output frequency is proportional to the active power.
The maximum output frequency, with ac input signals at full scale and CFNUM = 0x00 and CFDEN = 0x00, is approximately 23 kHz.
The ADE7753 incorporates two registers, CFNUM[11:0] and CFDEN[11:0], to set the CF frequency. These are unsigned 12-bit registers, which can be used to adjust the CF frequency to a wide range of values. These frequency-scaling registers are 12-bit registers, which can scale the output frequency by 1/212 to 1 with a step of 1/212.
If the value 0 is written to any of these registers, the value 1 would be applied to the register. The ratio (CFNUM + 1)/ (CFDEN + 1) should be smaller than 1 to ensure proper operation. If the ratio of the registers (CFNUM + 1)/(CFDEN + 1) is greater than 1, the register values would be adjusted to a ratio (CFNUM + 1)/(CFDEN + 1) of 1. For example, if the output frequency is 1.562 kHz while the contents of CFDEN are 0 (0x000), then the output frequency can be set to 6.1 Hz by writing 0xFF to the CFDEN register.
When CFNUM and CFDEN are both set to one, the CF pulse width is fixed at 16 CLKIN/4 clock cycles, approximately 18 μs with a CLKIN of 3.579545 MHz. If the CF pulse output is longer than 180 ms for an active energy frequency of less than 5.56 Hz, the pulse width is fixed at 90 ms. Otherwise, the pulse width is 50% of the duty cycle.
The output frequency has a slight ripple at a frequency equal to twice the line frequency. This is due to imperfect filtering of the instantaneous power signal to generate the active power signal—see the Active Power Calculation section. Equation 9 from the Active Power Calculation section gives an expression for the instantaneous power signal. This is filtered by LPF2, which has a magnitude response given by Equation 17. 29.811)(2ffH+= (17)
The active power signal (output of LPF2) can be rewritten as
p(t) = VI −⎥⎥⎥⎥⎥⎦⎤⎢⎢⎢⎢⎢⎣⎡⎟⎠⎞⎜⎝⎛+29.81L2fVI× cos(4πfLt) (18)
where fL is the line frequency, for example, 60 Hz.
From Equation 13,
E(t) = VIt − ⎥⎥⎥⎥⎥⎦⎤⎢⎢⎢⎢⎢⎣⎡⎟⎠⎞⎜⎝⎛+π29.814LL2ffVI× sin(4πfLt) (19)
ADE7753
Rev. C | Page 32 of 60
From Equation 19 it can be seen that there is a small ripple in the energy calculation due to a sin(2 ωt) component. This is shown graphically in Figure 68. The active energy calculation is shown by the dashed straight line and is equal to V × I × t. The sinusoidal ripple in the active energy calculation is also shown.
Since the average value of a sinusoid is 0, this ripple does not contribute to the energy calculation over time. However, the ripple can be observed in the frequency output, especially at higher output frequencies. The ripple gets larger as a percentage of the frequency at larger loads and higher output frequencies. The reason is simply that at higher output frequencies the integration or averaging time in the energy-to-frequency conversion process is shorter. As a consequence, some of the sinusoidal ripple is observable in the frequency output. Choosing a lower output frequency at CF for calibration can significantly reduce the ripple. Also, averaging the output frequency by using a longer gate time for the counter achieves the same results. VI–sin(4×π×fL×t)4×π×fL(1+2×fL/8.9Hz)E(t)tVlt02875-0-067
Figure 68. Output Frequency Ripple
WDIV[7:0]APOS[15:0]WGAIN[11:0]LPF1++LAENERGY [23:0]ACCUMULATE ACTIVEENERGY IN INTERNALREGISTER AND UPDATETHE LAENERGY REGISTERAT THE END OF LINECYCLINE CYCLESOUTPUTFROMLPF2FROMCHANNEL 2ADC230LINECYC [15:0]48002875-0-068%ZERO CROSSDETECTIONCALIBRATIONCONTROL
Figure 69. Energy Calculation Line Cycle Energy Accumulation Mode
ADE7753
Rev. C | Page 33 of 60
LINE CYCLE ENERGY ACCUMULATION MODE
In line cycle energy accumulation mode, the energy accumula-tion of the ADE7753 can be synchronized to the Channel 2 zero crossing so that active energy can be accumulated over an integral number of half line cycles. The advantage of summing the active energy over an integer number of line cycles is that the sinusoidal component in the active energy is reduced to 0. This eliminates any ripple in the energy calculation. Energy is calculated more accurately and in a shorter time because the integration period can be shortened. By using the line cycle energy accumulation mode, the energy calibration can be greatly simplified, and the time required to calibrate the meter can be significantly reduced. The ADE7753 is placed in line cycle energy accumulation mode by setting Bit 7 (CYCMODE) in the mode register. In line cycle energy accumulation mode, the ADE7753 accumulates the active power signal in the LAENERGY register (Address 0x04) for an integral number of line cycles, as shown in Figure 69. The number of half line cycles is specified in the LINECYC register (Address 0x1C). The ADE7753 can accumulate active power for up to 65,535 half line cycles. Because the active power is integrated on an integral number of line cycles, at the end of a line cycle energy accumu-lation cycle the CYCEND flag in the interrupt status register is set (Bit 2). If the CYCEND enable bit in the interrupt enable register is enabled, the IRQ output also goes active low. Thus the IRQ line can also be used to signal the completion of the line cycle energy accumulation. Another calibration cycle can start as long as the CYCMODE bit in the mode register is set.
From Equations 13 and 18,
E(t) = ∫∫⎪⎪⎭⎪⎪⎬⎫⎪⎪⎩⎪⎪⎨⎧⎟⎠⎞⎜⎝⎛+−nTnTfVIdtVI020cos9.81(2πft)dt (20)
where: n is an integer. T is the line cycle period.
Since the sinusoidal component is integrated over an integer number of line cycles, its value is always 0. Therefore,
E = + 0 (21) ∫nTVIdt0
E(t) = VInT (22)
Note that in this mode, the 16-bit LINECYC register can hold a maximum value of 65,535. In other words, the line energy accumulation mode can be used to accumulate active energy for a maximum duration over 65,535 half line cycles. At 60 Hz line frequency, it translates to a total duration of 65,535/120 Hz = 546 seconds.
POSITIVE-ONLY ACCUMULATION MODE
In positive-only accumulation mode, the energy accumulation is done only for positive power, ignoring any occurrence of negative power above or below the no-load threshold, as shown in Figure 70. The CF pulse also reflects this accumulation method when in this mode. The ADE7753 is placed in positive-only accumulation mode by setting the MSB of the mode register (MODE[15]). The default setting for this mode is off. Transitions in the direction of power flow, going from negative to positive or positive to negative, set the IRQ pin to active low if the interrupt enable register is enabled. The interrupt status registers, PPOS and PNEG, show which transition has occurred—see the ADE7753 register descriptions in . Table 12PNEGPPOSPPOSINTERRUPT STATUS REGISTERSPPOSPNEGPNEGIRQNO-LOADTHRESHOLDACTIVE POWERNO-LOADTHRESHOLDACTIVE ENERGY02875-0-069
Figure 70. Energy Accumulation in Positive-Only Accumulation Mode
NO-LOAD THRESHOLD
The ADE7753 includes a no-load threshold feature on the active energy that eliminates any creep effects in the meter. The ADE7753 accomplishes this by not accumulating energy if the multiplier output is below the no-load threshold. This threshold is 0.001% of the full-scale output frequency of the multiplier. Compare this value to the IEC1036 specification, which states that the meter must start up with a load equal to or less than 0.4% Ib. This standard translates to .0167% of the full-scale output frequency of the multiplier.
REACTIVE POWER CALCULATION
Reactive power is defined as the product of the voltage and current waveforms when one of these signals is phase-shifted by
ADE7753
Rev. C | Page 34 of 60
90°. The resulting waveform is called the instantaneous reactive power signal. Equation 25 gives an expression for the instanta-neous reactive power signal in an ac system when the phase of the current channel is shifted by +90°.
The average reactive power over an integral number of lines (n) is given in Equation 26.
v(t) = )sin(2θ+ωtV (23) ∫==nTVIdttRpnTRP0)sin()(1θ (26)
i(t) = )sin(2tIω ⎟⎠⎞⎜⎝⎛π+ω=′2sin2)(tIti (24)
where: T is the line cycle period. RP is referred to as the reactive power.
Note that the reactive power is equal to the dc component of the instantaneous reactive power signal Rp(t) in Equation 25. This is the relationship used to calculate reactive power in the ADE7753. The instantaneous reactive power signal Rp(t) is generated by multiplying Channel 1 and Channel 2. In this case, the phase of Channel 1 is shifted by +90°. The dc component of the instantaneous reactive power signal is then extracted by a low-pass filter in order to obtain the reactive power informa-tion. Figure 71 shows the signal processing in the reactive power calculation in the ADE7753.
where: θ is the phase difference between the voltage and current channel. V is the rms voltage. I is the rms current.
Rp(t) = v(t) × i’(t) (25)
Rp(t) = VI sin (θ) + VI sin(2ωt + θ)
ZERO-CROSSINGDETECTIONMULTIPLIER++LVARENERGY [23:0]ACCUMULATE REACTIVEENERGY IN INTERNALREGISTER AND UPDATETHE LVARENERGY REGISTERAT THE END OF LINECYC HALFLINE CYCLESINSTANTANEOUS REACTIVEPOWER SIGNAL (Rp(t))23049002875-0-070LPF1FROMCHANNEL 2ADCLINECYC [15:0]LPF2CALIBRATIONCONTROLπ2VI90 DEGREEPHASE SHIFT
Figure 71. Reactive Power Signal Processing
ADE7753
Rev. C | Page 35 of 60
The features of the line reactive energy accumulation are the same as the line active energy accumulation. The number of half line cycles is specified in the LINECYC register. LINECYC is an unsigned 16-bit register. The ADE7753 can accumulate reactive power for up to 65535 combined half cycles. At the end of an energy calibration cycle, the CYCEND flag in the interrupt status register is set. If the CYCEND mask bit in the interrupt mask register is enabled, the IRQ output also goes active low. Thus the IRQ line can also be used to signal the end of a cali-bration. The ADE7753 accumulates the reactive power signal in the LVARENERGY register for an integer number of half cycles, as shown in . Figure 71
SIGN OF REACTIVE POWER CALCULATION
Note that the average reactive power is a signed calculation. The phase shift filter has –90° phase shift when the integrator is enabled, and +90° phase shift when the integrator is disabled. Table 9 summarizes the relationship between the phase differ-ence between the voltage and the current and the sign of the resulting VAR calculation.
Table 9. Sign of Reactive Power Calculation
Angle
Integrator
Sign
Between 0° to 90°
Off
Positive
Between –90° to 0°
Off
Negative
Between 0° to 90°
On
Positive
Between –90° to 0°
On
Negative
APPARENT POWER CALCULATION
The apparent power is defined as the maximum power that can be delivered to a load. Vrms and Irms are the effective voltage and current delivered to the load; the apparent power (AP) is defined as Vrms × Irms. The angle θ between the active power and the apparent power generally represents the phase shift due to non-resistive loads. For single-phase applications, θ represents the angle between the voltage and the current signals—see Figure 72. REACTIVEPOWERAPPARENTPOWERACTIVEPOWER02875-0-071θ
Figure 72. Power Triangle
The apparent power is defined as Vrms × Irms. This expression is independent from the phase angle between the current and the voltage.
Figure 73 illustrates the signal processing in each phase for the calculation of the apparent power in the ADE7753. VrmsIrms0xAD055APPARENTPOWERSIGNAL(P)CURRENT RMS SIGNAL– i(t)VOLTAGERMSSIGNAL– v(t)MULTIPLIER02875-0-0720x000x1C82B30x000x17D338VAGAIN
Figure 73. Apparent Power Signal Processing
The gain of the apparent energy can be adjusted by using the multiplier and VAGAIN register (VAGAIN[11:0]). The gain is adjusted by writing a twos complement, 12-bit word to the VAGAIN register. Equation 29 shows how the gain adjustment is related to the contents of the VAGAIN register. ⎟⎟⎠⎞⎜⎜⎝⎛⎭⎬⎫⎩⎨⎧+×=1221VAGAINPowerApparentINOutputVAGA(29)
For example, when 0x7FF is written to the VAGAIN register, the power output is scaled up by 50%. 0x7FF = 2047d, 2047/212 = 0.5. Similarly, 0x800 = –2047d (signed twos complement) and power output is scaled by –50%. Each LSB represents 0.0244% of the power output. The apparent power is calculated with the current and voltage rms values obtained in the rms blocks of the ADE7753. Figure 74 shows the maximum code (hexadecimal) output range of the apparent power signal. Note that the output range changes depending on the contents of the apparent power gain registers. The minimum output range is given when the apparent power gain register content is equal to 0x800 and the maximum range is given by writing 0x7FF to the apparent power gain register. This can be used to calibrate the apparent power (or energy) calculation in the ADE7753. 0x1038800xAD0550x5682B0x000000x0000x7FF0x800{VAGAIN[11:0]}APPARENTPOWER100%FSAPPARENTPOWER150%FSAPPARENTPOWER50%FSAPPARENT POWERCALIBRATION RANGEVOLTAGE AND CURRENTCHANNEL INPUTS: 0.5V/GAIN02875-0-073
Figure 74. Apparent Power Calculation Output Range
Apparent Power Offset Calibration
Each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value—see Channel 1 RMS Calculation and Channel 2 RMS Calculation sections. The Channel 1 and Channel 2 rms values are then multiplied together in the apparent power signal processing. Since no additional offsets are created in the multiplication of the rms values, there is no specific offset
ADE7753
Rev. C | Page 36 of 60
compensation in the apparent power signal processing. The offset compensation of the apparent power measurement is done by calibrating each individual rms measurement.
APPARENT ENERGY CALCULATION
The apparent energy is given as the integral of the apparent power.
∫=dttPowerApparentEnergyApparent)( (30)
The ADE7753 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal 49-bit register. The apparent energy register (VAENERGY[23:0]) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 31 expresses the relationship
⎪⎭⎪⎬⎫⎪⎩⎪⎨⎧×=Σ∞=→00)(nTTnTPowerApparentLimEnergyApparent (31)
where:
n is the discrete time sample number. T is the sample period.
The discrete time sample period (T) for the accumulation register in the ADE7753 is 1.1 μs (4/CLKIN).
Figure 75 shows this discrete time integration or accumulation. The apparent power signal is continuously added to the internal register. This addition is a signed addition even if the apparent energy remains theoretically always positive.
The 49 bits of the internal register are divided by VADIV. If the value in the VADIV register is 0, then the internal active energy register is divided by 1. VADIV is an 8-bit unsigned register. The upper 24 bits are then written in the 24-bit apparent energy register (VAENERGY[23:0]). RVAENERGY register (24 bits long) is provided to read the apparent energy. This register is reset to 0 after a read operation.
Figure 76 shows this apparent energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three curves displayed illustrate the minimum time it takes the energy register to roll over when the VAGAIN registers content is equal to 0x7FF, 0x000, and 0x800. The VAGAIN register is used to carry out an apparent power calibration in the ADE7753. As shown, the fastest integration time occurs when the VAGAIN register is set to maximum full scale, i.e., 0x7FF. VADIVAPPARENT POWER++VAENERGY [23:0]APPARENTPOWERAREACCUMULATED(INTEGRATED)INTHEAPPARENTENERGYREGISTER23048048002875-0-074%TIME (nT)TACTIVEPOWERSIGNAL=P
Figure 75. ADE7753 Apparent Energy Calculation
0xFF,FFFF0x80,00000x40,00000x20,00000x00,0000VAENERGY[23:0]6.2612.5218.7825.04TIME (minutes)VAGAIN = 0x7FFVAGAIN = 0x000VAGAIN = 0x80002875-0-075
Figure 76. Energy Register Rollover Time for Full-Scale Power (Maximum and Minimum Power Gain)
Note that the apparent energy register is unsigned—see Figure 76. By using the interrupt enable register, the ADE7753 can be con-figured to issue an interrupt (IRQ) when the apparent energy register is more than half full or when an overflow occurs. The half full interrupt for the unsigned apparent energy register is based on 24 bits as opposed to 23 bits for the signed active energy register.
Integration Times under Steady Load
As mentioned in the last section, the discrete time sample period (T) for the accumulation register is 1.1 μs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs and the VAGAIN register set to 0x000, the average word value from apparent power stage is 0xAD055—see the Apparent Power Calculation section. The maximum value that can be stored in the apparent energy register before it overflows is 224 or 0xFF,FFFF. The average word value is added to the internal register, which can store 248 or 0xFFFF,FFFF,FFFF before it
ADE7753
Rev. C | Page 37 of 60
overflows. Therefore, the integration time under these conditions with VADIV = 0 is calculated as follows:
LINE APPARENT ENERGY ACCUMULATION
Time = 055xD0FFFFFFFF,xFFFF,0× 1.2 μs = 888 s = 12.52 min(32)
When VADIV is set to a value different from 0, the integration time varies, as shown in Equation 33.
Time = TimeWDIV = 0 × VADIV (33)
The ADE7753 is designed with a special apparent energy accumulation mode, which simplifies the calibration process. By using the on-chip zero-crossing detection, the ADE7753 accumulates the apparent power signal in the LVAENERGY register for an integral number of half cycles, as shown in Figure 77. The line apparent energy accumulation mode is always active.
The number of half line cycles is specified in the LINECYC register, which is an unsigned 16-bit register. The ADE7753 can accumulate apparent power for up to 65535 combined half cycles. Because the apparent power is integrated on the same integral number of line cycles as the line active energy register, these two values can be compared easily. The active energy and the apparent energy are calculated more accurately because of this precise timing control and provide all the information needed for reactive power and power factor calculation. At the end of an energy calibration cycle, the CYCEND flag in the interrupt status register is set. If the CYCEND mask bit in the interrupt mask register is enabled, the IRQ output also goes active low. Thus the IRQ line can also be used to signal the end of a calibration.
The line apparent energy accumulation uses the same signal path as the apparent energy accumulation. The LSB size of these two registers is equivalent.
VADIV[7:0]LPF1++LVAENERGY [23:0]LVAENERGY REGISTER ISUPDATED EVERY LINECYCZERO CROSSINGS WITH THETOTAL APPARENT ENERGYDURING THAT DURATIONAPPARENTPOWERFROMCHANNEL 2ADC230LINECYC [15:0]48002875-0-076%ZERO-CROSSINGDETECTIONCALIBRATIONCONTROL
Figure 77. ADE7753 Apparent Energy Calibration
ADE7753
Rev. C | Page 38 of 60
ENERGIES SCALING
The ADE7753 provides measurements of active, reactive, and apparent energies. These measurements do not have the same scaling and thus cannot be compared directly to each other.
Table 10. Energies Scaling
PF = 1
PF = 0.707
PF = 0
Integrator On at 50 Hz
Active
Wh
Wh × 0.707
0
Reactive
0
Wh × 0.508
Wh × 0.719
Apparent
Wh × 0.848
Wh × 0.848
Wh × 0.848
Integrator Off at 50 Hz
Active
Wh
Wh × 0.707
0
Reactive
0
Wh × 0.245
Wh × 0.347
Apparent
Wh × 0.848
Wh × 0.848
Wh × 0.848
Integrator On at 60 Hz
Active
Wh
Wh × 0.707
0
Reactive
0
Wh × 0.610
Wh × 0.863
Apparent
Wh × 0.827
Wh × 0.827
Wh × 0.827
Integrator Off at 60 Hz
Active
Wh
Wh × 0.707
0
Reactive
0
Wh × 0.204
Wh × 0.289
Apparent
Wh × 0.827
Wh × 0.827
Wh × 0.827
CALIBRATING AN ENERGY METER BASED ON THE ADE7753
The ADE7753 provides gain and offset compensation for active and apparent energy calibration. Its phase compensation corrects phase error in active, apparent and reactive energy. If a shunt is used, offset and phase calibration may not be required. A reference meter or an accurate source can be used to calibrate the ADE7753.
When using a reference meter, the ADE7753 calibration output frequency, CF, is adjusted to match the frequency output of the reference meter. A pulse output is only provided for the active energy measurement in the ADE7753. If it is desired to use a reference meter for calibrating the VA and VAR, then additional code would have to be written in a microprocessor to produce a pulsed output for these quantities. Otherwise, VA and VAR calibration require an accurate source.
The ADE7753 provides a line cycle accumulation mode for calibration using an accurate source. In this method, the active energy accumulation rate is adjusted to produce a desired CF frequency. The benefit of using this mode is that the effect of the ripple noise in the active energy is eliminated. Up to 65535 half line cycles can be accumulated, thus providing a stable energy value to average. The accumulation time is calculated from the line cycle period, measured by the ADE7753 in the PERIOD register, and the number of half line cycles in the accumulation, fixed by the LINECYC register.
Current and voltage rms offset calibration removes any apparent energy offset. A gain calibration is also provided for apparent energy. Figure 79 shows an optimized calibration flow for active energy, rms, and apparent energy.
Active and apparent energy gain calibrations can take place concurrently, with a read of the accumulated apparent energy register following that of the accumulated active energy register.
Figure 78 shows the calibration flow for the active energy portion of the ADE7753.
Figure 78. Active Energy Calibration
The ADE7753 does not provide means to calibrate reactive energy gain and offset. The reactive energy portion of the ADE7753 can be calibrated externally, through a MCU.
Figure 79. Apparent and Active Energy Calibration
ADE7753
Rev. C | Page 39 of 60
Watt Gain
The first step of calibrating the gain is to define the line voltage, base current and the maximum current for the meter. A meter constant needs to be determined for CF, such as 3200 imp/kWh or 3.2 imp/Wh. Note that the line voltage and the maximum current scale to half of their respective analog input ranges in this example.
The expected CF in Hz is
CFexpected (Hz) = )cos(s/h3600(W)(imp/Wh)ϕ××LoadantMeterConst (34)
whereϕis the angle between I and V, and cos is the power factor. )(ϕ
The ratio of active energy LSBs per CF pulse is adjusted using the CFNUM, CFDEN, and WDIV registers.
CFexpected = )1()1((s)++××CFDENCFNUMWDIVonTimeAccumulatiLAENERGY (35)
The relationship between watt-hours accumulated and the quantity read from AENERGY can be determined from the amount of active energy accumulated over time with a given load: hLAENERGYTimeonAccumulatiLoads/3600(s)(W)LSBWh××= (36)
where Accumulation Time can be determined from the value in the line period and the number of half line cycles fixed in the LINECYC register.
Accumulation time(s) =2(s)PeriodLineLINECYCIB× (37)
The line period can be determined from the PERIOD register:
Line Period(s) = PERIOD ×CLKIN8 (38)
The AENERGY Wh/LSB ratio can also be expressed in terms of the meter constant: (imp/Wh))1()1(LSBWhantMeterConstWDIVCFDENCFNUM×++= (39)
In a meter design, WDIV, CFNUM, and CFDEN should be kept constant across all meters to ensure that the Wh/LSB constant is maintained. Leaving WDIV at its default value of 0 ensures maximum resolution. The WDIV register is not included in the CF signal chain so it does not affect the frequency pulse output.
The WGAIN register is used to finely calibrate each meter. Cali-brating the WGAIN register changes both CF and AENERGY for a given load condition.
AENERGYexpected = AENERGYnominal ×⎟⎠⎞⎜⎝⎛+1221WGAIN (40)
CFexpected (Hz) = CFnominal × ⎟⎠⎞⎜⎝⎛+×++1221)1()1(WGAINCFDENCFNUM (41)
When calibrating with a reference meter, WGAIN is adjusted until CF matches the reference meter pulse output. If an accurate source is used to calibrate, WGAIN is modified until the active energy accumulation rate yields the expected CF pulse rate.
The steps of designing and calibrating the active energy portion of a meter with either a reference meter or an accurate source are outlined in the following examples. The specifications for this example are
Meter Constant: MeterConstant(imp/Wh) = 3.2 Base Current: Ib = 10 A Maximum Current: IMAX = 60 A Line Voltage: Vnominal = 220 V Line Frequency: fl = 50 Hz
The first step in calibration with either a reference meter or an accurate source is to calculate the CF denominator, CFDEN. This is done by comparing the expected CF pulse output to the nominal CF output with the default CFDEN = 0x3F and CFNUM = 0x3F and when the base current is applied.
The expected CF output for this meter with the base current applied is 1.9556 Hz using Equation 34.
CFIB(expected)(Hz) = Hz9556.1)cos(s/h3600V220A10imp/Wh200.3=ϕ×××
Alternatively, CFexpected can be measured from a reference meter pulse output if available.
CFexpected(Hz) = CFref (42)
The maximum CF frequency measured without any frequency division and with ac inputs at full scale is 23 kHz. For this example, the nominal CF with the test current, Ib, applied is 958 Hz. In this example the line voltage and maximum current scale half of their respective analog input ranges. The line voltage and maximum current should not be fixed at the maximum analog inputs to account for occurrences such as spikes on the line.
CFnominal(Hz) = MAXII×××2121kHz23 (43)
CFIB(nominal)(Hz) = Hz95860102121kHz23=×××
The nominal CF on a sample set of meters should be measured using the default CFDEN, CFNUM, and WDIV to ensure that the best CFDEN is chosen for the design.
With the CFNUM register set to 0, CFDEN is calculated to be 489 for the example meter:
ADE7753
Rev. C | Page 40 of 60
CFDEN = 1)()(−⎟⎟⎠⎞⎜⎜⎝⎛expectedIBnominalIBCFCFINT (44)
CFDEN = 489)1490(19556.1958=−=−⎟⎠⎞⎜⎝⎛INT
This value for CFDEN should be loaded into each meter before calibration. The WGAIN and WDIV registers can then be used to finely calibrate the CF output. The following sections explain how to calibrate a meter based on ADE7753 when using a reference meter or an accurate source.
Calibrating Watt Gain Using a Reference Meter Example
The CFDEN and CFNUM values for the design should be written to their respective registers before beginning the calibration steps shown in Figure 80. When using a reference meter, the %ERROR in CF is measured by comparing the CF output of the ADE7753 meter with the pulse output of the reference meter with the same test conditions applied to both meters. Equation 45 defines the percent error with respect to the pulse outputs of both meters (using the base current, Ib):
%ERRORCF(IB) = 100)()(×−IBrefIBrefIBCFCFCF (45)
CALCULATE CFDEN VALUE FOR DESIGNWRITE CFDEN VALUE TO CFDEN REGISTERADDR. 0x15 = CFDENWRITE WGAIN VALUE TO THE WGAINREGISTER: ADDR. 0x12MEASURE THE % ERROR BETWEENTHE CF OUTPUT AND THEREFERENCE METER OUTPUTSET ITEST = Ib, VTEST = VNOM, PF = 102875-A-006CALCULATE WGAIN. SEE EQUATION 46.
Figure 80. Calibrating Watt Gain Using a Reference Meter
For this example:
Meter Constant: MeterConstant(imp/Wh) = 3.2 CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 % Error measured at Base Current: %ERRORCF(IB) = -3.07%
One LSB change in WGAIN changes the active energy registers and CF by 0.0244%. WGAIN is a signed twos complement register and can correct for up to a 50% error. Assuming a −3.07% error, WGAIN is 126:
WGAIN = INT⎟⎟⎠⎞⎜⎜⎝⎛−%0244.0%)(IBCFERROR (46)
WGAIN = INT 126%0244.0%07.3=⎟⎠⎞⎜⎝⎛−−
When CF is calibrated, the AENERGY register has the same Wh/LSB constant from meter to meter if the meter constant, WDIV, and the CFNUM/CFDEN ratio remain the same. The Wh/LSB ratio for this meter is 6.378 × 10−4 using Equation 39 with WDIV at the default value. (imp/Wh))1()1(LSBWhantMeterConstWDIVCFDENCFNUM×++= 410378.62.34901imp/Wh200.3)1490(1LSBWh−×=×=+=
Calibrating Watt Gain Using an Accurate Source Example
The CFDEN value calculated using Equation 44 should be written to the CFDEN register before beginning calibration and zero should be written to the CFNUM register. First, the line accumulation mode and the line accumulation interrupt should be enabled. Next, the number of half line cycles for the energy accumulation is written to the LINECYC register. This sets the accumulation time. Reset the interrupt status register and wait for the line cycle accumulation interrupt. The first line cycle accumulation results may not have used the accumulation time set by the LINECYC register and should be discarded. After resetting the interrupt status register, the following line cycle readings will be valid. When LINECYC half line cycles have elapsed, the IRQ pin goes active low and the nominal LAENERGY with the test current applied can be read. This LAENERGY value is compared to the expected LAENERGY value to deter-mine the WGAIN value. If apparent energy gain calibration is performed at the same time, LVAENERGY can be read directly after LAENERGY. Both registers should be read before the next interrupt is issued on the IRQ pin. Refer to the section for more details. details the steps that calibrate the watt gain using an accurate source. Apparent Energy CalculationFigure 81
ADE7753
Rev. C | Page 41 of 60
WRITE WGAIN VALUE TO THE WGAINREGISTER: ADDR. 0x12CALCULATE CFDEN VALUE FOR DESIGNWRITE CFDEN VALUE TO CFDEN REGISTERADDR. 0x15 = CFDENSET HALF LINECYCLES FOR ACCUMULATIONIN LINECYC REGISTER ADDR. 0x1CSET ITEST = Ib, VTEST = VNOM, PF = 1CALCULATE WGAIN. SEE EQUATION 47.SET MODE FOR LINE CYCLEACCUMULATION ADDR. 0x09 = 0x0080ENABLE LINE CYCLE ACCUMULATIONINTERRUPT ADDR. 0x0A = 0x04READ LINE ACCUMULATION ENERGYADDR. 0x04RESET THE INTERRUPT STATUSREAD REGISTER ADDR. 0x0CINTERRUPT?NONOYESYES02875-A-007RESET THE INTERRUPT STATUSREAD REGISTER ADDR. 0x0CINTERRUPT?
Figure 81. Calibrating Watt Gain Using an Accurate Source
Equation 47 describes the relationship between the expected LAENERGY value and the LAENERGY measured in the test condition:
WGAIN = INT⎟⎟⎠⎞⎜⎜⎝⎛×⎟⎟⎠⎞⎜⎜⎝⎛−12)()(21nominalIBexpectedIBLAENERGYLAENERGY (47)
The nominal LAENERGY reading, LAENERGYIB(nominal), is the LAENERGY reading with the test current applied. The expected LAENERGY reading is calculated from the following equation:
LAENERGYIB(expected) = INT⎟⎟⎟⎟⎠⎞⎜⎜⎜⎜⎝⎛×++×WDIVCFDENCFNUMTimeonAccumulatiCFexpectedIB11(s))( (48)
where CFIB(expected)(Hz) is calculated from Equation 34, accumula-tion time is calculated from Equation 37, and the line period is determined from the PERIOD register according to Equation 38.
For this example:
Meter Constant: MeterConstant(imp/Wh) = 3.2 Test Current: Ib = 10 A Line Voltage: Vnominal = 220 V Line Frequency: fl = 50 Hz Half Line Cycles: LINECYCIB = 2000 CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 Energy Reading at Base Current: LAENERGYIB (nominal) = 17174 Period Register Reading: PERIOD = 8959 Clock Frequency: CLKIN = 3.579545 MHz
CFexpected is calculated to be 1.9556 Hz according to Equation 34. LAENERGYexpected is calculated to be 19186 using Equation 48.
CFIB(expected)(Hz) = )(cos(s/h3600A10V220imp/Wh200.3ϕ××× = 1.9556 Hz
LAENERGYIB(expected) = INT⎟⎟⎟⎟⎠⎞⎜⎜⎜⎜⎝⎛×++×××WDIVCFDENCFNUMCLKINPERIODLINECYCCFIBexpectedIB11/82/)(
LAENERGYIB(expected) = INT114891)10579545.3/(889592/20009556.16⎟⎟⎟⎟⎠⎞⎜⎜⎜⎜⎝⎛+××××=
19186)4.19186(=INT
WGAIN is calculated to be 480 using Equation 47.
WGAIN = INT48021171741918612=⎟⎠⎞⎜⎝⎛×⎟⎠⎞⎜⎝⎛−
Note that WGAIN is a signed twos complement register.
With WDIV and CFNUM set to 0, LAENERGY can be expressed as
ADE7753
Rev. C | Page 42 of 60
LAENERGYIB(expected) = ))1(/82/()(+××××CFDENCLKINPERIODLINECYCCFINTIBexpectedIB
The calculated Wh/LSB ratio for the active energy register, using Equation 39 is 6.378 × 10−4: 410378.6imp/Wh200.3)1489(1LSBWh−×=+=
Watt Offset
Offset calibration allows outstanding performance over a wide dynamic range, for example, 1000:1. To do this calibration two measurements are needed at unity power factor, one at Ib and the other at the lowest current to be corrected. Either calibration frequency or line cycle accumulation measurements can be used to determine the energy offset. Gain calibration should be performed prior to offset calibration.
Offset calibration is performed by determining the active energy error rate. Once the active energy error rate has been determined, the value to write to the APOS register to correct the offset is calculated.
APOS = − CLKINRateErrorAENERGY352× (49)
The AENERGY registers update at a rate of CLKIN/4. The twos complement APOS register provides a fine adjustment to the active power calculation. It represents a fixed amount of power offset to be adjusted every CLKIN/4. The 8 LSBs of the APOS register are fractional such that one LSB of APOS represents 1/256 of the least significant bit of the internal active energy register. Therefore, one LSB of the APOS register represents 2−33 of the AENERGY[23:0] active energy register.
The steps involved in determining the active energy error rate for both line accumulation and reference meter calibration options are shown in the following sections.
Calibrating Watt Offset Using a Reference Meter Example
Figure 82 shows the steps involved in calibrating watt offset with a reference meter. WRITE APOS VALUE TO THE APOSREGISTER: ADDR. 0x11MEASURE THE % ERROR BETWEEN THECF OUTPUT AND THE REFERENCE METEROUTPUT, AND THE LOAD IN WATTSSET ITEST = IMIN, VTEST = VNOM, PF = 102875-A-008CALCULATE APOS. SEE EQUATION 49.
Figure 82. Calibrating Watt Offset Using a Reference Meter
For this example:
Meter Constant: MeterConstant(imp/Wh) = 3.2 Minimum Current: IMIN = 40 mA Load at Minimum Current: WIMIN = 9.6 W CF Error at Minimum Current: %ERRORCF(IMIN) = 1.3% CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 Clock Frequency: CLKIN = 3.579545 MHz
Using Equation 49, APOS is calculated to be −522 for this example.
CF Absolute Error = CFIMIN(nominal) − CFIMIN(expected) (50)
CF Absolute Error = (%ERRORCF(IMIN)) × WIMIN × 3600(imp/Wh)antMeterConst (51)
CF Absolute Error = Hz000110933.03600200.36.9100%3.1=××⎟⎠⎞⎜⎝⎛
Then,
AENERGY Error Rate (LSB/s) = CF Absolute Error × 11++CFNUMCFDEN (52)
AENERGY Error Rate (LSB/s) = 0.000110933 × 05436.01490=
Using Equation 49, APOS is −522.
APOS = − 52210579545.3205436.0635−=××
APOS can be represented as follows with CFNUM and WDIV set at 0:
APOS = −CLKINCFDENantMeterConstWERRORIMINIMINCF35)(2)1(3600(imp/Wh))(%×+×××
ADE7753
Rev. C | Page 43 of 60
Calibrating Watt Offset with an Accurate Source Example
Figure 83 is the flowchart for watt offset calibration with an accurate source. SET HALF LINE CYCLES FOR ACCUMULATIONIN LINECYC REGISTER ADDR. 0x1CSET ITEST = IMIN, VTEST = VNOM, PF = 1CALCULATE APOS. SEE EQUATION 49.SET MODE FOR LINE CYCLEACCUMULATION ADDR. 0x09 = 0x0080ENABLE LINE CYCLE ACCUMULATIONINTERRUPT ADDR. 0x0A = 0x04READ LINE ACCUMULATION ENERGYADDR. 0x04RESET THE INTERRUPT STATUSREAD REGISTER ADDR. 0x0CINTERRUPT?NONOYESYESRESET THE INTERRUPT STATUSREAD REGISTER ADDR. 0x0CINTERRUPT?WRITE APOS VALUE TO THE APOSREGISTER: ADDR. 0x1102875-A-009
Figure 83. Calibrating Watt Offset with an Accurate Source
For this example:
Meter Constant: MeterConstant(imp/Wh) = 3.2 Line Voltage: Vnominal = 220 V Line Frequency: fl = 50 Hz CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 Base Current: Ib = 10 A Half Line Cycles Used at Base Current: LINECYC(IB) = 2000 Period Register Reading: PERIOD = 8959 Clock Frequency: CLKIN = 3.579545 MHz Expected LAENERGY Register Value at Base Current (from the Watt Gain section):LAENERGYIB(expected) = 19186 Minimum Current: IMIN = 40 mA Number of Half Line Cycles used at Minimum Current: LINECYC(IMIN) = 35700 Active energy Reading at Minimum Current: LAENERGYIMIN(nominal) = 1395
The LAENERGYexpected at IMIN is 1370 using Equation 53.
LAENERGYIMIN(expected) = INT ⎟⎟⎠⎞⎜⎜⎝⎛××IBMINexpectedIBBMINLINECYCLINECYCILAENERGYII)((53)
LAENERGYIMIN(expected) = INT 1370)80.1369(200035700191861004.0==⎟⎠⎞⎜⎝⎛××INT
where: LAENERGYIB(expected) is the expected LAENERGY reading at Ib from the watt gain calibration. LINECYCIMIN is the number of half line cycles that energy is accumulated over when measuring at IMIN.
More line cycles could be required at the minimum current to minimize the effect of quantization error on the offset calibration. For example, if a test current of 40 mA results in an active energy accumulation of 113 after 2000 half line cycles, one LSB variation in this reading represents an 0.8% error. This measurement does not provide enough resolution to calibrate out a <1% offset error. However, if the active energy is accumulated over 37,500 half line cycles, one LSB variation results in 0.05% error, reducing the quantization error.
APOS is −672 using Equations 55 and 49.
LAENERGY Absolute Error = LAENERGYIMIN(nominal) − LAENERGYIMIN(expected)
LAENERGY Absolute Error = 1395 − 1370 = 25 (54)
AENERGY Error Rate (LSB/s) = PERIODCLKINLINECYCErrorAbsoluteLAENERGY××82/ (55)
AENERGY Error Rate (LSB/s) = 069948771.08959810579545.32/35700256=×××
APOS = −CLKINRateErrorAENERGY352×
APOS = −67210579545.32069948771.0635−=××
ADE7753
Rev. C | Page 44 of 60
Phase Calibration
The PHCAL register is provided to remove small phase errors. The ADE7753 compensates for phase error by inserting a small time delay or advance on the voltage channel input. Phase leads up to 1.84° and phase lags up to 0.72° at 50 Hz can be corrected. The error is determined by measuring the active energy at IB and two power factors, PF = 1 and PF =0.5 inductive.
Some CTs may introduce large phase errors that are beyond the range of the phase calibration register. In this case, coarse phase compensation has to be done externally with an analog filter.
The phase error can be obtained from either CF or LAENERGY measurements:
Error = 22)()(5.,expectedIBexpectedIBPFIBLAENERGYLAENERGYLAENERGY−= (56)
If watt gain and offset calibration have been performed, there should be 0% error in CF at unity power factor and then:
Error = %ERRORCF(IB,PF = .5) /100 (57)
The phase error is
Phase Error (°) = −Arcsin⎟⎟⎠⎞⎜⎜⎝⎛3Error (58)
The relationship between phase error and the PHCAL phase correction register is
PHCAL= INT()+⎟⎠⎞⎜⎝⎛°×°360PERIODErrorPhase0x0D (59)
The expression for PHCAL can be simplified using the assumption that at small x:
Arcsin(x) ≈ x
The delay introduced in the voltage channel by PHCAL is
Delay = (PHCAL − 0x0D) × 8/CLKIN (60)
The delay associated with the PHCAL register is a time delay if (PHCAL − 0x0D) is positive but represents a time advance if this quantity is negative. There is no time delay if PHCAL = 0x0D.
The phase correction is in the opposite direction of the phase error.
Phase Correction (°) = −(PHCAL − 0x0D) PERIOD°×360 (61)
Calibrating Phase Using a Reference Meter Example
A power factor of 0.5 inductive can be assumed if the pulse output rate of the reference meter is half of its PF = 1 rate. Then the %ERROR between CF and the pulse output of the reference meter can be used to perform the preceding calculations. WRITE PHCAL VALUE TO THE PHCALREGISTER: ADDR. 0x10MEASURE THE % ERROR BETWEENTHE CF OUTPUT AND THEREFERENCE METER OUTPUTSET ITEST = Ib, VTEST = VNOM, PF = 0.502875-A-010CALCULATE PHCAL. SEE EQUATION 59.
Figure 84. Calibrating Phase Using a Reference Meter
For this example:
CF % Error at PF = .5 Inductive: %ERRORCF(IB,PF = .5) = 0.215% PERIOD Register Reading: PERIOD = 8959
Then PHCAL is 11 using Equations 57 through 59:
Error = 0.215% / 100 = 0.00215
Phase Error (°) = −Arcsin°−=⎟⎟⎠⎞⎜⎜⎝⎛07.0300215.0
PHCAL = INT⎟⎠⎞⎜⎝⎛°×°−360895907.0+0x0D = −2 + 13 = 11
PHCAL can be expressed as follows:
PHCAL = INT ⎟⎟⎠⎞⎜⎜⎝⎛π×⎟⎟⎠⎞⎜⎜⎝⎛−23ArcsinPERIODError+ 0x0D (62)
Note that PHCAL is a signed twos complement register.
Setting the PHCAL register to 11 provides a phase correction of 0.08° to correct the phase lead:
Phase Correction (°) = PERIODPHCAL°×−−360)0x0D(
Phase Correction (°) = °=°×−−08.08960360)0x0D11(
ADE7753
Rev. C | Page 45 of 60
Calibrating Phase with an Accurate Source Example
With an accurate source, line cycle accumulation is a good method of calibrating phase error. The value of LAENERGY must be obtained at two power factors, PF = 1 and PF = 0.5 inductive. SET HALF LINE CYCLES FOR ACCUMULATIONIN LINECYC REGISTER ADDR. 0x1CSET ITEST = Ib, VTEST = VNOM, PF = 0.5CALCULATE PHCAL. SEE EQUATION 59.SET MODE FOR LINE CYCLEACCUMULATION ADDR. 0x09 = 0x0080ENABLE LINE CYCLE ACCUMULATIONINTERRUPT ADDR. 0x0A = 0x04READ LINE ACCUMULATION ENERGYADDR. 0x04RESET THE INTERRUPT STATUSREAD REGISTER ADDR. 0x0CINTERRUPT?NONOYESYESRESET THE INTERRUPT STATUSREAD REGISTER ADDR. 0x0CINTERRUPT?WRITE PHCAL VALUE TO THE PHCALREGISTER: ADDR. 0x1002875-A-011
Figure 85. Calibrating Phase with an Accurate Source
For this example:
Meter Constant: MeterConstant(imp/Wh) = 3.2 Line Voltage: Vnominal = 220 V Line Frequency: fl = 50 Hz CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 Base Current: Ib = 10 A Half Line Cycles Used at Base Current: LINECYCIB = 2000 PERIOD Register: PERIOD = 8959 Expected Line Accumulation at Unity Power Factor (from Watt Gain Section: LAENERGYIB(expected) = 19186 Active Energy Reading at PF = .5 inductive: LAENERGYIB, PF = .5 = 9613
The error using Equation 56 is
Error = 0021.02191862191869613=−
Phase Error (°) = −Arcsin°−=⎟⎟⎠⎞⎜⎜⎝⎛07.030021.0
Using Equation 59, PHCAL is calculated to be 11.
PHCAL = INT111320x0D360895907.0=+−=+⎟⎠⎞⎜⎝⎛°×°−
Note that PHCAL is a signed twos complement register.
The phase lead is corrected by 0.08° when the PHCAL register is set to 11:
Phase Correction (°) = PERIODPHCAL°×−−360)0x0D(
Phase Correction (°) = °=°×−−08.08960360)0x0D11(
VRMS and IRMS Calibration
VRMS and IRMS are calculated by squaring the input in a digital multiplier. )2cos()sin(V2)sin(V2)(tVVtttv222ω×−=ω×ω= (63)
The square of the rms value is extracted from v2(t) by a low-pass filter. The square root of the output of this low-pass filter gives the rms value. An offset correction is provided to cancel noise and offset contributions from the input.
There is ripple noise from the 2ω term because the low-pass filter does not completely attenuate the signal. This noise can be minimized by synchronizing the rms register readings with the zero crossing of the voltage signal. The IRQ output can be configured to indicate the zero crossing of the voltage signal.
This flowchart demonstrates how VRMS and IRMS readings are synchronized to the zero crossings of the voltage input. SET INTERRUPT ENABLE FOR ZEROCROSSING ADDR. 0x0A = 0x0010RESET THE INTERRUPT STATUSREAD REGISTER ADDR. 0x0CINTERRUPT?NOYES02875-A-003READ VRMS OR IRMSADDR. 0x17; 0x16RESET THE INTERRUPT STATUSREAD REGISTER ADDR. 0x0C
Figure 86. Synchronizing VRMS and IRMS Readings with Zero Crossings
ADE7753
Rev. C | Page 46 of 60
Apparent Energy
Voltage rms compensation is done after the LPF3 filter (see Figure 56).
Apparent energy gain calibration is provided for both meter-to-meter gain adjustment and for setting the VAh/LSB constant.
VRMS = VRMS0 + VRMSOS (64)
VAENERGY = ⎟⎠⎞⎜⎝⎛+××12211VAGAINVADIVVAENERGYinitial (68)
where:
VRMS0 is the rms measurement without offset correction. VRMS is linear from full-scale to full-scale/20.
VADIV is similar to the CFDEN for the watt hour calibration. It should be the same across all meters and determines the VAh/LSB constant. VAGAIN is used to calibrate individual meters.
To calibrate the offset, two VRMS measurements are required, for example, at Vnominal and Vnominal/10. Vnominal is set at half of the full-scale analog input range so the smallest linear VRMS reading is at Vnominal/10.
VRMSOS = 121221VVVRMSVVRMSV−×−× (65)
Apparent energy gain calibration should be performed before rms offset correction to make most efficient use of the current test points. Apparent energy gain and watt gain compensation require testing at Ib while rms and watt offset correction require a lower test current. Apparent energy gain calibration can be done at the same time as the watt-hour gain calibration using line cycle accumulation. In this case, LAENERGY and LVAENERGY, the line cycle accumulation apparent energy register, are both read following the line cycle accumulation interrupt. Figure 87 shows a flowchart for calibrating active and apparent energy simultaneously.
where VRMS1 and VRMS2 are rms register values without offset correction for input V1 and V2, respectively.
If the range of the 12-bit, twos complement VRMSOS register is not enough, the voltage channel offset register, CH2OS, can be used to correct the VRMS offset.
Current rms compensation is performed before the square root:
IRMS2 = IRMS02 + 32768 × IRMSOS (66)
VAGAIN = INT⎟⎟⎠⎞⎜⎜⎝⎛×⎟⎟⎠⎞⎜⎜⎝⎛−12)()(21nominalIBexpectedIBLVAENERGYLVAENERGY(69)
where IRMS0 is the rms measurement without offset correction. The current rms calculation is linear from full-scale to full-scale/100.
LVAENERGYIB(expected) = INT⎟⎟⎟⎟⎠⎞⎜⎜⎜⎜⎝⎛×××(s)s/h3600timeonAccumulaticonstantLSBVAhIVBnominal(70)
To calibrate this offset, two IRMS measurements are required, for example, at Ib and IMAX/50. IMAX is set at half of the full-scale analog input range so the smallest linear IRMS reading is at IMAX/50.
IRMSOS = 212221222221IIIRMSIIRMSI−×−××327681 (67)
The accumulation time is determined from Equation 37 and the line period can be determined from the PERIOD register accord-ing to Equation 38. The VAh represented by the VAENERGY register is
where IRMS1 and IRMS2 are rms register values without offset correction for input I1 and I2, respectively.
VAh = VAENERGY × VAh/LSB constant (71)
The VAh/LSB constant can be verified using this equation: LVAENERGYtimeonAccumulatiVAconstantLSBVAh3600(s)×= (72)
ADE7753
Rev. C | Page 47 of 60
CALCULATE CFDEN VALUE FOR DESIGNWRITE CFDEN VALUE TO CFDEN REGISTERADDR. 0x15 = CFDENSET HALF LINE CYCLES FOR ACCUMULATIONIN LINECYC REGISTER ADDR. 0x1CSET ITEST = Ib, VTEST = VNOM, PF = 1CALCULATE WGAIN. SEE EQUATION 47.SET MODE FOR LINE CYCLEACCUMULATION ADDR. 0x09 = 0x0080ENABLE LINE CYCLE ACCUMULATIONINTERRUPT ADDR. 0x0A = 0x04READ LINE ACCUMULATION ENERGYACTIVE ENERGY: ADDR. 0x04APPARAENT ENERGY: ADDR. 0x07RESET THE INTERRUPT STATUSREAD REGISTER ADDR. = 0x0CINTERRUPT?NONOYESYES02875-A-004RESET THE INTERRUPT STATUSREAD REGISTER ADDR. = 0x0CINTERRUPT?WRITE WGAIN VALUE TO ADDR. 0x12CALCULATE VAGAIN. SEE EQUATION 69.WRITE VGAIN VALUE TO ADDR. 0x1A
Figure 87. Active/Apparent Gain Calibration
Reactive Energy
Reactive energy is only available in line accumulation mode in the ADE7753. The accumulated reactive energy over LINECYC number of half line cycles is stored in the LVARENERGY register.
In the ADE7753, a low-pass filter at 2 Hz on the current channel is implemented for the reactive power calculation. This provides the 90 degree phase shift needed to calculate the reactive power. This filter introduces 1/f attenuation in the reactive energy accumulated. Compensation for this attenuation can be done externally in a microcontroller. The microcontroller can use the LVARENERGY register in order to produce a pulse output similar to the CF pulse for reactive energy.
To create a VAR pulse, an impulse/VARh constant must be determined. The 1/f attenuation correction factor is determined by comparing the nominal reactive energy accumulation rate to the expected value. The attenuation correction factor is multi-plied by the contents of the LVARENERGY register, with the ADE7753 in line accumulation mode.
ADE7753
Rev. C | Page 48 of 60
The impulse/LSB ratio used to convert the value in the LVARENERGY register into a pulse output can be expressed in terms of impulses/VARh and VARh/LSB.
imp/LSB = nominalexpectedIBVARCFVARCFLSBVARhVARhimp)(//=× (73)
VARCFIB(expected) = )sin(s/h3600)/(ϕ×××bnominalIVVARhimptVARConstan (74)
VARCFIB(nominal) = PERIODtimeonAccumulatiPERIODLVARENERGYIB××(s)Hz50 (75)
where the accumulation time is calculated from Equation 37. The line period can be determined from the PERIOD register according to Equation 38. Then VAR can be determined from the LVARENERGY register value:
VARh = PERIODPERIODLSBVARhLVARENERGYIBHz50/×× (76)
VAR = PERIODtimeonAccumulatiPERIODLSBVARhLVARENERGYIB×××(s)s/h3600/Hz50 (77)
The PERIOD50 Hz/PERIOD factor in the preceding VAR equations is the correction factor for the 1/f frequency attenuation of the low-pass filter. The PERIOD50 Hz term refers to the line period at calibration and could represent a frequency other than 50 Hz.
CLKIN FREQUENCY
In this data sheet, the characteristics of the ADE7753 are shown when CLKIN frequency is equal to 3.579545 MHz. However, the ADE7753 is designed to have the same accuracy at any CLKIN frequency within the specified range. If the CLKIN frequency is not 3.579545 MHz, various timing and filter characteristics need to be redefined with the new CLKIN frequency. For example, the cutoff frequencies of all digital filters such as LPF1, LPF2, or HPF1, shift in proportion to the change in CLKIN frequency according to the following equation: MHzFrequencyCLKINFrequencyOriginalFrequencyNew579545.3×= (78)
The change of CLKIN frequency does not affect the timing characteristics of the serial interface because the data transfer is synchronized with serial clock signal (SCLK). But one needs to observe the read/write timing of the serial data transfer—see the ADE7753 timing characteristics in Table 2. Table 11 lists various timing changes that are affected by CLKIN frequency.
Table 11. Frequency Dependencies of the ADE7753 Parameters
Parameter
CLKIN Dependency
Nyquist Frequency for CH 1 and CH 2 ADCs
CLKIN/8
PHCAL Resolution (Seconds per LSB)
4/CLKIN
Active Energy Register Update Rate (Hz)
CLKIN/4
Waveform Sampling Rate (per Second)
WAVSEL 1,0 = 0 0
CLKIN/128
0 1
CLKIN/256
1 0
CLKIN/512
1 1
CLKIN/1024
Maximum ZXTOUT Period
524,288/CLKIN
SUSPENDING ADE7753 FUNCTIONALITY
The analog and the digital circuit can be suspended separately. The analog portion of the ADE7753 can be suspended by setting the ASUSPEND bit (Bit 4) of the mode register to logic high—see the Mode Register (0x9) section. In suspend mode, all wave-form samples from the ADCs are set to 0. The digital circuitry can be halted by stopping the CLKIN input and maintaining a logic high or low on the CLKIN pin. The ADE7753 can be reactivated by restoring the CLKIN input and setting the ASUSPEND bit to logic low.
CHECKSUM REGISTER
The ADE7753 has a checksum register (CHECKSUM[5:0]) to ensure the data bits received in the last serial read operation are not corrupted. The 6-bit checksum register is reset before the first bit (MSB of the register to be read) is put on the DOUT pin. During a serial read operation, when each data bit becomes available on the rising edge of SCLK, the bit is added to the checksum register. In the end of the serial read operation, the content of the checksum register is equal to the sum of all ones in the register previously read. Using the checksum register, the user can determine if an error has occurred during the last read operation. Note that a read to the checksum register also generates a checksum of the checksum register itself. CONTENT OF REGISTER (n-bytes)CHECKSUM REGISTERADDR:0x3E++DOUT02875-0-077
Figure 88. Checksum Register for Serial Interface Read
ADE7753
Rev. C | Page 49 of 60
ADE7753 SERIAL INTERFACE
All ADE7753 functionality is accessible via several on-chip registers—see Figure 89. The contents of these registers can be updated or read using the on-chip serial interface. After power-on or toggling the RESET pin low or a falling edge on CS, the ADE7753 is placed in communications mode. In communica-tions mode, the ADE7753 expects a write to its communications register. The data written to the communications register determines whether the next data transfer operation is a read or a write and also which register is accessed. Therefore all data transfer operations with the ADE7753, whether a read or a write, must begin with a write to the communications register. COMMUNICATIONSREGISTERINOUTINOUTINOUTINOUTINOUTREGISTER 1REGISTER 2REGISTER 3REGISTER n–1REGISTER nREGISTERADDRESSDECODEDINDOUT02875-0-078
Figure 89. Addressing ADE7753 Registers via the Communications Register
The communications register is an 8-bit wide register. The MSB determines whether the next data transfer operation is a read or a write. The six LSBs contain the address of the register to be accessed—see the Communications Register section for a more detailed description.
Figure 90 and Figure 91 show the data transfer sequences for a read and write operation, respectively. On completion of a data transfer (read or write), the ADE7753 once again enters communications mode. A data transfer is complete when the LSB of the ADE7753 register being addressed (for a write or a read) is transferred to or from the ADE7753.
MULTIBYTECOMMUNICATIONS REGISTER WRITEDINSCLKCSDOUTREAD DATAADDRESS0002875-0-079
Figure 90. Reading Data from the ADE7753 via the Serial Interface
COMMUNICATIONS REGISTER WRITEDINSCLKCSADDRESS0102875-0-080MULTIBYTEREAD DATA
Figure 91. Writing Data to the ADE7753 via the Serial Interface
The serial interface of the ADE7753 is made up of four signals: SCLK, DIN, DOUT, and CS. The serial clock for a data transfer is applied at the SCLK logic input. This logic input has a Schmitt-trigger input structure that allows slow rising (and falling) clock edges to be used. All data transfer operations are synchronized to the serial clock. Data is shifted into the ADE7753 at the DIN logic input on the falling edge of SCLK. Data is shifted out of the ADE7753 at the DOUT logic output on a rising edge of SCLK. The CS logic input is the chip-select input. This input is used when multiple devices share the serial bus. A falling edge on CS also resets the serial interface and places the ADE7753 into communications mode. The CS input should be driven low for the entire data transfer operation. Bringing CS high during a data transfer operation aborts the transfer and places the serial bus in a high impedance state. The CS logic input can be tied low if the ADE7753 is the only device on the serial bus. However, with CS tied low, all initiated data transfer operations must be fully completed, i.e., the LSB of each register must be transferred because there is no other way of bringing the ADE7753 back into communications mode without resetting the entire device by using RESET.
ADE7753
Rev. C | Page 50 of 60
ADE7753 Serial Write Operation
The serial write sequence takes place as follows. With the ADE7753 in communications mode (i.e., the CS input logic low), a write to the communications register first takes place. The MSB of this byte transfer is a 1, indicating that the data transfer operation is a write. The LSBs of this byte contain the address of the register to be written to. The ADE7753 starts shifting in the register data on the next falling edge of SCLK. All remaining bits of register data are shifted in on the falling edge of subsequent SCLK pulses—see . As explained earlier, the data write is initiated by a write to the communications register followed by the data. During a data write operation to the ADE7753, data is transferred to all on-chip registers one byte at a time. After a byte is transferred into the serial port, there is a finite time before it is transferred to one of the ADE7753 on-chip registers. Although another byte transfer to the serial port can start while the previous byte is being transferred to an on-chip register, this second byte transfer Figure 92
should not finish until at least 4 μs after the end of the previous byte transfer. This functionality is expressed in the timing specification t6—see Figure 92. If a write operation is aborted during a byte transfer (CS brought high), then that byte cannot be written to the destination register.
Destination registers can be up to 3 bytes wide—see the ADE7753 Register Description tables. Therefore the first byte shifted into the serial port at DIN is transferred to the MSB (most significant byte) of the destination register. If, for example, the addressed register is 12 bits wide, a 2-byte data transfer must take place. The data is always assumed to be right justified, therefore in this case, the four MSBs of the first byte would be ignored and the four LSBs of the first byte written to the ADE7753 would be the four MSBs of the 12-bit word. Figure 93 illustrates this example.
DINSCLKCSt2t3t1t4t5t7t6t8COMMAND BYTEMOST SIGNIFICANT BYTELEAST SIGNIFICANT BYTE10A4A5A3A2A1A0DB7DB0DB7DB0t702875-0-081
Figure 92. Serial Interface Write Timing
SCLKDINXXXXDB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0MOST SIGNIFICANT BYTELEAST SIGNIFICANT BYTE02875-0-082
Figure 93. 12-Bit Serial Write Operation
ADE7753
Rev. C | Page 51 of 60
ADE7753 Serial Read Operation
During a data read operation from the ADE7753, data is shifted out at the DOUT logic output on the rising edge of SCLK. As is the case with the data write operation, a data read must be preceded with a write to the communications register.
With the ADE7753 in communications mode (i.e., CS logic low), an 8-bit write to the communications register first takes place. The MSB of this byte transfer is a 0, indicating that the next data transfer operation is a read. The LSBs of this byte contain the address of the register that is to be read. The ADE7753 starts shifting out of the register data on the next rising edge of SCLK—see . At this point, the DOUT logic output leaves its high impedance state and starts driving the data bus. All remaining bits of register data are shifted out on subsequent SCLK rising edges. The serial interface also enters communications mode again as soon as the read has been completed. At this point, the DOUT logic output enters a high impedance state on the falling edge of the last SCLK pulse. The read operation can be aborted by bringing the Figure 94CS logic input high before the data transfer is complete. The DOUT output enters a high impedance state on the rising edge of CS.
When an ADE7753 register is addressed for a read operation, the entire contents of that register are transferred to the serial port. This allows the ADE7753 to modify its on-chip registers without the risk of corrupting data during a multibyte transfer.
Note that when a read operation follows a write operation, the read command (i.e., write to communications register) should not happen for at least 4 μs after the end of the write operation. If the read command is sent within 4 μs of the write operation, the last byte of the write operation could be lost. This timing constraint is given as timing specification t9.
SCLKCSt1t10t1300A4A5A3A2A1A0DB0DB7DB0DB7DINDOUTt11t11t12COMMAND BYTEMOST SIGNIFICANT BYTELEAST SIGNIFICANT BYTEt902875-0-083
Figure 94. Serial Interface Read Timing
ADE7753
Rev. C | Page 52 of 60
ADE7753 REGISTERS
Table 12. Summary of Registers by Address
Address
Name
R/W
No. Bits
Default
Type1
Description
0x01
WAVEFORM
R
24
0x0
S
Waveform Register. This read-only register contains the sampled waveform data from either Channel 1, Channel 2, or the active power signal. The data source and the length of the waveform registers are selected by data Bits 14 and 13 in the mode register—see the Channel 1 Sampling and Channel 2 Sampling sections.
0x02
AENERGY
R
24
0x0
S
Active Energy Register. Active power is accumulated (integrated) over time in this 24-bit, read-only register—see the Energy Calculation section.
0x03
RAENERGY
R
24
0x0
S
Same as the active energy register except that the register is reset to 0 following a read operation.
0x04
LAENERGY
R
24
0x0
S
Line Accumulation Active Energy Register. The instantaneous active power is accumulated in this read-only register over the LINECYC number of half line cycles.
0x05
VAENERGY
R
24
0x0
U
Apparent Energy Register. Apparent power is accumulated over time in this read-only register.
0x06
RVAENERGY
R
24
0x0
U
Same as the VAENERGY register except that the register is reset to 0 following a read operation.
0x07
LVAENERGY
R
24
0x0
U
Line Accumulation Apparent Energy Register. The instantaneous real power is accumulated in this read-only register over the LINECYC number of half line cycles.
0x08
LVARENERGY
R
24
0x0
S
Line Accumulation Reactive Energy Register. The instantaneous reactive power is accumulated in this read-only register over the LINECYC number of half line cycles.
0x09
MODE
R/W
16
0x000C
U
Mode Register. This is a 16-bit register through which most of the ADE7753 functionality is accessed. Signal sample rates, filter enabling, and calibration modes are selected by writing to this register. The contents can be read at any time—see the Mode Register (0x9) section.
0x0A
IRQEN
R/W
16
0x40
U
Interrupt Enable Register. ADE7753 interrupts can be deactivated at any time by setting the corresponding bit in this 16- bit enable register to Logic 0. The status register continues to register an interrupt event even if disabled. However, the IRQ output is not activated—see the section. ADE7753 Interrupts
0x0B
STATUS
R
16
0x0
U
Interrupt Status Register. This is an 16-bit read-only register. The status register contains information regarding the source of ADE7753 interrupts—the see ADE7753 Interrupts section.
0x0C
RSTSTATUS
R
16
0x0
U
Same as the interrupt status register except that the register contents are reset to 0 (all flags cleared) after a read operation.
0x0D
CH1OS
R/W
8
0x00
S*
Channel 1 Offset Adjust. Bit 6 is not used. Writing to Bits 0 to 5 allows offsets on Channel 1 to be removed—see the Analog Inputs and CH1OS Register (0x0D) sections. Writing a Logic 1 to the MSB of this register enables the digital integrator on Channel 1, a Logic 0 disables the integrator. The default value of this bit is 0.
0x0E
CH2OS
R/W
8
0x0
S*
Channel 2 Offset Adjust. Bits 6 and 7 are not used. Writing to Bits 0 to 5 of this register allows any offsets on Channel 2 to be removed—see the Analog Inputs section. Note that the CH2OS register is inverted. To apply a positive offset, a negative number is written to this register.
0x0F
GAIN
R/W
8
0x0
U
PGA Gain Adjust. This 8-bit register is used to adjust the gain selection for the PGA in Channels 1 and 2—see the Analog Inputs section.
0x10
PHCAL
R/W
6
0x0D
S
Phase Calibration Register. The phase relationship between Channel 1 and 2 can be adjusted by writing to this 6-bit register. The valid content of this twos compliment register is between 0x1D to 0x21. At a line frequency of 60 Hz, this is a range from –2.06° to +0.7°—see the Phase Compensation section.
0x11
APOS
R/W
16
0x0
S
Active Power Offset Correction. This 16-bit register allows small offsets in the active power calculation to be removed—see the Active Power Calculation section.
ADE7753
Rev. C | Page 53 of 60
Address Name R/W No. Bits Default
Type1
Description
0x12
WGAIN
R/W
12
0x0
S
Power Gain Adjust. This is a 12-bit register. The active power calculation can be calibrated by writing to this register. The calibration range is ±50% of the nominal full-scale active power. The resolution of the gain adjust is 0.0244%/LSB —see the Calibrating an Energy Meter Based on the ADE7753 section.
0x13
WDIV
R/W
8
0x0
U
Active Energy Divider Register. The internal active energy register is divided by the value of this register before being stored in the AENERGY register.
0x14
CFNUM
R/W
12
0x3F
U
CF Frequency Divider Numerator Register. The output frequency on the CF pin is adjusted by writing to this 12-bit read/write register—see the Energy-to-Frequency Conversion section.
0x15
CFDEN
R/W
12
0x3F
U
CF Frequency Divider Denominator Register. The output frequency on the CF pin is adjusted by writing to this 12-bit read/write register—see the Energy-to-Frequency Conversion section.
0x16
IRMS
R
24
0x0
U
Channel 1 RMS Value (Current Channel).
0x17
VRMS
R
24
0x0
U
Channel 2 RMS Value (Voltage Channel).
0x18
IRMSOS
R/W
12
0x0
S
Channel 1 RMS Offset Correction Register.
0x19
VRMSOS
R/W
12
0x0
S
Channel 2 RMS Offset Correction Register.
0x1A
VAGAIN
R/W
12
0x0
S
Apparent Gain Register. Apparent power calculation can be calibrated by writing to this register. The calibration range is 50% of the nominal full-scale real power. The resolution of the gain adjust is 0.02444%/LSB.
0x1B
VADIV
R/W
8
0x0
U
Apparent Energy Divider Register. The internal apparent energy register is divided by the value of this register before being stored in the VAENERGY register.
0x1C
LINECYC
R/W
16
0xFFFF
U
Line Cycle Energy Accumulation Mode Line-Cycle Register. This 16-bit register is used during line cycle energy accumulation mode to set the number of half line cycles for energy accumulation—see the Line Cycle Energy Accumulation Mode section.
0x1D
ZXTOUT
R/W
12
0xFFF
U
Zero-Crossing Timeout. If no zero crossings are detected on Channel 2 within a time period specified by this 12-bit register, the interrupt request line (IRQ) is activated—see the section. Zero-Crossing Detection
0x1E
SAGCYC
R/W
8
0xFF
U
Sag Line Cycle Register. This 8-bit register specifies the number of consecutive line cycles the signal on Channel 2 must be below SAGLVL before the SAG output is activated—see the Line Voltage Sag Detection section.
0x1F
SAGLVL
R/W
8
0x0
U
Sag Voltage Level. An 8-bit write to this register determines at what peak signal level on Channel 2 the SAG pin becomes active. The signal must remain low for the number of cycles specified in the SAGCYC register before the SAG pin is activated—see the section. Line Voltage Sag Detection
0x20
IPKLVL
R/W
8
0xFF
U
Channel 1 Peak Level Threshold (Current Channel). This register sets the level of the current peak detection. If the Channel 1 input exceeds this level, the PKI flag in the status register is set.
0x21
VPKLVL
R/W
8
0xFF
U
Channel 2 Peak Level Threshold (Voltage Channel). This register sets the level of the voltage peak detection. If the Channel 2 input exceeds this level, the PKV flag in the status register is set.
0x22
IPEAK
R
24
0x0
U
Channel 1 Peak Register. The maximum input value of the current channel since the last read of the register is stored in this register.
0x23
RSTIPEAK
R
24
0x0
U
Same as Channel 1 Peak Register except that the register contents are reset to 0 after read.
0x24
VPEAK
R
24
0x0
U
Channel 2 Peak Register. The maximum input value of the voltage channel since the last read of the register is stored in this register.
0x25
RSTVPEAK
R
24
0x0
U
Same as Channel 2 Peak Register except that the register contents are reset to 0 after a read.
0x26
TEMP
R
8
0x0
S
Temperature Register. This is an 8-bit register which contains the result of the latest temperature conversion—see the Temperature Measurement section.
ADE7753
Rev. C | Page 54 of 60
Address Name R/W No. Bits Default
Type1
Description
0x27
PERIOD
R
16
0x0
U
Period of the Channel 2 (Voltage Channel) Input Estimated by Zero-Crossing Processing. The MSB of this register is always zero.
0x28–0x3C
Reserved.
0x3D
TMODE
R/W
8
–
U
Test Mode Register.
0x3E
CHKSUM
R
6
0x0
U
Checksum Register. This 6-bit read-only register is equal to the sum of all the ones in the previous read—see the ADE7753 Serial Read Operation section.
0x3F
DIEREV
R
8
–
U
Die Revision Register. This 8-bit read-only register contains the revision number of the silicon.
1 Type decoder: U = unsigned, S = signed by twos complement method, and S* = signed by sign magnitude method.
ADE7753
Rev. C | Page 55 of 60
ADE7753 REGISTER DESCRIPTIONS
All ADE7753 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications register and then transferring the register data. A full description of the serial interface protocol is given in the ADE7753 Serial Interface section.
COMMUNICATIONS REGISTER
The communications register is an 8-bit, write-only register which controls the serial data transfer between the ADE7753 and the host processor. All data transfer operations must begin with a write to the communications register. The data written to the communications register determines whether the next operation is a read or a write and which register is being accessed. Table 13 outlines the bit designations for the communications register.
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W/R
0
A5
A4
A3
A2
A1
A0
Table 13. Communications Register
Bit Location
Bit Mnemonic
Description
0 to 5
A0 to A5
The six LSBs of the communications register specify the register for the data transfer operation. Table 12 lists the address of each ADE7753 on-chip register.
6
RESERVED
This bit is unused and should be set to 0.
7
W/R
When this bit is a Logic 1, the data transfer operation immediately following the write to the communications register is interpreted as a write to the ADE7753.
When this bit is a Logic 0, the data transfer operation immediately following the write to the communications register is interpreted as a read operation.
MODE REGISTER (0x09)
The ADE7753 functionality is configured by writing to the mode register. Table 14 describes the functionality of each bit in the register.
Table 14. Mode Register
Bit Location
Bit Mnemonic
Default Value Description
0
DISHPF
0
HPF (high-pass filter) in Channel 1 is disabled when this bit is set.
1
DISLPF2
0
LPF (low-pass filter) after the multiplier (LPF2) is disabled when this bit is set.
2
DISCF
1
Frequency output CF is disabled when this bit is set.
3
DISSAG
1
Line voltage sag detection is disabled when this bit is set.
4
ASUSPEND
0
By setting this bit to Logic 1, both ADE7753 A/D converters can be turned off. In normal operation, this bit should be left at Logic 0. All digital functionality can be stopped by suspending the clock signal at CLKIN pin.
5
TEMPSEL
0
Temperature conversion starts when this bit is set to 1. This bit is automatically reset to 0 when the temperature conversion is finished.
6
SWRST
0
Software Chip Reset. A data transfer should not take place to the ADE7753 for at least 18 μs after a software reset.
7
CYCMODE
0
Setting this bit to Logic 1 places the chip into line cycle energy accumulation mode.
8
DISCH1
0
ADC 1 (Channel 1) inputs are internally shorted together.
9
DISCH2
0
ADC 2 (Channel 2) inputs are internally shorted together.
10
SWAP
0
By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and the analog inputs V1P and V1N are connected to ADC 2.
12, 11
DTRT1, 0
00
These bits are used to select the waveform register update rate.
DTRT 1
DTRT0
Update Rate
0
0
27.9 kSPS (CLKIN/128)
0
1
14 kSPS (CLKIN/256)
1
0
7 kSPS (CLKIN/512)
1
1
3.5 kSPS (CLKIN/1024)
ADE7753
Rev. C | Page 56 of 60
Bit Location Bit Mnemonic
Default Value Description
14, 13
WAVSEL1, 0
00
These bits are used to select the source of the sampled data for the waveform register.
WAVSEL1, 0
Length
Source
0
0
24 bits active power signal (output of LPF2)
0
1
Reserved
1
0
24 bits Channel 1
1
1
24 bits Channel 2
15
POAM
0
Writing Logic 1 to this bit allows only positive active power to be accumulated in the ADE7753.
Figure 95. Mode Register
ADE7753
Rev. C | Page 57 of 60
INTERRUPT STATUS REGISTER (0x0B), RESET INTERRUPT STATUS REGISTER (0x0C), INTERRUPT ENABLE REGISTER (0x0A)
The status register is used by the MCU to determine the source of an interrupt request (IRQ). When an interrupt event occurs in the ADE7753, the corresponding flag in the interrupt status register is set to logic high. If the enable bit for this flag is Logic 1 in the interrupt enable register, the IRQ logic output goes active low. When the MCU services the interrupt, it must first carry out a read from the interrupt status register to determine the source of the interrupt.
Table 15. Interrupt Status Register, Reset Interrupt Status Register, and Interrupt Enable Register
Bit Location
Interrupt Flag
Description
0
AEHF
Indicates that an interrupt occurred because the active energy register, AENERGY, is more than half full.
1
SAG
Indicates that an interrupt was caused by a SAG on the line voltage.
2
CYCEND
Indicates the end of energy accumulation over an integer number of half line cycles as defined by the content of the LINECYC register—see the Line Cycle Energy Accumulation Mode section.
3
WSMP
Indicates that new data is present in the waveform register.
4
ZX
This status bit is set to Logic 0 on the rising and falling edge of the the voltage waveform. See the Zero-Crossing Detection section.
5
TEMP
Indicates that a temperature conversion result is available in the temperature register.
6
RESET
Indicates the end of a reset (for both software or hardware reset). The corresponding enable bit has no function in the interrupt enable register, i.e., this status bit is set at the end of a reset, but it cannot be enabled to cause an interrupt.
7
AEOF
Indicates that the active energy register has overflowed.
8
PKV
Indicates that waveform sample from Channel 2 has exceeded the VPKLVL value.
9
PKI
Indicates that waveform sample from Channel 1 has exceeded the IPKLVL value.
A
VAEHF
Indicates that an interrupt occurred because the active energy register, VAENERGY, is more than half full.
B
VAEOF
Indicates that the apparent energy register has overflowed.
C
ZXTO
Indicates that an interrupt was caused by a missing zero crossing on the line voltage for the specified number of line cycles—see the Zero-Crossing Timeout section.
D
PPOS
Indicates that the power has gone from negative to positive.
E
PNEG
Indicates that the power has gone from positive to negative.
F
RESERVED
Reserved.
Figure 96. Interrupt Status/Interrupt Enable Register
ADE7753
Rev. C | Page 58 of 60
CH1OS REGISTER (0x0D)
The CH1OS register is an 8-bit, read/write enabled register. The MSB of this register is used to switch on/off the digital integrator in Channel 1, and Bits 0 to 5 indicates the amount of the offset correction in Channel 1. Table 16 summarizes the function of this register.
Table 16. CH1OS Register
Bit Location
Bit Mnemonic
Description
0 to 5
OFFSET
The six LSBs of the CH1OS register control the amount of dc offset correction in Channel 1 ADC. The 6-bit offset correction is sign and magnitude coded. Bits 0 to 4 indicate the magnitude of the offset correction. Bit 5 shows the sign of the offset correction. A 0 in Bit 5 means the offset correction is positive and a 1 indicates the offset correction is negative.
6
Not Used
This bit is unused.
7
INTEGRATOR
This bit is used to activate the digital integrator on Channel 1. The digital integrator is switched on by setting this bit. This bit is set to be 0 on default.
DIGITAL INTEGRATOR SELECTION1 = ENABLE0 = DISABLENOT USED0000000076543210ADDR: 0x0DSIGN AND MAGNITUDE CODEDOFFSET CORRECTION BITS02875-0-086
Figure 97. Channel 1 Offset Register
ADE7753
Rev. C | Page 59 of 60
OUTLINE DIMENSIONS
COMPLIANTTO JEDEC STANDARDS MO-150-AE060106-A20111017.507.206.908.207.807.405.605.305.00SEATINGPLANE0.05 MIN0.65 BSC2.00 MAX0.380.22COPLANARITY0.101.851.751.650.250.090.950.750.558°4°0°
Figure 98. 20-Lead Shrink Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADE7753ARS
−40°C to +85°C
20-Lead Shrink Small Outline Package [SSOP]
RS-20
ADE7753ARSRL
−40°C to +85°C
20-Lead Shrink Small Outline Package [SSOP]
RS-20
ADE7753ARSZ
−40°C to +85°C
20-Lead Shrink Small Outline Package [SSOP]
RS-20
ADE7753ARSZRL
−40°C to +85°C
20-Lead Shrink Small Outline Package [SSOP]
RS-20
EVAL-ADE7753ZEB
Evaluation Board
1 Z = RoHS Compliant Part.
ADE7753
Rev. C | Page 60 of 60
NOTES
Pin Programmable,
Precision Voltage Reference
Data Sheet AD584
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1978–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Four programmable output voltages
10.000 V, 7.500 V, 5.000 V, and 2.500 V
Laser-trimmed to high accuracies
No external components required
Trimmed temperature coefficient
15 ppm/°C maximum, 0°C to 70°C (AD584K)
15 ppm/°C maximum, −55°C to +125°C (AD584T)
Zero output strobe terminal provided
2-terminal negative reference: capability (5 V and above)
Output sources or sinks current
Low quiescent current: 1.0 mA maximum
10 mA current output capability
MIL-STD-883 compliant versions available
PIN CONFIGURATIONS
Figure 1. 8-Pin TO-99
Figure 2. 8-Lead PDIP
GENERAL DESCRIPTION
The AD584 is an 8-terminal precision voltage reference offering pin programmable selection of four popular output voltages: 10.000 V, 7.500 V, 5.000 V and 2.500 V. Other output voltages, above, below, or between the four standard outputs, are available by the addition of external resistors. The input voltage can vary between 4.5 V and 30 V.
Laser wafer trimming (LWT) is used to adjust the pin programmable output levels and temperature coefficients, resulting in the most flexible high precision voltage reference available in monolithic form.
In addition to the programmable output voltages, the AD584 offers a unique strobe terminal that permits the device to be turned on or off. When the AD584 is used as a power supply reference, the supply can be switched off with a single, low power signal. In the off state, the current drained by the AD584 is reduced to approximately 100 μA. In the on state, the total supply current is typically 750 μA, including the output buffer amplifier.
The AD584 is recommended for use as a reference for 8-, 10-, or 12-bit digital-to-analog converters (DACs) that require an external precision reference. In addition, the device is ideal for analog-to-digital converters (ADCs) of up to 14-bit accuracy, either successive approximation or integrating designs, and in general, it can offer better performance than that provided by standard self-contained references.
The AD584J and AD584K are specified for operation from 0°C to +70°C, and the AD584S and AD584T are specified for the −55°C to +125°C range. All grades are packaged in a hermetically sealed, eight-terminal TO-99 metal can, and the AD584J and AD584K are also available in an 8-lead PDIP.
PRODUCT HIGHLIGHTS
1. The flexibility of the AD584 eliminates the need to design-in and inventory several different voltage references. Furthermore, one AD584 can serve as several references simultaneously when buffered properly.
2. Laser trimming of both initial accuracy and temperature coefficient results in very low errors overtemperature without the use of external components.
3. The AD584 can be operated in a 2-terminal Zener mode at a 5 V output and above. By connecting the input and the output, the AD584 can be used in this Zener configuration as a negative reference.
4. The output of the AD584 is configured to sink or source currents. This means that small reverse currents can be tolerated in circuits using the AD584 without damage to the reference and without disturbing the output voltage (10 V, 7.5 V, and 5 V outputs).
5. The AD584 is available in versions compliant with MIL-STD-883. Refer to the Analog Devices current AD584/883B data sheet for detailed specifications. This can be found under the Additional Data Sheets section of the AD584 product page.
1267358V+TAB4AD584TOP VIEW(Not to Scale)COMMONSTROBEVBGCAP2.5V5.0V10.0V00527-00110.0V15.0V22.5V3COMMON4V+8CAP7VBG6STROBE5AD584TOP VIEW(Not to Scale)00527-002
AD584 Data Sheet
Rev. C | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configurations ........................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Theory of Operation ........................................................................ 6
Applying the AD584 .................................................................... 6
Performance over Temperature .................................................. 7
Output Current Characteristics ...................................................7
Dynamic Performance ..................................................................7
Noise Filtering ...............................................................................8
Using the Strobe Terminal ...........................................................8
Percision High Current Supply....................................................8
The AD584 as a Current Limiter.................................................9
Negative Reference Voltages from an AD584 ...............................9
10 V Reference with Multiplying CMOS DACs or ADCs .......9
Precision DAC Reference .......................................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 12
REVISION HISTORY
5/12—Rev. B to Rev. C
Deleted AD584L ................................................................. Universal
Changes to Features Section, General Description Section and Product Highlights Section ............................................................. 1
Deleted Metalization Photograph .................................................. 4
Changes to 10 V Reference with Multiplying CMOS DACs or ADCs Section .................................................................................... 9
Changes to Precision DAC Reference Section and Figure 19... 10
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 12
7/01—Rev. A to Rev. B
Data Sheet AD584
Rev. C | Page 3 of 12
SPECIFICATIONS
VIN = 15 V and 25°C, unless otherwise noted.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed; although, only those shown in boldface are tested on all production units.
Table 1.
AD584J
AD584K
Model
Min
Typ
Max
Min
Typ
Max
Unit
OUTPUT VOLTAGE TOLERANCE
Maximum Error at Pin 1 for Nominal
Outputs of
10.000 V
±30
±10
mV
7.500 V
±20
±8
mV
5.000 V
±15
±6
mV
2.500 V
±7.5
±3.5
mV
OUTPUT VOLTAGE CHANGE
Maximum Deviation from 25°C Value, TMIN to TMAX1
10.000 V, 7.500 V, and 5.000 V Outputs
30
15
ppm/°C
2.500 V Output
30
15
ppm/°C
Differential Temperature Coefficients Between Outputs
5
3
ppm/°C
QUIESCENT CURRENT
0.75
1.0
0.75
1.0
mA
Temperature Variation
1.5
1.5
μA/°C
TURN-ON SETTLING TIME TO 0.1%
200
200
μs
NOISE (0.1 Hz TO 10 Hz)
50
50
μV p-p
LONG-TERM STABILITY
25
25
ppm/1000 Hrs
SHORT-CIRCUIT CURRENT
30
30
mA
LINE REGULATION (NO LOAD)
15 V ≤ VIN ≤ 30 V
0.002
0.002
%/V
(VOUT + 2.5 V) ≤ VIN ≤ 15 V
0.005
0.005
%/V
LOAD REGULATION
0 ≤ IOUT ≤ 5 mA, All Outputs
20
50
20
50
ppm/mA
OUTPUT CURRENT
VIN ≥ VOUT + 2.5 V
Source at 25°C
10
10
mA
Source TMIN to TMAX
5
5
mA
Sink TMIN to TMAX
5
5
mA
TEMPERATURE RANGE
Operating
0
70
0
70
°C
Storage
−65
+175
−65
+175
°C
PACKAGE OPTION
8-Pin Metal Header (TO-99, H-08)
AD584JH
AD584KH
8-Lead Plastic Dual In-Line Package (PDIP, N-8)
AD584JN
AD584KN
1 Calculated as average over the operating temperature range.
AD584 Data Sheet
Rev. C | Page 4 of 12
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed; although, only those shown in boldface are tested on all production units.
Table 2.
AD584S
AD584T
Model
Min
Typ
Max
Min
Typ
Max
Unit
OUTPUT VOLTAGE TOLERANCE
Maximum Error at Pin 1 for Nominal
Outputs of
10.000 V
±30
±10
mV
7.500 V
±20
±8
mV
5.000 V
±15
±6
mV
2.500 V
±7.5
±3.5
mV
OUTPUT VOLTAGE CHANGE
Maximum Deviation from 25°C Value, TMIN to TMAX1
10.000 V, 7.500 V, and 5.000 V Outputs
30
15
ppm/°C
2.500 V Output
30
20
ppm/°C
Differential Temperature Coefficients Between Outputs
5
3
ppm/°C
QUIESCENT CURRENT
0.75
1.0
0.75
1.0
mA
Temperature Variation
1.5
1.5
μA/°C
TURN-ON SETTLING TIME TO 0.1%
200
200
μs
NOISE (0.1 Hz TO 10 Hz)
50
50
μV p-p
LONG-TERM STABILITY
25
25
ppm/1000 Hrs
SHORT-CIRCUIT CURRENT
30
30
mA
LINE REGULATION (NO LOAD)
15 V ≤ VIN ≤ 30 V
0.002
0.002
%/V
(VOUT + 2.5 V) ≤ VIN ≤ 15 V
0.005
0.005
%/V
LOAD REGULATION
0 ≤ IOUT ≤ 5 mA, All Outputs
20
50
20
50
ppm/mA
OUTPUT CURRENT
VIN ≥ VOUT + 2.5 V
Source at 25°C
10
10
mA
Source TMIN to TMAX
5
5
mA
Sink TMIN to TMAX
5
5
mA
TEMPERATURE RANGE
Operating
−55
+125
−55
+125
°C
Storage
−65
+175
−65
+175
°C
PACKAGE OPTION
8-Pin Metal Header (TO-99, H-08)
AD584SH
AD584TH
1 Calculated as average over the operating temperature range.
Data Sheet AD584
Rev. C | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Input Voltage VIN to Ground
40 V
Power Dissipation at 25°C
600 mW
Operating Junction Temperature Range
−55°C to +125°C
Lead Temperature (Soldering 10 sec)
300°C
Thermal Resistance
Junction-to-Ambient (H-08A)
150°C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
AD584 Data Sheet
Rev. C | Page 6 of 12
THEORY OF OPERATION
APPLYING THE AD584
With power applied to Pin 8 and Pin 4 and all other pins open, the AD584 produces a buffered nominal 10.0 V output between Pin 1 and Pin 4 (see Figure 3). The stabilized output voltage can be reduced to 7.5 V, 5.0 V, or 2.5 V by connecting the programming pins as shown in Table 4.
Table 4.
Output Voltage (V)
Pin Programming
7.5
Join the 2.5 V (Pin 3) and 5.0 V (Pin 2) pins.
5.0
Connect the 5.0 V pin (Pin 2) to the output pin (Pin 1).
2.5
Connect the 2.5 V pin (Pin 3) to the output pin (Pin 1).
The options shown in Table 4 are available without the use of any additional components. Multiple outputs using only one AD584 can be provided by buffering each voltage programming pin with a unity-gain, noninverting op amp.
Figure 3. Variable Output Options
The AD584 can also be programmed over a wide range of output voltages, including voltages greater than 10 V, by the addition of one or more external resistors. Figure 3 illustrates the general adjustment procedure, with approximate values given for the internal resistors of the AD584. The AD584 may be modeled as an op amp with a noninverting feedback connection, driven by a high stability 1.215 V band gap reference (see Figure 5 for schematic).
When the feedback ratio is adjusted with external resistors, the output amplifier can be made to multiply the reference voltage by almost any convenient amount, making popular outputs of 10.24 V, 5.12 V, 2.56 V, or 6.3 V easy to obtain. The most general adjustment (which gives the greatest range and poorest resolution) uses R1 and R2 alone (see Figure 3). As R1 is adjusted to its upper limit, the 2.5V pin (Pin 3) is connected to the output, which reduces to 2.5 V. As R1 is adjusted to its lower limit, the output voltage rises to a value limited by R2. For example, if R2 is approximately 6 kΩ, the upper limit of the output range is approximately 20 V, even for the large values of R1. Do not omit R2; choose its value to limit the output to a value that can be tolerated by the load circuits. If R2 is zero, adjusting R1 to its lower limit results in a loss of control over the output voltage. When precision voltages are set at levels other than the standard outputs, account for the 20% absolute tolerance in the internal resistor ladder.
Alternatively, the output voltage can be raised by loading the 2.5 V tap with R3 alone. The output voltage can be lowered by connecting R4 alone. Either of these resistors can be a fixed resistor selected by test or an adjustable resistor. In all cases, the resistors should have a low temperature coefficient to match the AD584 internal resistors, which have a negative temperature coefficient less than 60 ppm/°C. If both R3 and R4 are used, these resistors should have matching temperature coefficients.
When only small adjustments or trims are required, the circuit in Figure 4 offers better resolution over a limited trim range. The circuit can be programmed to 5.0 V, 7.5 V, or 10 V, and it can be adjusted by means of R1 over a range of about ±200 mV. To trim the 2.5 V output option, R2 (see Figure 4) can be reconnected to the band gap reference (Pin 6). In this configuration, limit the adjustment to ±100 mV to avoid affecting the performance of the AD584.
Figure 4. Output Trimming
Figure 5. Schematic Diagram
AD584VSUPPLYVOUT812361.215V10V5V*2.5V12kΩ6kΩVBGR44COMMONR1R2R36kΩ24kΩ*THE 2.5V TAP IS USED INTERNALLY AS A BIAS POINTAND SHOULD NOT BE CHANGED BY MORE THAN 100mVIN ANY TRIM CONFIGURATION.00527-004AD584VOUT110.0V8V+4COMMON25.0V32.5V6VBGR110kΩR2300kΩ00527-005R38R40Q10Q16Q13Q11Q14Q12Q15SUBCAPR41R42R34R37R35R30R31R36Q6Q8Q5C51C52C50Q20Q7STROBEV+OUT 10V5V TAP2.5V TAPVBGV–R32R33Q3Q4Q2Q1R3900527-006
Data Sheet AD584
Rev. C | Page 7 of 12
PERFORMANCE OVER TEMPERATURE
Each AD584 is tested at three temperatures over the −55°C to +125°C range to ensure that each device falls within the maximum error band (see Figure 6) specified for a particular grade (that is, S and T grades); three-point measurement guarantees performance within the error band from 0°C to 70°C (that is, J and K grades). The error band guaranteed for the AD584 is the maximum deviation from the initial value at 25°C. Thus, given the grade of the AD584, the maximum total error from the initial tolerance plus the temperature variation can easily be determined. For example, for the AD584T, the initial tolerance is ±10 mV, and the error band is ±15 mV. Therefore, the unit is guaranteed to be 10.000 V ± 25 mV from −55°C to +125°C.
Figure 6. Typical Temperature Characteristic
OUTPUT CURRENT CHARACTERISTICS
The AD584 has the capability to either source or sink current and provide good load regulation in either direction; although, it has better characteristics in the source mode (positive current into the load). The circuit is protected for shorts to either positive supply or ground. Figure 7 shows the output voltage vs. the output current characteristics of the device. Source current is displayed as negative current in the figure, and sink current is displayed as positive current. The short-circuit current (that is, 0 V output) is about 28 mA; however, when shorted to 15 V, the sink current goes to approximately 20 mA.
Figure 7. Output Voltage vs. Output Current (Sink and Source)
DYNAMIC PERFORMANCE
Many low power instrument manufacturers are becoming increasingly concerned with the turn-on characteristics of the components being used in their systems. Fast turn-on components often enable the end user to keep power off when not needed and yet respond quickly when the power is turned on. Figure 8 displays the turn-on characteristic of the AD584. Figure 8 is generated from cold-start operation and represents the true turn-on waveform after an extended period with the supplies off. Figure 8 shows both the coarse and fine transient characteristics of the device; the total settling time to within ±10 mV is about 180 μs, and there is no long thermal tail appearing after the point.
Figure 8. Output Settling Characteristic
10.00510.0009.995–5502570125VOUT (
V)TEMPERATURE (°C)00527-007OUTPUT CURRENT (
mA)OUTPUT VOLTAGE (V)05101520–5–10–15SINKSOURCE–2014121086420+VS = 15VTA = 25°C00527-008SETTLING TIME (μs)10015020025050010.03V10.02V12V11V10V20V10V0V10.01V10.00VOUTPUTOUTPUTPOWERSUPPLYINPUT00527-009
AD584 Data Sheet
Rev. C | Page 8 of 12
NOISE FILTERING
The bandwidth of the output amplifier in the AD584 can be reduced to filter output noise. A capacitor ranging between 0.01 μF and 0.1 μF connected between the CAP and VBG terminals further reduces the wideband and feedthrough noise in the output of the AD584, as shown in Figure 9 and Figure 10. However, this tends to increase the turn-on settling time of the device; therefore, allow for ample warm-up time.
Figure 9. Additional Noise Filtering with an External Capacitor
Figure 10. Spectral Noise Density and Total RMS Noise vs. Frequency
USING THE STROBE TERMINAL
The AD584 has a strobe input that can be used to zero the output. This unique feature permits a variety of new applications in signal and power conditioning circuits.
Figure 11 illustrates the strobe connection. A simple NPN switch can be used to translate a TTL logic signal into a strobe of the output. The AD584 operates normally when there is no current drawn from Pin 5. Bringing this terminal low, to less than 200 mV, allows the output voltage to go to zero. In this mode, the AD584 is not required to source or sink current (unless a 0.7 V residual output is permissible). If the AD584 is required to sink a transient current while strobe is off, limit the strobe terminal input current by a 100 Ω resistor, as shown in Figure 11.
Figure 11. Use of the Strobe Terminal
The strobe terminal tolerates up to 5 μA leakage, and its driver should be capable of sinking 500 μA continuous. A low leakage, open collector gate can be used to drive the strobe terminal directly, provided the gate can withstand the AD584 output voltage plus 1 V.
PERCISION HIGH CURRENT SUPPLY
The AD584 can be easily connected to a power PNP or power PNP Darlington device to provide much greater output current capability. The circuit shown in Figure 12 delivers a precision 10 V output with up to 4 A supplied to the load. If the load has a significant capacitive component, the 0.1 μF capacitor is required. If the load is purely resistive, improved high frequency, supply rejection results from removing the capacitor.
Figure 12. High Current Precision Supply
AD584110.0V8SUPPLYV+4COMMON7CAP6VBG0.01μF*TO0.1μF*INCREASES TURN-ON TIME00527-0101000100110101001k10k100k1MFREQUENCY (Hz)NOISE SPECTRAL DENSITY (nV/ Hz)TOTAL NOISE (μV rms) UP TOSPECIFIED FREQUENCYNO CAPNO CAP100pF1000pF0.01μF00527-011AD584110.0V238V+4COMMON5STROBE10kΩ20kΩ2N2222100ΩLOGICINPUTHI = OFFLO = ON00527-012AD584110.0VVOUT10V @ 4A8V+4COMMON470Ω0.1μFVIN ≥ 15V2N604000527-013
Data Sheet AD584
Rev. C | Page 9 of 12
The AD584 can also use an NPN or NPN Darlington transistor to boost its output current. Simply connect the 10 V output terminal of the AD584 to the base of the NPN booster and take the output from the booster emitter, as shown in Figure 13. The 5.0V pin or the 2.5V pin must connect to the actual output in this configuration. Variable or adjustable outputs (as shown in Figure 3 and Figure 4) can be combined with a 5.0 V connection to obtain outputs above 5.0 V.
Figure 13. NPN Output Current Booster
THE AD584 AS A CURRENT LIMITER
The AD584 represents an alternative to current limiter diodes that require factory selection to achieve a desired current. Use of current limiting diodes often results in temperature coefficients of 1%/°C. Use of the AD584 in this mode is not limited to a set current limit; it can be programmed from 0.75 mA to 5 mA with the insertion of a single external resistor (see Figure 14). The minimum voltage required to drive the connection is 5 V.
Figure 14. A Two-Component Precision Current Limiter
NEGATIVE REFERENCE VOLTAGES FROM AN AD584
The AD584 can also be used in a 2-terminal Zener mode to provide a precision −10 V, −7.5 V, or −5.0 V reference. As shown in Figure 15, the VIN and VOUT terminals are connected together to the positive supply (in this case, ground). The AD584 COMMON pin is connected through a resistor to the negative supply. The output is now taken from the COMMON pin instead of VOUT. With 1 mA flowing through the AD584 in this mode, a typical unit shows a 2 mV increase in the output level over that produced in 3-terminal mode. Also, note that the effective output impedance in this connection increases from 0.2 Ω typical to 2 Ω. It is essential to arrange the output load and the supply resistor, RS, so that the net current through the AD584 is always between 1 mA and 5 mA (between 2 mA and 5 mA for operation beyond 85°C).
The temperature characteristics and long-term stability of the device is essentially the same as that of a unit used in standard 3-terminal mode.
Figure 15. 2-Terminal, −5 V Reference
The AD584 can also be used in 2-terminal mode to develop a positive reference. VIN and VOUT are tied together and to the positive supply through an appropriate supply resistor. The performance characteristics are similar to those of a negative 2-terminal connection. The only advantage of this connection over the standard 3-terminal connection is that a lower primary supply can be used, as low as 0.5 V above the desired output voltage. This type of operation requires considerable attention to load and to the primary supply regulation to ensure that the AD584 always remains within its regulating range of 1 mA to 5 mA (2 mA to 5 mA for operation beyond 85°C).
10 V REFERENCE WITH MULTIPLYING CMOS DACs OR ADCs
The AD584 is ideal for application with the AD7533 10-bit multiplying CMOS DAC, especially for low power applications. It is equally suitable for the AD7574 8-bit ADC. In the standard hook-up, as shown in Figure 16, the standard output voltages are inverted by the amplifier/DAC configuration to produce converted voltage ranges. For example, a +10 V reference produces a 0 V to −10 V range. If an OP1177 amplifier is used, total quiescent supply current is typically 2 mA.
Figure 16. Low Power 10-Bit CMOS DAC Application
AD584110.0V5.0V2.5V238V+4COMMONDARLINGTONNPN 2N6057VOUT(5V, 12AAS SHOWN)1kΩRAW SUPPLY (≈5V > VOUT)00527-014AD5841VOUT =
2.5V2.5VTAP38V+4COMMON=i+ 0.75mA2.5VRRLOAD00527-015AD5841VOUTVREF–5V5.0VTAP28V+4COMMON–15VRS2.4kΩ5%ANALOGGND1μF00527-016AD58410.0VV+184COMMON+15VAD75334BIT 1 (MSB)5DIGITALINPUT131612BIT 10 (LSB)15314VREF+15V–15VVOUT0V TO –10VRFBIOUT1IOUT2COMMON00527-017
AD584 Data Sheet
Rev. C | Page 10 of 12
The AD584 is normally used in the −10 V mode with the AD7574 to give a 0 V to +10 V ADC range. This is shown in Figure 17. Bipolar output applications and other operating details can be found in the data sheets for the CMOS products.
Figure 17. AD584 as −10 V Reference for CMOS ADC
PRECISION DAC REFERENCE
The AD565A, like many DACs, can operate with an external 10 V reference element (see Figure 19). This 10 V reference voltage is converted into a reference current of approximately 0.5 mA via the internal 19.95 kΩ resistor (in series with the external 100 Ω trimmer). The gain temperature coefficient of the AD565A is primarily governed by the temperature tracking of the 19.95 kΩ resistor and the 5 kΩ/10 kΩ span resistors; this gain temperature coefficient is guaranteed to 3 ppm/°C. Therefore, using the AD584K (at 5 ppm/°C) as the 10 V reference guarantees a maximum full-scale temperature coefficient of 18 ppm/°C more than the commercial range. The 10 V reference also supplies the normal 1 mA bipolar offset current through the 9.95 kΩ bipolar offset resistor. The bipolar offset temperature coefficient thus depends only on the temperature coefficient matching of the bipolar offset resistor to the input reference resistor and is guaranteed to 3 ppm/°C. Figure 18 demonstrates the flexibility of the AD584 applied to another popular digital-to-analog configuration.
Figure 18. Current Output, 8-Bit Digital-to-Analog Configuration
Figure 19. Precision 12-Bit DAC
–10V REFAD584418–15VV+10.0VCOMMONR31.2kΩ5%0.1μF+15V1182345AD7574(TOP VIEW)SIGNALINPUT0V TO +10VANALOGGROUNDGROUNDINTERTIEDIGITALSUPPLYRETURNR12kΩ 10%**R1 AND R2 CAN BE OMITTED IFGAIN TRIM IS NOT REQUIRED.GAIN TRIMR2 2kΩ*00527-019CA1 (
MSB)514A2615A37A48A59A610A7114IOA8 (
LSB)12COMP161VLCRLR15R14 =
R15V+13V–32ADDAC08VREF (+)VREF (–)AD5844813COMMONV+2.5V10.0VR1400527-020IOUT00527-0180.5mAIREFDACAD565A5kΩ20V SPAN10V SPANDAC OUT–VEEREFGNDBIPOLAR OFF5kΩ8kΩIOCODE INPUTLSBMSB10VVCCREF OUTREFINPOWERGND19.95kΩ20kΩ9.95kΩIOUT =4 × IREF × CODE0.1μF0.1μFOP1177+15V–15V236OP AMPOUTPUT±10V+15V+15V148AD584R2100Ω15TGAINADJUSTR1100Ω15TBIPOLAR OFFSETADJUST–15V
Data Sheet AD584
Rev. C | Page 11 of 12
OUTLINE DIMENSIONS
Figure 20. 8-Pin Metal Header [TO-99] (H-08) Dimensions shown in inches and (millimeters)
Figure 21. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS(INPARENTHESES)ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLYANDARE NOTAPPROPRIATE FOR USE IN DESIGN. COMPLIANTTO JEDEC STANDARDS MO-002-AK0.2500 (6.35) MIN0.5000 (12.70)MIN0.1850 (4.70)0.1650 (4.19)REFERENCE PLANE0.0500 (1.27) MAX0.0190 (0.48)0.0160 (0.41)0.0210 (0.53)0.0160 (0.41)0.0400 (1.02)0.0100 (0.25)0.0400 (1.02) MAX0.0340 (0.86)0.0280 (0.71)0.0450 (1.14)0.0270 (0.69)0.1600 (4.06)0.1400 (3.56)0.1000 (2.54)BSC6287 54 310.2000(5.08)BSC0.1000(2.54)BSC0.3700 (
9.40)0.3350 (8.51)0.3350 (8.51)0.3050 (7.75)45° BSCBASE & SEATING PLANE022306-ACOMPLIANTTO JEDEC STANDARDS MS-001CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS(INPARENTHESES)ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLYANDARE NOTAPPROPRIATE FOR USE IN DESIGN.CORNER LEADS MAY BE CONFIGUREDAS WHOLE OR HALF LEADS.070606-A0.022 (
0.56)0.018 (0.46)0.014 (0.36)SEATINGPLANE0.015(0.38)MIN0.210 (5.33)MAX0.150 (3.81)0.130 (3.30)0.115 (2.92)0.070 (1.78)0.060 (1.52)0.045 (1.14)81450.280 (7.11)0.250 (6.35)0.240 (6.10)0.100 (2.54)BSC0.400 (10.16)0.365 (9.27)0.355 (9.02)0.060 (1.52)MAX0.430 (10.92)MAX0.014 (0.36)0.010 (0.25)0.008 (0.20)0.325 (8.26)0.310 (7.87)0.300 (7.62)0.195 (4.95)0.130 (3.30)0.115 (2.92)0.015 (0.38)GAUGEPLANE0.005 (0.13)MIN
AD584 Data Sheet
Rev. C | Page 12 of 12
ORDERING GUIDE
Model1
Output Voltage (VO)
Initial Accuracy
Temperature Coefficient (ppm/°C)
Temperature Range (°C)
Package Description
Package Option
Ordering Quantity
mV
%
AD584JH
2.5
±7.5
0.30
30
0 to 70
8-Pin TO-99
H-08
100
AD584JNZ
2.5
±7.5
0.30
30
0 to 70
8-Lead PDIP
N-8
50
AD584KH
2.5
±3.5
0.14
15
0 to 70
8-Pin TO-99
H-08
100
AD584KNZ
2.5
±3.5
0.14
15
0 to 70
8-Lead PDIP
N-8
50
AD584SH
2.5
±7.5
0.30
30
−55 to +125
8-Pin TO-99
H-08
100
AD584SH/883B
2.5
±7.5
0.30
30
−55 to +125
8-Pin TO-99
H-08
100
AD584TH
2.5
±3.5
0.14
20
−55 to +125
8-Pin TO-99
H-08
100
AD584TH/883B
2.5
±3.5
0.14
20
−55 to +125
8-Pin TO-99
H-08
100
AD584JH
5.0
±15.0
0.30
30
0 to 70
8-Pin TO-99
H-08
100
AD584JNZ
5.0
±15.0
0.30
30
0 to 70
8-Lead PDIP
N-8
50
AD584KH
5.0
±6.0
0.12
15
0 to 70
8-Pin TO-99
H-08
100
AD584KNZ
5.0
±6.0
0.12
15
0 to 70
8-Lead PDIP
N-8
50
AD584SH
5.0
±15.0
0.14
30
−55 to +125
8-Pin TO-99
H-08
100
AD584SH/883B
5.0
±15.0
0.30
30
−55 to +125
8-Pin TO-99
H-08
100
AD584TH
5.0
±6.0
0.30
15
−55 to +125
8-Pin TO-99
H-08
100
AD584TH/883B
5.0
±6.0
0.12
15
−55 to +125
8-Pin TO-99
H-08
100
AD584JH
7.5
±20.0
0.27
30
0 to 70
8-Pin TO-99
H-08
100
AD584JNZ
7.5
±20.0
0.27
30
0 to 70
8-Lead PDIP
N-8
50
AD584KH
7.5
±8.0
0.11
15
0 to 70
8-Pin TO-99
H-08
100
AD584KNZ
7.5
±8.0
0.11
15
0 to 70
8-Lead PDIP
N-8
50
AD584SH
7.5
±20.0
0.27
30
−55 to +125
8-Pin TO-99
H-08
100
AD584SH/883B
7.5
±20.0
0.27
30
−55 to +125
8-Pin TO-99
H-08
100
AD584TH
7.5
±8.0
0.11
15
−55 to +125
8-Pin TO-99
H-08
100
AD584TH/883B
7.5
±8.0
0.11
15
−55 to +125
8-Pin TO-99
H-08
100
AD584JH
10.0
±30.0
0.30
30
0 to 70
8-Pin TO-99
H-08
100
AD584JNZ
10.0
±30.0
0.30
30
0 to 70
8-Lead PDIP
N-8
50
AD584KH
10.0
±10.0
0.10
15
0 to 70
8-Pin TO-99
H-08
100
AD584KNZ
10.0
±10.0
0.10
15
0 to 70
8-Lead PDIP
N-8
50
AD584SH
10.0
±30.0
0.30
30
−55 to +125
8-Pin TO-99
H-08
100
AD584SH/883B
10.0
±30.0
0.30
30
−55 to +125
8-Pin TO-99
H-08
100
AD584TH
10.0
±10.0
0.10
15
−55 to +125
8-Pin TO-99
H-08
100
AD584TH/883B
10.0
±10.0
0.10
15
−55 to +125
8-Pin TO-99
H-08
100
1 Z = RoHS Compliant Part.
©1978–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00527-0-5/12(C)
LF to 2.5 GHz
TruPwr™ Detector
Data Sheet AD8361
Rev. D Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES Calibrated rms response
Excellent temperature stability
Up to 30 dB input range at 2.5 GHz 700 mV rms, 10 dBm, re 50 Ω maximum input
±0.25 dB linear response up to 2.5 GHz Single-supply operation: 2.7 V to 5.5 V Low power: 3.3 mW at 3 V supply
Rapid power-down to less than 1 μA
APPLICATIONS
Measurement of CDMA, W-CDMA, QAM, other complex
modulation waveforms
RF transmitter or receiver power measurement
GENERAL DESCRIPTION
The AD8361 is a mean-responding power detector for use in high frequency receiver and transmitter signal chains, up to 2.5 GHz. It is very easy to apply. It requires a single supply only between 2.7 V and 5.5 V, a power supply decoupling capacitor,
and an input coupling capacitor in most applications. The
output is a linear-responding dc voltage with a conversion gain of 7.5 V/V rms. An external filter capacitor can be added to increase the averaging time constant.
Figure 1. Output in the Three Reference Modes, Supply 3 V, Frequency 1.9
GHz (6-Lead SOT-23 Package Ground Reference Mode Only)
FUNCTIONAL BLOCK DIAGRAMS
Figure 2. 8-Lead MSOP Figure 3. 6-Lead SOT-23 The AD8361 is intended for true power measurement of simple and complex waveforms. The device is particularly useful for measuring high crest-factor (high peak-to-rms ratio) signals,
such as CDMA and W-CDMA. The AD8361 has three operating modes to accommodate a
variety of analog-to-digital converter requirements: 1. Ground reference mode, in which the origin is zero. 2. Internal reference mode, which offsets the output 350 mV
above ground. 3. Supply reference mode, which offsets the output to VS/7.5.
The AD8361 is specified for operation from −40°C to +85°C
and is available in 8-lead MSOP and 6-lead SOT-23 packages. It
is fabricated on a proprietary high fT silicon bipolar process.
RFIN (V rms)
3.0
1.6
0 0.1 0.5 0.20.30.4
2.6
2.2
2.0
1.8
2.8
2.4
V rms (Volts)
1.4
1.2
1.0
0.6
0.8
0.4
0.2
0.0
SUPPLY
REFERENCE MODE
INTERNAL
REFERENCE MODE
GROUND
REFERENCE MODE
01088-C-001
RFIN
IREF
PWDN
VPOS
FLTR
SREF
VRMS
COMM
BAND-GAP
REFERENCE
ERROR
AMP
AD8361
INTERNAL FILTER
ADD
OFFSET
TRANSCONDUCTANCE
CELLS
i
i 7.5
BUFFER
2
2
01088-C-002
RFIN
IREF
PWDN
VPOS
FLTR
VRMS
COMM
BAND-GAP
REFERENCE
ERROR
AMP
AD8361
INTERNAL FILTER
TRANSCONDUCTANCE
CELLS
i
i 7.5
BUFFER
2
2
01088-C-003
AD8361 Data Sheet
Rev. D | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ..............................................6
Circuit Description......................................................................... 11
Applications ..................................................................................... 12
Output Reference Temperature Drift Compensation ........... 16
Evaluation Board ............................................................................ 21
Characterization Setups............................................................. 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
3/14—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 24 Updated Outline Dimensions ....................................................... 24
8/04—Data Sheet Changed from Rev. B to Rev. C
Changed Trimpots to Trimmable Potentiometers ......... Universal Changes to Specifications ................................................................ 3 Changed Using the AD8361 Section Title to Applications ....... 12 Changes to Figure 43 ...................................................................... 14 Changes to Ordering Guide .......................................................... 24 Updated Outline Dimensions ....................................................... 24
2/01—Data Sheet Changed from Rev. A to Rev. B.
Data Sheet AD8361
Rev. D | Page 3 of 24
SPECIFICATIONS
TA = 25°C, VS = 3 V, fRF = 900 MHz, ground reference output mode, unless otherwise noted.
Table 1.
Parameter
Condition
Min
Typ
Max
Unit
SIGNAL INPUT INTERFACE
(Input RFIN)
Frequency Range1
2.5
GHz
Linear Response Upper Limit
VS = 3 V
390
mV rms
Equivalent dBm, re 50 Ω
4.9
dBm
VS = 5 V
660
mV rms
Equivalent dBm, re 50 Ω
9.4
dBm
Input Impedance2
225||1
Ω||pF
RMS CONVERSION
(Input RFIN to Output V rms)
Conversion Gain
7.5
V/V rms
fRF = 100 MHz, VS = 5 V
6.5
8.5
V/V rms
Dynamic Range
Error Referred to Best Fit Line3
±0.25 dB Error4
CW Input, −40°C < TA < +85°C
14
dB
±1 dB Error
CW Input, −40°C < TA < +85°C
23
dB
±2 dB Error
CW Input, −40°C < TA < +85°C
26
dB
CW Input, VS = 5 V, −40°C < TA < +85°C
30
dB
Intercept-Induced Dynamic
Internal Reference Mode
1
dB
Range Reduction5, 6
Supply Reference Mode, VS = 3.0 V
1
dB
Supply Reference Mode, VS = 5.0 V
1.5
dB
Deviation from CW Response
5.5 dB Peak-to-Average Ratio (IS95 Reverse Link)
0.2
dB
12 dB Peak-to-Average Ratio (W-CDMA 4 Channels)
1.0
dB
18 dB Peak-to-Average Ratio (W-CDMA 15 Channels)
1.2
dB
OUTPUT INTERCEPT5
Inferred from Best Fit Line3
Ground Reference Mode (GRM)
0 V at SREF, VS at IREF
0
V
fRF = 100 MHz, VS = 5 V
−50
+150
mV
Internal Reference Mode (IRM)
0 V at SREF, IREF Open
350
mV
fRF = 100 MHz, VS = 5 V
300
500
mV
Supply Reference Mode (SRM)
3 V at IREF, 3 V at SREF
400
mV
VS at IREF, VS at SREF
VS/7.5
V
fRF = 100 MHz, VS = 5 V
590
750
mV
POWER-DOWN INTERFACE
PWDN HI Threshold
2.7 ≤ VS ≤ 5.5 V, −40°C < TA < +85°C
VS − 0.5
V
PWDN LO Threshold
2.7 ≤ VS ≤ 5.5 V, −40°C < TA < +85°C
0.1
V
Power-Up Response Time
2 pF at FLTR Pin, 224 mV rms at RFIN
5
μs
100 nF at FLTR Pin, 224 mV rms at RFIN
320
μs
PWDN Bias Current
<1
μA
POWER SUPPLIES
Operating Range
−40°C < TA < +85°C
2.7
5.5
V
Quiescent Current
0 mV rms at RFIN, PWDN Input LO7
1.1
mA
Power-Down Current
GRM or IRM, 0 mV rms at RFIN, PWDN Input HI
<1
μA
SRM, 0 mV rms at RFIN, PWDN Input HI
10 × VS
μA
1 Operation at arbitrarily low frequencies is possible; see Applications section.
2 Figure 17 and Figure 47 show impedance versus frequency for the MSOP and SOT-23, respectively.
3 Calculated using linear regression.
4 Compensated for output reference temperature drift; see Applications section.
5 SOT-23-6L operates in ground reference mode only.
6 The available output swing, and hence the dynamic range, is altered by both supply voltage and reference mode; see Figure 39 and Figure 40.
7 Supply current is input level dependent; see Figure 16.
AD8361 Data Sheet
Rev. D | Page 4 of 24
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage VS 5.5 V
SREF, PWDN 0 V, VS
IREF VS − 0.3 V, VS
RFIN 1 V rms
Equivalent Power, re 50 Ω 13 dBm
Internal Power Dissipation1 200 mW
6-Lead SOT-23 170 mW
8-Lead MSOP 200 mW
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
(Soldering 60 sec)
300°C
1 Specification is for the device in free air.
6-Lead SOT-23: θJA = 230°C/W; θJC = 92°C/W.
8-Lead MSOP: θJA = 200°C/W; θJC = 44°C/W. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. ESD CAUTION
Data Sheet AD8361
Rev. D | Page 5 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. 8-Lead MSOP Figure 5. 6-Lead SOT-23 Table 3. Pin Function Descriptions Pin No. MSOP
Pin No. SOT-23 Mnemonic Description
1 6 VPOS Supply Voltage Pin. Operational range 2.7 V to 5.5 V. 2 N/A IREF Output Reference Control Pin. Internal reference mode enabled when pin is left open; otherwise, this
pin should be tied to VPOS. Do not ground this pin. 3 5 RFIN Signal Input Pin. Must be driven from an ac-coupled source. The low frequency real input impedance is
225 Ω. 4 4 PWDN Power-Down Pin. For the device to operate as a detector, it needs a logical low input (less than 100 mV). When a logic high (greater than VS − 0.5 V) is applied, the device is turned off and the supply
current goes to nearly zero (ground and internal reference mode less than 1 μA, supply reference mode VS divided by 100 kΩ). 5 2 COMM Device Ground Pin.
6 3 FLTR By placing a capacitor between this pin and VPOS, the corner frequency of the modulation filter is lowered. The on-chip filter is formed with 27 pF||2 kΩ for small input signals. 7 1 VRMS Output Pin. Near rail-to-rail voltage output with limited current drive capabilities. Expected load
>10 kΩ to ground.
8 N/A SREF Supply Reference Control Pin. To enable supply reference mode, this pin must be connected to VPOS;
otherwise, it should be connected to COMM (ground). VPOS 1
IREF 2
RFIN 3
PWDN 4
8 SREF
7 VRMS
6 FLTR
5 COMM
AD8361
TOP VIEW
(Not to Scale)
01088-C-004
VRMS 1
COMM 2
FLTR 3
6 VPOS
5 RFIN
4 PWDN
AD8361
TOP VIEW
(Not to Scale)
01088-C-005
AD8361 Data Sheet
Rev. D | Page 6 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. Output vs. Input Level, Frequencies 100 MHz, 900 MHz, 1900 MHz, and 2500 MHz, Supply 2.7 V, Ground Reference Mode, MSOP
Figure 7. Output vs. Input Level, Supply 2.7 V, 3.0 V, 5.0 V, and 5.5 V, Frequency 900 MHz
Figure 8. Output vs. Input Level with Different Waveforms Sine Wave (CW), IS95 Reverse Link, W-CDMA 4-Channel and W-CDMA 15-Channel, Supply 5.0 V
Figure 9. Error from Linear Reference vs. Input Level, 3 Sigma to Either Side of Mean, Sine Wave, Supply 3.0 V, Frequency 900 MHz
Figure 10. Error from Linear Reference vs. Input Level, 3 Sigma to Either Side of Mean, Sine Wave, Supply 5.0 V, Frequency 900 MHz
Figure 11. Error from CW Linear Reference vs. Input with Different Waveforms Sine Wave (CW), IS95 Reverse Link, W-CDMA 4-Channel and W-CDMA 15-Channel, Supply 3.0 V, Frequency 900 MHz
INPUT (V rms)2.82.60.800.50.10.20.30.42.01.41.21.02.42.21.61.8OUTPUT (
V)0.60.40.20.0900MHz100MHz1900MHz2.5GHz01088-C-006INPUT (V rms)5.51.500.50.10.20.30.44.03.02.52.05.04.53.5OUTPUT (
V)1.00.50.05.5V5.0V3.0V2.7V0.60.70.801088-C-007INPUT (V rms)5.01.500.50.10.20.30.44.03.02.52.04.53.5OUTPUT (
V)1.00.50.00.60.70.8CWIS95REVERSE LINKWCDMA4- AND 15-CHANNEL01088-C-008INPUT (V rms)3.02.5–1.00.4(+5dBm)0.011.50–0.52.00.51.0ERROR (
dB)–1.5–2.0–2.5–3.00.1(–7dBm)0.02(–21dBm)MEAN±3 SIGMA01088-C-009INPUT (V rms)3.02.5–1.00.6(+8.6dBm)0.011.50–0.52.00.51.0ERROR (
dB)–1.5–2.0–2.5–3.00.10.02MEAN±3 SIGMA(–7dBm)(–21dBm)01088-C-010INPUT (
V
rms)3.02.5–1.01.00.010.11.50.0–0.52.00.51.0ERROR (
dB)–1.5–2.0–2.5–3.00.020.60.2IS95REVERSE LINKCW15-CHANNEL4-CHANNEL01088-C-011
Data Sheet AD8361
Rev. D | Page 7 of 24
Figure 12. Error from CW Linear Reference vs. Input, 3 Sigma to Either Side of Mean, IS95 Reverse Link Signal, Supply 3.0 V, Frequency 900 MHz
Figure 13. Error from CW Linear Reference vs. Input Level, 3 Sigma to Either Side of Mean, IS95 Reverse Link Signal, Supply 5.0 V, Frequency 900 MHz
Figure 14. Output Delta from +25°C vs. Input Level, 3 Sigma to Either Side of Mean Sine Wave, Supply 3.0 V, Frequency 900 MHz, Temperature −40°C to +85°C
Figure 15. Output Delta from +25°C vs. Input Level, 3 Sigma to Either Side of Mean Sine Wave, Supply 3.0 V, Frequency 1900 MHz, Temperature −40°C to +85°C
Figure 16. Supply Current vs. Input Level, Supplies 3.0 V, and 5.0 V, Temperatures −40°C, +25°C, and +85°C
Figure 17. Input Impedance vs. Frequency, Supply 3 V, Temperatures −40°C, +25°C, and +85°C, MSOP (See Applications for SOT-23 Data)
3.02.5–1.00.4(+5dBm)0.011.50–0.52.00.51.0ERROR (
dB)–1.5–2.02.5–3.00.10.02MEAN±3 SIGMAINPUT (V rms)(–7dBm)(–21dBm)01088-C-012INPUT (
V
rms)3.02.5–1.00.6(+8.6dBm)0.011.50–0.52.00.51.0ERROR (
dB)–1.5–2.0–2.5–3.00.10.02MEAN±3 SIGMA(–7dBm)(–21dBm)01088-C-013INPUT (
V
rms)3.02.5–1.00.4(+5dBm)0.011.50–0.52.00.51.0ERROR (
dB)–1.5–2.0–2.5–3.00.10.02–40°C+85°C(–7dBm)(–21dBm)01088-C-014INPUT (
V
rms)3.02.5–1.00.4(+5dBm)0.011.50–0.52.00.51.0ERROR (
dB)–1.5–2.0–2.5–3.00.10.02(–7dBm)(–21dBm)–40°C+85°C01088-C-015INPUT (V rms)11300.50.10.20.30.486541097SUPPLY CURRENT (
mA)2100.60.70.8+85°C–40°C+25°CVS = 5VINPUT OUTOF RANGE+25°C+85°C–40°CVS = 3VINPUT OUTOF RANGE01088-C-016FREQUENCY (MHz)05001000250200150SHUNT RESISTANCE (
Ω)100500200025001.41.21.0SHUNT CAPACITANCE (
pF)0.80.60.41500+85°C+25°C–40°C+85°C+25°C–40°C1.61.801088-C-017
AD8361 Data Sheet
Rev. D | Page 8 of 24
Figure 18. Output Reference Change vs. Temperature, Supply 3 V, Ground Reference Mode
Figure 19. Output Reference Change vs. Temperature, Supply 3 V, Internal Reference Mode (MSOP Only)
Figure 20. Output Reference Change vs. Temperature, Supply 3 V, Supply Reference Mode (MSOP Only)
Figure 21. Conversion Gain Change vs. Temperature, Supply 3 V, Ground Reference Mode, Frequency 900 MHz
Figure 22. Conversion Gain Change vs. Temperature, Supply 3 V, Internal Reference Mode, Frequency 900 MHz (MSOP Only)
Figure 23. Conversion Gain Change vs. Temperature, Supply 3 V, Supply Reference Mode, Frequency 900 MHz (MSOP Only)
TEMPERATURE (°C)–0.0240–40–200200.030.010.00–0.010.02INTERCEPT CHANGE (
V)–0.03–0.04–0.056080100MEAN±3 SIGMA01088-C-018TEMPERATURE (°C)–0.0140–40–200200.020.010.00INTERCEPT CHANGE (
V)–0.02–0.036080100MEAN±3 SIGMA01088-C-019TEMPERATURE (°C)–0.0240–40–200200.030.010.00–0.010.02INTERCEPT CHANGE (
V)–0.03–0.04–0.056080100MEAN±3 SIGMA01088-C-020TEMPERATURE (°C)0.0240–40–200200.120.080.060.040.10GAIN CHANGE (
V/V
rms)0.00–0.02–0.046080100MEAN±3 SIGMA–0.060.140.160.1801088-C-021TEMPERATURE (°C)0.0240–40–200200.120.080.060.040.10GAIN CHANGE (
V/V
rms)0.00–0.02–0.046080100MEAN±3 SIGMA–0.060.140.160.1801088-C-022TEMPERATURE (°C)0.0240–40–200200.120.080.060.040.10GAIN CHANGE (
V/V
rms)0.00–0.02–0.046080100MEAN±3 SIGMA–0.060.140.160.1801088-C-023
Data Sheet AD8361
Rev. D | Page 9 of 24
Figure 24. Output Response to Modulated Pulse Input for Various RF Input
Levels, Supply 3 V, Modulation Frequency 900 MHz, No Filter Capacitor Figure 25. Output Response to Modulated Pulse Input for Various RF Input
Levels, Supply 3 V, Modulation Frequency 900 MHz, 0.01 μF Filter Capacitor
Figure 26. Hardware Configuration for Output Response to Modulated Pulse Input
Figure 27. Output Response Using Power-Down Mode for Various RF Input
Levels, Supply 3 V, Frequency 900 MHz, No Filter Capacitor Figure 28. Output Response Using Power-Down Mode for Various RF Input
Levels, Supply 3 V, Frequency 900 MHz, 0.01 μF Filter Capacitor Figure 29. Hardware Configuration for Output Response Using Power-Down Mode 67mV
370mV
270mV
25mV
5s PER HORIZONTAL DIVISION
GATE PULSE FOR
900MHz RF TONE
RF INPUT
500mV PER
VERTICAL
DIVISION
01088-C-024
67mV
370mV
25mV
500mV PER
VERTICAL
DIVISION
50s PER HORIZONTAL DIVISION
RF INPUT
GATEPULSEFOR
900MHzRFTONE
270mV
01088-C-025 R1
75
0.1F
HPE3631A
POWER SUPPLY
C4
0.01F
C2
100pF
HP8648B
SIGNAL
GENERATOR
C1 C3
TEK TDS784C
SCOPE
C5
100pF
TEK P6204
FET PROBE
1
2
3
4
8
7
6
5
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
01088-C-026
RF INPUT
67mV
370mV
270mV
25mV
500mV PER
VERTICAL
DIVISION
PWDN INPUT
2s PER HORIZONTAL DIVISION
01088-C-027
67mV
370mV
270mV
25mV
500mV PER
VERTICAL
DIVISION
PWDN INPUT
RF INPUT
01088-C-028
20s PER HORIZONTAL DIVISION
R1
75
0.1F
HPE3631A
POWER SUPPLY
C4
0.01F
C2
100pF
HP8648B
SIGNAL
GENERATOR
HP8110A
SIGNAL
GENERATOR
C1 C3
TEK TDS784C
SCOPE
C5
100pF
TEK P6204
FET PROBE
1
2
3
4
8
7
6
5
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
01088-C-029
AD8361 Data Sheet
Rev. D | Page 10 of 24
Figure 30. Conversion Gain Change vs. Frequency, Supply 3 V, Ground Reference Mode, Frequency 100 MHz to 2500 MHz, Representative Device
Figure 31. Output Response to Gating on Power Supply, for Various RF Input Levels, Supply 3 V, Modulation Frequency 900 MHz, 0.01 μF Filter Capacitor
Figure 32. Hardware Configuration for Output Response to Power Supply Gating Measurements
Figure 33. Conversion Gain Distribution Frequency 100 MHz, Supply 5 V, Sample Size 3000
Figure 34. Output Reference, Internal Reference Mode, Supply 5 V, Sample Size 3000 (MSOP Only)
Figure 35. Output Reference, Supply Reference Mode, Supply 5 V, Sample Size 3000 (MSOP Only)
CARRIER FREQUENCY (MHz)7.87.66.210010007.26.66.47.46.87.0CONVERSION GAIN (
V/V
rms)6.05.85.6VS= 3V01088-C-03067mV370mV270mV25mV500mV PERVERTICALDIVISIONSUPPLY20μs PER HORIZONTAL DIVISIONRFINPUT01088-C-031R175Ω732Ω50Ω0.1μFC40.01μFC2100pFHP8648BSIGNALGENERATORC1C3TEK TDS784CSCOPEC5100pFTEK P6204FET PROBE12348765AD8361VPOSIREFRFINPWDNSREFVRMSFLTRCOMM01088-C-032HP8110APULSEGENERATORAD811CONVERSION GAIN (V/V rms)7.66.97.07.216PERCENT7.47.81412108642001088-C-033IREF MODE INTERCEPT (V)0.400.320.340.36PERCENT0.380.441210864200.4201088-C-034SREF MODE INTERCEPT (V)0.720.640.660.68PERCENT0.700.761210864200.7401088-C-035
Data Sheet AD8361
Rev. D | Page 11 of 24
CIRCUIT DESCRIPTION
The AD8361 is an rms-responding (mean power) detector that provides an approach to the exact measurement of RF power that is basically independent of waveform. It achieves this function through the use of a proprietary technique in which the outputs of two identical squaring cells are balanced by the action of a high-gain error amplifier.
The signal to be measured is applied to the input of the first squaring cell, which presents a nominal (LF) resistance of 225 Ω between the RFIN and COMM pins (connected to the ground plane). Because the input pin is at a bias voltage of about 0.8 V above ground, a coupling capacitor is required. By making this an external component, the measurement range may be extended to arbitrarily low frequencies.
The AD8361 responds to the voltage, VIN, at its input by squaring this voltage to generate a current proportional to VIN squared. This is applied to an internal load resistor, across which a capacitor is connected. These form a low-pass filter, which extracts the mean of VIN squared. Although essentially voltage-responding, the associated input impedance calibrates this port in terms of equivalent power. Therefore, 1 mW corresponds to a voltage input of 447 mV rms. The Applications section shows how to match this input to 50 Ω.
The voltage across the low-pass filter, whose frequency may be arbitrarily low, is applied to one input of an error-sensing amplifier. A second identical voltage-squaring cell is used to close a negative feedback loop around this error amplifier. This second cell is driven by a fraction of the quasi-dc output voltage of the AD8361. When the voltage at the input of the second squaring cell is equal to the rms value of VIN, the loop is in a stable state, and the output then represents the rms value of the input. The feedback ratio is nominally 0.133, making the rms-dc conversion gain ×7.5, that is
rmsVVINOUT×=5.7
By completing the feedback path through a second squaring cell, identical to the one receiving the signal to be measured, several benefits arise. First, scaling effects in these cells cancel; thus, the overall calibration may be accurate, even though the open-loop response of the squaring cells taken separately need not be. Note that in implementing rms-dc conversion, no reference voltage enters into the closed-loop scaling. Second, the tracking in the responses of the dual cells remains very close over temperature, leading to excellent stability of calibration.
The squaring cells have very wide bandwidth with an intrinsic response from dc to microwave. However, the dynamic range of such a system is fairly small, due in part to the much larger dynamic range at the output of the squaring cells. There are practical limitations to the accuracy of sensing very small error signals at the bottom end of the dynamic range, arising from small random offsets that limit the attainable accuracy at small inputs.
On the other hand, the squaring cells in the AD8361 have a Class-AB aspect; the peak input is not limited by their quiescent bias condition but is determined mainly by the eventual loss of square-law conformance. Consequently, the top end of their response range occurs at a fairly large input level (approximately 700 mV rms) while preserving a reasonably accurate square-law response. The maximum usable range is, in practice, limited by the output swing. The rail-to-rail output stage can swing from a few millivolts above ground to less than 100 mV below the supply. An example of the output induced limit: given a gain of 7.5 and assuming a maximum output of 2.9 V with a 3 V supply, the maximum input is (2.9 V rms)/7.5 or 390 mV rms.
Filtering
An important aspect of rms-dc conversion is the need for averaging (the function is root-MEAN-square). For complex RF waveforms, such as those that occur in CDMA, the filtering provided by the on-chip, low-pass filter, although satisfactory for CW signals above 100 MHz, is inadequate when the signal has modulation components that extend down into the kilohertz region. For this reason, the FLTR pin is provided: a capacitor attached between this pin and VPOS can extend the averaging time to very low frequencies.
Offset
An offset voltage can be added to the output (when using the MSOP version) to allow the use of ADCs whose range does not extend down to ground. However, accuracy at the low end degrades because of the inherent error in this added voltage. This requires that the IREF (internal reference) pin be tied to VPOS and SREF (supply reference) to ground.
In the IREF mode, the intercept is generated by an internal reference cell and is a fixed 350 mV, independent of the supply voltage. To enable this intercept, IREF should be open-circuited, and SREF should be grounded.
In the SREF mode, the voltage is provided by the supply. To implement this mode, tie IREF to VPOS and SREF to VPOS. The offset is then proportional to the supply voltage and is 400 mV for a 3 V supply and 667 mV for a 5 V supply.
AD8361 Data Sheet
Rev. D | Page 12 of 24
APPLICATIONS
Basic Connections
Figure 36 through Figure 38 show the basic connections for the AD8361’s MSOP version in its three operating modes. In all modes, the device is powered by a single supply of between 2.7 V and 5.5 V. The VPOS pin is decoupled using 100 pF and 0.01 μF capacitors. The quiescent current of 1.1 mA in operating mode can be reduced to 1 μA by pulling the PWDN pin up to VPOS.
A 75 Ω external shunt resistance combines with the ac-coupled input to give an overall broadband input impedance near 50 Ω. Note that the coupling capacitor must be placed between the input and the shunt impedance. Input impedance and input coupling are discussed in more detail below.
The input coupling capacitor combines with the internal input resistance (Figure 37) to provide a high-pass corner frequency given by the equation
INCRCf××=π21dB3
With the 100 pF capacitor shown in Figure 36 through Figure 38, the high-pass corner frequency is about 8 MHz.
Figure 36. Basic Connections for Ground Reference Mode
Figure 37. Basic Connections for Internal Reference Mode
Figure 38. Basic Connections for Supply Referenced Mode
The output voltage is nominally 7.5 times the input rms voltage (a conversion gain of 7.5 V/V rms). Three modes of operation are set by the SREF and IREF pins. In addition to the ground reference mode shown in Figure 36, where the output voltage swings from around near ground to 4.9 V on a 5.0 V supply, two additional modes allow an offset voltage to be added to the output. In the internal reference mode (Figure 37), the output voltage swing is shifted upward by an internal reference voltage of 350 mV. In supply referenced mode (Figure 38), an offset voltage of VS/7.5 is added to the output voltage. Table 4 summarizes the connections, output transfer function, and minimum output voltage (i.e., zero signal) for each mode.
Output Swing
Figure 39 shows the output swing of the AD8361 for a 5 V supply voltage for each of the three modes. It is clear from Figure 39 that operating the device in either internal reference mode or supply referenced mode reduces the effective dynamic range as the output headroom decreases. The response for lower supply voltages is similar (in the supply referenced mode, the offset is smaller), but the dynamic range reduces further as headroom decreases. Figure 40 shows the response of the AD8361 to a CW input for various supply voltages.
Figure 39. Output Swing for Ground, Internal, and Supply Referenced Mode, VPOS = 5 V (MSOP Only)
12348765AD8361VPOSIREFRFINPWDNSREFVRMSFLTRCOMMR175Ω0.01μFCC100pFCFLTR100pF+VS 2.7V– 5.5VRFINV rms01088-C-03612348765AD8361VPOSIREFRFINPWDNSREFVRMSFLTRCOMMR175Ω0.01μFCC100pFCFLTR100pF+VS 2.7V– 5.5VRFINV rms01088-C-03712348765AD8361VPOSIREFRFINPWDNSREFVRMSFLTRCOMMR175Ω0.01μFCC100pFCFLTR100pF+VS 2.7V– 5.5VRFINV rms01088-C-038INPUT (V rms)5.04.50.000.50.10.20.30.43.01.51.00.54.03.52.02.5OUTPUT (
V)SUPPLY REFINTERNAL REFGROUND REF0.60.70.801088-C-039
Data Sheet AD8361
Rev. D | Page 13 of 24
Figure 40. Output Swing for Supply Voltages of 2.7 V, 3.0 V, 5.0 V and 5.5 V (MSOP Only)
Dynamic Range
Because the AD8361 is a linear-responding device with a nominal transfer function of 7.5 V/V rms, the dynamic range in dB is not clear from plots such as Figure 39. As the input level is increased in constant dB steps, the output step size (per dB) also increases. Figure 41 shows the relationship between the output step size (i.e., mV/dB) and input voltage for a nominal transfer function of 7.5 V/V rms.
Table 4. Connections and Nominal Transfer Function for Ground, Internal, and Supply Reference Modes
Reference Mode
IREF
SREF
Output Intercept (No Signal)
Output
Ground
VPOS
COMM
Zero
7.5 VIN
Internal
OPEN
COMM
0.350 V
7.5 VIN + 0.350 V
Supply
VPOS
VPOS
VS/7.5
7.5 VIN + VS/7.5
Figure 41. Idealized Output Step Size as a Function of Input Voltage
Plots of output voltage versus input voltage result in a straight line. It may sometimes be more useful to plot the error on a logarithmic scale, as shown in Figure 42. The deviation of the plot for the ideal straight line characteristic is caused by output clipping at the high end and by signal offsets at the low end. It should however be noted that offsets at the low end can be either positive or negative, so this plot could also trend upwards at the low end. Figure 9, Figure 10, Figure 12, and Figure 13 show a ±3 sigma distribution of the device error for a large population of devices.
Figure 42. Representative Unit, Error in dB vs. Input Level, VS = 2.7 V
It is also apparent in Figure 42 that the error plot tends to shift to the right with increasing frequency. Because the input impedance decreases with frequency, the voltage actually applied to the input also tends to decrease (assuming a constant source impedance over frequency). The dynamic range is almost constant over frequency, but with a small decrease in conversion gain at high frequency.
Input Coupling and Matching
The input impedance of the AD8361 decreases with increasing frequency in both its resistive and capacitive components (Figure 17). The resistive component varies from 225 Ω at 100 MHz down to about 95 Ω at 2.5 GHz.
A number of options exist for input matching. For operation at multiple frequencies, a 75 Ω shunt to ground, as shown in Figure 43, provides the best overall match. For use at a single frequency, a resistive or a reactive match can be used. By plotting the input impedance on a Smith Chart, the best value for a resistive match can be calculated. The VSWR can be held below 1.5 at frequencies up to 1 GHz, even as the input impedance varies from part to part. (Both input impedance and input capacitance can vary by up to ±20% around their nominal values.) At very high frequencies (i.e., 1.8 GHz to 2.5 GHz), a shunt resistor is not sufficient to reduce the VSWR below 1.5. Where VSWR is critical, remove the shunt component and insert an inductor in series with the coupling capacitor as shown in Figure 44.
Table 5 gives recommended shunt resistor values for various frequencies and series inductor values for high frequencies. The coupling capacitor, CC, essentially acts as an ac-short and plays no intentional part in the matching.
INPUT (V rms)5.51.500.50.10.20.30.44.03.02.52.05.04.53.5OUTPUT (
V)1.00.50.05.5V5.0V3.0V2.7V0.60.70.801088-C-040INPUT (mV)7002000500100200300400500400300600mV/dB100060070080001088-C-041INPUT (V rms)2.0–0.50.010.50.01.51.0ERROR (
dB)–1.0–1.5–2.01.01.9GHz2.5GHz900MHz100MHz100MHz0.02(–21dBm)0.1(–7dBm)0.4(+5dBm)01088-C-042
AD8361 Data Sheet
Rev. D | Page 14 of 24
Figure 43. Input Coupling/Matching Options, Broadband Resistor Match
Figure 44. Input Coupling/Matching Options, Series Inductor Match
Figure 45. Input Coupling/Matching Options, Narrowband Reactive Match Figure 46. Input Coupling/Matching Options, Attenuating the Input Signal
Table 5. Recommended Component Values for Resistive or
Inductive Input Matching (Figure 43 and Figure 44) Frequency Matching Component
100 MHz 63.4 Ω Shunt 800 MHz 75 Ω Shunt 900 MHz 75 Ω Shunt 1800 MHz 150 Ω Shunt or 4.7 nH Series
1900 MHz 150 Ω Shunt or 4.7 nH Series
2500 MHz 150 Ω Shunt or 2.7 nH Series
Alternatively, a reactive match can be implemented using a shunt
inductor to ground and a series capacitor, as shown in Figure 45. A method for hand calculating the appropriate matching components is shown on page 12 of the AD8306 data sheet.
Matching in this manner results in very small values for CM,
especially at high frequencies. As a result, a stray capacitance as small as 1 pF can significantly degrade the quality of the match.
The main advantage of a reactive match is the increase in sensitivity that results from the input voltage being gained up (by the square root of the impedance ratio) by the matching network. Table 6 shows the recommended values for reactive
matching. Table 6. Recommended Values for a Reactive Input Matching (Figure 45)
Frequency (MHz) CM (pF) LM (nH)
100 16 180
800 2 15
900 2 12
1800 1.5 4.7
1900 1.5 4.7
2500 1.5 3.3
Input Coupling Using a Series Resistor
Figure 46 shows a technique for coupling the input signal into the AD8361 that may be applicable where the input signal is
much larger than the input range of the AD8361. A series
resistor combines with the input impedance of the AD8361 to
attenuate the input signal. Because this series resistor forms a
divider with the frequency dependent input impedance, the
apparent gain changes greatly with frequency. However, this
method has the advantage of very little power being tapped off
in RF power transmission applications. If the resistor is large
compared to the transmission line’s impedance, then the VSWR
of the system is relatively unaffected.
Figure 47. Input Impedance vs. Frequency, Supply 3 V, SOT-23
Selecting the Filter Capacitor
The AD8361’s internal 27 pF filter capacitor is connected in parallel with an internal resistance that varies with signal level from 2 kΩ for small signals to 500 Ω for large signals. The
resulting low-pass corner frequency between 3 MHz and
12 MHz provides adequate filtering for all frequencies above 240 MHz (i.e., 10 times the frequency at the output of the
squarer, which is twice the input frequency). However, signals
with high peak-to-average ratios, such as CDMA or W-CDMA
signals, and low frequency components require additional filtering. TDMA signals, such as GSM, PDC, or PHS, have a
peak-to average ratio that is close to that of a sinusoid, and the internal filter is adequate. AD8361
RFIN RFIN
RSH
01088-C-043
CC
AD8361
RFIN RFIN
LM
01088-C-044
CC
AD8361
RFIN RFIN
01088-C-045
CM CC
LM
AD8361
RFIN RFIN
01088-C-046
RSERIES CC
FREQUENCY (MHz)
200
0 500
RESISTANCE ()
100
0
250
150
50
1000 15002000250030003500
0.2
0.5
0.8
1.1
1.4
1.7
CAPACITANCE (pF)
01088-C-047
Data Sheet AD8361
Rev. D | Page 15 of 24
The filter capacitance of the AD8361 can be augmented by connecting a capacitor between Pin 6 (FLTR) and VPOS. Table 7 shows the effect of several capacitor values for various communications standards with high peak-to-average ratios along with the residual ripple at the output, in peak-to-peak and rms volts. Note that large filter capacitors increase the enable and pulse response times, as discussed below.
Table 7. Effect of Waveform and CFILT on Residual AC
Output
Residual AC
Waveform
CFILT
V dc
mV p-p
mV rms
IS95 Reverse Link
Open
0.5
550
100
1.0
1000
180
2.0
2000
360
0.01 μF
0.5
40
6
1.0
160
20
2.0
430
60
0.1 μF
0.5
20
3
1.0
40
6
2.0
110
18
IS95 8-Channel
0.01 μF
0.5
290
40
Forward Link
1.0
975
150
2.0
2600
430
0.1 μF
0.5
50
7
1.0
190
30
2.0
670
95
W-CDMA 15
0.01 μF
0.5
225
35
Channel
1.0
940
135
2.0
2500
390
0.1 μF
0.5
45
6
1.0
165
25
2.0
550
80
Operation at Low Frequencies
Although the AD8361 is specified for operation up to 2.5 GHz, there is no lower limit on the operating frequency. It is only necessary to increase the input coupling capacitor to reduce the corner frequency of the input high-pass filter (use an input resistance of 225 Ω for frequencies below 100 MHz). It is also necessary to increase the filter capacitor so that the signal at the output of the squaring circuit is free of ripple. The corner frequency is set by the combination of the internal resistance of 2 kΩ and the external filter capacitance.
Power Consumption, Enable and Power-On
The quiescent current consumption of the AD8361 varies with the size of the input signal from about 1 mA for no signal up to 7 mA at an input level of 0.66 V rms (9.4 dBm, re 50 Ω). If the input is driven beyond this point, the supply current increases steeply (see Figure 16). There is little variation in quiescent current with power supply voltage.
The AD8361 can be disabled either by pulling the PWDN (Pin 4) to VPOS or by simply turning off the power to the device. While turning off the device obviously eliminates the current consumption, disabling the device reduces the leakage current to less than 1 μA. Figure 27 and Figure 28 show the response of the output of the AD8361 to a pulse on the PWDN pin, with no capacitance and with a filter capacitance of 0.01 μF, respectively; the turn-on time is a function of the filter capacitor. Figure 31 shows a plot of the output response to the supply being turned on (i.e., PWDN is grounded and VPOS is pulsed) with a filter capacitor of 0.01 μF. Again, the turn-on time is strongly influenced by the size of the filter capacitor.
If the input of the AD8361 is driven while the device is disabled (PWDN = VPOS), the leakage current of less than 1 μA increases as a function of input level. When the device is disabled, the output impedance increases to approximately 16 kΩ.
Volts to dBm Conversion
In many of the plots, the horizontal axis is scaled in both rms volts and dBm. In all cases, dBm are calculated relative to an impedance of 50 Ω. To convert between dBm and volts in a 50 Ω system, the following equations can be used. Figure 48 shows this conversion in graphical form.
()()()()222010logW0.001Ω5010logdBmrmsVrmsVPower==
()20/10log10logΩ50W0.00111dBmdBmrmsV−−=
××=
Figure 48. Conversion from dBm to rms Volts
V rmsdBm+20+100–10–20–30–4010.10.010.00101088-C-048
AD8361 Data Sheet
Rev. D | Page 16 of 24
Output Drive Capability and Buffering The AD8361 is capable of sourcing an output current of approximately 3 mA. If additional current is required, a simple
buffering circuit can be used as shown in Figure 51. Similar
circuits can be used to increase or decrease the nominal conversion gain of 7.5 V/V rms (Figure 49 and Figure 50). In Figure 50, the AD8031 buffers a resistive divider to give a slope
of 3.75 V/V rms. In Figure 49, the op amp’s gain of two
increases the slope to 15 V/V rms. Using other resistor values,
the slope can be changed to an arbitrary value. The AD8031
rail-to-rail op amp, used in these example, can swing from 50 mV to 4.95 V on a single 5 V supply and operate at supply voltages down to 2.7 V. If high output current is required
(>10 mA), the AD8051, which also has rail-to- rail capability,
can be used down to a supply voltage of 3 V. It can deliver up to 45 mA of output current. Figure 49. Output Buffering Options, Slope of 15 V/V rms Figure 50. Output Buffering Options, Slope of 3.75 V/V rms Figure 51. Output Buffering Options, Slope of 7.5 V/V rms OUTPUT REFERENCE TEMPERATURE DRIFT
COMPENSATION
The error due to low temperature drift of the AD8361 can be
reduced if the temperature is known. Many systems incorporate
a temperature sensor; the output of the sensor is typically
digitized, facilitating a software correction. Using this information, only a two-point calibration at ambient is
required. The output voltage of the AD8361 at ambient (25°C) can be expressed by the equation OUT VIN GAIN V
where GAIN is the conversion gain in V/V rms and VOS is the
extrapolated output voltage for an input level of 0 V. GAIN and
VOS (also referred to as intercept and output reference) can be calculated at ambient using a simple two-point calibration by measuring the output voltages for two specific input levels.
Calibration at roughly 35 mV rms (−16 dBm) and 250 mV rms (+1 dBm) is recommended for maximum linear dynamic range.
However, alternative levels and ranges can be chosen to suit the
application. GAIN and VOS are then calculated using the equations
IN2 IN1
OUT2 OUT1
V V
V V
GAIN
OS OUT1 VIN1 GAIN V V
Both GAIN and VOS drift over temperature. However, the drift
of VOS has a bigger influence on the error relative to the output.
This can be seen by inserting data from Figure 18 and Figure 21 (intercept drift and conversion gain) into the equation for VOUT.
These plots are consistent with Figure 14 and Figure 15, which
show that the error due to temperature drift decreases with increasing input level. This results from the offset error having a
diminishing influence with increasing level on the overall
measurement error. From Figure 18, the average intercept drift is 0.43 mV/°C from −40°C to +25°C and 0.17 mV/°C from +25°C to +85°C. For a
less rigorous compensation scheme, the average drift over the
complete temperature range can be calculated as
C /V0.000304
C 40C85
V 0.028V0.010
C /V
DRIFTVOS
With the drift of VOS included, the equation for VOUT becomes
VOUT = (GAIN × VIN) + VOS + DRIFTVOS × (TEMP − 25°C)
0.01F 100pF
0.01F
AD8361
VOUT
VPOS
COMM PWDN
5k
5k
5V
AD8031 15V/V rms
01088-C-049
0.01F 100pF
0.01F
AD8361
VOUT
VPOS
COMM PWDN
5V
5k AD8031 3.75V/V rms
5k
10k
01088-C-050
0.01F 100pF
0.01F
AD8361
VOUT
VPOS
COMM PWDN
5V
AD8031 7.5V/V rms
01088-C-051
Data Sheet AD8361
Rev. D | Page 17 of 24
The equation can be rewritten to yield a temperature compensated value for VIN:
()()GAINTEMPDRIFTVVVVOSOSOUTINC25°−×−−=
Figure 52 shows the output voltage and error (in dB) as a function of input level for a typical device (note that output voltage is plotted on a logarithmic scale). Figure 53 shows the error in the calculated input level after the temperature compensation algorithm has been applied. For a supply voltage of 5 V, the part exhibits a worst-case linearity error over temperature of approximately ±0.3 dB over a dynamic range of 35 dB.
Figure 52. Typical Output Voltage and Error vs. Input Level, 800 MHz, VPOS = 5 V
Figure 53. Error after Temperature Compensation of Output Reference,800 MHz, VPOS = 5 V
Extended Frequency Characterization
Although the AD8361 was originally intended as a power measurement and control device for cellular wireless applications, the AD8361 has useful performance at higher frequencies. Typical applications may include MMDS, LMDS, WLAN, and other noncellular activities.
In order to characterize the AD8361 at frequencies greater than 2.5 GHz, a small collection of devices were tested. Dynamic range, conversion gain, and output intercept were measured at several frequencies over a temperature range of −30°C to +80°C. Both CW and 64 QAM modulated input wave forms were used in the characterization process in order to access varying peak-to-average waveform performance.
The dynamic range of the device is calculated as the input power range over which the device remains within a permissible error margin to the ideal transfer function. Devices were tested over frequency and temperature. After identifying an acceptable error margin for a given application, the usable dynamic measurement range can be identified using the plots in Figure 54 through Figure 57. For instance, for a 1 dB error margin and a modulated carrier at 3 GHz, the usable dynamic range can be found by inspecting the 3 GHz plot of Figure 57. Note that the −30°C curve crosses the −1 dB error limit at −17 dBm. For a 5 V supply, the maximum input power should not exceed 6 dBm in order to avoid compression. The resultant usable dynamic range is therefore
6 dBm − (−17 dBm)
or 23 dBm over a temperature range of −30°C to +80°C.
Figure 54. Transfer Function and Error Plots Measured at 1.5 GHz for a 64 QAM Modulated Signal
PIN (dBm)2.5–250–20–15–10–51.02.01.50.5ERROR (
dB)510+25°C–40°C0–0.5–1.0–1.5–2.0–2.50.1101.0VOUT (
V)+85°C01088-C-052PIN (dBm)–250–20–15–10–51.02.01.50.5ERROR (
dB)5100–0.5–1.0–1.5–2.0–2.5+25°C–40°C+85°C–3.0–3001088-C-053PIN (dBm)2.5–25ERROR (
dB)2.01.51.00.50–0.5–1.0–1.5–2.0–2.5–20–15–10–505101010.1VOUT (
V)+80°C+25°C–30°C01088-0-054
AD8361 Data Sheet
Rev. D | Page 18 of 24
Figure 55. Transfer Function and Error Plots Measured at 2.5 GHz for a 64 QAM Modulated Signal
Figure 56. Transfer Function and Error Plots Measured at 2.7 GHz for a 64 QAM Modulated Signal
Figure 57. Transfer Function and Error Plots Measured at 3.0 GHz for a 64 QAM Modulated Signal
Figure 58. Error from CW Linear Reference vs. Input Drive Level for CW and 64 QAM Modulated Signals at 3.0 GHz
Figure 59. Conversion Gain vs. Frequency for a Typical Device, Supply 3 V, Ground Reference Mode
The transfer functions and error for a CW input and a 64 QAM input waveform is shown in Figure 58. The error curve is generated from a linear reference based on the CW data. The increased crest factor of the 64 QAM modulation results in a decrease in output from the AD8361. This decrease in output is a result of the limited bandwidth and compression of the internal gain stages. This inaccuracy should be accounted for in systems where varying crest factor signals need to be measured.
The conversion gain is defined as the slope of the output voltage vs. the input rms voltage. An ideal best fit curve can be found for the measured transfer function at a given supply voltage and temperature. The slope of the ideal curve is identified as the conversion gain for a particular device. The conversion gain relates the measurement sensitivity of the AD8361 to the rms input voltage of the RF waveform. The conversion gain was measured for a number of devices over a temperature range of −30°C to +80°C. The conversion gain for a typical device is shown in Figure 59. Although the conversion gain tends to decrease with increasing frequency, the AD8361 provides measurement capability at frequencies greater than 2.5 GHz. However, it is necessary to calibrate for a given application to
PIN (dBm)2.5–25ERROR (
dB)2.01.51.00.50–0.5–1.0–1.5–2.0–2.5–20–15–10–505101010.1VOUT (
V)+80°C+25°C–30°C01088-C-055PIN (dBm)2.5–25ERROR (
dB)2.01.51.00.50–0.5–1.0–1.5–2.0–2.5–20–15–10–505101010.1VOUT (
V)+80°C+25°C–30°C01088-C-056PIN (dBm)2.5–25ERROR (
dB)2.01.51.00.50–0.5–1.0–1.5–2.0–2.5–20–15–10–550101010.1VOUT (
V)+80°C+25°C–30°C01088-C-057PIN (dBm)2.5–25ERROR (
dB)2.01.51.00.50–0.5–1.0–1.5–2.0–2.5–20–15–10–550101010.1VOUT (
V)CW64 QAM01088-C-058FREQUENCY (MHz)8.0100CONVERSION GAIN (
V/V
rms)7.57.06.56.05.55.020040080012001600220025002700300001088-C-059
Data Sheet AD8361
Rev. D | Page 19 of 24
accommodate for the change in conversion gain at higher frequencies.
Dynamic Range Extension for the AD8361
The accurate measurement range of the AD8361 is limited by internal dc offsets for small input signals and by square law conformance errors for large signals. The measurement range may be extended by using two devices operating at different signal levels and then choosing only the output of the device that provides accurate results at the prevailing input level.
Figure 60 depicts an implementation of this idea. In this circuit, the selection of the output is made gradually over an input level range of about 3 dB in order to minimize the impact of imperfect matching of the transfer functions of the two AD8361s. Such a mismatch typically arises because of the variation of the gain of the RF preamplifier U1 and both the gain and slope variations of the AD8361s with temperature.
One of the AD8361s (U2) has a net gain of about 14 dB preceding it and therefore operates most accurately at low input signal levels. This is referred to as the weak signal path. U4, on the other hand, does not have the added gain and provides accurate response at high levels. The output of U2 is attenuated by R1 in order to cancel the effect of U2’s preceding gain so that the slope of the transfer function (as seen at the slider of R1) is the same as that of U4 by itself.
The circuit comprising U3, U5, and U6 is a crossfader, in which the relative gains of the two inputs are determined by the output currents of a fuzzy comparator made from Q1 and Q2. Assuming that the slider of R2 is at 2.5 V dc, the fuzzy comparator commands full weighting of the weak signal path when the output of U2 is below about 2.0 V dc, and full weighting of the strong signal path when the output of U3 exceeds about 3.0 V dc. U3 and U5 are OTAs (operational transconductance amplifiers).
Figure 60. Range Extender Application
87651234AD83610.1μF5V100pF5V0.01μF68ΩU2ERA-320dBU1RFC270Ω12V6dBPAD6dBSPLITTERRFINPUT12V20kΩ1kΩ1kΩ5VR210kΩQ22N3906Q12N390616kΩR15kΩCA3080+12V–5VU320kΩCA3080+12V–5VU52356235620kΩ1MΩR310kΩ–5V+5V12kΩ87651234AD83610.1μF5V100pF5V0.01μF68ΩU4AD8205VU6238.2nF476VOUT100Ω01088-C-060
AD8361 Data Sheet
Rev. D | Page 20 of 24
U6 provides feedback to linearize the inherent tanh transfer function of the OTAs. When one OTA or the other is fully selected, the feedback is very effective. The active OTA has zero differential input; the inactive one has a potentially large differential input, but this does not matter because the inactive OTA is not contributing to the output. However, when both OTAs are active to some extent, and the two signal inputs to the crossfader are different, it is impossible to have zero differential inputs on the OTAs. In this event, the crossfader admittedly generates distortion because of the nonlinear transfer function of the OTAs. Fortunately, in this application, the distortion is not very objectionable for two reasons:
1. The mismatch in input levels to the crossfader is never large enough to evoke very much distortion because the AD8361s are reasonably well-behaved.
2. The effect of the distortion in this case is merely to distort the otherwise nearly linear slope of the transition between the crossfader’s two inputs.
Figure 61. Slope Adjustment
This circuit has three trimmable potentiometers. The suggested setup procedure is as follows:
3. Preset R3 at midrange.
4. Set R2 so that its slider’s voltage is at the middle of the desired transition zone (about 2.5 V dc is recommended).
5. Set R1 so that the transfer function’s slopes are equal on both sides of the transition zone. This is perhaps best accomplished by making a plot of the overall transfer function (using linear voltage scales for both axes) to assess the match in slope between one side of the transition region and the other (see Figure 61). Note: it may be helpful to adjust R3 to remove any large misalignment in the transfer function in order to correctly perceive slope differences.
6. Finally (re)adjust R3 as required to remove any remaining misalignment in the transfer function (see Figure 62).
Figure 62. Intercept Adjustment
In principle, this method could be extended to three or more AD8361s in pursuit of even more measurement range. However, it is very important to pay close attention to the matter of not excessively overdriving the AD8361s in the weaker signal paths under strong signal conditions.
Figure 63 shows the extended range transfer function at multiple temperatures. The discontinuity at approximately 0.2 V rms arises as a result of component temperature dependencies. Figure 64 shows the error in dB of the range extender circuit at ambient temperature. For a 1 dB error margin, the range extender circuit offers 38 dB of measurement range.
Figure 63. Output vs. Drive Level over Temperature for a 1 GHz 64 QAM Modulated Signal
Figure 64. Error from Linear Reference at 25°C for a 1 GHz 64 QAM Modulated Signal
VOUTm1m2m1≠m2DIFFERINGSLOPES INDICATEMALADJUSTMENTOF R1RF INPUT LEVEL– V rmsTRANSITIONREGION01088-C-061VOUTRF INPUT LEVEL– V rmsTRANSITIONREGIONMISALIGNMENT INDICATESMALADJUSTMENT OF R301088-C-062DRIVE LEVEL (V rms)3.02.5001.00.2VOUT (
V)0.40.60.82.01.51.00.5REF LINE+80°C–30°C01088-C-063DRIVE LEVEL (dBm)5–32ERROR (
dB)43210–1–2–3–4–5–27–22–17–12–7–2381301088-C-064
Data Sheet AD8361
Rev. D | Page 21 of 24
EVALUATION BOARD
Figure 65 and Figure 68 show the schematic of the AD8361 evaluation board. Note that uninstalled components are drawn in as dashed. The layout and silkscreen of the component side are shown in Figure 66, Figure 67, Figure 69, and Figure 70. The board is powered by a single supply in the 2.7 V to 5.5 V range. The power supply is decoupled by 100 pF and 0.01 μF capacitors. Additional decoupling, in the form of a series resistor or inductor in R6, can also be added. Table 8 details the various configuration options of the evaluation board.
Table 8. Evaluation Board Configuration Options
Component
Function
Default Condition
TP1, TP2
Ground and Supply Vector Pins.
Not Applicable
SW1
Device Enable. When in Position A, the PWDN pin is connected to +VS and the AD8361 is in power-down mode. In Position B, the PWDN pin is grounded, putting the device in operating mode.
SW1 = B
SW2/SW3
Operating Mode. Selects either ground reference mode, internal reference mode or supply reference mode. See Table 4 for more details.
SW2 = A, SW3 = B (Ground Reference Mode)
C1, R2
Input Coupling. The 75 Ω resistor in Position R2 combines with the AD8361’s internal input impedance to give a broadband input impedance of around 50 Ω. For more precise matching at a particular frequency, R2 can be replaced by a different value (see Input Coupling and Matching and Figure 43 through Figure 46).
Capacitor C1 ac couples the input signal and creates a high-pass input filter whose corner frequency is equal to approximately 8 MHz. C1 can be increased for operation at lower frequencies. If resistive attenuation is desired at the input, series resistor R1, which is nominally 0 Ω, can be replaced by an appropriate value.
R2 = 75 Ω (Size 0402) C1 = 100 pF (Size 0402)
C2, C3, R6
Power Supply Decoupling. The nominal supply decoupling of 0.01 μF and 100 pF. A series inductor or small resistor can be placed in R6 for additional decoupling.
C2 = 0.01 μF (Size 0402) C3 = 100 pF (Size 0402) R6 = 0 Ω (Size 0402)
C5
Filter Capacitor. The internal 50 pF averaging capacitor can be augmented by placing a capacitance in C5.
C5 = 1 nF (Size 0603)
C4, R5
Output Loading. Resistors and capacitors can be placed in C4 and R5 to load test V rms.
C4 = R5 = Open (Size 0603)
AD8361 Data Sheet
Rev. D | Page 22 of 24
Figure 65. Evaluation Board Schematic, MSOP
Figure 66. Layout of Component Side, MSOP
Figure 67. Silkscreen of Component Side, MSOP
Figure 68. Evaluation Board Schematic, SOT-23
Figure 69. Layout of the Component Side, SOT-23
Figure 70. Silkscreen of the Component Side, SOT-23
12348765AD8361VPOSIREFRFINPWDNSREFVRMSFLTRCOMMC20.01μFC3100pFC1100pFC5RFINVrmsVPOSVSSW2VSSW3SW1ABAB1nFABTP2TP1VPOSVPOSR275ΩR40ΩR60ΩC4(OPEN)R5(OPEN)01088-C-06501088-C-06601088-C-067R275ΩR750ΩR40ΩC20.01μFC1100pFC3100pFC51nFJ2J3J1TP2C4(OPEN)R5(OPEN)AD8361VPOSRFINPWDNVRMSFLTRCOMMTP1SW1123VPOS12365401088-C-06801088-C-06901088-C-070
Data Sheet AD8361
Rev. D | Page 23 of 24
Problems caused by impedance mismatch may arise using the
evaluation board to examine the AD8361 performance. One way to reduce these problems is to put a coaxial 3 dB attenuator on the RFIN SMA connector. Mismatches at the source, cable,
and cable interconnection, as well as those occurring on the
evaluation board, can cause these problems. A simple (and common) example of such a problem is triple
travel due to mismatch at both the source and the evaluation board. Here the signal from the source reaches the evaluation board and mismatch causes a reflection. When that reflection reaches the source mismatch, it causes a new reflection, which
travels back to the evaluation board, adding to the original
signal incident at the board. The resultant voltage varies with both cable length and frequency dependence on the relative phase of the initial and reflected signals. Placing the 3 dB pad at
the input of the board improves the match at the board and thus reduces the sensitivity to mismatches at the source. When such precautions are taken, measurements are less sensitive to cable
length and other fixture issues. In an actual application when
the distance between AD8361 and source is short and well defined, this 3 dB attenuator is not needed. CHARACTERIZATION SETUPS Equipment The primary characterization setup is shown in Figure 72. The signal source used was a Rohde & Schwarz SMIQ03B, version
3.90HX. The modulated waveforms used for IS95 reverse link,
IS95 nine active channels forward (forward link 18 setting), and W-CDMA 4-channel and 15-channel were generated using the default settings coding and filtering. Signal levels were
calibrated into a 50 Ω impedance.
Analysis
The conversion gain and output reference are derived using the coefficients of a linear regression performed on data collected in its central operating range (35 mV rms to 250 mV rms). This
range was chosen to avoid areas of operation where offset
distorts the linear response. Error is stated in two forms error from linear response to CW waveform and output delta from 2°C performance. The error from linear response to CW waveform is the
difference in output from the ideal output defined by the
conversion gain and output reference. This is a measure of both the linearity of the device response to both CW and modulated waveforms. The error in dB uses the conversion gain multiplied by the input as its reference. Error from linear response to CW waveform is not a measure of absolute accuracy, since it is
calculated using the gain and output reference of each device.
However, it does show the linearity and effect of modulation on
the device response. Error from 25°C performance uses the
performance of a given device and waveform type as the
reference; it is predominantly a measure of output variation with temperature.
Figure 71. Characterization Board Figure 72. Characterization Setup 1
2
3
4
8
7
6
5
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
C1
0.1F
R1
75
RFIN
C3
C4
0.1F
C2
100pF
IREF
PWDN
VPOS SREF
VRMS
01088-C-071
AD8361
CHARACTERIZATION
BOARD
RFIN
PRUP +VS SREF IREF
VRMS
SMIQ038B RF SIGNAL DC OUTPUT
RF SOURCE
IEEE BUS
PC CONTROLLER DC MATRIX / DC SUPPLIES / DMM
DC SOURCES
3dB
ATTENUATOR
01088-C-072
AD8361 Data Sheet
Rev. D | Page 24 of 24
OUTLINE DIMENSIONS
Figure 73. 8-Lead Mini Small Outline Package [MSOP] (RM-8)
Dimensions shown in millimeters
Figure 74. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding AD8361ARM −40°C to +85°C 8-Lead MSOP, Tube RM-8 J3A
AD8361ARM-REEL7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 J3A
AD8361ARMZ −40°C to +85°C 8-Lead MSOP, Tube RM-8 J3A
AD8361ARMZ-REEL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 J3A
AD8361ARMZ-REEL7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 J3A
AD8361ARTZ-RL7 −40°C to +85°C 6-Lead SOT-23, 7" Tape and Reel RJ-6 Q0V
AD8361-EVALZ Evaluation Board MSOP
AD8361ART-EVAL Evaluation Board SOT-23-6L
1 Z = RoHS Compliant Part.
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX 0.95
0.85
0.75
0.15
0.05
10-07-2009-B
COMPLIANTTOJEDECSTANDARDSMO-178-AB
10°
4°
0°
SEATING
PLANE
1.90
BSC
0.95BSC
0.60
BSC
6 5
1 2 3
4
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0.15MAX
0.05MIN
1.45MAX
0.95MIN
0.20MAX
0.08MIN
0.50MAX
0.30MIN
0.55
0.45
0.35
PIN1
INDICATOR
12-16-2008-A
©2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01088–0–3/14(D)
Fast, Voltage-Out, DC to 440 MHz,
95 dB Logarithmic Amplifier
AD8310
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.
FEATURES
Multistage demodulating logarithmic amplifier
Voltage output, rise time <15 ns
High current capacity: 25 mA into grounded RL
95 dB dynamic range: −91 dBV to +4 dBV
Single supply of 2.7 V min at 8 mA typ
DC to 440 MHz operation, ±0.4 dB linearity
Slope of +24 mV/dB, intercept of −108 dBV
Highly stable scaling over temperature
Fully differential dc-coupled signal path
100 ns power-up time, 1 mA sleep current
APPLICATIONS
Conversion of signal level to decibel form
Transmitter antenna power measurement
Receiver signal strength indication (RSSI)
Low cost radar and sonar signal processing
Network and spectrum analyzers
Signal-level determination down to 20 Hz
True-decibel ac mode for multimeters
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD8310 is a complete, dc to 440 MHz demodulating logarithmic amplifier (log amp) with a very fast voltage mode output, capable of driving up to 25 mA into a grounded load in under 15 ns. It uses the progressive compression (successive detection) technique to provide a dynamic range of up to 95 dB to ±3 dB law conformance or 90 dB to a ±1 dB error bound up to 100 MHz. It is extremely stable and easy to use, requiring no significant external components. A single-supply voltage of 2.7 V to 5.5 V at 8 mA is needed, corresponding to a power consumption of only 24 mW at 3 V. A fast-acting CMOS-compatible enable pin is provided.
Each of the six cascaded amplifier/limiter cells has a small-signal gain of 14.3 dB, with a −3 dB bandwidth of 900 MHz. A total of nine detector cells are used to provide a dynamic range that extends from −91 dBV (where 0 dBV is defined as the amplitude of a 1 V rms sine wave), an amplitude of about ±40 μV, up to +4 dBV (or ±2.2 V). The demodulated output is accurately scaled, with a log slope of 24 mV/dB and an intercept of −108 dBV. The scaling parameters are supply- and temperature-independent.
The fully differential input offers a moderately high impedance (1 kΩ in parallel with about 1 pF). A simple network can match the input to 50 Ω and provide a power sensitivity of −78 dBm to +17 dBm. The logarithmic linearity is typically within ±0.4 dB up to 100 MHz over the central portion of the range, but it is somewhat greater at 440 MHz. There is no minimum frequency limit; the AD8310 can be used down to low audio frequencies. Special filtering features are provided to support this wide range.
The output voltage runs from a noise-limited lower boundary of 400 mV to an upper limit within 200 mV of the supply voltage for light loads. The slope and intercept can be readily altered using external resistors. The output is tolerant of a wide variety of load conditions and is stable with capacitive loads of 100 pF.
The AD8310 provides a unique combination of low cost, small size, low power consumption, high accuracy and stability, high dynamic range, a frequency range encompassing audio to UHF, fast response time, and good load-driving capabilities, making this product useful in numerous applications that require the reduction of a signal to its decibel equivalent.
The AD8310 is available in the industrial temperature range of −40°C to +85°C in an 8-lead MSOP package.
AD8310
Rev. F | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ........................................................................ 9
Progressive Compression ............................................................ 9
Slope and Intercept Calibration ................................................ 10
Offset Control ............................................................................. 10
Product Overview ........................................................................... 11
Enable Interface .......................................................................... 11
Input Interface ............................................................................ 11
Offset Interface ........................................................................... 12
Output Interface ......................................................................... 12
Using the AD8310 .......................................................................... 14
Basic Connections ...................................................................... 14
Transfer Function in Terms of Slope and Intercept ............... 15
dBV vs. dBm ............................................................................... 15
Input Matching ........................................................................... 15
Narrow-Band Matching ............................................................ 16
General Matching Procedure .................................................... 16
Slope and Intercept Adjustments ............................................. 17
Increasing the Slope to a Fixed Value ...................................... 17
Output Filtering .......................................................................... 18
Lowering the High-Pass Corner Frequency of the Offset Compensation Loop .................................................................. 18
Applications Information .............................................................. 19
Cable-Driving ............................................................................. 19
DC-Coupled Input ..................................................................... 19
Evaluation Board ............................................................................ 20
Die Information .............................................................................. 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
6/10—Rev. E to Rev. F Added Die Information Section ................................................... 22 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23
6/05—Rev. D to Rev. E Changes to Figure 6 .......................................................................... 6 Change to Basic Connections Section ......................................... 14 Changes to Equation 10 ................................................................. 17 Changes to Ordering Guide .......................................................... 22
10/04—Rev. C to Rev. D Format Updated .................................................................. Universal Typical Performance Characteristics Reordered .......................... 6 Changes to Figure 41 and Figure 42 ............................................. 20
7/03—Rev. B to Rev. C Replaced TPC 12 ............................................................................... 5 Change to DC-Coupled Input Section ........................................ 14 Replaced Figure 20 ......................................................................... 15 Updated Outline Dimensions ....................................................... 16
2/03—Rev. A to Rev. B Change to Evaluation Board Section ........................................... 15 Change to Table III ......................................................................... 16 Updated Outline Dimensions ....................................................... 16
1/00—Rev. 0 to Rev. A
10/99—Revision 0: Initial Version
AD8310
Rev. F | Page 3 of 24
SPECIFICATIONS
TA = 25°C, VS = 5 V, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT STAGE
Inputs INHI, INLO
Maximum Input1
Single-ended, p-p
±2.0
±2.2
V
4
dBV
Equivalent Power in 50 Ω
Termination resistor of 52.3 Ω
17
dBm
Differential drive, p-p
20
dBm
Noise Floor
Terminated 50 Ω source
1.28
nV/√Hz
Equivalent Power in 50 Ω
440 MHz bandwidth
−78
dBm
Input Resistance
From INHI to INLO
800
1000
1200
Ω
Input Capacitance
From INHI to INLO
1.4
pF
DC Bias Voltage
Either input
3.2
V
LOGARITHMIC AMPLIFIER
Output VOUT
±3 dB Error Dynamic Range
From noise floor to maximum input
95
dB
Transfer Slope
10 MHz ≤ f ≤ 200 MHz
22
24
26
mV/dB
Overtemperature, −40°C < TA < +85°C
20
26
mV/dB
Intercept (Log Offset)2
10 MHz ≤ f ≤ 200 MHz
−115
−108
−99
dBV
Equivalent dBm (re 50 Ω)
−102
−95
−86
dBm
Overtemperature, −40°C ≤ TA ≤ +85°C
−120
−96
dBV
Equivalent dBm (re 50 Ω)
−107
−83
dBm
Temperature
sensitivity
−0.04
dB/°C
Linearity Error (Ripple)
Input from −88 dBV (−75 dBm) to +2 dBV (+15 dBm)
±0.4
dB
Output Voltage
Input = −91 dBV (−78 dBm)
0.4
V
Input = 9 dBV (22 dBm)
2.6
V
Minimum Load Resistance, RL
100
Ω
Maximum Sink Current
0.5
mA
Output Resistance
0.05
Ω
Video Bandwidth
25
MHz
Rise Time (10% to 90%)
Input level = −43 dBV (−30 dBm), RL ≥ 402 Ω, CL ≤ 68 pF
15
ns
Input level = −3 dBV (+10 dBm), RL ≥ 402 Ω, CL ≤ 68 pF
20
ns
Fall Time (90% to 10%)
Input level = −43 dBV (−30 dBm), RL ≥ 402 Ω, CL ≤ 68 pF
30
ns
Input level = −3 dBV (+10 dBm), RL ≥ 402 Ω, CL ≤ 68 pF
40
ns
Output Settling Time to 1%
Input level = −13 dBV (0 dBm), RL ≥ 402 Ω, CL ≤ 68 pF
40
ns
POWER INTERFACES
Supply Voltage, VPOS
2.7
5.5
V
Quiescent Current
Zero signal
6.5
8.0
9.5
mA
Overtemperature
−40°C < TA < +85°C
5.5
8.5
10
mA
Disable Current
0.05
μA
Logic Level to Enable Power
High condition, −40°C < TA < +85°C
2.3
V
Input Current When High
3 V at ENBL
35
μA
Logic Level to Disable Power
Low condition, −40°C < TA < +85°C
0.8
V
1 The input level is specified in dBV, because logarithmic amplifiers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of 1 V rms. A power level of 0 dBm (1 mW) in a 50 Ω termination corresponds to an input of 0.2236 V rms. Therefore, the relationship between dBV and dBm is a fixed offset of 13 dBm in the special case of a 50 Ω termination.
2 Guaranteed but not tested; limits are specified at six sigma levels.
AD8310
Rev. F | Page 4 of 24
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Supply Voltage, VS
7.5 V
Input Power (re 50 Ω), Single-Ended
18 dBm
Differential Drive
22 dBm
Internal Power Dissipation
200 mW
θJA
200°C/W
Maximum Junction Temperature
125°C
Operating Temperature Range
−40°C to +85°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature (Soldering 60 sec)
300°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
AD8310
Rev. F | Page 5 of 24
01084-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
INLO1INHI8
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
INLO
One of Two Balanced Inputs. Biased roughly to VPOS/2.
2
COMM
Common Pin. Usually grounded.
3
OFLT
Offset Filter Access. Nominally at about 1.75 V.
4
VOUT
Low Impedance Output Voltage. Carries a 25 mA maximum load.
5
VPOS
Positive Supply. 2.7 V to 5.5 V at 8 mA quiescent current.
6
BFIN
Buffer Input. Used to lower postdetection bandwidth.
7
ENBL
CMOS Compatible Chip Enable. Active when high.
8
INHI
Second of Two Balanced Inputs. Biased roughly to VPOS/2.
AD8310
Rev. F | Page 6 of 24
TYPICAL PERFORMANCE CHARACTERISTICS 3.00RSSI OUTPUT (
V)2.52.01.51.00.5TA = +85°CTA = +25°CTA =–40°C01084-011
Figure 3. RSSI Output vs. Input Level, 100 MHz Sine Input at TA = −40°C, +25°C, and +85°C, Single-Ended Input
3.0RSSI OUTPUT (
V)2.52.01.51.00.5010MHz50MHz100MHz
Figure 4. RSSI Output vs. Input Level at TA = 25°C for Frequencies of 10 MHz, 50 MHz, and 100 MHz 3.00RSSI OUTPUT (
V)2.52.01.51.00.5200MHz300MHz440MHz
Figure 5. RSSI Output vs. Input Level at TA = 25°C for Frequencies of 200 MHz, 300 MHz, and 440 MHz
Figure 6. Log Linearity of RSSI Output vs. Input Level, 100 MHz Sine Input at TA = −40°C, +25°C, and +85°C
Figure 7. Log Linearity of RSSI Output vs. Input Level at TA = 25°C for Frequencies of 10 MHz, 50 MHz, and 100 MHz
Figure 8. Log Linearity of RSSI Output vs. Input Level at TA = 25°C for Frequencies of 200 MHz, 300 MHz, and 440 MHz
AD8310
Rev. F | Page 7 of 24
500mV PERVERTICALDIVISIONVOUT100pF3300pFGROUND REFERENCE0.01μF
Figure 9. Small-Signal AC Response of RSSI Output with External BFIN Capacitance of 100 pF, 3300 pF, and 0.01 μF GND REFERENCEINPUT 500mV PERVERTICALDIVISIONVOUT154Ω100Ω200Ω
Figure 10. Large-Signal RSSI Pulse Response with CL = 100 pF and RL = 100 Ω, 154 Ω, and 200 Ω 100ns PERHORIZONTALDIVISIONGND REFERENCEINPUT500mV PERVERTICALDIVISIONVOUT
Figure 12. Small-Signal RSSI Pulse Response with RL = 402 Ω and CL = 68 pF
Figure 13. Large-Signal RSSI Pulse Response with RL = 100 Ω and CL = 33 pF, 68 pF, and 100 pF
Figure 11. RSSI Pulse Response with RL = 402 Ω and CL = 68 pF, for Inputs Stepped from 0 dBV to −33 dBV, −23 dBV, −13 dBV, and −3 dBV 01084-008
Figure 14. Small-Signal RSSI Pulse Response with RL = 50 Ω and Back Termination of 50 Ω (Total Load = 100 Ω)
AD8310 100SUPPLY CURRENT (
mA)1010.10.010.0010.0001TA = +85°CTA = +25°C
Figure 18. Power-On/Off Response Time with RF Input of −83 dBV to −3 dBV
Figure 15. Supply Current vs. Enable Voltage at TA = −40°C, +25°C, and +85°C 3029RSSI SLOPE (
mV/dB)24232226252827
Figure 16. RSSI Slope vs. Frequency
Figure 19. RSSI Intercept vs. Frequency INTERCEPT (dBV)0–115–113 3010COUNT252015 3540NORMAL(23.6584,0.308728)
Figure 17. Transfer Slope Distribution, VS = 5 V, Frequency = 100 MHz, 25°C –111–109–107–105–103–101–99–97
Figure 20. Intercept Distribution, VS = 5 V, Frequency = 100 MHz, 25°C
AD8310
Rev. F | Page 9 of 24
THEORY OF OPERATION
Logarithmic amplifiers perform a more complex operation than classical linear amplifiers, and their circuitry is significantly different. A good grasp of what log amps do and how they do it can help users avoid many pitfalls in their applications. For a complete discussion of the theory, see the AD8307 data sheet.
The essential purpose of a log amp is not to amplify (though amplification is needed internally), but to compress a signal of wide dynamic range to its decibel equivalent. It is, therefore, a measurement device. An even better term might be logarithmic converter, because the function is to convert a signal from one domain of representation to another via a precise nonlinear transformation:
⎞⎛INV (1)
where: VOUT is the output voltage. VY is the slope voltage. The logarithm is usually taken to base ten, in which case VY is also the volts-per-decade. VIN is the input voltage. VX is the intercept voltage.
Log amps implicitly require two references (here VX and VY) that determine the scaling of the circuit. The accuracy of a log amp cannot be any better than the accuracy of its scaling references. In the AD8310, these are provided by a band gap reference. VOUT5VY4VY3VY2VYVY VOUT =0LOGVINVSHIFTLOWER INTERCEPTVIN=10–2VX–40dBcVIN=102VX+40dBcVIN=104VX+80dBcVIN =VX0dBc
Figure 21. General Form of the Logarithmic Function
While Equation 1, plotted in Figure 21, is fundamentally correct, a different formula is appropriate for specifying the calibration attributes or demodulating log amps like the AD8310, operating in RF applications with a sine wave input.
(2)
where: VOUT is the demodulated and filtered baseband (video or RSSI) output. VSLOPE is the logarithmic slope, now expressed in V/dB (25 mV/dB for the AD8310). PIN is the input power, expressed in dB relative to some reference power level. PO is the logarithmic intercept, expressed in dB relative to the same reference level.
A widely used reference in RF systems is dB above 1 mW in 50 Ω, a level of 0 dBm. Note that the quantity (PIN − PO) is dB. The logarithmic function disappears from the formula, because the conversion has already been implicitly performed in stating the input in decibels. This is strictly a concession to popular convention. Log amps manifestly do not respond to power (tacitly, power absorbed at the input), but rather to input voltage. The input is specified in dBV (decibels with respect to 1 V rms) throughout this data sheet. This is more precise, although still incomplete, because the signal waveform is also involved. Many users specify RF signals in terms of power (usually in dBm/50 Ω), and this convention is used in this data sheet when specifying the performance of the AD8310.
PROGRESSIVE COMPRESSION
High speed, high dynamic-range log amps use a cascade of nonlinear amplifier cells to generate the logarithmic function as a series of contiguous segments, a type of piecewise linear technique. The AD8310 employs six cells in its main signal path, each having a small-signal gain of 14.3 dB (×5.2) and a −3 dB bandwidth of about 900 MHz. The overall gain is about 20,000 (86 dB), and the overall bandwidth of the chain is approximately 500 MHz, resulting in a gain-bandwidth product (GBW) of 10,000 GHz, about a million times that of a typical op amp. This very high GBW is essential to accurate operation under small-signal conditions and at high frequencies. The AD8310 exhibits a logarithmic response down to inputs as small as 40 μV at 440 MHz.
Progressive compression log amps either provide a baseband video response or accept an RF input and demodulate this signal to develop an output that is essentially the envelope of the input represented on a logarithmic or decibel scale. The AD8310 is the latter kind. Demodulation is performed in a total of nine detector cells. Six are associated with the amplifier stages, and three are passive detectors that receive a progres-sively attenuated fraction of the full input. The maximum signal frequency can be 440 MHz, but, because all the gain stages are dc-coupled, operation at very low frequencies is possible.
AD8310
Rev. F | Page 10 of 24
SLOPE AND INTERCEPT CALIBRATION
All monolithic log amps from Analog Devices use precision design techniques to control the logarithmic slope and intercept. The primary source of this calibration is a pair of accurate voltage references that provide supply- and temperature-independent scaling. The slope is set to 24 mV/dB by the bias chosen for the detector cells and the subsequent gain of the postdetector output interface. With this slope, the full 95 dB dynamic range can be easily accommodated within the output swing capacity, when operating from a 2.7 V supply. Intercept positioning at −108 dBV (−95 dBm re 50 Ω) has likewise been chosen to provide an output centered in the available voltage range.
Precise control of the slope and intercept results in a log amp with stable scaling parameters, making it a true measurement device as, for example, a calibrated received signal strength indicator (RSSI). In this application, the input waveform is invariably sinusoidal. The input level is correctly specified in dBV. It can alternatively be stated as an equivalent power, in dBm, but in this case, it is necessary to specify the impedance in which this power is presumed to be measured. In RF practice, it is common to assume a reference impedance of 50 Ω, in which 0 dBm (1 mW) corresponds to a sinusoidal amplitude of 316.2 mV (223.6 mV rms). However, the power metric is correct only when the input impedance is lowered to 50 Ω, either by a termination resistor added across INHI and INLO, or by the use of a narrow-band matching network.
Note that log amps do not inherently respond to power, but to the voltage applied to their input. The AD8310 presents a nominal input impedance much higher than 50 Ω (typically 1 kΩ at low frequencies). A simple input matching network can considerably improve the power sensitivity of this type of log amp. This increases the voltage applied to the input and, therefore, alters the intercept. For a 50 Ω reactive match, the voltage gain is about 4.8, and the whole dynamic range moves down by 13.6 dB. The effective intercept is a function of wave-form. For example, a square-wave input reads 6 dB higher than a sine wave of the same amplitude, and a Gaussian noise input reads 0.5 dB higher than a sine wave of the same rms value.
OFFSET CONTROL
In a monolithic log amp, direct coupling is used between the stages for several reasons. First, it avoids the need for coupling capacitors, which typically have a chip area at least as large as that of a basic gain cell, considerably increasing die size. Second, the capacitor values predetermine the lowest frequency at which the log amp can operate. For moderate values, this can be as high as 30 MHz, limiting the application range. Third, the parasitic back-plate capacitance lowers the bandwidth of the cell, further limiting the scope of applications.
However, the very high dc gain of a direct-coupled amplifier raises a practical issue. An offset voltage in the early stages of the chain is indistinguishable from a real signal. If it were as high as 400 μV, it would be 18 dB larger than the smallest ac signal (50 μV), potentially reducing the dynamic range by this amount. This problem can be averted by using a global feedback path from the last stage to the first, which corrects this offset in a similar fashion to the dc negative feedback applied around an op amp. The high frequency components of the feedback signal must, of course, be removed to prevent a reduction of the HF gain in the forward path.
An on-chip filter capacitor of 33 pF provides sufficient suppres-sion of HF feedback to allow operation above 1 MHz. The −3 dB point in the high-pass response is at 2 MHz, but the usable range extends well below this frequency. To further lower the frequency range, an external capacitor can be added at OFLT (Pin 3). For example, 300 pF lowers it by a factor of 10.
Operation at low audio frequencies requires a capacitor of about 1 μF. Note that this filter has no effect for input levels well above the offset voltage, where the frequency range would extend down to dc (for a signal applied directly to the input pins). The dc offset can optionally be nulled by adjusting the voltage on the OFLT pin (see the Applications Information section).
AD8310
Rev. F | Page 11 of 24
PRODUCT OVERVIEW
The AD8310 has six main amplifier/limiter stages. These six cells and their and associated gm styled full-wave detectors handle the lower two-thirds of the dynamic range. Three top-end detectors, placed at 14.3 dB taps on a passive attenuator, handle the upper third of the 95 dB range. The first amplifier stage provides a low noise spectral density (1.28 nV/√Hz). Biasing for these cells is provided by two references: one determines their gain, and the other is a band gap circuit that determines the logarithmic slope and stabilizes it against supply and temperature variations. The AD8310 can be enabled or disabled by a CMOS-compatible level at ENBL (Pin 7).
The differential current-mode outputs of the nine detectors are summed and then converted to single-sided form, nominally scaled 2 μA/dB. The output voltage is developed by applying this current to a 3 kΩ load resistor followed by a high speed gain-of-four buffer amplifier, resulting in a logarithmic slope of 24 mV/dB (480 mV/decade) at VOUT (Pin 4). The unbuffered voltage can be accessed at BFIN (Pin 6), allowing certain functional modifications such as the addition of an external postdemodulation filter capacitor and the alteration or adjustment of slope and intercept. +–VPOSINHIINLOCOMM38mA1.0kΩBAND GAP REFERENCEAND BIASINGSIX 14.3dB 900MHzAMPLIFIER STAGESNINE DETECTOR CELLSSPACED 14.3dBINPUT-OFFSETCOMPENSATION LOOP22μA/dBMIRROR3kΩ3kΩ1kΩCOMMCOMMENBLBFINVOUTOFLTENABLEBUFFERINPUTOUTPUTOFFSETFILTERAD8310SUPPLY+INPUT–INPUTCOMMON
Figure 22. Main Features of the AD8310
The last gain stage also includes an offset-sensing cell. This generates a bipolarity output current, if the main signal path exhibits an imbalance due to accumulated dc offsets. This current is integrated by an on-chip capacitor that can be increased in value by an off-chip component at OFLT (Pin 3). The resulting voltage is used to null the offset at the output of the first stage. Because it does not involve the signal input connections, whose ac-coupling capacitors otherwise introduce a second pole into the feedback path, the stability of the offset correction loop is assured.
The AD8310 is built on an advanced, dielectrically isolated, complementary bipolar process. In the following interface diagrams shown in Figure 23 to Figure 26, resistors labeled as R are thin-film resistors that have a low temperature coefficient of resistance (TCR) and high linearity under large-signal conditions. Their absolute tolerance is typically within ±20%. Similarly, capacitors labeled as C have a typical tolerance of ±15% and essentially zero temperature or voltage sensitivity. Most interfaces have additional small junction capacitances associated with them, due to active devices or ESD protection, which might not be accurate or stable. Component numbering in these interface diagrams is local.
ENABLE INTERFACE
The chip-enable interface is shown in Figure 23. The currents in the diode-connected transistors control the turn-on and turn-off states of the band gap reference and the bias generator. They are a maximum of 100 μA when ENBL is taken to 5 V under worst-case conditions. For voltages below 1 V, the AD8310 is disabled and consumes a sleep current of less than 1 μA. When tied to the supply or a voltage above 2 V, it is fully enabled. The internal bias circuitry is very fast (typically <100 ns for either off or on). In practice, however, the latency period before the log amp exhibits its full dynamic range is more likely to be limited by factors relating to the use of ac coupling at the input or the settling of the offset-control loop (see the following sections).
Figure 23. Enable Interface
INPUT INTERFACE
Figure 24 shows the essentials of the input interface. CP and CM are parasitic capacitances, and CD is the differential input capacitance, largely due to Q1 and Q2. In most applications, both input pins are ac-coupled. The S switches close when enable is asserted. When disabled, bias current IE is shut off and the inputs float; therefore, the coupling capacitors remain charged. If the log amp is disabled for long periods, small leakage currents discharge these capacitors. Then, if they are poorly matched, charging currents at power-up can generate a transient input voltage that can block the lower reaches of the dynamic range until it becomes much less than the signal.
A single-sided signal can be applied via a blocking capacitor to either Pin 1 or Pin 8, with the other pin ac-coupled to ground. Under these conditions, the largest input signal that can be handled is 0 dBV (a sine amplitude of 1.4 V) when using a 3 V supply; a 5 dBV input (2.5 V amplitude) can be handled with a 5 V supply. When using a fully balanced drive, this maximum input level is permissible for supply voltages as low as 2.7 V. Above 10 MHz, this is easily achieved using an LC matching network. Such a network, having an inductor at the input, usefully eliminates the input transient noted above.
AD8310 TOP-ENDDETECTORSCOMINHIINLOCPCDCMCOM4kΩ~3kΩ125Ω6kΩ6kΩ2kΩTYP 2.2V FOR3V SUPPLY,3.2V AT 5VSVPOSIE2.4mAQ1Q2 581
Figure 24. Signal Input Interface
Occasionally, it might be desirable to use the dc-coupled potential of the AD8310 in baseband applications. The main challenge here is to present the signal at the elevated common-mode input level, which might require the use of low noise, low offset buffer amplifiers. In some cases, it might be possible to use dual supplies of ±3 V, which allow the input pins to operate at ground potential. The output, which is internally referenced to the COMM pin (now at −3 V), can be positioned back to ground level, with essentially no sensitivity to the particular value of the negative supply.
OFFSET INTERFACE
The input-referred dc offsets in the signal path are nulled via the interface associated with Pin 3, shown in Figure 25. Q1 and Q2 are the first-stage input transistors, having slightly unbalanced load resistors, resulting in a deliberate offset voltage of about 1.5 mV referred to the input pins. Q3 generates a small current to null this error, dependent on the voltage at the OFLT pin. When Q1 and Q2 are perfectly matched, this voltage is about 1.75 V. In practice, it can range from approximately 1 V to 2.5 V for an input-referred offset of ±1.5 mV.
Figure 25. Offset Interface and Offset-Nulling Path
In normal operation using an ac-coupled input signal, the OFLT pin should be left unconnected. The gm cell, which is gated off when the chip is disabled, converts a residual offset (sensed at a point near the end of the cascade of amplifiers) to a current. This is integrated by the on-chip capacitor, CHP, plus any added external capacitance, COFLT, to generate the voltage that is applied back to the input stage in the polarity needed to null the output offset. From a small-signal perspective, this feedback alters the response of the amplifier, which exhibits a zero in its ac transfer function, resulting in a closed-loop, high-pass −3 dB corner at about 2 MHz. An external capacitor lowers the high-pass corner to arbitrarily low frequencies; using 1 μF, the 3 dB corner is at 60 Hz.
OUTPUT INTERFACE
The nine detectors generate differential currents, having an average value that is dependent on the signal input level, plus a fluctuation at twice the input frequency. These are summed at nodes LGP and LGN in Figure 26. Further currents are added at these nodes to position the intercept by slightly raising the output for zero input and to provide temperature compensation.
0.2pF3kΩ VOUT4
Figure 26. Simplified Output Interface
AD8310
Rev. F | Page 13 of 24
For zero-signal conditions, all the detector output currents are equal. For a finite input of either polarity, their difference is converted by the output interface to a single-sided unipolar current, nominally scaled 2 μA/dB (40 μA/decade), at the output pin BFIN. An on-chip resistor of ~3 kΩ, R1, converts this current to a voltage of 6 mV/dB. This is then amplified by a factor of 4 in the output buffer, which can drive a current of up to 25 mA in a grounded load resistor. The overall rise time of the AD8310 is less than 15 ns. There is also a delay time of about 6 ns when the log amp is driven by an RF burst, starting at zero amplitude.
When driving capacitive loads, it is desirable to add a low value of load resistor to speed up the return to the baseline; the buffer is stable for loads of a least 100 pF. The output bandwidth can be lowered by adding a grounded capacitor at BFIN. The time-constant of the resulting single-pole filter is formed with the 3 kΩ internal load resistor (with a tolerance of 20%). Therefore, to set the −3 dB frequency to 20 kHz, use a capacitor of 2.7 nF. Using 2.7 μF, the filter corner is at 20 Hz.
AD8310
Rev. F | Page 14 of 24
USING THE AD8310
The AD8310 has very high gain and bandwidth. Consequently, it is susceptible to all signals that appear at the input terminals within a very broad frequency range. Without the benefit of filtering, these are indistinguishable from the desired signal and have the effect of raising the apparent noise floor (that is, lowering the useful dynamic range). For example, while the signal of interest has an IF of 50 MHz, any of the following can easily be larger than the IF signal at the lower extremities of its dynamic range: a few hundred mV of 60 Hz hum picked up due to poor grounding techniques, spurious coupling from a digital clock source on the same PC board, local radio stations, and so on. Careful shielding and supply decoupling is, therefore, essential. A ground plane should be used to provide a low impedance connection to the common pin COMM, for the decoupling capacitor(s) used at VPOS, and for the output ground.
BASIC CONNECTIONS
Figure 27 shows the connections needed for most applications. A supply voltage between 2.7 V and 5.5 V is applied to VPOS and is decoupled using a 0.01 μF capacitor close to the pin. Optionally, a small series resistor can be placed in the power line to give additional filtering of power-supply noise. The ENBL input, which has a threshold of approximately 1.3 V (see Figure 15), should be tied to VPOS when this feature is not needed. VS(2.7V–5.5V)C20.01μF52.3Ω C10.01μFC40.01μFNCNCINHIENBLBFINVPOSINLOCOMMOFLTVOUTAD83104.7ΩOPTIONALVOUT (RSSI)SIGNALINPUT87651234
Figure 27. Basic Connections
While the AD8310’s input can be driven differentially, the input signal is, in general, single-ended. C1 is tied to ground, and the input signal is coupled in through C2. Capacitor C1 and Capacitor C2 should have the same value to minimize start-up transients when the enable feature is used; otherwise, their values need not be equal.
The 52.3 Ω resistor combines with the 1.1 kΩ input impedance of the AD8310 to yield a simple broadband 50 Ω input match. An input matching network can also be used (see the Input Matching section).
The coupling time constant, 50 × CC/2, forms a high-pass corner with a 3 dB attenuation at fHP = 1/(π × 50 × CC), where C1 = C2 = CC. In high frequency applications, fHP should be as large as possible to minimize the coupling of unwanted low frequency signals. In low frequency applications, a simple RC network forming a low-pass filter should be added at the input for similar reasons. This should generally be placed at the generator side of the coupling capacitors, thereby lowering the required capacitance value for a given high-pass corner frequency.
For applications in which the ground plane might not be an equi-potential (possibly due to noise in the ground plane), the low input of an unbalanced source should generally be ac-coupled through a separate connection of the low associated with the source. Furthermore, it is good practice in such situations to break the ground loop by inserting a small resistance to ground in the low side of the input connector (see Figure 28).
Figure 28. Connections for Isolation of Source Ground from Device Ground
Figure 29 shows the output vs. the input level for sine inputs at 10 MHz, 50 MHz, and 100 MHz. Figure 30 shows the logarith-mic conformance under the same conditions.
Figure 29. Output vs. Input Level at 10 MHz, 50 MHz, and 100 MHz
AD8310
Rev. F | Page 15 of 24
5ERROR (
dB)4–1–2–3–4203110MHz50MHz ±3dB DYNAMIC RANGE±1dB DYNAMIC RANGE
Figure 30. Log Conformance Error vs. Input Level at 10 MHz, 50 MHz, and 100 MHz
TRANSFER FUNCTION IN TERMS OF SLOPE AND INTERCEPT
The transfer function of the AD8310 is characterized in terms of its slope and intercept. The logarithmic slope is defined as the change in the RSSI output voltage for a 1 dB change at the input. For the AD8310, slope is nominally 24 mV/dB. Therefore, a 10 dB change at the input results in a change at the output of approximately 240 mV. The plot of log conformance shows the range over which the device maintains its constant slope. The dynamic range of the log amp is defined as the range over which the slope remains within a certain error band, usually ±1 dB or ±3 dB. In Figure 30, for example, the ±1 dB dynamic range is approximately 95 dB (from +4 dBV to −91 dBV).
The intercept is the point at which the extrapolated linear response would intersect the horizontal axis (see Figure 29). For the AD8310, the intercept is calibrated to be −108 dBV (−95 dBm). Using the slope and intercept, the output voltage can be calculated for any input level within the specified input range using the following equation:
VOUT = VSLOPE × (PIN − PO) (3)
where: VOUT is the demodulated and filtered RSSI output. VSLOPE is the logarithmic slope expressed in V/dB. PIN is the input signal expressed in dB relative to some reference level (either dBm or dBV in this case). PO is the logarithmic intercept expressed in dB relative to the same reference level.
For example, for an input level of −33 dBV (−20 dBm), the output voltage is
VOUT = 0.024 V/dB × (−33 dBV − (−108 dBV)) = 1.8 V (4)
dBV vs. dBm
The most widely used convention in RF systems is to specify power in dBm, decibels above 1 mW in 50 Ω. Specification of the log amp input level in terms of power is strictly a concession to popular convention. As mentioned previously, log amps do not respond to power (power absorbed at the input), but to the input voltage. The use of dBV, defined as decibels with respect to a 1 V rms sine wave, is more precise. However, this is still ambiguous, because waveform is also involved in the response of a log amp, which, for a complex input such as a CDMA signal, does not follow the rms value exactly. Because most users specify RF signals in terms of power (more specifically, in dBm/50 Ω) both dBV and dBm are used to specify the perform-ance of the AD8310, showing equivalent dBm levels for the special case of a 50 Ω environment. Values in dBV are converted to dBm re 50 Ω by adding 13 dB.
Table 4. Correction for Signals with Differing Crest Factors
Signal Type
Correction Factor1 (dB)
Sine wave
0
Square wave or dc
−3.01
Triangular wave
0.9
GSM channel (all time slots on)
0.55
CDMA channel (forward link, nine channels on)
3.55
CDMA channel (reverse link)
0.5
PDC channel (all time slots on)
0.58
1 Add to the measured input level.
INPUT MATCHING
Where higher sensitivity is required, an input matching network is useful. Using a transformer to achieve the impedance trans-formation also eliminates the need for coupling capacitors, lowers the offset voltage generated directly at the input, and balances the drive amplitude to INLO and INHI.
The choice of turns ratio depends somewhat on the frequency. At frequencies below 50 MHz, the reactance of the input capacitance is much higher than the real part of the input impedance. In this frequency range, a turns ratio of about 1:4.8 lowers the input impedance to 50 Ω, while raising the input voltage lowers the effect of the short-circuit noise voltage by the same factor. The intercept is also lowered by the turns ratio; for a 50 Ω match, it is reduced by 20 log10 (4.8) or 13.6 dB. The total noise is reduced by a somewhat smaller factor, because there is a small contribution from the input noise current.
AD8310
Rev. F | Page 16 of 24
NARROW-BAND MATCHING
Transformer coupling is useful in broadband applications. However, a magnetically coupled transformer might not be convenient in some situations. Table 5 lists narrow-band matching values.
Table 5. Narrow-Band Matching Values
fC (MHz)
ZIN (Ω)
C1 (pF)
C2 (pF)
LM (nH)
Voltage Gain (dB)
10
45
160
150
3300
13.3
20
44
82
75
1600
13.4
50
46
30
27
680
13.4
100
50
15
13
270
13.4
150
57
10
8.2
220
13.2
200
57
7.5
6.8
150
12.8
250
50
6.2
5.6
100
12.3
500
54
3.9
3.3
39
10.9
10
103
100
91
5600
10.4
20
102
51
43
2700
10.4
50
99
22
18
1000
10.6
100
98
11
9.1
430
10.5
150
101
7.5
6.2
260
10.3
200
95
5.6
4.7
180
10.3
250
92
4.3
3.9
130
9.9
500
114
2.2
2.0
47
6.8
At high frequencies, it is often preferable to use a narrow-band matching network, as shown in Figure 31. This has several advan-tages. The same voltage gain is achieved, providing increased sensitivity, but a measure of selectivity is also introduced. The component count is low: two capacitors and an inexpensive chip inductor. Additionally, by making these capacitors unequal, the amplitudes at INP and INM can be equalized when driving from a single-sided source; that is, the network also serves as a balun. Figure 32 shows the response for a center frequency of 100 MHz; note the very high attenuation at low frequencies. The high fre-quency attenuation is due to the input capacitance of the log amp. C1 INHIAD8310SIGNALINPUTLM8
Figure 31. Reactive Matching Network
Figure 32. Response of 100 MHz Matching Network
GENERAL MATCHING PROCEDURE
For other center frequencies and source impedances, the following steps can be used to calculate the basic matching parameters.
Step 1: Tune Out CIN
At a center frequency, fC, the shunt impedance of the input capacitance, CIN, can be made to disappear by resonating with a temporary inductor, LIN, whose value is given by
(5)
where CIN = 1.4 pF. For example, at fC = 100 MHz, LIN = 1.8 μH.
Step 2: Calculate CO and LO
Now, having a purely resistive input impedance, calculate the nominal coupling elements, CO and LO, using
(6)
For the AD8310, RIN is 1 kΩ. Therefore, if a match to 50 Ω is needed, at fC = 100 MHz, CO must be 7.12 pF and LO must be 356 nH.
Step 3: Split CO into Two Parts
To provide the desired fully balanced form of the network shown in Figure 31, two capacitors C1 and C2, each of nominally twice CO, can be used. This requires a value of 14.24 pF in this example. Under these conditions, the voltage amplitudes at INHI and INLO are similar. A somewhat better balance in the two drives can be achieved when C1 is made slightly larger than C2, which also allows a wider range of choices in selecting from standard values.
For example, capacitors of C1 = 15 pF and C2 = 13 pF can be used, making CO = 6.96 pF.
AD8310
Rev. F | Page 17 of 24
( )
Step 4: Calculate LM
The matching inductor required to provide both LIN and LO is the parallel combination of these.
(7)
With LIN = 1.8 μH and LO = 356 nH, the value of LM to complete this example of a match of 50 Ω at 100 MHz is 297.2 nH.
The nearest standard value of 270 nH can be used with only a slight loss of matching accuracy. The voltage gain at resonance depends only on the ratio of impedances, as given by
(8)
SLOPE AND INTERCEPT ADJUSTMENTS
Where system (that is, software) calibration is not available, the adjustments shown in Figure 33 can be used, either singly or in combination, to trim the absolute accuracy of the AD8310. The log slope can be raised or lowered by VR1; the values shown provide a calibration range of ±10% (22.6 mV/dB to 27.4 mV/dB), which includes full allowance for the variability in the value of the internal resistances. The adjustment can be made by alternately applying two fixed input levels, provided by an accurate signal generator, spaced over the central portion of the dynamic range, for example, −60 dBV and −20 dBV.
Alternatively, an AM-modulated signal at about the center of the dynamic range can be used. For a modulation depth M, expressed as a fraction, the decibel range between the peaks and troughs over one cycle of the modulation period is given by
(9)
For example, using a generator output of −40 dBm with a 70% modulation depth (M = 0.7), the decibel range is 15 dB, because the signal varies from −47.5 dBm to −32.5 dBm.
The log intercept is adjustable by VR2 over a −3 dB range with the component values shown. VR2 is adjusted while applying an accurately known CW signal, preferably near the lower end of the dynamic range, to minimize the effect of any residual uncertainty in the slope. For example, to position the intercept to −80 dBm, a test level of −65 dBm can be applied, and VR2 can be adjusted to produce a dc output of 15 dB above 0 at 24 mV/dB, which is 360 mV. 52.3 AD8310
Figure 33. Slope and Intercept Adjustments
INCREASING THE SLOPE TO A FIXED VALUE
It is also possible to increase the slope to a new fixed value and, therefore, to increase the change in output for each decibel of input change. A common example of this is the need to map the output swing of the AD8310 into the input range of an analog-to-digital converter (ADC) with a rail-to-rail input swing. Alternatively, a situation might arise when only a part of the total dynamic range is required (for example, just 20 dB) in an application where the nominal input level is more tightly constrained, and a higher sensitivity to a change in this level is required. Of course, the maximum output is limited by either the load resistance and the maximum output current rating of 25 mA or by the supply voltage (see the Specifications section).
The slope can easily be raised by adding a resistor from VOUT to BFIN, as shown in Figure 34. This alters the gain of the output buffer, by means of stable positive feedback, from its normal value of 4 to an effective value that can be as high as 16, corresponding to a slope of 100 mV/dB. INHI 8765
Figure 34. Raising the Slope to 100 mV/dB
The resistor, RSLOPE, is set according to the equation SlopeRSLOPEmV/dB241− =
(10)
AD8310
Rev. F | Page 18 of 24
OUTPUT FILTERING
LOWERING THE HIGH-PASS CORNER FREQUENCY OF THE OFFSET COMPENSATION LOOP
For applications in which maximum video bandwidth and, consequently, fast rise time are desired, it is essential that the BFIN pin be left unconnected and free of any stray capacitance.
In normal operation using an ac-coupled input signal, the OFLT pin should be left unconnected. Input-referred dc offsets of about 1.5 mV in the signal path are nulled via an internal offset control loop. This loop has a high-pass −3 dB corner at about 2 MHz. In low frequency ac-coupled applications, it is necessary to lower this corner frequency to prevent input signals from being misinterpreted as offsets. An external capacitor on OFLT lowers the high-pass corner to arbitrarily low frequencies (Figure 36). For example, by using a 1 μF capacitor, the 3 dB corner is reduced to 60 Hz.
The nominal output video bandwidth of 25 MHz can be reduced by connecting a ground-referenced capacitor (CFILT) to the BFIN pin, as shown in Figure 35. This is generally done to reduce out-put ripple (at twice the input frequency for a symmetric input waveform such as sinusoidal signals). +42μA/dB3kΩVOUTBFIN AD8310
Figure 35. Lowering the Postdemodulation Video Bandwidth
CFILT is selected using the following equation:
Figure 36. Lowering the High-Pass Corner Frequency of the Offset Control Loop
(11)
The corner frequency is set by the following equation:
The video bandwidth should typically be set at a frequency equal to about one-tenth the minimum input frequency. This ensures that the output ripple of the demodulated log output, which is at twice the input frequency, is well filtered.
In many log amp applications, it might be necessary to lower the corner frequency of the postdemodulation filtering to achieve low output ripple while maintaining a rapid response time to changes in signal level. An example of a 4-pole active filter is shown in the AD8307 data sheet.
(12)
where COFLT is the capacitor connected to OFLT.
AD8310
Rev. F | Page 19 of 24
APPLICATIONS INFORMATION
The AD8310 is highly versatile and easy to use. It needs only a few external components, most of which can be immediately accommodated using the simple connections shown in the Using the AD8310 section.
A few examples of more specialized applications are provided in the following sections. See the AD8307 data sheet for more applications (note the slightly different pin configuration).
CABLE-DRIVING
For a supply voltage of 3 V or greater, the AD8310 can drive a grounded 100 Ω load to 2.5 V. If reverse-termination is required when driving a 50 Ω cable, it should be included in series with the output, as shown in Figure 37. The slope at the load is then 12 mV/dB. In some cases, it might be permissible to operate the cable without a termination at the far end, in which case the slope is not lowered. Where a further increase in slope is desirable, the scheme shown in Figure 34 can be used.
AD8310VOUT50Ω50Ω
Figure 37. Output Response of Cable-Driver Application
DC-COUPLED INPUT
It might occasionally be necessary to provide response to dc inputs. Because the AD8310 is internally dc-coupled, there is no reason why this cannot be done. However, its differential inputs must be positioned at least 2 V above the COM potential for proper biasing of the first stage. Usually, the source is a single-sided ground-referenced signal, so level-shifting and a single-ended-to-differential conversion must be provided to correctly drive the AD8310’s inputs.
Figure 38 shows how a level-shift to midsupply (2.5 V in this example) and a single-ended-to-differential conversion can be accomplished using the AD8138 differential amplifier. The four 499 Ω resistors set up a gain of unity. An output common-mode (or bias) voltage of 2.5 is achieved by applying 2.5 V from a supply-referenced resistive divider to the VOCM pin of the AD8138. The differential outputs of the AD8138 directly drive the 1.1 kΩ input impedance of the AD8310.
Figure 38. DC-Coupled Log Amp
In this application the offset voltage of the AD8138 must be trimmed. The internal offset compensation circuitry of the AD8310 is disabled by applying a nominal voltage of ~1.9 V to the OFLT pin, so the trim on the AD8138 is effectively trimming the offsets of both devices. The trim is done by grounding the circuit’s input and slightly varying the gain resistors on the inverting input of the AD8138 (a 50 Ω potentiometer is used in this example) until the voltage on the AD8310’s output reaches a minimum.
After trimming, the lower end of the dynamic range is limited by the broadband noise at the output of the AD8138, which is approximately 425 μV p-p. A differential low-pass filter can be added between the AD8138 and the AD8310 when the very fast pulse response of the circuit is not required.
Figure 39. Transfer Function of DC-Coupled Log Amp Application
AD8310
Rev. F | Page 20 of 24
EVALUATION BOARD
An evaluation board is available that has been carefully laid out and tested to demonstrate the specified high speed performance of the AD8310. Figure 40 shows the schematic of the evaluation board, which follows the basic connections schematic shown in Figure 27.
Connectors INHI, INLO, and VOUT are of the SMA type. Supply and ground are connected to the TP1 and TP2 vector pins. The layout and silkscreen for the component side of the board are shown in Figure 41 and Figure 42. Switches and component settings for different setups are described in Table 6. For ordering information, see the Ordering Guide. C20.01μFINHIENBLBFINVPOSINLOCOMMOFLTVOUTAD831012348765C40.01μFC10.01μFR352.3ΩSW1ABR40ΩR1INHIINLOTP2C7OPENW1W2R60Ω VOUTC5OPENC3OPENR50ΩTP1VPOSR2
Figure 40. Evaluation Board Schematic
Figure 41. Layout of the Component Side of the Evaluation Board
01084-042
Figure 42. Component Side Silkscreen of the Evaluation Board
AD8310
Rev. F | Page 21 of 24 Table 6. Evaluation Board Setup Options
Component Function Default Condition
TP1, TP2 Supply and Ground Vector Pins. Not applicable SW1 Device Enable. When in Position A, the ENBL pin is connected to +VS, and the AD8310 is in normal
operating mode. When in Position B, the ENBL pin is connected to ground, putting the device into
sleep mode.
SW1 = A
R1/R4 SMA Connector Grounds. Connects common of INHI and INLO SMA connectors to ground. They can be used to isolate the generator ground from the evaluation board ground. See Figure 28. R1 = R4 = 0 Ω
C1, C2, R3 Input Interface. R3 (52.3 Ω) combines with the AD8310’s 1 kΩ input impedance to give an overall
broadband input impedance of 50 Ω. C1, C2, and the AD8310’s input impedance combine to set a
high-pass input corner of 32 kHz. Alternatively, R3, C1, and C2 can be replaced by an inductor and
matching capacitors to form an input matching network. See the Input Matching section for details.
R3 = 52.3 Ω,
C1 = C2 = 0.01 μF
C3 RSSI (Video) Bandwidth Adjust. The addition of C3 (farads) lowers the RSSI bandwidth of the
AD8310’s output according to the following equation:
CFILT = 1/(2π × 3 kΩ Video Bandwidth) − 2.1 pF
C3 = open
C4, C5, R5 Supply Decoupling. The normal supply decoupling of 0.01 μF (C4) can be augmented by a larger
capacitor in C5. An inductor or small resistor can be placed in R5 for additional decoupling.
C4 = 0.01 μF,
C5 = open, R5 = 0 Ω
R6 Output Source Impedance. In cable-driving applications, a resistor (typically 50 Ω or 75 Ω) can be placed in R6 to give the circuit a back-terminated output impedance.
R6 = 0 Ω
W1, W2, C6, R7 Output Loading. Resistors and capacitors can be placed in C6 and R7 to load-test VOUT. Jumper W1
and Jumper W2 are used to connect or disconnect the loads. C6 = R7 = open,
W1 = W2 = installed
C7 Offset Compensation Loop. A capacitor in C7 reduces the corner frequency of the offset control
loop in low frequency applications. C7 = open
AD8310
DIE INFORMATION
Figure 43. Die Outline Dimensions
Table 7. Die Pad Function Descriptions
Pin No.
Mnemonic
Description
1
INLO
One of Two Balanced Inputs. Biased roughly to VPOS/2.
2
COMM
Common Pin. Usually grounded.
3
OFLT
Offset Filter Access. Nominally at about 1.75 V.
4
VOUT
Low Impedance Output Voltage. Carries a 25 mA maximum load.
5A, 5B
VPOS
Positive Supply. 2.7 V to 5.5 V at 8 mA quiescent current.
6
BFIN
Buffer Input. Used to lower postdetection bandwidth.
7
ENBL
CMOS Compatible Chip Enable. Active when high.
8
INHI
Second of Two Balanced Inputs. Biased roughly to VPOS/2.
AD8310
OUTLINE DIMENSIONS
Figure 44. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
Branding
AD8310ARM
−40°C to +85°C
8-Lead MSOP, Tube
RM-8
J6A
AD8310ARM-REEL7
−40°C to +85°C
8-Lead MSOP, 7” Tape and Reel
RM-8
J6A
AD8310ARMZ
−40°C to +85°C
8-Lead MSOP, Tube
RM-8
J6A
AD8310ARMZ-REEL7
−40°C to +85°C
8-Lead MSOP, 7” Tape and Reel
RM-8
J6A
AD8310ACHIPS
−40°C to +85°C
Die
AD8310-EVAL
Evaluation Board
1 Z = RoHS Compliant Part.
AD8310
Rev. F | Page 24 of 24
NOTES
© 2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01084–0–6/10(F)
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
Q
NC
G
Q
NC
F
Q
Q
NC
E
A
Q
NC
B
QC
B
A
NC
CLK
CLR
V
Q
D
GND
NC
CC
H
Q
NC − No internal connection
1
2
3
4
5
6
7
14
13
12
11
10
9
8
A
B
Q
Q
Q
Q
GND
A
B
C
D
VCC
Q
Q
Q
Q
CLR
H
G
F
E
CLK
SN54HC164, SN74HC164
www.ti.com SCLS115F –DECEMBER 1982–REVISED OCTOBER 2013
8-Bit Parallel-Out Serial Shift Registers
Check for Samples: SN54HC164, SN74HC164
1FEATURES DESCRIPTION
• Wide Operating Voltage Range of 2 V to 6 V These 8-bit shift registers feature AND-gated serial
• Outputs Can Drive Up To 10 LSTTL Loads inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control
• Low Power Consumption, 80-μA Max ICC over incoming data; a low at either input inhibits entry
• Typical tpd= 20 ns of the new data and resets the first flip-flop to the low
• ±4-mA Output Drive at 5 V level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the
• Low Input Current of 1-μA Max state of the first flip-flop. Data at the serial inputs can
• AND-Gated (Enable/Disable) Serial Inputs be changed while CLK is high or low, provided the
• Fully Buffered Clock and Serial Inputs minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.
• Direct Clear
SN54HC164...J OR W PACKAGE
SN74HC164...D, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54HC164...FK PACKAGE
(TOP VIEW)
FUNCTION TABLE(1)(2)
INPUTS OUTPUTS
CLR CLK A B QA QB . . . QH
L X X X L L L
H L X X QA0 QB0 QH0
H ↑ H H H QAn QGn
H ↑ L X L QAn QGn
H ↑ X L L QAn QGn
(1) QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before the
indicated steady-state input conditions were established.
(2) QAn, QGn = the level of QA or QG before the most recent ↑ transition
of CLK: indicates a 1-bit shift.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 1982–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CLK
A
B
CLR
QA
QB
QC
QD
QE
QF
QG
QH
Clear Clear
Serial Inputs Outputs
9
A
B
CLR
CLK
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
C1
1D
R
3
QA
C1
1D
R
4
QB
C1
1D
R
5
QC
C1
1D
R
6
QD
C1
1D
R
10
QE
C1
1D
R
11
QF
C1
1D
R
12
QG
C1
1D
R
13
QH
2
1
8
SN54HC164, SN74HC164
SCLS115F –DECEMBER 1982–REVISED OCTOBER 2013 www.ti.com
LOGIC DIAGRAM (POSITIVE LOGIC)
TYPICAL CLEAR, SHIFT, AND CLEAR SEQUENCE
2 Submit Documentation Feedback Copyright © 1982–2013, Texas Instruments Incorporated
Product Folder Links: SN54HC164 SN74HC164
SN54HC164, SN74HC164
www.ti.com SCLS115F –DECEMBER 1982–REVISED OCTOBER 2013
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNITS
VCC Supply voltage range −0.5 7 V
IIK Input clamp current VI < 0 or VI > VCC
(2) ±20 mA
IOK Output clamp current VO < 0 or VO > VCC
(2) ±20 mA
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
D package 86
N package 80
θJA
(3) Package thermal impedance °C/W
NS package 76
PW package 113
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS(1)
SN54HC164 SN74HC164
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VCC = 6 V 1.8 1.8
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
Δt/Δv(2) Input transition rise/fall time VCC = 4.5 V 500 500 ns
VCC = 6 V 400 400
TA Operating free-air temperature −55 125 −40 125 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) If this device is used in the threshold region (from VIL max = 0.5 V to VIH min = 1.5 V), there is a potential to go into the wrong state from
induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device;
however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
Copyright © 1982–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: SN54HC164 SN74HC164
SN54HC164, SN74HC164
SCLS115F –DECEMBER 1982–REVISED OCTOBER 2013 www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
SN54HC164 SN74HC164 Recommended TA = 25°C –55°C to 125°C –55°C to 85°C SN74HC164 PARAMETER TEST CONDITIONS VCC –55°C to 125°C UNIT
MIN TYP MAX MIN MAX MIN MAX MIN MAX
2 V 1.9 1.998 1.9 1.9 1.9
IOH = −20 μA 4.5 V 4.4 4.499 4.4 4.4 4.4
VOH VI = VIH or VIL 6 V 5.9 5.999 5.9 5.9 5.9 V
IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84 3.7
IOH = −5.2 mA 6 V 5.48 5.8 5.2 5.34 5.2
2 V 0.002 0.1 0.1 0.1 0.1
IOL = 20 μA 4.5 V 0.001 0.1 0.1 0.1 0.1
VOL VI = VIH or VIL 6 V 0.001 0.1 0.1 0.1 0.1 V
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 0.4
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33 0.4
II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 ±1000 nA
ICC VI = VCC or 0 IO = 0 6 V 8 160 80 160 μA
Ci 2 V to 6 V 3 10 10 10 10 pF
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted)
SN54HC164 SN74HC164 Recommended TA = 25°C –55°C to 125°C –55°C to 85°C SN74HC164 PARAMETER VCC –55°C to 125°C UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
2 V 6 4.2 5 4.2
fclock Clock frequency 4.5 V 31 21 25 21 MHz
6 V 36 25 28 25
2 V 100 150 125 125
CLR low 4.5 V 20 30 25 25
Pulse 6 V 17 25 21 21 tw duration ns 2 V 80 120 100 120
CLK high or low 4.5 V 16 24 20 24
6 V 14 20 18 20
2 V 100 150 125 125
Data 4.5 V 20 30 25 25
Setup time 6 V 17 25 21 25 tsu before CLK↑ ns 2 V 100 150 125 125
CLR inactive 4.5 V 20 30 25 25
6 V 17 25 21 25
2 V 5 5 5 5
th Hold time, data after CLK↑ 4.5 V 5 5 5 5 ns
6 V 5 5 5 5
4 Submit Documentation Feedback Copyright © 1982–2013, Texas Instruments Incorporated
Product Folder Links: SN54HC164 SN74HC164
SN54HC164, SN74HC164
www.ti.com SCLS115F –DECEMBER 1982–REVISED OCTOBER 2013
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54HC164 SN74HC164 Recommended PARAMETE FROM TO TA = 25°C SN74HC164 (OUTPUT VCC –55°C to 125°C –55°C to 85°C –55°C to 125°C UNIT R (INPUT) )
MIN TYP MAX MIN MAX MIN MAX MIN MAX
2 V 6 10 4.2 5 4..2
fmax 4.5 V 31 54 21 25 21 MHz
6 V 36 62 25 28 25
2 V 140 205 295 255 255
tPHL CLR Any Q 4.5 V 28 41 59 51 51
6 V 24 35 51 46 46
ns
2 V 115 175 265 220 220
tpd CLK Any Q 4.5 V 23 35 53 44 44
6 V 20 30 45 38 38
2 V 38 75 110 95 110
tt 4.5 V 8 15 22 19 22 ns
6 V 6 13 19 16 19
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 135 pF
Copyright © 1982–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: SN54HC164 SN74HC164
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
tsu th
50%
50% 50%
10% 10%
90% 90%
VCC
VCC
0 V
0 V
tr t
Reference
f
Input
Data
Input
50%
High-Level
Pulse
50%
VCC
0 V
50% 50%
VCC
0 V
t
Low-Level
w
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50% 50%
10% 10%
90% 90%
VCC
VOH
VOL
0 V
tr t
Input
f
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10%
90% 90%
VOH
VOL
tf tr
tPHL tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ! 1 MHz, ZO = 50 !, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
SN54HC164, SN74HC164
SCLS115F –DECEMBER 1982–REVISED OCTOBER 2013 www.ti.com
PARAMETER MEASUREMENT INFORMATION
Figure 1. Load Circuit and Voltage Waveforms
6 Submit Documentation Feedback Copyright © 1982–2013, Texas Instruments Incorporated
Product Folder Links: SN54HC164 SN74HC164
SN54HC164, SN74HC164
www.ti.com SCLS115F –DECEMBER 1982–REVISED OCTOBER 2013
REVISION HISTORY
Changes from Revision E (November 2010) to Revision F Page
• Updated document to new TI data sheet format - no specification changes. ...................................................................... 1
• Removed ordering information. ............................................................................................................................................ 1
• Updated operating temperature range. ................................................................................................................................. 3
Copyright © 1982–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: SN54HC164 SN74HC164
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8416201VCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8416201VC
A
SNV54HC164J
5962-8416201VDA ACTIVE CFP W 14 25 TBD A42 N / A for Pkg Type -55 to 125 5962-8416201VD
A
SNV54HC164W
84162012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84162012A
SNJ54HC
164FK
8416201CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8416201CA
SNJ54HC164J
SN54HC164J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC164J
SN74HC164D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164
SN74HC164DE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164
SN74HC164DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164
SN74HC164DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 HC164
SN74HC164DRG3 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU SN Level-1-260C-UNLIM -40 to 125 HC164
SN74HC164DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164
SN74HC164DT ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164
SN74HC164N ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU | CU SN N / A for Pkg Type -40 to 125 SN74HC164N
SN74HC164N3 OBSOLETE PDIP N 14 TBD Call TI Call TI -40 to 125
SN74HC164NE3 PREVIEW PDIP N 14 25 Green (RoHS
& no Sb/Br)
CU SN Level-1-260C-UNLIM -40 to 125 SN74HC164N
SN74HC164NE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -40 to 125 SN74HC164N
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74HC164NSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164
SN74HC164PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164
SN74HC164PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164
SN74HC164PWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164
SN74HC164PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164
SN74HC164PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164
SN74HC164PWT ACTIVE TSSOP PW 14 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164
SN74HC164PWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 HC164
SNJ54HC164FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84162012A
SNJ54HC
164FK
SNJ54HC164J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8416201CA
SNJ54HC164J
SNJ54HC164W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 8416201DA
SNJ54HC164W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
Addendum-Page 3
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC164, SN54HC164-SP, SN74HC164 :
• Catalog: SN74HC164, SN54HC164
• Military: SN54HC164
• Space: SN54HC164-SP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
SN74HC164DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC164DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC164DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
SN74HC164DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
SN74HC164DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC164DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC164DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC164NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74HC164PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC164PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Apr-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC164DR SOIC D 14 2500 367.0 367.0 38.0
SN74HC164DR SOIC D 14 2500 333.2 345.9 28.6
SN74HC164DR SOIC D 14 2500 364.0 364.0 27.0
SN74HC164DRG3 SOIC D 14 2500 364.0 364.0 27.0
SN74HC164DRG4 SOIC D 14 2500 333.2 345.9 28.6
SN74HC164DRG4 SOIC D 14 2500 367.0 367.0 38.0
SN74HC164DT SOIC D 14 250 367.0 367.0 38.0
SN74HC164NSR SO NS 14 2000 367.0 367.0 38.0
SN74HC164PWR TSSOP PW 14 2000 367.0 367.0 35.0
SN74HC164PWT TSSOP PW 14 250 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Apr-2014
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
0.1 GHz to 2.5 GHz 70 dB
Logarithmic Detector/Controller
AD8313
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
Wide bandwidth: 0.1 GHz to 2.5 GHz min
High dynamic range: 70 dB to ±3.0 dB
High accuracy: ±1.0 dB over 65 dB range (@ 1.9 GHz)
Fast response: 40 ns full-scale typical
Controller mode with error output
Scaling stable over supply and temperature
Wide supply range: 2.7 V to 5.5 V
Low power: 40 mW at 3 V
Power-down feature: 60 mW at 3 V
Complete and easy to use
APPLICATIONS
RF transmitter power amplifier setpoint control and
level monitoring
Logarithmic amplifier for RSSI measurement cellular
base stations, radio link, radar
FUNCTIONAL BLOCK DIAGRAM +++++AD8313VOUTVSETCOMMPWDNGAINBIASBAND GAPREFERENCESLOPECONTROLINTERCEPTCONTROLEIGHT 8dB 3.5GHz AMPLIFIER STAGES8dB8dBVPOSINHIINLOVPOS8dB8dBNINE DETECTOR CELLSCINTLPI→VV→I1876523401085-C-001
Figure 1.
GENERAL DESCRIPTION
The AD8313 is a complete multistage demodulating logarithmic amplifier that can accurately convert an RF signal at its differ-ential input to an equivalent decibel-scaled value at its dc output. The AD8313 maintains a high degree of log conformance for signal frequencies from 0.1 GHz to 2.5 GHz and is useful over the range of 10 MHz to 3.5 GHz. The nominal input dynamic range is –65 dBm to 0 dBm (re: 50 Ω), and the sensitivity can be increased by 6 dB or more with a narrow-band input impedance matching network or a balun. Application is straightforward, requiring only a single supply of 2.7 V to 5.5 V and the addition of a suitable input and supply decoupling. Operating on a 3 V supply, its 13.7 mA consumption (for TA = 25°C) is only 41 mW. A power-down feature is provided; the input is taken high to initiate a low current (20 μA) sleep mode, with a threshold at half the supply voltage.
The AD8313 uses a cascade of eight amplifier/limiter cells, each having a nominal gain of 8 dB and a −3 dB bandwidth of 3.5 GHz. This produces a total midband gain of 64 dB. At each amplifier output, a detector (rectifier) cell is used to convert the RF signal to baseband form; a ninth detector cell is placed directly at the input of the AD8313. The current-mode outputs of these cells are summed to generate a piecewise linear approxi-mation to the logarithmic function. They are converted to a low impedance voltage-mode output by a transresistance stage, which also acts as a low-pass filter.
When used as a log amplifier, scaling is determined by a separate feedback interface (a transconductance stage) that sets the slope to approximately 18 mV/dB; used as a controller, this stage accepts the setpoint input. The logarithmic intercept is positioned to nearly −100 dBm, and the output runs from about 0.45 V dc at −73 dBm input to 1.75 V dc at 0 dBm input. The scale and intercept are supply- and temperature-stable.
The AD8313 is fabricated on Analog Devices’ advanced 25 GHz silicon bipolar IC process and is available in an 8-lead MSOP package. The operating temperature range is −40°C to +85°C. An evaluation board is available. INPUT AMPLITUDE (dBm)2.0–80OUTPUT VOLTAGE (
V
DC)1.81.61.41.21.00.80.60.40.20–70–60–50–40–30–20–100FREQUENCY = 1.9GHz543210–1–2–3–4–5OUTPUT ERROR (
dB)01085-C-002
Figure 2. Typical Logarithmic Response and Error vs. Input Amplitude
AD8313
Rev. D | Page 2 of 24
TABLE OF CONTENTS
Specifications.....................................................................................3
Absolute Maximum Ratings............................................................6
ESD Caution..................................................................................6
Pin Configurations and Function Description.............................7
Typical Performance Characteristics.............................................8
Circuit Description.........................................................................11
Interfaces..........................................................................................13
Power-Down Interface, PWDN................................................13
Signal Inputs, INHI, INLO........................................................13
Logarithmic/Error Output, VOUT..........................................13
Setpoint Interface, VSET............................................................14
Applications.....................................................................................15
Basic Connections for Log (RSSI) Mode.................................15
Operating in Controller Mode.................................................15
Input Coupling...........................................................................16
Narrow-Band LC Matching Example at 100 MHz................16
Adjusting the Log Slope.............................................................18
Increasing Output Current........................................................19
Effect of Waveform Type on Intercept.....................................19
Evaluation Board............................................................................20
Schematic and Layout................................................................20
General Operation.....................................................................20
Using the AD8009 Operational Amplifier..............................20
Varying the Logarithmic Slope.................................................20
Operating in Controller Mode.................................................20
RF Burst Response.....................................................................20
Outline Dimensions.......................................................................24
Ordering Guide..........................................................................24
REVISION HISTORY
6/04—Data Sheet Changed from Rev. C to Rev. D Updated Evaluation Board Section..............................................21
2/03—Data Sheet changed from Rev. B to Rev. C TPCs and Figures Renumbered........................................Universal Edits to SPECIFICATIONS.............................................................2 Updated ESD CAUTION................................................................4 Updated OUTLINE DIMENSIONS..............................................7
8/99—Data Sheet changed from Rev. A to Rev. B
5/99—Data Sheet changed from Rev. 0 to Rev. A
8/98—Revision 0: Initial Version
AD8313
Rev. D | Page 3 of 24
SPECIFICATIONS
TA = 25°C, VS = 5 V1, RL 10 kΩ, unless otherwise noted.
Table 1.
Parameter
Conditions
Min2
Typ
Max2
Unit
SIGNAL INPUT INTERFACE
Specified Frequency Range
0.1
2.5
GHz
DC Common-Mode Voltage
VPOS – 0.75
V
Input Bias Currents
10
μA
Input Impedance
fRF < 100 MHz3
900||1.1
Ω||pF4
LOG (RSSI) MODE
Sinusoidal, input termination configuration shown in Figure 29
100 MHz5
Nominal conditions
±3 dB Dynamic Range6
53.5
65
dB
Range Center
−31.5
dBm
±1 dB Dynamic Range
56
dB
Slope
17
19
21
mV/dB
Intercept
−96
−88
−80
dBm
2.7 V ≤ VS ≤ 5.5 V, −40°C ≤ T ≤ +85°C
±3 dB Dynamic Range
51
64
dB
Range Center
−31
dBm
±1 dB Dynamic Range
55
dB
Slope
16
19
22
mV/dB
Intercept
−99
−89
−75
dBm
Temperature Sensitivity
PIN = −10 dBm
−0.022
dB/°C
900 MHz5
Nominal conditions
±3 dB Dynamic Range
60
69
dB
Range Center
−32.5
dBm
±1 dB Dynamic Range
62
dB
Slope
15.5
18
20.5
mV/dB
Intercept
−105
−93
−81
dBm
2.7 V ≤ VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C
±3 dB Dynamic Range
55.5
68.5
dB
Range Center
–32.75
dBm
±1 dB Dynamic Range
61
dB
Slope
15
18
21
mV/dB
Intercept
–110
–95
–80
dBm
Temperature Sensitivity
PIN = –10 dBm
–0.019
dB/°C
1.9 GHz7
Nominal conditions
±3 dB Dynamic Range
52
73
dB
Range Center
–36.5
dBm
±1 dB Dynamic Range
62
dB
Slope
15
17.5
20.5
mV/dB
Intercept
–115
–100
–85
dBm
2.7 V ≤ VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C
±3 dB Dynamic Range
50
73
dB
Range Center
–36.5
dBm
±1 dB Dynamic Range
60
dB
Slope
14
17.5
21.5
mV/dB
Intercept
–125
–101
–78
dBm
Temperature Sensitivity
PIN = –10 dBm
–0.019
dB/°C
AD8313
Rev. D | Page 4 of 24
Parameter Conditions Min2 Typ Max2 Unit
2.5 GHz7
Nominal conditions
±3 dB Dynamic Range
48
66
dB
Range Center
–34
dBm
±1 dB Dynamic Range
46
dB
Slope
16
20
25
mV/dB
Intercept
–111
–92
–72
dBm
2.7 V ≤ VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C
±3 dB Dynamic Range
47
68
dB
Range Center
–34.5
dBm
±1 dB Dynamic Range
46
dB
Slope
14.5
20
25
mV/dB
Intercept
–128
–92
–56
dBm
Temperature Sensitivity
PIN =–10 dBm
–0.040
dB/°C
3.5 GHz5
Nominal conditions
±3 dB Dynamic Range
43
dB
±1 dB Dynamic Range
35
dB
Slope
24
mV/dB
Intercept
–65
dBm
CONTROL MODE
Controller Sensitivity
f = 900 MHz
23
V/dB
Low Frequency Gain
VSET to VOUT8
84
dB
Open-Loop Corner Frequency
VSET to VOUT8
700
Hz
Open-Loop Slew Rate
f = 900 MHz
2.5
V/μs
VSET Delay Time
150
ns
VOUT INTERFACE
Current Drive Capability
Source Current
400
μA
Sink Current
10
mA
Minimum Output Voltage
Open-loop
50
mV
Maximum Output Voltage
Open-loop
VPOS – 0.1
V
Output Noise Spectral Density
PIN = –60 dBm, fSPOT = 100 Hz
2.0
μV/√Hz
PIN = –60 dBm, fSPOT = 10 MHz
1.3
μV/√Hz
Small Signal Response Time
PIN = –60 dBm to –57 dBm, 10% to 90%
40
60
ns
Large Signal Response Time
PIN = No signal to 0 dBm; settled to 0.5 dB
110
160
ns
VSET INTERFACE
Input Voltage Range
0
VPOS
V
Input Impedance
18||1
kΩ||pF4
POWER-DOWN INTERFACE
PWDN Threshold
VPOS/2
V
Power-Up Response Time
Time delay following high to low transition until device meets full specifications.
1.8
μs
PWDN Input Bias Current
PWDN = 0 V
5
μA
PWDN = VS
<1
μA
POWER SUPPLY
Operating Range
2.7
5.5
V
Powered-Up Current
13.7
15.5
mA
4.5 V ≤VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C
18.5
mA
2.7 V ≤VS ≤ 3.3 V, –40°C ≤ T ≤ +85°C
18.5
mA
Powered-Down Current
4.5 V ≤VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C
50
150
μA
2.7 V ≤VS ≤ 3.3 V, –40°C ≤ T ≤ +85°C
20
50
μA
AD8313
Rev. D | Page 5 of 24
1 Except where otherwise noted; performance at VS = 3 V is equivalent to 5 V operation.
2 Minimum and maximum specified limits on parameters that are guaranteed but not tested are 6 sigma values.
3 Input impedance shown over frequency range in Figure 26.
4 Double vertical bars (||) denote “in parallel with.”
5 Linear regression calculation for error curve taken from –40 dBm to –10 dBm for all parameters.
6 Dynamic range refers to range over which the linearity error remains within the stated bound.
7 Linear regression calculation for error curve taken from –60 dBm to –5 dBm for 3 dB dynamic range. All other regressions taken from –40 dBm to –10 dBm.
8 AC response shown in Figure 12.
AD8313
Rev. D | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
Table 2.
Supply Voltage VS
5.5 V
VOUT, VSET, PWDN
0 V, VPOS
Input Power Differential (re: 50 Ω, 5.5 V)
25 dBm
Input Power Single-Ended (re: 50 Ω, 5.5 V)
19 dBm
Internal Power Dissipation
200 mW
θJA
200°C/W
Maximum Junction Temperature
125°C
Operating Temperature Range
–40°C to +85°C
Storage Temperature Range
–65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
AD8313
Rev. D | Page 7 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTION
VPOS1INHI2INLO3VPOS4VOUT8VSET7COMM6PWDN5AD8313TOP VIEW(Not to Scale)01085-C-003
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 4
VPOS
Positive Supply Voltage (VPOS), 2.7 V to 5.5 V.
2
INHI
Noninverting Input. This input should be ac-coupled.
3
INLO
Inverting Input. This input should be ac-coupled.
5
PWDN
Connect Pin to Ground for Normal Operating Mode. Connect this pin to the supply for power-down mode.
6
COMM
Device Common.
7
VSET
Setpoint Input for Operation in Controller Mode. To operate in RSSI mode, short VSET and VOUT.
8
VOUT
Logarithmic/Error Output.
AD8313
Rev. D | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 5 V, RL input match shown in Figure 29, unless otherwise noted. INPUT AMPLITUDE (dBm)2.0–70VOUT (
V)1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–100101.9GHz2.5GHz900MHz100MHz01085-C-004
Figure 4. VOUT vs. Input Amplitude INPUT AMPLITUDE (dBm)6–6–7010–60ERROR (
dB)–50–40–30–20–100420–2–4900MHz100MHz100MHz900MHz1.9GHz2.5GHz2.5GHz1.9GHz01085-C-005
Figure 5. Log Conformance vs. Input Amplitude
INPUT AMPLITUDE (dBm)2.0–70VOUT (
V)1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–10010543210–1–2–3–4–5ERROR (
dB)–40°C+25°C+85°CSLOPE AND INTERCEPT NORMALIZED AT +25°CAND APPLIED TO–40°C AND +85°C01085-C-006
Figure 6. VOUT and Log Conformance vs. Input Amplitude at 100 MHz for Multiple Temperatures INPUT AMPLITUDE (dBm)2.0–70VOUT (
V)1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–10010543210–1–2–3–4–5ERROR (
dB)+25°C+85°C–40°CSLOPE AND INTERCEPT NORMALIZED AT +25°CAND APPLIED TO–40°C AND +85°C01-85-C-007
Figure 7. VOUT and Log Conformance vs. Input Amplitude at 900 MHz for Multiple Temperatures INPUT AMPLITUDE (dBm)2.0–70VOUT (
V)1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–10010543210–1–2–3–4–5ERROR (
dB)–40°C+25°C+85°CSLOPE AND INTERCEPT NORMALIZED AT +25°CAND APPLIED TO–40°C AND +85°C01085-C-008
Figure 8. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz for Multiple Temperatures INPUT AMPLITUDE (dBm)2.0–70VOUT (
V)1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–10010543210–1–2–3–4–5ERROR (
dB)–40°C+25°C+85°CSLOPE AND INTERCEPTNORMALIZED AT +25°C ANDAPPLIED TO–40°C AND +85°C01085-C-009
Figure 9. VOUT and Log Conformance vs. Input Amplitude at 2.5 GHz for Multiple Temperatures
AD8313
Rev. D | Page 9 of 24
FREQUENCY (MHz)22211602500500SLOPE (
mV/dB)10001500200020191817–40°C+25°C+85°C01085-C-010
Figure 10. VOUT Slope vs. Frequency for Multiple Temperatures
SUPPLY VOLTAGE (V)242.5SLOPE (
mV/dB)232221201918171615143.03.54.04.55.05.56.01.9GHz2.5GHz900MHz100MHzSPECIFIED OPERATING RANGE01085-C-011
Figure 11. VOUT Slope vs. Supply Voltage
FREQUENCY (Hz)VSET TO VOUT GAIN (dB)1001k10k100k1M REF LEVEL = 92dBSCALE: 10dB/DIV01085-C-012
Figure 12. AC Response from VSET to VOUTFREQUENCY (MHz)–11002500500INTERCEPT (
dBm)100015002000–70–80–90–100+85°C–40°C+25°C01085-C-013
Figure 13. VOUT Intercept vs. Frequency for Multiple Temperatures
SUPPLY VOLTAGE (V)–702.5INTERCEPT (
dBm)–75–80–85–90–95–100–105–1103.03.54.04.55.05.56.01.9GHz2.5GHz900MHz100MHzSPECIFIED OPERATING RANGE01085-C-014
Figure 14. VOUT Intercept vs. Supply Voltage
FREQUENCY (Hz)100100.1μV/ Hz11k10k100k1M10M2GHz RF INPUTRF INPUT–70dBm–60dBm–55dBm–50dBm–45dBm–40dBm–35dBm–30dBm01085-C-015
Figure 15. VOUT Noise Spectral Density
AD8313
Rev. D | Page 10 of 24
PWDN VOLTAGE (V)0100.00SUPPLY CURRENT (
mA)10.001.000.100.012134 5
40μAVPOS = +3VVPOS = +5V20μA13.7mA01085-C-016
Figure 16. Typical Supply Current vs. PWDN Voltage CH. 1 AND CH. 2: 1V/DIVCH. 3: 5V/DIVHORIZONTAL: 1μs/DIVVOUT @VS = +5.5VPWDNCH. 1 GNDCH. 2 GNDCH. 3 GNDVOUT @VS = +2.7V01085-C-017
Figure 17. PWDN Response Time CH. 1CH. 1 GNDCH. 2 GNDCH. 2CH. 1 AND CH. 2: 200mV/DIVAVERAGE: 50 SAMPLESVS = +5.5VVS = +2.7VHORIZONTAL: 50ns/DIVPULSED RF100MHz,–45dBm01085-C-019
Figure 18. Response Time, No Signal to –45 dBm CH.1&CH.2:500mV/DIVAVERAGE:50SAMPLESHORIZONTAL:50ns/DIVCH. 1 GNDCH. 2 GNDPULSED RF100MHz,0dBmCH.1CH.2VS = +5.5VVS = +2.7V01085-C-020
Figure 19. Response Time, No Signal to 0 dBm
________________________________________________________________________________________________________________________________
HP8648BSIGNALGENERATORHP8112APULSEGENERATOR0.1μF54.9Ω0.01μF0.01μF10Ω10Ω0.1μF+VS+VSTEKTDS784CSCOPE87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD8313TEK P6205FET PROBETRIG0603 SIZE SURFACEMOUNT COMPONENTS ONA LOW LEAKAGE PC BOARDEXT TRIGOUTPIN = 0dBmRF OUT10MHz REF OUTPUT01085-C-018
Figure 20. Test Setup for PWDN Response Time
0.1μF54.9Ω0.01μF0.01μF10Ω10Ω0.1μF+VS+VSTEKTDS784CSCOPE87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD8313TEK P6205FET PROBETRIG0603 SIZE SURFACEMOUNT COMPONENTS ONA LOW LEAKAGE PC BOARD01085-C-021TRIGOUTEXT TRIGRF OUT10MHz REF OUTPUT–6dBRFSPLITTER–6dBHP8648BSIGNALGENERATORPULSEMODULATIONMODEPULSE MODE INOUTHP8112APULSEGENERATOR
Figure 21. Test Setup for RSSI Mode Pulse Response
AD8313
Rev. D | Page 11 of 24
CIRCUIT DESCRIPTION
The AD8313 is an 8-stage logarithmic amplifier, specifically designed for use in RF measurement and power amplifier control applications at frequencies up to 2.5 GHz. A block diagram is shown in Figure 22. For a detailed description of log amp theory and design principles, refer to the AD8307 data sheet. +++++AD8313VOUTVSETCOMMPWDNGAINBIASBAND GAPREFERENCESLOPECONTROLINTERCEPTCONTROLEIGHT 8dB 3.5GHz AMPLIFIER STAGES8dB8dBVPOSINHIINLOVPOS8dB8dBNINE DETECTOR CELLSCINTLPI→VV→I1876523401085-C-001
Figure 22. Block Diagram
A fully differential design is used. Inputs INHI and INLO (Pins 2 and 3) are internally biased to approximately 0.75 V below the supply voltage, and present a low frequency impedance of nominally 900 Ω in parallel with 1.1 pF. The noise spectral density referred to the input is 0.6 nV/√Hz, equivalent to a voltage of 35 V rms in a 3.5 GHz bandwidth, or a noise power of −76 dBm re: 50 Ω. This sets the lower limit to the dynamic range; the Applications section shows how to increase the sensitivity by using a matching network or input transformer. However, the low end accuracy of the AD8313 is enhanced by specially shaping the demodulation transfer characteristic to partially compensate for errors due to internal noise.
Each of the eight cascaded stages has a nominal voltage gain of 8 dB and a bandwidth of 3.5 GHz. Each stage is supported by precision biasing cells that determine this gain and stabilize it against supply and temperature variations. Since these stages are direct-coupled and the dc gain is high, an offset compensation loop is included. The first four stages and the biasing system are powered from Pin 4, while the later stages and the output inter-faces are powered from Pin 1. The biasing is controlled by a logic interface PWDN (Pin 5); this is grounded for normal operation, but may be taken high (to VS) to disable the chip. The threshold is at VPOS/2 and the biasing functions are enabled and disabled within 1.8 μs.
Each amplifier stage has a detector cell associated with its output. These nonlinear cells perform an absolute value (full-wave rectification) function on the differential voltages along this backbone in a transconductance fashion; their outputs are in current-mode form and are thus easily summed. A ninth detector cell is added at the input of the AD8313. Since the midrange response of each of these nine detector stages is separated by 8 dB, the overall dynamic range is about 72 dB (Figure 23). The upper end of this range is determined by the capacity of the first detector cell, and occurs at approximately 0 dBm. The practical dynamic range is over 70 dB to the ±3 dB error points. However, some erosion of this range can occur at temperature and frequency extremes. Useful operation to over 3 GHz is possible, and the AD8313 remains serviceable at 10 MHz, needing only a small amount of additional ripple filtering. INPUT AMPLITUDE (dBm)2.0–80VOUT (
V)1.81.61.41.21.00.80.60.40.20–70–60–50–40–30–20–100543210–1–2–3–4–5ERROR (
dB)–90INTERCEPT =–100dBmSLOPE = 18mV/dB01085-c-023
Figure 23. Typical RSSI Response and Error vs. Input Power at 1.9 GHz
The fluctuating current output generated by the detector cells, with a fundamental component at twice the signal frequency, is filtered first by a low-pass section inside each cell, and then by the output stage. The output stage converts these currents to a voltage, VOUT, at VOUT (Pin 8), which can swing rail-to-rail. The filter exhibits a 2-pole response with a corner at approximately 12 MHz and full-scale rise time (10% to 90%) of 40 ns. The residual output ripple at an input frequency of 100 MHz has an amplitude of under 1 mV. The output can drive a small resistive load; it can source currents of up to 400 μA, and sink up to 10 mA. The output is stable with any capacitive load, though settling time could be impaired. The low frequency incremental output impedance is approximately 0.2 Ω.
In addition to its use as an RF power measurement device (that is, as a logarithmic amplifier), the AD8313 may also be used in controller applications by breaking the feedback path from VOUT to VSET (Pin 7), which determines the slope of the output (nominally 18 mV/dB). This pin becomes the setpoint input in controller modes. In this mode, the voltage VOUT remains close to ground (typically under 50 mV) until the decibel equivalent of the voltage VSET is reached at the input, when VOUT makes a rapid transition to a voltage close to VPOS (see the Operating in Controller Mode section). The logarithmic intercept is nominally positioned at −100 dBm (re: 50 Ω); this is effective in both the log amp mode and the controller mode.
AD8313
Rev. D | Page 12 of 24
With Pins 7 and 8 connected (log amp mode), the output can be stated as
)dBm100(+=INSLOPEOUTPVV
where PIN is the input power stated in dBm when the source is directly terminated in 50 Ω. However, the input impedance of the AD8313 is much higher than 50 Ω, and the sensitivity of this device may be increased by about 12 dB by using some type of matching network (see below), which adds a voltage gain and lowers the intercept by the same amount. Dependence on the ref-erence impedance can be avoided by restating the expression as
)V2.2/(log20μ×××=INSLOPEOUTVVV
where VIN is the rms value of a sinusoidal input appearing across Pins 2 and 3; here, 2.2 μV corresponds to the intercept, expressed in voltage terms. For detailed information on the effect of signal waveform and metrics on the intercept positioning for a log amp, refer to the AD8307 data sheet.
With Pins 7 and 8 disconnected (controller mode), the output can be stated as
SETINSLOPESOUTVPVVV>→)100/(logwhen
SETINSLOPEOUTVPVV<→)100/(logwhen0
when the input is stated in terms of the power of a sinusoidal signal across a net termination impedance of 50 Ω. The transition zone between high and low states is very narrow since the output stage behaves essentially as a fast integrator. The above equations can be restated as
SETINSLOPESOUTVVVVV>μ→)V2.2/(logwhen
SETINSLOPEOUTVVVV<μ→)V2.2/(logwhen0
Another use of the separate VOUT and VSET pins is in raising the load-driving current capability by including an external NPN emitter follower. More complete information about usage in these modes is provided in the Applications section.
AD8313
Rev. D | Page 13 of 24
INTERFACES
This section describes the signal and control interfaces and their behavior. On-chip resistances and capacitances exhibit variations of up to ±20%. These resistances are sometimes temperature-dependent, and the capacitances may be voltage-dependent.
POWER-DOWN INTERFACE, PWDN
The power-down threshold is accurately centered at the midpoint of the supply as shown in Figure 24. If Pin 5 is left unconnected or tied to the supply voltage (recommended), the bias enable current is shut off, and the current drawn from the supply is predominately through a nominal 300 kΩ chain (20 μA at 3 V). When grounded, the bias system is turned on. The threshold level is accurately at VPOS/2. When operating in the device ON state, the input bias current at the PWDN pin is approximately 5 μA for VPOS = 3 V. 5PWDNVPOS75kΩ6COMM150kΩ50kΩ150kΩTO BIASENABLE401085-C-024
Figure 24. Power-Down Threshold Circuitry
SIGNAL INPUTS, INHI, INLO
The simplest low frequency ac model for this interface consists of just a 900 Ω resistance, RIN, in shunt with a 1.1 pF input cap-acitance, CIN, connected across INHI and INLO. Figure 25 shows these distributed in the context of a more complete schematic. The input bias voltage shown is for the enabled chip; when disabled, it rises by a few hundred millivolts. If the input is coupled via capacitors, this change may cause a low level signal transient to be introduced, having a time constant formed by these capacitors and RIN. For this reason, large coupling capacitors should be well matched. This is not necessary when using the small capacitors found in many impedance transforming networks used at high frequencies.
1.25kΩCOMMVPOSINHIINLOVPOS0.5pF0.5pF0.7pF2.5kΩ2.5kΩ~0.75V(1ST DETECTOR)250Ω~1.4mA125Ω125Ω1.25kΩ1.24VGAIN BIASTO 2NDSTAGETO STAGES1 TO 4123401085-C-025
Figure 25. Input Interface Simplified Schematic
For high frequency use, Figure 26 shows the input impedance plotted on a Smith chart. This measured result of a typical device includes a 191 mil 50 Ω trace and a 680 pF capacitor to ground from the INLO pin. 1.1pF900Ω1.9GHzFrequency100MHz900MHz1.9GHz2.5GHzR650552223+jX–j400–j135–j65–j432.5GHz900MHz100MHzAD8313 MEASURED01085-C-026
Figure 26. Typical Input Impedance
LOGARITHMIC/ERROR OUTPUT, VOUT
The rail-to-rail output interface is shown in Figure 27. VOUT can run from within about 50 mV of ground, to within about 100 mV of the supply voltage, and is short-circuit safe to either supply. However, the sourcing load current, ISOURCE, is limited to that which is provided by the PNP transistor, typically 400 μA. Larger load currents can be provided by adding an external NPN transistor (see the Applications section). The dc open-loop gain of this amplifier is high, and it may be regarded as an integrator having a capacitance of 2 pF (CINT) driven by the current-mode signal generated by the summed outputs of the nine detector stages, which is scaled approximately 4.0 μA/dB. COMMgmSTAGECINTLPLM10mAMAXVOUTCLBIASISOURCE400μAVPOSFROMSETPOINTSUMMEDDETECTOROUTPUTS68101085-C-027
Figure 27. Output Interface Circuitry
Thus, for midscale RF input of about 3 mV, which is some 40 dB above the minimum detector output, this current is 160 μA, and the output changes by 8 V/μs. When VOUT is connected to VSET, the rise and fall times are approximately 40 ns (for RL ≥ 10 kΩ ).
The nominal slew rate is 2.5 V/μs. The HF compensation tech-nique results in stable operation with a large capacitive load, CL, though the positive-going slew rate is then limited by ISOURCE/CL to 1 V/μs for CL = 400 pF.
AD8313
Rev. D | Page 14 of 24
SETPOINT INTERFACE, VSET
The setpoint interface is shown in Figure 28. The voltage, VSET, is divided by a factor of 3 in a resistive attenuator of 18 kΩ total resistance. The signal is converted to a current by the action of the op amp and the resistor R3 (1.5 kΩ), which balances the current generated by the summed output of the nine detector cells at the input to the previous cell. The logarithmic slope is nominally 3 μs × 4.0 μA/dB × 1.5 kΩ = 18 mV/dB.
8VSETVPOSR112kΩR26kΩ6COMM25μA25μAFDBKTO O/PSTAGE1R31.5kΩLP01085-C-028
Figure 28. Setpoint Interface Circuitry
AD8313
Rev. D | Page 15 of 24
APPLICATIONS
BASIC CONNECTIONS FOR LOG (RSSI) MODE
Figure 29 shows the AD8313 connected in its basic measurement mode. A power supply between 2.7 V and 5.5 V is required. The power supply to each of the VPOS pins should be decoupled with a 0.1 μF surface-mount ceramic capacitor and a 10 Ω series resistor.
The PWDN pin is shown as grounded. The AD8313 may be disabled by a logic high at this pin. When disabled, the chip current is reduced to about 20 μA from its normal value of 13.7 mA. The logic threshold is at VPOS/2, and the enable function occurs in about 1.8 μs. However, that additional settling time is generally needed at low input levels. While the input in this case is terminated with a simple 50 Ω broadband resistive match, there are many ways in which the input termi-nation can be accomplished. These are discussed in the Input Coupling section.
VSET is connected to VOUT to establish a feedback path that controls the overall scaling of the logarithmic amplifier. The load resistance, RL, should not be lower than 5 kΩ so that the full-scale output of 1.75 V can be generated with the limited available current of 400 μA max.
As stated in the Absolute Maximum Ratings table, an externally applied overvoltage on the VOUT pin, which is outside the range 0 V to VPOS, is sufficient to cause permanent damage to the device. If overvoltages are expected on the VOUT pin, a series resistor, RPROT, should be included as shown. A 500 Ω resistor is sufficient to protect against overvoltage up to ±5 V; 1000 Ω should be used if an overvoltage of up to ±15 V is expected. Since the output stage is meant to drive loads of no more than 400 μA, this resistor does not impact device perform-ance for higher impedance drive applications (higher output current applications are discussed in the Increasing Output Current section). 0.1μF53.6Ω680pF680pFR110ΩR210Ω0.1μF+VS+VS87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD8313RPROTRL= 1MΩ01085-C-029
Figure 29. Basic Connections for Log (RSSI) Mode
OPERATING IN CONTROLLER MODE
Figure 30 shows the basic connections for operation in controller mode. The link between VOUT and VSET is broken and a set-point is applied to VSET. Any difference between VSET and the equivalent input power to the AD8313 drives VOUT either to the supply rail or close to ground. If VSET is greater than the equivalent input power, VOUT is driven toward ground, and vice versa. 0.1μFR110ΩR310Ω0.1μF+VS+VS87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD8313RPROT01085-C-030
Figure 30. Basic Connections for Operation in the Controller Mode
This mode of operation is useful in applications where the output power of an RF power amplifier (PA) is to be controlled by an analog AGC loop (Figure 31). In this mode, a setpoint voltage, proportional in dB to the desired output power, is applied to the VSET pin. A sample of the output power from the PA, via a directional coupler or other means, is fed to the input of the AD8313. SETPOINTCONTROL DACRFINVOUTVSETAD8313DIRECTIONALCOUPLERPOWERAMPLIFIERRF INENVELOPE OFTRANSMITTEDSIGNAL01085-C-031
Figure 31. Setpoint Controller Operation
VOUT is applied to the gain control terminal of the power amplifier. The gain control transfer function of the power amplifier should be an inverse relationship, that is, increasing voltage decreases gain.
A positive input step on VSET (indicating a demand for increased power from the PA) drives VOUT toward ground. This should be arranged to increase the gain of the PA. The loop settles when VOUT settles to a voltage that sets the input power to the AD8313 to the dB equivalent of VSET.
AD8313
Rev. D | Page 16 of 24
INPUT COUPLING
The signal can be coupled to the AD8313 in a variety of ways. In all cases, there must not be a dc path from the input pins to ground. Some of the possibilities include dual-input coupling capacitors, a flux-linked transformer, a printed circuit balun, direct drive from a directional coupler, or a narrow-band impedance matching network.
Figure 32 shows a simple broadband resistive match. A termination resistor of 53.6 Ω combines with the internal input impedance of the AD8313 to give an overall resistive input impedance of approximately 50 Ω. It is preferable to place the termination resistor directly across the input pins, INHI to INLO, where it lowers the possible deleterious effects of dc offset voltages on the low end of the dynamic range. At low frequencies, this may not be quite as beneficial, since it requires larger coupling capacitors. The two 680 pF input coupling capacitors set the high-pass corner frequency of the network at 9.4 MHz. RMATCH53.6ΩC2680pFC1680pFCINRINAD831350Ω50ΩSOURCE01085-C-032
Figure 32. A Simple Broadband Resistive Input Termination
The high-pass corner frequency can be set higher according to the equation 50213××π×=CfdB
where: C2C1C2C1C××=
In high frequency applications, the use of a transformer, balun, or matching network is advantageous. The impedance matching characteristics of these networks provide what is essentially a gain stage before the AD8313 that increases the device sensitivity. This gain effect is explored in the following matching example.
Figure 33 and Figure 34 show device performance under these three input conditions at 900 MHz and 1.9 GHz.
While the 900 MHz case clearly shows the effect of input matching by realigning the intercept as expected, little improvement is seen at 1.9 GHz. Clearly, if no improvement in sensitivity is required, a simple 50 Ω termination may be the best choice for a given design based on ease of use and cost of components. INPUT AMPLITUDE (dBm)–80–70–60–50–40–30–20–103210–1–2–3ERROR (
dB)TERMINATEDDR = 66dB–90100BALANCEDMATCHEDBALANCEDDR = 71dBMATCHEDDR = 69dB01085-C-033
Figure 33. Comparison of Terminated, Matched, and Balanced Input Drive at 900 MHz
INPUT AMPLITUDE (dBm)–80–70–60–50–40–30–20–1003210–1–2–3ERROR (
dB)–9010TERMINATEDDR = 75dBBALANCEDBALANCEDDR = 75dBMATCHEDDR = 73dBMATCHEDTERMINATED01085-C-034
Figure 34. Comparison of Terminated, Matched, and Balanced Input Drive at 1.9 GHz
NARROW-BAND LC MATCHING EXAMPLE AT 100 MHz
While numerous software programs provide an easy way to calculate the values of matching components, a clear under-standing of the calculations involved is valuable. A low frequency (100 MHz) value has been used for this example because of the deleterious board effects at higher frequencies. RF layout simulation software is useful when board design at higher frequencies is required.
A narrow-band LC match can be implemented either as a series-inductance/shunt-capacitance or as a series-capacitance/ shunt-inductance. However, the concurrent requirement that the AD8313 inputs, INHI and INLO, be ac-coupled, makes a series-capacitance/shunt-inductance type match more appropriate (Figure 35).
AD8313
Rev. D | Page 17 of 24
LMATCHC2C1CINRINAD831350Ω50ΩSOURCE01085-C-035
Figure 35. Narrow-Band Reactive Match
Typically, the AD8313 needs to be matched to 50 Ω. The input impedance of the AD8313 at 100 MHz can be read from the Smith chart (Figure 26) and corresponds to a resistive input impedance of 900 Ω in parallel with a capacitance of 1.1 pF.
To make the matching process simpler, the AD8313 input cap-acitance, CIN, can be temporarily removed from the calculation by adding a virtual shunt inductor (L2), which resonates away CIN (Figure 36). This inductor is factored back into the calculation later. This allows the main calculation to be based on a simple resistive-to-resistive match, that is, 50 Ω to 900 Ω.
The resonant frequency is defined by the equation INCL2×=ω1
therefore, H3.212μ=ω=INCL2 L1C2C1CINCMATCH=(C1× C2)(C1 + C2)RINAD831350Ω50ΩSOURCE01085-C-036L2TEMPORARYINDUCTANCELMATCH=(C1× C2)(C1 + C2)
Figure 36. Input Matching Example
With CIN and L2 temporarily out of the picture, the focus is now on matching a 50 Ω source resistance to a (purely resistive) load of 900 Ω and calculating values for CMATCH and L1. When MATCHINSCL1RR=
the input looks purely resistive at a frequency given by MHz10021=×π=MATCH0CL1f
Solving for CMATCH gives pF5.72110=π×=fRRCINSMATCH
Solving for L1 gives nH6.33720=π=fRRL1INS
Because L1 and L2 are parallel, they can be combined to give the final value for LMATCH, that is, nH294=+×=L2L1L2L1LMATCH
C1 and C2 can be chosen in a number of ways. First, C2 can be set to a large value, for example, 1000 pF, so that it appears as an RF short. C1 would then be set equal to the calculated value of CMATCH. Alternatively, C1 and C2 can each be set to twice CMATCH so that the total series capacitance is equal to CMATCH. By making C1 and C2 slightly unequal (that is, select C2 to be about 10% less than C1) but keeping their series value the same, the ampli-tude of the signals on INHI and INLO can be equalized so that the AD8313 is driven in a more balanced manner. Any of the options detailed above can be used provided that the combined series value of C1 and C2, that is, C1 × C2/(C1 + C2) is equal to CMATCH.
In all cases, the values of CMATCH and LMATCH must be chosen from standard values. At this point, these values need now be installed on the board and measured for performance at 100 MHz. Because of board and layout parasitics, the component values from the preceding example had to be tuned to the final values of CMATCH = 8.9 pF and LMATCH = 270 nH as shown in Table 4.
Assuming a lossless matching network and noting conservation of power, the impedance transformation from RS to RIN (50 Ω to 900 Ω) has an associated voltage gain given by dB6.12log20dB=×=SINRRGain
Because the AD8313 input responds to voltage and not to true power, the voltage gain of the matching network increases the effective input low-end power sensitivity by this amount. Thus, in this case, the dynamic range is shifted downward, that is, the 12.6 dB voltage gain shifts the 0 dBm to −65 dBm input range downward to −12.6 dBm to −77.6 dBm. However, because of network losses, this gain is not be fully realized in practice. Refer to Figure 33 and Figure 34 for an example of practical attainable voltage gains.
Table 4 shows recommended values for the inductor and cap-acitors in Figure 35 for some selected RF frequencies in addition to the associated theoretical voltage gain. These values for a reactive match are optimal for the board layout detailed as Figure 45.
AD8313
Rev. D | Page 18 of 24
As previously discussed, a modification of the board layout produces networks that may not perform as specified. At 2.5 GHz, a shunt inductor is sufficient to achieve proper matching. Con-sequently, C1 and C2 are set sufficiently high that they appear as RF shorts.
Table 4. Recommended Values for C1, C2, and LMATCH in Figure 35
Freq. (MHz)
CMATCH (pF)
C1 (pF)
C2 (pF)
LMATCH (nH)
Voltage Gain(dB)
100
8.9
22
15
270
12.6
1000
270
900
1.5
3
3
8.2
9.0
1.5
1000
8.2
1900
1.5
3
3
2.2
6.2
1.5
1000
2.2
2500
Large
390
390
2.2
3.2
Figure 37 shows the voltage response of the 100 MHz matching network. Note the high attenuation at lower frequencies typical of a high-pass network. FREQUENCY (MHz)1550VOLTAGE GAIN (
dB)1050–510020001085-C-037
Figure 37. Voltage Response of 100 MHz Narrow-Band Matching Network
ADJUSTING THE LOG SLOPE
Figure 38 shows how the log slope can be adjusted to an exact value. The idea is simple: the output at the VOUT pin is attenu-ated by the variable resistor R2 working against the internal 18 kΩ of input resistance at the VSET pin. When R2 is 0, the attenu-ation it introduces is 0, and thus the slope is the basic 18 mV/dB. Note that this value varies with frequency, (Figure 10). When R2 is set to its maximum value of 10 kΩ, the attenuation from VOUT to VSET is the ratio 18/(18 + 10), and the slope is raised to (28/18) × 18 mV, or 28 mV/dB. At about the midpoint, the nominal scale is 23 mV/dB. Thus, a 70 dB input range changes the output by 70 × 23 mV, or 1.6 V. 0.1μFR110ΩR310ΩR210kΩ0.1μF+VS+VS87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD831301085-C-03818–30mV/dB
Figure 38. Adjusting the Log Slope
As stated, the unadjusted log slope varies with frequency from 17 mV/dB to 20 mV/dB, as shown in Figure 10. By placing a resistor between VOUT and VSET, the slope can be adjusted to a convenient 20 mV/dB as shown in Figure 39.
Table 5 shows the recommended values for this resistor, REXT. Also shown are values for REXT, which increase the slope to approximately 50 mV/dB. The corresponding voltage swings for a −65 dBm to 0 dBm input range are also shown in Table 6. 0.1μFR110ΩR310ΩREXT0.1μF+VS+VS87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD831301085-C-03920mV/dB
Figure 39. Adjusting the Log Slope to a Fixed Value
Table 5. Values for R in Figure 39EXT
Frequency MHz
REXT kV
Slope mV/dB
VOUT Swing for Pin −65 dBm to 0 dBm – V
100
0.953
20
0.44 to 1.74
900
2.00
20
0.58 to 1.88
1900
2.55
20
0.70 to 2.00
2500
0
20
0.54 to 1.84
100
29.4
50
1.10 to 4.35
900
32.4
50.4
1.46 to 4.74
1900
33.2
49.8
1.74 to 4.98
2500
26.7
49.7
1.34 to 4.57
The value for REXT is calculated by
()Ω×−=k18SlopeOriginalSlopeOriginalSlopeNewREXT
The value for the Original Slope, at a particular frequency, can be read from Figure 10. The resulting output swing is calculated by simply inserting the New Slope value and the intercept at that frequency (Figure 10 and Figure 13) into the general equation for the AD8313’s output voltage:
VOUT = Slope(PIN − Intercept)
AD8313
Rev. D | Page 19 of 24
INCREASING OUTPUT CURRENT
To drive a more substantial load, either a pull-up resistor or an emitter-follower can be used.
In Figure 40, a 1 kΩ pull-up resistor is added at the output, which provides the load current necessary to drive a 1 kΩ load to 1.7 V for VS = 2.7 V. The pull-up resistor slightly lowers the intercept and the slope. As a result, the transfer function of the AD8313 is shifted upward (intercept shifts downward). 0.1μFR110ΩR310Ω0.1μF+VS+VS87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD831301085-C-0401kΩRL= 1kΩ+VS20mV/dB
Figure 40. Increasing AD8313 Output Current Capability
In Figure 41, an emitter-follower provides the current gain, when a 100 Ω load can readily be driven to full-scale output. While a high ß transistor such as the BC848BLT1 (min ß = 200) is recommended, a 2 kΩ pull-up resistor between VOUT and +VS can provide additional base current to the transistor.
βMIN = 2000.1μFR110ΩR310Ω0.1μF+VS+VS+VS87651234VPOSVOUTINHIINLOVPOSPWDNCOMMVSETAD831301085-C-041RL100ΩOUTPUT13kΩ10kΩBC848BLT1
Figure 41. Output Current Drive Boost Connection
In addition to providing current gain, the resistor/potentiometer combination between VSET and the emitter of the transistor increases the log slope to as much as 45 mV/dB, at maximum resistance. This gives an output voltage of 4 V for a 0 dBm input. If no increase in the log slope is required, VSET can be connected directly to the emitter of the transistor.
EFFECT OF WAVEFORM TYPE ON INTERCEPT
Although specified for input levels in dBm (dB relative to 1 mW), the AD8313 responds to voltage and not to power. A direct consequence of this characteristic is that input signals of equal rms power but differing crest factors produce different results at the log amp’s output.
Different signal waveforms vary the effective value of the log amp’s intercept upward or downward. Graphically, this looks like a vertical shift in the log amp’s transfer function. The device’s logarithmic slope, however, is in principle not affected. For example, if the AD8313 is being fed alternately from a continuous wave and from a single CDMA channel of the same rms power, the AD8313 output voltage differs by the equivalent of 3.55 dB (64 mV) over the complete dynamic range of the device (the output for a CDMA input being lower).
Table 6 shows the correction factors that should be applied to measure the rms signal strength of a various signal types. A continuous wave input is used as a reference. To measure the rms power of a square wave, for example, the mV equivalent of the dB value given in the table (18 mV/dB × 3.01 dB) should be subtracted from the output voltage of the AD8313.
Table 6. Shift in AD8313 Output for Signals with Differing Crest Factors
Signal Type
Correction Factor (Add to Output Reading)
CW Sine Wave
0 dB
Square Wave or DC
−3.01 dB
Triangular Wave
+0.9 dB
GSM Channel (All Time Slots On)
+0.55 dB
CDMA Channel
+3.55 dB
PDC Channel (All Time Slots On)
+0.58 dB
Gaussian Noise
+2.51 dB
AD8313
Rev. D | Page 20 of 24
EVALUATION BOARD
SCHEMATIC AND LAYOUT
Figure 44 shows the schematic of the AD8313 evaluation board. Note that uninstalled components are indicated as open. This board contains the AD8313 as well as the AD8009 current-feedback operational amplifier.
This is a 4-layer board (top and bottom signal layers, ground, and power). The top layer silkscreen and layout are shown in Figure 42 and Figure 43. A detailed drawing of the recommended PCB footprint for the MSOP package and the pads for the matching components are shown in Figure 45.
The vacant portions of the signal and power layers are filled out with ground plane for general noise suppression. To ensure a low impedance connection between the planes, there are multiple through-hole connections to the RF ground plane. While the ground planes on the power and signal planes are used as general-purpose ground returns, any RF grounds related to the input matching network (for example, C2) are returned directly to the RF internal ground plane.
GENERAL OPERATION
The AD8313 should be powered by a single supply in the range of 2.7 V to 5.5 V. The power supply to each AD8313 VPOS pin is decoupled by a 10 Ω resistor and a 0.1 μF capacitor. The AD8009 can run on either single or dual supplies, +5 V to ±6 V. Both the positive and negative supply traces are decoupled using a 0.1 μF capacitor. Pads are provided for a series resistor or inductor to provide additional supply filtering.
The two signal inputs are ac-coupled using 680 pF high quality RF capacitors (C1, C2). A 53.6 Ω resistor across the differential signal inputs (INHI, INLO) combines with the internal 900 Ω input impedance to give a broadband input impedance of 50.6 Ω. This termination is not optimal from a noise perspective due to the Johnson noise of the 53.6 Ω resistor. Neither does it account for the AD8313’s reactive input impedance nor for the decrease over frequency of the resistive component of the input imped-ance. However, it does allow evaluation of the AD8313 over its complete frequency range without having to design multiple matching networks.
For optimum performance, a narrow-band match can be implemented by replacing the 53.6 Ω resistor (labeled L/R) with an RF inductor and replacing the 680 pF capacitors with appropriate values. The Narrow-Band LC Matching Example at 100 MHz section includes a table of recommended values for selected frequencies and explains the method of calculation.
Switch 1 is used to select between power-up and power-down modes. Connecting the PWDN pin to ground enables normal operation of the AD8313. In the opposite position, the PWDN pin can be driven externally (SMA connector labeled ENBL) to either device state, or it can be allowed to float to a disabled device state.
The evaluation board comes with the AD8313 configured to operate in RSSI/measurement mode. This mode is set by the 0 Ω resistor (R11), which shorts the VOUT and VSET pins to each other. When using the AD8009, the AD8313 logarithmic output appears on the SMA connector labeled VOUT. Using only the AD8313, the log output can be measured at TP1 or the SMA connector labeled VSET.
USING THE AD8009 OPERATIONAL AMPLIFIER
The AD8313 can supply only 400 μA at VOUT. It is also sensitive to capacitive loading, which can cause inaccurate measurements, especially in applications where the AD8313 is used to measure the envelope of RF bursts.
The AD8009 alleviates both of these issues. It is an ultrahigh speed current feedback amplifier capable of delivering over 175 mA of load current, with a slew rate of 5,500 V/μs, which results in a rise time of 545 ps, making it ideal as a pulse amplifier.
The AD8009 is configured as a buffer amplifier with a gain of 1. Other gain options can be implemented by installing the appro-priate resistors at R10 and R12.
Various output filtering and loading options are available using R5, R6, and C6. Note that some capacitive loads may cause the AD8009 to become unstable. It is recommended that a 42.2 Ω resistor be installed at R5 when driving a capacitive load. More details can be found in the AD8009 data sheet.
VARYING THE LOGARITHMIC SLOPE
The slope of the AD8313 can be increased from its nominal value of 18 mV/dB to a maximum of 40 mV/dB by removing R11, the 0 Ω resistor, which shorts VSET to VOUT. VSET and VOUT are now connected through the 20 kΩ potentiometer. The AD8009 must be configured for a gain of 1 to accurately vary the slope of the AD8313.
OPERATING IN CONTROLLER MODE
To put the AD8313 into controller mode, R7 and R11 should be removed, breaking the link between VOUT and VSET. The VSET pin can then be driven externally via the SMA connector labeled VSET.
RF BURST RESPONSE
The VOUT pin of the AD8313 is very sensitive to capacitive loading, as a result care must be taken when measuring the device’s response to RF bursts. For best possible response time measurements it is recommended that the AD8009 be used to buffer the output from the AD8313. No connection should be made to TP1, the added load will effect the response time.
AD8313
Rev. D | Page 21 of 24
001085-C-048
Figure 42. Layout of Signal Layer 01085-C-049
Figure 43. Signal Layer Silkscreen
AD8313
Rev. D | Page 22 of 24
VPS1VPS101085-C-046R210ΩEXT ENABLESW1R110Ω1234INHIINLOVPOSPWDNCOMMVSETAD83138765INHIVOUTEXT VSETAD8009VPOSVOUTC70.1μFC1680pFC2680pFC30.1μFC50.1μFR40ΩR12301ΩR50ΩR70ΩR30ΩR110ΩR90ΩR210ΩL/R53.6ΩVNEGVPS2INLOTP1Z1Z2R10OPENR6OPENR820kΩC6OPENABC40.1μF
Figure 44. Evaluation Board Schematic
Table 7. Evaluation Board Configuration Options
Component
Function
Default
VPS1, VPS2, GND, VNEG
Supply Pins. VPS1 is the positive supply pin for the AD8313. VPS2 and VNEG are the positive and negative supply pins for the AD8009. If the AD8009 is being operated from a single supply, VNEG should be connected to GND. VPS1 and VPS2 are independent. GND is shared by both devices.
Not Applicable
Z1
AD8313 Logarithmic Amplifier. If the AD8313 is used in measurement mode, it is not necessary to power up the AD8009 op amp. The log output can be measured at TP1 or at the SMA connector labeled VSET.
Installed
Z1
AD8009 Operational Amplifier.
Installed
SW1
Device Enable. When in Position A, the PWDN pin is connected to ground and the AD8313 is in normal operating mode. In Position B, the PWDN pin is connected to an SMA connector labeled ENBL. A signal can be applied to this connector.
SW1 = A
R7, R8
Slope Adjust. The slope of the AD8313 can be increased from its nominal value of 18 mV/dB to a maximum of 40 mV/dB by removing R11, the 0 Ω resistor, which shorts VSET to VOUT, and installing a 0 Ω resistor at R7. The 20 kΩ potentiometer at R8 can then be used to change the slope.
R7 = 0 Ω (Size 0603)
R8 = installed
Operating in Controller Mode. To put the AD8313 into controller mode, R7 and R11 should be removed, breaking the link between VOUT and VSET. The VSET pin can then be driven externally via the SMA connector labeled VSET.
L/R, C1, C2, R9
Input Interface. The 52.3 Ω resistor in position L/R, along with C1 and C2, create a wideband 50 Ω input. Alternatively, the 52.3 Ω resistor can be replaced by an inductor to form an input matching network. See Input Coupling section for more details. Remove the 0 Ω resistor at R9 for differential drive applications.
L/R = 53.6 Ω (Size 0603)
C1 = C2 = 680 pF (Size 0603)
R9 = 0 Ω (Size 0603)
R10, R12
Op Amp Gain Adjust. The AD8009 is initially configured as a buffer; gain = 1. To increase the gain of the op amp, modify the resistor values R10 and R12.
R10 = open (Size 0603)
R12 = 301 Ω (Size 0603)
R5, R6, C6
Op Amp Output Loading/Filtering. A variety of loading and filtering options are available for the AD8009. The robust output of the op amp is capable of driving low impedances such as 50 Ω or 75 Ω, configure R5 and R6 accordingly. See the AD8009 data sheet for more details.
R5 = 0 Ω (Size 0603)
R6 = open (Size 0603)
C6 = open (Size 0603)
R1, R2, R3, R4, C3, C4, C5, C7
Supply Decoupling.
R1 = R2 = 10 Ω (Size 0603)
R3 = R4 = 0 Ω (Size 0603)
C3 = C4 = 0.1 μF (Size 0603)
C5 = C7 = 0.1 μF (Size 0603)
AD8313
Rev. D | Page 23 of 24
4854.490.6282027.57550201950354122464851.791.3511016126TRACE WIDTH15.4NOT CRITICAL DIMENSIONSUNIT = MILS01085-C-047
Figure 45. Detail of PCB Footprint for Package and Pads for Matching Network
AD8313
Rev. D | Page 24 of 24
OUTLINE DIMENSIONS 0.800.600.408°0°4854.90BSCPIN 10.65 BSC3.00BSCSEATINGPLANE0.150.000.380.221.10 MAX3.00BSCCOPLANARITY0.100.230.08COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 46 . 8-Lead MicroSOIC Package [MSOP] (RM-08) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
Temperature Range
Package Descriptions
Package Option
Branding
AD8313ARM
−40°C to +85°C
8-Lead MSOP
RM-08
J1A
AD8313ARM-REEL
−40°C to +85°C
13" Tape and Reel
RM-08
J1A
AD8313ARM-REEL7
−40°C to +85°C
7" Tape and Reel
RM-08
J1A
AD8313ARMZ1
−40°C to +85°C
8-Lead MSOP
AD8313ARMZ-REEL71
−40°C to +85°C
7" Tape and Reel
AD8313-EVAL
Evaluation Board
1 Z = Pb-free part.
TUSB3410, TUSB3410I
USB to Serial Port Controller
January 2010 Connectivity Interface Solutions
Data Manual
SLLS519H
Contents
May 2008 SLLS519G iii
Contents
Section Page
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Controller Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 USB Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Enhanced UART Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Terminal Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Detailed Controller Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 USB Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.1 External Memory Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.2 Host Download Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 USB Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Serial Port Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Serial Port Data Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5.1 RS-232 Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5.2 RS-485 Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5.3 IrDA Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 MCU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1.1 ROMS: ROM Shadow Configuration Register (Addr:FF90h) . . . . . . . . . . . . . . . . . . . 14
4.1.2 Boot Operation (MCU Firmware Loading) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1.3 WDCSR: Watchdog Timer, Control, and Status Register (Addr:FF93h) . . . . . . . . . 15
4.2 Buffers + I/O RAM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Endpoint Descriptor Block (EDB−1 to EDB−3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.1 OEPCNF_n: Output Endpoint Configuration (n = 1 to 3)
(Base Addr: FF08h, FF10h, FF18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3.2 OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1) . . . . 19
4.3.3 OEPBCTX_n: Output Endpoint X Byte Count (n = 1 to 3) (Offset 2) . . . . . . . . . . . . 20
4.3.4 OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5) . . . . 20
4.3.5 OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3) (Offset 6) . . . . . . . . . . . . 20
4.3.6 OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7) . . . . . . . . . 21
4.3.7 IEPCNF_n: Input Endpoint Configuration (n = 1 to 3)
(Base Addr: FF48h, FF50h, FF58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.8 IEPBBAX_n: Input Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1) . . . . . . 21
4.3.9 IEPBCTX_n: Input Endpoint X-Byte Count (n = 1 to 3) (Offset 2) . . . . . . . . . . . . . . 22
4.3.10 IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5) . . . . . . 22
4.3.11 IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3) (Offset 6) . . . . . . . . . . . . . . . 22
4.3.12 IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7) . . . . . . . . . . . . 23
4.4 Endpoint-0 Descriptor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4.1 IEPCNFG_0: Input Endpoint-0 Configuration Register (Addr:FF80h) . . . . . . . . . . . 23
4.4.2 IEPBCNT_0: Input Endpoint-0 Byte Count Register (Addr:FF81h) . . . . . . . . . . . . . 24
4.4.3 OEPCNFG_0: Output Endpoint-0 Configuration Register (Addr:FF82h) . . . . . . . . . 24
4.4.4 OEPBCNT_0: Output Endpoint-0 Byte Count Register (Addr:FF83h) . . . . . . . . . . . 24
Contents
iv SLLS519G May 2008
Section Page
5 USB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 FUNADR: Function Address Register (Addr:FFFFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 USBSTA: USB Status Register (Addr:FFFEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 USBMSK: USB Interrupt Mask Register (Addr:FFFDh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4 USBCTL: USB Control Register (Addr:FFFCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.5 MODECNFG: Mode Configuration Register (Addr:FFFBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.6 Vendor ID/Product ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.7 SERNUM7: Device Serial Number Register (Byte 7) (Addr:FFEFh) . . . . . . . . . . . . . . . . . . . . . . 28
5.8 SERNUM6: Device Serial Number Register (Byte 6) (Addr:FFEEh) . . . . . . . . . . . . . . . . . . . . . . 29
5.9 SERNUM5: Device Serial Number Register (Byte 5) (Addr:FFEDh) . . . . . . . . . . . . . . . . . . . . . . 29
5.10 SERNUM4: Device Serial Number Register (Byte 4) (Addr:FFECh) . . . . . . . . . . . . . . . . . . . . . . 29
5.11 SERNUM3: Device Serial Number Register (Byte 3) (Addr:FFEBh) . . . . . . . . . . . . . . . . . . . . . . 29
5.12 SERNUM2: Device Serial Number Register (Byte 2) (Addr:FFEAh) . . . . . . . . . . . . . . . . . . . . . . 30
5.13 SERNUM1: Device Serial Number Register (Byte 1) (Addr:FFE9h) . . . . . . . . . . . . . . . . . . . . . . 30
5.14 SERNUM0: Device Serial Number Register (Byte 0) (Addr:FFE8h) . . . . . . . . . . . . . . . . . . . . . . 30
5.15 Function Reset And Power-Up Reset Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.16 Pullup Resistor Connect/Disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1 DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.1 DMACDR1: DMA Channel Definition Register (UART Transmit Channel)
(Addr:FFE0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1.2 DMACSR1: DMA Control And Status Register (UART Transmit Channel)
(Addr:FFE1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1.3 DMACDR3: DMA Channel Definition Register (UART Receive Channel)
(Addr:FFE4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.4 DMACSR3: DMA Control And Status Register (UART Receive Channel)
(Addr:FFE5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2 Bulk Data I/O Using the EDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2.1 IN Transaction (TUSB3410 to Host) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.2 OUT Transaction (Host to TUSB3410) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .